From scott at notabs.org  Sun May  1 05:37:09 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sat, 30 Apr 2011 22:37:09 -0500
Subject: [coreboot] use gcc 4.6.0 link time optimization to reduce
	coreboot execution time
In-Reply-To: <20110430155620.GA14417@morn.localdomain>
References: <4E2C6DA2F6424C5BBA589A3E5D85B414@m3a78>
	<20110430155620.GA14417@morn.localdomain>
Message-ID: <C2294C9FBDD44B398C89282144A66EC4@m3a78>

Kevin O'Connor wrote:

] That's a great boot time!  Do you have a breakdown of where the 640ms
] is spent?
]
] -Kevin

Hello Kevin,

I tried adding some serial logging to get an idea about where
the time is spent. The logging adds 8 ms to the boot time:

Time in ms
0      cold reset
366    memory initialization complete
469    seabios: maininit(void)
483    seabios: vga_setup() called
604    seabios: vga_setup() returned
621    seabios: startBoot(void)
648    dos autoexec utility logs pmtimer value

It looks like the lengthy operations are memory init and VBIOS
execution, which is consistent with past experience.

UEFI BIOS on this same hardware platform is taking more than 
10 seconds.

Here seabios kconfig options I changed:

Build for coreboot                           y
Hardware init during option ROM execution    y
Bootmenu                                     n
ATA controllers                              n
AHCI controllers                             y
Floppy controller                            n
PS/2 port                                    n
USB UHCI controllers                         n
Parallel port                                n
PCIBIOS interface                            n
APM interface                                n
PnP BIOS interface                           n
S3 resume                                    n
SMBIOS                                       n
Serial port debugging                        y
Show screen writes on debug ports            n

Thanks,
Scott




From anton.kochkov at gmail.com  Sun May  1 05:45:18 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Sun, 1 May 2011 07:45:18 +0400
Subject: [coreboot] Fwd: use gcc 4.6.0 link time optimization to reduce
 coreboot execution time
In-Reply-To: <BANLkTinbS0wAwtYhxmK1t5Qn-orUyvtV7Q@mail.gmail.com>
References: <4E2C6DA2F6424C5BBA589A3E5D85B414@m3a78>
	<20110430155620.GA14417@morn.localdomain>
	<C2294C9FBDD44B398C89282144A66EC4@m3a78>
	<BANLkTinbS0wAwtYhxmK1t5Qn-orUyvtV7Q@mail.gmail.com>
Message-ID: <BANLkTi=-Q4xCy7z2skCSx_vJutL=aT-aNg@mail.gmail.com>

May be add something like profiling option with patch for implementing
such feature?
Best regards,
Anton Kochkov.




On Sun, May 1, 2011 at 07:37, Scott Duplichan <scott at notabs.org> wrote:
> Kevin O'Connor wrote:
>
> ] That's a great boot time! ?Do you have a breakdown of where the 640ms
> ] is spent?
> ]
> ] -Kevin
>
> Hello Kevin,
>
> I tried adding some serial logging to get an idea about where
> the time is spent. The logging adds 8 ms to the boot time:
>
> Time in ms
> 0 ? ? ?cold reset
> 366 ? ?memory initialization complete
> 469 ? ?seabios: maininit(void)
> 483 ? ?seabios: vga_setup() called
> 604 ? ?seabios: vga_setup() returned
> 621 ? ?seabios: startBoot(void)
> 648 ? ?dos autoexec utility logs pmtimer value
>
> It looks like the lengthy operations are memory init and VBIOS
> execution, which is consistent with past experience.
>
> UEFI BIOS on this same hardware platform is taking more than
> 10 seconds.
>
> Here seabios kconfig options I changed:
>
> Build for coreboot ? ? ? ? ? ? ? ? ? ? ? ? ? y
> Hardware init during option ROM execution ? ?y
> Bootmenu ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? n
> ATA controllers ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?n
> AHCI controllers ? ? ? ? ? ? ? ? ? ? ? ? ? ? y
> Floppy controller ? ? ? ? ? ? ? ? ? ? ? ? ? ?n
> PS/2 port ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?n
> USB UHCI controllers ? ? ? ? ? ? ? ? ? ? ? ? n
> Parallel port ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?n
> PCIBIOS interface ? ? ? ? ? ? ? ? ? ? ? ? ? ?n
> APM interface ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?n
> PnP BIOS interface ? ? ? ? ? ? ? ? ? ? ? ? ? n
> S3 resume ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?n
> SMBIOS ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? n
> Serial port debugging ? ? ? ? ? ? ? ? ? ? ? ?y
> Show screen writes on debug ports ? ? ? ? ? ?n
>
> Thanks,
> Scott
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

From peter at stuge.se  Sun May  1 06:01:01 2011
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 May 2011 06:01:01 +0200
Subject: [coreboot] Fwd: use gcc 4.6.0 link time optimization to
	reduce	coreboot execution time
In-Reply-To: <BANLkTi=-Q4xCy7z2skCSx_vJutL=aT-aNg@mail.gmail.com>
References: <4E2C6DA2F6424C5BBA589A3E5D85B414@m3a78>
	<20110430155620.GA14417@morn.localdomain>
	<C2294C9FBDD44B398C89282144A66EC4@m3a78>
	<BANLkTinbS0wAwtYhxmK1t5Qn-orUyvtV7Q@mail.gmail.com>
	<BANLkTi=-Q4xCy7z2skCSx_vJutL=aT-aNg@mail.gmail.com>
Message-ID: <20110501040101.28531.qmail@stuge.se>

????? ?????? wrote:
> May be add something like profiling option with patch for implementing
> such feature?

Feel free to send a patch?


//Peter



From scott at notabs.org  Sun May  1 06:11:37 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sat, 30 Apr 2011 23:11:37 -0500
Subject: [coreboot] Fwd: use gcc 4.6.0 link time optimization to reduce
	coreboot execution time
In-Reply-To: <BANLkTi=-Q4xCy7z2skCSx_vJutL=aT-aNg@mail.gmail.com>
References: <4E2C6DA2F6424C5BBA589A3E5D85B414@m3a78><20110430155620.GA14417@morn.localdomain><C2294C9FBDD44B398C89282144A66EC4@m3a78><BANLkTinbS0wAwtYhxmK1t5Qn-orUyvtV7Q@mail.gmail.com>
	<BANLkTi=-Q4xCy7z2skCSx_vJutL=aT-aNg@mail.gmail.com>
Message-ID: <AF76E004E8E6434E84036B9FD0858F7B@m3a78>

Anton Kochkov wrote:

] May be add something like profiling option with patch for implementing
] such feature?
] Best regards,
] Anton Kochkov.

Hello Anton,

In the past I have seen such logging code added to a BIOS code base.
It was for Phoenix legacy if I remember correctly. A challenge with 
this method is using it to exactly pinpoint a problem. For this board
I have the luxury of a jtag debugging setup, the Sage SmartProbe. This
arrangement is very handy for boot time reduction. I do a crude form
of profiling by breaking in randomly during post. I still find it
spending some time in lzma decode of ramstage. That time was reduced
by the -flto compiler option. 

Thanks,
Scott




From wmk587 at yahoo.com  Sun May  1 14:13:45 2011
From: wmk587 at yahoo.com (Boris Shpoungin)
Date: Sun, 1 May 2011 05:13:45 -0700 (PDT)
Subject: [coreboot] Porting Coreboot to Atom based platform (Atom E660 +
	EG20T chipset)
Message-ID: <736148.71339.qm@web33001.mail.mud.yahoo.com>

We are considering to port Coreboot for Intel Atom E660 + EG20T chipset patform. Our platform base on Intel Crown Bay evaluation board.

I wonder what are the first steps of porting?
What should we start to work from?
Any manuals, documents, suggestions, etc?

Thanks




From kevin at koconnor.net  Sun May  1 17:15:24 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sun, 1 May 2011 11:15:24 -0400
Subject: [coreboot] Fwd: use gcc 4.6.0 link time optimization to reduce
 coreboot execution time
In-Reply-To: <AF76E004E8E6434E84036B9FD0858F7B@m3a78>
References: <4E2C6DA2F6424C5BBA589A3E5D85B414@m3a78>
	<20110430155620.GA14417@morn.localdomain>
	<C2294C9FBDD44B398C89282144A66EC4@m3a78>
	<BANLkTinbS0wAwtYhxmK1t5Qn-orUyvtV7Q@mail.gmail.com>
	<BANLkTi=-Q4xCy7z2skCSx_vJutL=aT-aNg@mail.gmail.com>
	<AF76E004E8E6434E84036B9FD0858F7B@m3a78>
Message-ID: <20110501151524.GA4214@morn.localdomain>

On Sat, Apr 30, 2011 at 11:11:37PM -0500, Scott Duplichan wrote:
> Anton Kochkov wrote:
> 
> ] May be add something like profiling option with patch for implementing
> ] such feature?
> ] Best regards,
> ] Anton Kochkov.
> 
> Hello Anton,
> 
> In the past I have seen such logging code added to a BIOS code base.
> It was for Phoenix legacy if I remember correctly. A challenge with 
> this method is using it to exactly pinpoint a problem. For this board

There is a tool in the seabios repo - tools/readserial.py .  It can be
run on a separate host that reads the debug serial output - it
provides timing info on each line read and can adjust the times to
eliminate the cost of writing to the serial port.

It's not perfect, but it can provide a broad overview of where time is
spent.

If you haven't already tried it, it's usage follows:

./tools/readserial.py /dev/ttyS0 115200

>For this board
> I have the luxury of a jtag debugging setup, the Sage SmartProbe. This
> arrangement is very handy for boot time reduction. I do a crude form
> of profiling by breaking in randomly during post. I still find it
> spending some time in lzma decode of ramstage. That time was reduced
> by the -flto compiler option. 

Thanks - I'll have to try that on my board (an old epia-cn machine).
I found lzma to be time intensive.

-Kevin



From kevin at koconnor.net  Sun May  1 17:42:11 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sun, 1 May 2011 11:42:11 -0400
Subject: [coreboot] use gcc 4.6.0 link time optimization to reduce
 coreboot execution time
In-Reply-To: <C2294C9FBDD44B398C89282144A66EC4@m3a78>
References: <4E2C6DA2F6424C5BBA589A3E5D85B414@m3a78>
	<20110430155620.GA14417@morn.localdomain>
	<C2294C9FBDD44B398C89282144A66EC4@m3a78>
Message-ID: <20110501154211.GB4214@morn.localdomain>

On Sat, Apr 30, 2011 at 10:37:09PM -0500, Scott Duplichan wrote:
> Kevin O'Connor wrote:
> ] That's a great boot time!  Do you have a breakdown of where the 640ms
> ] is spent?
> I tried adding some serial logging to get an idea about where
> the time is spent. The logging adds 8 ms to the boot time:
> 
> Time in ms
> 0      cold reset
> 366    memory initialization complete
> 469    seabios: maininit(void)
> 483    seabios: vga_setup() called
> 604    seabios: vga_setup() returned
> 621    seabios: startBoot(void)
> 648    dos autoexec utility logs pmtimer value

Interesting - thanks.  These numbers look similar to the times I was
getting with a different board last year:

http://www.coreboot.org/pipermail/coreboot/2009-December/054770.html

> It looks like the lengthy operations are memory init and VBIOS
> execution, which is consistent with past experience.
> 
> UEFI BIOS on this same hardware platform is taking more than 
> 10 seconds.

:-)

> Here seabios kconfig options I changed:
[...]
> ATA controllers                              n
> AHCI controllers                             y
> Floppy controller                            n
> PS/2 port                                    n
> USB UHCI controllers                         n
> Parallel port                                n
> PCIBIOS interface                            n
> APM interface                                n
> PnP BIOS interface                           n
> S3 resume                                    n
> SMBIOS                                       n

Do these options change the boot time?  Since there is already 160ms
of time spent in SeaBIOS, I would have thought the time for all of
these could have been done in parallel anyway.

-Kevin



From svn at coreboot.org  Mon May  2 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 02 May 2011 16:00:02 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1QGtfO-0007Tw-Tt@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110502/60789bf5/attachment.html>

From svens at stackframe.org  Mon May  2 16:13:33 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Mon,  2 May 2011 16:13:33 +0200
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
Message-ID: <1304345613-28138-1-git-send-email-svens@stackframe.org>

Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to grub takes
4s, with around 1s required for decompressing ramstage. This is probably
caused by the fact the decompression does a lot of single byte/word/qword
accesses, which are really slow on SPI buses. So give the user the option
to store ramstage uncompressed, if he has enough memory.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 Makefile.inc |    4 ++++
 src/Kconfig  |    8 ++++++++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 6c4a16a..6267539 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -85,7 +85,11 @@ cbfs-files-handler= \
 
 #######################################################################
 # a variety of flags for our build
+CBFS_COMPRESS_FLAG:=
+ifeq ($(CONFIG_COMPRESS_RAMSTAGE),y)
 CBFS_COMPRESS_FLAG:=l
+endif
+
 CBFS_PAYLOAD_COMPRESS_FLAG:=
 CBFS_PAYLOAD_COMPRESS_NAME:=none
 ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y)
diff --git a/src/Kconfig b/src/Kconfig
index 76e77f8..a782315 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -98,6 +98,14 @@ config USE_OPTION_TABLE
 	  Enable this option if coreboot shall read options from the "CMOS"
 	  NVRAM instead of using hard coded values.
 
+config COMPRESS_RAMSTAGE
+	bool "Compress ramstage with LZMA"
+	default y
+	help
+	  Compress ramstage to save memory in the flash image. Note
+	  that decompression might slow down booting if the BIOS flash
+	  is connected through a slow Link (i.e. SPI)
+
 endmenu
 
 source src/mainboard/Kconfig
-- 
1.7.4.4




From patrick at georgi-clan.de  Mon May  2 17:42:02 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 02 May 2011 17:42:02 +0200
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <1304345613-28138-1-git-send-email-svens@stackframe.org>
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
Message-ID: <4DBED0CA.7000402@georgi-clan.de>

Am 02.05.2011 16:13, schrieb Sven Schnelle:
> Add an option to make compression of ramstage configurable. Right now
> it is always compressed. On my Thinkpad, the complete boot to grub takes
> 4s, with around 1s required for decompressing ramstage. This is probably
> caused by the fact the decompression does a lot of single byte/word/qword
> accesses, which are really slow on SPI buses. So give the user the option
> to store ramstage uncompressed, if he has enough memory.
> 
> Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>



From scott at notabs.org  Mon May  2 17:45:32 2011
From: scott at notabs.org (Scott Duplichan)
Date: Mon, 2 May 2011 10:45:32 -0500
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <1304345613-28138-1-git-send-email-svens@stackframe.org>
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
Message-ID: <45D5161B228A422E8A2BAD267716F8E3@m3a78>

Sven Schnelle wrote:

]Add an option to make compression of ramstage configurable. Right now
]it is always compressed. On my Thinkpad, the complete boot to grub takes
]4s, with around 1s required for decompressing ramstage. This is probably
]caused by the fact the decompression does a lot of single byte/word/qword
]accesses, which are really slow on SPI buses. So give the user the option
]to store ramstage uncompressed, if he has enough memory.
]
]Signed-off-by: Sven Schnelle <svens at stackframe.org>

Hello Sven,

Thanks, I like having this option. For AMD Persimmon I get these
boot times for coreboot+seabios+dos ssd drive:

                                      Standard    No compress
SPI 33 MHz fast mode, prefetch        0.690       0.717
SPI 33 MHz fast mode, no prefetch     0.933       1.041
AMD Simnow                            9.0         3.0

For this project compress disable slows booting on real hardware slightly,
but it vastly improves simnow boot time.

Is your SB SPI prefetch enabled? Using the cycle logging feature of
DediProg EM100 shows that for AMD, SPI reads are all dwords until the
SB SPI prefetch is enabled, at which time they become cache line reads.

Thanks,
Scott




From stefan.reinauer at coreboot.org  Mon May  2 20:34:42 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 2 May 2011 20:34:42 +0200
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <1304345613-28138-1-git-send-email-svens@stackframe.org>
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
Message-ID: <20110502183442.GA5871@coreboot.org>

* Sven Schnelle <svens at stackframe.org> [110502 16:13]:
> Add an option to make compression of ramstage configurable. Right now
> it is always compressed. On my Thinkpad, the complete boot to grub takes
> 4s, with around 1s required for decompressing ramstage. This is probably
> caused by the fact the decompression does a lot of single byte/word/qword
> accesses, which are really slow on SPI buses. So give the user the option
> to store ramstage uncompressed, if he has enough memory.

Hi Sven,

can you try whether your thinkpad can boot faster if you enable spi
prefetching in src/southbridge/intel/i82801gx/bootblock.c

i.e.

static void enable_spi_prefetch(void)
{
        u8 reg8;
        device_t dev;

        dev = PCI_DEV(0, 0x1f, 0);

        reg8 = pci_read_config8(dev, 0xdc);
        reg8 &= ~(3 << 2);
        reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
        pci_write_config8(dev, 0xdc, reg8);
}

static void bootblock_southbridge_init(void)
{
        ...
        enable_spi_prefetch();
        ...
}

Stefan




From peter at stuge.se  Mon May  2 20:49:38 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 2 May 2011 20:49:38 +0200
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <1304345613-28138-1-git-send-email-svens@stackframe.org>
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
Message-ID: <20110502184938.29112.qmail@stuge.se>

Sven Schnelle wrote:
> +++ b/src/Kconfig
..
> +	help
> +	  Compress ramstage to save memory in the flash image. Note
> +	  that decompression might slow down booting if the BIOS flash
> +	  is connected through a slow Link (i.e. SPI)

Please write "boot flash" since there may not be any BIOS.


//Peter



From scott at notabs.org  Mon May  2 20:30:49 2011
From: scott at notabs.org (Scott Duplichan)
Date: Mon, 2 May 2011 13:30:49 -0500
Subject: [coreboot] use gcc 4.6.0 link time optimization to reduce
	coreboot execution time
In-Reply-To: <20110501154211.GB4214@morn.localdomain>
References: <4E2C6DA2F6424C5BBA589A3E5D85B414@m3a78><20110430155620.GA14417@morn.localdomain><C2294C9FBDD44B398C89282144A66EC4@m3a78>
	<20110501154211.GB4214@morn.localdomain>
Message-ID: <16784FFE71754D48ACA1CD853860605B@m3a78>

Kevin O'Connor wrote:

]> Here seabios kconfig options I changed:
][...]
]> ATA controllers                              n
]> AHCI controllers                             y
]> Floppy controller                            n
]> PS/2 port                                    n
]> USB UHCI controllers                         n
]> Parallel port                                n
]> PCIBIOS interface                            n
]> APM interface                                n
]> PnP BIOS interface                           n
]> S3 resume                                    n
]> SMBIOS                                       n
]
]Do these options change the boot time?  Since there is already 160ms
]of time spent in SeaBIOS, I would have thought the time for all of
]these could have been done in parallel anyway.
]
]-Kevin

It looks like disabling unused options saves about 5 ms. Even if
the code has no significant execution time, removing it makes the
compressed payload smaller and take less time to read from flash.

Thanks,
Scott




From svn at coreboot.org  Mon May  2 21:53:05 2011
From: svn at coreboot.org (repository service)
Date: Mon, 02 May 2011 21:53:05 +0200
Subject: [coreboot] [commit] r6552 - in trunk: . src
Message-ID: <E1QGzB3-0001H8-D4@ra.coresystems.de>

Author: svens
Date: Mon May  2 21:53:04 2011
New Revision: 6552
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6552

Log:
Add option 'compress ramstage'

Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to grub takes
4s, with around 1s required for decompressing ramstage. This is probably
caused by the fact the decompression does a lot of single byte/word/qword
accesses, which are really slow on SPI buses. So give the user the option
to store ramstage uncompressed, if he has enough memory.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/Makefile.inc
   trunk/src/Kconfig

Modified: trunk/Makefile.inc
==============================================================================
--- trunk/Makefile.inc	Sat Apr 30 02:22:04 2011	(r6551)
+++ trunk/Makefile.inc	Mon May  2 21:53:04 2011	(r6552)
@@ -85,7 +85,11 @@
 
 #######################################################################
 # a variety of flags for our build
+CBFS_COMPRESS_FLAG:=
+ifeq ($(CONFIG_COMPRESS_RAMSTAGE),y)
 CBFS_COMPRESS_FLAG:=l
+endif
+
 CBFS_PAYLOAD_COMPRESS_FLAG:=
 CBFS_PAYLOAD_COMPRESS_NAME:=none
 ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y)

Modified: trunk/src/Kconfig
==============================================================================
--- trunk/src/Kconfig	Sat Apr 30 02:22:04 2011	(r6551)
+++ trunk/src/Kconfig	Mon May  2 21:53:04 2011	(r6552)
@@ -98,6 +98,14 @@
 	  Enable this option if coreboot shall read options from the "CMOS"
 	  NVRAM instead of using hard coded values.
 
+config COMPRESS_RAMSTAGE
+	bool "Compress ramstage with LZMA"
+	default y
+	help
+	  Compress ramstage to save memory in the flash image. Note
+	  that decompression might slow down booting if the boot flash
+	  is connected through a slow Link (i.e. SPI)
+
 endmenu
 
 source src/mainboard/Kconfig



From ebiederm at xmission.com  Mon May  2 22:00:29 2011
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Mon, 02 May 2011 13:00:29 -0700
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <1304345613-28138-1-git-send-email-svens@stackframe.org> (Sven
	Schnelle's message of "Mon, 2 May 2011 16:13:33 +0200")
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
Message-ID: <m11v0gx482.fsf@fess.ebiederm.org>

Sven Schnelle <svens at stackframe.org> writes:

> Add an option to make compression of ramstage configurable. Right now
> it is always compressed. On my Thinkpad, the complete boot to grub takes
> 4s, with around 1s required for decompressing ramstage. This is probably
> caused by the fact the decompression does a lot of single byte/word/qword
> accesses, which are really slow on SPI buses. So give the user the option
> to store ramstage uncompressed, if he has enough memory.

Odd. Historically this has been solved by simply putting an mtrr over
the compressed area.  So that you would still get full cache block
transfers during the decompression.  I am fuzzy about the appropriate
mode.  Write protect I think.

Have you tried setting up an mtrr over the area that will be
decompressed.  That should result in something that is even faster
than copying non-compressed data.

Eric



From stefan.reinauer at coreboot.org  Tue May  3 01:02:19 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 3 May 2011 01:02:19 +0200
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <m11v0gx482.fsf@fess.ebiederm.org>
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
	<m11v0gx482.fsf@fess.ebiederm.org>
Message-ID: <20110502230219.GA7058@coreboot.org>

* Eric W. Biederman <ebiederm at xmission.com> [110502 22:00]:
> Sven Schnelle <svens at stackframe.org> writes:
> 
> > Add an option to make compression of ramstage configurable. Right now
> > it is always compressed. On my Thinkpad, the complete boot to grub takes
> > 4s, with around 1s required for decompressing ramstage. This is probably
> > caused by the fact the decompression does a lot of single byte/word/qword
> > accesses, which are really slow on SPI buses. So give the user the option
> > to store ramstage uncompressed, if he has enough memory.
> 
> Odd. Historically this has been solved by simply putting an mtrr over
> the compressed area.  So that you would still get full cache block
> transfers during the decompression.  I am fuzzy about the appropriate
> mode.  Write protect I think.
> 
> Have you tried setting up an mtrr over the area that will be
> decompressed.  That should result in something that is even faster
> than copying non-compressed data.

The problem is that the code hard coded those values assuming coreboot
lives in the first 1MB which is not the case anymore since we have SMM
handlers.

Stefan





From stefan.reinauer at coreboot.org  Tue May  3 01:04:15 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 3 May 2011 01:04:15 +0200
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <20110502183442.GA5871@coreboot.org>
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
	<20110502183442.GA5871@coreboot.org>
Message-ID: <20110502230415.GB7058@coreboot.org>

* Stefan Reinauer <stefan.reinauer at coreboot.org> [110502 20:34]:
> * Sven Schnelle <svens at stackframe.org> [110502 16:13]:
> > Add an option to make compression of ramstage configurable. Right now
> > it is always compressed. On my Thinkpad, the complete boot to grub takes
> > 4s, with around 1s required for decompressing ramstage. This is probably
> > caused by the fact the decompression does a lot of single byte/word/qword
> > accesses, which are really slow on SPI buses. So give the user the option
> > to store ramstage uncompressed, if he has enough memory.
> 
> Hi Sven,
> 
> can you try whether your thinkpad can boot faster if you enable spi
> prefetching in src/southbridge/intel/i82801gx/bootblock.c
> 
> i.e.
> 
> static void enable_spi_prefetch(void)
> {
>         u8 reg8;
>         device_t dev;
> 
>         dev = PCI_DEV(0, 0x1f, 0);
> 
>         reg8 = pci_read_config8(dev, 0xdc);
>         reg8 &= ~(3 << 2);
>         reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
>         pci_write_config8(dev, 0xdc, reg8);
> }
> 
> static void bootblock_southbridge_init(void)
> {
>         ...
>         enable_spi_prefetch();
>         ...
> }

And in addition you need to set up MTRRs correctly by doing something
like this: (sorry, wrong CPU type but the code should be fairly similar)

Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

--- src/cpu/intel/model_106cx/cache_as_ram.inc
+++ src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -195,13 +195,27 @@ clear_mtrrs:
 
 	post_code(0x38)
 
-	/* Enable Write Back and Speculative Reads for the first 1MB. */
+	/* Enable Write Back and Speculative Reads for the first MB
+	 * and coreboot_ram.
+	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
-	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
 	xorl	%edx, %edx
 	wrmsr
 



From peter at stuge.se  Tue May  3 02:50:14 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 3 May 2011 02:50:14 +0200
Subject: [coreboot] [PATCH] Set up MTRR for coreboot_ram
In-Reply-To: <20110502230415.GB7058@coreboot.org>
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
	<20110502183442.GA5871@coreboot.org>
	<20110502230415.GB7058@coreboot.org>
Message-ID: <20110503005014.5285.qmail@stuge.se>

Stefan Reinauer wrote:
> And in addition you need to set up MTRRs correctly by doing something
> like this: (sorry, wrong CPU type but the code should be fairly similar)
> 
> Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Acked-by: Peter Stuge <peter at stuge.se>

> --- src/cpu/intel/model_106cx/cache_as_ram.inc
> +++ src/cpu/intel/model_106cx/cache_as_ram.inc
> @@ -195,13 +195,27 @@ clear_mtrrs:
>  
>  	post_code(0x38)
>  
> -	/* Enable Write Back and Speculative Reads for the first 1MB. */
> +	/* Enable Write Back and Speculative Reads for the first MB
> +	 * and coreboot_ram.
> +	 */
>  	movl	$MTRRphysBase_MSR(0), %ecx
>  	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
>  	xorl	%edx, %edx
>  	wrmsr
>  	movl	$MTRRphysMask_MSR(0), %ecx
> -	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
> +	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
> +	xorl	%edx, %edx
> +	wrmsr
> +
> +	/* Enable Caching and speculative Reads for the
> +	 * complete ROM now that we actually have RAM.
> +	 */
> +	movl	$MTRRphysBase_MSR(1), %ecx
> +	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
> +	xorl	%edx, %edx
> +	wrmsr
> +	movl	$MTRRphysMask_MSR(1), %ecx
> +	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
>  	xorl	%edx, %edx
>  	wrmsr



From ebiederm at xmission.com  Tue May  3 01:26:12 2011
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Mon, 02 May 2011 16:26:12 -0700
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <20110502230219.GA7058@coreboot.org> (Stefan Reinauer's message
	of "Tue, 3 May 2011 01:02:19 +0200")
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
	<m11v0gx482.fsf@fess.ebiederm.org>
	<20110502230219.GA7058@coreboot.org>
Message-ID: <m1liyovg4r.fsf@fess.ebiederm.org>

Stefan Reinauer <stefan.reinauer at coreboot.org> writes:

> * Eric W. Biederman <ebiederm at xmission.com> [110502 22:00]:
>> Sven Schnelle <svens at stackframe.org> writes:
>> 
>> > Add an option to make compression of ramstage configurable. Right now
>> > it is always compressed. On my Thinkpad, the complete boot to grub takes
>> > 4s, with around 1s required for decompressing ramstage. This is probably
>> > caused by the fact the decompression does a lot of single byte/word/qword
>> > accesses, which are really slow on SPI buses. So give the user the option
>> > to store ramstage uncompressed, if he has enough memory.
>> 
>> Odd. Historically this has been solved by simply putting an mtrr over
>> the compressed area.  So that you would still get full cache block
>> transfers during the decompression.  I am fuzzy about the appropriate
>> mode.  Write protect I think.
>> 
>> Have you tried setting up an mtrr over the area that will be
>> decompressed.  That should result in something that is even faster
>> than copying non-compressed data.
>
> The problem is that the code hard coded those values assuming coreboot
> lives in the first 1MB which is not the case anymore since we have SMM
> handlers.

Was that a destination hard code?  The code itself should come out of
the last couple of megabytes before 4G.

Regardless the performance penalty for not caching is huge fractions
of the boot time so whatever small practical issues exist we should
figure them out.

Eric



From stefan.reinauer at coreboot.org  Tue May  3 03:23:05 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 3 May 2011 03:23:05 +0200
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <m1liyovg4r.fsf@fess.ebiederm.org>
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
	<m11v0gx482.fsf@fess.ebiederm.org>
	<20110502230219.GA7058@coreboot.org>
	<m1liyovg4r.fsf@fess.ebiederm.org>
Message-ID: <20110503012305.GA27608@coreboot.org>

* Eric W. Biederman <ebiederm at xmission.com> [110503 01:26]:
> Was that a destination hard code?  The code itself should come out of
> the last couple of megabytes before 4G.
 
Yes. Only the lower 1MB of the destination memory was cached, while
coreboot's ram stage is now copied to 1MB.

My other mail to the list shows how to fix it.




From marcj303 at gmail.com  Tue May  3 07:13:45 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 2 May 2011 23:13:45 -0600
Subject: [coreboot] Update AMD Persimmon project to support Windows 7, XP,
	linux
In-Reply-To: <DF9883C3F0C54A4ABDBAFC086F972F43@m3a78>
References: <BANLkTik2J19V5QBrXGUU3nFYWmEwhCVNYw@mail.gmail.com>
	<DF9883C3F0C54A4ABDBAFC086F972F43@m3a78>
Message-ID: <BANLkTinO1_=pgkJL-aykv8+3fRk6OPx52w@mail.gmail.com>

Hi Scott,
Thanks for this discussion.

On Thu, Apr 21, 2011 at 1:10 PM, Scott Duplichan <scott at notabs.org> wrote:
> I have a set of AMD persimmon patches for improved OS support.
> The changes should easily port to ASRock E350M1 and AMD Inagua.
>
> These operating systems were tested and can install from a DVD and boot from hard disk:
> 1) Windows 7 with SP1 and latest AMD video driver
> 2) ubuntu-11.04-beta2-dvd-amd64.iso
> 3) Windows Server 2003 x64 SP2
> 4) Windows XP x64 SP2
>
> Live CD test only:
> 1) linuxmint-9
> 2) slax 6.12
> 3) nimblex 2010 beta
>
> Here is a summary of the changes. Change #1 is essential, but it is a work around
> and not a true fix. Before submitting the patches, we should decide what to do
> about item #1. Here is a past discussion of the problem. While the past problem
> occurred only when a PCI video card was added, the current problem happens with
> no added cards:
> http://www.coreboot.org/pipermail/coreboot/2010-October/061320.html
>
> Here is the work around I am testing with. It limits device memory
> allocation to the area below MMCONF_BASE. The method works, but
> wastes address space:
> Index: src/devices/pci_device.c
> ===================================================================
> --- src/devices/pci_device.c ?(revision 6483)
> +++ src/devices/pci_device.c ?(working copy)
> @@ -259,6 +259,7 @@
> ? ? ?if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
> ? ? ? ? /* 32bit limit. */
> ? ? ? ? resource->limit = 0xffffffffUL;
> + ? ? ? ?resource->limit = CONFIG_MMCONF_BASE_ADDRESS - 1;
> ? ? ?} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
> ? ? ? ? /* 1MB limit. */
> ? ? ? ? resource->limit = 0x000fffffUL;
>
>
> 1) Work around coreboot resource allocation problem that causes
> overlap of PCIe MMIO space and graphics MMIO space.

Why isn't this covered by the bus resource allocation for MMCONF? I
think that this should handle the situation. How does the overlap
happen?

static void cpu_bus_read_resources(device_t dev)
{
    printk(BIOS_DEBUG, "\nFam14h - cpu_bus_read_resources.\n");

#if CONFIG_MMCONF_SUPPORT
    struct resource *resource = new_resource(dev, 0xc0010058);
    resource->base = CONFIG_MMCONF_BASE_ADDRESS;
    resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
    resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
        IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
#endif
}

Thanks,
Marc


> 2) Add device allocation for AP cores so that they will be reported and used by OS.
> 3) Change cimx wrapper code so that OS shutdown function will work.
> 4) Fix problems that cause incorrect programming and incorrect reporting of I/O APIC ID.
> 5) Fix code that ignores MMCONF_BUS_NUMBER value and always uses 256.
> 6) Change coreboot ACPI code to not report RTC as PIIX4 compatible.
> 7) Add coreboot ACPI code to report PS/2 KB and mouse (ASRock only).
> 8) Change coreboot ACPI code to report memory range A0000-Bffff as used.
> 9) Change coreboot ACPI code to report proper FADT revision.
> 10) Correct MP table reporting of APIC version.
> 11) Program SB800 MiscCntrl earlier so first serial output is not garbled.
> 12) Enable cache early to decrease coreboot execution time.
> 13) Remove some unused HT code. Remove other unneeded code.
> 14) Change seabios to use DMA instead of PIO for disk reads.
>
> Thanks,
> Scott
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



-- 
http://se-eng.com



From svn at coreboot.org  Tue May  3 09:55:30 2011
From: svn at coreboot.org (repository service)
Date: Tue, 03 May 2011 09:55:30 +0200
Subject: [coreboot] [commit] r6553 - trunk/src/southbridge/intel/i82801gx
Message-ID: <E1QHASA-0006wh-J3@ra.coresystems.de>

Author: svens
Date: Tue May  3 09:55:30 2011
New Revision: 6553
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6553

Log:
i82801gx: enable SPI prefetching

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>

Added:
   trunk/src/southbridge/intel/i82801gx/bootblock.c
Modified:
   trunk/src/southbridge/intel/i82801gx/Kconfig

Modified: trunk/src/southbridge/intel/i82801gx/Kconfig
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/Kconfig	Mon May  2 21:53:04 2011	(r6552)
+++ trunk/src/southbridge/intel/i82801gx/Kconfig	Tue May  3 09:55:30 2011	(r6553)
@@ -38,5 +38,10 @@
 	int
 	default 1 
 
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+        string
+	default "southbridge/intel/i82801gx/bootblock.c"
+	depends on SOUTHBRIDGE_INTEL_I82801GX
+
 endif
 

Added: trunk/src/southbridge/intel/i82801gx/bootblock.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/bootblock.c	Tue May  3 09:55:30 2011	(r6553)
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+static void enable_spi_prefetch(void)
+{
+        u8 reg8;
+        device_t dev;
+
+        dev = PCI_DEV(0, 0x1f, 0);
+
+        reg8 = pci_read_config8(dev, 0xdc);
+        reg8 &= ~(3 << 2);
+        reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+        pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void bootblock_southbridge_init(void)
+{
+        enable_spi_prefetch();
+}
+



From svn at coreboot.org  Tue May  3 09:55:44 2011
From: svn at coreboot.org (repository service)
Date: Tue, 03 May 2011 09:55:44 +0200
Subject: [coreboot] [commit] r6554 - trunk/src/cpu/intel/model_6ex
Message-ID: <E1QHASO-00072o-E3@ra.coresystems.de>

Author: svens
Date: Tue May  3 09:55:43 2011
New Revision: 6554
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6554

Log:
Enable caching for ROM area in model_6ex/cache_as_ram.inc

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>

Modified:
   trunk/src/cpu/intel/model_6ex/cache_as_ram.inc

Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Tue May  3 09:55:30 2011	(r6553)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Tue May  3 09:55:43 2011	(r6554)
@@ -201,7 +201,17 @@
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
-	movl	$(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx	// 36bit address space
+	wrmsr
+
+	/* Enable caching and Speculative Reads for the last 4MB. */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
 	movl	$0x0000000f, %edx	// 36bit address space
 	wrmsr
 



From paulepanter at users.sourceforge.net  Tue May  3 10:17:18 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 03 May 2011 10:17:18 +0200
Subject: [coreboot] [commit] r6554 - trunk/src/cpu/intel/model_6ex
In-Reply-To: <E1QHASO-00072o-E3@ra.coresystems.de>
References: <E1QHASO-00072o-E3@ra.coresystems.de>
Message-ID: <1304410638.13481.40.camel@mattotaupa>

Dear Sven,


Am Dienstag, den 03.05.2011, 09:55 +0200 schrieb repository service:
> Author: svens
> Date: Tue May  3 09:55:43 2011
> New Revision: 6554
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6554
> 
> Log:
> Enable caching for ROM area in model_6ex/cache_as_ram.inc

it would be great if you could add a small comment to the commit message
if that change improved anything or not.

> Signed-off-by: Sven Schnelle <svens at stackframe.org>
> Acked-by: Sven Schnelle <svens at stackframe.org>
> 
> Modified:
>    trunk/src/cpu/intel/model_6ex/cache_as_ram.inc

[?]

Thank you for your great work. I am looking forward to the LinuxTag 2011
to meet you (and the other folks) in person and to see your Lenovo
system running coreboot.


Thanks,

Paul
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From svens at stackframe.org  Tue May  3 10:20:44 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 03 May 2011 10:20:44 +0200
Subject: [coreboot] [PATCH] Add option 'compress ramstage'
In-Reply-To: <20110503012305.GA27608@coreboot.org> (Stefan Reinauer's message
	of "Tue\, 3 May 2011 03\:23\:05 +0200")
References: <1304345613-28138-1-git-send-email-svens@stackframe.org>
	<m11v0gx482.fsf@fess.ebiederm.org>
	<20110502230219.GA7058@coreboot.org>
	<m1liyovg4r.fsf@fess.ebiederm.org>
	<20110503012305.GA27608@coreboot.org>
Message-ID: <87vcxsfb4z.fsf@begreifnix.stackframe.org>

Hi Stefan, hi Eric,

Stefan Reinauer <stefan.reinauer at coreboot.org> writes:

> * Eric W. Biederman <ebiederm at xmission.com> [110503 01:26]:
>> Was that a destination hard code?  The code itself should come out of
>> the last couple of megabytes before 4G.
>  
> Yes. Only the lower 1MB of the destination memory was cached, while
> coreboot's ram stage is now copied to 1MB.

thanks for all your help. I've did both changes (enabling SPI prefetch
and setting the MTRRs right). Boot time decreased now to 1.8s (with only
1s spent in coreboot). Decompression time is now about 100ms, which is
much better than what we had before (1.9s only for ramstage loading).

Thanks,

Sven.



From svens at stackframe.org  Tue May  3 10:23:17 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 03 May 2011 10:23:17 +0200
Subject: [coreboot] [commit] r6554 - trunk/src/cpu/intel/model_6ex
In-Reply-To: <1304410638.13481.40.camel@mattotaupa> (Paul Menzel's message of
	"Tue\, 03 May 2011 10\:17\:18 +0200")
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
Message-ID: <87r58gfb0q.fsf@begreifnix.stackframe.org>

Hi Paul,

Paul Menzel <paulepanter at users.sourceforge.net> writes:

> Am Dienstag, den 03.05.2011, 09:55 +0200 schrieb repository service:
>> Author: svens
>> Date: Tue May  3 09:55:43 2011
>> New Revision: 6554
>> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6554
>> 
>> Log:
>> Enable caching for ROM area in model_6ex/cache_as_ram.inc
>
> it would be great if you could add a small comment to the commit message
> if that change improved anything or not.

See my other mail to Stefan and Eric - Stage loading time decreased from
1.9s to around 100ms, which is pretty nice :)

> Thank you for your great work. I am looking forward to the LinuxTag 2011
> to meet you (and the other folks) in person and to see your Lenovo
> system running coreboot.

Nice to know that you'll be there. :)

See you in Berlin,

Sven.



From peter at stuge.se  Tue May  3 15:04:47 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 3 May 2011 15:04:47 +0200
Subject: [coreboot] [commit] r6553 -	trunk/src/southbridge/intel/i82801gx
In-Reply-To: <E1QHASA-0006wh-J3@ra.coresystems.de>
References: <E1QHASA-0006wh-J3@ra.coresystems.de>
Message-ID: <20110503130447.16540.qmail@stuge.se>

repository service wrote:
> +++ trunk/src/southbridge/intel/i82801gx/Kconfig	Tue May  3 09:55:30 2011	(r6553)
> @@ -38,5 +38,10 @@
>  	int
>  	default 1 
>  
> +config BOOTBLOCK_SOUTHBRIDGE_INIT
> +        string
> +	default "southbridge/intel/i82801gx/bootblock.c"
> +	depends on SOUTHBRIDGE_INTEL_I82801GX
> +

Why in Kconfig and not a Makefile variable?

Oh and please always double-check the whitespace. (See "string")


//Peter



From svens at stackframe.org  Tue May  3 15:17:01 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 03 May 2011 15:17:01 +0200
Subject: [coreboot] [commit] r6553 -	trunk/src/southbridge/intel/i82801gx
In-Reply-To: <20110503130447.16540.qmail@stuge.se> (Peter Stuge's message of
	"Tue\, 3 May 2011 15\:04\:47 +0200")
References: <E1QHASA-0006wh-J3@ra.coresystems.de>
	<20110503130447.16540.qmail@stuge.se>
Message-ID: <87k4e7gbzm.fsf@begreifnix.stackframe.org>

Peter Stuge <peter at stuge.se> writes:

> repository service wrote:
>> +++ trunk/src/southbridge/intel/i82801gx/Kconfig	Tue May  3 09:55:30 2011	(r6553)
>> @@ -38,5 +38,10 @@
>>  	int
>>  	default 1 
>>  
>> +config BOOTBLOCK_SOUTHBRIDGE_INIT
>> +        string
>> +	default "southbridge/intel/i82801gx/bootblock.c"
>> +	depends on SOUTHBRIDGE_INTEL_I82801GX
>> +
>
> Why in Kconfig and not a Makefile variable?

That's how the current implementation wants it. Changing that
is beyond the scope of that Patch. Sorry for the whitespace
error.

Sven.



From stefan.reinauer at coresystems.de  Tue May  3 18:10:11 2011
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Tue, 3 May 2011 09:10:11 -0700
Subject: [coreboot] [commit] r6553 -	trunk/src/southbridge/intel/i82801gx
In-Reply-To: <20110503130447.16540.qmail@stuge.se>
References: <E1QHASA-0006wh-J3@ra.coresystems.de>
	<20110503130447.16540.qmail@stuge.se>
Message-ID: <6F5437C6-297E-47D7-9FFF-DC85F44B24EB@coresystems.de>


On 03.05.2011, at 06:04, Peter Stuge <peter at stuge.se> wrote:

> repository service wrote:
>> +++ trunk/src/southbridge/intel/i82801gx/Kconfig    Tue May  3 09:55:30 2011    (r6553)
>> @@ -38,5 +38,10 @@
>>    int
>>    default 1 
>> 
>> +config BOOTBLOCK_SOUTHBRIDGE_INIT
>> +        string
>> +    default "southbridge/intel/i82801gx/bootblock.c"
>> +    depends on SOUTHBRIDGE_INTEL_I82801GX
>> +
> 
> Why in Kconfig and not a Makefile variable?
> 
> Oh and please always double-check the whitespace. (See "string")
> 
> 
> //Peter

I agree this belongs in the Makefiles.. Not sure why we chose to put it here but it might have required another makefile pass otherwise 





From patrick at georgi-clan.de  Tue May  3 20:01:16 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 03 May 2011 20:01:16 +0200
Subject: [coreboot] [commit] r6553 -	trunk/src/southbridge/intel/i82801gx
In-Reply-To: <6F5437C6-297E-47D7-9FFF-DC85F44B24EB@coresystems.de>
References: <E1QHASA-0006wh-J3@ra.coresystems.de>	<20110503130447.16540.qmail@stuge.se>
	<6F5437C6-297E-47D7-9FFF-DC85F44B24EB@coresystems.de>
Message-ID: <4DC042EC.3000006@georgi-clan.de>

Am 03.05.2011 18:10, schrieb Stefan Reinauer:
> I agree this belongs in the Makefiles.. Not sure why we chose to put it here but it might have required another makefile pass otherwise 
"Back then" the build system was a bit limited, so this was more feasible.

We also need to push data from build system variables into romcc (ie.
-DA=B flags) for bootblock. Not impossible, but not as automatic as it
currently works.


Patrick



From stefan.reinauer at coresystems.de  Tue May  3 20:11:20 2011
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Tue, 3 May 2011 11:11:20 -0700
Subject: [coreboot] [commit] r6553 -	trunk/src/southbridge/intel/i82801gx
In-Reply-To: <4DC042EC.3000006@georgi-clan.de>
References: <E1QHASA-0006wh-J3@ra.coresystems.de>
	<20110503130447.16540.qmail@stuge.se>
	<6F5437C6-297E-47D7-9FFF-DC85F44B24EB@coresystems.de>
	<4DC042EC.3000006@georgi-clan.de>
Message-ID: <D385C3AF-74B4-42BF-A74E-42240D874D5B@coresystems.de>



On 03.05.2011, at 11:01, Patrick Georgi <patrick at georgi-clan.de> wrote:

> Am 03.05.2011 18:10, schrieb Stefan Reinauer:
>> I agree this belongs in the Makefiles.. Not sure why we chose to put it here but it might have required another makefile pass otherwise 
> "Back then" the build system was a bit limited, so this was more feasible.
> 
> We also need to push data from build system variables into romcc (ie.
> -DA=B flags) for bootblock. Not impossible, but not as automatic as it
> currently works.
> 
> 

Can't we just call the bootblock compilation with -include path/to/component/bootblock.c ?



> Patrick
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 



From patrick at georgi-clan.de  Tue May  3 20:15:48 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 03 May 2011 20:15:48 +0200
Subject: [coreboot] [commit] r6553 -	trunk/src/southbridge/intel/i82801gx
In-Reply-To: <D385C3AF-74B4-42BF-A74E-42240D874D5B@coresystems.de>
References: <E1QHASA-0006wh-J3@ra.coresystems.de>
	<20110503130447.16540.qmail@stuge.se>
	<6F5437C6-297E-47D7-9FFF-DC85F44B24EB@coresystems.de>
	<4DC042EC.3000006@georgi-clan.de>
	<D385C3AF-74B4-42BF-A74E-42240D874D5B@coresystems.de>
Message-ID: <4DC04654.5060301@georgi-clan.de>

Am 03.05.2011 20:11, schrieb Stefan Reinauer:
> On 03.05.2011, at 11:01, Patrick Georgi <patrick at georgi-clan.de> wrote:
>> We also need to push data from build system variables into romcc (ie.
>> -DA=B flags) for bootblock. Not impossible, but not as automatic as it
>> currently works.
> Can't we just call the bootblock compilation with -include path/to/component/bootblock.c ?
Feasible, with some additional plumbing


Patrick



From stefan.reinauer at coreboot.org  Tue May  3 20:29:32 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 3 May 2011 20:29:32 +0200
Subject: [coreboot] [commit] r6554 - trunk/src/cpu/intel/model_6ex
In-Reply-To: <87r58gfb0q.fsf@begreifnix.stackframe.org>
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
Message-ID: <20110503182932.GA18695@coreboot.org>

* Sven Schnelle <svens at stackframe.org> [110503 10:23]:
> Hi Paul,
> 
> Paul Menzel <paulepanter at users.sourceforge.net> writes:
> 
> > Am Dienstag, den 03.05.2011, 09:55 +0200 schrieb repository service:
> >> Author: svens
> >> Date: Tue May  3 09:55:43 2011
> >> New Revision: 6554
> >> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6554
> >> 
> >> Log:
> >> Enable caching for ROM area in model_6ex/cache_as_ram.inc
> >
> > it would be great if you could add a small comment to the commit message
> > if that change improved anything or not.
> 
> See my other mail to Stefan and Eric - Stage loading time decreased from
> 1.9s to around 100ms, which is pretty nice :)

Can you do a new analysis on where the boot time goes now? It would be
nice to see if there are more optimizations we can do...





From svens at stackframe.org  Tue May  3 21:41:41 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 03 May 2011 21:41:41 +0200
Subject: [coreboot] [commit] r6554 - trunk/src/cpu/intel/model_6ex
In-Reply-To: <20110503182932.GA18695@coreboot.org> (Stefan Reinauer's message
	of "Tue\, 3 May 2011 20\:29\:32 +0200")
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
Message-ID: <87ei4ffu6i.fsf@begreifnix.stackframe.org>

Stefan Reinauer <stefan.reinauer at coreboot.org> writes:

> * Sven Schnelle <svens at stackframe.org> [110503 10:23]:
>> Hi Paul,
>> 
>> Paul Menzel <paulepanter at users.sourceforge.net> writes:
>> 
>> > Am Dienstag, den 03.05.2011, 09:55 +0200 schrieb repository service:
>> >> Author: svens
>> >> Date: Tue May  3 09:55:43 2011
>> >> New Revision: 6554
>> >> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6554
>> >> 
>> >> Log:
>> >> Enable caching for ROM area in model_6ex/cache_as_ram.inc
>> >
>> > it would be great if you could add a small comment to the commit message
>> > if that change improved anything or not.
>> 
>> See my other mail to Stefan and Eric - Stage loading time decreased from
>> 1.9s to around 100ms, which is pretty nice :)
>
> Can you do a new analysis on where the boot time goes now? It would be
> nice to see if there are more optimizations we can do...

Will do. But right now i have the problem that the Keyboard isn't
working on cold boot - seabios is probably started so early that some
hardware parts are not finished with reset or similar things.

Just enabling debug output in coreboot slows down things enough to
make the Keyboard working again.

The original Vendor BIOS talks after around ~1s to the Keyboard
controller, so that's quite different to coreboot (coreboot is handing
over to seabios after ~200ms)

So i want to figure out first if there's some
'i-finished-reset-you-can-talk-to-me' flag, or if that problem is caused
by another reason.

Sven.





From stefan.reinauer at coreboot.org  Tue May  3 22:33:19 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 3 May 2011 22:33:19 +0200
Subject: [coreboot] [commit] r6554 - trunk/src/cpu/intel/model_6ex
In-Reply-To: <87ei4ffu6i.fsf@begreifnix.stackframe.org>
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
Message-ID: <20110503203319.GB3715@coreboot.org>

* Sven Schnelle <svens at stackframe.org> [110503 21:41]:
> Stefan Reinauer <stefan.reinauer at coreboot.org> writes:
> > Can you do a new analysis on where the boot time goes now? It would be
> > nice to see if there are more optimizations we can do...
> 
> Will do. But right now i have the problem that the Keyboard isn't
> working on cold boot - seabios is probably started so early that some
> hardware parts are not finished with reset or similar things.
> 
> Just enabling debug output in coreboot slows down things enough to
> make the Keyboard working again.

Does just putting in a delay of some 100ms fix the issue, too? Do you do
keyboard init in coreboot? Did you do it before?
Just want to make sure there are no side effects coming in through
debugging. However, having an EC/SuperIO that needs more than 200ms to boot up
does not sound too unlikely.

> The original Vendor BIOS talks after around ~1s to the Keyboard
> controller, so that's quite different to coreboot (coreboot is handing
> over to seabios after ~200ms)

Getting through all of coreboot in as little as 200ms? This is totally
awesome! 

> So i want to figure out first if there's some
> 'i-finished-reset-you-can-talk-to-me' flag, or if that problem is caused
> by another reason.

Does the keyboard init code get any type of timeout?

Stefan





From r.marek at assembler.cz  Wed May  4 00:48:50 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 04 May 2011 00:48:50 +0200
Subject: [coreboot] u-boot as payload
In-Reply-To: <4DBC7595.3030909@assembler.cz>
References: <4DBC7595.3030909@assembler.cz>
Message-ID: <4DC08652.8070904@assembler.cz>

Hi again,

Getting rid of u-boot option CONFIG_PCI_PNP fixes the PCI stuff ;)

And I also did an insane hack, which just inject RSDP to right place making the 
u-boot boot system a kernel and system on AMD 64bit platform (Asrock 939A785G)!

Jumping to boot code at fc0013
POST: 0xf8
entry    = 0x00fc0013
lb_start = 0x00100000
lb_size  = 0x00094000
adjust   = 0x2fd5c000
buffer   = 0x2fdc8000
      elf_boot_notes = 0x0011ae90
adjusted_boot_notes = 0x2fe76e90
dram init
type: 16, base 0 size 1000
type: 1, base 1000 size 9f000
type: 1, base c0000 size 2fe30000
type: 16, base 2fef0000 size 110000
RSDP found at 2fef2400type: 2, base 30000000 size 10000000


U-Boot 2011.03-00214-g24b6bc2-dirty (May 03 2011 - 23:58:39)

DRAM Configuration:
Bank #0: 00001000 636 KiB
Bank #1: 000c0000 766.2 MiB
Bank #2: 00000000 0 Bytes
Bank #3: 00000000 0 Bytes
## Unknown flash on Bank 1 - Size = 0x00000000 = 0 MB
## Unknown flash on Bank 2 - Size = 0x00000000 = 0 MB
## Unknown flash on Bank 3 - Size = 0x00000000 = 0 MB
Flash: 0 Bytes
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
IDE:   Bus 0: OK
   Device 0: Model: WDC WD600BB-00CAA1 Firm: 17.07W17 Ser#: WD-WMA8F113824
             Type: Hard Disk
             Capacity: 57241.8 MB = 55.9 GB (117231408 x 512)
Net:   No ethernet found.
Serck Controls eNET
boot > ext2ls ide 0:5 /boot
<DIR>       4096 .
<DIR>       4096 ..
          2063256 bzImage
<DIR>       4096 filo
<DIR>      12288 grub
            22608 memdisk
         71290880 a.tar
<DIR>       4096 a
          1225518 System.map-2.6.26-1-amd64
            85588 config-2.6.26-1-amd64
          1755088 vmlinuz-2.6.26-1-amd64
          2172192 bzImage28
          2236288 bzImage29
          7707622 initrd.img-2.6.26-1-amd64
         33554432 disk
          2414688 vmlinuz-2.6.32-5-amd64
          6802950 initrd.img-2.6.26-1-amd64.bak
           104510 config-2.6.32-5-amd64
           165084 memtest86+.bin
          1660631 System.map-2.6.32-5-amd64
          9446666 initrd.img-2.6.32-5-amd64
           124648 memtest86.bin
           167264 memtest86+_multiboot.bin
boot > setenv bootargs console=ttyS0,9600 root=/dev/sda
boot > ext2load
ext2load - load binary file from a Ext2 filesystem

Usage:
ext2load <interface> <dev[:part]> [addr] [filename] [bytes]
     - load binary file 'filename' from 'dev' on 'interface'
       to address 'addr' from ext2 filesystem
boot > ext2load 0:5 2000000 /boot/bzImage29
** No boot file defined **
boot > ext2load ide 0:5 2000000 /boot/bzImage29
Loading file "/boot/bzImage29" from ide device 0:5 (hda5)
2236288 bytes read
boot > zboot 2000000
Valid Boot Flag
Magic signature found
Setup Size = 0x00002c00
Moving Real-Mode Code to 0x00090000 (11264 bytes)
Using boot protocol version 2.09
Linux kernel version 2.6.29.2 (root at ruiktest) #1 SMP PREEMPT Sat May 2 00:24:59 
CEST 2009
Kernel command line: "console=ttyS0,9600 root=/dev/sda"
Loading bzImage at address 0x00100000 (2225024 bytes)
## Transferring control to Linux (at address 00090000) ...

Starting kernel ...

copy to 7c0 from 101e3d4 size 166
copied 9c666066
Linux version 2.6.29.2 (root at ruiktest) (gcc version 4.3.2 (Debian 4.3.2-1) ) #1 
SMP PREEMPT Sat May 2 00:24:59 CEST 2009
Command line: console=ttyS0,9600 root=/dev/sda
KERNEL supported cpus:
   Intel GenuineIntel
   AMD AuthenticAMD
   Centaur CentaurHauls
BIOS-provided physical RAM map:
  BIOS-e801: 0000000000000000 - 000000000009f000 (usable)
  BIOS-e801: 0000000000100000 - 0000000004000000 (usable)
DMI present.
AMI BIOS detected: BIOS may corrupt low RAM, working around it.
last_pfn = 0x4000 max_arch_pfn = 0x100000000
Scanning 0 areas for low memory corruption
modified physical RAM map:
  modified: 0000000000000000 - 0000000000010000 (reserved)
  modified: 0000000000010000 - 000000000009f000 (usable)
  modified: 0000000000100000 - 0000000004000000 (usable)
init_memory_mapping: 0000000000000000-0000000004000000
last_map_addr: 4000000 end: 4000000
ACPI: RSDP 000F0540, 0014 (r0 CORE  )
ACPI: RSDT 2FEF2424, 0034 (r1 CORE   COREBOOT        0 CORE        0)
ACPI: HPET 2FEF24C8, 0038 (r1 CORE   COREBOOT        0 CORE        0)
ACPI: APIC 2FEF2500, 0054 (r1 CORE   COREBOOT        0 CORE        0)
ACPI: SSDT 2FEF2554, 020C (r2 CORE   DYNADATA       2A CORE       2A)
ACPI: FACP 2FEF3B49, 00F4 (r3 CORE   COREBOOT        0 CORE        0)
...

Rest is attached.

Thanks,
Rudolf


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From r.marek at assembler.cz  Wed May  4 01:24:23 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 04 May 2011 01:24:23 +0200
Subject: [coreboot] u-boot as payload
In-Reply-To: <4DC08652.8070904@assembler.cz>
References: <4DBC7595.3030909@assembler.cz> <4DC08652.8070904@assembler.cz>
Message-ID: <4DC08EA7.3010209@assembler.cz>

Hi

Due to popular demand here is the yet another patch on the top of those two 
previously posted. It bit talks to coreboot tables.

Known issues:

* The memory is still 64MB for linux - this can be fixed by reporting correct 
amount to uboot (bios_*.c) but because there is no e820 just need to report 
continuous memory to the first hole.

* loading stuff just in 1MB wont work because the LMA is set for bios and 
realmode trampoline there, please now load kernel from 2MB or more.

* I had to swap IDE drives because this board has only secondary IDE


Thanks,
Rudolf
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From scott at notabs.org  Wed May  4 08:58:41 2011
From: scott at notabs.org (Scott Duplichan)
Date: Wed, 4 May 2011 01:58:41 -0500
Subject: [coreboot] Update AMD Persimmon project to support Windows 7, XP,
	linux
In-Reply-To: <BANLkTinO1_=pgkJL-aykv8+3fRk6OPx52w@mail.gmail.com>
References: <BANLkTik2J19V5QBrXGUU3nFYWmEwhCVNYw@mail.gmail.com>
	<DF9883C3F0C54A4ABDBAFC086F972F43@m3a78>
	<BANLkTinO1_=pgkJL-aykv8+3fRk6OPx52w@mail.gmail.com>
Message-ID: <13E4E8EFA3284438B44917691092BDA3@m3a78>

Marc Jones wrote:

]> 1) Work around coreboot resource allocation problem that causes
]> overlap of PCIe MMIO space and graphics MMIO space.
]
]Why isn't this covered by the bus resource allocation for MMCONF? I
]think that this should handle the situation. How does the overlap
]happen?

Hello Marc,

I think the short answer is the mmconf range is added to a device that
is skipped by the bus resource allocation code. The mmconf range is
added to APIC_CLUSTER:0, which is not looked at by the resource
allocation code. Here is what I found a while back:

  Why does the current code for handling fixed resources allow the mmconf
  space to get allocated to a PCI device? Function avoid_fixed_resources
  calls function constrain_resources, which recursively searches the
  device tree for fixed io and memory resources. The ioapic fixed memory
  address is found and avoided during the recursive search because this
  southbridge device is below the level where the search starts. On the
  other hand, the mmconf fixed resource is added from the northbridge code,
  and falls under 'APIC_CLUSTER: 0'. This device is not part of the search
  for two reasons. One is that it is not at or below 'pci_domain 0' in the
  device tree. Another reason is that its type is APIC_CLUSTER and not
  PCI_DOMAIN.

The last patch I sent includes a better workaround. To avoid modification
of the resource allocation code, mmconf is moved from e0000000 to f8000000.
This is the solution I attempted originally, but had to set aside until a 
couple of mmio problems were fixed.

Thanks,
Scott 




From svens at stackframe.org  Wed May  4 09:49:50 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Wed, 04 May 2011 09:49:50 +0200
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60 (was: Re:
	[commit] r6554 - trunk/src/cpu/intel/model_6ex)
In-Reply-To: <20110503203319.GB3715@coreboot.org> (Stefan Reinauer's message
	of "Tue\, 3 May 2011 22\:33\:19 +0200")
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
	<20110503203319.GB3715@coreboot.org>
Message-ID: <87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>

Hi Setfan,

Stefan Reinauer <stefan.reinauer at coreboot.org> writes:

> * Sven Schnelle <svens at stackframe.org> [110503 21:41]:
>> Stefan Reinauer <stefan.reinauer at coreboot.org> writes:
>> > Can you do a new analysis on where the boot time goes now? It would be
>> > nice to see if there are more optimizations we can do...
>> 
>> Will do. But right now i have the problem that the Keyboard isn't
>> working on cold boot - seabios is probably started so early that some
>> hardware parts are not finished with reset or similar things.
>> 
>> Just enabling debug output in coreboot slows down things enough to
>> make the Keyboard working again.
>
> Does just putting in a delay of some 100ms fix the issue, too? Do you do
> keyboard init in coreboot? Did you do it before?
> Just want to make sure there are no side effects coming in through
> debugging. However, having an EC/SuperIO that needs more than 200ms to boot up
> does not sound too unlikely.

I do not initialize the Keyboard in coreboot, i'll leave that to
seabios. (Enabling it in coreboot doesn't help either).

>> The original Vendor BIOS talks after around ~1s to the Keyboard
>> controller, so that's quite different to coreboot (coreboot is handing
>> over to seabios after ~200ms)
>
> Getting through all of coreboot in as little as 200ms? This is totally
> awesome! 
>
>> So i want to figure out first if there's some
>> 'i-finished-reset-you-can-talk-to-me' flag, or if that problem is caused
>> by another reason.
>
> Does the keyboard init code get any type of timeout?


Well, i've enabled some debugging in seabios, and it's pretty obvious
what's happening here. SeaBIOS sends command 0xff (which is RESET i
think), and SeabIOS gets 0xfe as response (which is RESEND, but seabios
handles that as NAK, and doesn't resend the command).

You can find the boot log here: 

http://stackframe.org/seriallog-20110503_175245.log

Sven.



From svens at stackframe.org  Wed May  4 10:16:17 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Wed, 04 May 2011 10:16:17 +0200
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60
In-Reply-To: <87aaf2gb1d.fsf_-_@begreifnix.stackframe.org> (Sven Schnelle's
	message of "Wed\, 04 May 2011 09\:49\:50 +0200")
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
	<20110503203319.GB3715@coreboot.org>
	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>
Message-ID: <874o5ag9ta.fsf@begreifnix.stackframe.org>

Sven Schnelle <svens at stackframe.org> writes:

> Hi Setfan,
>
> Stefan Reinauer <stefan.reinauer at coreboot.org> writes:
>
>> * Sven Schnelle <svens at stackframe.org> [110503 21:41]:
>>> Stefan Reinauer <stefan.reinauer at coreboot.org> writes:
>>> > Can you do a new analysis on where the boot time goes now? It would be
>>> > nice to see if there are more optimizations we can do...
>>> 
>>> Will do. But right now i have the problem that the Keyboard isn't
>>> working on cold boot - seabios is probably started so early that some
>>> hardware parts are not finished with reset or similar things.
>>> 
>>> Just enabling debug output in coreboot slows down things enough to
>>> make the Keyboard working again.
>>
>> Does just putting in a delay of some 100ms fix the issue, too? Do you do
>> keyboard init in coreboot? Did you do it before?
>> Just want to make sure there are no side effects coming in through
>> debugging. However, having an EC/SuperIO that needs more than 200ms to boot up
>> does not sound too unlikely.
>
> I do not initialize the Keyboard in coreboot, i'll leave that to
> seabios. (Enabling it in coreboot doesn't help either).
>
>>> The original Vendor BIOS talks after around ~1s to the Keyboard
>>> controller, so that's quite different to coreboot (coreboot is handing
>>> over to seabios after ~200ms)
>>
>> Getting through all of coreboot in as little as 200ms? This is totally
>> awesome! 
>>
>>> So i want to figure out first if there's some
>>> 'i-finished-reset-you-can-talk-to-me' flag, or if that problem is caused
>>> by another reason.
>>
>> Does the keyboard init code get any type of timeout?
>
>
> Well, i've enabled some debugging in seabios, and it's pretty obvious
> what's happening here. SeaBIOS sends command 0xff (which is RESET i
> think), and SeabIOS gets 0xfe as response (which is RESEND, but seabios
> handles that as NAK, and doesn't resend the command).
>
> You can find the boot log here: 
>
> http://stackframe.org/seriallog-20110503_175245.log

I've just modified seabios to resend commands when 0xfe is received as a
quick hack. It makes my keyboard working again. I'm not sure if SeabIOS
should handle 0xfe as RESEND or not - have not monitored much Keyboards,
and don't know wether this has any side effects.

The boot log can be found here:
http://stackframe.org/seriallog-20110504_100837.log

The diff i've made to seabios is: (beware, it's just an ugly hack just for
testing)

diff --git a/src/ps2port.c b/src/ps2port.c
index d1e6d48..a4cd4de 100644
--- a/src/ps2port.c
+++ b/src/ps2port.c
@@ -186,7 +186,8 @@ ps2_recvbyte(int aux, int needack, int timeout)
 static int
 ps2_sendbyte(int aux, u8 command, int timeout)
 {
-    dprintf(7, "ps2_sendbyte aux=%d cmd=%x\n", aux, command);
+resend:
+    dprintf(7, "ps2_sendbyte aux=%d cmd=%x\n", aux, command);
     int ret;
     if (aux)
         ret = i8042_aux_write(command);
@@ -199,6 +200,8 @@ ps2_sendbyte(int aux, u8 command, int timeout)
     ret = ps2_recvbyte(aux, 1, timeout);
     if (ret < 0)
         return ret;
+    if (ret == 0xfe)
+	    goto resend;
     if (ret != PS2_RET_ACK)
         return -1;
 
@@ -232,7 +235,7 @@ __ps2_command(int aux, int command, u8 *param)
     ret = i8042_command(I8042_CMD_CTL_WCTR, &newctr);
     if (ret)
         goto fail;
-
+resend:
     if (command == ATKBD_CMD_RESET_BAT) {
         // Reset is special wrt timeouts and bytes received.
 
@@ -243,10 +246,14 @@ __ps2_command(int aux, int command, u8 *param)
 
         // Receive parameters.
         ret = ps2_recvbyte(aux, 0, 4000);
+	if (ret == 0xfe)
+		goto resend;
         if (ret < 0)
             goto fail;
         param[0] = ret;
         ret = ps2_recvbyte(aux, 0, 100);
+	if (ret == 0xfe)
+		goto resend;
         if (ret < 0)
             // Some devices only respond with one byte on reset.
             ret = 0;
@@ -261,6 +268,8 @@ __ps2_command(int aux, int command, u8 *param)
 
         // Receive parameters.
         ret = ps2_recvbyte(aux, 0, 500);
+	if (ret == 0xfe)
+	    goto resend;
         if (ret < 0)
             goto fail;
         param[0] = ret;
@@ -268,6 +277,8 @@ __ps2_command(int aux, int command, u8 *param)
             || ret == 0x60 || ret == 0x47) {
             // These ids (keyboards) return two bytes.
             ret = ps2_recvbyte(aux, 0, 500);
+	    if (ret == 0xfe)
+		goto resend;
             if (ret < 0)
                 goto fail;
             param[1] = ret;
@@ -291,6 +302,8 @@ __ps2_command(int aux, int command, u8 *param)
         // Receive parameters (if any).
         for (i = 0; i < receive; i++) {
             ret = ps2_recvbyte(aux, 0, 500);
+	    if (ret == 0xfe)
+		    goto resend;
             if (ret < 0)
                 goto fail;
             param[i] = ret;



From r.marek at assembler.cz  Wed May  4 10:54:15 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 04 May 2011 10:54:15 +0200
Subject: [coreboot] u-boot on x86 reloaded
Message-ID: <4DC11437.9090405@assembler.cz>

Hello,

I was asked to post it here too.

I would like to announce that I was able to boot Linux using u-boot on AMD64 
motherboard Asrock 939A785G. The development was done on QEMU.

How does it work?

Coreboot does the complete HW init including memory setup PCI etc. When finishes 
it loads u-boot.

Coreboot is free software replacement for BIOS, but unlike BIOS it only does the 
hardware init (and ACPI). A payload needs to be executed which does something 
useful for the user (like a linux kernel, SeaBIOS, FILO, grub etc)

You can read more about coreboot on http://coreboot.org

How the porting was done is described here:

http://blogs.coreboot.org/blog/2011/04/30/u-boot-as-coreboot-payload/

http://www.coreboot.org/pipermail/coreboot/2011-April/064877.html
http://www.coreboot.org/pipermail/coreboot/2011-May/064914.html
http://www.coreboot.org/pipermail/coreboot/2011-May/064915.html

And boot log http://assembler.cz/minicom42.txt

This project started "just for fun" or "because I can". Maybe there are some 
real uses. If you can think of some, please let me know.

Anyone with more free time could work on this?

I'm not subscribed, please cc me. I'm ccing coreboot mailing list too.

Thanks,
Rudolf




From r.marek at assembler.cz  Wed May  4 14:37:59 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 04 May 2011 14:37:59 +0200
Subject: [coreboot] [U-Boot] u-boot on x86 reloaded
In-Reply-To: <4DC13A12.5080509@gmail.com>
References: <4DC11437.9090405@assembler.cz> <4DC13A12.5080509@gmail.com>
Message-ID: <4DC148A7.4050007@assembler.cz>

Hello all,

> Excellent - U-Boot on a new x86 board

Yes and in general any supported coreboot board.

> This is one of the ways I was thinking of getting U-Boot running on
> mainstream PC boards. The other is to create U-Boot as a GRUB payload.
> Either way, it's all about getting the SDRAM initialised

Not only, also HyperTransport, complex PCI stuff, power mngmt etc, lots of lots 
of stuff.

> Well, that's why I started too - kudos for the effort

Thanks.

>> Anyone with more free time could work on this?
>
> Well I did have someone else contact me about doing exactly as you have
> done (I have Bcc'd him in case he is interested)
>
> As the U-Boot x86 maintainer, I am extremely interested in going further
> with this and am keen to help get your work mainlined

Ok

> OK, a few little points which may help answer some questions you didn't
> realise you even had ;)
>
>   - The build warnings and errors you incurred are probably fixed in
> mainline (x86 is a bit of a forgotten cousin which gets broken when global
> patches are made to Makefile, linker scripts etc). If you still have
> problems compiling the latest U-Boot git head, please post them to the
> mailing list and I'll sort them out ASAP

The links to the coreboot mailing list contain some patches.

>   - The x86 port of U-Boot was the first to implement the (now pretty much
> standard) relocation scheme. Understanding it is a Very Good Idea(tm)
>   - SYS_TEXT_BASE=0?19000000 is very specific to the eNET - It is the start
> of non-volatile (battery backed) SRAM. We can run from SRAM prior to
> initialising SDRAM, so I use it as an alternative to Flash for testing new
> builds (reset ->  TFTP new image to 0x19000000 ->  go 19000000)

Yes I move that to 16MB boundary to load it just into RAM. u-boot ELF can be 
loaded from coreboot, where it is stored compressed.

>   - When launching U-Boot as a payload from Coreboot, you really don't need
> to worry about what is at the end of the image (reset vector and jump to
> protected mode). All the fun begins at the first byte of u-boot.bin which
> is the first line of code in start.S

I think it jumps to _start which is 32 bit entry point. The coreboot is in flat 
mode 32bit.

>   - CONFIG_SYS_INIT_SP_ADDR is a temporary stack pointer which is used
> during the relocation of U-Boot from ROM (Flash) into SDRAM. Typically the
> CPU's Cache-As-RAM (CAR) capability is used. However, if SDRAM is already
> initialised, you can set CONFIG_SYS_INIT_SP_ADDR to anywhere in SDRAM that
> will not get clobbered by the relocation

Yes I set it to 256KB boundary.

>   - I'm in the middle of re-writing the entire real-mode switch code and
> real-mode support in U-Boot. The new code allows you to write real-mode
> code in C - I even have the Linux real-mode printf ported :) This will make
> writing your own 'BIOS' code for your board a lot easier

Well I liked here that there is no BIOS at all. The SeaBIOS is the layer used by 
coreboot to have full legacy BIOS stuff. This is used by KVM/Qenu too.

The coreboot can do VGA init (it has kind of BIOS emulation stuff for this) so 
at the end VGA + keyboard could be possible.

I guess if u-boot is for linux loading, then we need to add e820 stuff to have 
support for over 4GB of memory.

>   - Ultimately, I would like to bypass Linux's real-mode stub (like GRUB)
> and ditch the real-mode code (for the purpose of booting Linux)

This is done in FILO. Check http://www.coreboot.org/FILO I guess it can be just 
ported. The coreboot will provide the memory map and this is how the FILO is 
doing that, just  transforming it and passing it directly to kernel.

> I would really like to see some U-Boot patches on the mailing list -
> Technically U-Boot is meant to be a stand-alone and self-sufficient, but I
> think for x86 there is merit in creating board configuration that gets
> boot-strapped by Coreboot (we just need to make sure the documentation is
> up-to-scratch)

The patches are just now on coreboot mailing list. It is just a hack, because 
there are places which needs to be fixed, the computation of place for the 
realmode and bios sections needs to be fixed.  I added the coreboot as a board 
and subarchitecture.

What is specific is that we will need to copy "MPtable" "PIR" and "RSDP" pointer 
to F-segment just after the bios section. The memory map can be read out of 
coreboot tables stored in high mem. Also a PCI mem stuff should be fixed in u-boot.

Also if we get rid of the .bios and .realmode section then the problem that 
those two sections are not relocated to end of memory disappears.

> Looking forward to moving this forward

Good. Please check the patches on coreboot ml and feel free to join #coreboot 
channel. I'm in both now as "ruik".

Thanks,
Rudolf



From marcj303 at gmail.com  Wed May  4 18:12:07 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 4 May 2011 10:12:07 -0600
Subject: [coreboot] AMD Persimmon update
In-Reply-To: <B0FDAE3158B74F6497F657AD6D0408C4@m3a78>
References: <AcwHFoUqRoIXoGvWQa+u/zj10boGfw==>
	<B0FDAE3158B74F6497F657AD6D0408C4@m3a78>
Message-ID: <BANLkTinMuJUPs1SCFoTkL7NEcrewsOyQzA@mail.gmail.com>

On Sat, Apr 30, 2011 at 3:10 AM, Scott Duplichan <scott at notabs.org> wrote:
> The attached changes for the AMD Persimmon board improve OS support and reduce boot time.
> DOS boot from SSD drive is 640 ms. Windows 7, Windows XP, and linux can install from
> DVD and boot from hard disk.
>
> Signed-off-by: Scott Duplichan <scott at notabs.org>
>
> Thanks,
> Scott

H Scott,

Thanks for all the patches. I missed this while I was on the road. I
will start reviewing these over the next few days. Maybe we can get
some others to help review and test too.

Marc




-- 
http://se-eng.com



From graeme.russ at gmail.com  Wed May  4 13:35:46 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Wed, 04 May 2011 21:35:46 +1000
Subject: [coreboot] [U-Boot] u-boot on x86 reloaded
In-Reply-To: <4DC11437.9090405@assembler.cz>
References: <4DC11437.9090405@assembler.cz>
Message-ID: <4DC13A12.5080509@gmail.com>

On 04/05/11 18:54, Rudolf Marek wrote:
> Hello,
> 
> I was asked to post it here too.
> 
> I would like to announce that I was able to boot Linux using u-boot on AMD64 
> motherboard Asrock 939A785G. The development was done on QEMU.

Excellent - U-Boot on a new x86 board

> 
> How does it work?
> 
> Coreboot does the complete HW init including memory setup PCI etc. When finishes 
> it loads u-boot.

This is one of the ways I was thinking of getting U-Boot running on
mainstream PC boards. The other is to create U-Boot as a GRUB payload.
Either way, it's all about getting the SDRAM initialised

[Snip]

> How the porting was done is described here:
> 
> http://blogs.coreboot.org/blog/2011/04/30/u-boot-as-coreboot-payload/

Excellent write-up - Thanks!

> 
> http://www.coreboot.org/pipermail/coreboot/2011-April/064877.html
> http://www.coreboot.org/pipermail/coreboot/2011-May/064914.html
> http://www.coreboot.org/pipermail/coreboot/2011-May/064915.html
> 
> And boot log http://assembler.cz/minicom42.txt
> 
> This project started "just for fun" or "because I can". Maybe there are some 
> real uses. If you can think of some, please let me know.

Well, that's why I started too - kudos for the effort

> 
> Anyone with more free time could work on this?

Well I did have someone else contact me about doing exactly as you have
done (I have Bcc'd him in case he is interested)

As the U-Boot x86 maintainer, I am extremely interested in going further
with this and am keen to help get your work mainlined

> 
> I'm not subscribed, please cc me. I'm ccing coreboot mailing list too.
> 

OK, a few little points which may help answer some questions you didn't
realise you even had ;)

 - The build warnings and errors you incurred are probably fixed in
mainline (x86 is a bit of a forgotten cousin which gets broken when global
patches are made to Makefile, linker scripts etc). If you still have
problems compiling the latest U-Boot git head, please post them to the
mailing list and I'll sort them out ASAP
 - The x86 port of U-Boot was the first to implement the (now pretty much
standard) relocation scheme. Understanding it is a Very Good Idea(tm)
 - SYS_TEXT_BASE=0?19000000 is very specific to the eNET - It is the start
of non-volatile (battery backed) SRAM. We can run from SRAM prior to
initialising SDRAM, so I use it as an alternative to Flash for testing new
builds (reset -> TFTP new image to 0x19000000 -> go 19000000)
 - When launching U-Boot as a payload from Coreboot, you really don't need
to worry about what is at the end of the image (reset vector and jump to
protected mode). All the fun begins at the first byte of u-boot.bin which
is the first line of code in start.S
 - CONFIG_SYS_INIT_SP_ADDR is a temporary stack pointer which is used
during the relocation of U-Boot from ROM (Flash) into SDRAM. Typically the
CPU's Cache-As-RAM (CAR) capability is used. However, if SDRAM is already
initialised, you can set CONFIG_SYS_INIT_SP_ADDR to anywhere in SDRAM that
will not get clobbered by the relocation
 - I'm in the middle of re-writing the entire real-mode switch code and
real-mode support in U-Boot. The new code allows you to write real-mode
code in C - I even have the Linux real-mode printf ported :) This will make
writing your own 'BIOS' code for your board a lot easier
 - Ultimately, I would like to bypass Linux's real-mode stub (like GRUB)
and ditch the real-mode code (for the purpose of booting Linux)

I would really like to see some U-Boot patches on the mailing list -
Technically U-Boot is meant to be a stand-alone and self-sufficient, but I
think for x86 there is merit in creating board configuration that gets
boot-strapped by Coreboot (we just need to make sure the documentation is
up-to-scratch)

Looking forward to moving this forward

Regards,

Graeme



From nrubinstein at proformatique.com  Thu May  5 17:44:40 2011
From: nrubinstein at proformatique.com (Noe Rubinstein)
Date: Thu, 5 May 2011 17:44:40 +0200
Subject: [coreboot] [PATCH] replace while with do; while to avoid repetition
Message-ID: <20110505154440.GA17008@xivo-clients.proformatique.com>

Cosmetic only; replaces some 'while' loops with 'do; while' loops to
avoid repetition.

Replacement performed by the Ruby expression:
t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
	"\\1do \\2\n\\1\\3;")

Signed-off-by: Noe Rubinstein <nrubinstein at proformatique.com>
---
 src/northbridge/intel/e7520/raminit.c         |   55 +++++++++--------------
 src/northbridge/intel/e7525/raminit.c         |   55 +++++++++--------------
 src/northbridge/intel/i3100/raminit.c         |   55 +++++++++--------------
 src/northbridge/intel/i3100/raminit_ep80579.c |   60 ++++++++++---------------
 4 files changed, 90 insertions(+), 135 deletions(-)

diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 6eed196..499698e 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -1128,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 		write32(BAR+0x100, (0x83000000 | (i<<20)));
 
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 
 	}
 
@@ -1139,9 +1138,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs++) {
 		write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1152,9 +1150,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* EMRS dll's enabled */
@@ -1166,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000001);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	/* MRS reset dll's */
 	do_delay();
@@ -1187,9 +1183,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, mode_reg);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1202,25 +1197,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do 2 refreshes */
 	do_delay();
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	/* for good luck do 6 more */
@@ -1253,9 +1245,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do only if DDR2  EMRS dll's enabled */
@@ -1264,9 +1255,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 for(cs=0;cs<8;cs++) {
                         write32(BAR+DCALADDR, (0x0b940001));
                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-			data32 = read32(BAR+DCALCSR);
-			while(data32 & 0x80000000)
-				data32 = read32(BAR+DCALCSR);
+			do data32 = read32(BAR+DCALCSR);
+			while(data32 & 0x80000000);
                 }
         }
 
@@ -1310,9 +1300,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Bring memory subsystem on line */
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index aabe8cf..6eb9956 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -1104,9 +1104,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 		write32(BAR+0x100, (0x83000000 | (i<<20)));
 
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 
 	}
 
@@ -1115,9 +1114,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs++) {
 		write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1128,9 +1126,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* EMRS dll's enabled */
@@ -1142,9 +1139,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000001);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	/* MRS reset dll's */
 	do_delay();
@@ -1163,9 +1159,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, mode_reg);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1178,25 +1173,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do 2 refreshes */
 	do_delay();
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	/* for good luck do 6 more */
@@ -1229,9 +1221,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do only if DDR2  EMRS dll's enabled */
@@ -1240,9 +1231,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 for(cs=0;cs<8;cs++) {
                         write32(BAR+DCALADDR, (0x0b940001));
                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-			data32 = read32(BAR+DCALCSR);
-			while(data32 & 0x80000000)
-				data32 = read32(BAR+DCALCSR);
+			do data32 = read32(BAR+DCALCSR);
+			while(data32 & 0x80000000);
                 }
         }
 
@@ -1283,9 +1273,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Bring memory subsystem on line */
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 86e610f..ced3de1 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -1020,9 +1020,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));
 		write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
 
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Apply NOP */
@@ -1030,9 +1029,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1040,9 +1038,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, 0x04000000);
 		write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* EMRS dll's enabled */
@@ -1051,9 +1048,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		/* fixme hard code AL additive latency */
 		write32(MCBAR+DCALADDR, 0x0b940001);
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	/* MRS reset dll's */
 	do_delay();
@@ -1064,9 +1060,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, mode_reg);
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1076,25 +1071,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, 0x04000000);
 		write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do 2 refreshes */
 	do_delay();
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	/* for good luck do 6 more */
@@ -1127,9 +1119,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do only if DDR2  EMRS dll's enabled */
@@ -1137,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, (0x0b940001));
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	do_delay();
@@ -1173,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Bring memory subsystem on line */
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 8967594..de3ffce 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -534,9 +534,8 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 }
 
@@ -603,9 +602,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		udelay(16);
 		write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
 		write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* Apply NOP */
@@ -615,9 +613,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug_hex8(cs);
 		print_debug("\n");
 		write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* Precharge all banks */
@@ -628,9 +625,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, 0x04000000);
 		write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* EMRS: Enable DLLs, set OCD calibration mode to default */
@@ -641,9 +637,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 	/* MRS: Reset DLLs */
 	udelay(16);
@@ -653,9 +648,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, mode_reg);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* Precharge all banks */
@@ -666,9 +660,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, 0x04000000);
 		write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* Do 2 refreshes */
@@ -679,9 +672,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 			print_debug_hex8(cs);
 			print_debug("\n");
 			write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
-			data32 = read32(BAR+DCALCSR);
-			while (data32 & 0x80000000)
-				data32 = read32(BAR+DCALCSR);
+			do data32 = read32(BAR+DCALCSR);
+			while (data32 & 0x80000000);
 		}
 	}
 
@@ -693,9 +685,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* EMRS: Enable DLLs */
@@ -706,9 +697,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
         }
 
 	udelay(16);
@@ -729,9 +719,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug_hex8(cs);
 		print_debug("\n");
 		write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	dump_dcal_regs();
@@ -756,9 +745,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug_hex8(cs);
 		print_debug("\n");
 		write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
-		data32 = read32(BAR+MBCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+MBCSR);
+		do data32 = read32(BAR+MBCSR);
+		while (data32 & 0x80000000);
 		if (data32 & 0x40000000)
 			print_debug("failed!\n");
 	}
-- 
No? Rubinstein
Proformatique (groupe Avencall) - XiVO IPBX OpenHardware
10 bis, rue Lucien VOILIN - 92800 Puteaux
T?l. : +33 (0)1 41 38 99 60 ext 123
Fax. : +33 (0)1 41 38 99 70




From Frank.Vibrans at amd.com  Thu May  5 18:27:49 2011
From: Frank.Vibrans at amd.com (Vibrans, Frank)
Date: Thu, 5 May 2011 11:27:49 -0500
Subject: [coreboot] A patch to add VOID to empty parameter lists to get rid
 of some build warnings.
Message-ID: <276EC11373289744A112A8FE6675506701ABDC9063@SAUSEXMBP01.amd.com>

Adds VOID to empty parameter lists to get rid of some build warnings.

This change modifies a collection of files by adding the VOID parameter
to empty parameter lists to cut down on the number of warnings produced
when compiling the AMD Agesa code.  This should cut down the number of
warnings by about 1100 each for rom- and ramstage.

Signed-off by Frank Vibrans <frank.vibrans at amd.com>

--

This patch is compressed to retain line endings.  My Windows environment has the tendency to change them.
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From svn at coreboot.org  Thu May  5 18:45:36 2011
From: svn at coreboot.org (repository service)
Date: Thu, 05 May 2011 18:45:36 +0200
Subject: [coreboot] [commit] r6555 - in trunk: .
	src/vendorcode/amd/agesa/Include
Message-ID: <E1QI1gG-0004C2-RH@ra.coresystems.de>

Author: mjones
Date: Thu May  5 18:45:36 2011
New Revision: 6555
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6555

Log:
Remove AMD Agesa requirement for standard include files

This change modifies Makefile.inc to add the -nostdinc flag to the default
CFLAGS value and removes the test for non-AMD Agesa builds.  Other code is
added to the gcc-intrin.h file in the Agesa Include folder to make the
requirement for the standard includes obsolete from the Agesa perspective.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/Makefile.inc
   trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h

Modified: trunk/Makefile.inc
==============================================================================
--- trunk/Makefile.inc	Tue May  3 09:55:43 2011	(r6554)
+++ trunk/Makefile.inc	Thu May  5 18:45:36 2011	(r6555)
@@ -106,16 +106,13 @@
 # abspath is a workaround for romcc
 INCLUDES += -include $(abspath $(obj)/config.h)
 
-CFLAGS = $(INCLUDES) -Os -pipe -g
+CFLAGS = $(INCLUDES) -Os -pipe -g -nostdinc
 CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
 CFLAGS += -Wstrict-aliasing -Wshadow
 ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y)
 CFLAGS += -Werror
 endif
-ifneq ($(CONFIG_AMD_AGESA),y)
-CFLAGS += -nostdinc 
-endif
 CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 
 additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/options

Modified: trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h	Tue May  3 09:55:43 2011	(r6554)
+++ trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h	Thu May  5 18:45:36 2011	(r6555)
@@ -27,8 +27,6 @@
  */
  
 #if defined (__GNUC__)
-#include <pmmintrin.h>
-
 
 /* I/O intrin functions.  */
 static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
@@ -558,6 +556,10 @@
   return value;
 }
 
+#ifdef __SSE3__
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+
 static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
 {
   __asm__(".byte 0x64"); // fs prefix
@@ -567,9 +569,10 @@
 static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
 {
   __m128i data;
-  data = _mm_lddqu_si128 (__B);
+  data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
   _mm_stream_si128_fs2 (__A, data);
 }
+#endif
 
 static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
 {
@@ -577,6 +580,16 @@
   __builtin_ia32_clflush (__A);
 }
 
+static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
+{
+  __builtin_ia32_mfence ();
+}
+
+static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
+{
+  __builtin_ia32_sfence ();
+}
+
 static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count)
 {
    __asm__ __volatile__ (



From svn at coreboot.org  Thu May  5 18:49:12 2011
From: svn at coreboot.org (repository service)
Date: Thu, 05 May 2011 18:49:12 +0200
Subject: [coreboot] [commit] r6556 - in trunk/src/vendorcode/amd/agesa/Proc:
	CPU Common GNB/Nb/Family GNB/Nb/Family/0x14 Mem Mem/Main Mem/Tech
Message-ID: <E1QI1jk-0000ea-Q9@ra.coresystems.de>

Author: mjones
Date: Thu May  5 18:49:11 2011
New Revision: 6556
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6556

Log:
Adds VOID to empty parameter lists to get rid of some build warnings.

This change modifies a collection of files by adding the VOID parameter
to empty parameter lists to cut down on the number of warnings produced
when compiling the AMD Agesa code.  This should cut down the number of
warnings by about 1100 each for rom- and ramstage.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h
   trunk/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c
   trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c
   trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h
   trunk/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c
   trunk/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c
   trunk/src/vendorcode/amd/agesa/Proc/Mem/mm.h
   trunk/src/vendorcode/amd/agesa/Proc/Mem/mn.h
   trunk/src/vendorcode/amd/agesa/Proc/Mem/mt.h
   trunk/src/vendorcode/amd/agesa/Proc/Mem/mu.h

Modified: trunk/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h	Thu May  5 18:49:11 2011	(r6556)
@@ -151,14 +151,14 @@
  *
  */
 UINT32
-GetPlatformNumberOfSockets ();
+GetPlatformNumberOfSockets (VOID);
 
 /**
  * Get the number of Modules to check presence in each Processor.
  *
  */
 UINT32
-GetPlatformNumberOfModules ();
+GetPlatformNumberOfModules (VOID);
 
 BOOLEAN
 IsProcessorPresent (

Modified: trunk/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c	Thu May  5 18:49:11 2011	(r6556)
@@ -70,7 +70,7 @@
 * @retval TRUE  Default case, no special action
 */
 BOOLEAN
-CommonReturnTrue ()
+CommonReturnTrue (VOID)
 {
   return TRUE;
 }
@@ -83,7 +83,7 @@
 * @retval FALSE  Default case, no special action
 */
 BOOLEAN
-CommonReturnFalse ()
+CommonReturnFalse (VOID)
 {
   return FALSE;
 }
@@ -96,7 +96,7 @@
  * @retval zero    None, or only case zero.
  */
 UINT8
-CommonReturnZero8 ()
+CommonReturnZero8 (VOID)
 {
   return 0;
 }
@@ -109,7 +109,7 @@
  * @retval zero    None, or only case zero.
  */
 UINT32
-CommonReturnZero32 ()
+CommonReturnZero32 (VOID)
 {
   return 0;
 }
@@ -122,7 +122,7 @@
  * @retval zero    None, or only case zero.
  */
 UINT64
-CommonReturnZero64 ()
+CommonReturnZero64 (VOID)
 {
   return 0;
 }
@@ -134,7 +134,7 @@
  * @retval NULL    pointer to nothing
  */
 VOID *
-CommonReturnNULL ()
+CommonReturnNULL (VOID)
 {
   return NULL;
 }
@@ -146,7 +146,7 @@
 * @retval AGESA_SUCCESS Success.
 */
 AGESA_STATUS
-CommonReturnAgesaSuccess ()
+CommonReturnAgesaSuccess (VOID)
 {
   return AGESA_SUCCESS;
 }
@@ -158,7 +158,7 @@
  *
  */
 VOID
-CommonVoid ()
+CommonVoid (VOID)
 {
 }
 
@@ -168,7 +168,7 @@
  *
  */
 VOID
-CommonAssert ()
+CommonAssert (VOID)
 {
   ASSERT (FALSE);
 }

Modified: trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c	Thu May  5 18:49:11 2011	(r6556)
@@ -115,6 +115,7 @@
 
 FUSE_TABLE*
 NbFmGetFuseTranslationTable (
+  VOID
   )
 {
   return  &FuseTable;

Modified: trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h	Thu May  5 18:49:11 2011	(r6556)
@@ -86,6 +86,7 @@
 
 FUSE_TABLE*
 NbFmGetFuseTranslationTable (
+  VOID
   );
 
 VOID

Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c	Thu May  5 18:49:11 2011	(r6556)
@@ -89,7 +89,7 @@
  */
 
 VOID
-memDefRet ()
+memDefRet (VOID)
 {
 }
 
@@ -100,7 +100,7 @@
  *
  */
 BOOLEAN
-memDefTrue ()
+memDefTrue (VOID)
 {
   return TRUE;
 }
@@ -112,7 +112,7 @@
  *
  */
 BOOLEAN
-memDefFalse ()
+memDefFalse (VOID)
 {
   return FALSE;
 }
@@ -137,7 +137,7 @@
  *
  */
 AGESA_STATUS
-memDefRetSuccess ()
+memDefRetSuccess (VOID)
 {
   return AGESA_SUCCESS;
 }

Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c	Thu May  5 18:49:11 2011	(r6556)
@@ -150,11 +150,11 @@
 
 UINT8
 STATIC
-MemTMaxByteLanesByte ();
+MemTMaxByteLanesByte (VOID);
 
 UINT8
 STATIC
-MemTDlyTableWidthByte ();
+MemTDlyTableWidthByte (VOID);
 
 VOID
 STATIC
@@ -689,7 +689,7 @@
 
 UINT8
 STATIC
-MemTMaxByteLanesByte ()
+MemTMaxByteLanesByte (VOID)
 {
   return MAX_BYTELANES;
 }
@@ -704,7 +704,7 @@
 
 UINT8
 STATIC
-MemTDlyTableWidthByte ()
+MemTDlyTableWidthByte (VOID)
 {
   return MAX_DELAYS;
 }

Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/mm.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/Mem/mm.h	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/Mem/mm.h	Thu May  5 18:49:11 2011	(r6556)
@@ -984,10 +984,10 @@
   );
 
 VOID
-MemRecDefRet ();
+MemRecDefRet (VOID);
 
 BOOLEAN
-MemRecDefTrue ();
+MemRecDefTrue (VOID);
 
 VOID
 SetMemRecError (
@@ -996,7 +996,7 @@
   );
 
 AGESA_STATUS
-memDefRetSuccess ();
+memDefRetSuccess (VOID);
 
 #endif  /* _MM_H_ */
 

Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/mn.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/Mem/mn.h	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/Mem/mn.h	Thu May  5 18:49:11 2011	(r6556)
@@ -548,7 +548,7 @@
   VOID (*Feature) (struct _MEM_NB_BLOCK *NBPtr); ///< Feature support.
   UINT8 (*GetSocketRelativeChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Dct, UINT8 Channel); ///< Get channel number relative to a socket.
   VOID (*SetDramOdtRec) (struct _MEM_NB_BLOCK *NBPtr, ODT_MODE OdtMode, UINT8 ChipSelect, UINT8 TargetCS); ///< Set Dram ODT.
-  UINT32 (*GetSysAddrRec) (); ///< Get system address for training.
+  UINT32 (*GetSysAddrRec) (VOID); ///< Get system address for training.
   VOID (*SwitchNodeRec) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< Switch to current node.
   VOID (*TechBlockSwitch) (struct _MEM_NB_BLOCK *NBPtr); ///< Selects appropriate Tech functions for the NB.
   VOID (*SetEccSymbolSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Set Ecc Symbol Size.
@@ -979,6 +979,7 @@
 
 UINT32
 MemRecNGetMCTSysAddrNb (
+  VOID
   );
 
 UINT32

Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/mt.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/Mem/mt.h	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/Mem/mt.h	Thu May  5 18:49:11 2011	(r6556)
@@ -206,11 +206,11 @@
   VOID (*SkipChipSelPass1) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
   VOID (*SkipChipSelPass2) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
   UINT16 (*CompareTestPatternFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< compare training pattern with filter.
-  UINT8 (*MaxByteLanes) (); ///< return maximum number of bytelanes.
+  UINT8 (*MaxByteLanes) (VOID); ///< return maximum number of bytelanes.
   VOID (*SetDQSDelayCSR) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 Dly); ///< Set CSR.
   VOID (*DQSWindowSave) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 DlyMin, UINT8 DlyMax); ///< programs the trained DQS delay for the specified byte lane and stores its DQS window for reference.
   BOOLEAN (*FindMaxDlyForMaxRdLat) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< Find maximum receiver enable delay value.
-  UINT8 (*DlyTableWidth) (); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes.
+  UINT8 (*DlyTableWidth) (VOID); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes.
   UINT16 (*Compare1ClPatternOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT8 Side, UINT8 Receiver, BOOLEAN Side1En); ///< Compare training pattern of 1 cache line.
   VOID (*LoadRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value.
   VOID (*SetRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value.

Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/mu.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Proc/Mem/mu.h	Thu May  5 18:45:36 2011	(r6555)
+++ trunk/src/vendorcode/amd/agesa/Proc/Mem/mu.h	Thu May  5 18:49:11 2011	(r6556)
@@ -230,6 +230,7 @@
 
 VOID
 MemUMFenceInstr (
+  VOID
   );
 
 #endif  /* _MU_H_ */



From Frank.Vibrans at amd.com  Thu May  5 18:25:11 2011
From: Frank.Vibrans at amd.com (Vibrans, Frank)
Date: Thu, 5 May 2011 11:25:11 -0500
Subject: [coreboot] A patch to remove AMD Agesa requirement for standard
	include files
Message-ID: <276EC11373289744A112A8FE6675506701ABDC9050@SAUSEXMBP01.amd.com>

Remove AMD Agesa requirement for standard include files

This change modifies Makefile.inc to add the -nostdinc flag to the default
CFLAGS value and removes the test for non-AMD Agesa builds.  Other code is
added to the gcc-intrin.h file in the Agesa Include folder to make the
requirement for the standard includes obsolete from the Agesa perspective.

Signed-off by Frank Vibrans <frank.vibrans at amd.com>

--

This patch is compressed to retain Linux line endings.
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From marc.jones at se-eng.com  Thu May  5 18:50:10 2011
From: marc.jones at se-eng.com (Marc Jones)
Date: Thu, 05 May 2011 10:50:10 -0600
Subject: [coreboot] A patch to add VOID to empty parameter lists to get
 rid of some build warnings.
In-Reply-To: <276EC11373289744A112A8FE6675506701ABDC9063@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE6675506701ABDC9063@SAUSEXMBP01.amd.com>
Message-ID: <4DC2D542.5070400@se-eng.com>

On 05/05/2011 10:27 AM, Vibrans, Frank wrote:
>
> *Adds VOID to empty parameter lists to get rid of some build warnings.*
>
> **
>
> *This change modifies a collection of files by adding the VOID parameter*
>
> *to empty parameter lists to cut down on the number of warnings produced*
>
> *when compiling the AMD Agesa code.  This should cut down the number of*
>
> *warnings by about 1100 each for rom- and ramstage.*
>
> **
>
> *Signed-off by Frank Vibrans <frank.vibrans at amd.com>*
>
> **
>
> --
>
> This patch is compressed to retain line endings.  My Windows 
> environment has the tendency to change them.
>
Acked-by: Marc Jones <marcj303 at gmail.com>

r6556
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From marc.jones at se-eng.com  Thu May  5 18:46:49 2011
From: marc.jones at se-eng.com (Marc Jones)
Date: Thu, 05 May 2011 10:46:49 -0600
Subject: [coreboot] A patch to remove AMD Agesa requirement for standard
 include files
In-Reply-To: <276EC11373289744A112A8FE6675506701ABDC9050@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE6675506701ABDC9050@SAUSEXMBP01.amd.com>
Message-ID: <4DC2D479.9000307@se-eng.com>

On 05/05/2011 10:25 AM, Vibrans, Frank wrote:
>
> *Remove AMD Agesa requirement for standard include files*
>
> **
>
> *This change modifies Makefile.inc to add the -nostdinc flag to the 
> default*
>
> *CFLAGS value and removes the test for non-AMD Agesa builds.  Other 
> code is*
>
> *added to the gcc-intrin.h file in the Agesa Include folder to make the*
>
> *requirement for the standard includes obsolete from the Agesa 
> perspective.*
>
> **
>
> *Signed-off by Frank Vibrans <frank.vibrans at amd.com>*
>
> **
>
> --
>
> This patch is compressed to retain Linux line endings.
>
Acked-by: Marc Jones <marcj303 at gmail.com>
r6555

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From Kerry.She at amd.com  Fri May  6 04:33:46 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Fri, 6 May 2011 10:33:46 +0800
Subject: [coreboot] [Patch 2/4] compile sb800 code without agesav5
In-Reply-To: <BANLkTikm5Mh98q4=tjiYNWkxR_FuvM-SUQ@mail.gmail.com>
References: <F53A09371FB723428826B442A4B20A4105C2AB91@sbjgexmb1.amd.com>
	<20110422195822.GB13117@coreboot.org>
	<BANLkTikm5Mh98q4=tjiYNWkxR_FuvM-SUQ@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4105F5C765@sbjgexmb1.amd.com>

Hello,


> -----Original Message-----
> From: Marc Jones [mailto:marcj303 at gmail.com]
> Sent: Friday, May 06, 2011 8:52 AM
> To: Stefan Reinauer
> Cc: She, Kerry; coreboot at coreboot.org
> Subject: Re: [coreboot] [Patch 2/4] compile sb800 code without agesav5
> 
> On Fri, Apr 22, 2011 at 1:58 PM, Stefan Reinauer
> <stefan.reinauer at coreboot.org> wrote:
> > * She, Kerry <Kerry.She at amd.com> [110422 05:12]:
> >> Signed-off-by: Kerry She <Kerry.she at amd.com>
> >>
> >> SB800 CIMX code can share the AGESA V5 lib code,
> >> some platform only use sb800 cimx code, not use AGESA v5 code,
> >> compile the sb800 cimx and AGESA v5 lib code.
> >>
> >> Signed-off-by: Kerry She <Kerry.she at amd.com>
> >>
> >> Index: Makefile.inc
> >> ===================================================================
> >> --- Makefile.inc ? ? ? ?(revision 6481)
> >> +++ Makefile.inc ? ? ? ?(working copy)
> >> @@ -110,7 +110,9 @@
> >> ?CFLAGS += -Werror
> >> ?endif
> >> ?ifneq ($(CONFIG_AMD_AGESA),y)
> >> -CFLAGS += -nostdinc
> >> + ifneq ($(CONFIG_AMD_CIMX_SB800),y)
> >> + ?CFLAGS += -nostdinc
> >> + endif
> >> ?endif
> >> ?CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-
> pointer
> >>
> >
> > Why is that needed. Can we instead fix the code, please?
> 
> Kerry,
> 
> I think that this is fixed with the last patch from Frank. Can you update this patch and resend.

I have update the patch, sb800 code not use stdinc and sse option.
Thanks
--
kerry


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From Kerry.She at amd.com  Fri May  6 04:43:51 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Fri, 6 May 2011 10:43:51 +0800
Subject: [coreboot] [Patch 2/4] compile sb800 code without agesav5
References: <F53A09371FB723428826B442A4B20A4105C2AB91@sbjgexmb1.amd.com>
	<20110422195822.GB13117@coreboot.org>
	<BANLkTikm5Mh98q4=tjiYNWkxR_FuvM-SUQ@mail.gmail.com> 
Message-ID: <F53A09371FB723428826B442A4B20A4105F5C796@sbjgexmb1.amd.com>

> Hello,
> 
> 
> > -----Original Message-----
> > From: Marc Jones [mailto:marcj303 at gmail.com]
> > Sent: Friday, May 06, 2011 8:52 AM
> > To: Stefan Reinauer
> > Cc: She, Kerry; coreboot at coreboot.org
> > Subject: Re: [coreboot] [Patch 2/4] compile sb800 code without agesav5
> >
> > On Fri, Apr 22, 2011 at 1:58 PM, Stefan Reinauer
> > <stefan.reinauer at coreboot.org> wrote:
> > > * She, Kerry <Kerry.She at amd.com> [110422 05:12]:
> > >> Signed-off-by: Kerry She <Kerry.she at amd.com>
> > >>
> > >> SB800 CIMX code can share the AGESA V5 lib code, some platform only
> > >> use sb800 cimx code, not use AGESA v5 code, compile the sb800 cimx
> > >> and AGESA v5 lib code.
> > >>
> > >> Signed-off-by: Kerry She <Kerry.she at amd.com>
> > >>
> > >> Index: Makefile.inc
> > >> ===================================================================
> > >> --- Makefile.inc ? ? ? ?(revision 6481)
> > >> +++ Makefile.inc ? ? ? ?(working copy)
> > >> @@ -110,7 +110,9 @@
> > >> ?CFLAGS += -Werror
> > >> ?endif
> > >> ?ifneq ($(CONFIG_AMD_AGESA),y)
> > >> -CFLAGS += -nostdinc
> > >> + ifneq ($(CONFIG_AMD_CIMX_SB800),y)
> > >> + ?CFLAGS += -nostdinc
> > >> + endif
> > >> ?endif
> > >> ?CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-
> > pointer
> > >>
> > >
> > > Why is that needed. Can we instead fix the code, please?
> >
> > Kerry,
> >
> > I think that this is fixed with the last patch from Frank. Can you
> update this patch and resend.
> 
> I have update the patch, sb800 code not use stdinc and sse option.
> Thanks
> --
> Kerry
Another small patch to make sb800 code works without compile agesav5
thanks

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From marcj303 at gmail.com  Fri May  6 02:52:24 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 5 May 2011 18:52:24 -0600
Subject: [coreboot] [Patch 2/4] compile sb800 code without agesav5
In-Reply-To: <20110422195822.GB13117@coreboot.org>
References: <F53A09371FB723428826B442A4B20A4105C2AB91@sbjgexmb1.amd.com>
	<20110422195822.GB13117@coreboot.org>
Message-ID: <BANLkTikm5Mh98q4=tjiYNWkxR_FuvM-SUQ@mail.gmail.com>

On Fri, Apr 22, 2011 at 1:58 PM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * She, Kerry <Kerry.She at amd.com> [110422 05:12]:
>> Signed-off-by: Kerry She <Kerry.she at amd.com>
>>
>> SB800 CIMX code can share the AGESA V5 lib code,
>> some platform only use sb800 cimx code, not use AGESA v5 code,
>> compile the sb800 cimx and AGESA v5 lib code.
>>
>> Signed-off-by: Kerry She <Kerry.she at amd.com>
>>
>> Index: Makefile.inc
>> ===================================================================
>> --- Makefile.inc ? ? ? ?(revision 6481)
>> +++ Makefile.inc ? ? ? ?(working copy)
>> @@ -110,7 +110,9 @@
>> ?CFLAGS += -Werror
>> ?endif
>> ?ifneq ($(CONFIG_AMD_AGESA),y)
>> -CFLAGS += -nostdinc
>> + ifneq ($(CONFIG_AMD_CIMX_SB800),y)
>> + ?CFLAGS += -nostdinc
>> + endif
>> ?endif
>> ?CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
>>
>
> Why is that needed. Can we instead fix the code, please?

Kerry,

I think that this is fixed with the last patch from Frank. Can you
update this patch and resend.

Marc



-- 
http://se-eng.com



From scott at notabs.org  Fri May  6 18:04:26 2011
From: scott at notabs.org (Scott Duplichan)
Date: Fri, 6 May 2011 11:04:26 -0500
Subject: [coreboot] [PATCH] AMD Persimmon: disable memory clear for boot
	time reduction
Message-ID: <mailman.4219.1355071912.16123.coreboot@coreboot.org>

The attached patch (along with the 04/30/2011 Persimmon patch set)
is needed to get the 640 ms coreboot+seabios+dos boot time.


Signed-off-by: Scott Duplichan <scott at notabs.org>

Index: src/mainboard/amd/persimmon/BiosCallOuts.c
===================================================================
--- src/mainboard/amd/persimmon/BiosCallOuts.c	(revision 6556)
+++ src/mainboard/amd/persimmon/BiosCallOuts.c	(working copy)
@@ -512,6 +512,9 @@
       Data8 &= ~(UINT8)BIT6;
       Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
   }
+
+  // disable memory clear for boot time reduction
+  MemData->ParameterListPtr->EnableMemClr = FALSE;
   return Status;
 }
 /*  Call the host environment interface to provide a user hook opportunity.
*/
-------------- next part --------------
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From marcj303 at gmail.com  Fri May  6 19:37:57 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 6 May 2011 11:37:57 -0600
Subject: [coreboot] [Patch 2/4] compile sb800 code without agesav5
In-Reply-To: <F53A09371FB723428826B442A4B20A4105F5C765@sbjgexmb1.amd.com>
References: <F53A09371FB723428826B442A4B20A4105C2AB91@sbjgexmb1.amd.com>
	<20110422195822.GB13117@coreboot.org>
	<BANLkTikm5Mh98q4=tjiYNWkxR_FuvM-SUQ@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4105F5C765@sbjgexmb1.amd.com>
Message-ID: <BANLkTik4pWPA5rAETfrT0dmbPwMvmcaSFg@mail.gmail.com>

On Thu, May 5, 2011 at 8:33 PM, She, Kerry <Kerry.She at amd.com> wrote:
> Hello,
>
>
>> -----Original Message-----
>> From: Marc Jones [mailto:marcj303 at gmail.com]
>> Sent: Friday, May 06, 2011 8:52 AM
>> To: Stefan Reinauer
>> Cc: She, Kerry; coreboot at coreboot.org
>> Subject: Re: [coreboot] [Patch 2/4] compile sb800 code without agesav5
>>
>> On Fri, Apr 22, 2011 at 1:58 PM, Stefan Reinauer
>> <stefan.reinauer at coreboot.org> wrote:
>> > * She, Kerry <Kerry.She at amd.com> [110422 05:12]:
>> >> Signed-off-by: Kerry She <Kerry.she at amd.com>
>> >>
>> >> SB800 CIMX code can share the AGESA V5 lib code,
>> >> some platform only use sb800 cimx code, not use AGESA v5 code,
>> >> compile the sb800 cimx and AGESA v5 lib code.
>> >>
>> >> Signed-off-by: Kerry She <Kerry.she at amd.com>
>> >>
>> >> Index: Makefile.inc
>> >> ===================================================================
>> >> --- Makefile.inc ? ? ? ?(revision 6481)
>> >> +++ Makefile.inc ? ? ? ?(working copy)
>> >> @@ -110,7 +110,9 @@
>> >> ?CFLAGS += -Werror
>> >> ?endif
>> >> ?ifneq ($(CONFIG_AMD_AGESA),y)
>> >> -CFLAGS += -nostdinc
>> >> + ifneq ($(CONFIG_AMD_CIMX_SB800),y)
>> >> + ?CFLAGS += -nostdinc
>> >> + endif
>> >> ?endif
>> >> ?CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-
>> pointer
>> >>
>> >
>> > Why is that needed. Can we instead fix the code, please?
>>
>> Kerry,
>>
>> I think that this is fixed with the last patch from Frank. Can you update this patch and resend.
>
> I have update the patch, sb800 code not use stdinc and sse option.
> Thanks
> --
> kerry

Acked-by: Marc Jones <marcj303 at gmail.com>



-- 
http://se-eng.com



From marcj303 at gmail.com  Fri May  6 19:38:07 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 6 May 2011 11:38:07 -0600
Subject: [coreboot] [Patch 2/4] compile sb800 code without agesav5
In-Reply-To: <F53A09371FB723428826B442A4B20A4105F5C796@sbjgexmb1.amd.com>
References: <F53A09371FB723428826B442A4B20A4105C2AB91@sbjgexmb1.amd.com>
	<20110422195822.GB13117@coreboot.org>
	<BANLkTikm5Mh98q4=tjiYNWkxR_FuvM-SUQ@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4105F5C796@sbjgexmb1.amd.com>
Message-ID: <BANLkTiksBHd-ZAAcpRYiDSx+VXZMvxj+BA@mail.gmail.com>

On Thu, May 5, 2011 at 8:43 PM, She, Kerry <Kerry.She at amd.com> wrote:
>> Hello,
>>
>>
>> > -----Original Message-----
>> > From: Marc Jones [mailto:marcj303 at gmail.com]
>> > Sent: Friday, May 06, 2011 8:52 AM
>> > To: Stefan Reinauer
>> > Cc: She, Kerry; coreboot at coreboot.org
>> > Subject: Re: [coreboot] [Patch 2/4] compile sb800 code without agesav5
>> >
>> > On Fri, Apr 22, 2011 at 1:58 PM, Stefan Reinauer
>> > <stefan.reinauer at coreboot.org> wrote:
>> > > * She, Kerry <Kerry.She at amd.com> [110422 05:12]:
>> > >> Signed-off-by: Kerry She <Kerry.she at amd.com>
>> > >>
>> > >> SB800 CIMX code can share the AGESA V5 lib code, some platform only
>> > >> use sb800 cimx code, not use AGESA v5 code, compile the sb800 cimx
>> > >> and AGESA v5 lib code.
>> > >>
>> > >> Signed-off-by: Kerry She <Kerry.she at amd.com>
>> > >>
>> > >> Index: Makefile.inc
>> > >> ===================================================================
>> > >> --- Makefile.inc ? ? ? ?(revision 6481)
>> > >> +++ Makefile.inc ? ? ? ?(working copy)
>> > >> @@ -110,7 +110,9 @@
>> > >> ?CFLAGS += -Werror
>> > >> ?endif
>> > >> ?ifneq ($(CONFIG_AMD_AGESA),y)
>> > >> -CFLAGS += -nostdinc
>> > >> + ifneq ($(CONFIG_AMD_CIMX_SB800),y)
>> > >> + ?CFLAGS += -nostdinc
>> > >> + endif
>> > >> ?endif
>> > >> ?CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-
>> > pointer
>> > >>
>> > >
>> > > Why is that needed. Can we instead fix the code, please?
>> >
>> > Kerry,
>> >
>> > I think that this is fixed with the last patch from Frank. Can you
>> update this patch and resend.
>>
>> I have update the patch, sb800 code not use stdinc and sse option.
>> Thanks
>> --
>> Kerry
> Another small patch to make sb800 code works without compile agesav5
> thanks
>
>

Acked-by: Marc Jones <marcj303 at gmail.com>

-- 
http://se-eng.com



From marcj303 at gmail.com  Fri May  6 20:41:19 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 6 May 2011 12:41:19 -0600
Subject: [coreboot] [PATCH 4/4] RS780 PCIE GEN2 Software Compliance
	support
In-Reply-To: <20110422200546.GD13117@coreboot.org>
References: <F53A09371FB723428826B442A4B20A4105C2AB9D@sbjgexmb1.amd.com>
	<20110422200546.GD13117@coreboot.org>
Message-ID: <BANLkTimmDqyXpnAaj5eKK+Vr1yURQx0yKg@mail.gmail.com>

On Fri, Apr 22, 2011 at 2:05 PM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * She, Kerry <Kerry.She at amd.com> [110422 05:14]:
>> Hello,
>>
>> RS780 PCIE GEN2 Software Compliance support
>>
>>
>>
>> Signed-off-by: Kerry She <Kerry.she at amd.com>
>
>
>>
>> + ? ? ? /* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */
>
> Yes, I suggest to add a silent Kconfig option here that can be enabled
> (or disabled) by a mainboard's Kconfig
>

This may be more suited to a devicetree register option like the other
780 settings.

Marc


-- 
http://se-eng.com



From marcj303 at gmail.com  Fri May  6 20:42:58 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 6 May 2011 12:42:58 -0600
Subject: [coreboot] [PATCH 3/4] RS780 DDI Lanes configure support
In-Reply-To: <F53A09371FB723428826B442A4B20A4105DA21CC@sbjgexmb1.amd.com>
References: <F53A09371FB723428826B442A4B20A4105C2AB9C@sbjgexmb1.amd.com>
	<20110422200145.GC13117@coreboot.org>
	<F53A09371FB723428826B442A4B20A4105DA21CC@sbjgexmb1.amd.com>
Message-ID: <BANLkTikChtEYuEuMhmoMVUsjVLv2DNJ4jw@mail.gmail.com>

On Mon, Apr 25, 2011 at 5:34 AM, She, Kerry <Kerry.She at amd.com> wrote:
> Hello, Stefan
>
> void get_cpu_rev() is print the cpu revision info,
> and the cpu information has been printed when doing the
> microcode patching before.
>
> This function GET nothing back but print,
> The function name is a little bit confuse people, So can we remove this function?
>
> --
> kerry
>
>
>> -----Original Message-----
>> From: Stefan Reinauer [mailto:stefan.reinauer at coreboot.org]
>> Sent: Saturday, April 23, 2011 4:02 AM
>> To: She, Kerry
>> Cc: coreboot at coreboot.org
>> Subject: Re: [coreboot] [PATCH 3/4] RS780 DDI Lanes configure support
>>
>> * She, Kerry <Kerry.She at amd.com> [110422 05:13]:
>> > Hello,
>> >
>> > RS780 DDI Lanes configure support
>> >
>> >
>> >
>> > Signed-off-by: Kerry She <Kerry.she at amd.com>
>>
>> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
>>
>>
>> With this list getting longer, it might be nice to:
>> a) make it a case (eax) { ... } construct instead
>> b) print "CPU Rev is" first, then just print the name.
>>
>> > Index: src/southbridge/amd/rs780/early_setup.c
>> > ===================================================================
>> > --- src/southbridge/amd/rs780/early_setup.c ? ? (revision 6481)
>> > +++ src/southbridge/amd/rs780/early_setup.c ? ? (working copy)
>> > @@ -166,6 +166,26 @@
>> > ? ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
>> > ? ? ? ? else if (eax <= 0x100000)
>> > ? ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
>> > + ? ? ? else if (eax == 0x100f21)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 DR_B1.\n");
>> > + ? ? ? else if (eax == 0x100f22)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 DR_B2.\n");
>> > + ? ? ? else if (eax == 0x100f23)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 DR_B3.\n");
>> > + ? ? ? else if (eax == 0x100f2A)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 DR_BA.\n");
>> > + ? ? ? else if (eax == 0x100f42)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 RB_C2.\n");
>> > + ? ? ? else if (eax == 0x100f43)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 RB_C3.\n");
>> > + ? ? ? else if (eax == 0x100f52)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 BL_C2.\n");
>> > + ? ? ? else if (eax == 0x100f53)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 BL_C3.\n");
>> > + ? ? ? else if (eax == 0x100f62)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 DA_C2.\n");
>> > + ? ? ? else if (eax == 0x100f63)
>> > + ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10 DA_C3.\n");
>> > ? ? ? ? else if (eax <= 0x100f00)
>> > ? ? ? ? ? ? ? ? printk(BIOS_INFO, "CPU Rev is Fam 10.\n");
>> > ? ? ? ? else
>> >
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
+	u8 gfx_pcie_config;		/* GFX PCIE Modes */
+	u8 gfx_ddi_config;		/* GFX DDI Modes */

Will you add these default settings to all the 780 platforms? Please
make sure that abuild passes before committing.

Acked-by: Marc Jones <marcj303 at gmail.com>


-- 
http://se-eng.com



From svn at coreboot.org  Sat May  7 10:33:14 2011
From: svn at coreboot.org (repository service)
Date: Sat, 07 May 2011 10:33:14 +0200
Subject: [coreboot] [commit] r6557 - trunk/src/vendorcode/amd/agesa
Message-ID: <E1QIcws-0008SF-Eq@ra.coresystems.de>

Author: kerry
Date: Sat May  7 10:33:14 2011
New Revision: 6557
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6557

Log:
put the amdlib and agesa constant to .rodata segment.
so amdlib.c would not complain "Do not use global variables in romstage"

Signed-off-by: Kerry She <kerry.she at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/vendorcode/amd/agesa/Porting.h

Modified: trunk/src/vendorcode/amd/agesa/Porting.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Porting.h	Thu May  5 18:49:11 2011	(r6556)
+++ trunk/src/vendorcode/amd/agesa/Porting.h	Sat May  7 10:33:14 2011	(r6557)
@@ -226,9 +226,7 @@
   #define VOLATILE volatile
   #define TRUE 1
   #define FALSE 0
-  //#define CONST const - avoid const until the large job of making agesa use it consistently is complete
-#undef CONST
-  #define CONST
+  #define CONST const
   #define ROMDATA
   #define CALLCONV
   #define _16BYTE_ALIGN __attribute__ ((aligned (16)))



From svn at coreboot.org  Sat May  7 10:37:39 2011
From: svn at coreboot.org (repository service)
Date: Sat, 07 May 2011 10:37:39 +0200
Subject: [coreboot] [commit] r6558 - in trunk/src/vendorcode/amd/agesa:
	Include Lib
Message-ID: <E1QId19-0006Qc-1s@ra.coresystems.de>

Author: kerry
Date: Sat May  7 10:37:38 2011
New Revision: 6558
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6558

Log:
1. move _mm_clflush_fs() to __SSE3__ block, because __builtin_ia32_sfence() is the sse built-in function
2. move the Amd Lib functions using sse build-in functions to __SSE3__ block

Signed-off-by: Kerry She <kerry.she at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h
   trunk/src/vendorcode/amd/agesa/Lib/amdlib.c

Modified: trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h	Sat May  7 10:33:14 2011	(r6557)
+++ trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h	Sat May  7 10:37:38 2011	(r6558)
@@ -572,7 +572,6 @@
   data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
   _mm_stream_si128_fs2 (__A, data);
 }
-#endif
 
 static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
 {
@@ -589,6 +588,7 @@
 {
   __builtin_ia32_sfence ();
 }
+#endif
 
 static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count)
 {

Modified: trunk/src/vendorcode/amd/agesa/Lib/amdlib.c
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Lib/amdlib.c	Sat May  7 10:33:14 2011	(r6557)
+++ trunk/src/vendorcode/amd/agesa/Lib/amdlib.c	Sat May  7 10:37:38 2011	(r6558)
@@ -401,6 +401,8 @@
                                  };
   ((VOID (*)(VOID)) (size_t) opcode) (); // call the function
 }
+
+#ifdef __SSE3__
 VOID F10RevDProbeFilterCritical (
   IN       PCI_ADDR PciAddress,
   IN       UINT32   PciRegister
@@ -416,23 +418,7 @@
   _mm_mfence ();
   __writemsr (0xC001001F, msrsave); 
 }
-VOID
-IdsOutPort (
-  IN       UINT32 Addr,
-  IN       UINT32 Value,
-  IN       UINT32 Flag
-  )
-{
-  __outdword ((UINT16) Addr, Value);
-}
-VOID 
-StopHere (
-  VOID
-  )
-{
-  VOLATILE UINTN x = 1;
-  while (x);
-}
+
 VOID
 LibAmdCLFlush (
   IN       UINT64 Address,
@@ -450,7 +436,25 @@
   }
   RestoreHwcr (hwcrSave);
 }
+#endif //__SSE3__
 
+VOID
+IdsOutPort (
+  IN       UINT32 Addr,
+  IN       UINT32 Value,
+  IN       UINT32 Flag
+  )
+{
+  __outdword ((UINT16) Addr, Value);
+}
+VOID 
+StopHere (
+  VOID
+  )
+{
+  VOLATILE UINTN x = 1;
+  while (x);
+}
 
 /*---------------------------------------------------------------------------------------*/
 /**



From svn at coreboot.org  Sat May  7 10:43:40 2011
From: svn at coreboot.org (repository service)
Date: Sat, 07 May 2011 10:43:40 +0200
Subject: [coreboot] [commit] r6559 - in trunk/src:
	southbridge/amd/cimx_wrapper/sb800 vendorcode/amd/cimx/sb800
Message-ID: <E1QId6y-00078p-Ti@ra.coresystems.de>

Author: kerry
Date: Sat May  7 10:43:40 2011
New Revision: 6559
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6559

Log:
SB800 CIMX code can share the AGESA V5 lib code,
some platform only use sb800 cimx code, not use AGESA v5 code.
for such platform, one can compile the sb800 cimx and AGESA v5 lib code.

Signed-off-by: Kerry She <kerry.she at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h
   trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
   trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h	Sat May  7 10:37:38 2011	(r6558)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h	Sat May  7 10:43:40 2011	(r6559)
@@ -161,7 +161,7 @@
   IN OUT   unsigned int          EBX_Reg;                ///< CPUID instruction result in EBX
   IN OUT   unsigned int          ECX_Reg;                ///< CPUID instruction result in ECX
   IN OUT   unsigned int          EDX_Reg;                ///< CPUID instruction result in EDX
-} SB_CPUID_DATA;
+} CPUID_DATA;
 
 #define WARM_RESET 1
 #define COLD_RESET 2      // Cold reset

Modified: trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h	Sat May  7 10:37:38 2011	(r6558)
+++ trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h	Sat May  7 10:43:40 2011	(r6559)
@@ -104,3 +104,14 @@
  *
  */
 void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length);
+
+
+/* SB800 CIMx and AGESA V5 can share lib functions */
+unsigned char ReadIo8(IN unsigned short Address);
+unsigned short ReadIo16(IN unsigned short Address);
+unsigned int ReadIo32(IN unsigned short Address);
+void WriteIo8(IN unsigned short Address, IN unsigned char Data);
+void WriteIo16(IN unsigned short Address, IN unsigned short Data);
+void WriteIo32(IN unsigned short Address, IN unsigned int Data);
+void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
+unsigned char ReadNumberOfCpuCores(void);

Modified: trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c	Sat May  7 10:37:38 2011	(r6558)
+++ trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c	Sat May  7 10:43:40 2011	(r6559)
@@ -329,7 +329,7 @@
 {
   UINT32   abValue;
   UINT16   dwTempVar;
-  SB_CPUID_DATA  CpuId;
+  CPUID_DATA  CpuId;
   UINT8   cimNativepciesupport;
   UINT8   cimIrConfig;
   UINT8   Data;



From svn at coreboot.org  Sat May  7 10:51:33 2011
From: svn at coreboot.org (repository service)
Date: Sat, 07 May 2011 10:51:33 +0200
Subject: [coreboot] [commit] r6560 - trunk/src/southbridge/amd/rs780
Message-ID: <E1QIdEb-0002Jk-Hb@ra.coresystems.de>

Author: kerry
Date: Sat May  7 10:51:32 2011
New Revision: 6560
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6560

Log:
RS780 DDI Lanes configure support,
and remove RS780 get_cpu_rev().

Signed-off-by: Kerry She <kerry.she at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/southbridge/amd/rs780/chip.h
   trunk/src/southbridge/amd/rs780/early_setup.c
   trunk/src/southbridge/amd/rs780/gfx.c

Modified: trunk/src/southbridge/amd/rs780/chip.h
==============================================================================
--- trunk/src/southbridge/amd/rs780/chip.h	Sat May  7 10:43:40 2011	(r6559)
+++ trunk/src/southbridge/amd/rs780/chip.h	Sat May  7 10:51:32 2011	(r6560)
@@ -33,6 +33,8 @@
 	u8 gfx_compliance;		/* whether support compliance? */
 	u8 gfx_reconfiguration;		/* Dynamic Lind Width Control */
 	u8 gfx_link_width;		/* Desired width of lane 2 */
+	u8 gfx_pcie_config;		/* GFX PCIE Modes */
+	u8 gfx_ddi_config;		/* GFX DDI Modes */
 };
 struct chip_operations;
 extern struct chip_operations southbridge_amd_rs780_ops;

Modified: trunk/src/southbridge/amd/rs780/early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/early_setup.c	Sat May  7 10:43:40 2011	(r6559)
+++ trunk/src/southbridge/amd/rs780/early_setup.c	Sat May  7 10:51:32 2011	(r6560)
@@ -142,32 +142,6 @@
 	}
 }
 
-static void get_cpu_rev(void)
-{
-	u32 eax;
-
-	eax = cpuid_eax(1);
-	printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
-	if (eax <= 0xfff)
-		printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
-	else if (eax <= 0x10fff)
-		printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
-	else if (eax <= 0x20fff)
-		printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
-	else if (eax <= 0x40fff)
-		printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
-	else if (eax == 0x60fb1 || eax == 0x60f81)	/*These two IDS are exception, they are G1. */
-		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
-	else if (eax <= 0X60FF0)
-		printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
-	else if (eax <= 0x100000)
-		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
-	else if (eax <= 0x100f00)
-		printk(BIOS_INFO, "CPU Rev is Fam 10.\n");
-	else
-		printk(BIOS_INFO, "CPU Rev is K8_10.\n");
-}
-
 static u8 is_famly10(void)
 {
 	return (cpuid_eax(1) & 0xff00000) != 0;
@@ -630,6 +604,13 @@
 
 	/* ATINB_CLKCFG_PORT_TABLE */
 	/* rs780 A11 SB Link full swing? */
+
+	/* SET NB_MISC_REG01 BIT8 to Enable HDMI, reference CIMX_5_9_3 NBPOR_InitPOR(),
+	 * then the accesses to internal graphics IO space 0x60/0x64, are forwarded to
+	 * nbconfig:0x60/0x64
+	 */
+
+	set_nbmisc_enable_bits(nb_dev, 0x01, ~(1 << 8), (1 << 8));
 }
 
 /* enable CFG access to Dev8, which is the SB P2P Bridge */
@@ -647,8 +628,6 @@
 	device_t nb_dev = PCI_DEV(0, 0, 0);
 	printk(BIOS_INFO, "rs780_early_setup()\n");
 
-	get_cpu_rev();
-
 	/* The printk(BIOS_INFO, s) below cause the system unstable. */
 	switch (get_nb_rev(nb_dev)) {
 	case REV_RS780_A11:

Modified: trunk/src/southbridge/amd/rs780/gfx.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/gfx.c	Sat May  7 10:43:40 2011	(r6559)
+++ trunk/src/southbridge/amd/rs780/gfx.c	Sat May  7 10:51:32 2011	(r6560)
@@ -303,6 +303,43 @@
 }
 #endif
 
+#define GFX_CONFIG_DDI1		0x04
+#define GFX_CONFIG_DDI2		0x08
+#define GFX_CONFIG_DDI		(GFX_CONFIG_DDI1 | GFX_CONFIG_DDI2)
+
+/**
+ * Force poweron pads for lanes used for DDI
+ * reference CIMx PCIEL_PowerOnDDILanes()
+ *
+ * Inactive    B_PRX_PDNB_FDIS  B_PTX_PDNB_FDIS
+ *  Lanes
+ * Lanes  0-1   Bit  8           Bit 0
+ * Lanes  2-3   Bit  9           Bit 1
+ * Lanes  4-5   Bit 10           Bit 2
+ * Lanes  6-7   Bit 11           Bit 3
+ * Lanes  8-9   Bit 12           Bit 4
+ * Lanes 10-11  Bit 13           Bit 5
+ * Lanes 12-13  Bit 14           Bit 6
+ * Lanes 14-15  Bit 15           Bit 7
+ */
+static void poweron_ddi_lanes(device_t nb_dev)
+{
+	u8 i;
+	u32 gfx_cfg = 0;
+	u32 ddi_pads = 0;
+
+	ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */
+	gfx_cfg = nbmisc_read_index(nb_dev, 0x74);
+	for (i = 0; i < 3 ; i++) {
+		if (gfx_cfg & GFX_CONFIG_DDI) {
+			ddi_pads |= (3 << (i * 2));
+		}
+		gfx_cfg >>= 8;
+	}
+	ddi_pads |= ddi_pads << 8; /* both TX and RX */
+	nbpcie_ind_write_index(nb_dev, 0x65, ~ddi_pads);
+}
+
 static void internal_gfx_pci_dev_init(struct device *dev)
 {
 	unsigned char * bpointer;
@@ -535,6 +572,9 @@
 		}
 	}
 
+	/* Poweron DDI Lanes */
+	poweron_ddi_lanes(nb_dev);
+
 	/* Transfer the Table to VBIOS. */
 	pointer = (u32 *)&vgainfo;
 	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
@@ -1111,6 +1151,147 @@
 
 	/* step 2, TMDS, (only need if CMOS option is enabled) */
 	if (cfg->gfx_tmds) {
+		/**
+		 * PCIe Initialization for DDI.
+		 * The VBIOS/Driver is responsible for DDI programming sequence,
+		 * The SBIOS is responsible for programming the lane and clock muxing specific to each case.
+		 * Refer to RPR Chapter 7: "PCIe Initialization for DDI".
+		 * Note: This programming must be done before hold training is released.
+		 */
+		switch (cfg->gfx_pcie_config) {
+			case 1: /* 1x16 GFX -default case, no programming required */
+				break;
+			case 2: /* 1x8 GFX on Lanes 0-7 */
+			case 5: /* 1x4 GPP on Lanes 0-3 */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6); /* Disables PCIe mode on PHY Lanes  8-11 */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7); /* Disables PCIe mode on PHY Lanes 12-15 */
+				break;
+			case 3: /* 1x8 on Lanes 8-15 */
+			case 7: /* 1x4 GPP on Lanes 8-11 */
+				/* TXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
+				set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x0 << 0);
+				/* RXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x2 << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14);
+				/* TX Lane Muxing */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5);
+				break;
+			case 4:  /* 2x8 */
+			case 10: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 8-11 */
+			case 14: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 8-11 */
+			case 17: /* 1x4 GPP on Lanes 0-3 and 1x8 GFX on Lanes 8-15 */
+				/* Set dual slot configuration */
+				set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
+				break;
+			case 9: /* PCIe 2x4 GPPs on Lanes 0-7 */
+			case 6: /* PCIe 1x4 GPP on Lanes 4-7 */
+				/* Set dual slot configuration */
+				set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
+				/* TXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20);
+				set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 0, 0x0 << 0);
+				/* RXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x1 << 10);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x0 << 14);
+				/* TX Lane Muxing */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7);
+				break;
+			case 13: /* 2x4 GPPs on Lanes 8-15 */
+			case 8:  /* 1x4 GPP on Lanes 12-15 */
+				/* Set dual slot configuration */
+				set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
+				/* TXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
+				set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x3 << 0);
+				/* RXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x3 << 10);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14);
+				/* TX Lane Muxing */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
+				set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5);
+				break;
+			case 15: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 12-15 */
+			case 11: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 12-15 */
+				/* Set dual slot configuration */
+				set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
+				/* TXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20);
+				set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x1 << 0);
+				/* RXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x0 << 10);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x3 << 14);
+				/* TX Lane Muxing */
+				set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6);
+				break;
+			case 16: /* 1x8 GFX on Lanes 8-15 and 1x4 GPP on Lanes 4-7 */
+			case 12: /* 1x4 GPP on Lanes 4-7 and 1x8 GFX on Lanes 8-15 */
+				/* Set dual slot configuration */
+				set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
+				/* TXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
+				set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 22, 0x2 << 22);
+				set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x2 << 0);
+				/* RXCLK */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x1 << 14);
+				/* TX Lane Muxing */
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1);
+				set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
+				break;
+			default:
+				printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
+				break;
+		}
+
+		/* DDI Configuration */
+		switch (cfg->gfx_ddi_config) {
+			case 1: /* DDI_SL lanes0-3 */
+				nbmisc_write_index(nb_dev, 0x74, GFX_CONFIG_DDI);
+				break;
+			case 2: /* DDI_SL lanes4-7 */
+				nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8));
+				break;
+			case 5: /* DDI_SL lanes0-4, lanes4-7 */
+				nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI);
+				break;
+			case 6: /* DDI_DL lanes0-7 */
+				nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI);
+				break;
+			default:
+				printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
+				break;
+		}
 	}
 
 #if 1				/* external clock mode */
@@ -1123,8 +1304,6 @@
 	/* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
 	/* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
 	/* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
-	set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
-			       1 << 6 | 1 << 8 | 1 << 10);
 	reg32 = nbmisc_read_index(nb_dev, 0x28);
 	printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
 



From svn at coreboot.org  Sat May  7 11:15:03 2011
From: svn at coreboot.org (repository service)
Date: Sat, 07 May 2011 11:15:03 +0200
Subject: [coreboot] [commit] r6561 - in trunk/src/mainboard: . advansus
	advansus/a785e-i advansus/a785e-i/acpi
Message-ID: <E1QIdbL-0004mm-Gp@ra.coresystems.de>

Author: kerry
Date: Sat May  7 11:15:02 2011
New Revision: 6561
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6561

Log:
ADVANSUS A785E-I Mainboard support, Family10h ASB2, RS880(RS785E) + SB820 platform.

Signed-off-by: Kerry She <kerry.she at amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Added:
   trunk/src/mainboard/advansus/
   trunk/src/mainboard/advansus/Kconfig
   trunk/src/mainboard/advansus/a785e-i/
   trunk/src/mainboard/advansus/a785e-i/Kconfig
   trunk/src/mainboard/advansus/a785e-i/Makefile.inc
   trunk/src/mainboard/advansus/a785e-i/acpi/
   trunk/src/mainboard/advansus/a785e-i/acpi/cpstate.asl
   trunk/src/mainboard/advansus/a785e-i/acpi/ide.asl
   trunk/src/mainboard/advansus/a785e-i/acpi/routing.asl
   trunk/src/mainboard/advansus/a785e-i/acpi/sata.asl
   trunk/src/mainboard/advansus/a785e-i/acpi/usb.asl
   trunk/src/mainboard/advansus/a785e-i/acpi_tables.c
   trunk/src/mainboard/advansus/a785e-i/chip.h
   trunk/src/mainboard/advansus/a785e-i/cmos.layout
   trunk/src/mainboard/advansus/a785e-i/devicetree.cb
   trunk/src/mainboard/advansus/a785e-i/dsdt.asl
   trunk/src/mainboard/advansus/a785e-i/fadt.c
   trunk/src/mainboard/advansus/a785e-i/get_bus_conf.c
   trunk/src/mainboard/advansus/a785e-i/irq_tables.c
   trunk/src/mainboard/advansus/a785e-i/mainboard.c
   trunk/src/mainboard/advansus/a785e-i/mb_sysconf.h
   trunk/src/mainboard/advansus/a785e-i/mptable.c
   trunk/src/mainboard/advansus/a785e-i/pmio.c
   trunk/src/mainboard/advansus/a785e-i/pmio.h
   trunk/src/mainboard/advansus/a785e-i/reset.c
   trunk/src/mainboard/advansus/a785e-i/resourcemap.c
   trunk/src/mainboard/advansus/a785e-i/romstage.c
Modified:
   trunk/src/mainboard/Kconfig

Modified: trunk/src/mainboard/Kconfig
==============================================================================
--- trunk/src/mainboard/Kconfig	Sat May  7 10:51:32 2011	(r6560)
+++ trunk/src/mainboard/Kconfig	Sat May  7 11:15:02 2011	(r6561)
@@ -6,6 +6,8 @@
 
 config VENDOR_ABIT
 	bool "Abit"
+config VENDOR_ADVANSUS
+        bool "Advansus"
 config VENDOR_ADVANTECH
 	bool "Advantech"
 config VENDOR_AMD
@@ -119,6 +121,7 @@
 
 source "src/mainboard/a-trend/Kconfig"
 source "src/mainboard/abit/Kconfig"
+source "src/mainboard/advansus/Kconfig"
 source "src/mainboard/advantech/Kconfig"
 source "src/mainboard/amd/Kconfig"
 source "src/mainboard/arima/Kconfig"

Added: trunk/src/mainboard/advansus/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/Kconfig	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+if VENDOR_ADVANSUS
+
+choice
+	prompt "Mainboard model"
+
+config BOARD_ADVANSUS_A785E_I
+	bool "A785E-I"
+
+endchoice
+
+source "src/mainboard/advansus/a785e-i/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Advansus"
+
+endif # VENDOR_ADVANSUS

Added: trunk/src/mainboard/advansus/a785e-i/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/Kconfig	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,112 @@
+if BOARD_ADVANSUS_A785E_I
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_SOCKET_ASB2
+	select DIMM_DDR3
+	select DIMM_REGISTERED
+	select QRANK_DIMM_SUPPORT
+	select NORTHBRIDGE_AMD_AMDFAM10
+	select SOUTHBRIDGE_AMD_RS780
+	select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+	select SUPERIO_WINBOND_W83627HF #COM1, COM2
+	#select SUPERIO_FINTEK_F81216AD #COM3, COM4
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select AMDMCT
+	select HAVE_MP_TABLE
+	select HAVE_ACPI_TABLES
+	select BOARD_HAS_FADT
+	select GENERATE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_1024
+	select RAMINIT_SYSINFO
+	select ENABLE_APIC_EXT_ID
+	select TINY_BOOTBLOCK
+	select GFXUMA
+	select HAVE_DEBUG_CAR
+	select SET_FIDVID
+
+config AMD_CIMX_SB800
+        bool
+        default y
+
+config MAINBOARD_DIR
+	string
+	default advansus/a785e-i
+
+config APIC_ID_OFFSET
+	hex
+	default 0x0
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "A785E-I"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+
+config MEM_TRAIN_SEQ
+	int
+	default 2
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x1
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config AMD_UCODE_PATCH_FILE
+	string
+	default "mc_patch_010000b6.h"
+
+config RAMTOP
+	hex
+	default 0x2000000
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+config RAMBASE
+	hex
+	default 0x200000
+
+config VGA_BIOS_ID
+        string
+        default "1002,9712"
+
+config WARNINGS_ARE_ERRORS
+        bool
+        default n
+
+endif #BOARD_ADVANSUS_A785E_I

Added: trunk/src/mainboard/advansus/a785e-i/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/Makefile.inc	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,19 @@
+#romstage-y += reset.c #FIXME romstage have include test_rest.c
+romstage-y += pmio.c
+
+ramstage-y += reset.c
+ramstage-y += pmio.c
+
+#SB800 CIMx share AGESA V5 lib code
+ifneq ($(CONFIG_AMD_AGESA),y)
+ romstage-y += ../../../vendorcode/amd/agesa/Lib/amdlib.c
+ ramstage-y += ../../../vendorcode/amd/agesa/Lib/amdlib.c
+
+ AGESA_INC := -Isrc/vendorcode/amd/agesa/ \
+	      -Isrc/vendorcode/amd/agesa/Include \
+	      -Isrc/vendorcode/amd/agesa/Proc/IDS/ \
+	      -Isrc/vendorcode/amd/agesa/Proc/CPU/ \
+	      -Isrc/vendorcode/amd/agesa/Proc/CPU/Family
+
+ CFLAGS += $(AGESA_INC)
+endif

Added: trunk/src/mainboard/advansus/a785e-i/acpi/cpstate.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/acpi/cpstate.asl	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}

Added: trunk/src/mainboard/advansus/a785e-i/acpi/ide.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/acpi/ide.asl	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}

Added: trunk/src/mainboard/advansus/a785e-i/acpi/routing.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/acpi/routing.asl	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,398 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+
+		Package(){0x0009FFFF, 0, INTB, 0 },
+		Package(){0x0009FFFF, 1, INTC, 0 },
+		Package(){0x0009FFFF, 2, INTD, 0 },
+		Package(){0x0009FFFF, 3, INTA, 0 },
+
+		Package(){0x000AFFFF, 0, INTC, 0 },
+		Package(){0x000AFFFF, 1, INTD, 0 },
+		Package(){0x000AFFFF, 2, INTA, 0 },
+		Package(){0x000AFFFF, 3, INTB, 0 },
+
+		Package(){0x000BFFFF, 0, INTD, 0 },
+		Package(){0x000BFFFF, 1, INTA, 0 },
+		Package(){0x000BFFFF, 2, INTB, 0 },
+		Package(){0x000BFFFF, 3, INTC, 0 },
+
+		Package(){0x000CFFFF, 0, INTA, 0 },
+		Package(){0x000CFFFF, 1, INTB, 0 },
+		Package(){0x000CFFFF, 2, INTC, 0 },
+		Package(){0x000CFFFF, 3, INTD, 0 },
+
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		Package(){0x0016FFFF, 1, INTB, 0 },
+
+		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+
+		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, 0, 18 },
+		package(){0x0001FFFF, 1, 0, 19 },
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, 0, 17 }, */
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Package(){0x0006FFFF, 0, 0, 18 }, */
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Package(){0x0007FFFF, 0, 0, 19 }, */
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Dev 9 - PCIe Bridge for network card */
+		Package(){0x0009FFFF, 0, 0, 17 },
+		/* Package(){0x0009FFFF, 1, 0, 16 }, */
+		/* Package(){0x0009FFFF, 2, 0, 17 }, */
+		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		/* Bus 0, Dev A - PCIe Bridge for network card */
+		Package(){0x000AFFFF, 0, 0, 18 },
+		/* Package(){0x000AFFFF, 1, 0, 16 }, */
+		/* Package(){0x000AFFFF, 2, 0, 17 }, */
+		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, 0, 18 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		/* Package(){0x0012FFFF, 2, 0, 18 }, */
+
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+		/* Package(){0x0013FFFF, 2, 0, 16 }, */
+
+		/* Package(){0x00140000, 0, 0, 16 }, */
+
+		Package(){0x0016FFFF, 0, 0, 18 },
+		Package(){0x0016FFFF, 1, 0, 17 },
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+
+		/* TODO: pcie */
+		Package(){0x0015FFFF, 0, 0, 16 },
+		Package(){0x0015FFFF, 1, 0, 17 },
+		Package(){0x0015FFFF, 2, 0, 18 },
+		Package(){0x0015FFFF, 3, 0, 19 },
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+	Name(APR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE0, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APE0, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PE1, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APE1, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PE2, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APE2, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE3, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APE3, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+		Package(){0x0007FFFF, 0, 0, 0x16 },
+		Package(){0x0007FFFF, 1, 0, 0x17 },
+		Package(){0x0007FFFF, 2, 0, 0x14 },
+		Package(){0x0007FFFF, 3, 0, 0x15 },
+	})
+}

Added: trunk/src/mainboard/advansus/a785e-i/acpi/sata.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/acpi/sata.asl	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00110000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}

Added: trunk/src/mainboard/advansus/a785e-i/acpi/usb.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/acpi/usb.asl	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "usb.asl"
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+    	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+	Scope (\_GPE) {
+		Method (_L1A) {
+			UCOC()
+			if (LEqual(GPB5,PLC5)) {
+				Not(PLC5,PLC5)
+				Store(PLC5, \_SB.PT5D)
+			}
+		}
+	}
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ 	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}

Added: trunk/src/mainboard/advansus/a785e-i/acpi_tables.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/acpi_tables.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+#include "mb_sysconf.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+extern const unsigned char AmlCode_ssdt2[];
+extern const unsigned char AmlCode_ssdt3[];
+extern const unsigned char AmlCode_ssdt4[];
+extern const unsigned char AmlCode_ssdt5[];
+#endif
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+	acpi_header_t *ssdtx;
+	void *p;
+	int i;
+#endif
+
+	get_bus_conf();	/* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	/* SLIT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdp, slit);
+
+	/* SSDT */
+	current	  = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)current;
+	memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+	current += ssdt->length;
+	memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+	//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
+	update_ssdt((void*)ssdt);
+	/* recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	current = acpi_add_ssdt_pstates(rsdp, current);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+
+	/* same htio, but different position? We may have to copy,
+	change HCIN, and recalculate the checknum and add_table */
+
+	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+		if((sysconf.pci1234[i] & 1) != 1 ) continue;
+		u8 c;
+		if (i < 7) {
+			c = (u8) ('4' + i - 1);
+		} else {
+			c = (u8) ('A' + i - 1 - 6);
+		}
+		current	  = ( current + 0x07) & -0x08;
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
+		ssdtx = (acpi_header_t *)current;
+		switch (sysconf.hcid[i]) {
+		case 1:
+			p = &AmlCode_ssdt2;
+			break;
+		case 2:
+			p = &AmlCode_ssdt3;
+			break;
+		case 3:	/* 8131 */
+			p = &AmlCode_ssdt4;
+			break;
+		default:
+			/* HTX no io apic */
+			p = &AmlCode_ssdt5;
+			break;
+		}
+		memcpy(ssdtx, p, sizeof(acpi_header_t));
+		current += ssdtx->length;
+		memcpy(ssdtx, p, ssdtx->length);
+		update_ssdtx((void *)ssdtx, i);
+		ssdtx->checksum = 0;
+		ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
+		acpi_add_table(rsdp, ssdtx);
+	}
+#endif
+
+	/* DSDT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FDAT */
+#if CONFIG_BOARD_HAS_FADT == 1
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+#endif
+
+#if DUMP_ACPI_TABLES == 1
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}

Added: trunk/src/mainboard/advansus/a785e-i/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/chip.h	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};

Added: trunk/src/mainboard/advansus/a785e-i/cmos.layout
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/cmos.layout	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

Added: trunk/src/mainboard/advansus/a785e-i/devicetree.cb
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/devicetree.cb	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,124 @@
+# sample config for advansus/A785E-I
+chip northbridge/amd/amdfam10/root_complex
+	device lapic_cluster 0 on
+		chip cpu/amd/socket_ASB2  #L1 and DDR3
+			 device lapic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id.
+		chip northbridge/amd/amdfam10
+			device pci 18.0 on #  northbridge
+				chip southbridge/amd/rs780
+					device pci 0.0 on end # HT  	0x9600
+					device pci 1.0 on end # Internal Graphics P2P bridge 0x9712
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
+					device pci 3.0 off end # PCIE P2P bridge 0x960b
+					device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless
+					device pci 5.0 off end # PCIE P2P bridge 0x9605
+					device pci 6.0 off end # PCIE P2P bridge 0x9606
+					device pci 7.0 off end # PCIE P2P bridge 0x9607
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					device pci 9.0 on end # Ethernet
+					device pci a.0 on end # Ethernet
+					register "gppsb_configuration" = "4"	# Configuration E
+					register "gpp_configuration" = "3"	# Configuration D
+					register "port_enable" = "0x6f6"
+					register "gfx_dev2_dev3" = "0"
+					register "gfx_dual_slot" = "0"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+					register "gfx_tmds" = "1"
+					register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
+					register "gfx_ddi_config" = "1"  # Lanes 0-3 DDI_SL
+				end
+				chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pci bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.2 on end # USB
+	 				device pci 14.0 on # SM
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x439c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on
+                                                chip superio/winbond/w83627hf
+                                                        device pnp 2e.0 off #  Floppy
+                                                                io 0x60 = 0x3f0
+                                                                irq 0x70 = 6
+                                                                drq 0x74 = 2
+                                                        end
+                                                        device pnp 2e.1 off #  Parallel Port
+                                                                io 0x60 = 0x378
+                                                                irq 0x70 = 7
+                                                        end
+                                                        device pnp 2e.2 on #  Com1
+                                                                io 0x60 = 0x3f8
+                                                                irq 0x70 = 4
+                                                        end
+                                                        device pnp 2e.3 on #  Com2
+                                                                io 0x60 = 0x2f8
+                                                                irq 0x70 = 3
+                                                        end
+                                                        device pnp 2e.5 on #  Keyboard
+                                                                io 0x60 = 0x60
+                                                                io 0x62 = 0x64
+                                                                irq 0x70 = 1
+                                                                irq 0x72 = 12
+                                                        end
+                                                        device pnp 2e.6 off  # SFI
+                                                                io 0x62 = 0x100
+                                                        end
+                                                        device pnp 2e.7 off #  GPIO_GAME_MIDI
+                                                                io 0x60 = 0x220
+                                                                io 0x62 = 0x300
+                                                                irq 0x70 = 9
+                                                        end
+                                                        device pnp 2e.8 off end #  WDTO_PLED
+                                                        device pnp 2e.9 off end #  GPIO_SUSLED
+                                                        device pnp 2e.a off end #  ACPI
+                                                        device pnp 2e.b on #  HW Monitor
+                                                                io 0x60 = 0x290
+                                                                irq 0x70 = 5
+                                                        end
+                                                end     #superio/winbond/w83627hf
+					end # LPC	0x439d
+					device pci 14.4 off end # PCI	0x4384 # PCI-b conflict with GPIO.
+					device pci 14.5 on end # USB 2
+					device pci 14.6 off end # Gec
+					device pci 15.0 on end # PCIe 0
+					device pci 15.1 on end # PCIe 1
+					device pci 15.2 on end # PCIe 2
+					device pci 15.3 on end # PCIe 3
+					device pci 16.0 on end # USB
+					device pci 16.2 on end # USB
+					#register "gpp_configuration" = "0" #4:0:0:0
+					#register "gpp_configuration" = "2" #2:2:0:0
+					#register "gpp_configuration" = "3" #2:1:1:0
+					register "gpp_configuration" = "4" #1:1:1:1
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				end	#southbridge/amd/cimx_wrapper/sb800
+			end #  device pci 18.0
+
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+		end
+	end #pci_domain
+end

Added: trunk/src/mainboard/advansus/a785e-i/dsdt.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/dsdt.asl	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,1824 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"ADVANSUS",               /* OEMID */
+	"A785E-I ",	     /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include "../../../arch/x86/acpi/debug.asl" */		/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			CPU0,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU1,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU2,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU3,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+	} /* End _PR scope */
+
+	/* PIC IRQ mapping registers, C00h-C01h. */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PIRA, 0x00000008,	/* Index 0 */
+		PIRB, 0x00000008,	/* Index 1 */
+		PIRC, 0x00000008,	/* Index 2 */
+		PIRD, 0x00000008,	/* Index 3 */
+		PIRE, 0x00000008,	/* Index 4 */
+		PIRF, 0x00000008,	/* Index 5 */
+		PIRG, 0x00000008,	/* Index 6 */
+		PIRH, 0x00000008,	/* Index 7 */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk. TODO: should be 0x60 */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve){
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+
+	#include "acpi/routing.asl"
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+		Method(CIRQ, 0x00, NotSerialized){
+			Store(0, PIRA)
+			Store(0, PIRB)
+			Store(0, PIRC)
+			Store(0, PIRD)
+			Store(0, PIRE)
+			Store(0, PIRF)
+			Store(0, PIRG)
+			Store(0, PIRH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PIRA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PIRA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PIRB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PIRB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PIRC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PIRC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIRD) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIRD)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRD, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRD)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PIRE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PIRE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PIRF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PIRF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PIRG) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PIRG)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRG, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRG)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PIRH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PIRH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			/* Notify (\_TZ.TZ00, 0x80) */
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event - Moved to USB.asl */
+		/* Method(_L1A) {
+		*	DBGO("\\_GPE\\_L1A\n")
+		* }
+		*/
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	#include "acpi/usb.asl"
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			External (TOM1)
+			External (TOM2)
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+			/* GPP */
+			Device(PBR9) {
+				Name(_ADR, 0x00090000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS9) }   /* APIC mode */
+					Return (PS9)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR9 */
+
+			Device(PBRa) {
+				Name(_ADR, 0x000A0000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APSa) }   /* APIC mode */
+					Return (PSa)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBRa */
+
+			Device(PE20) {
+				Name(_ADR, 0x00150000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE0) }   /* APIC mode */
+					Return (PE0)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE20 */
+			Device(PE21) {
+				Name(_ADR, 0x00150001)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE1) }   /* APIC mode */
+					Return (PE1)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE21 */
+			Device(PE22) {
+				Name(_ADR, 0x00150002)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE2) }   /* APIC mode */
+					Return (APE2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE22 */
+			Device(PE23) {
+				Name(_ADR, 0x00150003)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE3) }   /* APIC mode */
+					Return (PE3)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE23 */
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00110000)
+				#include "acpi/sata.asl"
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00120000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00120002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00160000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UOH6) {
+				Name(_ADR, 0x00160002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00140005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				#include "acpi/ide.asl"
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#if 0
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#endif
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* length */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+#if 0
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/*  Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/*  Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+#endif
+                                /* memory space for PCI BARs below 4GB */
+                                Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+#if 0
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM1, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	Subtract(TOM2, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+#endif
+                                CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+                                CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+                                /*
+                                 * Declare memory between TOM1 and 4GB as available
+                                 * for PCI MMIO.
+                                 * Use ShiftLeft to avoid 64bit constant (for XP).
+                                 * This will work even if the OS does 32bit arithmetic, as
+                                 * 32bit (0x00000000 - TOM1) will wrap and give the same
+                                 * result as 64bit (0x100000000 - TOM1).
+                                 */
+                                Store(TOM1, MM1B)
+                                ShiftLeft(0x10000000, 4, Local0)
+                                Subtract(Local0, TOM1, Local0)
+                                Store(Local0, MM1L)
+
+				Return(CRES) /* note to change the Name buffer */
+			}  /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+#if 0
+	/* SMBUS Support */
+	Mutex (SBX0, 0x00)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x10, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+			If (LEqual (Local0, Zero)) {
+				Release (SBX0)
+				Return (0x0)
+			}
+
+			Store (0x1F, HSTS)
+			Store (Or (ShiftLeft (Arg1, One), One), HADD)
+			Store (Arg2, HCMD)
+			If (LEqual (Arg0, 0x07)) {
+				Store (0x48, HCNT) /* read byte */
+			}
+
+			Store (SWTC (0x03E8), Local1) /* 1000 ms */
+			If (LEqual (Local1, Zero)) {
+				If (LEqual (Arg0, 0x07)) {
+					Store (DAT0, Local0)
+				}
+			}
+			Else {
+				Store (Local1, Local0)
+			}
+
+			Release (SBX0)
+		}
+
+		/* DBGO("the value of SMBusData0 register ") */
+		/* DBGO(Arg2) */
+		/* DBGO(" is ") */
+		/* DBGO(Local0) */
+		/* DBGO("\n") */
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 2732)
+		Name (THOT, 800)
+		Name (TCRT, 850)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+				If (LGreater (Local0, 0x10)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400, KELV))
+				}
+
+				Store (SMBR (0x07, 0x4C, 0x01), Local0)
+				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+				If (LGreater (Local0, 0x10)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Multiply (Local1, 10, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+#endif
+}
+/* End of ASL file */

Added: trunk/src/mainboard/advansus/a785e-i/fadt.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/fadt.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "pmio.h"
+
+/*extern*/ u16 pm_base = 0x800;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of rs780. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+#define ACPI_PM_EVT_BLK		(pm_base + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK	(pm_base + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK	(pm_base + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK		(pm_base + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK		(pm_base + 0x10) /* 8 bytes */
+#define ACPI_CPU_CONTORL	(pm_base + 0x08) /* 6 bytes */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	pm_base &= 0xFFFF;
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
+	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
+	pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
+	pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
+	pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
+	pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
+	pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
+	pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+
+	/* CpuControl is in \_PR.CPU0, 6 bytes */
+	pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
+	pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
+
+	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
+	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
+
+	pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
+	pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+
+	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
+					* the contents of the PM registers at
+					* index 60-6B to decode ACPI I/O address.
+					* AcpiSmiEn & SmiCmdEn*/
+	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
+
+	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}

Added: trunk/src/mainboard/advansus/a785e-i/get_bus_conf.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/get_bus_conf.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/multicore.h>
+#endif
+#include <cpu/amd/amdfam10_sysconf.h>
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+int bus_isa;
+u8 bus_rs780[11];
+u8 bus_sb800[3];
+u32 apicid_sb800;
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+	0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+	0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_rs780;
+u32 sbdn_sb800;
+
+extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+	u32 apicid_base;
+	device_t dev;
+	int i, j;
+
+	if (get_bus_conf_done == 1)
+		return;		/* do it only once */
+	get_bus_conf_done = 1;
+
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+	for (i = 0; i < sysconf.hc_possible_num; i++) {
+		sysconf.pci1234[i] = pci1234x[i];
+		sysconf.hcdn[i] = hcdnx[i];
+	}
+
+	get_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
+	sbdn_rs780 = sysconf.sbdn;
+	sbdn_sb800 = 0;
+
+	for (i = 0; i < 3; i++) {
+		bus_sb800[i] = 0;
+	}
+	for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
+		bus_rs780[i] = 0;
+	}
+
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+	bus_type[0] = 1;	/* pci */
+
+	bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb800[0] = bus_rs780[0];
+
+	bus_type[bus_rs780[0]] = 1;
+
+	/* sb800 */
+	dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+	if (dev) {
+		bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb800[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	for (i = 0; i < 4; i++) {
+		dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x15, i));
+		if (dev) {
+			bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+			bus_isa++;
+		}
+	}
+	for (j = bus_sb800[2]; j < bus_isa; j++)
+		bus_type[j] = 1;
+
+	/* rs780 */
+	for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
+		dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
+		if (dev) {
+			bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			if(255 != bus_rs780[i]) {
+				bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+				bus_isa++;
+				bus_type[bus_rs780[i]] = 1; /* PCI bus. */
+			}
+		}
+	}
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+	apicid_sb800 = apicid_base + 0;
+}

Added: trunk/src/mainboard/advansus/a785e-i/irq_tables.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/irq_tables.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			    u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+
+extern u8 bus_isa;
+extern u8 bus_rs780[8];
+extern u8 bus_sb800[2];
+extern unsigned long sbdn_sb800;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb800[0];
+	pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+	slot_num++;
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+}

Added: trunk/src/mainboard/advansus/a785e-i/mainboard.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/mainboard.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+//#include <southbridge/amd/sb800/sb800.h>
+#include "pmio.h"
+#include "chip.h"
+
+uint64_t uma_memory_base, uma_memory_size;
+
+u8 is_dev3_present(void);
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+void enable_int_gfx(void);
+
+/* GPIO6. */
+void enable_int_gfx(void)
+{
+	u8 byte;
+
+	volatile u8 *gpio_reg;
+
+	pm_iowrite(0xEA, 0x01);	/* diable the PCIB */
+	/* Disable Gec */
+	byte = pm_ioread(0xF6);
+	byte |= 1;
+	pm_iowrite(0xF6, byte);
+	/* make sure the fed80000 is accessible */
+	byte = pm_ioread(0x24);
+	byte |= 1;
+	pm_iowrite(0x24, byte);
+
+	gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
+
+	*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
+	*(gpio_reg + 170) = 0x1; /* gpio_gate */
+
+	gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
+
+	*(gpio_reg + 0x6) = 0x8;
+	*(gpio_reg + 170) = 0x0;
+}
+
+void set_pcie_dereset()
+{
+}
+
+void set_pcie_reset(void)
+{
+}
+
+u8 is_dev3_present(void)
+{
+	return 0;
+}
+
+
+/*************************************************
+* enable the dedicated function in A785E-I board.
+* This function called early than rs780_enable.
+*************************************************/
+static void a785e_i_enable(device_t dev)
+{
+	/* Leave it for furture use. */
+	/* struct mainboard_config *mainboard =
+	   (struct mainboard_config *)dev->chip_info; */
+
+	printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev);
+
+#if (CONFIG_GFXUMA == 1)
+	msr_t msr, msr2;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	/* refer to UMA Size Consideration in 780 BDG. */
+	switch (msr.lo) {
+	case 0x10000000:	/* 256M system memory */
+		uma_memory_size = 0x4000000;	/* 64M recommended UMA */
+		break;
+
+	case 0x20000000:	/* 512M system memory */
+		uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+		break;
+
+	default:		/* 1GB and above system memory */
+		uma_memory_size = 0x10000000;	/* 256M recommended UMA */
+		break;
+	}
+
+	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+		    __func__, uma_memory_size, uma_memory_base);
+
+	/* TODO: TOP_MEM2 */
+#else
+	uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+	uma_memory_base = 0x38000000;	/* 1GB  system memory supposed */
+#endif
+
+	set_pcie_dereset();
+	enable_int_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	/* UMA is removed from system memory in the northbridge code, but
+	 * in some circumstances we want the memory mentioned as reserved.
+ 	 */
+#if (CONFIG_GFXUMA == 1)
+	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+		    uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+			    uma_memory_size);
+#endif
+	return 0;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("ADVANSUS A785E-I Mainboard")
+	.enable_dev = a785e_i_enable,
+};

Added: trunk/src/mainboard/advansus/a785e-i/mb_sysconf.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/mb_sysconf.h	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+	u8 bus_isa;
+	u8 bus_8132_0;
+	u8 bus_8132_1;
+	u8 bus_8132_2;
+	u8 bus_8111_0;
+	u8 bus_8111_1;
+	u8 bus_8132a[31][3];
+	u8 bus_8151[31][2];
+
+	u32 apicid_8111;
+	u32 apicid_8132_1;
+	u32 apicid_8132_2;
+	u32 apicid_8132a[31][2];
+	u32 sbdn3;
+	u32 sbdn3a[31];
+	u32 sbdn5[31];
+	u32 bus_type[256];
+};
+
+#endif

Added: trunk/src/mainboard/advansus/a785e-i/mptable.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/mptable.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,160 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include "pmio.h"
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern int bus_isa;
+extern u8 bus_rs780[11];
+extern u8 bus_sb800[2];
+extern u32 apicid_sb800;
+extern u32 bus_type[256];
+extern u32 sbdn_rs780;
+extern u32 sbdn_sb800;
+
+u8 intr_data[] = {
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
+};
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	u32 dword;
+	u8 byte;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LAPIC_ADDR);
+
+	smp_write_processors(mc);
+
+	get_bus_conf();
+
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/* I/O APICs:   APIC ID Version State   Address */
+
+	dword = 0;
+	dword = pm_ioread(0x34) & 0xF0;
+	dword |= (pm_ioread(0x35) & 0xFF) << 8;
+	dword |= (pm_ioread(0x36) & 0xFF) << 16;
+	dword |= (pm_ioread(0x37) & 0xFF) << 24;
+	smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#if CONFIG_GENERATE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
+
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);
+
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+	/* on board NIC & Slot PCIE.  */
+	/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
+/* 	PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
+	PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
+	/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
+	PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
+	/* configuration B doesnt need dev 5,6,7 */
+	/*
+	 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
+	 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
+	 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
+	 */
+	PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
+	PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum =
+	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+		     mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}

Added: trunk/src/mainboard/advansus/a785e-i/pmio.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/pmio.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "pmio.h"
+
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
+{
+	outb(reg, port_base);
+	outb(value, port_base + 1);
+}
+
+static u8 pmio_read_index(u16 port_base, u8 reg)
+{
+	outb(reg, port_base);
+	return inb(port_base + 1);
+}
+
+void pm_iowrite(u8 reg, u8 value)
+{
+	pmio_write_index(PM_INDEX, reg, value);
+}
+
+u8 pm_ioread(u8 reg)
+{
+	return pmio_read_index(PM_INDEX, reg);
+}
+
+void pm2_iowrite(u8 reg, u8 value)
+{
+	pmio_write_index(PM2_INDEX, reg, value);
+}
+
+u8 pm2_ioread(u8 reg)
+{
+	return pmio_read_index(PM2_INDEX, reg);
+}

Added: trunk/src/mainboard/advansus/a785e-i/pmio.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/pmio.h	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _PMIO_H_
+#define _PMIO_H_
+
+#define PM_INDEX	0xCD6
+#define PM_DATA		0xCD7
+#define PM2_INDEX	0xCD0
+#define PM2_DATA	0xCD1
+
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+#endif

Added: trunk/src/mainboard/advansus/a785e-i/reset.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/reset.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes, htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for (i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}

Added: trunk/src/mainboard/advansus/a785e-i/resourcemap.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/resourcemap.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,278 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration regin i
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+	};
+
+	int max;
+	max = ARRAY_SIZE(register_values);
+	setup_resource_map(register_values, max);
+}

Added: trunk/src/mainboard/advansus/a785e-i/romstage.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/advansus/a785e-i/romstage.c	Sat May  7 11:15:02 2011	(r6561)
@@ -0,0 +1,279 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+//#define SYSTEM_TYPE 0	/* SERVER */
+#define SYSTEM_TYPE 1	/* DESKTOP */
+//#define SYSTEM_TYPE 2	/* MOBILE */
+
+//used by incoherent_ht
+#define FAM10_SCAN_PCI_BUS 0
+#define FAM10_ALLOCATE_IO_RANGE 0
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <cpu/amd/model_10xxx_rev.h>
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdfam10/reset_test.c"
+#include <console/loglevel.h>
+#include "cpu/x86/bist.h"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include <SbEarly.h>
+#include <SBPLATFORM.h> /* SB OEM constants */
+#include <southbridge/amd/cimx_wrapper/sb800/smbus.h>
+#include "northbridge/amd/amdfam10/debug.c"
+
+static void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+static int spd_read_byte(u32 device, u32 address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/pci.c"
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#if CONFIG_UPDATE_CPU_MICROCODE
+#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "northbridge/amd/amdfam10/early_ht.c"
+#include "spd.h"
+
+#include <reset.h>
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
+//FIXME copyed from sb800
+#include <pmio.h>
+static void sb800_clk_output_48Mhz(void)
+{
+        /* AcpiMMioDecodeEn */
+        u8 reg8;
+        reg8 = pm_ioread(0x24);
+        reg8 |= 1;
+        reg8 &= ~(1 << 1);
+        pm_iowrite(0x24, reg8);
+
+        *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+        *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
+	u32 bsp_apicid = 0, val;
+	msr_t msr;
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		/* mov bsp to bus 0xff when > 8 nodes */
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		//enable port80 decoding and southbridge poweron init
+		sb_poweron_init();
+	}
+
+	post_code(0x30);
+
+	if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
+		/* All cores run this but the BSP(node0,core0) is the only core that returns. */
+	}
+
+	post_code(0x32);
+
+	enable_rs780_dev8();
+	sb800_clk_output_48Mhz();
+
+	w83627hf_set_clksel_48(PNP_DEV(0x2e, 0));
+	w83627hf_enable_serial(0, CONFIG_TTYS0_BASE);
+
+	uart_init();
+	console_init();
+	printk(BIOS_DEBUG, "\n");
+
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+	printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	/* Setup sysinfo defaults */
+	set_sysinfo_in_ram(0);
+
+#if CONFIG_UPDATE_CPU_MICROCODE
+	update_microcode(val);
+#endif
+	post_code(0x33);
+
+	cpuSetAMDMSR();
+	post_code(0x34);
+
+	amd_ht_init(sysinfo);
+	post_code(0x35);
+
+	/* Setup nodes PCI space and start core 0 AP init. */
+	finalize_node_setup(sysinfo);
+
+	/* Setup any mainboard PCI settings etc. */
+	setup_mb_resource_map();
+	post_code(0x36);
+
+	/* wait for all the APs core0 started by finalize_node_setup. */
+	/* FIXME: A bunch of cores are going to start output to serial at once.
+	   It would be nice to fixup prink spinlocks for ROM XIP mode.
+	   I think it could be done by putting the spinlock flag in the cache
+	   of the BSP located right after sysinfo.
+	 */
+	wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* Core0 on each node is configured. Now setup any additional cores. */
+	printk(BIOS_DEBUG, "start_other_cores()\n");
+	start_other_cores();
+	post_code(0x37);
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+
+	post_code(0x38);
+
+	/* run _early_setup before soft-reset. */
+	rs780_early_setup();
+
+#if CONFIG_SET_FIDVID == 1
+	msr = rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	post_code(0x39);
+
+	if (!warm_reset_detect(0)) {			// BSP is node 0
+		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+	} else {
+		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
+	}
+
+	post_code(0x3A);
+
+	/* show final fid and vid */
+	msr=rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+#endif
+
+	rs780_htinit();
+
+	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	if (!warm_reset_detect(0)) {
+		print_info("...WARM RESET...\n\n\n");
+		soft_reset();
+		die("After soft_reset_x - shouldn't see this message!!!\n");
+	}
+
+	post_code(0x3B);
+
+	/* It's the time to set ctrl in sysinfo now; */
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+	post_code(0x40);
+
+//	die("Die Before MCT init.");
+
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
+	raminit_amdmct(sysinfo);
+	post_code(0x41);
+
+/*
+	dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
+*/
+
+//	ram_check(0x00200000, 0x00200000 + (640 * 1024));
+//	ram_check(0x40200000, 0x40200000 + (640 * 1024));
+
+//	die("After MCT init before CAR disabled.");
+
+	rs780_before_pci_init();
+
+	post_code(0x42);
+	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
+	post_code(0x43);	// Should never see this post code.
+}
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+
+	return 0;
+}



From graeme.russ at gmail.com  Sat May  7 14:39:47 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Sat, 07 May 2011 22:39:47 +1000
Subject: [coreboot] [U-Boot] u-boot on x86 reloaded
In-Reply-To: <4DC148A7.4050007@assembler.cz>
References: <4DC11437.9090405@assembler.cz> <4DC13A12.5080509@gmail.com>
	<4DC148A7.4050007@assembler.cz>
Message-ID: <4DC53D93.5030102@gmail.com>

Hi Rodulf,

On 04/05/11 22:37, Rudolf Marek wrote:
> Hello all,
> 

[snip]

>>   - The build warnings and errors you incurred are probably fixed in
>> mainline (x86 is a bit of a forgotten cousin which gets broken when global
>> patches are made to Makefile, linker scripts etc). If you still have
>> problems compiling the latest U-Boot git head, please post them to the
>> mailing list and I'll sort them out ASAP
> 
> The links to the coreboot mailing list contain some patches.
> 

Ok - I see two fixes needed (one in bios_setup.c and one in realmode.c).
These are both effectively in my realmode re-write, but if you can send
through a patch to fix them in the meantime, that would be great

>>   - When launching U-Boot as a payload from Coreboot, you really don't need
>> to worry about what is at the end of the image (reset vector and jump to
>> protected mode). All the fun begins at the first byte of u-boot.bin which
>> is the first line of code in start.S
> 
> I think it jumps to _start which is 32 bit entry point. The coreboot is in
> flat mode 32bit.
> 

If you look at start.S, you will see a tiny bit of code before _start which
is the 'warm boot' entry point:

	cli
	cld

	/* Turn of cache (this might require a 486-class CPU) */
	movl	%cr0, %eax
	orl	$(X86_CR0_NW | X86_CR0_CD), %eax
	movl	%eax, %cr0
	wbinvd

	/* Tell 32-bit code it is being entered from an in-RAM copy */
	movw	$GD_FLG_WARM_BOOT, %bx

Looking at coreboot in src/arch/x86/lib/c_start.S it appears coreboot and
U-Boot use the same GDT for code (0x10) and data (0x18) in a flat protected
mode configuration. We can probably make that a little more robust by
jumping over the segment register loads during warm-boot and just use
whatever coreboot gives us. U-Boot will wipe it all clean later anyway (see
arch/x86/cpu/x86_cpu_init_r) - x86_cpu_init_r calls reload_gdt() after
U-Boot has been relocated.

So if you build u-boot.bin with TEXT_BASE set wherever it will end up in
the coreboot image then you can just have coreboot jump to TEXT_BASE.

Now as for booting an ELF image, maybe the linker script needs to be
tweaked to set the entry point to _x86boot_start rather than _start

>>   - CONFIG_SYS_INIT_SP_ADDR is a temporary stack pointer which is used
>> during the relocation of U-Boot from ROM (Flash) into SDRAM. Typically the
>> CPU's Cache-As-RAM (CAR) capability is used. However, if SDRAM is already
>> initialised, you can set CONFIG_SYS_INIT_SP_ADDR to anywhere in SDRAM that
>> will not get clobbered by the relocation
> 
> Yes I set it to 256KB boundary.

Sounds reasonable - but you really need to set it to somewhere you know
there is physical RAM. Maybe this could be passed in a register in the warm
boot scenario and the address determined by coreboot

[big snip - we'll deal with real-mode / BIOS later]

>> I would really like to see some U-Boot patches on the mailing list -
>> Technically U-Boot is meant to be a stand-alone and self-sufficient, but I
>> think for x86 there is merit in creating board configuration that gets
>> boot-strapped by Coreboot (we just need to make sure the documentation is
>> up-to-scratch)
> 
> The patches are just now on coreboot mailing list. It is just a hack,
> because there are places which needs to be fixed, the computation of place
> for the realmode and bios sections needs to be fixed.  I added the coreboot
> as a board and subarchitecture.

I've had a chance to look at them, and the impact on U-Boot is surprisingly
minimal. A few comments:

-PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -march=i386 -Werror
+PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -march=i386

NACK - Do not remove -Werror

-LDPPFLAGS += -DRESET_SEG_START=0xffff0000
+LDPPFLAGS += -DRESET_SEG_START=0xFF0000

NACK - As mentioned above, I see no reason to mess with this. Set TEXT_BASE
to be the location of U-Boot in the coreboot flash image and simply jump to it.

In /arch/x86/cpu/interrupts.c you add setup_i8259() and call it in
cpu_init_interrupts() which is called from cpu_init_r() - This is the wrong
place to be setting up the PIC (this file initialises the CPU interrupt
sub-system, not the external glue logic). And how is setup_i8259()
different from interrupt_init() found in arch/x86/lib/pcat_interrupt.c?

Now the problem could be that interrupt_init() is called after cpu_init_r()
- i.e. the CPU interrupt sub-system is setup before the PIC has been
configured. Maybe the PIC should be configured prior to relocation (and
therefore prior to initialisation of the CPU interrupt sub-system). Lets
look at moving that to board_early_init_f()

Apart from that, the patches look 'promising' ;)

Now, for me to officially consider them, they need to be posted to the
U-Boot mailing list using git format-patch / git send-email AFTER they have
been run through checkpatch (which can be found in the Linux source under
scripts/). You patches will end up in patchwork where they will be managed

> 
> What is specific is that we will need to copy "MPtable" "PIR" and "RSDP"
> pointer to F-segment just after the bios section. The memory map can be
> read out of coreboot tables stored in high mem. Also a PCI mem stuff should
> be fixed in u-boot.
> 
> Also if we get rid of the .bios and .realmode section then the problem that
> those two sections are not relocated to end of memory disappears.

I think these can be dealt with later

> 
>> Looking forward to moving this forward
> 
> Good. Please check the patches on coreboot ml and feel free to join
> #coreboot channel. I'm in both now as "ruik".

I've re-joined the coreboot ml. Any discussions on U-Boot patches need to
be conducted on the U-Boot ml so we can all comment.

> 
> Thanks,
> Rudolf
> 

Regards,

Graeme



From puneet.maillist at gmail.com  Sat May  7 14:43:28 2011
From: puneet.maillist at gmail.com (Puneet Goel)
Date: Sat, 7 May 2011 18:13:28 +0530
Subject: [coreboot] bootsplash patch for 2.6.38
Message-ID: <BANLkTi=oXSQUa-N27XVnjSLci9QjuZ6B5g@mail.gmail.com>

Hi

Can anyone tell me if bootsplash patch is available for 2.6.38 kernel over
atyfb. I am not using vesafb

Thanks
Puneet
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From peter at stuge.se  Sat May  7 16:59:04 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 7 May 2011 16:59:04 +0200
Subject: [coreboot] [RFC] cheapish and free usb spi flashing device
In-Reply-To: <201104272042.p3RKgaCQ021700@mail2.student.tuwien.ac.at>
References: <201104220134.p3M1Y7sP015027@mail2.student.tuwien.ac.at>
	<20110422030832.21364.qmail@stuge.se>
	<201104272042.p3RKgaCQ021700@mail2.student.tuwien.ac.at>
Message-ID: <20110507145904.7599.qmail@stuge.se>

Stefan Tauner wrote:
> > > right now my plan is the following:
> > > an avr atmegaXXu2 is connected via usb and implements the serprog
> > > protocol
> > 
> > Please do not! Make good use of USB and design a protocol that
> > actually takes advantage of relevant USB features, instead of
> > pretending that USB is a serial port, which is really lame.
> 
> what features do you think _are_ relevant?

The fundamental feature is that USB communication is highly
structured on the very lowest level. It is a tremendous waste not to
take full advantage of this property.


> > USB is a packet bus. Making it behave like a dumb stream of bytes is
> > almost never a good idea.
> 
> if i had to transfer the content of a file i would choose tcp instead
> of udp. this is quite similar imho.

That comparison isn't valid because USB does not always resemble UDP,
only when using isochronouse transfers. Consider this:

Would you use telnet+Zmodem to transfer the file, or rather FTP?

(Remember that you are implementing both ends of the connection and
disregard the complications in FTP caused by worldwide NAT.)


> there are several drawbacks:
> - we cant tunnel it as easily (e.g. over tcp like serprog)

Any protocol can be tunneled over any other protocol. In fact I think
what I suggest would be even easier to network enable than serprog.


> - everything gets way more complicated on the microcontroller

I don't know about *way* more, but yes, more complicated. The flip
side is that the interface is tremendously more elegant, and easy to
use. This is more important than saving a few hours of development
IMNSHO.


> i dont see a lot of performance improvements from it either.

Not about performance, about usability and elegance. Concepts not
very common in software development worldwide. But in fact they may
be the only worthy goals in software development. They also tend to
go hand in hand.


> maybe i am missing something though. please layout your basic ideas
> how an USB flashing protocol should look like,

I've tried to explain the general idea to several people but noone
has really gotten what I mean, so to answer your question I have been
thinking a bit more about the details of the protocol.

The design goal is to be able to cat a .rom file into a device node
created by standard Linux kernel drivers, and have that .rom file
written to a flash chip. In practise the goal is unreachable because
the kernel doesn't expose endpoints as device nodes anymore, but we
want to come as close to the goal as possible. Consider a usbcat
program being used instead of regular cat.

The question is what other information the hardware must be given
before it can accomplish this. This is the SPI flashing data model
that I have been asking for several times.

1. Flash bus - SPI or LPC/FWH (only SPI first, but keep LPC in mind)
2. What SPI commands to use for identify, erase and program
3. Max SCK speed
(4. How to do identify, erase and program on LPC)

I think flashrom already knows these things except maybe 3, the data
is just not exported in any suitable way yet.

So far I can think of two ideas for how this data is sent to a
microcontroller:

1. Oneshot transfer of a datastructure with some or all parameters,
followed by one single transfer of the data to be programmed

2. An instruction set is created that gets executed by a simple state
machine in the microcontroller, and instead of the parameterized data
structure above, one microcode snippet would be sent for each
operation identify/erase/program.

Of course it's also possible to do both of the above, and in fact
they might complement each other. 1. assumes that we can design a
very future proof data model for SPI programming, or the
microcontroller firmware might have to be updated for a future SPI
chip. While I think we could actually do this, it's still nice to
have a completely generic interface such as 2. since then the user
can always create the needed microcode snippets from a data sheet,
without having to upgrade the firmware. (OTOH, the LPC1343 is
extremely easy to reprogram, so this may be moot as long as
microcontroller developers are eager and quick.)

I hope this is not too abstract for people to understand the idea?

To spell it out even more, in USB terms, there would be, at least:

* a control transfer to set the SPI clock speed
* a control transfer to set the current address in memory
* a control transfer to switch power supply to the flash chip
* bulk out sends SPI bytes
* bulk in reads SPI bytes

The above is the simplest interface, even simpler and more stupid
than any of 1. and 2. I describe above. But it would be the minimum
to start with, to guarantee a completely future proof hardware. It's
also easy to implement.

The next step would be:

* a control transfer to set command(s) used for identify
* a control transfer to set command(s) used for erase
* a control transfer to set command(s) used for program

These command(s) are not just one byte, a "language" (data model 1.,
or microcode 2.) is needed to express the various sequences.


> btw do we want to support non-spi flashes at all?

Yes, but one thing at a time. The microcontroller will not likely
have LPC master hardware so it will have to be bit-banged, and will
thus not be too fast. Good use of USB to speak SPI is more important.


> > > i was also thinking about an offline mode which uses an SD-card
..
> > And the filesystems are buggy as well.
> we would not need one... wear leveling is done by the card and we
> only need a continuous block.

Then the use of the SD card as media is significantly reduced,
because a PC with a card reader can not use the default file transfer
tools (Explorer, Finder, mount/mtools) to put an image to-be-flashed
onto the card.


//Peter



From kevin at koconnor.net  Sat May  7 19:01:59 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 7 May 2011 13:01:59 -0400
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60
In-Reply-To: <874o5ag9ta.fsf@begreifnix.stackframe.org>
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
	<20110503203319.GB3715@coreboot.org>
	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>
	<874o5ag9ta.fsf@begreifnix.stackframe.org>
Message-ID: <20110507170159.GA29093@morn.localdomain>

On Wed, May 04, 2011 at 10:16:17AM +0200, Sven Schnelle wrote:
> >>> Will do. But right now i have the problem that the Keyboard isn't
> >>> working on cold boot - seabios is probably started so early that some
> >>> hardware parts are not finished with reset or similar things.
[...]
> I've just modified seabios to resend commands when 0xfe is received as a
> quick hack. It makes my keyboard working again. I'm not sure if SeabIOS
> should handle 0xfe as RESEND or not - have not monitored much Keyboards,
> and don't know wether this has any side effects.

Some ps2 ports send NAK (0xfe) when there is no keyboard plugged in.
The detection for NAK was added so that it doesn't take a full second
to recognize that no keyboard is present.  The patch you sent would
loop infinitely in this situation.

It's possible to have ps2_send_byte() attempt a resend on each NAK and
use the timer to detect when to stop.  However, that will re-introduce
the problem of having to wait a second when there is no keyboard
present.

Do you know how long it takes for your keyboard to become responsive?
(You can pass "-n" to tools/readserial.py to have it report wall times
instead of adjusted times.)

Have you considerd using a USB keyboard?  :-)

BTW, if you want to improve boot time, setting
CONFIG_THREAD_OPTIONROMS should help.

-Kevin



From kevin at koconnor.net  Sat May  7 19:14:34 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 7 May 2011 13:14:34 -0400
Subject: [coreboot] [U-Boot] u-boot on x86 reloaded
In-Reply-To: <4DC13A12.5080509@gmail.com>
References: <4DC11437.9090405@assembler.cz>
 <4DC13A12.5080509@gmail.com>
Message-ID: <20110507171434.GA32066@morn.localdomain>

On Wed, May 04, 2011 at 09:35:46PM +1000, Graeme Russ wrote:
>  - I'm in the middle of re-writing the entire real-mode switch code and
> real-mode support in U-Boot. The new code allows you to write real-mode
> code in C - I even have the Linux real-mode printf ported :) This will make
> writing your own 'BIOS' code for your board a lot easier

FYI - SeaBIOS ( http://seabios.org/ ) uses gcc for real-mode code.
Indeed, the name "SeaBIOS" is a play on words - it's a BIOS written in
C code.

-Kevin



From paulepanter at users.sourceforge.net  Sat May  7 20:03:25 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sat, 07 May 2011 20:03:25 +0200
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60
In-Reply-To: <20110507170159.GA29093@morn.localdomain>
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
	<20110503203319.GB3715@coreboot.org>
	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>
	<874o5ag9ta.fsf@begreifnix.stackframe.org>
	<20110507170159.GA29093@morn.localdomain>
Message-ID: <1304791405.2047.55.camel@mattotaupa>

Am Samstag, den 07.05.2011, 13:01 -0400 schrieb Kevin O'Connor:
> On Wed, May 04, 2011 at 10:16:17AM +0200, Sven Schnelle wrote:
> > >>> Will do. But right now i have the problem that the Keyboard isn't
> > >>> working on cold boot - seabios is probably started so early that some
> > >>> hardware parts are not finished with reset or similar things.
> [...]
> > I've just modified seabios to resend commands when 0xfe is received as a
> > quick hack. It makes my keyboard working again. I'm not sure if SeabIOS
> > should handle 0xfe as RESEND or not - have not monitored much Keyboards,
> > and don't know wether this has any side effects.
> 
> Some ps2 ports send NAK (0xfe) when there is no keyboard plugged in.
> The detection for NAK was added so that it doesn't take a full second
> to recognize that no keyboard is present.  The patch you sent would
> loop infinitely in this situation.
> 
> It's possible to have ps2_send_byte() attempt a resend on each NAK and
> use the timer to detect when to stop.  However, that will re-introduce
> the problem of having to wait a second when there is no keyboard
> present.
> 
> Do you know how long it takes for your keyboard to become responsive?
> (You can pass "-n" to tools/readserial.py to have it report wall times
> instead of adjusted times.)
> 
> Have you considerd using a USB keyboard?  :-)

I do not know how to interpret your ?:-)?, but to clarify Sven is using
coreboot on his laptop so the non-working keyboard is the build in
keyboard.

> BTW, if you want to improve boot time, setting
> CONFIG_THREAD_OPTIONROMS should help.


Thanks,

Paul
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From svens at stackframe.org  Sat May  7 20:48:45 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sat, 07 May 2011 20:48:45 +0200
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60
In-Reply-To: <20110507170159.GA29093@morn.localdomain> (Kevin O'Connor's
	message of "Sat\, 7 May 2011 13\:01\:59 -0400")
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
	<20110503203319.GB3715@coreboot.org>
	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>
	<874o5ag9ta.fsf@begreifnix.stackframe.org>
	<20110507170159.GA29093@morn.localdomain>
Message-ID: <87mxiye48i.fsf@begreifnix.stackframe.org>

Kevin O'Connor <kevin at koconnor.net> writes:

> On Wed, May 04, 2011 at 10:16:17AM +0200, Sven Schnelle wrote:
>> >>> Will do. But right now i have the problem that the Keyboard isn't
>> >>> working on cold boot - seabios is probably started so early that some
>> >>> hardware parts are not finished with reset or similar things.
> [...]
>> I've just modified seabios to resend commands when 0xfe is received as a
>> quick hack. It makes my keyboard working again. I'm not sure if SeabIOS
>> should handle 0xfe as RESEND or not - have not monitored much Keyboards,
>> and don't know wether this has any side effects.
>
> Some ps2 ports send NAK (0xfe) when there is no keyboard plugged in.
> The detection for NAK was added so that it doesn't take a full second
> to recognize that no keyboard is present.  The patch you sent would
> loop infinitely in this situation.

Yes, the patch was only for testing purposes. :)

I feared that are controllers out there that behave like this, so i have
to find another solution.

> It's possible to have ps2_send_byte() attempt a resend on each NAK and
> use the timer to detect when to stop.  However, that will re-introduce
> the problem of having to wait a second when there is no keyboard
> present.

Yes.

> Do you know how long it takes for your keyboard to become responsive?
> (You can pass "-n" to tools/readserial.py to have it report wall times
> instead of adjusted times.)

It takes something about 0.8s, according to serial output. I've already
monitored the EC registers, but there seems to be no bit that
can be used as indicator wether EC is ready for Keyboard action or not.

> Have you considerd using a USB keyboard?  :-)

Well - it's a Thinkpad. :-)

> BTW, if you want to improve boot time, setting
> CONFIG_THREAD_OPTIONROMS should help.

I already have that option set. ;)

Sven.



From kevin at koconnor.net  Sat May  7 21:05:03 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 7 May 2011 15:05:03 -0400
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60
In-Reply-To: <87mxiye48i.fsf@begreifnix.stackframe.org>
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
	<20110503203319.GB3715@coreboot.org>
	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>
	<874o5ag9ta.fsf@begreifnix.stackframe.org>
	<20110507170159.GA29093@morn.localdomain>
	<87mxiye48i.fsf@begreifnix.stackframe.org>
Message-ID: <20110507190502.GA4560@morn.localdomain>

On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
> Kevin O'Connor <kevin at koconnor.net> writes:
> > Do you know how long it takes for your keyboard to become responsive?
> > (You can pass "-n" to tools/readserial.py to have it report wall times
> > instead of adjusted times.)
> 
> It takes something about 0.8s, according to serial output.

Does adding "msleep(800)" to the top of ps2port.c:keyboard_init()
help?

>I've already
> monitored the EC registers, but there seems to be no bit that
> can be used as indicator wether EC is ready for Keyboard action or not.

The logs you posted show the i8042 controller responsive when SeaBIOS
starts talking to it.  So, I wonder if it's the keyboard that is still
powering up (instead of the superIO).  (Of course, if the EC contains
both the keyboard and superIO, then this is irrelevant.)

> > BTW, if you want to improve boot time, setting
> > CONFIG_THREAD_OPTIONROMS should help.
> 
> I already have that option set. ;)

Oh, okay.  The logs you posted show this option disabled.

When this option is enabled, the "init ps2port" message should appear
before the VGA init.  It should also eliminate any wait at the boot
prompt, as the boot menu delay should overlap with your hard drive
spin-up.

-Kevin



From kevin at koconnor.net  Sat May  7 21:21:30 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 7 May 2011 15:21:30 -0400
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60
In-Reply-To: <87mxiye48i.fsf@begreifnix.stackframe.org>
References: <E1QHASO-00072o-E3@ra.coresystems.de>
	<1304410638.13481.40.camel@mattotaupa>
	<87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
	<20110503203319.GB3715@coreboot.org>
	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>
	<874o5ag9ta.fsf@begreifnix.stackframe.org>
	<20110507170159.GA29093@morn.localdomain>
	<87mxiye48i.fsf@begreifnix.stackframe.org>
Message-ID: <20110507192130.GA6004@morn.localdomain>

On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
> Kevin O'Connor <kevin at koconnor.net> writes:
> > Some ps2 ports send NAK (0xfe) when there is no keyboard plugged in.
> > The detection for NAK was added so that it doesn't take a full second
> > to recognize that no keyboard is present.  The patch you sent would
> > loop infinitely in this situation.
> 
> Yes, the patch was only for testing purposes. :)
> 
> I feared that are controllers out there that behave like this, so i have
> to find another solution.

How about something like (untested):

--- a/src/ps2port.c
+++ b/src/ps2port.c
@@ -438,9 +438,14 @@ keyboard_init(void *data)
 
     /* ------------------- keyboard side ------------------------*/
     /* reset keyboard and self test  (keyboard side) */
-    ret = ps2_kbd_command(ATKBD_CMD_RESET_BAT, param);
-    if (ret)
-        return;
+    u64 end = calc_future_tsc(4000);
+    for (;;) {
+        ret = ps2_kbd_command(ATKBD_CMD_RESET_BAT, param);
+        if (!ret)
+            break;
+        if (check_tsc(end))
+            return;
+    }
     if (param[0] != 0xaa) {
         dprintf(1, "keyboard self test failed (got %x not 0xaa)\n", param[0]);
         return;

If it works, the 4000 could be turned into a config option.

-Kevin



From vikram186 at gmail.com  Sat May  7 21:04:16 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Sun, 08 May 2011 00:34:16 +0530
Subject: [coreboot] [PATCH] Replace the values of APIC timer init with macros
Message-ID: <4DC597B0.4050204@gmail.com>

This replaces the fixed shift values in the apic timer init with macros.

Signed-off by: Vikram Narayanan <vikram186 at gmail.com>
---
--- a/src/cpu/x86/lapic/apic_timer.c	Sun May  8 00:18:12 2011
+++ b/src/cpu/x86/lapic/apic_timer.c	Sun May  8 00:08:54 2011
@@ -36,7 +36,7 @@
 	msr_t fsb_clock_sts;
 
 	/* Set the apic timer to no interrupts and periodic mode */
-	lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 << 0));
+	lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED));
 
 	/* Set the divider to 1, no divider */
 	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);

Thanks,
Vikram




From stefan.reinauer at coreboot.org  Sat May  7 22:19:23 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 07 May 2011 13:19:23 -0700
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60
In-Reply-To: <20110507190502.GA4560@morn.localdomain>
References: <E1QHASO-00072o-E3@ra.coresystems.de>	<1304410638.13481.40.camel@mattotaupa>	<87r58gfb0q.fsf@begreifnix.stackframe.org>	<20110503182932.GA18695@coreboot.org>	<87ei4ffu6i.fsf@begreifnix.stackframe.org>	<20110503203319.GB3715@coreboot.org>	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>	<874o5ag9ta.fsf@begreifnix.stackframe.org>	<20110507170159.GA29093@morn.localdomain>	<87mxiye48i.fsf@begreifnix.stackframe.org>
	<20110507190502.GA4560@morn.localdomain>
Message-ID: <4DC5A94B.20609@coreboot.org>

On 5/7/11 12:05 PM, Kevin O'Connor wrote:
> On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
>> Kevin O'Connor<kevin at koconnor.net>  writes:
>>> Do you know how long it takes for your keyboard to become responsive?
>>> (You can pass "-n" to tools/readserial.py to have it report wall times
>>> instead of adjusted times.)
>> It takes something about 0.8s, according to serial output.
> Does adding "msleep(800)" to the top of ps2port.c:keyboard_init()
> help?
Please don't do things like that. Probing the hardware is much better 
than a fixed delay.

The various i8042 reimplementations out there are quite ugly and each in 
its specific way.

Maybe we should look at the coreboot mainboard type in order to decide 
whether to poll the hardware or drop out on the first 0xfe answer. Or at 
least make the behavior configurable in Kconfig?

> The logs you posted show the i8042 controller responsive when SeaBIOS
> starts talking to it.  So, I wonder if it's the keyboard that is still
> powering up (instead of the superIO).

Not unlikely. It might also just be some crappy implementation of EC 
firmware.

Stefan




From stefan.reinauer at coreboot.org  Sat May  7 22:22:50 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 07 May 2011 13:22:50 -0700
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60
In-Reply-To: <20110507190502.GA4560@morn.localdomain>
References: <E1QHASO-00072o-E3@ra.coresystems.de>	<1304410638.13481.40.camel@mattotaupa>	<87r58gfb0q.fsf@begreifnix.stackframe.org>	<20110503182932.GA18695@coreboot.org>	<87ei4ffu6i.fsf@begreifnix.stackframe.org>	<20110503203319.GB3715@coreboot.org>	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>	<874o5ag9ta.fsf@begreifnix.stackframe.org>	<20110507170159.GA29093@morn.localdomain>	<87mxiye48i.fsf@begreifnix.stackframe.org>
	<20110507190502.GA4560@morn.localdomain>
Message-ID: <4DC5AA1A.7090008@coreboot.org>

On 5/7/11 12:05 PM, Kevin O'Connor wrote:
> On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
>> Kevin O'Connor<kevin at koconnor.net>  writes:
>>> Do you know how long it takes for your keyboard to become responsive?
>>> (You can pass "-n" to tools/readserial.py to have it report wall times
>>> instead of adjusted times.)
>> It takes something about 0.8s, according to serial output.
Maybe we can add some "shoot and run" ps2 initialization code to 
coreboot that runs before most other code, giving the keyboard or kbc 
time to initialize while we do all the other stuff.

Have we considered threading in coreboot? It seems the time we spend in 
ramstage is unsignificant and the effort of multitasking in romstage is 
not worth the trouble.






From kevin at koconnor.net  Sun May  8 00:24:08 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 7 May 2011 18:24:08 -0400
Subject: [coreboot] [SeaBIOS]  Keyboard not working on Thinkpad X60/T60
In-Reply-To: <4DC5A94B.20609@coreboot.org>
References: <87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
	<20110503203319.GB3715@coreboot.org>
	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>
	<874o5ag9ta.fsf@begreifnix.stackframe.org>
	<20110507170159.GA29093@morn.localdomain>
	<87mxiye48i.fsf@begreifnix.stackframe.org>
	<20110507190502.GA4560@morn.localdomain>
	<4DC5A94B.20609@coreboot.org>
Message-ID: <20110507222408.GA14459@morn.localdomain>

On Sat, May 07, 2011 at 01:19:23PM -0700, Stefan Reinauer wrote:
> On 5/7/11 12:05 PM, Kevin O'Connor wrote:
> >On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
> >>Kevin O'Connor<kevin at koconnor.net>  writes:
> >>>Do you know how long it takes for your keyboard to become responsive?
> >>>(You can pass "-n" to tools/readserial.py to have it report wall times
> >>>instead of adjusted times.)
> >>It takes something about 0.8s, according to serial output.
> >Does adding "msleep(800)" to the top of ps2port.c:keyboard_init()
> >help?
> Please don't do things like that. Probing the hardware is much
> better than a fixed delay.

Heh - I was only asking as a test.  There's no way I would add an
800ms delay for all users.  :-)

-Kevin



From kevin at koconnor.net  Sun May  8 00:54:11 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 7 May 2011 18:54:11 -0400
Subject: [coreboot] Keyboard not working on Thinkpad X60/T60
In-Reply-To: <4DC5AA1A.7090008@coreboot.org>
References: <87r58gfb0q.fsf@begreifnix.stackframe.org>
	<20110503182932.GA18695@coreboot.org>
	<87ei4ffu6i.fsf@begreifnix.stackframe.org>
	<20110503203319.GB3715@coreboot.org>
	<87aaf2gb1d.fsf_-_@begreifnix.stackframe.org>
	<874o5ag9ta.fsf@begreifnix.stackframe.org>
	<20110507170159.GA29093@morn.localdomain>
	<87mxiye48i.fsf@begreifnix.stackframe.org>
	<20110507190502.GA4560@morn.localdomain>
	<4DC5AA1A.7090008@coreboot.org>
Message-ID: <20110507225411.GB14459@morn.localdomain>

On Sat, May 07, 2011 at 01:22:50PM -0700, Stefan Reinauer wrote:
> On 5/7/11 12:05 PM, Kevin O'Connor wrote:
> >On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
> >>Kevin O'Connor<kevin at koconnor.net>  writes:
> >>>Do you know how long it takes for your keyboard to become responsive?
> >>>(You can pass "-n" to tools/readserial.py to have it report wall times
> >>>instead of adjusted times.)
> >>It takes something about 0.8s, according to serial output.
> Maybe we can add some "shoot and run" ps2 initialization code to
> coreboot that runs before most other code, giving the keyboard or
> kbc time to initialize while we do all the other stuff.

There's a good chance it just needs more time from power up - starting
the init sooner may have no impact.

I don't think ps2 keyboard init should be in coreboot - it is (in the
general case) an optional external device that is auto-discoverable.
There's nothing really special about a ps2 keyboard that requires it
to be handled in the lowest layer of the firmware.

> Have we considered threading in coreboot? It seems the time we spend
> in ramstage is unsignificant and the effort of multitasking in
> romstage is not worth the trouble.

Are you referring to something like the cooperative multitasking
system in SeaBIOS?  If so, do you have ideas on which device
initialization could be done in parallel?  (SeaBIOS can parallelize
initialization of each disk controller, the ps2 controller, each USB
controller, and each USB device.)

-Kevin



From hamo.by at gmail.com  Sun May  8 07:04:23 2011
From: hamo.by at gmail.com (Hamo)
Date: Sun, 8 May 2011 13:04:23 +0800
Subject: [coreboot] What's the purpose of xcompile?
Message-ID: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>

Dear lists,
After review my cross-compiler patch, I found it does not work as
expect. We use a script called xcompile to set and verify the compile
toolchain. Must we use it? Can we just trust our users to let them set
their compiler prefix by themselves? If so, we can add cross-compiler
for ARM easily. If not, How could I add cross-compiler support to
xcompile? I just read the code when we supported PPC and alpha, but It
has changed a lot since then.

Thanks,
Hamo



From vikram186 at gmail.com  Sun May  8 19:54:41 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Sun, 08 May 2011 23:24:41 +0530
Subject: [coreboot] [PATCH] Fixes the build error while generating
	option_table.h
Message-ID: <4DC6D8E1.50103@gmail.com>

Hi, 
I was facing a compilation error while the make is trying to generate the option_table.h from cmos.layout file. 
Unfortunately the error info generated doesn't tell where the problem is. While going through the source, I found the error producing lines.
Below is the code snippet.
<code>
if (!is_ident((char *)ce->name)) {
			fprintf(stderr,
				"Error - Name %s is an invalid identifier in line\n %s\n",
				ce->name, line);
			exit(1);
		}
</code>
Since the ce->name and line doesn't contain any thing, the make just showed me this.
"Error - Name is an invalid identifier in line"
After spending a little time I found that the line endings in the file cmos.layout are the one that is causing issues. (Think I have opened the file in windows.)
A little change in the code can make the user happy and he doesn't need to worry about the line endings. (If this isn't a good idea, may be we can give the user a more intuitive error. something like "please check your line endings". If you want it this way, I will post the patch for that too).
Please share your views.

Signed-off by: Vikram Narayanan <vikram186 at gmail.com>
---
--- a/util/options/build_opt_tbl.c.orig	Sun May  8 22:18:54 2011
+++ a/util/options/build_opt_tbl.c	Sun May  8 22:34:34 2011
@@ -372,7 +372,7 @@
 
 		/* skip commented and blank lines */
 		if(line[0]=='#') continue;
-		if(line[strspn(line," ")]=='\n') continue;
+		if(line[0]=='\n' || line[0]=='\r') continue;
 		/* scan in the input data */
 		sscanf(line,"%d %d %c %d %s",
 			&ce->bit,&ce->length,&uc,&ce->config_id,&ce->name[0]);

-
Thanks,
Vikram 



From peter at stuge.se  Sun May  8 20:01:14 2011
From: peter at stuge.se (Peter Stuge)
Date: Sun, 8 May 2011 20:01:14 +0200
Subject: [coreboot] [PATCH] Fixes the build error while
	generating	option_table.h
In-Reply-To: <4DC6D8E1.50103@gmail.com>
References: <4DC6D8E1.50103@gmail.com>
Message-ID: <20110508180114.5916.qmail@stuge.se>

Vikram Narayanan wrote:
> I found that the line endings in the file cmos.layout are the one
> that is causing issues.

Good find.


> (Think I have opened the file in windows.)

Please be careful.


> A little change in the code can make the user happy and he doesn't
> need to worry about the line endings. (If this isn't a good idea,
> may be we can give the user a more intuitive error. something like
> "please check your line endings". If you want it this way, I will
> post the patch for that too). Please share your views.

I think it's a good idea to accept \r\n in addition to \n, but..


> +++ a/util/options/build_opt_tbl.c	Sun May  8 22:34:34 2011
> @@ -372,7 +372,7 @@
>  
>  		/* skip commented and blank lines */
>  		if(line[0]=='#') continue;
> -		if(line[strspn(line," ")]=='\n') continue;
> +		if(line[0]=='\n' || line[0]=='\r') continue;

..your patch changes the semantics in another way; with your patch a
line containing only space will no longer be treated the same way by
the program. I don't think this is so good. Maybe:

if(!strncmp(line[strspn(line," ")],"\r\n",2) continue;


//Peter



From patrick at georgi-clan.de  Sun May  8 20:06:23 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 08 May 2011 20:06:23 +0200
Subject: [coreboot] [PATCH] Fixes the build error
	while	generating	option_table.h
In-Reply-To: <20110508180114.5916.qmail@stuge.se>
References: <4DC6D8E1.50103@gmail.com> <20110508180114.5916.qmail@stuge.se>
Message-ID: <4DC6DB9F.2060205@georgi-clan.de>

Am 08.05.2011 20:01, schrieb Peter Stuge:
> if(!strncmp(line[strspn(line," ")],"\r\n",2) continue;
More like:
char val=line[strspn(line," ")];
if (val=='#' || val=='\n' || val=='\r') continue;

This has the benefit of handling
"    # comment"
and mac-style newlines, too.


Patrick



From patrick at georgi-clan.de  Sun May  8 20:09:47 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 08 May 2011 20:09:47 +0200
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>
Message-ID: <4DC6DC6B.7000600@georgi-clan.de>

Am 08.05.2011 07:04, schrieb Hamo:
> for ARM easily. If not, How could I add cross-compiler support to
> xcompile? I just read the code when we supported PPC and alpha, but It
> has changed a lot since then.
Maybe:
- Rename CC, AS, ... to I386_CC, I386_AS, ...

- Add support to check for other architectures (there's already a
comment "This should be a loop over all supported architectures",
storing that in ARM_CC, ARM_AS, ...

- Change Makefile to set:
CC:=$($(CONFIG_SOME_CONFIG_VARIABLE_WITH_ARCHITECTURE))_CC ...
depending on the chosen target hardware


Patrick



From peter at stuge.se  Sun May  8 20:13:06 2011
From: peter at stuge.se (Peter Stuge)
Date: Sun, 8 May 2011 20:13:06 +0200
Subject: [coreboot] [PATCH] Fixes the build error while
	generating	option_table.h
In-Reply-To: <4DC6DB9F.2060205@georgi-clan.de>
References: <4DC6D8E1.50103@gmail.com> <20110508180114.5916.qmail@stuge.se>
	<4DC6DB9F.2060205@georgi-clan.de>
Message-ID: <20110508181306.7145.qmail@stuge.se>

Patrick Georgi wrote:
> Am 08.05.2011 20:01, schrieb Peter Stuge:
> > if(!strncmp(line[strspn(line," ")],"\r\n",2) continue;
> More like:
> char val=line[strspn(line," ")];
> if (val=='#' || val=='\n' || val=='\r') continue;
> 
> This has the benefit of handling
> "    # comment"

..which is another change in the rules. :)


> and mac-style newlines, too.

Hmm.. Can those old Macs even connect to the internet? :p


//Peter



From patrick at georgi-clan.de  Sun May  8 20:14:22 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 08 May 2011 20:14:22 +0200
Subject: [coreboot] [PATCH] Fixes the build error
	while	generating	option_table.h
In-Reply-To: <20110508181306.7145.qmail@stuge.se>
References: <4DC6D8E1.50103@gmail.com>
	<20110508180114.5916.qmail@stuge.se>	<4DC6DB9F.2060205@georgi-clan.de>
	<20110508181306.7145.qmail@stuge.se>
Message-ID: <4DC6DD7E.2050503@georgi-clan.de>

Am 08.05.2011 20:13, schrieb Peter Stuge:
>> "    # comment"
> 
> ..which is another change in the rules. :)
Fear not, this code will be removed in a not too far future anyway.
And ideally we can change the format soon afterwards.


Patrick



From hamo.by at gmail.com  Mon May  9 05:00:49 2011
From: hamo.by at gmail.com (Hamo)
Date: Mon, 9 May 2011 11:00:49 +0800
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <4DC6DC6B.7000600@georgi-clan.de>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>
	<4DC6DC6B.7000600@georgi-clan.de>
Message-ID: <BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>

On Mon, May 9, 2011 at 2:09 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 08.05.2011 07:04, schrieb Hamo:
>> for ARM easily. If not, How could I add cross-compiler support to
>> xcompile? I just read the code when we supported PPC and alpha, but It
>> has changed a lot since then.
> Maybe:
> - Rename CC, AS, ... to I386_CC, I386_AS, ...
>
> - Add support to check for other architectures (there's already a
> comment "This should be a loop over all supported architectures",
> storing that in ARM_CC, ARM_AS, ...
>
> - Change Makefile to set:
> CC:=$($(CONFIG_SOME_CONFIG_VARIABLE_WITH_ARCHITECTURE))_CC ...
> depending on the chosen target hardware
>
>
> Patrick
>
There are a few gcc toolchain prefixes such as arm-elf, armel-elf,
arm-none-eabi, etc. It is a little difficult hard coding all the
prefixes in this script. And Such as U-boot and Kernel, both allow
their users set their own toolchain prefix.



From bari at onelabs.com  Mon May  9 05:35:56 2011
From: bari at onelabs.com (bari)
Date: Sun, 08 May 2011 22:35:56 -0500
Subject: [coreboot] ARM Toolchain for coreboot
Message-ID: <4DC7611C.10507@onelabs.com>

Hamo,

What's your plan for the ARM tool chain? QEMU on x86 or?

-Bari



From r.marek at assembler.cz  Mon May  9 07:37:32 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 09 May 2011 07:37:32 +0200
Subject: [coreboot] Hackaton in Prague 2011
Message-ID: <4DC77D9C.8010804@assembler.cz>

Hi all,

I think it is time to make a reservation for the Hotel/Hostel. Is there anyone 
else besides Peter, Sven and Florentin? Just reminding that it take place in 
Prague on last weekend in May.

The Hackaton topics I have in mind:

* make netconsole work on secondary PCI buses
* implement a gdb stub for coreboot
* fix the u-boot patches/submit them
* ... (need to get info from the attending guys)

Thanks,
Rudolf



From stefan.reinauer at coreboot.org  Mon May  9 07:51:47 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sun, 08 May 2011 22:51:47 -0700
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC77D9C.8010804@assembler.cz>
References: <4DC77D9C.8010804@assembler.cz>
Message-ID: <4DC780F3.8070300@coreboot.org>

On 5/8/11 10:37 PM, Rudolf Marek wrote:
>
> * implement a gdb stub for coreboot 
Why not use the one that is there?



From peter at stuge.se  Mon May  9 07:58:53 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 May 2011 07:58:53 +0200
Subject: [coreboot] ARM Toolchain for coreboot
In-Reply-To: <4DC7611C.10507@onelabs.com>
References: <4DC7611C.10507@onelabs.com>
Message-ID: <20110509055853.13540.qmail@stuge.se>

bari wrote:
> What's your plan for the ARM tool chain? QEMU on x86 or?

Why not just cross compile.


//Peter



From peter at stuge.se  Mon May  9 08:04:13 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 May 2011 08:04:13 +0200
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>
	<4DC6DC6B.7000600@georgi-clan.de>
	<BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>
Message-ID: <20110509060414.14178.qmail@stuge.se>

Hamo wrote:
> There are a few gcc toolchain prefixes such as arm-elf, armel-elf,
> arm-none-eabi, etc. It is a little difficult hard coding all the
> prefixes in this script. And Such as U-boot and Kernel, both allow
> their users set their own toolchain prefix.

I think it would be OK to require one specific prefix. I would
suggest arm-none-eabi because it is correct, very widely used and
also because it is what CodeSourcery G++ Lite uses.


//Peter



From r.marek at assembler.cz  Mon May  9 08:34:08 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 09 May 2011 08:34:08 +0200
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC780F3.8070300@coreboot.org>
References: <4DC77D9C.8010804@assembler.cz> <4DC780F3.8070300@coreboot.org>
Message-ID: <4DC78AE0.2090107@assembler.cz>

>> * implement a gdb stub for coreboot
> Why not use the one that is there?

Yep, but it seems it does not use HW debugging features like HW watchpoints. 
Anyway this was just an idea.

Rudolf



From hamo.by at gmail.com  Mon May  9 09:28:37 2011
From: hamo.by at gmail.com (Hamo)
Date: Mon, 9 May 2011 15:28:37 +0800
Subject: [coreboot] ARM Toolchain for coreboot
In-Reply-To: <20110509055853.13540.qmail@stuge.se>
References: <4DC7611C.10507@onelabs.com> <20110509055853.13540.qmail@stuge.se>
Message-ID: <BANLkTi=RcDHW+-eMMFRYoMfSz8ubs5wB8Q@mail.gmail.com>

On Mon, May 9, 2011 at 1:58 PM, Peter Stuge <peter at stuge.se> wrote:
> bari wrote:
>> What's your plan for the ARM tool chain? QEMU on x86 or?
>
> Why not just cross compile.
>
Yes, I will use a cross compile toolchain from CodeSourcery G++ Lite
and test my code maybe using qemu-system-arm on x86 or a real
platform.
>
> //Peter
>



From peter at stuge.se  Mon May  9 09:47:34 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 May 2011 09:47:34 +0200
Subject: [coreboot] ARM Toolchain for coreboot
In-Reply-To: <BANLkTi=RcDHW+-eMMFRYoMfSz8ubs5wB8Q@mail.gmail.com>
References: <4DC7611C.10507@onelabs.com> <20110509055853.13540.qmail@stuge.se>
	<BANLkTi=RcDHW+-eMMFRYoMfSz8ubs5wB8Q@mail.gmail.com>
Message-ID: <20110509074734.24508.qmail@stuge.se>

Hamo wrote:
> >> What's your plan for the ARM tool chain? QEMU on x86 or?
> >
> > Why not just cross compile.
> 
> Yes, I will use a cross compile toolchain from CodeSourcery G++ Lite
> and test my code maybe using qemu-system-arm on x86 or a real
> platform.

Perfect plan.


//Peter



From patrick at georgi-clan.de  Mon May  9 10:03:13 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 09 May 2011 10:03:13 +0200
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>
	<4DC6DC6B.7000600@georgi-clan.de>
	<BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>
Message-ID: <4DC79FC1.5070004@georgi-clan.de>

Am 09.05.2011 05:00, schrieb Hamo:
> There are a few gcc toolchain prefixes such as arm-elf, armel-elf,
> arm-none-eabi, etc. It is a little difficult hard coding all the
> prefixes in this script. And Such as U-boot and Kernel, both allow
> their users set their own toolchain prefix.
We mostly care about what crossgcc creates. Other toolchains work (or
not) at the user's risk.


Patrick



From hamo.by at gmail.com  Mon May  9 09:34:09 2011
From: hamo.by at gmail.com (Hamo)
Date: Mon, 9 May 2011 15:34:09 +0800
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <20110509060414.14178.qmail@stuge.se>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>
	<4DC6DC6B.7000600@georgi-clan.de>
	<BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>
	<20110509060414.14178.qmail@stuge.se>
Message-ID: <BANLkTi=Z8dp1zOQgfL+QFV5jPCHMeMRkRA@mail.gmail.com>

On Mon, May 9, 2011 at 2:04 PM, Peter Stuge <peter at stuge.se> wrote:
> Hamo wrote:
>> There are a few gcc toolchain prefixes such as arm-elf, armel-elf,
>> arm-none-eabi, etc. It is a little difficult hard coding all the
>> prefixes in this script. And Such as U-boot and Kernel, both allow
>> their users set their own toolchain prefix.
>
> I think it would be OK to require one specific prefix. I would
> suggest arm-none-eabi because it is correct, very widely used and
> also because it is what CodeSourcery G++ Lite uses.
>
If so, Could I use the idea of Patrick, create variables CC_$(ARCH),
AS_$(ARCH), LD_$(ARCH) and etc. in script xcompile and assign them to
$(CC), $(AS), $(LD) and so on when the user has selected their ARCH?
>
> //Peter



From svens at stackframe.org  Mon May  9 10:32:46 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Mon, 09 May 2011 10:32:46 +0200
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC77D9C.8010804@assembler.cz> (Rudolf Marek's message of "Mon\,
	09 May 2011 07\:37\:32 +0200")
References: <4DC77D9C.8010804@assembler.cz>
Message-ID: <87iptke0k1.fsf@begreifnix.stackframe.org>

Rudolf Marek <r.marek at assembler.cz> writes:

> I think it is time to make a reservation for the Hotel/Hostel. Is
> there anyone else besides Peter, Sven and Florentin? Just reminding
> that it take place in Prague on last weekend in May.

Cool! Thanks for organizing this Event!

> The Hackaton topics I have in mind:
>
> * make netconsole work on secondary PCI buses
> * implement a gdb stub for coreboot
> * fix the u-boot patches/submit them
> * ... (need to get info from the attending guys)

What i'm working on right now (i will bring the Hardware with me, if there's
any interest)

- Thinkpad T4x support, which means getting the i855PM chipset supported
  (which is a bit different from the i855GM we have in coreboot)

- Thinkpad X61 support, i should receive a X61 motherboard this
  week. Uses the i965 (crestline) northbridge, which isn't
  supported. Not sure if i will succeed in adding support for it.

As i'm going by car to prague, i could also bring some
soldering/measuring equipment with me. Not sure what we have there,
and what's needed. The Logic Analyzer is rather heavy (around 90 pounds)
so i'll only bring it if there's something to hack on where it would be
an adavantage to have that thing :)

See you in Prague,

Sven.



From paulepanter at users.sourceforge.net  Mon May  9 11:27:45 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Mon, 09 May 2011 11:27:45 +0200
Subject: [coreboot] ARM Toolchain for coreboot
In-Reply-To: <BANLkTi=RcDHW+-eMMFRYoMfSz8ubs5wB8Q@mail.gmail.com>
References: <4DC7611C.10507@onelabs.com> <20110509055853.13540.qmail@stuge.se>
	<BANLkTi=RcDHW+-eMMFRYoMfSz8ubs5wB8Q@mail.gmail.com>
Message-ID: <1304933265.3791.10.camel@mattotaupa>

Am Montag, den 09.05.2011, 15:28 +0800 schrieb Hamo:
> On Mon, May 9, 2011 at 1:58 PM, Peter Stuge <peter at stuge.se> wrote:
> > bari wrote:
> >> What's your plan for the ARM tool chain? QEMU on x86 or?
> >
> > Why not just cross compile.
>
> Yes, I will use a cross compile toolchain from CodeSourcery G++ Lite

Why did you choose CodeSourcery? I do not know much about it and how
difficult it is to obtain and install. But would not the GNU GCC be also
good enough for compiling for ARM?

> and test my code maybe using qemu-system-arm on x86 or a real
> platform.


Thank,

Paul
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From patrick at georgi-clan.de  Mon May  9 12:11:17 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 09 May 2011 12:11:17 +0200
Subject: [coreboot] ARM Toolchain for coreboot
In-Reply-To: <1304933265.3791.10.camel@mattotaupa>
References: <4DC7611C.10507@onelabs.com>
	<20110509055853.13540.qmail@stuge.se>	<BANLkTi=RcDHW+-eMMFRYoMfSz8ubs5wB8Q@mail.gmail.com>
	<1304933265.3791.10.camel@mattotaupa>
Message-ID: <4DC7BDC5.6090004@georgi-clan.de>

Am 09.05.2011 11:27, schrieb Paul Menzel:
> Why did you choose CodeSourcery? I do not know much about it and how
> difficult it is to obtain and install. But would not the GNU GCC be also
> good enough for compiling for ARM?
CodeSourcery is one of the main gcc developers/service providers. Their
products are (very likely) all gcc-based.


Patrick



From hamo.by at gmail.com  Mon May  9 13:50:44 2011
From: hamo.by at gmail.com (Hamo)
Date: Mon, 9 May 2011 19:50:44 +0800
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <4DC79FC1.5070004@georgi-clan.de>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>
	<4DC6DC6B.7000600@georgi-clan.de>
	<BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>
	<4DC79FC1.5070004@georgi-clan.de>
Message-ID: <BANLkTiniRFpOESH3x5LKhjiPPiXeTLShfg@mail.gmail.com>

On Mon, May 9, 2011 at 4:03 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 09.05.2011 05:00, schrieb Hamo:
>> There are a few gcc toolchain prefixes such as arm-elf, armel-elf,
>> arm-none-eabi, etc. It is a little difficult hard coding all the
>> prefixes in this script. And Such as U-boot and Kernel, both allow
>> their users set their own toolchain prefix.
> We mostly care about what crossgcc creates. Other toolchains work (or
> not) at the user's risk.
>
You mean that we need using crossgcc creates our own ARM-gcc cross
toolchain? Why must we do this? Could we just trust the famous and
mostly used toolchain like g++? In this script, it says that it could
not create an ARM toolchain. Should I fix it?
>
> Patrick
>



From patrick at georgi-clan.de  Mon May  9 13:58:58 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 09 May 2011 13:58:58 +0200
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <BANLkTiniRFpOESH3x5LKhjiPPiXeTLShfg@mail.gmail.com>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>
	<4DC6DC6B.7000600@georgi-clan.de>
	<BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>
	<4DC79FC1.5070004@georgi-clan.de>
	<BANLkTiniRFpOESH3x5LKhjiPPiXeTLShfg@mail.gmail.com>
Message-ID: <4DC7D702.7090709@georgi-clan.de>

Am 09.05.2011 13:50, schrieb Hamo:
> You mean that we need using crossgcc creates our own ARM-gcc cross
> toolchain? Why must we do this? Could we just trust the famous and
> mostly used toolchain like g++? 
"mostly used" is probably an overstatement. There are probably more ARM
toolchains out there than linux distros (which were our main concern
with requiring buildgcc toolchains, given how they all managed to mess
up gcc for us). I expect the same kind of trouble with all these, so
we'd better have some standard toolchain around that we can point people to.

In that case if/when people chose to use their own toolchains and things
break, that's their problem, not ours.

> In this script, it says that it could
> not create an ARM toolchain. Should I fix it?
That script was originally created for building ARM toolchains, before
we repurposed it for coreboot uses (because of the toolchain mess hinted
at above).

It should be enough to run "buildgcc -p arm-elf" (or arm-none-eabi or
something), with maybe a bugfix here or there.


Patrick



From peter at stuge.se  Mon May  9 14:36:34 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 May 2011 14:36:34 +0200
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <BANLkTi=Z8dp1zOQgfL+QFV5jPCHMeMRkRA@mail.gmail.com>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>
	<4DC6DC6B.7000600@georgi-clan.de>
	<BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>
	<20110509060414.14178.qmail@stuge.se>
	<BANLkTi=Z8dp1zOQgfL+QFV5jPCHMeMRkRA@mail.gmail.com>
Message-ID: <20110509123634.22614.qmail@stuge.se>

Hamo wrote:
> If so, Could I use the idea of Patrick, create variables CC_$(ARCH),
> AS_$(ARCH), LD_$(ARCH) and etc. in script xcompile and assign them to
> $(CC), $(AS), $(LD) and so on

I think this is a good approach.


> when the user has selected their ARCH?

Remember that we may want ARCH to be set by mainboards rather than
users. This might become important because xcompile usually runs
also before configuration.


//Peter



From patrick at georgi-clan.de  Mon May  9 14:38:17 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 09 May 2011 14:38:17 +0200
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <20110509123634.22614.qmail@stuge.se>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>	<4DC6DC6B.7000600@georgi-clan.de>	<BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>	<20110509060414.14178.qmail@stuge.se>	<BANLkTi=Z8dp1zOQgfL+QFV5jPCHMeMRkRA@mail.gmail.com>
	<20110509123634.22614.qmail@stuge.se>
Message-ID: <4DC7E039.7010505@georgi-clan.de>

Am 09.05.2011 14:36, schrieb Peter Stuge:
> Remember that we may want ARCH to be set by mainboards rather than
> users. This might become important because xcompile usually runs
> also before configuration.
That's why (in my proposal) the actual assignment is done in the
Makefile, not in xcompile. xcompile lists _all_ candidate toolchains it
finds, Makefile selects the one for the current build out of those given
by xcompile.


Patrick



From graeme.russ at gmail.com  Mon May  9 14:21:26 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Mon, 09 May 2011 22:21:26 +1000
Subject: [coreboot] What's the purpose of xcompile?
In-Reply-To: <4DC7D702.7090709@georgi-clan.de>
References: <BANLkTimLnFNf=w9WH1uFFFBq-P+aSqB8og@mail.gmail.com>	<4DC6DC6B.7000600@georgi-clan.de>	<BANLkTikKehTwffPXUW85_tKBJYEkWB=hRw@mail.gmail.com>	<4DC79FC1.5070004@georgi-clan.de>	<BANLkTiniRFpOESH3x5LKhjiPPiXeTLShfg@mail.gmail.com>
	<4DC7D702.7090709@georgi-clan.de>
Message-ID: <4DC7DC46.1080501@gmail.com>

On 09/05/11 21:58, Patrick Georgi wrote:
> Am 09.05.2011 13:50, schrieb Hamo:
>> You mean that we need using crossgcc creates our own ARM-gcc cross
>> toolchain? Why must we do this? Could we just trust the famous and
>> mostly used toolchain like g++? 
> "mostly used" is probably an overstatement. There are probably more ARM
> toolchains out there than linux distros (which were our main concern
> with requiring buildgcc toolchains, given how they all managed to mess
> up gcc for us). I expect the same kind of trouble with all these, so
> we'd better have some standard toolchain around that we can point people to.
> 
> In that case if/when people chose to use their own toolchains and things
> break, that's their problem, not ours.
> 
>> In this script, it says that it could
>> not create an ARM toolchain. Should I fix it?
> That script was originally created for building ARM toolchains, before
> we repurposed it for coreboot uses (because of the toolchain mess hinted
> at above).
> 
> It should be enough to run "buildgcc -p arm-elf" (or arm-none-eabi or
> something), with maybe a bugfix here or there.
> 
> 
> Patrick
> 

Might be worth talking to the U-Boot guys - They have a LOT of experience
with toolchain issues (particularly ARM and the EABI)

Regards,

Graeme



From graeme.russ at gmail.com  Mon May  9 14:18:09 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Mon, 09 May 2011 22:18:09 +1000
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC77D9C.8010804@assembler.cz>
References: <4DC77D9C.8010804@assembler.cz>
Message-ID: <4DC7DB81.9090501@gmail.com>

Hi Rudolf,

On 09/05/11 15:37, Rudolf Marek wrote:
> Hi all,
> 
> I think it is time to make a reservation for the Hotel/Hostel. Is there
> anyone else besides Peter, Sven and Florentin? Just reminding that it take
> place in Prague on last weekend in May.
> 
> The Hackaton topics I have in mind:
> 
> * make netconsole work on secondary PCI buses
> * implement a gdb stub for coreboot
> * fix the u-boot patches/submit them

If you like, I can create a coreboot 'test and development' branch in the
u-boot-x86 repository. I think I can relax the rules a little and expedite
patches from your hackathon into a central u-boot git repository as a
'testing' branch isolated from mainline

After the hackathon, the coreboot patches can be cleaned up and
cherry-picked into u-boot-x86 master (after posting on the u-boot mailing
list of course)

Given that the license for u-boot is the same as coreboot (GPLv2 -
preferably later) there should be no problem with any overlap code

Any chance we could get a bit of a design for coreboot/u-boot integration
sorted before the hackathon? For example:
 - Formalising the u-boot payload API. For example ELF/binary,
compressed/raw, passing memory size, temporary stack location, relocation,
transition from u-boot back to coreboot
 - Can u-boot piggy-back on SeaBIOS loaded by coreboot?
 - Can we move more hardware init and drivers from coreboot into u-boot and
provide more commands in u-boot for coreboot supported boards
 - VGA & Keyboard support
 - U-Boot splash screen support
 - Flash updates from u-boot

> * ... (need to get info from the attending guys)
> 
> Thanks,
> Rudolf
> 

I'm really looking forward to the u-boot integration :)

Regards

Graeme Russ (U-Boot x86 custodian)



From peter at stuge.se  Mon May  9 14:48:43 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 May 2011 14:48:43 +0200
Subject: [coreboot] ARM Toolchain for coreboot
In-Reply-To: <4DC7BDC5.6090004@georgi-clan.de>
References: <4DC7611C.10507@onelabs.com> <20110509055853.13540.qmail@stuge.se>
	<BANLkTi=RcDHW+-eMMFRYoMfSz8ubs5wB8Q@mail.gmail.com>
	<1304933265.3791.10.camel@mattotaupa>
	<4DC7BDC5.6090004@georgi-clan.de>
Message-ID: <20110509124843.24029.qmail@stuge.se>

Patrick Georgi wrote:
> > Why did you choose CodeSourcery? I do not know much about it and how
> > difficult it is to obtain and install. But would not the GNU GCC be also
> > good enough for compiling for ARM?
> 
> CodeSourcery is one of the main gcc developers/service providers.
> Their products are (very likely) all gcc-based.

Right. In particular the G++ Lite product is nothing but an ARM cross
compile toolchain with GCC and binutils.

Download at
http://www.codesourcery.com/sgpp/lite/arm/portal/release1592

Source is also available. For Linux I recommend the "Advanced Package"
with only a tarball because their installer script has not worked
very well for me.


//Peter



From peter at stuge.se  Mon May  9 14:52:18 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 May 2011 14:52:18 +0200
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <87iptke0k1.fsf@begreifnix.stackframe.org>
References: <4DC77D9C.8010804@assembler.cz>
	<87iptke0k1.fsf@begreifnix.stackframe.org>
Message-ID: <20110509125218.24599.qmail@stuge.se>

Sven Schnelle wrote:
> Logic Analyzer is rather heavy (around 90 pounds) so i'll only
> bring it if there's something to hack on where it would be an
> adavantage to have that thing :)

I'll bring the OLS which is very easy to pack. Not much in the way of
protocol decoders, but still something.


//Peter



From svn at coreboot.org  Mon May  9 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 09 May 2011 16:00:02 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1QJR0E-0008S6-Am@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110509/3df1a3a5/attachment.html>

From vikram186 at gmail.com  Mon May  9 15:50:02 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Mon, 09 May 2011 19:20:02 +0530
Subject: [coreboot] [PATCH] Fixes the build error while generating
	option_table.h
In-Reply-To: <mailman.994.1304922861.19636.coreboot@coreboot.org>
References: <mailman.994.1304922861.19636.coreboot@coreboot.org>
Message-ID: <4DC7F10A.6010402@gmail.com>

> Am 08.05.2011 20:01, schrieb Peter Stuge:
>> if(!strncmp(line[strspn(line," ")],"\r\n",2) continue;
> More like:
> char val=line[strspn(line," ")];
> if (val=='#' || val=='\n' || val=='\r') continue;
> 
> This has the benefit of handling
> "    # comment"
> and mac-style newlines, too.
Thanks for all your comments. 
As Patrick suggested, here is the new patch.

Signed-off by: Vikram Narayanan <vikram186 at gmail.com>
Signed-off by: Patrick Georgi <patrick at georgi-clan.de>
---
--- C:/coreboot/util/options/build_opt_tbl.c.orig	Sun May  8 22:18:54 2011
+++ C:/coreboot/util/options/build_opt_tbl.c	Mon May  9 19:09:32 2011
@@ -276,6 +276,7 @@
 	int enum_length;
 	int len;
 	char buf[16];
+	char val;
 
         for(i=1;i<argc;i++) {
                 if(argv[i][0]!='-') {
@@ -371,8 +372,9 @@
 		}
 
 		/* skip commented and blank lines */
-		if(line[0]=='#') continue;
-		if(line[strspn(line," ")]=='\n') continue;
+		val = line[strspn(line," ")];
+		/* takes care of *nix,Mac and Windows line ending formats */
+		if (val=='#' || val=='\n' || val=='\r') continue;
 		/* scan in the input data */
 		sscanf(line,"%d %d %c %d %s",
 			&ce->bit,&ce->length,&uc,&ce->config_id,&ce->name[0]);

-
Thanks,
Vikram



From patrick at georgi-clan.de  Mon May  9 17:05:17 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 09 May 2011 17:05:17 +0200
Subject: [coreboot] [PATCHes] Adopt coreboot build system for libpayload
Message-ID: <590c6ea59d26018ac88b21bfebf58ab6@localhost>

Content-Type: text/plain; charset=UTF-8

Content-Transfer-Encoding: quoted-printable
=0D
Hi,=0D
=0D
attached patches change libpayload to use the coreboot build system copie=
d=0D
into libpayload. Among the advantages is that it simplifies building a mo=
re=0D
standard set of libraries (eg. libcurses, libc, libpci) which simplifies=0D
porting code to libpayload a bit (as Makefiles can be used with fewer=0D
changes).=0D
=0D
For compatibility purposes, the build system still generates a=0D
libpayload.a, which is simply a superset over all other libraries.=0D
=0D
The first patch changes the build system to the new style.=0D
The second patch fixes up the tree so it compiles with the tighter=0D
warning/error regime imposed by the build system.=0D
As a bonus, the third patch adds openbsd's strlcpy (in addition to strlca=
t=0D
which we already have).=0D
=0D
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>=0D
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Content-Transfer-Encoding: base64

Content-Type: text/x-c; charset=us-ascii; charset=UTF-8;
 name=0002-Reduce-warnings-errors-in-libpayload-when-using-pick.patch

Content-Disposition: attachment;
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Ci0tIAoxLjcuNC40Cgo=

From patrick at georgi-clan.de  Mon May  9 17:08:01 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 09 May 2011 17:08:01 +0200
Subject: [coreboot] =?utf-8?q?=5BPATCH=5D_Hide_CMOS=5FVSTART=5F_and_CMOS?=
 =?utf-8?q?=5FVLEN=5F_prefixes___for_read=5Foption=28=29_use?=
Message-ID: <83bcb9e97d99c4986060e49288c525dc@localhost>

Content-Type: text/plain; charset=UTF-8

Content-Transfer-Encoding: quoted-printable
=0D
Hi,=0D
=0D
as a first step to the CMOS infrastructure project (as detailed in the=0D
wiki), this patch changes read_option() by wrapping it in a macro,=0D
simplifying its use from=0D
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)=0D
to=0D
read_option(foo, somedefault)=0D
=0D
=0D
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>=0D
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From ivaylo at e-valkov.org  Mon May  9 16:54:18 2011
From: ivaylo at e-valkov.org (Ivaylo Valkov)
Date: Mon, 09 May 2011 17:54:18 +0300
Subject: [coreboot] PATCH RS740 PCI Ids (Was Re: [PATCH] RS690 code booting
 RS740 with ECS A740GM-M)
In-Reply-To: <87hbcyw1vp.fsf@e-valkov.org>
References: <87bp3cy4d6.fsf@e-valkov.org>
	<20110123064253.1276.qmail@stuge.se>  <87hbcyw1vp.fsf@e-valkov.org>
Message-ID: <1304952858.2106.88.camel@dreamland>

Adds RS740 HT and internal graphics PCI ids. 

Signed-off-by: Ivaylo Valkov <ivaylo at e-valkov.org>
---

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From ivaylo at e-valkov.org  Mon May  9 16:54:02 2011
From: ivaylo at e-valkov.org (Ivaylo Valkov)
Date: Mon, 09 May 2011 17:54:02 +0300
Subject: [coreboot] [PATCH] RS690 code booting RS740 with ECS A740GM-M
In-Reply-To: <87hbcyw1vp.fsf@e-valkov.org>
References: <87bp3cy4d6.fsf@e-valkov.org>
	<20110123064253.1276.qmail@stuge.se>  <87hbcyw1vp.fsf@e-valkov.org>
Message-ID: <1304952842.2106.86.camel@dreamland>

At 24.01.2011 Ivaylo Valkov wrote:
> Peter Stuge writes:
> 
> > Ivaylo Valkov wrote:
> >> Adds RS740 HT and internal graphics PCI ids. 
> >> Adds support for RS740 in RS690 code (some of the fam10 code from RS780).
> >> Adds support for ECS A740GM-M.
> >> 
> >> This definitely needs more patches and fine-tuning. 
> >> Only tested on RS740.
> >
> > Please keep working on this and keep sending patches! I think in
> > particular splitting this up into individual patches will be
> > neccessary to get anyone to really take a look at it.
> 
> In that case I will split it like this:
> * patch for PCI IDs
> * patch for RS690 code (gfx, ht, early_setup)
> * patch for ECS A740GM-M with files from multiple boards sources and modifications
> * patch for ECS A740GM-M with directly copied files from other boards
> 
> The patches will have to be applied in that order. Some of them can be
> split even further.  I'll keep sending my patches in this thread.

Hello, list.

I finally had some time to split these patches and test them against the
latest code in svn. My two boards are in use and it is harder to test.

Updates:

PCI network cards crash my kernel after few packets are sent. I've
tested at least two or three cards few months ago. I am able to
reproduce this even with the first patches I've sent.

The extracted VGA ROM does not work with the internal graphics anymore.
There is no video output. The output from dmesg is:

pci 0000:01:05.0: Invalid ROM contents

The kernel loads and the system seems to be working. I was able to log
via ssh over the internal network card. The patches are sent as separate
messages in this thread.


Regards,
Ivaylo Valkov
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From ivaylo at e-valkov.org  Mon May  9 16:54:36 2011
From: ivaylo at e-valkov.org (Ivaylo Valkov)
Date: Mon, 09 May 2011 17:54:36 +0300
Subject: [coreboot] ECS A740GM-M support (Was Re: [PATCH] RS690 code booting
 RS740 with ECS A740GM-M)
In-Reply-To: <87hbcyw1vp.fsf@e-valkov.org>
References: <87bp3cy4d6.fsf@e-valkov.org>
	<20110123064253.1276.qmail@stuge.se>  <87hbcyw1vp.fsf@e-valkov.org>
Message-ID: <1304952876.2106.92.camel@dreamland>

Adds support for the ECS A740GM-M board based on the RS740 chipset.

Signed-off-by: Ivaylo Valkov <ivaylo at e-valkov.org>
---

The ecs-a740gm-m-files-copied-from-amd-mahogany-fam10.patch could be
skipped, if the following files are copied (svn copy): 

src/mainboard/amd/mahogany_fam10/acpi_tables.c
src/mainboard/amd/mahogany_fam10/cmos.layout
src/mainboard/amd/mahogany_fam10/mb_sysconf.h
src/mainboard/amd/mahogany_fam10/resourcemap.c
src/mainboard/amd/mahogany_fam10/acpi/ide.asl
src/mainboard/amd/mahogany_fam10/acpi/cpstate.asl
src/mainboard/amd/mahogany_fam10/acpi/routing.asl
src/mainboard/amd/mahogany_fam10/acpi/sata.asl
src/mainboard/amd/mahogany_fam10/acpi/usb.asl

as: 

src/mainboard/ecs/a740gm-m/acpi_tables.c
src/mainboard/ecs/a740gm-m/cmos.layout
src/mainboard/ecs/a740gm-m/mb_sysconf.h
src/mainboard/ecs/a740gm-m/resourcemap.c
src/mainboard/ecs/a740gm-m/acpi/ide.asl
src/mainboard/ecs/a740gm-m/acpi/cpstate.asl
src/mainboard/ecs/a740gm-m/acpi/routing.asl
src/mainboard/ecs/a740gm-m/acpi/sata.asl
src/mainboard/ecs/a740gm-m/acpi/usb.asl

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From ivaylo at e-valkov.org  Mon May  9 16:54:29 2011
From: ivaylo at e-valkov.org (Ivaylo Valkov)
Date: Mon, 09 May 2011 17:54:29 +0300
Subject: [coreboot] PATCH Support for RS740 in RS690 code (Was Re: [PATCH]
 RS690 code booting RS740 with ECS A740GM-M)
In-Reply-To: <87hbcyw1vp.fsf@e-valkov.org>
References: <87bp3cy4d6.fsf@e-valkov.org>
	<20110123064253.1276.qmail@stuge.se>  <87hbcyw1vp.fsf@e-valkov.org>
Message-ID: <1304952869.2106.90.camel@dreamland>

Adds support for RS740 (HT, internal graphics and early setup) in RS690
code.

Signed-off-by: Ivaylo Valkov <ivaylo at e-valkov.org>
---

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From paulepanter at users.sourceforge.net  Mon May  9 18:29:30 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Mon, 09 May 2011 18:29:30 +0200
Subject: [coreboot] [PATCH] Fixes the build error while generating
 option_table.h
In-Reply-To: <4DC7F10A.6010402@gmail.com>
References: <mailman.994.1304922861.19636.coreboot@coreboot.org>
	<4DC7F10A.6010402@gmail.com>
Message-ID: <1304958570.3939.2.camel@mattotaupa>

Am Montag, den 09.05.2011, 19:20 +0530 schrieb Vikram Narayanan:
> > Am 08.05.2011 20:01, schrieb Peter Stuge:
> >> if(!strncmp(line[strspn(line," ")],"\r\n",2) continue;
> > More like:
> > char val=line[strspn(line," ")];
> > if (val=='#' || val=='\n' || val=='\r') continue;
> > 
> > This has the benefit of handling
> > "    # comment"
> > and mac-style newlines, too.
> Thanks for all your comments. 
> As Patrick suggested, here is the new patch.

A short commit message would have been nice.

> Signed-off by: Vikram Narayanan <vikram186 at gmail.com>
> Signed-off by: Patrick Georgi <patrick at georgi-clan.de>
> ---
> --- C:/coreboot/util/options/build_opt_tbl.c.orig	Sun May  8 22:18:54 2011
> +++ C:/coreboot/util/options/build_opt_tbl.c	Mon May  9 19:09:32 2011
> @@ -276,6 +276,7 @@
>  	int enum_length;
>  	int len;
>  	char buf[16];
> +	char val;
>  
>          for(i=1;i<argc;i++) {
>                  if(argv[i][0]!='-') {
> @@ -371,8 +372,9 @@
>  		}
>  
>  		/* skip commented and blank lines */
> -		if(line[0]=='#') continue;
> -		if(line[strspn(line," ")]=='\n') continue;
> +		val = line[strspn(line," ")];
> +		/* takes care of *nix,Mac and Windows line ending formats */

Whoever has commit rights and commits this, please add a space behind
the comma.

> +		if (val=='#' || val=='\n' || val=='\r') continue;
>  		/* scan in the input data */
>  		sscanf(line,"%d %d %c %d %s",
>  			&ce->bit,&ce->length,&uc,&ce->config_id,&ce->name[0]);

Acked-by: Paul Menzel <paulepanter at users.sourceforge.net>


Thanks,

Paul
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From paulepanter at users.sourceforge.net  Mon May  9 18:32:09 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Mon, 09 May 2011 18:32:09 +0200
Subject: [coreboot] [PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes
 for read_option() use
In-Reply-To: <83bcb9e97d99c4986060e49288c525dc@localhost>
References: <83bcb9e97d99c4986060e49288c525dc@localhost>
Message-ID: <1304958729.3939.4.camel@mattotaupa>

Dear Patrick,


Am Montag, den 09.05.2011, 17:08 +0200 schrieb Patrick Georgi:
> Content-Type: text/plain; charset=UTF-8
> 
> Content-Transfer-Encoding: quoted-printable
> =0D
> Hi,=0D
> =0D

did you change your mail setup? Somehow your message is not displayed
correctly, i. e. it is not formatted.

> as a first step to the CMOS infrastructure project (as detailed in the=0D
> wiki),

An URL would be nice.

> this patch changes read_option() by wrapping it in a macro,=0D
> simplifying its use from=0D
> read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)=0D
> to=0D
> read_option(foo, somedefault)=0D
> =0D
> =0D
> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>=0D


Thanks,

Paul
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From patrick at georgi-clan.de  Mon May  9 18:54:26 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 09 May 2011 18:54:26 +0200
Subject: [coreboot] [PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes
 for read_option() use
In-Reply-To: <1304958729.3939.4.camel@mattotaupa>
References: <83bcb9e97d99c4986060e49288c525dc@localhost>
	<1304958729.3939.4.camel@mattotaupa>
Message-ID: <4DC81C42.50105@georgi-clan.de>

Am 09.05.2011 18:32, schrieb Paul Menzel:
> did you change your mail setup? Somehow your message is not displayed
> correctly, i. e. it is not formatted.
Oops, I'll resend (that was with webmail stuff, and I rarely use the
webmail with attachments)

Thanks for the heads-up

>> as a first step to the CMOS infrastructure project (as detailed in the
>> wiki),
> An URL would be nice.
http://www.coreboot.org/Infrastructure_Projects#CMOS_handling


Patrick



From vikram186 at gmail.com  Mon May  9 19:09:24 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Mon, 09 May 2011 22:39:24 +0530
Subject: [coreboot] [PATCH] Fixes the build error while generating
 option_table.h
In-Reply-To: <1304958570.3939.2.camel@mattotaupa>
References: <mailman.994.1304922861.19636.coreboot@coreboot.org>
	<4DC7F10A.6010402@gmail.com>  <1304958570.3939.2.camel@mattotaupa>
Message-ID: <1304960964.2422.8.camel@ubuntu.ubuntu-domain>

On Mon, 2011-05-09 at 18:29 +0200, Paul Menzel wrote:
> Am Montag, den 09.05.2011, 19:20 +0530 schrieb Vikram Narayanan:
> > > Am 08.05.2011 20:01, schrieb Peter Stuge:
> > >> if(!strncmp(line[strspn(line," ")],"\r\n",2) continue;
> > > More like:
> > > char val=line[strspn(line," ")];
> > > if (val=='#' || val=='\n' || val=='\r') continue;
> > > 
> > > This has the benefit of handling
> > > "    # comment"
> > > and mac-style newlines, too.
> > Thanks for all your comments. 
> > As Patrick suggested, here is the new patch.
> 
> A short commit message would have been nice.

This patch fixes the compilation error arising due to non-unix style line endings in cmos.layout file while generating option_table.h.
Windows, Mac and *nix type line endings are now taken care of. 

> > Signed-off by: Vikram Narayanan <vikram186 at gmail.com>
> > Signed-off by: Patrick Georgi <patrick at georgi-clan.de>
> > ---
> > --- C:/coreboot/util/options/build_opt_tbl.c.orig	Sun May  8 22:18:54 2011
> > +++ C:/coreboot/util/options/build_opt_tbl.c	Mon May  9 19:09:32 2011
> > @@ -276,6 +276,7 @@
> >  	int enum_length;
> >  	int len;
> >  	char buf[16];
> > +	char val;
> >  
> >          for(i=1;i<argc;i++) {
> >                  if(argv[i][0]!='-') {
> > @@ -371,8 +372,9 @@
> >  		}
> >  
> >  		/* skip commented and blank lines */
> > -		if(line[0]=='#') continue;
> > -		if(line[strspn(line," ")]=='\n') continue;
> > +		val = line[strspn(line," ")];
> > +		/* takes care of *nix,Mac and Windows line ending formats */
> 
> Whoever has commit rights and commits this, please add a space behind
> the comma.
> 
> > +		if (val=='#' || val=='\n' || val=='\r') continue;
> >  		/* scan in the input data */
> >  		sscanf(line,"%d %d %c %d %s",
> >  			&ce->bit,&ce->length,&uc,&ce->config_id,&ce->name[0]);
> 
> Acked-by: Paul Menzel <paulepanter at users.sourceforge.net>

Thanks,
Vikram




From patrick at georgi-clan.de  Mon May  9 19:14:01 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 09 May 2011 19:14:01 +0200
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC7DB81.9090501@gmail.com>
References: <4DC77D9C.8010804@assembler.cz> <4DC7DB81.9090501@gmail.com>
Message-ID: <4DC820D9.4000303@georgi-clan.de>

Am 09.05.2011 14:18, schrieb Graeme Russ:
>  - Formalising the u-boot payload API. For example ELF/binary,
> compressed/raw, passing memory size, temporary stack location, relocation,
> transition from u-boot back to coreboot
compressed/raw is nothing the payload needs to concern itself with with
coreboot.

Transitioning back to coreboot doesn't happen (what for?), though we
have bayou which allows handling multiple payloads with proper exit
semantics.

memory size is in cbtable, payloads are ELF by convention (worst case
would be to objcopy a binary uboot image into ELF to use that), stack
location and relocation are payload matters (ie. nothing coreboot cares
about), though optional relocation support might be provided by
libpayload in the not too far future.

>  - Can u-boot piggy-back on SeaBIOS loaded by coreboot?
In the context of coreboot: why?

>  - Can we move more hardware init and drivers from coreboot into u-boot and
> provide more commands in u-boot for coreboot supported boards
Code duplication? *shudder*

>  - VGA & Keyboard support
>  - U-Boot splash screen support
libpayload

>  - Flash updates from u-boot
libflashrom (work in progress)


Patrick



From stefan.reinauer at coreboot.org  Mon May  9 19:45:12 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 9 May 2011 19:45:12 +0200
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC78AE0.2090107@assembler.cz>
References: <4DC77D9C.8010804@assembler.cz> <4DC780F3.8070300@coreboot.org>
	<4DC78AE0.2090107@assembler.cz>
Message-ID: <20110509174512.GA18567@coreboot.org>

* Rudolf Marek <r.marek at assembler.cz> [110509 08:34]:
> >>* implement a gdb stub for coreboot
> >Why not use the one that is there?
> 
> Yep, but it seems it does not use HW debugging features like HW
> watchpoints. Anyway this was just an idea.
 
Ah this sounds great. Just wanted to make sure you didn't miss that
there already is something around that could potentially be useful.
Extending the debugging functionality would be awesome.





From josh+coreboot at pcinw.net  Mon May  9 20:50:37 2011
From: josh+coreboot at pcinw.net (Josh Stump)
Date: Mon, 9 May 2011 11:50:37 -0700
Subject: [coreboot] Lenovo T60 coreboot build error
Message-ID: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>

This is with svn checkout of version 6561 - I have tried with Seabios stable
& Seabios master but get the same error.  Building under Ubuntu 11.04 64 bit

Makefile:225: warning: overriding commands for target
`build/cpu/x86/name/name.ramstage.o'
Makefile:225: warning: ignoring old commands for target
`build/cpu/x86/name/name.ramstage.o'
    GEN        bootblock/ldscript.ld
    LINK       bootblock.elf
    OBJCOPY    coreboot.bootblock
    CC         lib/memset.romstage.o
    CC         lib/memcpy.romstage.o
    CC         lib/memcmp.romstage.o
    CC         lib/cbfs.romstage.o
    CC         lib/lzma.romstage.o
    CC         lib/ramtest.romstage.o
    CC         lib/cbmem.romstage.o
    CC         lib/uart8250.romstage.o
    CC         console/vtxprintf.romstage.o
    GEN        build.h
    CC         console/console.romstage.o
    CC         console/post.romstage.o
    CC         console/die.romstage.o
    CC         romstage.inc
    POST       romstage.inc
    GEN        romstage/crt0.S
    CC         mainboard/lenovo/t60/crt0.s
    CC         mainboard/lenovo/t60/crt0.romstage.o
    CC         mainboard/lenovo/t60/dock.romstage.o
    CC         arch/x86/lib/romstage_console.romstage.o
    CC         arch/x86/lib/cbfs_and_run.romstage.o
    CC         southbridge/intel/i82801gx/early_smbus.romstage.o
    CC         northbridge/intel/i945/udelay.romstage.o
    CC         northbridge/intel/i945/raminit.romstage.o
    CC         northbridge/intel/i945/early_init.romstage.o
    CC         northbridge/intel/i945/errata.romstage.o
    CC         northbridge/intel/i945/debug.romstage.o
    GEN        romstage/ldscript.ld
    LINK       coreboot.romstage
    CBFS       coreboot.pre
    CC         arch/x86/lib/c_start.ramstage.o
    CC         console/uart8250_console.driver.o
    CC         ec/lenovo/h8/h8.driver.o
    CC         ec/lenovo/pmh7/pmh7.driver.o
    CC         southbridge/intel/i82801gx/i82801gx.driver.o
    CC         southbridge/intel/i82801gx/ac97.driver.o
    CC         southbridge/intel/i82801gx/azalia.driver.o
    CC         southbridge/intel/i82801gx/ide.driver.o
    CC         southbridge/intel/i82801gx/lpc.driver.o
    CC         southbridge/intel/i82801gx/nic.driver.o
    CC         southbridge/intel/i82801gx/pci.driver.o
    CC         southbridge/intel/i82801gx/pcie.driver.o
    CC         southbridge/intel/i82801gx/sata.driver.o
    CC         southbridge/intel/i82801gx/smbus.driver.o
    CC         southbridge/intel/i82801gx/usb.driver.o
    CC         southbridge/intel/i82801gx/usb_ehci.driver.o
    CC         southbridge/ti/pci1x2x/pci1x2x.driver.o
    CC         northbridge/intel/i945/northbridge.driver.o
    CC         northbridge/intel/i945/gma.driver.o
    CC         cpu/intel/model_69x/model_69x_init.driver.o
    CC         cpu/intel/model_6dx/model_6dx_init.driver.o
    CC         cpu/intel/model_6ex/model_6ex_init.driver.o
    CC         cpu/intel/model_6fx/model_6fx_init.driver.o
    CC         mainboard/lenovo/t60/static.ramstage.o
    CC         lib/memset.ramstage.o
    CC         lib/memcpy.ramstage.o
    CC         lib/memcmp.ramstage.o
    CC         lib/memmove.ramstage.o
    CC         lib/malloc.ramstage.o
    CC         lib/delay.ramstage.o
    CC         lib/fallback_boot.ramstage.o
    CC         lib/compute_ip_checksum.ramstage.o
    CC         lib/version.ramstage.o
    CC         lib/cbfs.ramstage.o
    CC         lib/lzma.ramstage.o
    CC         lib/gcc.ramstage.o
    CC         lib/clog2.ramstage.o
    CC         lib/cbmem.ramstage.o
    CC         lib/uart8250.ramstage.o
    CC         boot/hardwaremain.ramstage.o
    CC         boot/selfboot.ramstage.o
    CC         console/printk.ramstage.o
    CC         console/console.ramstage.o
    CC         console/vtxprintf.ramstage.o
    CC         console/vsprintf.ramstage.o
    CC         console/post.ramstage.o
    CC         console/die.ramstage.o
    CC         devices/device.ramstage.o
    CC         devices/root_device.ramstage.o
    CC         devices/device_util.ramstage.o
    CC         devices/pci_device.ramstage.o
    CC         devices/pcix_device.ramstage.o
    CC         devices/pciexp_device.ramstage.o
    CC         devices/agp_device.ramstage.o
    CC         devices/cardbus_device.ramstage.o
    CC         devices/pnp_device.ramstage.o
    CC         devices/pci_ops.ramstage.o
    CC         devices/smbus_ops.ramstage.o
    CC         devices/pci_rom.ramstage.o
    CC         mainboard/lenovo/t60/mainboard.ramstage.o
    CC         mainboard/lenovo/t60/mptable.ramstage.o
    CC         mainboard/lenovo/t60/irq_tables.ramstage.o
    CC         mainboard/lenovo/t60/acpi_tables.ramstage.o
    IASL       build/mainboard/lenovo/t60/dsdt.ramstage.o

Intel ACPI Component Architecture
ASL Optimizing Compiler version 20100528 [Oct 15 2010]
Copyright (c) 2000 - 2010 Intel Corporation
Supports ACPI Specification Revision 4.0a

ASL Input:  build/mainboard/lenovo/t60/dsdt.ramstage.asl - 2334 lines, 42093
bytes, 1027 keywords
AML Output: build/mainboard/lenovo/t60/dsdt.aml - 11765 bytes, 471 named
objects, 556 executable opcodes

Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 386 Optimizations
    CC         mainboard/lenovo/t60/fadt.ramstage.o
    CC         pc80/mc146818rtc.ramstage.o
    CC         pc80/isa-dma.ramstage.o
    CC         pc80/i8259.ramstage.o
    CC         pc80/keyboard.ramstage.o
    CC         devices/oprom/x86.ramstage.o
    CC         devices/oprom/x86_asm.ramstage.o
    CC         devices/oprom/x86_interrupts.ramstage.o
    CC         ec/acpi/ec.ramstage.o
    CC         arch/x86/boot/boot.ramstage.o
    CC         arch/x86/boot/coreboot_table.ramstage.o
    CC         arch/x86/boot/multiboot.ramstage.o
    CC         arch/x86/boot/gdt.ramstage.o
    CC         arch/x86/boot/tables.ramstage.o
    CC         arch/x86/boot/mpspec.ramstage.o
    CC         arch/x86/boot/pirq_routing.ramstage.o
    CC         arch/x86/boot/acpi.ramstage.o
    CC         arch/x86/boot/acpigen.ramstage.o
    CC         arch/x86/boot/wakeup.ramstage.o
    CC         arch/x86/lib/cpu.ramstage.o
    CC         arch/x86/lib/pci_ops_conf1.ramstage.o
    CC         arch/x86/lib/pci_ops_conf2.ramstage.o
    CC         arch/x86/lib/pci_ops_mmconf.ramstage.o
    CC         arch/x86/lib/pci_ops_auto.ramstage.o
    CC         arch/x86/lib/exception.ramstage.o
    CC         arch/x86/lib/ioapic.ramstage.o
    CC         pc80/vga/vga_io.ramstage.o
    CC         southbridge/intel/i82801gx/reset.ramstage.o
    CC         southbridge/intel/i82801gx/watchdog.ramstage.o
    CC         southbridge/intel/i82801gx/smi.ramstage.o
    CC         northbridge/intel/i945/acpi.ramstage.o
    CC         superio/nsc/pc87382/superio.ramstage.o
    CC         superio/nsc/pc87384/superio.ramstage.o
    CC         cpu/intel/socket_mFCPGA478/socket_mFCPGA478.ramstage.o
    CC         cpu/x86/mtrr/mtrr.ramstage.o
    CC         cpu/x86/lapic/lapic.ramstage.o
    CC         cpu/x86/lapic/lapic_cpu_init.ramstage.o
    CC         cpu/x86/lapic/secondary.ramstage.o
    CC         cpu/x86/lapic/apic_timer.ramstage.o
    CC         cpu/x86/cache/cache.ramstage.o
    CC         lib/memcpy.smm.o
    CC         lib/uart8250.smm.o
    CC         console/printk.smm.o
    CC         console/vtxprintf.smm.o
    CC         mainboard/lenovo/t60/mainboard_smi.smm.o
    CC         mainboard/lenovo/t60/dock.smm.o
    CC         ec/acpi/ec.smm.o
    CC         southbridge/intel/i82801gx/smihandler.smm.o
    CC         northbridge/intel/i945/udelay.smm.o
    CC         cpu/x86/smm/smmhandler.smm.o
    CC         cpu/x86/smm/smihandler.smm.o
    CC         cpu/x86/smm/smiutil.smm.o
    OBJCOPY    cpu/x86/smm/smm_wrap.ramstage.o
    CC         cpu/x86/smm/smmrelocate.ramstage.o
    CC         cpu/intel/microcode/microcode.ramstage.o
    CC         cpu/intel/hyperthreading/intel_sibling.ramstage.o
    CC         cpu/intel/speedstep/acpi.ramstage.o
    CC         cpu/x86/name/name.ramstage.o
    AR         coreboot.a
    CC         coreboot_ram.o
    CC         coreboot_ram
    GIT        SeaBIOS origin/master
Switched to branch 'master'
Deleted branch coreboot (was 1efb10b).
Branch coreboot set up to track remote branch master from origin.
Switched to a new branch 'coreboot'
    CONFIG     SeaBIOS origin/master
  Build default config
#
# configuration written to
/home/josh/bios/coreboot/payloads/external/SeaBIOS/seabios/.config
#
    MAKE       SeaBIOS origin/master
  Build Kconfig config file
/home/josh/bios/coreboot/payloads/external/SeaBIOS/seabios/.config:77:warning:
override: reassigning to symbol COREBOOT
/home/josh/bios/coreboot/payloads/external/SeaBIOS/seabios/.config:78:warning:
override: reassigning to symbol DEBUG_SERIAL
#
# configuration written to
/home/josh/bios/coreboot/payloads/external/SeaBIOS/seabios/.config
#
  Compiling whole program out/ccode.16.s
  Compiling to assembler out/asm-offsets.s
  Generating offset file out/asm-offsets.h
  Compiling (16bit) out/code16.o
  Compiling whole program out/ccode32flat.o
  Compiling whole program out/code32seg.o
  Building ld scripts (version "pre-0.6.3-20110509_113214-josh-laptop")
Fixed space: 0xe05b-0x10000  total: 8101  slack: 3  Percent slack: 0.0%
16bit size:           39456
32bit segmented size: 2412
32bit flat size:      13972
32bit flat init size: 39392
  Linking out/rom16.o
out/romlayout16.lds:705 cannot move location counter backwards (from
000000000000ca88 to 000000000000ca6c)
make[2]: *** [out/rom16.o] Error 1
make[1]: *** [seabios] Error 2
make: *** [seabios] Error 2
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From peter at stuge.se  Mon May  9 21:22:06 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 May 2011 21:22:06 +0200
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>
References: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>
Message-ID: <20110509192206.31945.qmail@stuge.se>

Josh Stump wrote:
> This is with svn checkout of version 6561 - I have tried with Seabios stable
> & Seabios master but get the same error.  Building under Ubuntu 11.04 64 bit
..
>   Linking out/rom16.o
> out/romlayout16.lds:705 cannot move location counter backwards (from
> 000000000000ca88 to 000000000000ca6c)

The toolchain in Ubuntu 11.04 isn't capable of building coreboot then. :\

Please build the reference toolchain:

cd util/crossgcc
./buildgcc i386-elf
cd ../..
rm -f .xcompile
make


//Peter



From svn at coreboot.org  Mon May  9 22:53:39 2011
From: svn at coreboot.org (repository service)
Date: Mon, 09 May 2011 22:53:39 +0200
Subject: [coreboot] [commit] r6562 - trunk/src/include/device
Message-ID: <E1QJXSV-0004lt-Cy@ra.coresystems.de>

Author: mjones
Date: Mon May  9 22:53:38 2011
New Revision: 6562
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6562

Log:
Adds RS740 HT and internal graphics PCI ids.

Signed-off-by: Ivaylo Valkov <ivaylo at e-valkov.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/include/device/pci_ids.h

Modified: trunk/src/include/device/pci_ids.h
==============================================================================
--- trunk/src/include/device/pci_ids.h	Sat May  7 11:15:02 2011	(r6561)
+++ trunk/src/include/device/pci_ids.h	Mon May  9 22:53:38 2011	(r6562)
@@ -332,6 +332,7 @@
 #define PCI_DEVICE_ID_ATI_SB800_GEC             0x1699
 
 #define PCI_DEVICE_ID_ATI_RS690_HT		0x7910
+#define PCI_DEVICE_ID_ATI_RS740_HT		0x7911
 #define PCI_DEVICE_ID_ATI_RS690_PCIE		0x7912
 #define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2	0x7913
 #define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3	0x791B
@@ -342,6 +343,7 @@
 #define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8	0x7918
 #define PCI_DEVICE_ID_ATI_RS690_INT_GFX		0x791e
 #define PCI_DEVICE_ID_ATI_RS690MT_INT_GFX	0x791f
+#define PCI_DEVICE_ID_ATI_RS740_INT_GFX		0x796e
 
 #define PCI_DEVICE_ID_AMD_RS780_HT		0x9600
 #define PCI_DEVICE_ID_AMD_RS780_PCIE		0x9602



From marcj303 at gmail.com  Mon May  9 22:54:05 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 9 May 2011 14:54:05 -0600
Subject: [coreboot] PATCH RS740 PCI Ids (Was Re: [PATCH] RS690 code
 booting RS740 with ECS A740GM-M)
In-Reply-To: <1304952858.2106.88.camel@dreamland>
References: <87bp3cy4d6.fsf@e-valkov.org> <20110123064253.1276.qmail@stuge.se>
	<87hbcyw1vp.fsf@e-valkov.org> <1304952858.2106.88.camel@dreamland>
Message-ID: <BANLkTi=yHr6MapYcjy7cr_Zen8L6p6Dazw@mail.gmail.com>

On Mon, May 9, 2011 at 8:54 AM, Ivaylo Valkov <ivaylo at e-valkov.org> wrote:
> Adds RS740 HT and internal graphics PCI ids.
>
> Signed-off-by: Ivaylo Valkov <ivaylo at e-valkov.org>

Acked-by: Marc Jones <marcj303 at gmail.com>

r6562

Thanks,
Marc


-- 
http://se-eng.com



From josh+coreboot at pcinw.net  Mon May  9 22:57:26 2011
From: josh+coreboot at pcinw.net (Josh Stump)
Date: Mon, 9 May 2011 13:57:26 -0700
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <20110509192206.31945.qmail@stuge.se>
References: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>
	<20110509192206.31945.qmail@stuge.se>
Message-ID: <BANLkTiny2a3FwqrpY9-JAbqLrTg=+Ejapg@mail.gmail.com>

Thank you kindly.  I have now compiled the BIOS.  Next challenge is how to
get flashrom to flash it.  The wiki shows flashrom support.  I have
downloaded the latest svn version and flashrom does not detect my system.
 flashrom -L does not list Lenovo T60, any suggestions or shall I get on the
flashrom mailing list to ask?  Thank you again.


On Mon, May 9, 2011 at 12:22 PM, Peter Stuge <peter at stuge.se> wrote:

> Josh Stump wrote:
> > This is with svn checkout of version 6561 - I have tried with Seabios
> stable
> > & Seabios master but get the same error.  Building under Ubuntu 11.04 64
> bit
> ..
> >   Linking out/rom16.o
> > out/romlayout16.lds:705 cannot move location counter backwards (from
> > 000000000000ca88 to 000000000000ca6c)
>
> The toolchain in Ubuntu 11.04 isn't capable of building coreboot then. :\
>
> Please build the reference toolchain:
>
> cd util/crossgcc
> ./buildgcc i386-elf
> cd ../..
> rm -f .xcompile
> make
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From stefan.reinauer at coreboot.org  Tue May 10 00:17:38 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 10 May 2011 00:17:38 +0200
Subject: [coreboot] [RFC] src/drivers/generic/generic used but not there
Message-ID: <20110509221738.GA32602@coreboot.org>

Hi,

Looking for drivers/generic/generic in the source code, we use it quite
a lot:

grep generic.generic src/mainboard/*/*/devicetree.cb |wc -l
391


However:

ls src/drivers/generic/
Kconfig  Makefile.inc  debug

It does not exist.

Should we drop all those sub trees? Or try to fix them? What is needed
to fix them?





From graeme.russ at gmail.com  Tue May 10 01:20:47 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Tue, 10 May 2011 09:20:47 +1000
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC820D9.4000303@georgi-clan.de>
References: <4DC77D9C.8010804@assembler.cz> <4DC7DB81.9090501@gmail.com>
	<4DC820D9.4000303@georgi-clan.de>
Message-ID: <BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>

Hi Patrick

On Tue, May 10, 2011 at 3:14 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 09.05.2011 14:18, schrieb Graeme Russ:
>> ?- Formalising the u-boot payload API. For example ELF/binary,
>> compressed/raw, passing memory size, temporary stack location, relocation,
>> transition from u-boot back to coreboot
> compressed/raw is nothing the payload needs to concern itself with with
> coreboot.
>
> Transitioning back to coreboot doesn't happen (what for?), though we
> have bayou which allows handling multiple payloads with proper exit
> semantics.

Well, I do not know the semantic architecture of coreboot :) In addition to
'boot OS and die', U-Boot has a 'standalone application' API which allows a
'payload' to be run with control returning to U-Boot. If coreboot does not
have any such concept then you are right, no need to worry about returning
back to coreboot

> memory size is in cbtable, payloads are ELF by convention (worst case
> would be to objcopy a binary uboot image into ELF to use that), stack
> location and relocation are payload matters (ie. nothing coreboot cares
> about), though optional relocation support might be provided by
> libpayload in the not too far future.

My point being that U-Boot needs to know about the arrangement of memory
of the target board. As the primary bootloader, U-Boot figures this out
during SDRAM initialisation (in addition to some hard-coded board level
defines in some cases). If coreboot is doing all the memory init, we
need a way of telling U-Boot about the memory on the board.

The idea of adding support for relocatable ELF images to libpayload is
interesting. If coreboot can load U-Boot at an appropriate target address
than we can skip a memcpy and relocation fixup loop in U-Boot. Need to
have a closer look at the impact of some post-relocation code such as
reloading of the GDT (although off the top of my head, I don't think this
will be a problem at all)

>> ?- Can u-boot piggy-back on SeaBIOS loaded by coreboot?
> In the context of coreboot: why?

Again, probably a missunderstanding of coreboot on my behalf - U-Boot has
a REALLY primative BIOS implementation (just enough to trick Linux into
booting in an embedded environment). It is basically just some empty VGA
stubs and simple e820 support. If coreboot can load SeaBIOS, U-Boot could
transition to it and I could ditch all of the real-mode support from
U-Boot. This could allow U-Boot to support booting of OSs that require a
BIOS. For Linux, I can implement a protected mode transition from U-Boot
for which we would not need to load SeaBIOS at all.

>> ?- Can we move more hardware init and drivers from coreboot into u-boot and
>> provide more commands in u-boot for coreboot supported boards
> Code duplication? *shudder*

The point being that U-Boot provides a shell and command line with
diagnostic features. These require hooks into the hardware drivers.

>> ?- VGA & Keyboard support
>> ?- U-Boot splash screen support
> libpayload
>
>> ?- Flash updates from u-boot
> libflashrom (work in progress)

How will these work in practice? Where are they initiated from?

Regards,

Graeme



From peter at stuge.se  Tue May 10 02:30:02 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 10 May 2011 02:30:02 +0200
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>
References: <4DC77D9C.8010804@assembler.cz> <4DC7DB81.9090501@gmail.com>
	<4DC820D9.4000303@georgi-clan.de>
	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>
Message-ID: <20110510003002.32657.qmail@stuge.se>

Graeme Russ wrote:
> Well, I do not know the semantic architecture of coreboot :)

Welcome to the list.


> In addition to 'boot OS and die', U-Boot has a 'standalone
> application' API which allows a 'payload' to be run with control
> returning to U-Boot. If coreboot does not have any such concept
> then you are right, no need to worry about returning back to
> coreboot

coreboot does not.


> > memory size is in cbtable, payloads are ELF by convention
..
> 
> My point being that U-Boot needs to know about the arrangement of
> memory of the target board.

Yes. The information is published by coreboot in the "coreboot table"
AKA cbtable. libpayload already has code to find it.


> The idea of adding support for relocatable ELF images to libpayload is
> interesting. If coreboot can load U-Boot at an appropriate target
> address than we can skip a memcpy and relocation fixup loop in U-Boot.

I think the coreboot loader does this already. If U-Boot is built as
an ELF located at the appropriate target address then that's where
coreboot will run it from.


> >> ?- Can u-boot piggy-back on SeaBIOS loaded by coreboot?
> > In the context of coreboot: why?
> 
> Again, probably a missunderstanding of coreboot on my behalf -
> U-Boot has a REALLY primative BIOS implementation (just enough to
> trick Linux into booting in an embedded environment). It is
> basically just some empty VGA stubs and simple e820 support. If
> coreboot can load SeaBIOS, U-Boot could transition to it and I
> could ditch all of the real-mode support from U-Boot.

coreboot starts one payload and one payload only. SeaBIOS when built
as payload for coreboot can actually start other files in the boot
flash that are identical to the coreboot payload.

The sequence would then be coreboot->SeaBIOS->U-Boot. Note that
coreboot is not a BIOS and does not want to be a BIOS.


> This could allow U-Boot to support booting of OSs that require a BIOS.

That should work fine if SeaBIOS is inserted before U-Boot and can
set up the complete BIOS environment.


> For Linux, I can implement a protected mode transition from U-Boot
> for which we would not need to load SeaBIOS at all.

This would be something similar to what FILO, GRUB 2 and gPXE do I
guess. Even mkelfImage.


> >> ?- Can we move more hardware init and drivers from coreboot into
> >> u-boot and provide more commands in u-boot for coreboot
> >> supported boards
> > Code duplication? *shudder*
> 
> The point being that U-Boot provides a shell and command line with
> diagnostic features. These require hooks into the hardware drivers.

coreboot does not generally have drivers. coreboot knows how to do
the init, but the payload is responsible for driving any hardware
that needs to be driven.

One could argue that coreboot is only a collection of CPU and chipset
drivers, which so far have very few if any knobs.


> >> ?- VGA & Keyboard support
> >> ?- U-Boot splash screen support
> > libpayload
> >
> >> ?- Flash updates from u-boot
> > libflashrom (work in progress)
> 
> How will these work in practice? Where are they initiated from?

coreboot starts one payload.

The payload can be very easily created with libpayload, a C library
that we have created in order to make it easy to create payloads. Run
lpgcc instead of gcc to link against libpayload. Some
coreboot-specific functions like accessing the coreboot tables are
available, and a good deal of libc compatibility.

Besides using libpayload, U-Boot would also use libflashrom, to take
advantage of the rich boot flash writing code that is flashrom also
at boot time.


//Peter



From graeme.russ at gmail.com  Tue May 10 02:53:17 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Tue, 10 May 2011 10:53:17 +1000
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <20110510003002.32657.qmail@stuge.se>
References: <4DC77D9C.8010804@assembler.cz> <4DC7DB81.9090501@gmail.com>
	<4DC820D9.4000303@georgi-clan.de>
	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>
	<20110510003002.32657.qmail@stuge.se>
Message-ID: <BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>

On Tue, May 10, 2011 at 10:30 AM, Peter Stuge <peter at stuge.se> wrote:
> Graeme Russ wrote:
>> Well, I do not know the semantic architecture of coreboot :)
>
> Welcome to the list.

Thanks

>
>
>> In addition to 'boot OS and die', U-Boot has a 'standalone
>> application' API which allows a 'payload' to be run with control
>> returning to U-Boot. If coreboot does not have any such concept
>> then you are right, no need to worry about returning back to
>> coreboot
>
> coreboot does not.
>

OK - No need to worry about re-entering coreboot then :)

>
>> > memory size is in cbtable, payloads are ELF by convention
> ..
>>
>> My point being that U-Boot needs to know about the arrangement of
>> memory of the target board.
>
> Yes. The information is published by coreboot in the "coreboot table"
> AKA cbtable. libpayload already has code to find it.

Hmm - I don't think linking U-Boot against libpayload is the right
solution. U-Boot is designed to be the primary bootloader
much like coreboot is - It is not a 'payload'. There is a rather special
case with NAND booting where a bootstrap loader loads U-Boot into RAM,
but even in this case U-Boot is treated like a binary blob exectuted
in RAM with no real concept of how it got there (i.e. no link-backs to
the 'loader')

>
>> The idea of adding support for relocatable ELF images to libpayload is
>> interesting. If coreboot can load U-Boot at an appropriate target
>> address than we can skip a memcpy and relocation fixup loop in U-Boot.
>
> I think the coreboot loader does this already. If U-Boot is built as
> an ELF located at the appropriate target address then that's where
> coreboot will run it from.
>

U-Boot is build with the target address in Flash. It initialises memory
and copies itself into RAM at an address calculated by the RAM init code.
It then processes the ELF symbol table (embedded in the raw binary image)
to adjust memory addresses in the in-RAM copy before jumping out of flash
and into RAM

So what would be really neat is if coreboot calculated where the final
in-RAM location of U-Boot needs to be, copy U-Boot there, do the
relocation fixups and jumps into the in-RAM copy of U-Boot. U-Boot would
then skip all it's own relocation code. The other option is to not use
coreboot's ELF loader and simply have coreboot jump to the U-Boot binary
image in Flash. This is a far simpler method, and all the code already
exists in U-Boot anyway - all we need to do is tell U-Boot the highest
available memory address.

>
>> >> ?- Can u-boot piggy-back on SeaBIOS loaded by coreboot?
>> > In the context of coreboot: why?
>>
>> Again, probably a missunderstanding of coreboot on my behalf -
>> U-Boot has a REALLY primative BIOS implementation (just enough to
>> trick Linux into booting in an embedded environment). It is
>> basically just some empty VGA stubs and simple e820 support. If
>> coreboot can load SeaBIOS, U-Boot could transition to it and I
>> could ditch all of the real-mode support from U-Boot.
>
> coreboot starts one payload and one payload only. SeaBIOS when built
> as payload for coreboot can actually start other files in the boot
> flash that are identical to the coreboot payload.
>
> The sequence would then be coreboot->SeaBIOS->U-Boot. Note that
> coreboot is not a BIOS and does not want to be a BIOS.

Neither is (or does) U-Boot. But in order to load many OSs, there needs
(unfortunately) to be some BIOS functionality.

>
>> This could allow U-Boot to support booting of OSs that require a BIOS.
>
> That should work fine if SeaBIOS is inserted before U-Boot and can
> set up the complete BIOS environment.
>

Sounds good

>
>> For Linux, I can implement a protected mode transition from U-Boot
>> for which we would not need to load SeaBIOS at all.
>
> This would be something similar to what FILO, GRUB 2 and gPXE do I
> guess. Even mkelfImage.
>
>
>> >> ?- Can we move more hardware init and drivers from coreboot into
>> >> u-boot and provide more commands in u-boot for coreboot
>> >> supported boards
>> > Code duplication? *shudder*
>>
>> The point being that U-Boot provides a shell and command line with
>> diagnostic features. These require hooks into the hardware drivers.
>
> coreboot does not generally have drivers. coreboot knows how to do
> the init, but the payload is responsible for driving any hardware
> that needs to be driven.
>
> One could argue that coreboot is only a collection of CPU and chipset
> drivers, which so far have very few if any knobs.

U-Boot is similar, but having a command line and shell which can run
scripts means that it can do a bit more with the hardware (set Ethernet
MAC addresses, intialise devices on I2C busses, display a bitmap splash
screen, toggle LEDs etc)

>
>
>> >> ?- VGA & Keyboard support
>> >> ?- U-Boot splash screen support
>> > libpayload
>> >
>> >> ?- Flash updates from u-boot
>> > libflashrom (work in progress)
>>
>> How will these work in practice? Where are they initiated from?
>
> coreboot starts one payload.
>
> The payload can be very easily created with libpayload, a C library
> that we have created in order to make it easy to create payloads. Run
> lpgcc instead of gcc to link against libpayload. Some
> coreboot-specific functions like accessing the coreboot tables are
> available, and a good deal of libc compatibility.
>
> Besides using libpayload, U-Boot would also use libflashrom, to take
> advantage of the rich boot flash writing code that is flashrom also
> at boot time.

As I said earlier, I don't want to tie U-Boot to libpayload. With regard
to VGA and keyboard support, how can we make them usable in U-Boot (i.e.
so the command prompt is displayed on a monitor and the user can use the
keyboard to enter commands?)

Regards,

Graeme



From peter at stuge.se  Tue May 10 03:15:42 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 10 May 2011 03:15:42 +0200
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>
References: <4DC77D9C.8010804@assembler.cz> <4DC7DB81.9090501@gmail.com>
	<4DC820D9.4000303@georgi-clan.de>
	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>
	<20110510003002.32657.qmail@stuge.se>
	<BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>
Message-ID: <20110510011542.4938.qmail@stuge.se>

Graeme Russ wrote:
> >> My point being that U-Boot needs to know about the arrangement of
> >> memory of the target board.
> >
> > Yes. The information is published by coreboot in the "coreboot table"
> > AKA cbtable. libpayload already has code to find it.
> 
> Hmm - I don't think linking U-Boot against libpayload is the right
> solution.

Why not?


> U-Boot is designed to be the primary bootloader much like coreboot
> is - It is not a 'payload'.

If coreboot is participating then yes, U-Boot is the (coreboot)
payload. The idea is to leverage the shell and bootloading features
of U-Boot, after the platform initialization in coreboot has run.


> There is a rather special case with NAND booting where a bootstrap
> loader loads U-Boot into RAM, but even in this case U-Boot is
> treated like a binary blob exectuted in RAM with no real concept of
> how it got there (i.e. no link-backs to the 'loader')

Make no mistake, coreboot payloads have no link-back to the 'loader'.

I guess this is getting a little confusing because both projects use
the term payload to mean different things.


> U-Boot is build with the target address in Flash. It initialises memory
> and copies itself into RAM at an address calculated by the RAM init code.

Here there should probably be a second possible entry point, for when
U-Boot is a coreboot payload.


> It then processes the ELF symbol table (embedded in the raw binary image)
> to adjust memory addresses in the in-RAM copy before jumping out of flash
> and into RAM

I guess this processing would remain, but the bytes it operates on
would already be in RAM.


> So what would be really neat is if coreboot calculated where the final
> in-RAM location of U-Boot needs to be,

This is decided at (coreboot payload) build time.


> copy U-Boot there,

Sure thing.


> do the relocation fixups

But possibly not this one.


> and jumps into the in-RAM copy of U-Boot.

Yep.


> U-Boot would then skip all it's own relocation code.

ELF is the way to happiness in coreboot land. coreboot would like a
U-Boot ELF binary and will copy it to given address in RAM and run
it.


> The other option is to not use coreboot's ELF loader and simply
> have coreboot jump to the U-Boot binary image in Flash.

Does not fit the coreboot model so well. Something could be hacked of
course, but that's not so nice..


> This is a far simpler method, and all the code already exists in
> U-Boot anyway - all we need to do is tell U-Boot the highest
> available memory address.

That can be read from the cbtable.


> > coreboot does not generally have drivers. coreboot knows how to do
> > the init, but the payload is responsible for driving any hardware
> > that needs to be driven.
> >
> > One could argue that coreboot is only a collection of CPU and chipset
> > drivers, which so far have very few if any knobs.
> 
> U-Boot is similar, but having a command line and shell which can
> run scripts means that it can do a bit more with the hardware (set
> Ethernet MAC addresses, intialise devices on I2C busses, display a
> bitmap splash screen, toggle LEDs etc)

My point was that coreboot has no drivers of that sort. :)


> > Besides using libpayload, U-Boot would also use libflashrom, to take
> > advantage of the rich boot flash writing code that is flashrom also
> > at boot time.
> 
> As I said earlier, I don't want to tie U-Boot to libpayload.

Again, why not? For the particular U-Boot build that runs as coreboot
payload it should save a lot of development time.


> With regard to VGA and keyboard support, how can we make them
> usable in U-Boot (i.e. so the command prompt is displayed on a
> monitor and the user can use the keyboard to enter commands?)

If U-Boot will require SeaBIOS then some VGA option ROM will likely
have been executed and all the standard BIOS services for console are
there.

When U-Boot is the coreboot payload there are no BIOS services, and
U-Boot needs to implement everything on it's own. Or it can use
libpayload, which already has console support for a few hardware
types.


//Peter



From graeme.russ at gmail.com  Tue May 10 04:18:58 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Tue, 10 May 2011 12:18:58 +1000
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <20110510011542.4938.qmail@stuge.se>
References: <4DC77D9C.8010804@assembler.cz> <4DC7DB81.9090501@gmail.com>
	<4DC820D9.4000303@georgi-clan.de>
	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>
	<20110510003002.32657.qmail@stuge.se>
	<BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>
	<20110510011542.4938.qmail@stuge.se>
Message-ID: <BANLkTimTQmUVyEGO-RauWktpuz8MVm7vQw@mail.gmail.com>

On Tue, May 10, 2011 at 11:15 AM, Peter Stuge <peter at stuge.se> wrote:
> Graeme Russ wrote:
>> >> My point being that U-Boot needs to know about the arrangement of
>> >> memory of the target board.
>> >
>> > Yes. The information is published by coreboot in the "coreboot table"
>> > AKA cbtable. libpayload already has code to find it.
>>
>> Hmm - I don't think linking U-Boot against libpayload is the right
>> solution.
>
> Why not?

a) High probablility of impacting on the U-Boot build process (you mention
   using lpgcc rather than gcc)
b) Breaks the ethos of U-Boot being a self-contained binary image
   intended to be written directly to a boot Flash
c) The U-Boot maintainer (Wolfgang Denk) won't allow patches that result
   in U-Boot relying on code external to the U-Boot git tree. All that
   should ever be required to build U-Boot is a pull from the U-Boot git
   tree and standard set of build tools (compiler and linker)

>
>> U-Boot is designed to be the primary bootloader much like coreboot
>> is - It is not a 'payload'.
>
> If coreboot is participating then yes, U-Boot is the (coreboot)
> payload. The idea is to leverage the shell and bootloading features
> of U-Boot, after the platform initialization in coreboot has run.
>
>
>> There is a rather special case with NAND booting where a bootstrap
>> loader loads U-Boot into RAM, but even in this case U-Boot is
>> treated like a binary blob exectuted in RAM with no real concept of
>> how it got there (i.e. no link-backs to the 'loader')
>
> Make no mistake, coreboot payloads have no link-back to the 'loader'.

I guess I need to understand what, exactly, libpayload is all about. I
get the impression that, while not a link-back to coreboot, it does
provide a set of low-level APIs (some of which provide access to data
structures created by coreboot and some to access hardware features)

> I guess this is getting a little confusing because both projects use
> the term payload to mean different things.

U-Boot does not have a 'payload' - It has a 'standalone application' which
can be invoked with control returning back to U-Boot and an OS 'image'
which, when invoked, typically results in U-Boot being 'blown away'

>
>> U-Boot is build with the target address in Flash. It initialises memory
>> and copies itself into RAM at an address calculated by the RAM init code.
>
> Here there should probably be a second possible entry point, for when
> U-Boot is a coreboot payload.

Already exists - It is the very first byte of u-boot.bin (which is a dozen
or so bytes before the entry point used by the x86 cold-reset vector code

I mentioned in an unrelated email that the U-Boot linker script needs to
be adjusted to fix the ELF entry point

>
>> It then processes the ELF symbol table (embedded in the raw binary image)
>> to adjust memory addresses in the in-RAM copy before jumping out of flash
>> and into RAM
>
> I guess this processing would remain, but the bytes it operates on
> would already be in RAM.
>
>
>> So what would be really neat is if coreboot calculated where the final
>> in-RAM location of U-Boot needs to be,
>
> This is decided at (coreboot payload) build time.

The in-RAM location of U-Boot is dynamically determined after RAM is
initialised so as to place U-Boot as high in memory as possible to allow
for the maximum amount of contiuous RAM below U-Boot

>
>> copy U-Boot there,
>
> Sure thing.
>
>> do the relocation fixups
>
> But possibly not this one.
>
>> and jumps into the in-RAM copy of U-Boot.
>
> Yep.
>
>> U-Boot would then skip all it's own relocation code.
>
> ELF is the way to happiness in coreboot land. coreboot would like a
> U-Boot ELF binary and will copy it to given address in RAM and run
> it.

This is only viable if coreboot can:
  - Load U-Boot to an arbitrary memory address based on total available
    system RAM
  - Perform the relocation fixups (which are fairly trival to imeplement -
    Look in u-boot's arch/x86/lib/board.c for details)
  - Does not require U-Boot to be linked against libpayload (which is
    possibly negotiable ;)

>> The other option is to not use coreboot's ELF loader and simply
>> have coreboot jump to the U-Boot binary image in Flash.
>
> Does not fit the coreboot model so well. Something could be hacked of
> course, but that's not so nice..

Hmm, can we wrap u-boot.bin in a 'payload' - In U-Boot, you create an
'image' using the mkimage tool. U-Boot images support a range of formats
including compressed/uncompress, raw/ELF etc. I suppose it is as close
to a coreboot 'payload' as you can get, but does not carry any API for
the contents of the image to use. The image content is always stand-alone
with U-Boot providing the API. Correct me if I am wrong, but it would
seem with coreboot that once the 'payload' is launched, coreboot is
gone and the only API available is what is in libpayload

>
>> This is a far simpler method, and all the code already exists in
>> U-Boot anyway - all we need to do is tell U-Boot the highest
>> available memory address.
>
> That can be read from the cbtable.

Which is only available via libpayload? - Can a link to cbtable be
provided via a reserved register (perhaps a reseved segment even)

>> > coreboot does not generally have drivers. coreboot knows how to do
>> > the init, but the payload is responsible for driving any hardware
>> > that needs to be driven.
>> >
>> > One could argue that coreboot is only a collection of CPU and chipset
>> > drivers, which so far have very few if any knobs.
>>
>> U-Boot is similar, but having a command line and shell which can
>> run scripts means that it can do a bit more with the hardware (set
>> Ethernet MAC addresses, intialise devices on I2C busses, display a
>> bitmap splash screen, toggle LEDs etc)
>
> My point was that coreboot has no drivers of that sort. :)

But it does have more code for hardware that U-Boot :) Typically U-Boot
drivers are derived from Linux, so maybe coreboot's codebase is not
going to be as helpful as I might have thought. The question is, does
coreboot knows about any hardware that Linux does not?

>> > Besides using libpayload, U-Boot would also use libflashrom, to take
>> > advantage of the rich boot flash writing code that is flashrom also
>> > at boot time.
>>
>> As I said earlier, I don't want to tie U-Boot to libpayload.
>
> Again, why not? For the particular U-Boot build that runs as coreboot
> payload it should save a lot of development time.
>
>
>> With regard to VGA and keyboard support, how can we make them
>> usable in U-Boot (i.e. so the command prompt is displayed on a
>> monitor and the user can use the keyboard to enter commands?)
>
> If U-Boot will require SeaBIOS then some VGA option ROM will likely
> have been executed and all the standard BIOS services for console are
> there.
>
> When U-Boot is the coreboot payload there are no BIOS services, and
> U-Boot needs to implement everything on it's own. Or it can use
> libpayload, which already has console support for a few hardware
> types.

OK, so I think there are three things to really look into:
  - Giving coreboot to ability to load a relocatable ELF image to an
    arbitrary RAM location and performing the necessary relocation fixups
  - libpayload
  - Console I/O in U-Boot (porting support available in libpayload into
    U-Boot?)

Regards,

Graeme



From stefan.reinauer at coreboot.org  Tue May 10 06:06:28 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 09 May 2011 21:06:28 -0700
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>
References: <4DC77D9C.8010804@assembler.cz>
	<4DC7DB81.9090501@gmail.com>	<4DC820D9.4000303@georgi-clan.de>
	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>
Message-ID: <4DC8B9C4.2080902@coreboot.org>

On 5/9/11 4:20 PM, Graeme Russ wrote:
> Again, probably a missunderstanding of coreboot on my behalf - U-Boot has
> a REALLY primative BIOS implementation (just enough to trick Linux into
> booting in an embedded environment). It is basically just some empty VGA
> stubs and simple e820 support.
Why don't you use the 32bit entry point of the Linux kernel? Grub2 does 
this (at least on coreboot), FILO and mkelfImage too.

Would be nice to (at least be able to) boot Linux without real mode code 
being involved.

Stefan



From stefan.reinauer at coreboot.org  Tue May 10 06:22:23 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 09 May 2011 21:22:23 -0700
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>
References: <4DC77D9C.8010804@assembler.cz>
	<4DC7DB81.9090501@gmail.com>	<4DC820D9.4000303@georgi-clan.de>	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>	<20110510003002.32657.qmail@stuge.se>
	<BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>
Message-ID: <4DC8BD7F.50509@coreboot.org>

On 5/9/11 5:53 PM, Graeme Russ wrote:
>> Yes. The information is published by coreboot in the "coreboot table"
>> AKA cbtable. libpayload already has code to find it.
> Hmm - I don't think linking U-Boot against libpayload is the right
> solution. U-Boot is designed to be the primary bootloader
> much like coreboot is - It is not a 'payload'. There is a rather special
> case with NAND booting where a bootstrap loader loads U-Boot into RAM,
> but even in this case U-Boot is treated like a binary blob exectuted
> in RAM with no real concept of how it got there (i.e. no link-backs to
> the 'loader')
That's not the case for all platforms. On Nvidia Tegra2 there is a boot 
rom loading uboot. I remember on the Dbox uboot was piggybacked on the 
original firmware, too. At the least, uboot should play nice in such 
scenarios (which I think it does)
> U-Boot is build with the target address in Flash. It initialises memory
> and copies itself into RAM at an address calculated by the RAM init code.
> It then processes the ELF symbol table (embedded in the raw binary image)
> to adjust memory addresses in the in-RAM copy before jumping out of flash
> and into RAM

We should add a configuration option to avoid this copying with respect 
to boot time.

> So what would be really neat is if coreboot calculated where the final
> in-RAM location of U-Boot needs to be, copy U-Boot there, do the
> relocation fixups and jumps into the in-RAM copy of U-Boot.
Another option would be to have uboot do a virtual/physical mapping that 
allows us to skip the run time linking. As the copying, it's a (small 
but measurable) waste of time, and it makes the code unnecessarily 
complex. I'm not suggesting to remove this feature, but I think it 
should be configurable (and disabled for coreboot and anyone else who 
aims at booting quickly)
> U-Boot would
> then skip all it's own relocation code. The other option is to not use
> coreboot's ELF loader and simply have coreboot jump to the U-Boot binary
> image in Flash. This is a far simpler method, and all the code already
> exists in U-Boot anyway - all we need to do is tell U-Boot the highest
> available memory address.
coreboot does its ELF parsing at build time, not at runtime. This way we 
save yet another copy while preserving the option of compressing the 
payload (e.g. uboot) in flash.

>> The sequence would then be coreboot->SeaBIOS->U-Boot. Note that
>> coreboot is not a BIOS and does not want to be a BIOS.
> Neither is (or does) U-Boot. But in order to load many OSs, there needs
> (unfortunately) to be some BIOS functionality.
Piggybacking coreboot->seabios->uboot should not be a big deal, but the 
most common use case for uboot is booting Linux, not Windows or other 
bios prone OSes. Let's do one step after another.

>>>>>   - Can we move more hardware init and drivers from coreboot into
>>>>> u-boot and provide more commands in u-boot for coreboot
>>>>> supported boards
>>>> Code duplication? *shudder*
>>> The point being that U-Boot provides a shell and command line with
>>> diagnostic features. These require hooks into the hardware drivers.
>> coreboot does not generally have drivers. coreboot knows how to do
>> the init, but the payload is responsible for driving any hardware
>> that needs to be driven.
>>
>> One could argue that coreboot is only a collection of CPU and chipset
>> drivers, which so far have very few if any knobs.
> U-Boot is similar, but having a command line and shell which can run
> scripts means that it can do a bit more with the hardware (set Ethernet
> MAC addresses, intialise devices on I2C busses, display a bitmap splash
> screen, toggle LEDs etc)
Those things are often not available or required on the systems coreboot 
runs on.

>>>>>   - VGA&  Keyboard support
>>>>>   - U-Boot splash screen support
>>>> libpayload
>>>>
>>>>>   - Flash updates from u-boot
>>>> libflashrom (work in progress)
I don't think we want to plug flashrom into uboot (not in the beginning 
anyways) nor libpayload. Let's keep this minimal and then see what's 
actually missing. A clean design is more important right now than 
overplugging uboot with foreign libraries.

> As I said earlier, I don't want to tie U-Boot to libpayload. With regard
> to VGA and keyboard support, how can we make them usable in U-Boot (i.e.
> so the command prompt is displayed on a monitor and the user can use the
> keyboard to enter commands?)
Does uboot provide a USB stack on PCs (e.g. UHCI/OHCI/EHCI/XHCI)... 
those might be interesting parts of libpayload in the longer run.
For now, just adding a simple keyboard and vga driver should be fairly 
simple. It would be nice to also have an option for running on a linear 
framebuffer (with the framebuffer specs read from the coreboot table)

Stefan







From stefan.reinauer at coreboot.org  Tue May 10 06:32:38 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 09 May 2011 21:32:38 -0700
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <20110510011542.4938.qmail@stuge.se>
References: <4DC77D9C.8010804@assembler.cz>
	<4DC7DB81.9090501@gmail.com>	<4DC820D9.4000303@georgi-clan.de>	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>	<20110510003002.32657.qmail@stuge.se>	<BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>
	<20110510011542.4938.qmail@stuge.se>
Message-ID: <4DC8BFE6.5030601@coreboot.org>

On 5/9/11 6:15 PM, Peter Stuge wrote:
> Graeme Russ wrote:
>> U-Boot is build with the target address in Flash. It initialises memory
>> and copies itself into RAM at an address calculated by the RAM init code.
> Here there should probably be a second possible entry point, for when
> U-Boot is a coreboot payload.
>
Let's just add a compile time option and select that for a coreboot 
build. I don't think we need additional entry points.

KISS has always served us well.

>> It then processes the ELF symbol table (embedded in the raw binary image)
>> to adjust memory addresses in the in-RAM copy before jumping out of flash
>> and into RAM
> I guess this processing would remain, but the bytes it operates on
> would already be in RAM.
Please, no! Why would you do something at run time on every boot when 
you can do it at compile/build time?

It's firmware, not an OS. (Even if popular belief claims there is no 
difference)

>> As I said earlier, I don't want to tie U-Boot to libpayload.
> Again, why not? For the particular U-Boot build that runs as coreboot
> payload it should save a lot of development time.
>

I think copying over those one or two files from libpayload would allow 
to keep uboot without any build time dependencies, which sounds like a 
good thing and possibly worth the code duplication. Note that Rudolfs 
port already copies a small portion of libpayload code because he felt 
that the libpayload integration would make the code more complex than 
the code duplication. And I agree in this case.

> If U-Boot will require SeaBIOS then some VGA option ROM will likely
> have been executed and all the standard BIOS services for console are
> there.
>
> When U-Boot is the coreboot payload there are no BIOS services, and
> U-Boot needs to implement everything on it's own.
Not everything. It can rely on coreboot initializing video (and a 
framebuffer for example)

I think both above scenarios would make an excellent configuration choice in uboot, providing support for whatever the user wants.

On systems with SeaBIOS you probably don't care for uboot anyways as the additional benefit is rather small. On other systems where SeaBIOS is not the payload of choice uboot is much more interesting (for now)


Stefan



From stefan.reinauer at coreboot.org  Tue May 10 06:46:45 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 09 May 2011 21:46:45 -0700
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <BANLkTimTQmUVyEGO-RauWktpuz8MVm7vQw@mail.gmail.com>
References: <4DC77D9C.8010804@assembler.cz>
	<4DC7DB81.9090501@gmail.com>	<4DC820D9.4000303@georgi-clan.de>	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>	<20110510003002.32657.qmail@stuge.se>	<BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>	<20110510011542.4938.qmail@stuge.se>
	<BANLkTimTQmUVyEGO-RauWktpuz8MVm7vQw@mail.gmail.com>
Message-ID: <4DC8C335.1010705@coreboot.org>

On 5/9/11 7:18 PM, Graeme Russ wrote:
> On Tue, May 10, 2011 at 11:15 AM, Peter Stuge<peter at stuge.se>  wrote:
>> Graeme Russ wrote:
>>>>> My point being that U-Boot needs to know about the arrangement of
>>>>> memory of the target board.
>>>> Yes. The information is published by coreboot in the "coreboot table"
>>>> AKA cbtable. libpayload already has code to find it.
>>> Hmm - I don't think linking U-Boot against libpayload is the right
>>> solution.
>> Why not?
> a) High probablility of impacting on the U-Boot build process (you mention
>     using lpgcc rather than gcc)
FILO uses libpayload without lpgcc (and in fact I think we should 
obsolete lpgcc)

> b) Breaks the ethos of U-Boot being a self-contained binary image
>     intended to be written directly to a boot Flash
No. It's just a static library. Unlike uboot, it does not do any run 
time relocation and linking ;-)

> c) The U-Boot maintainer (Wolfgang Denk) won't allow patches that result
>     in U-Boot relying on code external to the U-Boot git tree. All that
>     should ever be required to build U-Boot is a pull from the U-Boot git
>     tree and standard set of build tools (compiler and linker)
Ok, I am sure politics will get in the way at some point, but that is 
something that should not limit our initial design.

If you build uboot for coreboot, you will have libpayload checked out 
anyways. So that would not be too ugly.

However, unless we start using large portions (e.g. more than 3-4 files 
from libpayload) we should just copy them over and not worry. Worst case 
we have another target we have to fix if something in libpayload changes.

>> This is decided at (coreboot payload) build time.
> The in-RAM location of U-Boot is dynamically determined after RAM is
> initialised so as to place U-Boot as high in memory as possible to allow
> for the maximum amount of contiuous RAM below U-Boot
What's the practical use case of this? While I see a point in having 
stand alone applications return, a (Linux) kernel will most likely not. 
At least not on x86.


> This is only viable if coreboot can:
>    - Load U-Boot to an arbitrary memory address based on total available
>      system RAM
>    - Perform the relocation fixups (which are fairly trival to imeplement -
>      Look in u-boot's arch/x86/lib/board.c for details)
>    - Does not require U-Boot to be linked against libpayload (which is
>      possibly negotiable ;)
I would rather want to renegotiate adding a linker to coreboot and do 
that at compile time rather than runtime. The x86 CPU provides excellent 
features that make such a relinking unnecessary.

> Hmm, can we wrap u-boot.bin in a 'payload'

Preferably I would not add additional layers/wrappers around uboot. Boot 
time is precious.

>> My point was that coreboot has no drivers of that sort. :)
> But it does have more code for hardware that U-Boot :) Typically U-Boot
> drivers are derived from Linux, so maybe coreboot's codebase is not
> going to be as helpful as I might have thought. The question is, does
> coreboot knows about any hardware that Linux does not?

Yes, lots of it. But Linux does not need that knowledge (and neither 
should uboot)

I think the code in uboot might be fine except for the lack of support 
for PC specific components (IDE, VGA output, PS2 input, XHCI/USB3 boot, ...)

That stuff traditionally lives in libpayload (or the payload) for us, 
not in coreboot. Coreboot takes care of RAM controllers, HT links, PCIe 
links, DMI links, etc. By the time uboot runs it can assume that all 
necessary devices already live on what looks like a PCI bus.


> OK, so I think there are three things to really look into:
>    - Giving coreboot to ability to load a relocatable ELF image to an
>      arbitrary RAM location and performing the necessary relocation fixups

Can I bribe?

>    - libpayload
I'd be fine with just ripping what we need for now, like this:

>    - Console I/O in U-Boot (porting support available in libpayload into
>      U-Boot?)







From graeme.russ at gmail.com  Tue May 10 06:47:28 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Tue, 10 May 2011 14:47:28 +1000
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC8BFE6.5030601@coreboot.org>
References: <4DC77D9C.8010804@assembler.cz> <4DC7DB81.9090501@gmail.com>
	<4DC820D9.4000303@georgi-clan.de>
	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>
	<20110510003002.32657.qmail@stuge.se>
	<BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>
	<20110510011542.4938.qmail@stuge.se>
	<4DC8BFE6.5030601@coreboot.org>
Message-ID: <BANLkTi=D443FuQHoQD4VG_ZBshhUUhGQgQ@mail.gmail.com>

Stefan,

On Tue, May 10, 2011 at 2:32 PM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> On 5/9/11 6:15 PM, Peter Stuge wrote:
>>
>> Graeme Russ wrote:
>>>
>>> U-Boot is build with the target address in Flash. It initialises memory
>>> and copies itself into RAM at an address calculated by the RAM init code.
>>
>> Here there should probably be a second possible entry point, for when
>> U-Boot is a coreboot payload.
>>
> Let's just add a compile time option and select that for a coreboot build. I
> don't think we need additional entry points.
>
> KISS has always served us well.
>

The second entry point already exists - It is an extremely small overhead
in the U-Boot source and I have been using it extensively to load new
images for testing into RAM and bypassing the cold-reset vector and
initial setup of a temporary GDT - It's value far outweighs the expense

>>> It then processes the ELF symbol table (embedded in the raw binary image)
>>> to adjust memory addresses in the in-RAM copy before jumping out of flash
>>> and into RAM
>>
>> I guess this processing would remain, but the bytes it operates on
>> would already be in RAM.
>
> Please, no! Why would you do something at run time on every boot when you
> can do it at compile/build time?

Because U-Boot is designed to load itself into the highest possible memory
address to provide a maximum RAM footprint to whatever image it loads.
Also, there is no guarantee of a particular amount of RAM existing. This
is not an x86 specific feature - This is a core U-Boot design principle

> It's firmware, not an OS. (Even if popular belief claims there is no
> difference)
>
>>> As I said earlier, I don't want to tie U-Boot to libpayload.
>>
>> Again, why not? For the particular U-Boot build that runs as coreboot
>> payload it should save a lot of development time.
>>
>
> I think copying over those one or two files from libpayload would allow to
> keep uboot without any build time dependencies, which sounds like a good
> thing and possibly worth the code duplication. Note that Rudolfs port
> already copies a small portion of libpayload code because he felt that the
> libpayload integration would make the code more complex than the code
> duplication. And I agree in this case.

Yes, I think small bits of libpayload could be easily integrated

>> If U-Boot will require SeaBIOS then some VGA option ROM will likely
>> have been executed and all the standard BIOS services for console are
>> there.
>>
>> When U-Boot is the coreboot payload there are no BIOS services, and
>> U-Boot needs to implement everything on it's own.
>
> Not everything. It can rely on coreboot initializing video (and a
> framebuffer for example)
>
> I think both above scenarios would make an excellent configuration choice in
> uboot, providing support for whatever the user wants.
>
> On systems with SeaBIOS you probably don't care for uboot anyways as the
> additional benefit is rather small. On other systems where SeaBIOS is not
> the payload of choice uboot is much more interesting (for now)

Well I think the examination of use cases could get very interesting. For
the time being, I think there are two options:

 1) Load SeaBIOS and then launch U-Boot and have U-Boot use the BIOS
    routines provided by SeaBIOS for I/O
 2) Incorporate parts of libpayload (and potentially bits of SeaBIOS
    implemented in 32-bit protected mode) into U-Boot and launch U-Boot
    directly

I think we could start with 1) and then transition to 2) over time. Note
that for 2), U-Boot could also provide a very thin 'BIOS wrapper' which
would translate 16-bit BIOS calls into the U-Boot core via for (optional)
support of legacy applications

Regards,

Graeme



From graeme.russ at gmail.com  Tue May 10 06:58:53 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Tue, 10 May 2011 14:58:53 +1000
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC8BD7F.50509@coreboot.org>
References: <4DC77D9C.8010804@assembler.cz> <4DC7DB81.9090501@gmail.com>
	<4DC820D9.4000303@georgi-clan.de>
	<BANLkTimyqOZadLG+T3-9OdsgvoToRqqhtQ@mail.gmail.com>
	<20110510003002.32657.qmail@stuge.se>
	<BANLkTin18NENUG=80CG1uxqCfbtEF-i==w@mail.gmail.com>
	<4DC8BD7F.50509@coreboot.org>
Message-ID: <BANLkTi=vNh5M5865tXyeYysX4GUnL2sxzw@mail.gmail.com>

On Tue, May 10, 2011 at 2:22 PM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> On 5/9/11 5:53 PM, Graeme Russ wrote:
>>>
>>> Yes. The information is published by coreboot in the "coreboot table"
>>> AKA cbtable. libpayload already has code to find it.
>>
>> Hmm - I don't think linking U-Boot against libpayload is the right
>> solution. U-Boot is designed to be the primary bootloader
>> much like coreboot is - It is not a 'payload'. There is a rather special
>> case with NAND booting where a bootstrap loader loads U-Boot into RAM,
>> but even in this case U-Boot is treated like a binary blob exectuted
>> in RAM with no real concept of how it got there (i.e. no link-backs to
>> the 'loader')
>
> That's not the case for all platforms. On Nvidia Tegra2 there is a boot rom
> loading uboot. I remember on the Dbox uboot was piggybacked on the original
> firmware, too. At the least, uboot should play nice in such scenarios (which
> I think it does)

Yes, there are other bootstrap loaders, but U-Boot is still a raw binary
image without any kind of payload wrapper as far as I am aware

>>
>> U-Boot is build with the target address in Flash. It initialises memory
>> and copies itself into RAM at an address calculated by the RAM init code.
>> It then processes the ELF symbol table (embedded in the raw binary image)
>> to adjust memory addresses in the in-RAM copy before jumping out of flash
>> and into RAM
>
> We should add a configuration option to avoid this copying with respect to
> boot time.

Nope - U-Boot is specifically designed to move itself into RAM - A primary
reason for moving into RAM is so the ROM can be re-flashed. This is
particularly neccessary when the U-Boot environment variables are embedded
in the U-Boot image

>
>> So what would be really neat is if coreboot calculated where the final
>> in-RAM location of U-Boot needs to be, copy U-Boot there, do the
>> relocation fixups and jumps into the in-RAM copy of U-Boot.
>
> Another option would be to have uboot do a virtual/physical mapping that
> allows us to skip the run time linking. As the copying, it's a (small but
> measurable) waste of time, and it makes the code unnecessarily complex. I'm
> not suggesting to remove this feature, but I think it should be configurable
> (and disabled for coreboot and anyone else who aims at booting quickly)
>>
>> U-Boot would
>> then skip all it's own relocation code. The other option is to not use
>> coreboot's ELF loader and simply have coreboot jump to the U-Boot binary
>> image in Flash. This is a far simpler method, and all the code already
>> exists in U-Boot anyway - all we need to do is tell U-Boot the highest
>> available memory address.
>
> coreboot does its ELF parsing at build time, not at runtime. This way we
> save yet another copy while preserving the option of compressing the payload
> (e.g. uboot) in flash.
>
>>> The sequence would then be coreboot->SeaBIOS->U-Boot. Note that
>>> coreboot is not a BIOS and does not want to be a BIOS.
>>
>> Neither is (or does) U-Boot. But in order to load many OSs, there needs
>> (unfortunately) to be some BIOS functionality.
>
> Piggybacking coreboot->seabios->uboot should not be a big deal, but the most
> common use case for uboot is booting Linux, not Windows or other bios prone
> OSes. Let's do one step after another.
>
>>>>>> ?- Can we move more hardware init and drivers from coreboot into
>>>>>> u-boot and provide more commands in u-boot for coreboot
>>>>>> supported boards
>>>>>
>>>>> Code duplication? *shudder*
>>>>
>>>> The point being that U-Boot provides a shell and command line with
>>>> diagnostic features. These require hooks into the hardware drivers.
>>>
>>> coreboot does not generally have drivers. coreboot knows how to do
>>> the init, but the payload is responsible for driving any hardware
>>> that needs to be driven.
>>>
>>> One could argue that coreboot is only a collection of CPU and chipset
>>> drivers, which so far have very few if any knobs.
>>
>> U-Boot is similar, but having a command line and shell which can run
>> scripts means that it can do a bit more with the hardware (set Ethernet
>> MAC addresses, intialise devices on I2C busses, display a bitmap splash
>> screen, toggle LEDs etc)
>
> Those things are often not available or required on the systems coreboot
> runs on.

au contraire - PC's have lots of little bits and pieces (like thermal
monitoring, fan speed monitoring/setting etc) - It may be very useful to
have access to these from the U-Boot command line / script.

>
>>>>>> ?- VGA& ?Keyboard support
>>>>>> ?- U-Boot splash screen support
>>>>>
>>>>> libpayload
>>>>>
>>>>>> ?- Flash updates from u-boot
>>>>>
>>>>> libflashrom (work in progress)
>
> I don't think we want to plug flashrom into uboot (not in the beginning
> anyways) nor libpayload. Let's keep this minimal and then see what's
> actually missing. A clean design is more important right now than
> overplugging uboot with foreign libraries.

We can always run flashrom as a standalone app from U-Boot

>
>> As I said earlier, I don't want to tie U-Boot to libpayload. With regard
>> to VGA and keyboard support, how can we make them usable in U-Boot (i.e.
>> so the command prompt is displayed on a monitor and the user can use the
>> keyboard to enter commands?)
>
> Does uboot provide a USB stack on PCs (e.g. UHCI/OHCI/EHCI/XHCI)... those
> might be interesting parts of libpayload in the longer run.

There are USB drivers in U-Boot - It's all a question of hardware support

> For now, just adding a simple keyboard and vga driver should be fairly
> simple. It would be nice to also have an option for running on a linear
> framebuffer (with the framebuffer specs read from the coreboot table)

Regards,

Graeme



From svens at stackframe.org  Tue May 10 08:59:38 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 10 May 2011 08:59:38 +0200
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <BANLkTiny2a3FwqrpY9-JAbqLrTg=+Ejapg@mail.gmail.com> (Josh
	Stump's message of "Mon\, 9 May 2011 13\:57\:26 -0700")
References: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>
	<20110509192206.31945.qmail@stuge.se>
	<BANLkTiny2a3FwqrpY9-JAbqLrTg=+Ejapg@mail.gmail.com>
Message-ID: <878vufdorp.fsf@begreifnix.stackframe.org>

Josh Stump <josh+coreboot at pcinw.net> writes:

> Thank you kindly. ?I have now compiled the BIOS. ?Next challenge is
> how to get flashrom to flash it. ?The wiki shows flashrom support.
> ?I have downloaded the latest svn version and flashrom does not detect
> my system. ?flashrom -L does not list Lenovo T60, any
> suggestions or shall I get on the flashrom mailing list to ask? ?Thank
> you again.

The Vendor BIOS prevents flashing with flashrom. (In fact it doesn't
allow the SPI opcodes necessary to detect, erase and write the Flash).
So you have to flash it either with an external programmer, or reverse
engineer how the Phoenix BIOS protection can be circumvented.

Sven.



From peter at stuge.se  Tue May 10 09:02:18 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 10 May 2011 09:02:18 +0200
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <878vufdorp.fsf@begreifnix.stackframe.org>
References: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>
	<20110509192206.31945.qmail@stuge.se>
	<BANLkTiny2a3FwqrpY9-JAbqLrTg=+Ejapg@mail.gmail.com>
	<878vufdorp.fsf@begreifnix.stackframe.org>
Message-ID: <20110510070218.9076.qmail@stuge.se>

Sven Schnelle wrote:
> Josh Stump <josh+coreboot at pcinw.net> writes:
> 
> > Thank you kindly. ?I have now compiled the BIOS. ?Next challenge is
> > how to get flashrom to flash it. ?The wiki shows flashrom support.

Which wiki and page please?


> The Vendor BIOS prevents flashing with flashrom. (In fact it doesn't
> allow the SPI opcodes necessary to detect, erase and write the Flash).
> So you have to flash it either with an external programmer, or reverse
> engineer how the Phoenix BIOS protection can be circumvented.

Yes. The wiki is wrong I'm afraid, the ThinkPads aren't currently
supported by flashrom. (Now that's ironic! coreboot support before
flashrom! :)


//Peter



From knuku at gap.upv.es  Tue May 10 11:01:19 2011
From: knuku at gap.upv.es (Knut Kujat)
Date: Tue, 10 May 2011 11:01:19 +0200
Subject: [coreboot] news about coreboot & llano Fudzilla.com
Message-ID: <4DC8FEDF.1080201@gap.upv.es>

Hi everyone,

FYI: 
http://www.fudzilla.com/processors/item/22677-amd-to-use-coreboot-in-llano-other-upcoming-parts

Bye,
Knut Kujat.



From r.marek at assembler.cz  Tue May 10 11:45:49 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 10 May 2011 11:45:49 +0200
Subject: [coreboot] news about coreboot & llano Fudzilla.com
In-Reply-To: <4DC8FEDF.1080201@gap.upv.es>
References: <4DC8FEDF.1080201@gap.upv.es>
Message-ID: <4DC9094D.2030809@assembler.cz>

Yes and LWN and slashdot:

http://hardware.slashdot.org/story/11/05/09/1115235/AMD-To-Support-Coreboot-On-All-Upcoming-Processors

http://lwn.net/Articles/442042/

Rudolf



From graeme.russ at gmail.com  Tue May 10 16:33:56 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Wed, 11 May 2011 00:33:56 +1000
Subject: [coreboot] U-Boot-x86 / coreboot Integration
Message-ID: <4DC94CD4.2050904@gmail.com>

Hi All,

I figured it might be best to start a new, clean thread dealing with the
technical design aspects of bootstrapping U-Boot from coreboot.

I am extremely excited about this as the x86 U-Boot maintainer, but even
more so by the idea of two very mature and respected FLOSS projects
potentially becoming greater than the sum of their parts :)

OK, enough with the warm and fuzzies. Lets look first at a few facts (as I
understand them - please feel free to correct me):
 - U-Boot is a bootloader for embedded systems - A market segment
   dominated by ARM, PPC et al - i.e. NOT x86
 - coreboot is a 'BIOS' replacement for mainstream PC's - A market segment
   dominated by x86
 - Both are principally designed as 'primary bootloaders' - i.e. intended
   to be executed at CPU reset and responsible for low level hardware
   initialisation
 - U-Boot has no support for modern x86 PC hardware (North and South
   bridges, Dual-Core x86 CPUs, microcode, ACPI, APM etc)
 - coreboot is 'dumb' (No command line, scripting etc) As I understand it
   you build a 'payload' into the coreboot image which coreboot simply runs
   after it has performed necessary low-level hardware initialisation
 - U-Boot is 'smart' (command line, scripting, network support, environment
   variables etc) but currently lacks the ability to perform low level
   hardware initialisation of x86 PC hardware
 - coreboot launches a 'payload' which is (typically) an ELF executable
   linked to 'libpayload'. libpayload provides access to some primitive
   libc functionality, I/O and coreboot generated data structures
 - Our primary target OS is GNU/Linux (of course!)
 - The majority of U-Boot and coreboot is licensed under the 'GPLv2 or (at
   your option) any later version'

So coreboot and U-Boot are a good complement to each other so bringing
U-Boot to x86 PC mainboards via coreboot looks like a good idea - Now the
politics ;)
 - The U-Boot source 'must' be self contained - No external libraries.
   Incorporating license compatible source is OK
 - coreboot payloads should be in ELF (linked to libpayload)
 - There should be minimal intrusion into the core U-Boot build scripts
   (Makefiles, mk.configs etc) - I would assume the same applies to
   coreboot build files as well. Hacking the U-Boot x86 specific build
   files should be fine
 - Everything should 'just work' with a recent GNU toolchain (gcc,
   binutils etc)
 - U-Boot relocates to 'Top of RAM' - This is a fundamental architectural
   design and not x86 specific. This feature should be retained for
   consistency with other U-Boot arches
 - Do we care about legacy BIOS support (SeaBIOS) for now (I think not)?

So, a few questions
 - How much of libpayload would we need to bring into U-Boot to provide
   bare minimal payload delivery? U-Boot already contains it's own minimal
   libc routines.
 - How do we get VGA and USB keyboard support working? Do other U-Boot
   boards implement console on anything other than serial?
 - Can we add relocation support to the coreboot ELF loader?
 - Does coreboot relocate into RAM? If so, what is the target address? What
   guarantee is there that the target address is valid?
 - Could coreboot benefit from U-Boot's 'load to top of RAM' philosophy?
 - Is it worth playing around with segment registers to 'relocate' U-Boot
 - What hardware should be initialised in coreboot and what should be
   initialised in U-Boot? (political question ;)
 - What about Chipset Microcode (CMC)
 - What about System Management Mode (SMM)

I think a good start would be to create a new U-Boot target which includes
a stripped down libpayload in the U-Boot source. This target can exclude
most of the assembler startup code (resetvec.S, start16.S, start.S). I
assume the coreboot ELF loader (or libpayload) takes care of setting up the
C environment (stack etc).

We can start with U-Boot linked to a fixed location in RAM and skip
relocations then work on either extending coreboot to perform relocation
fixups or have U-Boot perform the fixups based on RAM information read from
cbtable

>From there, we can start to add device support (USB, video, PCI, IDE/SATA etc)

It's getting late, so I'll stop now. Hopefully this gives a good design
platform to start from

Regards,

Graeme

P.S. Please keep both U-Boot and coreboot mailing lists Cc'd - Note: If you
are not on the coreboot ml, you emails will get bounced to a moderator :(




From harald.gutmann at gmx.net  Tue May 10 16:36:44 2011
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Tue, 10 May 2011 16:36:44 +0200
Subject: [coreboot] Hackaton in Prague 2011
In-Reply-To: <4DC77D9C.8010804@assembler.cz>
References: <4DC77D9C.8010804@assembler.cz>
Message-ID: <201105101636.45089.harald.gutmann@gmx.net>

On Monday 09 May 2011 07:37:32 Rudolf Marek wrote:
> Hi all,
> 
> I think it is time to make a reservation for the Hotel/Hostel. Is there
> anyone else besides Peter, Sven and Florentin? Just reminding that it take
> place in Prague on last weekend in May.

Hey, that's a good date as I'd be anyways in Prague. I wouldn't take the time 
to join the hackaton, but maybe just have a visit there.

Is there any detailed information about that event available?

Regards,
Harald


> The Hackaton topics I have in mind:
> 
> * make netconsole work on secondary PCI buses
> * implement a gdb stub for coreboot
> * fix the u-boot patches/submit them
> * ... (need to get info from the attending guys)
> 
> Thanks,
> Rudolf



From josh+coreboot at pcinw.net  Tue May 10 17:48:52 2011
From: josh+coreboot at pcinw.net (Josh Stump)
Date: Tue, 10 May 2011 08:48:52 -0700
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <20110510070218.9076.qmail@stuge.se>
References: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>
	<20110509192206.31945.qmail@stuge.se>
	<BANLkTiny2a3FwqrpY9-JAbqLrTg=+Ejapg@mail.gmail.com>
	<878vufdorp.fsf@begreifnix.stackframe.org>
	<20110510070218.9076.qmail@stuge.se>
Message-ID: <BANLkTi=SLUN089ChOATePW0vtx4HrUxeNQ@mail.gmail.com>

http://www.coreboot.org/Supported_Motherboards
<http://www.coreboot.org/Supported_Motherboards>And I am slightly incorrect
I must admit.  It is the Lenovo T60P that is listed on that page.  Do you
have a good site with information on an external programmer or are they
costly?  Any chances of being able to use a Windows based utility to flash,
I tried with Pheonix WinPhlash but it gave an error....

On Tue, May 10, 2011 at 12:02 AM, Peter Stuge <peter at stuge.se> wrote:

> Sven Schnelle wrote:
> > Josh Stump <josh+coreboot at pcinw.net> writes:
> >
> > > Thank you kindly.  I have now compiled the BIOS.  Next challenge is
> > > how to get flashrom to flash it.  The wiki shows flashrom support.
>
> Which wiki and page please?
>
>
> > The Vendor BIOS prevents flashing with flashrom. (In fact it doesn't
> > allow the SPI opcodes necessary to detect, erase and write the Flash).
> > So you have to flash it either with an external programmer, or reverse
> > engineer how the Phoenix BIOS protection can be circumvented.
>
> Yes. The wiki is wrong I'm afraid, the ThinkPads aren't currently
> supported by flashrom. (Now that's ironic! coreboot support before
> flashrom! :)
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From josh+coreboot at pcinw.net  Tue May 10 18:00:17 2011
From: josh+coreboot at pcinw.net (Josh Stump)
Date: Tue, 10 May 2011 09:00:17 -0700
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <20110510070218.9076.qmail@stuge.se>
References: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>
	<20110509192206.31945.qmail@stuge.se>
	<BANLkTiny2a3FwqrpY9-JAbqLrTg=+Ejapg@mail.gmail.com>
	<878vufdorp.fsf@begreifnix.stackframe.org>
	<20110510070218.9076.qmail@stuge.se>
Message-ID: <BANLkTi=FhOq8EpazB=3uROsqUryw3D9LwQ@mail.gmail.com>

http://www.coreboot.org/Supported_Motherboards
<http://www.coreboot.org/Supported_Motherboards>And I am slightly incorrect
I must admit.  It is the Lenovo T60P that is listed on that page.  Do you
have a good site with information on an external programmer or are they
costly?  Any chances of being able to use a Windows based utility to flash,
I tried with Pheonix WinPhlash but it gave an error....

On Tue, May 10, 2011 at 12:02 AM, Peter Stuge <peter at stuge.se> wrote:

> Sven Schnelle wrote:
> > Josh Stump <josh+coreboot at pcinw.net> writes:
> >
> > > Thank you kindly.  I have now compiled the BIOS.  Next challenge is
> > > how to get flashrom to flash it.  The wiki shows flashrom support.
>
> Which wiki and page please?
>
>
> > The Vendor BIOS prevents flashing with flashrom. (In fact it doesn't
> > allow the SPI opcodes necessary to detect, erase and write the Flash).
> > So you have to flash it either with an external programmer, or reverse
> > engineer how the Phoenix BIOS protection can be circumvented.
>
> Yes. The wiki is wrong I'm afraid, the ThinkPads aren't currently
> supported by flashrom. (Now that's ironic! coreboot support before
> flashrom! :)
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From josh+coreboot at pcinw.net  Tue May 10 18:00:45 2011
From: josh+coreboot at pcinw.net (Josh Stump)
Date: Tue, 10 May 2011 09:00:45 -0700
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <20110510070218.9076.qmail@stuge.se>
References: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>
	<20110509192206.31945.qmail@stuge.se>
	<BANLkTiny2a3FwqrpY9-JAbqLrTg=+Ejapg@mail.gmail.com>
	<878vufdorp.fsf@begreifnix.stackframe.org>
	<20110510070218.9076.qmail@stuge.se>
Message-ID: <BANLkTik7ASadWUCT6RNv6-B6zZ8u6zwpGQ@mail.gmail.com>

http://www.coreboot.org/Supported_Motherboards
<http://www.coreboot.org/Supported_Motherboards>And I am slightly incorrect
I must admit.  It is the Lenovo T60P that is listed on that page.  Do you
have a good site with information on an external programmer or are they
costly?  Any chances of being able to use a Windows based utility to flash,
I tried with Pheonix WinPhlash but it gave an error....

On Tue, May 10, 2011 at 12:02 AM, Peter Stuge <peter at stuge.se> wrote:

> Sven Schnelle wrote:
> > Josh Stump <josh+coreboot at pcinw.net> writes:
> >
> > > Thank you kindly.  I have now compiled the BIOS.  Next challenge is
> > > how to get flashrom to flash it.  The wiki shows flashrom support.
>
> Which wiki and page please?
>
>
> > The Vendor BIOS prevents flashing with flashrom. (In fact it doesn't
> > allow the SPI opcodes necessary to detect, erase and write the Flash).
> > So you have to flash it either with an external programmer, or reverse
> > engineer how the Phoenix BIOS protection can be circumvented.
>
> Yes. The wiki is wrong I'm afraid, the ThinkPads aren't currently
> supported by flashrom. (Now that's ironic! coreboot support before
> flashrom! :)
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From peter at stuge.se  Tue May 10 18:08:50 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 10 May 2011 18:08:50 +0200
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <4DC94CD4.2050904@gmail.com>
References: <4DC94CD4.2050904@gmail.com>
Message-ID: <20110510160850.2499.qmail@stuge.se>

Graeme Russ wrote:
> I am extremely excited about this as the x86 U-Boot maintainer, but
> even more so by the idea of two very mature and respected FLOSS
> projects potentially becoming greater than the sum of their parts :)

Yes good fun!


> OK, enough with the warm and fuzzies. Lets look first at a few facts
> (as I understand them - please feel free to correct me):
>  - U-Boot is a bootloader for embedded systems - A market segment
>    dominated by ARM, PPC et al - i.e. NOT x86
>  - coreboot is a 'BIOS' replacement for mainstream PC's - A market segment
>    dominated by x86
>  - Both are principally designed as 'primary bootloaders' - i.e. intended
>    to be executed at CPU reset and responsible for low level hardware
>    initialisation
>  - U-Boot has no support for modern x86 PC hardware (North and South
>    bridges, Dual-Core x86 CPUs, microcode, ACPI, APM etc)
>  - coreboot is 'dumb' (No command line, scripting etc) As I understand it
>    you build a 'payload' into the coreboot image which coreboot simply runs
>    after it has performed necessary low-level hardware initialisation
>  - U-Boot is 'smart' (command line, scripting, network support, environment
>    variables etc) but currently lacks the ability to perform low level
>    hardware initialisation of x86 PC hardware
>  - coreboot launches a 'payload' which is (typically) an ELF executable
>    linked to 'libpayload'. libpayload provides access to some primitive
>    libc functionality, I/O and coreboot generated data structures
>  - Our primary target OS is GNU/Linux (of course!)
>  - The majority of U-Boot and coreboot is licensed under the 'GPLv2 or (at
>    your option) any later version'

coreboot is GPLv2 only, otherwise the facts are accurate.


> Now the politics ;)
>  - The U-Boot source 'must' be self contained - No external libraries.
>    Incorporating license compatible source is OK

Well ok.. (why though?)


>  - coreboot payloads should be in ELF (linked to libpayload)

They do not neccessarily have to link to libpayload, but if they
don't they have to replicate some of what libpayload does. That code
duplication is pretty silly, so most payloads do use libpayload.


>  - There should be minimal intrusion into the core U-Boot build scripts
>    (Makefiles, mk.configs etc) - I would assume the same applies to
>    coreboot build files as well. Hacking the U-Boot x86 specific build
>    files should be fine

coreboot uses Kconfig for build time configuration and I think it
would be no problem (maybe even desirable) to add a few special
commands in order to grab a U-Boot from git, build it, and include it
as payload in the output coreboot.rom. This is done for SeaBIOS
already.


>  - Everything should 'just work' with a recent GNU toolchain (gcc,
>    binutils etc)

coreboot has significant experiences from distribution toolchains
being patched to the point where they are unable to correctly build
coreboot itself and/or payloads. If the distribution toolchain works
for you that's good, but most of the big name distributions have
messed up their toolchains. The coreboot source includes a script to
build known good versions of the toolchain, and the coreboot build
system will automatically pick up such a toolchain if it is found
during build.


>  - U-Boot relocates to 'Top of RAM' - This is a fundamental architectural
>    design and not x86 specific. This feature should be retained for
>    consistency with other U-Boot arches

IMO this might be a little misguided. Retaining behavior, especially
across architecture, shouldn't be an end in itself. If U-Boot was the
primary bootloader in this situation it would matter less. In the
context of coreboot however U-Boot would be much easier to integrate
with if this policy was not enforced. Maybe U-Boot wants to stay
resident however, then there's not much choice except top of memory.


>  - Do we care about legacy BIOS support (SeaBIOS) for now (I think
>    not)?

IMO it is not relevant to the integration of coreboot and U-Boot. If
a BIOS is needed by U-Boot itself or whatever it loads, then SeaBIOS
must be used as payload for coreboot, and SeaBIOS will then start
U-Boot after setting up the BIOS environment.


> So, a few questions
>  - How much of libpayload would we need to bring into U-Boot to provide
>    bare minimal payload delivery? U-Boot already contains it's own
>    minimal libc routines.

Not much at all. You basically just have to look up the coreboot
table.


>  - How do we get VGA and USB keyboard support working?

Write VGA and USB drivers. Or use the ones that are available in
libpayload. Estimate 5-6 months of development effort to write from
scratch. But you could also copy it all from libpayload of course.

One thing to keep in mind here is that VGA will only be available if
coreboot or SeaBIOS has set it up. coreboot only knows how to do this
for two or three graphics chipsets. SeaBIOS can initialize any VGA
option ROM, but then you need SeaBIOS in the loop.

Option ROMs are ageold technology and stupid, but they are still
firmly entrenched in PC hardware. A BIOS was always there so everyone
assumes it will always stay there, not very many question if
something better could be done.


>    Do other U-Boot boards implement console on anything other than
>    serial?

U-Boot? Can't say.


>  - Can we add relocation support to the coreboot ELF loader?

ELF payloads are parsed at build time, simplified into a
coreboot-internal format. Run time relocation is not so attractive.


>  - Does coreboot relocate into RAM? If so, what is the target address?

Determined at build time.

>    What guarantee is there that the target address is valid?

It's low enough in RAM.


>  - Could coreboot benefit from U-Boot's 'load to top of RAM' philosophy?

I doubt it, but maybe?


>  - Is it worth playing around with segment registers to 'relocate' U-Boot

Maybe?


>  - What hardware should be initialised in coreboot and what should be
>    initialised in U-Boot? (political question ;)

Actually this is well defined. coreboot in general does not touch
peripherals with VGA being the exception.


>  - What about Chipset Microcode (CMC)
>  - What about System Management Mode (SMM)

coreboot does provide the bare minimum for chipsets which need it,
but preference is to not go beyond the busses.


> We can start with U-Boot linked to a fixed location in RAM and skip
> relocations then work on either extending coreboot to perform
> relocation fixups or have U-Boot perform the fixups based on RAM
> information read from cbtable

The latter sounds better to me. :)


> From there, we can start to add device support (USB, video, PCI,
> IDE/SATA etc)

libpayload covers most of these. :) Take a look at a couple different
libpayload users. FILO would probably be the closest to what U-Boot
does.


//Peter



From peter at stuge.se  Tue May 10 18:52:02 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 10 May 2011 18:52:02 +0200
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <BANLkTi=SLUN089ChOATePW0vtx4HrUxeNQ@mail.gmail.com>
References: <BANLkTikByBu+b4DESwk388bSdFUknzM5Sw@mail.gmail.com>
	<20110509192206.31945.qmail@stuge.se>
	<BANLkTiny2a3FwqrpY9-JAbqLrTg=+Ejapg@mail.gmail.com>
	<878vufdorp.fsf@begreifnix.stackframe.org>
	<20110510070218.9076.qmail@stuge.se>
	<BANLkTi=SLUN089ChOATePW0vtx4HrUxeNQ@mail.gmail.com>
Message-ID: <20110510165202.10689.qmail@stuge.se>

Josh Stump wrote:
> http://www.coreboot.org/Supported_Motherboards

Ah, ok. This wiki page is correct. coreboot is separate from
flashrom, so being supported by one doesn't automatically mean being
supported by the other. Laptops are difficult for both projects.


> And I am slightly incorrect I must admit.  It is the Lenovo T60P
> that is listed on that page.

T60 T60p are similar enough.


> Do you have a good site with information on an external programmer
> or are they costly?  Any chances of being able to use a Windows
> based utility to flash, I tried with Pheonix WinPhlash but it gave
> an error....

I think it gets upset because you want to flash coreboot. :)

Here are some instructions for a hardware that will work with
flashrom today: http://flashrom.org/FT2232SPI_Programmer
But you need to build a little yourself. Only very little.

I have an alternative approach in mind with a microcontroller board
but some firmware still needs to be written. :)


//Peter



From vikram186 at gmail.com  Tue May 10 19:35:53 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Tue, 10 May 2011 23:05:53 +0530
Subject: [coreboot] [PATCH] Replace the values of APIC timer init with
 macros
In-Reply-To: <4DC597B0.4050204@gmail.com>
References: <4DC597B0.4050204@gmail.com>
Message-ID: <1305048953.4263.5.camel@ubuntu.ubuntu-domain>

On Sun, 2011-05-08 at 00:34 +0530, Vikram Narayanan wrote:
> This replaces the fixed shift values in the apic timer init with macros.
> 
> Signed-off by: Vikram Narayanan <vikram186 at gmail.com>
> ---
> --- a/src/cpu/x86/lapic/apic_timer.c	Sun May  8 00:18:12 2011
> +++ b/src/cpu/x86/lapic/apic_timer.c	Sun May  8 00:08:54 2011
> @@ -36,7 +36,7 @@
>  	msr_t fsb_clock_sts;
>  
>  	/* Set the apic timer to no interrupts and periodic mode */
> -	lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 << 0));
> +	lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED));
>  
>  	/* Set the divider to 1, no divider */
>  	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);

Think this is quite trivial. Can someone comment on this so that this
will be merged in the next commit?

-
Thanks,
Vikram





From seppk at arcor.de  Tue May 10 19:35:03 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Tue, 10 May 2011 19:35:03 +0200
Subject: [coreboot] support for siemens sitemp mainboard
Message-ID: <4DC97747.7070107@arcor.de>

I've compiled support for the Siemens 'sitemp' Mainboard. The board is 
similar to the AMD dbm690t.
I adapt the code from the dbm690t according to customer requirement 
specification.

I've been testing Linux as well as Windows XP booting on this board.

Added  2 patches:
0001-mainboard-siemens.patch
0002-mainboard_kconfig.patch

Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
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From scott at notabs.org  Tue May 10 20:13:27 2011
From: scott at notabs.org (Scott Duplichan)
Date: Tue, 10 May 2011 13:13:27 -0500
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <BANLkTi=SLUN089ChOATePW0vtx4HrUxeNQ@mail.gmail.com>
Message-ID: <mailman.4220.1355071914.16123.coreboot@coreboot.org>

Josh Stump wrote:

] Any chances of being able to use a Windows based utility to flash,
] I tried with Pheonix WinPhlash but it gave an error....

The advanced mode of WinPhlash might help. You could uncheck "Verify BIOS
part number"
and "Verify BIOS checksum". The help file shows how to enable advanced mode
by adding 
Advanced=1 to the [UI] section of phlash.ini. If that doesn't work, you
could try the 16-bit
version (phlash16.exe).

Even if this lets you flash coreboot using software, you still need a way to
recover in
case you end up in a non-booting state.

Thanks,
Scott








From wd at denx.de  Tue May 10 20:15:13 2011
From: wd at denx.de (Wolfgang Denk)
Date: Tue, 10 May 2011 20:15:13 +0200
Subject: [coreboot] [U-Boot]  U-Boot-x86 / coreboot Integration
In-Reply-To: <20110510160850.2499.qmail@stuge.se>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
Message-ID: <20110510181513.5F1CCD6BE23@gemini.denx.de>

Dear Peter Stuge,

In message <20110510160850.2499.qmail at stuge.se> you wrote:
>
> >  - U-Boot relocates to 'Top of RAM' - This is a fundamental architectural
> >    design and not x86 specific. This feature should be retained for
> >    consistency with other U-Boot arches
> 
> IMO this might be a little misguided. Retaining behavior, especially
> across architecture, shouldn't be an end in itself. If U-Boot was the
> primary bootloader in this situation it would matter less. In the
> context of coreboot however U-Boot would be much easier to integrate
> with if this policy was not enforced. Maybe U-Boot wants to stay
> resident however, then there's not much choice except top of memory.

It's not about staying resident, but for a number of other features
that are considered valuable, like:
- auto-adapting to the available RAM size so a maximum amount of
  contiguous RAM is available to load OS and/or file system images,
  etc.
- providing "persistent RAM" which keeps it's content even through a
  reset/crash/warmboot; frequently used for in-memory file systems
  (pramfs for example)
- sharing a log buffewr between U-Boot and Linux, so Linux can pick up
  U-Boot's POST codes using standard syslog tools, or U-Boot can read
  the Linux log buffer after a system crash - or Linux can pick up the
  last entries of the previous Linux kernel's messages after a
  crash/reboot
- sharing video RAM, so we can load a splash screen in U-Boot which
  can be assedon without any flicker to Linux, until application code
  starts drawing it's own graphics.
etc.

All these are based on the idea to reserve memory chunks from the top
of physical RAM.  And U-Boot is sitting just below all these reserved
chunks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
God is real, unless declared integer.



From wd at denx.de  Tue May 10 20:03:10 2011
From: wd at denx.de (Wolfgang Denk)
Date: Tue, 10 May 2011 20:03:10 +0200
Subject: [coreboot] [U-Boot] U-Boot-x86 / coreboot Integration
In-Reply-To: <4DC94CD4.2050904@gmail.com>
References: <4DC94CD4.2050904@gmail.com>
Message-ID: <20110510180310.8F8C8D6BE23@gemini.denx.de>

Dear Graeme Russ,

In message <4DC94CD4.2050904 at gmail.com> you wrote:
> 
> So coreboot and U-Boot are a good complement to each other so bringing
> U-Boot to x86 PC mainboards via coreboot looks like a good idea - Now the
> politics ;)
>  - The U-Boot source 'must' be self contained - No external libraries.
>    Incorporating license compatible source is OK

The same is probably true for coreboot.

>  - coreboot payloads should be in ELF (linked to libpayload)

Is this really necessary, assuming we have a self-contained payload
that does not request any services from the tool that was used to
start it?

>  - How much of libpayload would we need to bring into U-Boot to provide
>    bare minimal payload delivery? U-Boot already contains it's own minimal
>    libc routines.

Right.  See above - eventually such linking is not really necessary if
the U-Boot ELF image is really self-contained.

>  - How do we get VGA and USB keyboard support working? Do other U-Boot
>    boards implement console on anything other than serial?

Yes, we do support output on LCD and other video adapters, and we
support input from USB keyboard (not to mentione netconsole, or
netconsole over ethernet  over USB and similar fancy stuff).

>  - Can we add relocation support to the coreboot ELF loader?

Do we have to?

>  - Does coreboot relocate into RAM? If so, what is the target address? What
>    guarantee is there that the target address is valid?

Do we have to care?  I would expect that we consider both coreboot and
U-Boot as isolated entities, each performing it's own task. Coreboot
will initialize the RAM and load and start U-Boot, similar to what a
first stage loader does on systems that boot from NAND.  Once U-Bootis
running, it does so completely on its own.

>  - Could coreboot benefit from U-Boot's 'load to top of RAM' philosophy?

Is there any need for this?  Don't make things more complex than
needed.

>  - Is it worth playing around with segment registers to 'relocate' U-Boot

That's a U-Boot question, right?  Let's solve this independently.

>  - What hardware should be initialised in coreboot and what should be
>    initialised in U-Boot? (political question ;)

No, that's a very practical; question. Coreboot should do as many of
the x86 specific stuff as it can, and as it already does to load and
start other payloads.  And probably not more, at least not for now.

I think the best way to make this undertaking a success is to make it
as unintrusive to both involved projects as possible.

> I think a good start would be to create a new U-Boot target which includes
> a stripped down libpayload in the U-Boot source. This target can exclude

Why would we need that?  I can understand that this may make initial
porting and debugging easier ("early console output" etc.), but we
should try to do without this.

> We can start with U-Boot linked to a fixed location in RAM and skip
> relocations then work on either extending coreboot to perform relocation
> fixups or have U-Boot perform the fixups based on RAM information read from
> cbtable

I strongly recommend not to request changes to coreboot, and not to
deviate from standard U-Boot methods.

We are not re-inventing the wheel here.  We have many similar
situations where some ROM boot loader or xload or nand_spl code or
onenand_ipl code is loading an U-Boot image into a halfway initialized
system, and U-Boot starts there.  I see no need to make coreboot use a
different method.

> P.S. Please keep both U-Boot and coreboot mailing lists Cc'd - Note: If you
> are not on the coreboot ml, you emails will get bounced to a moderator :(

I hope he is tolerant enough...

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"...all the  good  computer  designs  are  bootlegged;  the  formally
planned  products,  if  they  are built at all, are dogs!" - David E.
Lundstrom, "A Few Good Men From Univac", MIT Press, 1987



From vikram186 at gmail.com  Tue May 10 20:10:59 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Tue, 10 May 2011 23:40:59 +0530
Subject: [coreboot]  Alternate for serial port debug messages
Message-ID: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>

Hi, 

I am using a DELL laptop. The superio used is 
"Found Nuvoton WPCE775x / NPCE781x (id=0x03, rev=0x06) at 0x4e".

Now the thing is there are no serial ports exposed outside in my laptop.
Is there any other way out to see the debug messages of coreboot.(If at
all coreboot supports my motherboard, or if I am planning to try if its
not there)

Thanks,
Vikram





From patrick at georgi-clan.de  Tue May 10 21:23:25 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 10 May 2011 21:23:25 +0200
Subject: [coreboot] [PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes for
 read_option() use
Message-ID: <4DC990AD.8030702@georgi-clan.de>

[let's try again]
Hi,

as a first step to the CMOS infrastructure project (as detailed in the
wiki), this patch changes read_option() by wrapping it in a macro,
simplifying its use from
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)


Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
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From patrick at georgi-clan.de  Tue May 10 21:24:47 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 10 May 2011 21:24:47 +0200
Subject: [coreboot] [PATCHes] Adopt coreboot build system for libpayload
Message-ID: <4DC990FF.4010305@georgi-clan.de>

[resend]
Hi,

attached patches change libpayload to use the coreboot build system copied
into libpayload. Among the advantages is that it simplifies building a more
standard set of libraries (eg. libcurses, libc, libpci) which simplifies
porting code to libpayload a bit (as Makefiles can be used with fewer
changes).

For compatibility purposes, the build system still generates a
libpayload.a, which is simply a superset over all other libraries.

The first patch changes the build system to the new style.
The second patch fixes up the tree so it compiles with the tighter
warning/error regime imposed by the build system.
As a bonus, the third patch adds openbsd's strlcpy (in addition to strlcat
which we already have).

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
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From corey.osgood at gmail.com  Tue May 10 21:25:27 2011
From: corey.osgood at gmail.com (Corey Osgood)
Date: Tue, 10 May 2011 15:25:27 -0400
Subject: [coreboot] Alternate for serial port debug messages
In-Reply-To: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>
References: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>
Message-ID: <BANLkTincQm_=e-ZY1uWAUh2eXDcEQi3xbA@mail.gmail.com>

On Tue, May 10, 2011 at 2:10 PM, Vikram Narayanan <vikram186 at gmail.com> wrote:
> Hi,
>
> I am using a DELL laptop. The superio used is
> "Found Nuvoton WPCE775x / NPCE781x (id=0x03, rev=0x06) at 0x4e".
>
> Now the thing is there are no serial ports exposed outside in my laptop.
> Is there any other way out to see the debug messages of coreboot.(If at
> all coreboot supports my motherboard, or if I am planning to try if its
> not there)

Check lspci -v, you probably have a USB port that has debug port
capability. You'll then need a USB debug cable.

-Corey



From josh+coreboot at pcinw.net  Tue May 10 21:58:18 2011
From: josh+coreboot at pcinw.net (Josh Stump)
Date: Tue, 10 May 2011 12:58:18 -0700
Subject: [coreboot] Lenovo T60 coreboot build error
In-Reply-To: <4dc98079.114cdf0a.03eb.3917SMTPIN_ADDED@mx.google.com>
References: <BANLkTi=SLUN089ChOATePW0vtx4HrUxeNQ@mail.gmail.com>
	<4dc98079.114cdf0a.03eb.3917SMTPIN_ADDED@mx.google.com>
Message-ID: <BANLkTinVoNmAzSkHTkkN7zoHmshKjva2FQ@mail.gmail.com>

I have attempted using Advanced Mode, I get the same error when I click
"Advanced Settings"...
Corrupted interface descriptors in the new BIOS file.  Part Table Signature
not found in the Interface.  Error code: -161
I will consider trying phlash16...

On Tue, May 10, 2011 at 11:13 AM, Scott Duplichan <scott at notabs.org> wrote:

> Josh Stump wrote:
>
> ] Any chances of being able to use a Windows based utility to flash,
> ] I tried with Pheonix WinPhlash but it gave an error....
>
> The advanced mode of WinPhlash might help. You could uncheck "Verify BIOS
> part number"
> and "Verify BIOS checksum". The help file shows how to enable advanced mode
> by adding
> Advanced=1 to the [UI] section of phlash.ini. If that doesn't work, you
> could try the 16-bit
> version (phlash16.exe).
>
> Even if this lets you flash coreboot using software, you still need a way
> to
> recover in
> case you end up in a non-booting state.
>
> Thanks,
> Scott
>
>
>
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From stefan.reinauer at coreboot.org  Tue May 10 22:07:14 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 10 May 2011 22:07:14 +0200
Subject: [coreboot] [PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes
 for read_option() use
In-Reply-To: <4DC990AD.8030702@georgi-clan.de>
References: <4DC990AD.8030702@georgi-clan.de>
Message-ID: <20110510200714.GA29286@coreboot.org>

* Patrick Georgi <patrick at georgi-clan.de> [110510 21:23]:
> [let's try again]
> Hi,
> 
> as a first step to the CMOS infrastructure project (as detailed in the
> wiki), this patch changes read_option() by wrapping it in a macro,
> simplifying its use from
> read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
> to
> read_option(foo, somedefault)
> 
> 
> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

> [PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes for read_option() use
> 
> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


> ---
>  src/cpu/amd/dualcore/dualcore.c           |    2 +-
>  src/cpu/amd/model_10xxx/init_cpus.c       |    2 +-
>  src/cpu/amd/model_fxx/init_cpus.c         |    2 +-
>  src/cpu/amd/quadcore/quadcore.c           |    2 +-
>  src/include/pc80/mc146818rtc.h            |    5 +++--
>  src/lib/uart8250.c                        |    2 +-
>  src/mainboard/getac/p470/romstage.c       |    2 +-
>  src/mainboard/kontron/986lcd-m/romstage.c |    8 ++++----
>  src/mainboard/roda/rk886ex/romstage.c     |    2 +-
>  src/northbridge/amd/amdk8/coherent_ht.c   |    2 +-
>  src/northbridge/amd/amdk8/raminit.c       |    6 +++---
>  src/northbridge/amd/amdk8/raminit_f.c     |    6 +++---
>  src/northbridge/intel/e7520/raminit.c     |    2 +-
>  src/northbridge/intel/e7525/raminit.c     |    2 +-
>  src/pc80/mc146818rtc_early.c              |    2 +-
>  15 files changed, 24 insertions(+), 23 deletions(-)
> 


Wow are those the only occurences of readoption in romstage code?

Should we document that somewhere? 


> diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c
> index 5206b07..9c2583f 100644
> --- a/src/cpu/amd/dualcore/dualcore.c
> +++ b/src/cpu/amd/dualcore/dualcore.c
> @@ -49,7 +49,7 @@ static inline void start_other_cores(void)
>  	unsigned nodes;
>  	unsigned nodeid;
>  
> -	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0))  {
> +	if (read_option(multi_core, 0))  {
>  		return; // disable multi_core
>  	}
>  
> diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
> index a256f9c..e0538af 100644
> --- a/src/cpu/amd/model_10xxx/init_cpus.c
> +++ b/src/cpu/amd/model_10xxx/init_cpus.c
> @@ -72,7 +72,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
>  	nodes = get_nodes();
>  
>  	if (!CONFIG_LOGICAL_CPUS ||
> -	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 means multi core
> +	    read_option(multi_core, 0) != 0) {	// 0 means multi core
>  		disable_siblings = 1;
>  	} else {
>  		disable_siblings = 0;
> diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
> index 570cb4e..0036277 100644
> --- a/src/cpu/amd/model_fxx/init_cpus.c
> +++ b/src/cpu/amd/model_fxx/init_cpus.c
> @@ -25,7 +25,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
>  	nodes = get_nodes();
>  
>  	if (!CONFIG_LOGICAL_CPUS ||
> -	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 means multi core
> +	    read_option(multi_core, 0) != 0) {	// 0 means multi core
>  		disable_siblings = 1;
>  	} else {
>  		disable_siblings = 0;
> diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
> index e7d9c7b..3bc97a3 100644
> --- a/src/cpu/amd/quadcore/quadcore.c
> +++ b/src/cpu/amd/quadcore/quadcore.c
> @@ -82,7 +82,7 @@ static void start_other_cores(void)
>  	u32 nodeid;
>  
>  	// disable multi_core
> -	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0)  {
> +	if (read_option(multi_core, 0) != 0)  {
>  		printk(BIOS_DEBUG, "Skip additional core init\n");
>  		return;
>  	}
> diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
> index 032e385..7be552d 100644
> --- a/src/include/pc80/mc146818rtc.h
> +++ b/src/include/pc80/mc146818rtc.h
> @@ -110,15 +110,16 @@ static inline void cmos_write(unsigned char val, unsigned char addr)
>  void rtc_init(int invalid);
>  #if CONFIG_USE_OPTION_TABLE
>  int get_option(void *dest, const char *name);
> -unsigned read_option(unsigned start, unsigned size, unsigned def);
> +unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def);
>  #else
>  static inline int get_option(void *dest __attribute__((unused)),
>  	const char *name __attribute__((unused))) { return -2; }
> -static inline unsigned read_option(unsigned start, unsigned size, unsigned def)
> +static inline unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
>  	{ return def; }
>  #endif
>  #else
>  #include <pc80/mc146818rtc_early.c>
>  #endif
> +#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))
>  
>  #endif /*  PC80_MC146818RTC_H */
> diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
> index 49dc591..64e8854 100644
> --- a/src/lib/uart8250.c
> +++ b/src/lib/uart8250.c
> @@ -99,7 +99,7 @@ void uart_init(void)
>  	static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 };
>  	unsigned b_index = 0;
>  #if defined(__PRE_RAM__)
> -	b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
> +	b_index = read_option(baud_rate, 0);
>  	b_index &= 7;
>  	div = divisor[b_index];
>  #else
> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
> index 582a7bd..0298404 100644
> --- a/src/mainboard/getac/p470/romstage.c
> +++ b/src/mainboard/getac/p470/romstage.c
> @@ -83,7 +83,7 @@ void setup_ich7_gpios(void)
>  static void ich7_enable_lpc(void)
>  {
>  	int lpt_en = 0;
> -	if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
> +	if (read_option(lpt, 0) != 0) {
>  	       lpt_en = 1<<2; // enable LPT
>  	}
>  	// Enable Serial IRQ
> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
> index 357adec..0d6816c 100644
> --- a/src/mainboard/kontron/986lcd-m/romstage.c
> +++ b/src/mainboard/kontron/986lcd-m/romstage.c
> @@ -59,7 +59,7 @@ void setup_ich7_gpios(void)
>  static void ich7_enable_lpc(void)
>  {
>  	int lpt_en = 0;
> -	if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
> +	if (read_option(lpt, 0) != 0) {
>  		lpt_en = 1<<2; // enable LPT
>  	}
>  	// Enable Serial IRQ
> @@ -228,18 +228,18 @@ static void rcba_config(void)
>  	reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
>  	reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
>  
> -	if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) {
> +	if (read_option(ethernet1, 0) != 0) {
>  		printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");
>  		reg32 |= FD_PCIE1;
>  	}
> -	if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) {
> +	if (read_option(ethernet2, 0) != 0) {
>  		printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");
>  		reg32 |= FD_PCIE2;
>  	} else {
>  		if (reg32 & FD_PCIE1)
>  			port_shuffle = 1;
>  	}
> -	if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) {
> +	if (read_option(ethernet3, 0) != 0) {
>  		printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");
>  		reg32 |= FD_PCIE3;
>  	} else {
> diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
> index 158e47c..9b9de25 100644
> --- a/src/mainboard/roda/rk886ex/romstage.c
> +++ b/src/mainboard/roda/rk886ex/romstage.c
> @@ -70,7 +70,7 @@ void setup_ich7_gpios(void)
>  static void ich7_enable_lpc(void)
>  {
>  	int lpt_en = 0;
> -	if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
> +	if (read_option(lpt, 0) != 0) {
>  	       lpt_en = 1<<2; // enable LPT
>  	}
>  	// Enable Serial IRQ
> diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
> index f66e2cf..8b50eed 100644
> --- a/src/northbridge/amd/amdk8/coherent_ht.c
> +++ b/src/northbridge/amd/amdk8/coherent_ht.c
> @@ -1599,7 +1599,7 @@ static void coherent_ht_finalize(unsigned nodes)
>  #if CONFIG_LOGICAL_CPUS==1
>  	unsigned total_cpus;
>  
> -	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */
> +	if (read_option(multi_core, 0) == 0) { /* multi_core */
>  		total_cpus = verify_dualcore(nodes);
>  	}
>  	else {
> diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
> index 2b76cff..3583dc3 100644
> --- a/src/northbridge/amd/amdk8/raminit.c
> +++ b/src/northbridge/amd/amdk8/raminit.c
> @@ -548,7 +548,7 @@ static void hw_enable_ecc(const struct mem_controller *ctrl)
>  	if (nbcap & NBCAP_ECC) {
>  		dcl |= DCL_DimmEccEn;
>  	}
> -	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
> +	if (read_option(ECC_memory, 1) == 0) {
>  		dcl &= ~DCL_DimmEccEn;
>  	}
>  	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
> @@ -1100,7 +1100,7 @@ static void order_dimms(const struct mem_controller *ctrl)
>  {
>  	unsigned long tom_k, base_k;
>  
> -	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
> +	if (read_option(interleave_chip_selects, 1) != 0) {
>  		tom_k = interleave_chip_selects(ctrl);
>  	} else {
>  		printk(BIOS_DEBUG, "Interleaving disabled\n");
> @@ -1530,7 +1530,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
>  
>  	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
>  	bios_cycle_time = min_cycle_times[
> -		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
> +		read_option(max_mem_clock, 0)];
>  	if (bios_cycle_time > min_cycle_time) {
>  		min_cycle_time = bios_cycle_time;
>  	}
> diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
> index 9ccc56b..3e6118d 100644
> --- a/src/northbridge/amd/amdk8/raminit_f.c
> +++ b/src/northbridge/amd/amdk8/raminit_f.c
> @@ -1108,7 +1108,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
>  	 * and if so count them.
>  	 */
>  #if defined(CMOS_VSTART_interleave_chip_selects)
> -	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) == 0)
> +	if (read_option(interleave_chip_selects, 1) == 0)
>  		return 0;
>  #else
>  #if !CONFIG_INTERLEAVE_CHIP_SELECTS
> @@ -1806,7 +1806,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
>  	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
>  	bios_cycle_time = min_cycle_times[
>  #ifdef CMOS_VSTART_max_mem_clock
> -		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)
> +		read_option(max_mem_clock, 0)
>  #else
>  #if defined(CONFIG_MAX_MEM_CLOCK)
>  		CONFIG_MAX_MEM_CLOCK
> @@ -2375,7 +2375,7 @@ static void set_ecc(const struct mem_controller *ctrl,
>  		dcl |= DCL_DimmEccEn;
>  	}
>  #ifdef CMOS_VSTART_ECC_memory
> -	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
> +	if (read_option(ECC_memory, 1) == 0) {
>  		dcl &= ~DCL_DimmEccEn;
>  	}
>  #else // CMOS_VSTART_ECC_memory not defined
> diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
> index 6eed196..7a0661c 100644
> --- a/src/northbridge/intel/e7520/raminit.c
> +++ b/src/northbridge/intel/e7520/raminit.c
> @@ -618,7 +618,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
>  	}
>  	ecc = 2;
>  #if CONFIG_HAVE_OPTION_TABLE
> -	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
> +	if (read_option(ECC_memory, 1) == 0) {
>  		ecc = 0;  /* ECC off in CMOS so disable it */
>  		print_debug("ECC off\n");
>  	} else
> diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
> index aabe8cf..495a142 100644
> --- a/src/northbridge/intel/e7525/raminit.c
> +++ b/src/northbridge/intel/e7525/raminit.c
> @@ -624,7 +624,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
>  	}
>  	ecc = 2;
>  #if CONFIG_HAVE_OPTION_TABLE
> -	if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
> +	if (read_option(ECC_memory, 1) == 0) {
>  		ecc = 0;  /* ECC off in CMOS so disable it */
>  		print_debug("ECC off\n");
>  	} else
> diff --git a/src/pc80/mc146818rtc_early.c b/src/pc80/mc146818rtc_early.c
> index d09d6b9..abddf87 100644
> --- a/src/pc80/mc146818rtc_early.c
> +++ b/src/pc80/mc146818rtc_early.c
> @@ -92,7 +92,7 @@ static inline int do_normal_boot(void)
>  	return (byte & (1<<1));
>  }
>  
> -unsigned read_option(unsigned start, unsigned size, unsigned def)
> +unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
>  {
>  #if CONFIG_USE_OPTION_TABLE
>  	unsigned byte;
> -- 
> 1.7.4.4
> 

> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From stefan.reinauer at coreboot.org  Tue May 10 22:19:24 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 10 May 2011 22:19:24 +0200
Subject: [coreboot] [PATCHes] Adopt coreboot build system for libpayload
In-Reply-To: <4DC990FF.4010305@georgi-clan.de>
References: <4DC990FF.4010305@georgi-clan.de>
Message-ID: <20110510201924.GB29286@coreboot.org>

* Patrick Georgi <patrick at georgi-clan.de> [110510 21:24]:
> -## modification, are permitted provided that the following conditions
> -## are met:
> -## 1. Redistributions of source code must retain the above copyright
> -##    notice, this list of conditions and the following disclaimer.
> -## 2. Redistributions in binary form must reproduce the above copyright
> -##    notice, this list of conditions and the following disclaimer in the
> -##    documentation and/or other materials provided with the distribution.
> -## 3. The name of the author may not be used to endorse or promote products
> -##    derived from this software without specific prior written permission.
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; version 2 of the License.


Hm... can we relicense this under the original license instead? I
dislike going to GPL in an otherwise cleanly BSD license based project.
The coresystems written parts may certainly be relicensed under BSD. Not
sure how much except the header is actually left from AMD and co.

> Reduce warnings/errors in libpayload when using picky compiler options
> 
> diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in
> index 0a9265d..fe53400 100644
> --- a/payloads/libpayload/Config.in
> +++ b/payloads/libpayload/Config.in
> @@ -73,6 +73,10 @@ config TARGET_POWERPC
>  
>  endchoice
>  
> +config MEMMAP_RAM_ONLY
> +	bool "Only consider RAM entries in memory map for further processing"
> +	default n
> +
>  config MULTIBOOT
>  	bool "Multiboot header support"
>  	depends on TARGET_I386


Is this needed for reducing the warnings? What else is it needed for?
> diff --git a/payloads/libpayload/drivers/keyboard.c b/payloads/libpayload/drivers/keyboard.c
> index 2b2ac26..a1860c5 100644
> --- a/payloads/libpayload/drivers/keyboard.c
> +++ b/payloads/libpayload/drivers/keyboard.c
> @@ -37,7 +37,7 @@
>  #define I8042_MODE_XLATE     0x40
>  
>  struct layout_maps {
> -	char *country;
> +	const char *country;
>  	unsigned short map[4][0x57];

can the map be const, too?

> --- a/payloads/libpayload/drivers/usb/usbhid.c
> +++ b/payloads/libpayload/drivers/usb/usbhid.c
> @@ -105,13 +105,13 @@ char *countries[36][2] = {
>  
>  struct layout_maps {
> -	char *country;
> -	short map[4][0x80];
> +	const char *country;
> +	const short map[4][0x80];
>  };
 

(like this one)
 
> diff --git a/payloads/libpayload/libpci/libpci.c b/payloads/libpayload/libpci/libpci.c
> index 0b54ba3..a62e30b 100644
> --- a/payloads/libpayload/libpci/libpci.c
> +++ b/payloads/libpayload/libpci/libpci.c
> @@ -96,6 +96,8 @@ void pci_filter_init(struct pci_access* pacc, struct pci_filter* pf)
>  	pf->device = -1;
>  }
>  
> +static char *invalid_pci_device_string = (char*)"invalid pci device string";

minor nitpick, i think this should be (char *), like char *invalid_....
earlier in the line. And maybe it can be const?

> Add strlcpy from OpenBSD
> 
> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

This one is
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From patrick at georgi-clan.de  Tue May 10 23:07:31 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 10 May 2011 23:07:31 +0200
Subject: [coreboot] [RFC] src/drivers/generic/generic used but not there
In-Reply-To: <20110509221738.GA32602@coreboot.org>
References: <20110509221738.GA32602@coreboot.org>
Message-ID: <4DC9A913.8090106@georgi-clan.de>

Am 10.05.2011 00:17, schrieb Stefan Reinauer:
> Looking for drivers/generic/generic in the source code, we use it quite
> a lot:

> Should we drop all those sub trees? Or try to fix them? What is needed
> to fix them?
Fix what? Is there an issue that needs fixing or should we just remove
all references to that driver?


Patrick



From stefan.reinauer at coreboot.org  Tue May 10 23:15:24 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 10 May 2011 23:15:24 +0200
Subject: [coreboot] [RFC] src/drivers/generic/generic used but not there
In-Reply-To: <4DC9A913.8090106@georgi-clan.de>
References: <20110509221738.GA32602@coreboot.org>
	<4DC9A913.8090106@georgi-clan.de>
Message-ID: <20110510211524.GA1507@coreboot.org>

* Patrick Georgi <patrick at georgi-clan.de> [110510 23:07]:
> Am 10.05.2011 00:17, schrieb Stefan Reinauer:
> > Looking for drivers/generic/generic in the source code, we use it quite
> > a lot:
> 
> > Should we drop all those sub trees? Or try to fix them? What is needed
> > to fix them?
>
> Fix what? Is there an issue that needs fixing or should we just remove
> all references to that driver?

That's what I am trying to find out. Why were all SPD ROMs referenced in
device tree.cb in the first place?

I think sconfig should through an error though if a chip XXX does not
exist (but not if XXX/chip.h does not exist)

Stefan




From svn at coreboot.org  Tue May 10 23:42:52 2011
From: svn at coreboot.org (repository service)
Date: Tue, 10 May 2011 23:42:52 +0200
Subject: [coreboot] [commit] r6563 - trunk/util/options
Message-ID: <E1QJuhg-0003p7-QZ@ra.coresystems.de>

Author: oxygene
Date: Tue May 10 23:42:52 2011
New Revision: 6563
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6563

Log:
Fix compilation error due to non-unix style line endings in cmos.layout file while generating option_table.h.

Windows, Mac and *nix type line endings are now taken care of.

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
Acked-by: Paul Menzel <paulepanter at users.sourceforge.net>

Modified:
   trunk/util/options/build_opt_tbl.c

Modified: trunk/util/options/build_opt_tbl.c
==============================================================================
--- trunk/util/options/build_opt_tbl.c	Mon May  9 22:53:38 2011	(r6562)
+++ trunk/util/options/build_opt_tbl.c	Tue May 10 23:42:52 2011	(r6563)
@@ -276,6 +276,7 @@
 	int enum_length;
 	int len;
 	char buf[16];
+	char val;
 
         for(i=1;i<argc;i++) {
                 if(argv[i][0]!='-') {
@@ -371,8 +372,9 @@
 		}
 
 		/* skip commented and blank lines */
-		if(line[0]=='#') continue;
-		if(line[strspn(line," ")]=='\n') continue;
+		val = line[strspn(line," ")];
+		/* takes care of *nix, Mac and Windows line ending formats */
+		if (val=='#' || val=='\n' || val=='\r') continue;
 		/* scan in the input data */
 		sscanf(line,"%d %d %c %d %s",
 			&ce->bit,&ce->length,&uc,&ce->config_id,&ce->name[0]);



From svn at coreboot.org  Tue May 10 23:47:57 2011
From: svn at coreboot.org (repository service)
Date: Tue, 10 May 2011 23:47:57 +0200
Subject: [coreboot] [commit] r6564 - trunk/src/cpu/x86/lapic
Message-ID: <E1QJumb-0002oU-QD@ra.coresystems.de>

Author: oxygene
Date: Tue May 10 23:47:57 2011
New Revision: 6564
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6564

Log:
This replaces the fixed shift values in the apic timer init with macros.

Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/cpu/x86/lapic/apic_timer.c

Modified: trunk/src/cpu/x86/lapic/apic_timer.c
==============================================================================
--- trunk/src/cpu/x86/lapic/apic_timer.c	Tue May 10 23:42:52 2011	(r6563)
+++ trunk/src/cpu/x86/lapic/apic_timer.c	Tue May 10 23:47:57 2011	(r6564)
@@ -36,7 +36,7 @@
 	msr_t fsb_clock_sts;
 
 	/* Set the apic timer to no interrupts and periodic mode */
-	lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 << 0));
+	lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED));
 
 	/* Set the divider to 1, no divider */
 	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);



From svn at coreboot.org  Tue May 10 23:53:13 2011
From: svn at coreboot.org (repository service)
Date: Tue, 10 May 2011 23:53:13 +0200
Subject: [coreboot] [commit] r6565 - in trunk/src: cpu/amd/dualcore
	cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/quadcore
	include/pc80 lib mainboard/getac/p470
	mainboard/kontron/986lcd-m mainboard/roda/rk886ex northb...
Message-ID: <E1QJurh-00030O-ON@ra.coresystems.de>

Author: oxygene
Date: Tue May 10 23:53:13 2011
New Revision: 6565
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6565

Log:
Change read_option() to a macro that wraps some API uglyness

Simplify
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/src/cpu/amd/dualcore/dualcore.c
   trunk/src/cpu/amd/model_10xxx/init_cpus.c
   trunk/src/cpu/amd/model_fxx/init_cpus.c
   trunk/src/cpu/amd/quadcore/quadcore.c
   trunk/src/include/pc80/mc146818rtc.h
   trunk/src/lib/uart8250.c
   trunk/src/mainboard/getac/p470/romstage.c
   trunk/src/mainboard/kontron/986lcd-m/romstage.c
   trunk/src/mainboard/roda/rk886ex/romstage.c
   trunk/src/northbridge/amd/amdk8/coherent_ht.c
   trunk/src/northbridge/amd/amdk8/raminit.c
   trunk/src/northbridge/amd/amdk8/raminit_f.c
   trunk/src/northbridge/intel/e7520/raminit.c
   trunk/src/northbridge/intel/e7525/raminit.c
   trunk/src/pc80/mc146818rtc_early.c

Modified: trunk/src/cpu/amd/dualcore/dualcore.c
==============================================================================
--- trunk/src/cpu/amd/dualcore/dualcore.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/cpu/amd/dualcore/dualcore.c	Tue May 10 23:53:13 2011	(r6565)
@@ -49,7 +49,7 @@
 	unsigned nodes;
 	unsigned nodeid;
 
-	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0))  {
+	if (read_option(multi_core, 0))  {
 		return; // disable multi_core
 	}
 

Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c	Tue May 10 23:53:13 2011	(r6565)
@@ -72,7 +72,7 @@
 	nodes = get_nodes();
 
 	if (!CONFIG_LOGICAL_CPUS ||
-	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 means multi core
+	    read_option(multi_core, 0) != 0) {	// 0 means multi core
 		disable_siblings = 1;
 	} else {
 		disable_siblings = 0;

Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/init_cpus.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/cpu/amd/model_fxx/init_cpus.c	Tue May 10 23:53:13 2011	(r6565)
@@ -25,7 +25,7 @@
 	nodes = get_nodes();
 
 	if (!CONFIG_LOGICAL_CPUS ||
-	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 means multi core
+	    read_option(multi_core, 0) != 0) {	// 0 means multi core
 		disable_siblings = 1;
 	} else {
 		disable_siblings = 0;

Modified: trunk/src/cpu/amd/quadcore/quadcore.c
==============================================================================
--- trunk/src/cpu/amd/quadcore/quadcore.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/cpu/amd/quadcore/quadcore.c	Tue May 10 23:53:13 2011	(r6565)
@@ -82,7 +82,7 @@
 	u32 nodeid;
 
 	// disable multi_core
-	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0)  {
+	if (read_option(multi_core, 0) != 0)  {
 		printk(BIOS_DEBUG, "Skip additional core init\n");
 		return;
 	}

Modified: trunk/src/include/pc80/mc146818rtc.h
==============================================================================
--- trunk/src/include/pc80/mc146818rtc.h	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/include/pc80/mc146818rtc.h	Tue May 10 23:53:13 2011	(r6565)
@@ -110,15 +110,16 @@
 void rtc_init(int invalid);
 #if CONFIG_USE_OPTION_TABLE
 int get_option(void *dest, const char *name);
-unsigned read_option(unsigned start, unsigned size, unsigned def);
+unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def);
 #else
 static inline int get_option(void *dest __attribute__((unused)),
 	const char *name __attribute__((unused))) { return -2; }
-static inline unsigned read_option(unsigned start, unsigned size, unsigned def)
+static inline unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
 	{ return def; }
 #endif
 #else
 #include <pc80/mc146818rtc_early.c>
 #endif
+#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))
 
 #endif /*  PC80_MC146818RTC_H */

Modified: trunk/src/lib/uart8250.c
==============================================================================
--- trunk/src/lib/uart8250.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/lib/uart8250.c	Tue May 10 23:53:13 2011	(r6565)
@@ -99,7 +99,7 @@
 	static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 };
 	unsigned b_index = 0;
 #if defined(__PRE_RAM__)
-	b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
+	b_index = read_option(baud_rate, 0);
 	b_index &= 7;
 	div = divisor[b_index];
 #else

Modified: trunk/src/mainboard/getac/p470/romstage.c
==============================================================================
--- trunk/src/mainboard/getac/p470/romstage.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/mainboard/getac/p470/romstage.c	Tue May 10 23:53:13 2011	(r6565)
@@ -83,7 +83,7 @@
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
-	if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
+	if (read_option(lpt, 0) != 0) {
 	       lpt_en = 1<<2; // enable LPT
 	}
 	// Enable Serial IRQ

Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c	Tue May 10 23:53:13 2011	(r6565)
@@ -59,7 +59,7 @@
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
-	if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
+	if (read_option(lpt, 0) != 0) {
 		lpt_en = 1<<2; // enable LPT
 	}
 	// Enable Serial IRQ
@@ -228,18 +228,18 @@
 	reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
 	reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
 
-	if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) {
+	if (read_option(ethernet1, 0) != 0) {
 		printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");
 		reg32 |= FD_PCIE1;
 	}
-	if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) {
+	if (read_option(ethernet2, 0) != 0) {
 		printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");
 		reg32 |= FD_PCIE2;
 	} else {
 		if (reg32 & FD_PCIE1)
 			port_shuffle = 1;
 	}
-	if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) {
+	if (read_option(ethernet3, 0) != 0) {
 		printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");
 		reg32 |= FD_PCIE3;
 	} else {

Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c	Tue May 10 23:53:13 2011	(r6565)
@@ -70,7 +70,7 @@
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
-	if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
+	if (read_option(lpt, 0) != 0) {
 	       lpt_en = 1<<2; // enable LPT
 	}
 	// Enable Serial IRQ

Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/coherent_ht.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/northbridge/amd/amdk8/coherent_ht.c	Tue May 10 23:53:13 2011	(r6565)
@@ -1599,7 +1599,7 @@
 #if CONFIG_LOGICAL_CPUS==1
 	unsigned total_cpus;
 
-	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */
+	if (read_option(multi_core, 0) == 0) { /* multi_core */
 		total_cpus = verify_dualcore(nodes);
 	}
 	else {

Modified: trunk/src/northbridge/amd/amdk8/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/northbridge/amd/amdk8/raminit.c	Tue May 10 23:53:13 2011	(r6565)
@@ -548,7 +548,7 @@
 	if (nbcap & NBCAP_ECC) {
 		dcl |= DCL_DimmEccEn;
 	}
-	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+	if (read_option(ECC_memory, 1) == 0) {
 		dcl &= ~DCL_DimmEccEn;
 	}
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
@@ -1100,7 +1100,7 @@
 {
 	unsigned long tom_k, base_k;
 
-	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
+	if (read_option(interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl);
 	} else {
 		printk(BIOS_DEBUG, "Interleaving disabled\n");
@@ -1530,7 +1530,7 @@
 
 	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
 	bios_cycle_time = min_cycle_times[
-		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
+		read_option(max_mem_clock, 0)];
 	if (bios_cycle_time > min_cycle_time) {
 		min_cycle_time = bios_cycle_time;
 	}

Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/northbridge/amd/amdk8/raminit_f.c	Tue May 10 23:53:13 2011	(r6565)
@@ -1108,7 +1108,7 @@
 	 * and if so count them.
 	 */
 #if defined(CMOS_VSTART_interleave_chip_selects)
-	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) == 0)
+	if (read_option(interleave_chip_selects, 1) == 0)
 		return 0;
 #else
 #if !CONFIG_INTERLEAVE_CHIP_SELECTS
@@ -1806,7 +1806,7 @@
 	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
 	bios_cycle_time = min_cycle_times[
 #ifdef CMOS_VSTART_max_mem_clock
-		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)
+		read_option(max_mem_clock, 0)
 #else
 #if defined(CONFIG_MAX_MEM_CLOCK)
 		CONFIG_MAX_MEM_CLOCK
@@ -2375,7 +2375,7 @@
 		dcl |= DCL_DimmEccEn;
 	}
 #ifdef CMOS_VSTART_ECC_memory
-	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+	if (read_option(ECC_memory, 1) == 0) {
 		dcl &= ~DCL_DimmEccEn;
 	}
 #else // CMOS_VSTART_ECC_memory not defined

Modified: trunk/src/northbridge/intel/e7520/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/e7520/raminit.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/northbridge/intel/e7520/raminit.c	Tue May 10 23:53:13 2011	(r6565)
@@ -618,7 +618,7 @@
 	}
 	ecc = 2;
 #if CONFIG_HAVE_OPTION_TABLE
-	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+	if (read_option(ECC_memory, 1) == 0) {
 		ecc = 0;  /* ECC off in CMOS so disable it */
 		print_debug("ECC off\n");
 	} else

Modified: trunk/src/northbridge/intel/e7525/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/e7525/raminit.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/northbridge/intel/e7525/raminit.c	Tue May 10 23:53:13 2011	(r6565)
@@ -624,7 +624,7 @@
 	}
 	ecc = 2;
 #if CONFIG_HAVE_OPTION_TABLE
-	if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
+	if (read_option(ECC_memory, 1) == 0) {
 		ecc = 0;  /* ECC off in CMOS so disable it */
 		print_debug("ECC off\n");
 	} else

Modified: trunk/src/pc80/mc146818rtc_early.c
==============================================================================
--- trunk/src/pc80/mc146818rtc_early.c	Tue May 10 23:47:57 2011	(r6564)
+++ trunk/src/pc80/mc146818rtc_early.c	Tue May 10 23:53:13 2011	(r6565)
@@ -92,7 +92,7 @@
 	return (byte & (1<<1));
 }
 
-unsigned read_option(unsigned start, unsigned size, unsigned def)
+unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
 {
 #if CONFIG_USE_OPTION_TABLE
 	unsigned byte;



From patrick at georgi-clan.de  Tue May 10 23:55:49 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 10 May 2011 23:55:49 +0200
Subject: [coreboot] [PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes
 for read_option() use
In-Reply-To: <20110510200714.GA29286@coreboot.org>
References: <4DC990AD.8030702@georgi-clan.de>
	<20110510200714.GA29286@coreboot.org>
Message-ID: <4DC9B465.9060203@georgi-clan.de>

Am 10.05.2011 22:07, schrieb Stefan Reinauer:
>> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
r6565, thanks.

>>  15 files changed, 24 insertions(+), 23 deletions(-)
> Wow are those the only occurences of readoption in romstage code?
read_option is used in romstage, get_option in ramstage. The latter
doesn't provide an option for default values.
I intend to change that once we declare defaults in cmos.layout (or its
successor), so the romstage gets the defaults from the same source.

But yes, there aren't any more read_option uses. Probably a sign that
the nvram subsystem is underused?

> Should we document that somewhere? 
Document what?


Patrick



From stefan.reinauer at coreboot.org  Wed May 11 00:04:36 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 11 May 2011 00:04:36 +0200
Subject: [coreboot] [PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes
 for read_option() use
In-Reply-To: <4DC9B465.9060203@georgi-clan.de>
References: <4DC990AD.8030702@georgi-clan.de>
	<20110510200714.GA29286@coreboot.org>
	<4DC9B465.9060203@georgi-clan.de>
Message-ID: <20110510220435.GA6571@coreboot.org>

* Patrick Georgi <patrick at georgi-clan.de> [110510 23:55]:
> Am 10.05.2011 22:07, schrieb Stefan Reinauer:
> >> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
> > Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
> r6565, thanks.
 
thanks.

> But yes, there aren't any more read_option uses. Probably a sign that
> the nvram subsystem is underused?

Yes, given how complex most cmos.layouts look, I was surprised.

Is there an easy way to clean those cmos.layout files up?
 
> > Should we document that somewhere? 
>
> Document what?

Which nvram variables are used in romstage (and by whom). e.g. that
multi_core does only make sense on AMD CPUs. Does it matter?




From stefan.reinauer at coreboot.org  Wed May 11 00:12:02 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 11 May 2011 00:12:02 +0200
Subject: [coreboot] Alternate for serial port debug messages
In-Reply-To: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>
References: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>
Message-ID: <20110510221202.GA16588@coreboot.org>

* Vikram Narayanan <vikram186 at gmail.com> [110510 20:10]:
> Hi, 
> 
> I am using a DELL laptop. The superio used is 
> "Found Nuvoton WPCE775x / NPCE781x (id=0x03, rev=0x06) at 0x4e".
> 
> Now the thing is there are no serial ports exposed outside in my laptop.
> Is there any other way out to see the debug messages of coreboot.(If at
> all coreboot supports my motherboard, or if I am planning to try if its
> not there)


You can use USB Debug or a MiniPCIe serial card from StarTech

http://www.coreboot.org/EHCI_Debug_Port
http://www.coreboot.org/Serial_console

Both options are around 50-100$

Stefan





From patrick at georgi-clan.de  Wed May 11 00:20:15 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 11 May 2011 00:20:15 +0200
Subject: [coreboot] [PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes
 for read_option() use
In-Reply-To: <20110510220435.GA6571@coreboot.org>
References: <4DC990AD.8030702@georgi-clan.de>
	<20110510200714.GA29286@coreboot.org>
	<4DC9B465.9060203@georgi-clan.de>
	<20110510220435.GA6571@coreboot.org>
Message-ID: <4DC9BA1F.2030303@georgi-clan.de>

Am 11.05.2011 00:04, schrieb Stefan Reinauer:
> Yes, given how complex most cmos.layouts look, I was surprised.
> Is there an easy way to clean those cmos.layout files up?
Obsolete build_opt_tbl by moving its functionality to nvramtool (that's
WIP here), define a new format (eg. the one on Infrastructure_Projects)
and implement that in nvramtool with both reader and writer. Then read
all cmos.layout files and write in their new form.

Not exactly "easy", but automated.

> Which nvram variables are used in romstage (and by whom). e.g. that
> multi_core does only make sense on AMD CPUs. Does it matter?
Infrastructure_Projects :-)
I'd like to move nvram variables to where they are used (eg. multi_core
to AMD CPUs).


Patrick



From scott at notabs.org  Wed May 11 01:41:37 2011
From: scott at notabs.org (Scott Duplichan)
Date: Tue, 10 May 2011 18:41:37 -0500
Subject: [coreboot] [PATCH] Replace the values of APIC timer init with
	macros
In-Reply-To: <1305048953.4263.5.camel@ubuntu.ubuntu-domain>
Message-ID: <mailman.4221.1355071914.16123.coreboot@coreboot.org>

Vikram Narayanan wrote:

]On Sun, 2011-05-08 at 00:34 +0530, Vikram Narayanan wrote:
]> This replaces the fixed shift values in the apic timer init with macros.
]> 
]> Signed-off by: Vikram Narayanan <vikram186 at gmail.com>
]> ---
]> --- a/src/cpu/x86/lapic/apic_timer.c	Sun May  8 00:18:12 2011
]> +++ b/src/cpu/x86/lapic/apic_timer.c	Sun May  8 00:08:54 2011
]> @@ -36,7 +36,7 @@
]>  	msr_t fsb_clock_sts;
]>  
]>  	/* Set the apic timer to no interrupts and periodic mode */
]> -	lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 <<
0));
]> +	lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC |
]LAPIC_LVT_MASKED));
]>  
]>  	/* Set the divider to 1, no divider */
]>  	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
]
]Think this is quite trivial. Can someone comment on this so that this
]will be merged in the next commit?
]
]-
]Thanks,
]Vikram

It looks OK to me, though there is an unneeded pair of parentheses.

acked by: Scott Duplichan <scott at notabs.org>





From graeme.russ at gmail.com  Wed May 11 01:44:00 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Wed, 11 May 2011 09:44:00 +1000
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <20110510160850.2499.qmail@stuge.se>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
Message-ID: <BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>

On Wed, May 11, 2011 at 2:08 AM, Peter Stuge <peter at stuge.se> wrote:
> Graeme Russ wrote:
>> I am extremely excited about this as the x86 U-Boot maintainer, but
>> even more so by the idea of two very mature and respected FLOSS
>> projects potentially becoming greater than the sum of their parts :)
>
> Yes good fun!
>
>

[snip]

>> ?- The majority of U-Boot and coreboot is licensed under the 'GPLv2 or (at
>> ? ?your option) any later version'
>
> coreboot is GPLv2 only, otherwise the facts are accurate.

>From http://www.coreboot.org/Development_Guidelines#License_Issues

    Contributed code must be GPL'd (preferably 'GPLv2 or any later
    version', but 'GPLv2' is fine, too). At the very minimum the code
    must have a GPL-compatible license.

But yes, I image a lot of the code predates this preference, much like
a lot of U-Boot code does

>> Now the politics ;)
>> ?- The U-Boot source 'must' be self contained - No external libraries.
>> ? ?Incorporating license compatible source is OK
>
> Well ok.. (why though?)

Because that's the way Wolfgang likes it ;)

>> ?- coreboot payloads should be in ELF (linked to libpayload)
>
> They do not neccessarily have to link to libpayload, but if they
> don't they have to replicate some of what libpayload does. That code
> duplication is pretty silly, so most payloads do use libpayload.

I think what will end up happening is porting enough of libpayload
across to U-Boot in order to get access to coreboot data structures.
Everything else either already exists in U-Boot (libc functionality) or
can be added using existing U-Boot architectural principals (USB keyboard,
VGA support etc)

>> ?- There should be minimal intrusion into the core U-Boot build scripts
>> ? ?(Makefiles, mk.configs etc) - I would assume the same applies to
>> ? ?coreboot build files as well. Hacking the U-Boot x86 specific build
>> ? ?files should be fine
>
> coreboot uses Kconfig for build time configuration and I think it
> would be no problem (maybe even desirable) to add a few special
> commands in order to grab a U-Boot from git, build it, and include it
> as payload in the output coreboot.rom. This is done for SeaBIOS
> already.

That's an issue for the coreboot team - sounds sensible enough

>> ?- Everything should 'just work' with a recent GNU toolchain (gcc,
>> ? ?binutils etc)
>
> coreboot has significant experiences from distribution toolchains
> being patched to the point where they are unable to correctly build
> coreboot itself and/or payloads. If the distribution toolchain works
> for you that's good, but most of the big name distributions have
> messed up their toolchains. The coreboot source includes a script to
> build known good versions of the toolchain, and the coreboot build
> system will automatically pick up such a toolchain if it is found
> during build.

I tend to use a pure breed toolchain (I build GCC and binutils from
scratch and don't use the disto's toolchain)

>> ?- U-Boot relocates to 'Top of RAM' - This is a fundamental architectural
>> ? ?design and not x86 specific. This feature should be retained for
>> ? ?consistency with other U-Boot arches
>
> IMO this might be a little misguided. Retaining behavior, especially
> across architecture, shouldn't be an end in itself. If U-Boot was the
> primary bootloader in this situation it would matter less. In the
> context of coreboot however U-Boot would be much easier to integrate
> with if this policy was not enforced. Maybe U-Boot wants to stay
> resident however, then there's not much choice except top of memory.

As Wolfgang has commented on in another post in this thread, there are
some pretty solid reasons behind this rationale. These reasons may be
more applicable to ARM/PPC embedded environments and possibly irrelevant
in the x86/PC world. Although this 'feature' is currently implemented on a
per-CPU architecture basis, this may change in the future - It's worth
keeping in mind so nobody gets blindsided

>> ?- Do we care about legacy BIOS support (SeaBIOS) for now (I think
>> ? ?not)?
>
> IMO it is not relevant to the integration of coreboot and U-Boot. If
> a BIOS is needed by U-Boot itself or whatever it loads, then SeaBIOS
> must be used as payload for coreboot, and SeaBIOS will then start
> U-Boot after setting up the BIOS environment.

Or U-Boot could load a SeaBIOS image and initialise it if needed. So
in a U-Boot script:
  - If the target OS is GNU/Linux the load the Linux kernel image and go
  - If the target OS is Windows (or any other OS which needs a BIOS) then
    U-Boot first loads a SeaBIOS image and then loads the image for the
    target OS (this may even be a 'GRUB' image for example)

>> So, a few questions
>> ?- How much of libpayload would we need to bring into U-Boot to provide
>> ? ?bare minimal payload delivery? U-Boot already contains it's own
>> ? ?minimal libc routines.
>
> Not much at all. You basically just have to look up the coreboot
> table.

Thought so - So we just port this bit

>> ?- How do we get VGA and USB keyboard support working?
>
> Write VGA and USB drivers. Or use the ones that are available in
> libpayload. Estimate 5-6 months of development effort to write from
> scratch. But you could also copy it all from libpayload of course.

U-Boot already has USB support framework - just a matter of writing device
drivers for the chipset hardware

>
> One thing to keep in mind here is that VGA will only be available if
> coreboot or SeaBIOS has set it up. coreboot only knows how to do this

Or if U-Boot does

> for two or three graphics chipsets. SeaBIOS can initialize any VGA
> option ROM, but then you need SeaBIOS in the loop.
> Option ROMs are ageold technology and stupid, but they are still
> firmly entrenched in PC hardware. A BIOS was always there so everyone
> assumes it will always stay there, not very many question if
> something better could be done.

Would be interesting to investigate implementing a stub in U-Boot to
initialise and use VGA option ROMs

>> ? ?Do other U-Boot boards implement console on anything other than
>> ? ?serial?
>
> U-Boot? Can't say.

>From Wolfgang : Yes

>> ?- Can we add relocation support to the coreboot ELF loader?
>
> ELF payloads are parsed at build time, simplified into a
> coreboot-internal format. Run time relocation is not so attractive.
>
>
>> ?- Does coreboot relocate into RAM? If so, what is the target address?
>
> Determined at build time.
>
>> ? ?What guarantee is there that the target address is valid?
>
> It's low enough in RAM.
>
>
>> ?- Could coreboot benefit from U-Boot's 'load to top of RAM' philosophy?
>
> I doubt it, but maybe?
>
>
>> ?- Is it worth playing around with segment registers to 'relocate' U-Boot
>
> Maybe?

On further though, probably not. The Linux protected mode entry point
requires a very specific segment setup - Using segments to 'relocate'
U-Boot is only going to make things very ugly, very quickly

>> ?- What hardware should be initialised in coreboot and what should be
>> ? ?initialised in U-Boot? (political question ;)
>
> Actually this is well defined. coreboot in general does not touch
> peripherals with VGA being the exception.

Agree - Have coreboot do the bare minimum to launch an arbitrary payload
and leave the rest up to U-Boot

>> ?- What about Chipset Microcode (CMC)
>> ?- What about System Management Mode (SMM)
>
> coreboot does provide the bare minimum for chipsets which need it,
> but preference is to not go beyond the busses.

Yes, I think CMC and SMM should be loaded by U-Boot. It may be
necessary for some boards to have CMC loaded by coreboot in order to
bring SDRAM controllers up

>> We can start with U-Boot linked to a fixed location in RAM and skip
>> relocations then work on either extending coreboot to perform
>> relocation fixups or have U-Boot perform the fixups based on RAM
>> information read from cbtable
>
> The latter sounds better to me. :)

But involves a double memcpy - A decision for later

>> From there, we can start to add device support (USB, video, PCI,
>> IDE/SATA etc)
>
> libpayload covers most of these. :) Take a look at a couple different
> libpayload users. FILO would probably be the closest to what U-Boot
> does.

Hmm, I'm thinking these should be implemented in U-Boot. I'm keeping
embedded x86 solutions in mind - I want to maintain the idea of U-Boot
being a primary bootloader for these systems and not rely on coreboot /
libpayload / SeaBIOS etc

Regards,

Graeme



From graeme.russ at gmail.com  Wed May 11 02:11:41 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Wed, 11 May 2011 10:11:41 +1000
Subject: [coreboot] [U-Boot] U-Boot-x86 / coreboot Integration
In-Reply-To: <20110510180310.8F8C8D6BE23@gemini.denx.de>
References: <4DC94CD4.2050904@gmail.com>
	<20110510180310.8F8C8D6BE23@gemini.denx.de>
Message-ID: <BANLkTi=P=H+3u+03+zyVfoUkzNFC2EPY2g@mail.gmail.com>

Hi Wolfgang

On Wed, May 11, 2011 at 4:03 AM, Wolfgang Denk <wd at denx.de> wrote:
> Dear Graeme Russ,
>
> In message <4DC94CD4.2050904 at gmail.com> you wrote:
>>
>> So coreboot and U-Boot are a good complement to each other so bringing
>> U-Boot to x86 PC mainboards via coreboot looks like a good idea - Now the
>> politics ;)
>> ?- The U-Boot source 'must' be self contained - No external libraries.
>> ? ?Incorporating license compatible source is OK
>
> The same is probably true for coreboot.
>
>> ?- coreboot payloads should be in ELF (linked to libpayload)
>
> Is this really necessary, assuming we have a self-contained payload
> that does not request any services from the tool that was used to
> start it?

Question for the coreboot guys. I think the linkage to libpayload can be
omitted, but include enough of libpayload to get to the coreboot data
structures which can tell U-Boot vital information regarding the hardware.

Also see below - If it's loading an ELF image, can't it just pass a
parameter which points to the tables?

>> ?- How much of libpayload would we need to bring into U-Boot to provide
>> ? ?bare minimal payload delivery? U-Boot already contains it's own minimal
>> ? ?libc routines.
>
> Right. ?See above - eventually such linking is not really necessary if
> the U-Boot ELF image is really self-contained.

Yes

>> ?- How do we get VGA and USB keyboard support working? Do other U-Boot
>> ? ?boards implement console on anything other than serial?
>
> Yes, we do support output on LCD and other video adapters, and we
> support input from USB keyboard (not to mentione netconsole, or
> netconsole over ethernet ?over USB and similar fancy stuff).

Nice :)

>> ?- Can we add relocation support to the coreboot ELF loader?
>
> Do we have to?

If we want U-Boot at top-of RAM and avoid a second memcpy then yes,
but as we know, it is not as simple as that. U-Boot relocates after it
has determined how much upper memory to reserve which isn't known until
U-Boot has enumerated it's hardware environment. Hence the reason U-Boot
will always have to suffer the penalty of the extra memcpy (the bootstrap
loader does not have enough information to reserve this memory for U-Boot)

>> ?- Does coreboot relocate into RAM? If so, what is the target address? What
>> ? ?guarantee is there that the target address is valid?
>
> Do we have to care? ?I would expect that we consider both coreboot and
> U-Boot as isolated entities, each performing it's own task. Coreboot
> will initialize the RAM and load and start U-Boot, similar to what a
> first stage loader does on systems that boot from NAND. ?Once U-Bootis
> running, it does so completely on its own.
>
>> ?- Could coreboot benefit from U-Boot's 'load to top of RAM' philosophy?
>
> Is there any need for this? ?Don't make things more complex than
> needed.

No, I don't think there is

>> ?- Is it worth playing around with segment registers to 'relocate' U-Boot
>
> That's a U-Boot question, right? ?Let's solve this independently.

Not really - If we want coreboot to place U-Boot at top-of-RAM then
coreboot would have to figure this out. But I think this is now a moot
point (see my other email)

>> ?- What hardware should be initialised in coreboot and what should be
>> ? ?initialised in U-Boot? (political question ;)
>
> No, that's a very practical; question. Coreboot should do as many of
> the x86 specific stuff as it can, and as it already does to load and
> start other payloads. ?And probably not more, at least not for now.

Yes - As I mentioned in my other post, coreboot should do as much as it
needs to (and not more) to load (arbitrary) payloads. The rest should
be up to U-Boot using the U-Boot principle of initialising only what
needs to be initialised.

> I think the best way to make this undertaking a success is to make it
> as unintrusive to both involved projects as possible.

Agree

>> I think a good start would be to create a new U-Boot target which includes
>> a stripped down libpayload in the U-Boot source. This target can exclude
>
> Why would we need that? ?I can understand that this may make initial
> porting and debugging easier ("early console output" etc.), but we
> should try to do without this.

Even more stripped than that - Just enough to get access to the coreboot
tables. Actually, if coreboot is launching an ELF payload, surely it
could pass a pointer to the tables as a argument to main()

>> We can start with U-Boot linked to a fixed location in RAM and skip
>> relocations then work on either extending coreboot to perform relocation
>> fixups or have U-Boot perform the fixups based on RAM information read from
>> cbtable
>
> I strongly recommend not to request changes to coreboot, and not to
> deviate from standard U-Boot methods.

Agree and Agree

> We are not re-inventing the wheel here. ?We have many similar
> situations where some ROM boot loader or xload or nand_spl code or
> onenand_ipl code is loading an U-Boot image into a halfway initialized
> system, and U-Boot starts there. ?I see no need to make coreboot use a
> different method.

Except the coreboot can load ELF images and if we can avoid a memcpy by
having coreboot do the relocation, we eek out that little bit more boot
speed ;)

>> P.S. Please keep both U-Boot and coreboot mailing lists Cc'd - Note: If you
>> are not on the coreboot ml, you emails will get bounced to a moderator :(
>
> I hope he is tolerant enough...

Regards,

Graeme



From kevin at koconnor.net  Wed May 11 02:23:42 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 10 May 2011 20:23:42 -0400
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
Message-ID: <20110511002341.GA30492@morn.localdomain>

On Wed, May 11, 2011 at 09:44:00AM +1000, Graeme Russ wrote:
> On Wed, May 11, 2011 at 2:08 AM, Peter Stuge <peter at stuge.se> wrote:
> > Graeme Russ wrote:
> >> ?- Do we care about legacy BIOS support (SeaBIOS) for now (I think
> >> ? ?not)?
> >
> > IMO it is not relevant to the integration of coreboot and U-Boot. If
> > a BIOS is needed by U-Boot itself or whatever it loads, then SeaBIOS
> > must be used as payload for coreboot, and SeaBIOS will then start
> > U-Boot after setting up the BIOS environment.
> 
> Or U-Boot could load a SeaBIOS image and initialise it if needed. So
> in a U-Boot script:
>   - If the target OS is GNU/Linux the load the Linux kernel image and go
>   - If the target OS is Windows (or any other OS which needs a BIOS) then
>     U-Boot first loads a SeaBIOS image and then loads the image for the
>     target OS (this may even be a 'GRUB' image for example)

That's possible to do, but would likely require some changes to SeaBIOS.

> > for two or three graphics chipsets. SeaBIOS can initialize any VGA
> > option ROM, but then you need SeaBIOS in the loop.
> > Option ROMs are ageold technology and stupid, but they are still
> > firmly entrenched in PC hardware. A BIOS was always there so everyone
> > assumes it will always stay there, not very many question if
> > something better could be done.
> 
> Would be interesting to investigate implementing a stub in U-Boot to
> initialise and use VGA option ROMs

VGA option ROMs call BIOS functions.  So, one needs a BIOS
implementation (eg, SeaBIOS) or an emulator for them (eg, in
coreboot).

-Kevin



From graeme.russ at gmail.com  Wed May 11 02:40:23 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Wed, 11 May 2011 10:40:23 +1000
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <20110511002341.GA30492@morn.localdomain>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
Message-ID: <BANLkTikf=UfxrBrT8=Y4QUEfvo=ZL8xLHg@mail.gmail.com>

Hi Kevin

On Wed, May 11, 2011 at 10:23 AM, Kevin O'Connor <kevin at koconnor.net> wrote:
> On Wed, May 11, 2011 at 09:44:00AM +1000, Graeme Russ wrote:
>> On Wed, May 11, 2011 at 2:08 AM, Peter Stuge <peter at stuge.se> wrote:
>> > Graeme Russ wrote:
>> >> ?- Do we care about legacy BIOS support (SeaBIOS) for now (I think
>> >> ? ?not)?
>> >
>> > IMO it is not relevant to the integration of coreboot and U-Boot. If
>> > a BIOS is needed by U-Boot itself or whatever it loads, then SeaBIOS
>> > must be used as payload for coreboot, and SeaBIOS will then start
>> > U-Boot after setting up the BIOS environment.
>>
>> Or U-Boot could load a SeaBIOS image and initialise it if needed. So
>> in a U-Boot script:
>> ? - If the target OS is GNU/Linux the load the Linux kernel image and go
>> ? - If the target OS is Windows (or any other OS which needs a BIOS) then
>> ? ? U-Boot first loads a SeaBIOS image and then loads the image for the
>> ? ? target OS (this may even be a 'GRUB' image for example)
>
> That's possible to do, but would likely require some changes to SeaBIOS.

I don't see why - I'm sure U-Boot could launch it in exactly the same way
coreboot does... Oh, I see - It will then start trying to boot the system
oops ;)

>
>> > for two or three graphics chipsets. SeaBIOS can initialize any VGA
>> > option ROM, but then you need SeaBIOS in the loop.
>> > Option ROMs are ageold technology and stupid, but they are still
>> > firmly entrenched in PC hardware. A BIOS was always there so everyone
>> > assumes it will always stay there, not very many question if
>> > something better could be done.
>>
>> Would be interesting to investigate implementing a stub in U-Boot to
>> initialise and use VGA option ROMs
>
> VGA option ROMs call BIOS functions. ?So, one needs a BIOS
> implementation (eg, SeaBIOS) or an emulator for them (eg, in
> coreboot).

How many functions are needed? (surely not all the IDE and keyboard stuff
for example) - Could the bare minimum be implemented in a stripped-down
modified SeaBIOS?

All this because stupid hardware manufacturers refuse to release details
of how to do even the most basic of functions with their hardware :(

Regards,

Graeme



From peter at stuge.se  Wed May 11 02:46:53 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 11 May 2011 02:46:53 +0200
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <BANLkTikf=UfxrBrT8=Y4QUEfvo=ZL8xLHg@mail.gmail.com>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
	<BANLkTikf=UfxrBrT8=Y4QUEfvo=ZL8xLHg@mail.gmail.com>
Message-ID: <20110511004653.26862.qmail@stuge.se>

Graeme Russ wrote:
> >> Would be interesting to investigate implementing a stub in U-Boot to
> >> initialise and use VGA option ROMs
> >
> > VGA option ROMs call BIOS functions. ?So, one needs a BIOS
> > implementation (eg, SeaBIOS) or an emulator for them (eg, in
> > coreboot).
> 
> How many functions are needed?

That depends completely on the particular VGA option ROM.

Having as complete a BIOS environment as can possibly be accomplished
is the only hope to making arbitrary option ROMs work.

Option ROMs are heavily tied into the BIOS concept.


> (surely not all the IDE and keyboard stuff for example)

I think I've seen some VGA option ROM get stuck waiting for
non-working keyboard BIOS services.


> - Could the bare minimum be implemented in a stripped-down modified
> SeaBIOS?

Not really.


> All this because stupid hardware manufacturers refuse to release details
> of how to do even the most basic of functions with their hardware :(

Welcome to coreboot.


//Peter



From kevin at koconnor.net  Wed May 11 02:53:53 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 10 May 2011 20:53:53 -0400
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <BANLkTikf=UfxrBrT8=Y4QUEfvo=ZL8xLHg@mail.gmail.com>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
	<BANLkTikf=UfxrBrT8=Y4QUEfvo=ZL8xLHg@mail.gmail.com>
Message-ID: <20110511005353.GA32299@morn.localdomain>

On Wed, May 11, 2011 at 10:40:23AM +1000, Graeme Russ wrote:
> On Wed, May 11, 2011 at 10:23 AM, Kevin O'Connor <kevin at koconnor.net> wrote:
> > VGA option ROMs call BIOS functions. ?So, one needs a BIOS
> > implementation (eg, SeaBIOS) or an emulator for them (eg, in
> > coreboot).
> 
> How many functions are needed? (surely not all the IDE and keyboard stuff
> for example) - Could the bare minimum be implemented in a stripped-down
> modified SeaBIOS?

The disk and keyboard drivers aren't needed to init VGA.

SeaBIOS has a Kconfig interface, and almost all features can be
disabled via that interface.

-Kevin



From kevin at koconnor.net  Wed May 11 02:38:37 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 10 May 2011 20:38:37 -0400
Subject: [coreboot] [U-Boot] U-Boot-x86 / coreboot Integration
In-Reply-To: <BANLkTi=P=H+3u+03+zyVfoUkzNFC2EPY2g@mail.gmail.com>
References: <4DC94CD4.2050904@gmail.com>
	<20110510180310.8F8C8D6BE23@gemini.denx.de>
	<BANLkTi=P=H+3u+03+zyVfoUkzNFC2EPY2g@mail.gmail.com>
Message-ID: <20110511003836.GB30492@morn.localdomain>

On Wed, May 11, 2011 at 10:11:41AM +1000, Graeme Russ wrote:
> On Wed, May 11, 2011 at 4:03 AM, Wolfgang Denk <wd at denx.de> wrote:
> > In message <4DC94CD4.2050904 at gmail.com> you wrote:
> >> ?- coreboot payloads should be in ELF (linked to libpayload)
> >
> > Is this really necessary, assuming we have a self-contained payload
> > that does not request any services from the tool that was used to
> > start it?
> 
> Question for the coreboot guys. I think the linkage to libpayload can be
> omitted, but include enough of libpayload to get to the coreboot data
> structures which can tell U-Boot vital information regarding the hardware.
> 
> Also see below - If it's loading an ELF image, can't it just pass a
> parameter which points to the tables?

Finding and parsing the coreboot tables is trivial - SeaBIOS does it
in ~170 lines of code.  See coreboot_fill_map():

http://code.coreboot.org/p/seabios/source/tree/master/src/coreboot.c#L126

Note, SeaBIOS is deployed as a coreboot payload, but it does not use
libpayload.

[...]
> >> ?- Can we add relocation support to the coreboot ELF loader?
> >
> > Do we have to?
> 
> If we want U-Boot at top-of RAM and avoid a second memcpy then yes,
> but as we know, it is not as simple as that. U-Boot relocates after it
> has determined how much upper memory to reserve which isn't known until
> U-Boot has enumerated it's hardware environment. Hence the reason U-Boot
> will always have to suffer the penalty of the extra memcpy (the bootstrap
> loader does not have enough information to reserve this memory for U-Boot)

If U-Boot can already relocate itself to top-of-ram, then I'd reuse
that - it can always be optimized later.

Note, SeaBIOS can also relocate part of itself to high memory.
(Though, SeaBIOS is pretty small, so the memcpy costs are trivial.)

-Kevin



From graeme.russ at gmail.com  Wed May 11 03:05:22 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Wed, 11 May 2011 11:05:22 +1000
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <20110511004653.26862.qmail@stuge.se>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
	<BANLkTikf=UfxrBrT8=Y4QUEfvo=ZL8xLHg@mail.gmail.com>
	<20110511004653.26862.qmail@stuge.se>
Message-ID: <BANLkTimE-0O19ZrYbKSh_von3AywJRioZA@mail.gmail.com>

On Wed, May 11, 2011 at 10:46 AM, Peter Stuge <peter at stuge.se> wrote:
> Graeme Russ wrote:
>> >> Would be interesting to investigate implementing a stub in U-Boot to
>> >> initialise and use VGA option ROMs
>> >
>> > VGA option ROMs call BIOS functions. ?So, one needs a BIOS
>> > implementation (eg, SeaBIOS) or an emulator for them (eg, in
>> > coreboot).
>>
>> How many functions are needed?
>
> That depends completely on the particular VGA option ROM.
>
> Having as complete a BIOS environment as can possibly be accomplished
> is the only hope to making arbitrary option ROMs work.
>
> Option ROMs are heavily tied into the BIOS concept.
>
>
>> (surely not all the IDE and keyboard stuff for example)
>
> I think I've seen some VGA option ROM get stuck waiting for
> non-working keyboard BIOS services.
>
>
>> - Could the bare minimum be implemented in a stripped-down modified
>> SeaBIOS?
>
> Not really.
>
>
>> All this because stupid hardware manufacturers refuse to release details
>> of how to do even the most basic of functions with their hardware :(
>
> Welcome to coreboot.

OK, well maybe the coreboot/u-boot scenarion goes like this:

1) coreboot initialises SDRAM and other 'critical' hardware
2) coreboot launches a U-Boot payload
3) If U-Boot does not care about console output then move on and boot
   the OS
4) If U-Boot has a driver for the video hardware then use it for console
   output
5) If U-Boot does not have a driver then load SeaBIOS (modified a bit) and
   the VGA option ROM and use BIOS calls for console output

horrid, horrid, horrid

Regards,

Graeme



From kevin at koconnor.net  Wed May 11 03:16:38 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 10 May 2011 21:16:38 -0400
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <20110511004653.26862.qmail@stuge.se>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
	<BANLkTikf=UfxrBrT8=Y4QUEfvo=ZL8xLHg@mail.gmail.com>
	<20110511004653.26862.qmail@stuge.se>
Message-ID: <20110511011638.GA606@morn.localdomain>

On Wed, May 11, 2011 at 02:46:53AM +0200, Peter Stuge wrote:
> Graeme Russ wrote:
> > >> Would be interesting to investigate implementing a stub in U-Boot to
> > >> initialise and use VGA option ROMs
> > >
> > > VGA option ROMs call BIOS functions. ?So, one needs a BIOS
> > > implementation (eg, SeaBIOS) or an emulator for them (eg, in
> > > coreboot).
> > 
> > How many functions are needed?
> 
> That depends completely on the particular VGA option ROM.
> 
> Having as complete a BIOS environment as can possibly be accomplished
> is the only hope to making arbitrary option ROMs work.
> 
> Option ROMs are heavily tied into the BIOS concept.
> 
> > (surely not all the IDE and keyboard stuff for example)
> 
> I think I've seen some VGA option ROM get stuck waiting for
> non-working keyboard BIOS services.

One will require all the BIOS interfaces, but the hardware drivers
shouldn't be needed.  So, in SeaBIOS' Kconfig menu, disabling stuff in
"BIOS interfaces" is risky, but one can pretty much disable all the
features under "General Features" and "Hardware support".

> > - Could the bare minimum be implemented in a stripped-down modified
> > SeaBIOS?
> 
> Not really.

Removing the hardware drivers and other niceties can be done.

Note that SeaBIOS is already pretty small (~96K uncompressed / 45K
compressed), so I doubt cutting out features would matter much for
size.  (In a quick test, pulling out everything but interfaces brought
the size to ~45K/24K.)  However, it could be done if one doesn't want
to bother initializing hardware (eg, USB) twice.

-Kevin



From graeme.russ at gmail.com  Wed May 11 05:12:16 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Wed, 11 May 2011 13:12:16 +1000
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <20110511002341.GA30492@morn.localdomain>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
Message-ID: <BANLkTikvBgJUqrgv9QXKi5oRkhQCF+ZykA@mail.gmail.com>

>> > for two or three graphics chipsets. SeaBIOS can initialize any VGA
>> > option ROM, but then you need SeaBIOS in the loop.
>> > Option ROMs are ageold technology and stupid, but they are still
>> > firmly entrenched in PC hardware. A BIOS was always there so everyone
>> > assumes it will always stay there, not very many question if
>> > something better could be done.
>>
>> Would be interesting to investigate implementing a stub in U-Boot to
>> initialise and use VGA option ROMs
>
> VGA option ROMs call BIOS functions. ?So, one needs a BIOS
> implementation (eg, SeaBIOS) or an emulator for them (eg, in
> coreboot).

What does Linux do? i.e. if you boot Linux from coreboot, how does it
output to the VGA console? I know it uses BIOS early on (before switching
to protected mode) but what does it do after entering protected mode?

Regards,

Graeme



From kevin at koconnor.net  Wed May 11 05:20:00 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 10 May 2011 23:20:00 -0400
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <BANLkTikvBgJUqrgv9QXKi5oRkhQCF+ZykA@mail.gmail.com>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
	<BANLkTikvBgJUqrgv9QXKi5oRkhQCF+ZykA@mail.gmail.com>
Message-ID: <20110511032000.GA13471@morn.localdomain>

On Wed, May 11, 2011 at 01:12:16PM +1000, Graeme Russ wrote:
> >> > for two or three graphics chipsets. SeaBIOS can initialize any VGA
> >> > option ROM, but then you need SeaBIOS in the loop.
> >> > Option ROMs are ageold technology and stupid, but they are still
> >> > firmly entrenched in PC hardware. A BIOS was always there so everyone
> >> > assumes it will always stay there, not very many question if
> >> > something better could be done.
> >>
> >> Would be interesting to investigate implementing a stub in U-Boot to
> >> initialise and use VGA option ROMs
> >
> > VGA option ROMs call BIOS functions. ?So, one needs a BIOS
> > implementation (eg, SeaBIOS) or an emulator for them (eg, in
> > coreboot).
> 
> What does Linux do? i.e. if you boot Linux from coreboot, how does it
> output to the VGA console? I know it uses BIOS early on (before switching
> to protected mode) but what does it do after entering protected mode?

In general, one enables the coreboot VGA option ROM emulation when
booting Linux directly from coreboot.

-Kevin



From graeme.russ at gmail.com  Wed May 11 05:27:30 2011
From: graeme.russ at gmail.com (Graeme Russ)
Date: Wed, 11 May 2011 13:27:30 +1000
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <20110511032000.GA13471@morn.localdomain>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
	<BANLkTikvBgJUqrgv9QXKi5oRkhQCF+ZykA@mail.gmail.com>
	<20110511032000.GA13471@morn.localdomain>
Message-ID: <BANLkTikWg9Od2VgkpyfqKoipfc15q7D5Ww@mail.gmail.com>

On Wed, May 11, 2011 at 1:20 PM, Kevin O'Connor <kevin at koconnor.net> wrote:
> On Wed, May 11, 2011 at 01:12:16PM +1000, Graeme Russ wrote:
>> >> > for two or three graphics chipsets. SeaBIOS can initialize any VGA
>> >> > option ROM, but then you need SeaBIOS in the loop.
>> >> > Option ROMs are ageold technology and stupid, but they are still
>> >> > firmly entrenched in PC hardware. A BIOS was always there so everyone
>> >> > assumes it will always stay there, not very many question if
>> >> > something better could be done.
>> >>
>> >> Would be interesting to investigate implementing a stub in U-Boot to
>> >> initialise and use VGA option ROMs
>> >
>> > VGA option ROMs call BIOS functions. ?So, one needs a BIOS
>> > implementation (eg, SeaBIOS) or an emulator for them (eg, in
>> > coreboot).
>>
>> What does Linux do? i.e. if you boot Linux from coreboot, how does it
>> output to the VGA console? I know it uses BIOS early on (before switching
>> to protected mode) but what does it do after entering protected mode?
>
> In general, one enables the coreboot VGA option ROM emulation when
> booting Linux directly from coreboot.
>

Yes, I understand that - But how does Linux output to the VGA console
after switching to Protected Mode? Does it still do BIOS calls?

And what about all those Linux drivers in drivers/video - Would porting
them (to U-Boot) elliminate the need for BIOS/Option ROMs

Note: Please pardon my ignorance if these appear to be dumb questions - I
really don't know how the guts of VGA console works

Regards,

Graeme



From kevin at koconnor.net  Wed May 11 05:51:49 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 10 May 2011 23:51:49 -0400
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <BANLkTikWg9Od2VgkpyfqKoipfc15q7D5Ww@mail.gmail.com>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
	<BANLkTikvBgJUqrgv9QXKi5oRkhQCF+ZykA@mail.gmail.com>
	<20110511032000.GA13471@morn.localdomain>
	<BANLkTikWg9Od2VgkpyfqKoipfc15q7D5Ww@mail.gmail.com>
Message-ID: <20110511035148.GA14339@morn.localdomain>

On Wed, May 11, 2011 at 01:27:30PM +1000, Graeme Russ wrote:
> On Wed, May 11, 2011 at 1:20 PM, Kevin O'Connor <kevin at koconnor.net> wrote:
> > On Wed, May 11, 2011 at 01:12:16PM +1000, Graeme Russ wrote:
> >> What does Linux do? i.e. if you boot Linux from coreboot, how does it
> >> output to the VGA console? I know it uses BIOS early on (before switching
> >> to protected mode) but what does it do after entering protected mode?
> >
> > In general, one enables the coreboot VGA option ROM emulation when
> > booting Linux directly from coreboot.
> 
> Yes, I understand that - But how does Linux output to the VGA console
> after switching to Protected Mode? Does it still do BIOS calls?
> 
> And what about all those Linux drivers in drivers/video - Would porting
> them (to U-Boot) elliminate the need for BIOS/Option ROMs

I'm not really sure - I'd guess it will vary significantly from card
to card and driver to driver.

I'm pretty sure you need to run the VGA option ROM if you want the
legacy text console mode.  However, some of the Linux/X11 drivers will
likely be able to get the card into graphics mode without running the
option ROM.

-Kevin



From patrick at georgi-clan.de  Wed May 11 08:47:33 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 11 May 2011 08:47:33 +0200
Subject: [coreboot] [PATCHes] Adopt coreboot build system for libpayload
In-Reply-To: <20110510201924.GB29286@coreboot.org>
References: <4DC990FF.4010305@georgi-clan.de>
	<20110510201924.GB29286@coreboot.org>
Message-ID: <4DCA3105.1000603@georgi-clan.de>

Am 10.05.2011 22:19, schrieb Stefan Reinauer:
> * Patrick Georgi <patrick at georgi-clan.de> [110510 21:24]:
>> -## modification, are permitted provided that the following conditions
> Hm... can we relicense this under the original license instead? I
> dislike going to GPL in an otherwise cleanly BSD license based project.
> The coresystems written parts may certainly be relicensed under BSD. Not
> sure how much except the header is actually left from AMD and co.
Most of it is by Ron, you and I. (as taken from svn annotate which isn't
entirely accurate, but gives a good estimate).
But things in Makefile are either rather trivial or ours, as all the
coreboot/libpayload specific rules were moved to Makefile.inc.

>> +config MEMMAP_RAM_ONLY
> Is this needed for reducing the warnings? What else is it needed for?
We had this ad-hoc config option in the code, so I made it selectable.
Maybe we should get rid of that option altogether?

>>  struct layout_maps {
>> -	char *country;
>> +	const char *country;
>>  	unsigned short map[4][0x57];
> can the map be const, too?
yes.

>> +static char *invalid_pci_device_string = (char*)"invalid pci device string";
> minor nitpick, i think this should be (char *), like char *invalid_....
> earlier in the line. And maybe it can be const?
It's an ugly hack to work around libpci API requirements, which is why
it is non-const.

>> Add strlcpy from OpenBSD
>> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
> This one is
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Thanks, but it depends (in this version) on the other patches (build
system hookup)


Patrick



From wd at denx.de  Wed May 11 08:51:10 2011
From: wd at denx.de (Wolfgang Denk)
Date: Wed, 11 May 2011 08:51:10 +0200
Subject: [coreboot] [U-Boot]  U-Boot-x86 / coreboot Integration
In-Reply-To: <20110511035148.GA14339@morn.localdomain>
References: <4DC94CD4.2050904@gmail.com> <20110510160850.2499.qmail@stuge.se>
	<BANLkTi=CfQduG+t5HdMfEanAmO7D_N4D7Q@mail.gmail.com>
	<20110511002341.GA30492@morn.localdomain>
	<BANLkTikvBgJUqrgv9QXKi5oRkhQCF+ZykA@mail.gmail.com>
	<20110511032000.GA13471@morn.localdomain>
	<BANLkTikWg9Od2VgkpyfqKoipfc15q7D5Ww@mail.gmail.com>
	<20110511035148.GA14339@morn.localdomain>
Message-ID: <20110511065110.8160ED6F24E@gemini.denx.de>

Dear Kevin O'Connor,

In message <20110511035148.GA14339 at morn.localdomain> you wrote:
>
> > And what about all those Linux drivers in drivers/video - Would porting
> > them (to U-Boot) elliminate the need for BIOS/Option ROMs
> 
> I'm not really sure - I'd guess it will vary significantly from card
> to card and driver to driver.

Indeed.

> I'm pretty sure you need to run the VGA option ROM if you want the
> legacy text console mode.  However, some of the Linux/X11 drivers will
> likely be able to get the card into graphics mode without running the
> option ROM.

Usually you have to run the ROM init code; on many cards this is
needed for example to initialize the video RAM (well known problem,
isn't it?). Guess why the code in drivers/bios_emulator is needed in
U-Boot ?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The human mind ordinarily operates at only ten percent of its capaci-
ty - the rest is overhead for the operating system.



From wd at denx.de  Wed May 11 08:47:32 2011
From: wd at denx.de (Wolfgang Denk)
Date: Wed, 11 May 2011 08:47:32 +0200
Subject: [coreboot] [U-Boot] U-Boot-x86 / coreboot Integration
In-Reply-To: <BANLkTi=P=H+3u+03+zyVfoUkzNFC2EPY2g@mail.gmail.com>
References: <4DC94CD4.2050904@gmail.com>
	<20110510180310.8F8C8D6BE23@gemini.denx.de>
	<BANLkTi=P=H+3u+03+zyVfoUkzNFC2EPY2g@mail.gmail.com>
Message-ID: <20110511064732.AA44DD6F24E@gemini.denx.de>

Dear Graeme Russ,

In message <BANLkTi=P=H+3u+03+zyVfoUkzNFC2EPY2g at mail.gmail.com> you wrote:
>
> >>  - Is it worth playing around with segment registers to 'relocate' U-Boot
> >
> > That's a U-Boot question, right?  Let's solve this independently.
>
> Not really - If we want coreboot to place U-Boot at top-of-RAM then
> coreboot would have to figure this out. But I think this is now a moot
> point (see my other email)

I think we should start simple, like we do for example with NAND
booting systems.  Here we agree on a fixed load address for U-Boot,
too, so we can certainly do the same for Coreboot.

At least initially.  If somebody finds time and ressources this could
be added as an optimization later.

> >>  - What hardware should be initialised in coreboot and what should be
> >>    initialised in U-Boot? (political question ;)
> >
> > No, that's a very practical; question. Coreboot should do as many of
> > the x86 specific stuff as it can, and as it already does to load and
> > start other payloads.  And probably not more, at least not for now.
>
> Yes - As I mentioned in my other post, coreboot should do as much as it
> needs to (and not more) to load (arbitrary) payloads. The rest should
> be up to U-Boot using the U-Boot principle of initialising only what
> needs to be initialised.

Yes, but we also should try to avoid duplication of code - if coreboot
already includes code to initialize things that need to be
initialized, we should use this, and not duplicate the function in
U-Boot without need.

> > We are not re-inventing the wheel here.  We have many similar
> > situations where some ROM boot loader or xload or nand_spl code or
> > onenand_ipl code is loading an U-Boot image into a halfway initialized
> > system, and U-Boot starts there.  I see no need to make coreboot use a
> > different method.
>
> Except the coreboot can load ELF images and if we can avoid a memcpy by
> having coreboot do the relocation, we eek out that little bit more boot
> speed ;)

Keep things simple first, and add optimization later, when we have
everything running.  Early optimization is...

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
God runs electromagnetics by wave theory on  Monday,  Wednesday,  and
Friday,  and the Devil runs them by quantum theory on Tuesday, Thurs-
day, and Saturday.                                   -- William Bragg



From svn at coreboot.org  Wed May 11 09:44:28 2011
From: svn at coreboot.org (repository service)
Date: Wed, 11 May 2011 09:44:28 +0200
Subject: [coreboot] [commit] r6566 - trunk/src/northbridge/amd/amdk8
Message-ID: <E1QK45s-0008NQ-1j@ra.coresystems.de>

Author: oxygene
Date: Wed May 11 09:44:27 2011
New Revision: 6566
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6566

Log:
Work around unclean CMOS handling for now

Stefan switched away from #ifdef across the tree (and is absolutely right with that), but
unfortunately there are some special cases that trigger in even more special situations.

Revert one such change selectively. It's destined to go once CMOS is reworked.

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/northbridge/amd/amdk8/raminit_f.c

Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f.c	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/northbridge/amd/amdk8/raminit_f.c	Wed May 11 09:44:27 2011	(r6566)
@@ -1111,7 +1111,7 @@
 	if (read_option(interleave_chip_selects, 1) == 0)
 		return 0;
 #else
-#if !CONFIG_INTERLEAVE_CHIP_SELECTS
+#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || !CONFIG_INTERLEAVE_CHIP_SELECTS
 	return 0;
 #endif
 #endif



From svn at coreboot.org  Wed May 11 09:47:44 2011
From: svn at coreboot.org (repository service)
Date: Wed, 11 May 2011 09:47:44 +0200
Subject: [coreboot] [commit] r6567 - in trunk/src/mainboard: . siemens
	siemens/sitemp_g1p1 siemens/sitemp_g1p1/acpi
Message-ID: <E1QK492-0004Xq-5m@ra.coresystems.de>

Author: oxygene
Date: Wed May 11 09:47:43 2011
New Revision: 6567
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6567

Log:
Add Siemens SITEMP-G1 board

The code is loosely based on AMD dbm690t (and copied from there)
and adapted to match the Siemens SITEMP-G1 board.
It boots both Linux and Windows XP (and if it doesn't then complain
with me [Patrick] because in that case I must have messed it up when
integrating the patch)

Signed-off-by: Josef Kellermann <seppk at arcor.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Added:
   trunk/src/mainboard/siemens/
   trunk/src/mainboard/siemens/Kconfig
   trunk/src/mainboard/siemens/sitemp_g1p1/
      - copied from r6565, trunk/src/mainboard/amd/dbm690t/
   trunk/src/mainboard/siemens/sitemp_g1p1/Makefile.inc
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.c
   trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.h
Modified:
   trunk/src/mainboard/Kconfig
   trunk/src/mainboard/siemens/sitemp_g1p1/Kconfig
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
   trunk/src/mainboard/siemens/sitemp_g1p1/chip.h
   trunk/src/mainboard/siemens/sitemp_g1p1/cmos.layout
   trunk/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
   trunk/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
   trunk/src/mainboard/siemens/sitemp_g1p1/fadt.c
   trunk/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
   trunk/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
   trunk/src/mainboard/siemens/sitemp_g1p1/mainboard.c
   trunk/src/mainboard/siemens/sitemp_g1p1/mptable.c
   trunk/src/mainboard/siemens/sitemp_g1p1/resourcemap.c
   trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c

Modified: trunk/src/mainboard/Kconfig
==============================================================================
--- trunk/src/mainboard/Kconfig	Wed May 11 09:44:27 2011	(r6566)
+++ trunk/src/mainboard/Kconfig	Wed May 11 09:47:43 2011	(r6567)
@@ -92,6 +92,8 @@
 	bool "RCA"
 config VENDOR_RODA
 	bool "Roda"
+config VENDOR_SIEMENS
+	bool "Siemens"
 config VENDOR_SOYO
 	bool "Soyo"
 config VENDOR_SUNW
@@ -163,6 +165,7 @@
 source "src/mainboard/pcengines/Kconfig"
 source "src/mainboard/rca/Kconfig"
 source "src/mainboard/roda/Kconfig"
+source "src/mainboard/siemens/Kconfig"
 source "src/mainboard/soyo/Kconfig"
 source "src/mainboard/sunw/Kconfig"
 source "src/mainboard/supermicro/Kconfig"

Added: trunk/src/mainboard/siemens/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/Kconfig	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,17 @@
+if VENDOR_SIEMENS
+
+choice
+	prompt "Mainboard model"
+
+config BOARD_SIEMENS_SITEMP_G1P1
+	bool "MB SITEMP-G1 (U1P0/U1P1)"
+
+endchoice
+
+source "src/mainboard/siemens/sitemp_g1p1/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Siemens"
+
+endif # VENDOR_SIEMENS

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/Kconfig	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/Kconfig	Wed May 11 09:47:43 2011	(r6567)
@@ -1,4 +1,4 @@
-if BOARD_AMD_DBM690T
+if BOARD_SIEMENS_SITEMP_G1P1
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -22,10 +22,16 @@
 	select RAMINIT_SYSINFO
 	select QRANK_DIMM_SUPPORT
 	select SET_FIDVID
-
+	select GFXUMA
+	select EXT_CONF_SUPPORT	
+	
 config MAINBOARD_DIR
 	string
-	default amd/dbm690t
+	default siemens/sitemp_g1p1
+	
+config LINT01_CONVERSION
+	bool
+	default y
 
 config APIC_ID_OFFSET
 	hex
@@ -33,7 +39,7 @@
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "DBM690T"
+	default "MB SITEMP-G1 (U1P0/U1P1)"
 
 config MAX_CPUS
 	int
@@ -42,7 +48,7 @@
 config MAX_PHYSICAL_CPUS
 	int
 	default 1
-
+	
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1
@@ -59,4 +65,16 @@
 	int
 	default 11
 
-endif # BOARD_AMD_DBM690T
+config IOMMU
+	bool
+	default n
+	
+config HW_SCRUBBER
+	bool
+	default n
+	
+config ECC_MEMORY
+	bool
+	default n
+	
+endif # BOARD_SIEMENS_SITEMP_G1P1

Added: trunk/src/mainboard/siemens/sitemp_g1p1/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/Makefile.inc	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2010 Siemens AG, Inc.
+## (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += int15_func.c
+

Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+	DefinitionBlock (
+		"DSDT.AML",
+		"DSDT",
+		0x01,
+		"XXXXXX",
+		"XXXXXXXX",
+		0x00010001
+		)
+	{
+		#include "debug.asl"
+	}
+*/
+
+/*
+* 0x80: POST_BASE
+* 0x3F8: DEBCOM_BASE
+* X80: POST_REGION
+* P80: PORT80
+*
+* CREG: DEBCOM_REGION
+* CUAR: DEBCOM_UART
+* CDAT: DEBCOM_DATA
+* CDLM: DEBCOM_DLM
+* DLCR: DEBCOM_LCR
+* CMCR: DEBCOM_MCR
+* CLSR: DEBCOM_LSR
+*
+* DEBUG_INIT	DINI
+*/
+
+OperationRegion(X80, SystemIO, 0x80, 1)
+	Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+	Field(CREG, ByteAcc, NoLock, Preserve)
+{
+	CDAT, 8,
+	CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
+}
+
+/*
+* DINI
+* Initialize the COM port to 115,200 8-N-1
+*/
+Method(DINI)
+{
+	store(0x83, DLCR)
+	store(0x01, CDAT)	/* 115200 baud (low) */
+	store(0x00, CDLM)	/* 115200 baud (high) */
+	store(0x03, DLCR)	/* word=8 stop=1 parity=none */
+	store(0x03, CMCR)	/* DTR=1 RTS=1 Out2=Off Loop=Off */
+	store(0x00, CDLM)	/* turn off interrupts */
+}
+
+/*
+* THRE
+* Wait for COM port transmitter holding register to go empty
+*/
+Method(THRE)
+{
+	and(CLSR, 0x20, local0)
+	while (Lequal(local0, Zero)) {
+		and(CLSR, 0x20, local0)
+	}
+}
+
+/*
+* OUTX
+* Send a single raw character
+*/
+Method(OUTX, 1)
+{
+	THRE()
+	store(Arg0, CDAT)
+}
+
+/*
+* OUTC
+* Send a single character, expanding LF into CR/LF
+*/
+Method(OUTC, 1)
+{
+	if (LEqual(Arg0, 0x0a)) {
+		OUTX(0x0d)
+	}
+	OUTX(Arg0)
+}
+
+/*
+* DBGN
+* Send a single hex nibble
+*/
+Method(DBGN, 1)
+{
+	and(Arg0, 0x0f, Local0)
+	if (LLess(Local0, 10)) {
+		add(Local0, 0x30, Local0)
+	} else {
+		add(Local0, 0x37, Local0)
+	}
+	OUTC(Local0)
+}
+
+/*
+* DBGB
+* Send a hex byte
+*/
+Method(DBGB, 1)
+{
+	ShiftRight(Arg0, 4, Local0)
+	DBGN(Local0)
+	DBGN(Arg0)
+}
+
+/*
+* DBGW
+* Send a hex word
+*/
+Method(DBGW, 1)
+{
+	ShiftRight(Arg0, 8, Local0)
+	DBGB(Local0)
+	DBGB(Arg0)
+}
+
+/*
+* DBGD
+* Send a hex Dword
+*/
+Method(DBGD, 1)
+{
+	ShiftRight(Arg0, 16, Local0)
+	DBGW(Local0)
+	DBGW(Arg0)
+}
+
+/*
+* DBGO
+* Send either a string or an integer
+*/
+Method(DBGO, 1)
+{
+	/* DINI() */
+	if (LEqual(ObjectType(Arg0), 1)) {
+		if (LGreater(Arg0, 0xffff)) {
+			DBGD(Arg0)
+		} else {
+			if (LGreater(Arg0, 0xff)) {
+				DBGW(Arg0)
+			} else {
+				DBGB(Arg0)
+			}
+		}
+	} else {
+		Name(BDBG, Buffer(80) {})
+		store(Arg0, BDBG)
+		store(0, Local1)
+		while (One) {
+			store(GETC(BDBG, Local1), Local0)
+			if (LEqual(Local0, 0)) {
+				return (0)
+			}
+			OUTC(Local0)
+			Increment(Local1)
+		}
+	}
+	return (0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+	CreateByteField(Arg0, Arg1, DBGC)
+	return (DBGC)
+}

Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,316 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+ 
+/* Supported sleep states: */
+Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+Name(\_SB.CSPS ,0)		/* Current Sleep State (S0, ... , S5) */
+Name(CSMS, 0)			/* Current System State */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+*		-none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort	the operation without notification to
+* the ACPI driver.  This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+	/* DBGO("\\_PTS\n") */
+	/* DBGO("From S0 to S") */
+	/* DBGO(Arg0) */
+	/* DBGO("\n") */
+
+	/* Don't allow PCIRST# to reset USB */
+	if (LEqual(Arg0,3)){
+		Store(0,URRE)
+	}
+
+	/* Clear sleep SMI status flag and enable sleep SMI trap. */
+	/*Store(One, CSSM)
+	Store(One, SSEN)*/
+
+	/* On older chips, clear PciExpWakeDisEn */
+	/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+	*    	Store(0,\_SB.PWDE)
+	*}
+	*/
+
+	/* Clear wake status structure. */
+	Store(0, Index(WKST,0))
+	Store(0, Index(WKST,1))
+	\_SB.PCI0.SIOS (Arg0)
+} /* End Method(\_PTS) */
+
+/*
+*  The following method results in a "not a valid reserved NameSeg"
+*  warning so I have commented it out for the duration.  It isn't
+*  used, so it could be removed.
+*
+*
+*  	\_GTS OEM Going To Sleep method
+*
+*  	Entry:
+*  		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*  	Exit:
+*  		-none-
+*
+*  Method(\_GTS, 1) {
+*  DBGO("\\_GTS\n")
+*  DBGO("From S0 to S")
+*  DBGO(Arg0)
+*  DBGO("\n")
+*  }
+*/
+
+/*
+*	\_BFS OEM Back From Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		-none-
+*/
+Method(\_BFS, 1) {
+	/* DBGO("\\_BFS\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+}
+
+/*
+*  \_WAK System Wake method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		Return package of 2 DWords
+*		Dword 1 - Status
+*			0x00000000	wake succeeded
+*			0x00000001	Wake was signaled but failed due to lack of power
+*			0x00000002	Wake was signaled but failed due to thermal condition
+*		Dword 2 - Power Supply state
+*			if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+	/* DBGO("\\_WAK\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+
+	/* Re-enable HPET */
+	Store(1,HPDE)
+
+	/* Restore PCIRST# so it resets USB */
+	if (LEqual(Arg0,3)){
+		Store(1,URRE)
+	}
+
+	/* Arbitrarily clear PciExpWakeStatus */
+	Store(PWST, PWST)
+
+	/* if(DeRefOf(Index(WKST,0))) {
+	*	Store(0, Index(WKST,1))
+	* } else {
+	*	Store(Arg0, Index(WKST,1))
+	* }
+	*/
+	\_SB.PCI0.SIOW (Arg0)
+	Return(WKST)
+} /* End Method(\_WAK) */
+
+Scope(\_GPE) {	/* Start Scope GPE */
+	/*  General event 3  */
+	Method(_L03) {
+		/* DBGO("\\_GPE\\_L00\n") */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  Legacy PM event  */
+	Method(_L08) {
+		/* DBGO("\\_GPE\\_L08\n") */
+	}
+
+	/*  Temp warning (TWarn) event  */
+	Method(_L09) {
+		/* DBGO("\\_GPE\\_L09\n") */
+		Notify (\_TZ.TZ00, 0x80)
+	}
+
+	/*  Reserved  */
+	/* Method(_L0A) {
+	*	DBGO("\\_GPE\\_L0A\n")
+	* }
+	*/
+
+	/*  USB controller PME#  */
+	Method(_L0B) {
+		/* DBGO("\\_GPE\\_L0B\n") */
+		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  AC97 controller PME#  */
+	/* Method(_L0C) {
+	*	DBGO("\\_GPE\\_L0C\n")
+	* }
+	*/
+
+	/*  OtherTherm PME#  */
+	/* Method(_L0D) {
+	*	DBGO("\\_GPE\\_L0D\n")
+	* }
+	*/
+
+	/*  GPM9 SCI event - Moved to USB.asl */
+	/* Method(_L0E) {
+	*	DBGO("\\_GPE\\_L0E\n")
+	* }
+	*/
+
+	/*  PCIe HotPlug event  */
+	/* Method(_L0F) {
+	* 	DBGO("\\_GPE\\_L0F\n")
+	* }
+	*/
+
+	/*  ExtEvent0 SCI event  */
+	Method(_L10) {
+		/* DBGO("\\_GPE\\_L10\n") */
+	}
+
+
+	/*  ExtEvent1 SCI event  */
+	Method(_L11) {
+		/* DBGO("\\_GPE\\_L11\n") */
+	}
+
+	/*  PCIe PME# event  */
+	/* Method(_L12) {
+	*	DBGO("\\_GPE\\_L12\n")
+	* }
+	*/
+
+	/*  GPM0 SCI event - Moved to USB.asl */
+	/* Method(_L13) {
+	* 	DBGO("\\_GPE\\_L13\n")
+	* }
+	*/
+
+	/*  GPM1 SCI event - Moved to USB.asl */
+	/* Method(_L14) {
+	* 	DBGO("\\_GPE\\_L14\n")
+	* }
+	*/
+
+	/*  GPM2 SCI event - Moved to USB.asl */
+	/* Method(_L15) {
+	* 	DBGO("\\_GPE\\_L15\n")
+	* }
+	*/
+
+	/*  GPM3 SCI event - Moved to USB.asl */
+	/* Method(_L16) {
+	*	DBGO("\\_GPE\\_L16\n")
+	* }
+	*/
+
+	/*  GPM8 SCI event - Moved to USB.asl */
+	/* Method(_L17) {
+	* 	DBGO("\\_GPE\\_L17\n")
+	* }
+	*/
+
+	/*  GPIO0 or GEvent8 event  */
+	Method(_L18) {
+		/* DBGO("\\_GPE\\_L18\n") */
+		Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  GPM4 SCI event - Moved to USB.asl */
+	/* Method(_L19) {
+	* 	DBGO("\\_GPE\\_L19\n")
+	* }
+	*/
+
+	/*  GPM5 SCI event - Moved to USB.asl */
+	/* Method(_L1A) {
+	*	DBGO("\\_GPE\\_L1A\n")
+	* }
+	*/
+
+	/*  Azalia SCI event  */
+	Method(_L1B) {
+		/* DBGO("\\_GPE\\_L1B\n") */
+		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  GPM6 SCI event - Reassigned to _L06 */
+	/* Method(_L1C) {
+	*	DBGO("\\_GPE\\_L1C\n")
+	* }
+	*/
+
+	/*  GPM7 SCI event - Reassigned to _L07 */
+	/* Method(_L1D) {
+	*	DBGO("\\_GPE\\_L1D\n")
+	* }
+	*/
+
+	/*  GPIO2 or GPIO66 SCI event  */
+	/* Method(_L1E) {
+	* 	DBGO("\\_GPE\\_L1E\n")
+	* }
+	*/
+
+	/*  SATA SCI event  */
+	/* SATA Hot Plug Support -> acpi/sata.asl */
+} 	/* End Scope GPE */

Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,218 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope(\_SB) {
+	#include "globutil.asl"
+}
+*/
+
+/* string compare functions */
+Method(MIN, 2)
+{
+	if (LLess(Arg0, Arg1)) {
+		Return(Arg0)
+	} else {
+		Return(Arg1)
+	}
+}
+
+Method(SLEN, 1)
+{
+	Store(Arg0, Local0)
+	Return(Sizeof(Local0))
+}
+
+Method(S2BF, 1)
+{
+	Add(SLEN(Arg0), One, Local0)
+	Name(BUFF, Buffer(Local0) {})
+	Store(Arg0, BUFF)
+	Return(BUFF)
+}
+
+/* Strong string compare.  Checks both length and content */
+Method(SCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	Store(Zero, Local4)
+	Store(SLEN(Arg0), Local5)
+	Store(SLEN(Arg1), Local6)
+	Store(MIN(Local5, Local6), Local7)
+
+	While(LLess(Local4, Local7)) {
+		Store(Derefof(Index(Local0, Local4)), Local2)
+		Store(Derefof(Index(Local1, Local4)), Local3)
+		if (LGreater(Local2, Local3)) {
+			Return(One)
+		} else {
+			if (LLess(Local2, Local3)) {
+				Return(Ones)
+			}
+		}
+		Increment(Local4)
+	}
+	if (LLess(Local4, Local5)) {
+		Return(One)
+	} else {
+		if (LLess(Local4, Local6)) {
+			Return(Ones)
+		} else {
+			Return(Zero)
+		}
+	}
+}
+
+/* Weak string compare.  Checks to find Arg1 at beginning of Arg0.
+* Fails if length(Arg0) < length(Arg1).  Returns 0 on Fail, 1 on
+* Pass.
+*/
+Method(WCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	if (LLess(SLEN(Arg0), SLEN(Arg1))) {
+		Return(0)
+	}
+	Store(Zero, Local2)
+	Store(SLEN(Arg1), Local3)
+
+	While(LLess(Local2, Local3)) {
+		if (LNotEqual(Derefof(Index(Local0, Local2)),
+			Derefof(Index(Local1, Local2)))) {
+			Return(0)
+		}
+		Increment(Local2)
+	}
+	Return(One)
+}
+
+/* ARG0 = IRQ Number(0-15)
+* Returns Bit Map
+*/
+Method(I2BM, 1)
+{
+	Store(0, Local0)
+	if (LNotEqual(ARG0, 0)) {
+		Store(1, Local1)
+		ShiftLeft(Local1, ARG0, Local0)
+	}
+	Return(Local0)
+}
+Method (SEQL, 2, Serialized)
+{
+	Store (SizeOf (Arg0), Local0)
+	Store (SizeOf (Arg1), Local1)
+	If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
+
+	Name (BUF0, Buffer (Local0) {})
+	Store (Arg0, BUF0)
+	Name (BUF1, Buffer (Local0) {})
+	Store (Arg1, BUF1)
+	Store (Zero, Local2)
+	While (LLess (Local2, Local0))
+	{
+		Store (DerefOf (Index (BUF0, Local2)), Local3)
+		Store (DerefOf (Index (BUF1, Local2)), Local4)
+		If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
+
+		Increment (Local2)
+	}
+
+	Return (One)
+}
+
+/* GetMemoryResources(Node, Link) */
+Method (GMEM, 2, NotSerialized)
+{
+	Name (BUF0, ResourceTemplate ()
+	{
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+			0x00000000, // Address Space Granularity
+			0x00000000, // Address Range Minimum
+			0x00000000, // Address Range Maximum
+			0x00000000, // Address Translation Offset
+			0x00000001,,,
+			, AddressRangeMemory, TypeStatic)
+	})
+	CreateDWordField (BUF0, 0x0A, MMIN)
+	CreateDWordField (BUF0, 0x0E, MMAX)
+	CreateDWordField (BUF0, 0x16, MLEN)
+	Store (0x00, Local0)
+	Store (0x00, Local4)
+	Store (0x00, Local3)
+	While (LLess (Local0, 0x10))
+	{
+		/* Get value of the first register */
+		Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
+		Increment (Local0)
+		Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
+		If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */
+		{
+			If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */
+			{
+				/* If Link Matches (or we got passed 0xFF) */
+				If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+				{
+					/* Extract the Base and Limit values */
+					Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
+					Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
+					Or (MMAX, 0xFFFF, MMAX)
+					Subtract (MMAX, MMIN, MLEN)
+					Increment (MLEN)
+
+					If (Local4) /* I've already done this once */
+					{
+						Concatenate (RTAG (BUF0), Local3, Local5)
+						Store (Local5, Local3)
+					}
+					Else
+					{
+						Store (RTAG (BUF0), Local3)
+					}
+
+					Increment (Local4)
+				}
+			}
+		}
+
+		Increment (Local0)
+	}
+
+	If (LNot (Local4)) /* No resources for this node and link. */
+	{
+		Store (RTAG (BUF0), Local3)
+	}
+
+	Return (Local3)
+}
+
+Method (RTAG, 1, NotSerialized)
+{
+	Store (Arg0, Local0)
+	Store (SizeOf (Local0), Local1)
+	Subtract (Local1, 0x02, Local1)
+	Multiply (Local1, 0x08, Local1)
+	CreateField (Local0, 0x00, Local1, RETB)
+	Store (RETB, Local2)
+	Return (Local2)
+}

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/acpi/ide.asl	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -50,18 +50,23 @@
 	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
 })
 
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
+OperationRegion(IDEC, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(IDEC, AnyAcc, NoLock, Preserve)
 {
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPTS, 8,	/* 0x40: 0:7  Primary PIO Slave Timing */
+	PPTM, 8,	/* 0x40: 8:15 Primary PIO Master Timing */
+	OFFSET(0x04),
+	PMTS, 8,	/* 0x44: 0:7  Primary MWDMA Slave Timing */
+	PMTM, 8,	/* 0x44: 7:15 Primary MWDMA Master Timing */
+	OFFSET(0x08),
+	PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A),
+	PPMM, 4,	/* Primary PIO master Mode */
 	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	OFFSET(0x14),
+	PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16),
+	PDMM, 4,	/* Primary UltraDMA Mode */
 	PDSM, 4,	/* Primary UltraDMA Mode */
 }
 
@@ -74,9 +79,9 @@
 	Return(Multiply(30, Add(Local0, Local1)))
 }
 
-Device(PRID)
+Device(PRIM)
 {
-	Name (_ADR, Zero)
+	Name (_ADR, 0)
 	Method(_GTM, 0)
 	{
 		NAME(OTBF, Buffer(20) { /* out buffer */
@@ -206,7 +211,7 @@
 		}
 	}		/* End Device(MST) */
 
-	Device(SLAV)
+	Device(SLV)
 	{
 		Name(_ADR, 1)
 		Method(_GTF) {

Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+Name(PCIF, 0)
+
+Method(_PIC, 1, NotSerialized)
+{
+	Store(Arg0, PCIF)
+	If (Arg0)
+	{
+		\_SB.PCI0.LPC0.CIRQ()
+	}
+}
+
+External (\_PR.CPU0, DeviceObj)
+External (\_PR.CPU1, DeviceObj)
+
+Scope(\_SB)
+{
+
+	Method(_INI, 0)
+	{
+		Store (2000, OSYS)
+
+		If (CondRefOf(_OSI, Local0)) {
+
+			If (_OSI("Linux")) {
+				Store (1, LINX)
+			}
+
+			If (_OSI("Windows 2001")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP1")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP2")) {
+				Store (2002, OSYS)
+			}
+
+			If (_OSI("Windows 2006")) {
+				Store (2006, OSYS)
+			}
+		}
+	}
+}
\ No newline at end of file

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/acpi/routing.asl	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,112 +18,33 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
+	
 /* Routing is in System Bus scope */
-Scope(\_SB) {
+Scope(\_SB)
+{
 	Name(PR0, Package(){
 		/* NB devices */
-		/* Bus 0, Dev 0 - RS690 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
-		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
-		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
-		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
 		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
 		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0012FFFF, 1, INTA, 0 },
+		Package(){0x0012FFFF, 1, \_SB.PCI0.LPC0.INTG, 0 },
 
 		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
-		Package(){0x0013FFFF, 0, INTA, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-		Package(){0x0013FFFF, 2, INTC, 0 },
-		Package(){0x0013FFFF, 3, INTD, 0 },
+		Package(){0x0013FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 },
+		Package(){0x0013FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 },
+		Package(){0x0013FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 },
+		Package(){0x0013FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 },
 
 		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
+		Package(){0x0014FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 },
+		Package(){0x0014FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 },
+		Package(){0x0014FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 },
+		Package(){0x0014FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 },
 	})
 
 	Name(APR0, Package(){
 		/* NB devices in APIC mode */
 		/* Bus 0, Dev 0 - RS690 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		/* Package(){0x0001FFFF, 0, 0, 18 }, */
-		/* package(){0x0001FFFF, 1, 0, 19 }, */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		/* Package(){0x0004FFFF, 1, 0, 17 }, */
-		/* Package(){0x0004FFFF, 2, 0, 18 }, */
-		/* Package(){0x0004FFFF, 3, 0, 19 }, */
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		/* Package(){0x0005FFFF, 1, 0, 18 }, */
-		/* Package(){0x0005FFFF, 2, 0, 19 }, */
-		/* Package(){0x0005FFFF, 3, 0, 16 }, */
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		/* Package(){0x0006FFFF, 1, 0, 19 }, */
-		/* Package(){0x0006FFFF, 2, 0, 16 }, */
-		/* Package(){0x0006FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		/* Package(){0x0007FFFF, 1, 0, 16 }, */
-		/* Package(){0x0007FFFF, 2, 0, 17 }, */
-		/* Package(){0x0007FFFF, 3, 0, 18 }, */
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
 		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
 		/* Bus 0, Dev 18 - SATA controller #1 */
 		Package(){0x0012FFFF, 0, 0, 22 },
 
@@ -130,42 +53,34 @@
 		Package(){0x0013FFFF, 1, 0, 17 },
 		Package(){0x0013FFFF, 2, 0, 18 },
 		Package(){0x0013FFFF, 3, 0, 19 },
-		/* Package(){0x00130004, 2, 0, 18 }, */
-		/* Package(){0x00130005, 3, 0, 19 }, */
 
 		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
-		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 0, 0, 16 }, 
 		Package(){0x0014FFFF, 1, 0, 17 },
 		Package(){0x0014FFFF, 2, 0, 18 },
 		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
 	})
 
 	Name(PR1, Package(){
 		/* Internal graphics - RS690 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
+		Package(){0x0005FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 },
+		Package(){0x0005FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 },
+		Package(){0x0005FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 },
+		Package(){0x0005FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 },
 	})
 
 	Name(APR1, Package(){
 		/* Internal graphics - RS690 VGA, Bus1, Dev5 */
 		Package(){0x0005FFFF, 0, 0, 18 },
 		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
 	})
 
 	Name(PS2, Package(){
 		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
+		Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTC, 0 },
+		Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTD, 0 },
+		Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTA, 0 },
+		Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTB, 0 },
 	})
 
 	Name(APS2, Package(){
@@ -178,10 +93,10 @@
 
 	Name(PS4, Package(){
 		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
+		Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 },
+		Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 },
+		Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 },
+		Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 },
 	})
 
 	Name(APS4, Package(){
@@ -194,10 +109,10 @@
 
 	Name(PS5, Package(){
 		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
+		Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTB, 0 },
+		Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTC, 0 },
+		Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTD, 0 },
+		Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTA, 0 },
 	})
 
 	Name(APS5, Package(){
@@ -210,10 +125,10 @@
 
 	Name(PS6, Package(){
 		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
+		Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTC, 0 },
+		Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTD, 0 },
+		Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTA, 0 },
+		Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTB, 0 },
 	})
 
 	Name(APS6, Package(){
@@ -225,15 +140,15 @@
 	})
 
 	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
+		/* PCIe slot - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTD, 0 },
+		Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTA, 0 },
+		Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTB, 0 },
+		Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTC, 0 },
 	})
 
 	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		/* PCIe slot - Hooked to PCIe slot 7 */
 		Package(){0x0000FFFF, 0, 0, 19 },
 		Package(){0x0000FFFF, 1, 0, 16 },
 		Package(){0x0000FFFF, 2, 0, 17 },
@@ -241,18 +156,23 @@
 	})
 
 	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
+		/* PCI slots: slot 1 behind Dev14, Fun4. */
+		Package(){0x005FFFF, 0, \_SB.PCI0.LPC0.INTF, 0 }, // Phoenix does it
+		Package(){0x005FFFF, 1, \_SB.PCI0.LPC0.INTG, 0 }, // Phoenix does it
+		Package(){0x004FFFF, 0, \_SB.PCI0.LPC0.INTE, 0 },
+		Package(){0x004FFFF, 1, \_SB.PCI0.LPC0.INTF, 0 },
+		Package(){0x004FFFF, 2, \_SB.PCI0.LPC0.INTG, 0 },
+		Package(){0x004FFFF, 3, \_SB.PCI0.LPC0.INTH, 0 },	
+	})
+	
+	Name(AP2P, Package(){
+		/* PCI slots: slot 0 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 21 }, // Phoenix does it
+		Package(){0x0005FFFF, 1, 0, 22 }, // Phoenix does it
+		Package(){0x0004FFFF, 0, 0, 20 },
+		Package(){0x0004FFFF, 1, 0, 21 },
+		Package(){0x0004FFFF, 2, 0, 22 },
+		Package(){0x0004FFFF, 3, 0, 23 },
 	})
+			
 }

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/acpi/sata.asl	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -118,7 +118,7 @@
 			if (LGreater(\_SB.P0IS,0)) {
 				sleep(32)
 			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			Notify(\_SB.PCI0.SATA.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
 			store(one, \_SB.P0PR)
 		}
 
@@ -126,7 +126,7 @@
 			if (LGreater(\_SB.P1IS,0)) {
 				sleep(32)
 			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			Notify(\_SB.PCI0.SATA.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
 			store(one, \_SB.P1PR)
 		}
 
@@ -134,7 +134,7 @@
 			if (LGreater(\_SB.P2IS,0)) {
 				sleep(32)
 			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			Notify(\_SB.PCI0.SATA.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
 			store(one, \_SB.P2PR)
 		}
 
@@ -142,8 +142,9 @@
 			if (LGreater(\_SB.P3IS,0)) {
 				sleep(32)
 			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			Notify(\_SB.PCI0.SATA.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
 			store(one, \_SB.P3PR)
 		}
 	}
 }
+

Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+/* Status and notification definitions */
+
+#define STA_MISSING			    0x00
+#define STA_PRESENT			    0x01
+#define	STA_ENABLED			    0x03
+#define STA_DISABLED		    0x09
+#define	STA_INVISIBLE		    0x0B
+#define	STA_UNAVAILABLE		    0x0D
+#define	STA_VISIBLE			    0x0F
+
+/* SMBus status codes */
+#define SMB_OK                  0x00
+#define SMB_UnknownFail         0x07
+#define SMB_DevAddrNAK          0x10
+#define SMB_DeviceError         0x11
+#define SMB_DevCmdDenied        0x12
+#define SMB_UnknownErr          0x13
+#define SMB_DevAccDenied        0x17
+#define SMB_Timeout             0x18
+#define SMB_HstUnsuppProtocol   0x19
+#define SMB_Busy                0x1A
+#define SMB_PktChkError         0x1F
+
+/* Device Object Notification Values */
+#define	NOTIFY_BUS_CHECK		0x00
+#define	NOTIFY_DEVICE_CHECK		0x01
+#define	NOTIFY_DEVICE_WAKE		0x02
+#define	NOTIFY_EJECT_REQUEST	0x03
+#define	NOTIFY_DEVICE_CHECK_JR	0x04
+#define	NOTIFY_FREQUENCY_ERROR	0x05
+#define	NOTIFY_BUS_MODE			0x06
+#define	NOTIFY_POWER_FAULT		0x07
+#define	NOTIFY_CAPABILITIES		0x08
+#define	NOTIFY_PLD_CHECK		0x09
+#define	NOTIFY_SLIT_UPDATE		0x0B
+
+/* Battery Device Notification Values */
+#define	NOTIFY_BAT_STATUSCHG	0x80
+#define	NOTIFY_BAT_INFOCHG  	0x81
+#define	NOTIFY_BAT_MAINTDATA    0x82
+
+/* Power Source Object Notification Values */
+#define	NOTIFY_PWR_STATUSCHG	0x80
+
+/* Thermal Zone Object Notification Values */
+#define	NOTIFY_TZ_STATUSCHG	    0x80
+#define	NOTIFY_TZ_TRIPPTCHG	    0x81
+#define	NOTIFY_TZ_DEVLISTCHG	0x82
+#define	NOTIFY_TZ_RELTBLCHG 	0x83
+
+/* Power Button Notification Values */
+#define	NOTIFY_POWER_BUTTON		0x80
+
+/* Sleep Button Notification Values */
+#define	NOTIFY_SLEEP_BUTTON		0x80
+
+/* Lid Notification Values */
+#define	NOTIFY_LID_STATUSCHG	0x80
+
+/* Processor Device Notification Values */
+#define	NOTIFY_CPU_PPCCHG   	0x80
+#define	NOTIFY_CPU_CSTATECHG  	0x81
+#define	NOTIFY_CPU_THROTLCHG    0x82
+
+/* User Presence Device Notification Values */
+#define	NOTIFY_USR_PRESNCECHG	0x80
+
+/* Battery Device Notification Values */
+#define	NOTIFY_ALS_ILLUMCHG 	0x80
+#define	NOTIFY_ALS_COLORTMPCHG 	0x81
+#define	NOTIFY_ALS_RESPCHG      0x82
+
+

Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+ 
+/* THERMAL */
+Scope(\_TZ) {
+	Name (KELV, 2732)
+	Name (THOT, 800)
+	Name (TCRT, 850)
+
+	ThermalZone(TZ00) {
+		Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+			/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+			Return(Add(0, 2730))
+		}
+		Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+			/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+			Return(Package() {\_TZ.TZ00.FAN0})
+		}
+		Device (FAN0) {
+			Name(_HID, EISAID("PNP0C0B"))
+			Name(_PR0, Package() {PFN0})
+		}
+
+		PowerResource(PFN0,0,0) {
+			Method(_STA) {
+				Store(0xF,Local0)
+				Return(Local0)
+			}
+			Method(_ON) {
+				/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+			}
+			Method(_OFF) {
+				/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+			}
+		}
+		
+		// Processors used for active cooling
+		Method (_PSL, 0, Serialized)
+		{
+			If (MPEN) {
+				Return (Package() {\_PR.CPU0, \_PR.CPU1})
+			}
+			Return (Package() {\_PR.CPU0})
+		}
+		
+		Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+			/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+			Return (Add (THOT, KELV))
+		}
+		Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+			/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+			Return (Add (TCRT, KELV))
+		}
+		Method(_TMP,0) {	/* return current temp of this zone */
+			Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+			If (LGreater (Local0, 0x10)) {
+				Store (Local0, Local1)
+			}
+			Else {
+				Add (Local0, THOT, Local0)
+				Return (Add (400, KELV))
+			}
+
+			Store (SMBR (0x07, 0x4C, 0x01), Local0)
+			/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+			/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+			If (LGreater (Local0, 0x10)) {
+				If (LGreater (Local0, Local1)) {
+					Store (Local0, Local1)
+				}
+
+				Multiply (Local1, 10, Local1)
+				Return (Add (Local1, KELV))
+			}
+			Else {
+				Add (Local0, THOT, Local0)
+				Return (Add (400 , KELV))
+			}
+		} /* end of _TMP */
+	} /* end of TZ00 */
+}
\ No newline at end of file

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/acpi/usb.asl	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -18,13 +18,6 @@
  */
 
 /* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
 Method(UCOC, 0) {
 	Sleep(20)
     	Store(0x13,CMTI)
@@ -38,7 +31,7 @@
 			UCOC()
 			if(LEqual(GPB0,PLC0)) {
 				Not(PLC0,PLC0)
-				Store(PLC0, \_SB.PT0D)
+				Store(PLC0, \_SB_.PT0D)
 			}
 		}
 	}
@@ -51,7 +44,7 @@
 			UCOC()
 			if (LEqual(GPB1,PLC1)) {
 				Not(PLC1,PLC1)
-				Store(PLC1, \_SB.PT1D)
+				Store(PLC1, \_SB_.PT1D)
 			}
 		}
 	}
@@ -64,7 +57,7 @@
 			UCOC()
 			if (LEqual(GPB2,PLC2)) {
 				Not(PLC2,PLC2)
-				Store(PLC2, \_SB.PT2D)
+				Store(PLC2, \_SB_.PT2D)
 			}
 		}
 	}
@@ -77,7 +70,7 @@
 			UCOC()
 			if (LEqual(GPB3,PLC3)) {
 				Not(PLC3,PLC3)
-				Store(PLC3, \_SB.PT3D)
+				Store(PLC3, \_SB_.PT3D)
 			}
 		}
 	}
@@ -90,7 +83,7 @@
 			UCOC()
 			if (LEqual(GPB4,PLC4)) {
 				Not(PLC4,PLC4)
-				Store(PLC4, \_SB.PT4D)
+				Store(PLC4, \_SB_.PT4D)
 			}
 		}
 	}
@@ -103,7 +96,7 @@
 			UCOC()
 			if (LEqual(GPB5,PLC5)) {
 				Not(PLC5,PLC5)
-				Store(PLC5, \_SB.PT5D)
+				Store(PLC5, \_SB_.PT5D)
 			}
 		}
 	}
@@ -117,7 +110,7 @@
 			UCOC()
 			if (LEqual(GPB6,PLC6)) {
 				Not(PLC6,PLC6)
-				Store(PLC6, \_SB.PT6D)
+				Store(PLC6, \_SB_.PT6D)
 			}
 		}
 	}
@@ -131,7 +124,7 @@
 			UCOC()
 			if (LEqual(GPB7,PLC7)) {
 				Not(PLC7,PLC7)
-				Store(PLC7, \_SB.PT7D)
+				Store(PLC7, \_SB_.PT7D)
 			}
 		}
 	}
@@ -143,7 +136,7 @@
 		Method (_L17) {
 			if (LEqual(G8IS,PLC8)) {
 				Not(PLC8,PLC8)
-				Store(PLC8, \_SB.PT8D)
+				Store(PLC8, \_SB_.PT8D)
 			}
 		}
 	}
@@ -154,7 +147,7 @@
 	Scope (\_GPE) {
 		Method (_L0E) {
 			if (LEqual(G9IS,0)) {
-			Store(1,\_SB.PT9D)
+			Store(1,\_SB_.PT9D)
 			}
 		}
 	}

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/acpi_tables.c	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c	Wed May 11 09:47:43 2011	(r6567)
@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,19 +23,25 @@
 #include <string.h>
 #include <arch/acpi.h>
 #include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
+#include <../../../northbridge/amd/amdk8/acpi.h>
 #include <arch/cpu.h>
 #include <cpu/amd/model_fxx_powernow.h>
-
-extern u16 pm_base;
+#include <southbridge/amd/rs690/rs690.h>
 
 #define DUMP_ACPI_TABLES 0
 
+#ifndef CONFIG_LINT01_CONVERSION
+#define CONFIG_LINT01_CONVERSION 1
+#endif
+
+extern u16 pm_base;
+
 /*
 * Assume the max pstate number is 8
 * 0x21(33 bytes) is one package length of _PSS package
@@ -41,11 +49,67 @@
 
 #define Maxpstate 8
 #define Defpkglength 0x21
+#define GLOBAL_VARS_SIZE 0x100
+
+typedef struct {
+	/* Miscellaneous */
+	u16 osys;
+	u16 linx;
+	u32	pcba;
+	u8  mpen;
+	u8 reserv[247];
+} __attribute__((packed)) global_vars_t;
+
+static void acpi_write_gvars(global_vars_t *gvars)
+{
+	device_t dev;
+	struct resource *res;
+
+	memset((void *)gvars, 0, GLOBAL_VARS_SIZE);
+
+	gvars->pcba = EXT_CONF_BASE_ADDRESS;
+	dev = dev_find_slot(0, PCI_DEVFN(0,0));
+	res = probe_resource(dev, 0x1C);
+	if( res )
+		gvars->pcba = res->base;
+
+	gvars->mpen = 1;
+}
+
+static void acpi_create_my_hpet(acpi_hpet_t *hpet)
+{
+#define HPET_ADDR  0xfed00000ULL
+	acpi_header_t *header=&(hpet->header);
+	acpi_addr_t *addr=&(hpet->addr);
+
+	memset((void *)hpet, 0, sizeof(acpi_hpet_t));
+
+	/* fill out header fields */
+	memcpy(header->signature, "HPET", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->length = sizeof(acpi_hpet_t);
+	header->revision = 1;
+
+	/* fill out HPET address */
+	addr->space_id		= 0; /* Memory */
+	addr->bit_width		= 64;
+	addr->bit_offset	= 0;
+	addr->addrl		= HPET_ADDR & 0xffffffff;
+	addr->addrh		= HPET_ADDR >> 32;
+
+	hpet->id = 0x43538301;
+	hpet->number	= 0;
+	hpet->min_tick  = 20;
+
+	header->checksum	= acpi_checksum((void *)hpet, sizeof(acpi_hpet_t));
+}
 
 #if DUMP_ACPI_TABLES == 1
 static void dump_mem(u32 start, u32 end)
 {
-
 	u32 i;
 	print_debug("dump_mem:");
 	for (i = start; i < end; i++) {
@@ -62,7 +126,17 @@
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-	/* Just a dummy */
+	struct resource *res;
+	resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default
+	
+	device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
+	// we report mmconf base
+	res = probe_resource(dev, 0x1C);
+	if( res )
+		mmconf_base = res->base;
+		
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ?
+
 	return current;
 }
 
@@ -74,20 +148,23 @@
 	/* Write SB600 IOAPIC, only one */
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
 					   IO_APIC_ADDR, 0);
-
+#if CONFIG_LINT01_CONVERSION == 0
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 						current, 0, 0, 2, 0);
+
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
-	/* 0: mean bus 0--->ISA */
+						current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+#else
+						/* 0: mean bus 0--->ISA */
 	/* 0: PIC 0 */
 	/* 2: APIC 2 */
 	/* 5 mean: 0101 --> Edige-triggered, Active high */
 
 	/* create all subtables for processors */
-	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	current = acpi_create_madt_lapic_nmis(current, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
 	/* 1: LINT1 connect to NMI */
-
+	set_nbcfg_enable_bits(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x68, 1 << 16, 1 << 16); // Local Interrupt Conversion Enable
+#endif
 	return current;
 }
 
@@ -97,99 +174,126 @@
 	return (unsigned long) (acpigen_get_current());
 }
 
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
+	int i;
+	
 	acpi_rsdp_t *rsdp;
 	acpi_rsdt_t *rsdt;
+	acpi_srat_t *srat;
+	acpi_xsdt_t *xsdt;
+	acpi_mcfg_t *mcfg;
 	acpi_hpet_t *hpet;
 	acpi_madt_t *madt;
 	acpi_fadt_t *fadt;
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
-
+	
 	get_bus_conf();		/* it will get sblk, pci1234, hcdn, and sbdn */
 
 	/* Align ACPI tables to 16byte */
-	start = (start + 0x0f) & -0x10;
 	current = start;
+	ALIGN_CURRENT;
 
 	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
 	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;	
 	rsdt = (acpi_rsdt_t *) current;
 	current += sizeof(acpi_rsdt_t);
-
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+	
 	/* clear all table memory */
 	memset((void *)start, 0, current - start);
 
-	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
 	acpi_write_rsdt(rsdt);
-
+	acpi_write_xsdt(xsdt);
 	/*
 	 * We explicitly add these tables later on:
 	 */
-	/* If we want to use HPET Timers Linux wants an MADT */
+	current = ALIGN(current, 64);
+	/* FACS */
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	acpi_create_facs(facs);
+	current += sizeof(acpi_facs_t);
+
+	 /* HPET */
 	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
+	acpi_create_my_hpet(hpet);
 	current += sizeof(acpi_hpet_t);
-	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
-
+	
+	/* If we want to use HPET Timers Linux wants an MADT */
 	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
+	/* MCFG */
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdp, mcfg);	
+	
 	/* SSDT */
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
-
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, "COREBOOT");
 	current += ssdt->length;
-	acpi_add_table(rsdp, ssdt);
-
-	/* FACS */
-	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
-	facs = (acpi_facs_t *) current;
-	current += sizeof(acpi_facs_t);
-	acpi_create_facs(facs);
-
+	acpi_add_table(rsdp, ssdt);	
+	
 	/* DSDT */
 	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *)current;
 	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
 	current += dsdt->length;
 	memcpy(dsdt, &AmlCode, dsdt->length);
-	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+
+	/* Pack gvars into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xBADEAFFE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up globals in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			*(u32*)(((u32)dsdt) + i) = current; 
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_write_gvars((global_vars_t *)current);
+	current += GLOBAL_VARS_SIZE;
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);	
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);	
+
 	/* FADT */
 	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
-
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-#if DUMP_ACPI_TABLES == 1
-	printk(BIOS_DEBUG, "rsdp\n");
-	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
-
-	printk(BIOS_DEBUG, "rsdt\n");
-	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+	/* SRAT */
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	acpi_add_table(rsdp, srat);
 
-	printk(BIOS_DEBUG, "madt\n");
-	dump_mem(madt, ((void *)madt) + madt->header.length);
-
-	printk(BIOS_DEBUG, "ssdt\n");
-	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
-
-	printk(BIOS_DEBUG, "fadt\n");
-	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
-#endif
+	printk(BIOS_DEBUG, "current = %lx\n", current);
 
 	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/chip.h
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/chip.h	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/chip.h	Wed May 11 09:47:43 2011	(r6567)
@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,4 +20,10 @@
  */
 
 extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+
+struct mainboard_config
+{
+	u32 uma_size;			/* How many UMA should be used in memory for TOP. */
+	unsigned int plx_present : 1;
+};
+

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/cmos.layout	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/cmos.layout	Wed May 11 09:47:43 2011	(r6567)
@@ -2,6 +2,8 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
+## Copyright (C) 2010 Siemens AG, Inc.
+## (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -32,9 +34,11 @@
 #56           8       r       0        day_of_month
 #64           8       r       0        month
 #72           8       r       0        year
+# =======================================================
 #80           4       r       0        rate_select
 #84           3       r       0        REF_Clock
 #87           1       r       0        UIP
+# =======================================================
 #88           1       r       0        auto_switch_DST
 #89           1       r       0        24_hour_mode
 #90           1       r       0        binary_values_enable
@@ -43,28 +47,44 @@
 #93           1       r       0        alarm_interrupt_enable
 #94           1       r       0        periodic_interrupt_enable
 #95           1       r       0        disable_clock_updates
+# ========================================================
 #96         288       r       0        temporary_filler
 0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-385          1       e       4        last_boot
-386          1       e       1        ECC_memory
+# ========================================================
+#384          1       e       4        unused
+385          1       r       4        last_boot
+#386          1       r       1        unused
+387          1       e       16       cmos_defaults_loaded
 388          4       r       0        reboot_bits
 392          3       e       5        baud_rate
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
+#395          1       r       1        unused
+#396          1       r       1        unused
+#397          2       r       8        unused
 399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-416          4       e       7        boot_first
-420          4       e       7        boot_second
-424          4       e       7        boot_third
-428          4       h       0        boot_index
-432          8       h       0        boot_countdown
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-728        256       h       0        user_data
+#400          8       r       18       reserved
+408          4       e       6        debug_level
+412          1       e       1        power_on_after_fail
+#413          1       r       1        unused
+414          1       e       17       sata_mode
+415          1       e       1        nmi
+416          1       e       1        cpu_fan_control
+417          1       e       1        chassis_fan_control
+418          1       e       13       cpu_fan_polarity
+419          1       e       13       chassis_fan_polarity
+420          4       e       14       cpu_t_min
+424          4       e       14       cpu_t_max
+428          4       e       15       cpu_dutycycle_min
+432          4       e       15       cpu_dutycycle_max
+436          4       e       14       chassis_t_min
+440          4       e       14       chassis_t_max
+444          4       e       15       chassis_dutycycle_min
+448          4       e       15       chassis_dutycycle_max
+#452          4       r       9        unused
+456          4       e       10       boot_delay
+460		     4       e       11       lcd_panel_id
+#===========================================================
+464          512     s       0        boot_devices
+976          8       h       0        boot_default
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
 1000        24       r       0        amd_reserved
@@ -88,30 +108,100 @@
 5     5     4800
 5     6     2400
 5     7     1200
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Network
-7     1     HDD
-7     2     Floppy
-7     8     Fallback_Network
-7     9     Fallback_HDD
-7     10    Fallback_Floppy
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+#7     0     Network
+#7     1     HDD
+#7     2     Floppy
+#7     8     Fallback_Network
+#7     9     Fallback_HDD
+#7     10    Fallback_Floppy
 #7     3     ROM
 8     0     DDR400
 8     1     DDR333
 8     2     DDR266
 8     3     DDR200
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
+# boot delay
+10    0     off
+10    1     1s
+10    2     2s
+10    3     3s
+10    4     4s
+10    5     5s
+10    6     6s
+10    7     7s
+10    8     8s
+10    9     9s
+10    10    10s
+# LCD Panel ID
+11	0	no_panel
+11	1	1024x768_65MHz_Dual
+11	2	1920x1200_162MHz
+11	3	1600x1200_162MHz
+11	4	1024x768_65MHz
+11	5	1400x1050_108MHz
+11	6	1680x1050_119MHz
+11	7	2048x1536_164MHz
+11	8	1280x1024_108MHz
+11	9	1366x768_86MHz_chimei_V32B1L01
+# TV Standard
+#12	0	NTSC
+#12	1	PAL
+#12	2	PALM
+#12	3	PAL60
+#12	4	NTSCJ
+#12	5	PALCN
+#12	6	PALN
+#12	9	SCART-RGB
+#12	15	no_tv
+# CPU/Chassis FAN Control: polarity
+13  0   Active_high
+13  1   Active_low
+# Temperature ?C
+14  0   30
+14  1   35
+14  2   40
+14  3   45
+14  4   50
+14  5   55
+14  6   60
+14  7   65
+14  8   70
+14  9   75
+14  10  80
+14  11  85
+14  12  90
+14  13  95
+14  14  100
+# Dutycycle %
+15  0   25%
+15  1   30%
+15  2   35%
+15  3   40%
+15  4   45%
+15  5   50%
+15  6   55%
+15  7   60%
+15  8   65%
+15  9   70%
+15  10  75%
+15  11  80%
+15  12  85%
+15  13  90%
+15  14  95%
+15  15  100%
+# cmos_defaults_loaded
+16  0   No
+16  1   Yes
+# sata_mode
+17  0   AHCI
+17  1   IDE
+# reserved
+18  32  2000
+# ==============================
 checksums
 
 checksum 392 983 984

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/devicetree.cb	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/devicetree.cb	Wed May 11 09:47:43 2011	(r6567)
@@ -15,30 +15,41 @@
 		end
 	end
 	device pci_domain 0 on
-		subsystemid 0x1022 0x3050 inherit
+		subsystemid 0x110a 0x4076 inherit	
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
-					device pci 0.0 on end # HT  	0x7910
+					device pci 0.0 on  # Northbridge configuration space (0x7910)
+					end
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						device pci 5.0 on end	# Internal Graphics 0x791F
+						device pci 5.0 on # Internal Graphics 0x791F
+						end
+						device pci 5.2 on # 
+						end
+					end
+					device pci 2.0 on  #  PCIE P2P bridge 0x7913  (external GFX-port0)
+					end
+					device pci 3.0 off  # PCIE P2P bridge 0x791b (external GFX-port1)
+					end
+					device pci 4.0 on  #  PCIE P2P bridge port 0 (0x7914)
+					end
+					device pci 5.0 on  #  PCIE P2P bridge port 1  (0x7915)
+					end
+					device pci 6.0 on  #  PCIE P2P bridge port 2  (0x7916)
+					end
+					device pci 7.0 on  #  PCIE P2P bridge port 3  (0x7917)
+					end
+					device pci 8.0 off  # NB/SB Link P2P bridge
 					end
-					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x7914
-					device pci 5.0 on end # PCIE P2P bridge 0x7915
-					device pci 6.0 on end # PCIE P2P bridge 0x7916
-					device pci 7.0 on end # PCIE P2P bridge 0x7917
-					device pci 8.0 off end # NB/SB Link P2P bridge
 					register "gpp_configuration" = "4"
 					register "port_enable" = "0xfc"
 					register "gfx_dev2_dev3" = "1"
 					register "gfx_dual_slot" = "0"
 					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "0"
+					register "gfx_tmds" = "1" # needed for DVI output, but this results in a conflict if PLX installed !
 					register "gfx_compliance" = "0"
 					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
+					register "gfx_link_width" = "0" # 4 (0x8) if PLX installed
 				end
 				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
 					device pci 12.0 on end # SATA  0x4380
@@ -48,7 +59,7 @@
 					device pci 13.3 on end # USB   0x438a
 					device pci 13.4 on end # USB   0x438b
 					device pci 13.5 on end # USB 2 0x4386
-	 				device pci 14.0 on # SM        0x4385
+	 				device pci 14.0 on     # SM    0x4385
 						chip drivers/generic/generic #dimm 0-0-0
 							device i2c 50 on end
 						end
@@ -75,7 +86,7 @@
 								io 0x60 = 0x3f8
 								irq 0x70 = 4
 							end
-							device pnp 2e.2 off #  Com2
+							device pnp 2e.2 on #  Com2
 								io 0x60 = 0x2f8
 								irq 0x70 = 3
 							end
@@ -107,7 +118,9 @@
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # ACI 0x4382
 					device pci 14.6 on end # MCI 0x438e
-					register "hda_viddid" = "0x10ec0882"
+#						register "ide0_enable" = "1"
+#						register "sata0_enable" = "1"
+						register "hda_viddid" = "0x10ec0882"
 				end	#southbridge/amd/sb600
 			end #  device pci 18.0
 

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/dsdt.asl	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/dsdt.asl	Wed May 11 09:47:43 2011	(r6567)
@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,30 +19,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* DefinitionBlock Statement */
-DefinitionBlock (
-	"DSDT.AML",           /* Output filename */
-	"DSDT",                 /* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	"AMD   ",               /* OEMID */
-	"DBM690T ",          /* TABLE ID */
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include "../../../arch/x86/acpi/debug.asl" */		/* Include global debug methods if needed */
-
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
+{
 	/* Data to be patched by the BIOS during POST */
-	/* FIXME the patching is not done yet! */
 	/* Memory related values */
 	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-	Name(PBLN, 0x0)	/* Length of BIOS area */
-
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
-	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
 	/* USB overcurrent mapping pins.   */
 	Name(UOM0, 0)
 	Name(UOM1, 2)
@@ -52,11 +37,9 @@
 	Name(UOM7, 2)
 	Name(UOM8, 6)
 	Name(UOM9, 6)
-
-	/* Some global data */
-	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-	Name(OSV, Ones)	/* Assume nothing */
-	Name(PMOD, One)	/* Assume APIC */
+	
+	Name(DSEN, 1)		// Display Output Switching Enable 
+	// Power notification
 
 	/* PIC IRQ mapping registers, C00h-C01h */
 	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
@@ -69,11 +52,8 @@
 		PINB, 0x00000008,	/* Index 1 */
 		PINC, 0x00000008,	/* Index 2 */
 		PIND, 0x00000008,	/* Index 3 */
-		AINT, 0x00000008,	/* Index 4 */
-		SINT, 0x00000008,	/*  Index 5 */
-		, 0x00000008,	             /* Index 6 */
-		AAUD, 0x00000008,	/* Index 7 */
-		AMOD, 0x00000008,	/* Index 8 */
+		SINT, 0x00000008,	/*  Index 4 */
+		Offset(0x09),
 		PINE, 0x00000008,	/* Index 9 */
 		PINF, 0x00000008,	/* Index A */
 		PING, 0x00000008,	/* Index B */
@@ -263,16 +243,26 @@
 		PWDA, 1,
 	}
 
-	Scope(\_SB) {
+	OperationRegion (GVAR, SystemMemory, 0xBADEAFFE, 0x100)
+	Field (GVAR, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x00),
+		OSYS,	16,
+		LINX,	16,
+		PCBA,   32,
+		MPEN,	8
+	}
+	
+	Name (IOLM,0xe0000000)
+	
+#include "acpi/platform.asl"	
 
+	Scope(\_SB) {
+	
 		/* PCIe Configuration Space for 16 busses */
-		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x2000000) /* PCIe reserved space for 31 busses */
 			Field(PCFG, ByteAcc, NoLock, Preserve) {
-			/* Byte offsets are computed using the following technique:
-			   * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-			   * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-			*/
-			Offset(0x00090024),	/* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+			Offset(0x00090024),	/* Byte offset to SATA BAR5 register 24h - Bus 0, Device 18, Function 0 */
 			STB5, 32,
 			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 			PT0D, 1,
@@ -296,9 +286,9 @@
 			,14,
 			P92E, 1,		/* Port92 decode enable */
 		}
-
-		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-			Field(SB5, AnyAcc, NoLock, Preserve)
+		
+		OperationRegion(BAR5, SystemMemory, STB5, 0x1000)
+			Field(BAR5, AnyAcc, NoLock, Preserve)
 			{
 			/* Port 0 */
 			Offset(0x120),		/* Port 0 Task file status */
@@ -369,794 +359,113 @@
 			P3PR, 1,
 		}
 	}
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-
-		Method(CkOT, 0){
-
-			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
-
-			if(CondRefOf(\_OSI,Local1))
-			{
-				Store(1, OSTP)                /* Assume some form of XP */
-				if (\_OSI("Windows 2006"))      /* Vista */
-				{
-					Store(2, OSTP)
-				}
-			} else {
-				If(WCMP(\_OS,"Linux")) {
-					Store(3, OSTP)            /* Linux */
-				} Else {
-					Store(4, OSTP)            /* Gotta be WinCE */
-				}
-			}
-			Return(OSTP)
-		}
-
-		Method(_PIC, 0x01, NotSerialized)
-		{
-			If (Arg0)
-			{
-				\_SB.CIRQ()
-			}
-			Store(Arg0, PMOD)
-		}
-
-		Method(CIRQ, 0x00, NotSerialized)
-		{
-			Store(0, PINA)
-			Store(0, PINB)
-			Store(0, PINC)
-			Store(0, PIND)
-			Store(0, PINE)
-			Store(0, PINF)
-			Store(0, PING)
-			Store(0, PINH)
-		}
-
-		Name(IRQB, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Shared){15}
-		})
-
-		Name(IRQP, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
-		})
-
-		Name(PITF, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){9}
-		})
-
-		Device(INTA) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 1)
-
-			Method(_STA, 0) {
-				if (PINA) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTA._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
-				Store(0, PINA)
-			} /* End Method(_SB.INTA._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTA._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINA, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTA._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINA)
-			} /* End Method(_SB.INTA._SRS) */
-		} /* End Device(INTA) */
-
-		Device(INTB) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 2)
-
-			Method(_STA, 0) {
-				if (PINB) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTB._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
-				Store(0, PINB)
-			} /* End Method(_SB.INTB._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTB._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINB, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTB._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINB)
-			} /* End Method(_SB.INTB._SRS) */
-		} /* End Device(INTB)  */
-
-		Device(INTC) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 3)
-
-			Method(_STA, 0) {
-				if (PINC) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTC._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
-				Store(0, PINC)
-			} /* End Method(_SB.INTC._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTC._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINC, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTC._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINC)
-			} /* End Method(_SB.INTC._SRS) */
-		} /* End Device(INTC)  */
-
-		Device(INTD) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 4)
-
-			Method(_STA, 0) {
-				if (PIND) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTD._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
-				Store(0, PIND)
-			} /* End Method(_SB.INTD._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTD._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PIND, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTD._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PIND)
-			} /* End Method(_SB.INTD._SRS) */
-		} /* End Device(INTD)  */
-
-		Device(INTE) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 5)
-
-			Method(_STA, 0) {
-				if (PINE) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTE._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
-				Store(0, PINE)
-			} /* End Method(_SB.INTE._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTE._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINE, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTE._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINE)
-			} /* End Method(_SB.INTE._SRS) */
-		} /* End Device(INTE)  */
-
-		Device(INTF) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 6)
-
-			Method(_STA, 0) {
-				if (PINF) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTF._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
-				Store(0, PINF)
-			} /* End Method(_SB.INTF._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
-				Return(PITF)
-			} /* Method(_SB.INTF._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINF, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTF._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINF)
-			} /*  End Method(_SB.INTF._SRS) */
-		} /* End Device(INTF)  */
-
-		Device(INTG) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 7)
-
-			Method(_STA, 0) {
-				if (PING) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTG._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
-				Store(0, PING)
-			} /* End Method(_SB.INTG._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PING, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PING)
-			} /* End Method(_SB.INTG._SRS)  */
-		} /* End Device(INTG)  */
-
-		Device(INTH) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 8)
-
-			Method(_STA, 0) {
-				if (PINH) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTH._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
-				Store(0, PINH)
-			} /* End Method(_SB.INTH._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINH, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINH)
-			} /* End Method(_SB.INTH._SRS)  */
-		} /* End Device(INTH)   */
-
-	}   /* End Scope(_SB)  */
-
-
-	/* Supported sleep states: */
-	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
-
-	If (LAnd(SSFG, 0x01)) {
-		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
-	}
-	If (LAnd(SSFG, 0x02)) {
-		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
-	}
-	If (LAnd(SSFG, 0x04)) {
-		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
-	}
-	If (LAnd(SSFG, 0x08)) {
-		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
-	}
-
-	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
-
-	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
-	Name(CSMS, 0)			/* Current System State */
-
-	/* Wake status package */
-	Name(WKST,Package(){Zero, Zero})
-
-	/*
-	* \_PTS - Prepare to Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-	*
-	* Exit:
-	*		-none-
-	*
-	* The _PTS control method is executed at the beginning of the sleep process
-	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
-	* control method may be executed a relatively long time before entering the
-	* sleep state and the OS may abort	the operation without notification to
-	* the ACPI driver.  This method cannot modify the configuration or power
-	* state of any device in the system.
-	*/
-	Method(\_PTS, 1) {
-		/* DBGO("\\_PTS\n") */
-		/* DBGO("From S0 to S") */
-		/* DBGO(Arg0) */
-		/* DBGO("\n") */
-
-		/* Don't allow PCIRST# to reset USB */
-		if (LEqual(Arg0,3)){
-			Store(0,URRE)
-		}
-
-		/* Clear sleep SMI status flag and enable sleep SMI trap. */
-		/*Store(One, CSSM)
-		Store(One, SSEN)*/
-
-		/* On older chips, clear PciExpWakeDisEn */
-		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
-		*}
-		*/
-
-		/* Clear wake status structure. */
-		Store(0, Index(WKST,0))
-		Store(0, Index(WKST,1))
-		\_SB.PCI0.SIOS (Arg0)
-	} /* End Method(\_PTS) */
-
-	/*
-	*  The following method results in a "not a valid reserved NameSeg"
-	*  warning so I have commented it out for the duration.  It isn't
-	*  used, so it could be removed.
-	*
-	*
-	*  	\_GTS OEM Going To Sleep method
-	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*  	Exit:
-	*  		-none-
-	*
-	*  Method(\_GTS, 1) {
-	*  DBGO("\\_GTS\n")
-	*  DBGO("From S0 to S")
-	*  DBGO(Arg0)
-	*  DBGO("\n")
-	*  }
-	*/
-
-	/*
-	*	\_BFS OEM Back From Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		-none-
-	*/
-	Method(\_BFS, 1) {
-		/* DBGO("\\_BFS\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-	}
-
-	/*
-	*  \_WAK System Wake method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		Return package of 2 DWords
-	*		Dword 1 - Status
-	*			0x00000000	wake succeeded
-	*			0x00000001	Wake was signaled but failed due to lack of power
-	*			0x00000002	Wake was signaled but failed due to thermal condition
-	*		Dword 2 - Power Supply state
-	*			if non-zero the effective S-state the power supply entered
-	*/
-	Method(\_WAK, 1) {
-		/* DBGO("\\_WAK\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-
-		/* Re-enable HPET */
-		Store(1,HPDE)
-
-		/* Restore PCIRST# so it resets USB */
-		if (LEqual(Arg0,3)){
-			Store(1,URRE)
-		}
-
-		/* Arbitrarily clear PciExpWakeStatus */
-		Store(PWST, PWST)
-
-		/* if(DeRefOf(Index(WKST,0))) {
-		*	Store(0, Index(WKST,1))
-		* } else {
-		*	Store(Arg0, Index(WKST,1))
-		* }
-		*/
-		\_SB.PCI0.SIOW (Arg0)
-		Return(WKST)
-	} /* End Method(\_WAK) */
-
-	Scope(\_GPE) {	/* Start Scope GPE */
-		/*  General event 0  */
-		/* Method(_L00) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 1  */
-		/* Method(_L01) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 2  */
-		/* Method(_L02) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 3  */
-		Method(_L03) {
-			/* DBGO("\\_GPE\\_L00\n") */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  General event 4  */
-		/* Method(_L04) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 5  */
-		/* Method(_L05) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 6 - Used for GPM6, moved to USB.asl */
-		/* Method(_L06) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 7 - Used for GPM7, moved to USB.asl */
-		/* Method(_L07) {
-		*	DBGO("\\_GPE\\_L07\n")
-		* }
-		*/
-
-		/*  Legacy PM event  */
-		Method(_L08) {
-			/* DBGO("\\_GPE\\_L08\n") */
-		}
-
-		/*  Temp warning (TWarn) event  */
-		Method(_L09) {
-			/* DBGO("\\_GPE\\_L09\n") */
-			Notify (\_TZ.TZ00, 0x80)
-		}
-
-		/*  Reserved  */
-		/* Method(_L0A) {
-		*	DBGO("\\_GPE\\_L0A\n")
-		* }
-		*/
-
-		/*  USB controller PME#  */
-		Method(_L0B) {
-			/* DBGO("\\_GPE\\_L0B\n") */
-			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  AC97 controller PME#  */
-		/* Method(_L0C) {
-		*	DBGO("\\_GPE\\_L0C\n")
-		* }
-		*/
-
-		/*  OtherTherm PME#  */
-		/* Method(_L0D) {
-		*	DBGO("\\_GPE\\_L0D\n")
-		* }
-		*/
-
-		/*  GPM9 SCI event - Moved to USB.asl */
-		/* Method(_L0E) {
-		*	DBGO("\\_GPE\\_L0E\n")
-		* }
-		*/
-
-		/*  PCIe HotPlug event  */
-		/* Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
-		* }
-		*/
-
-		/*  ExtEvent0 SCI event  */
-		Method(_L10) {
-			/* DBGO("\\_GPE\\_L10\n") */
-		}
-
-
-		/*  ExtEvent1 SCI event  */
-		Method(_L11) {
-			/* DBGO("\\_GPE\\_L11\n") */
-		}
-
-		/*  PCIe PME# event  */
-		/* Method(_L12) {
-		*	DBGO("\\_GPE\\_L12\n")
-		* }
-		*/
-
-		/*  GPM0 SCI event - Moved to USB.asl */
-		/* Method(_L13) {
-		* 	DBGO("\\_GPE\\_L13\n")
-		* }
-		*/
-
-		/*  GPM1 SCI event - Moved to USB.asl */
-		/* Method(_L14) {
-		* 	DBGO("\\_GPE\\_L14\n")
-		* }
-		*/
-
-		/*  GPM2 SCI event - Moved to USB.asl */
-		/* Method(_L15) {
-		* 	DBGO("\\_GPE\\_L15\n")
-		* }
-		*/
-
-		/*  GPM3 SCI event - Moved to USB.asl */
-		/* Method(_L16) {
-		*	DBGO("\\_GPE\\_L16\n")
-		* }
-		*/
-
-		/*  GPM8 SCI event - Moved to USB.asl */
-		/* Method(_L17) {
-		* 	DBGO("\\_GPE\\_L17\n")
-		* }
-		*/
-
-		/*  GPIO0 or GEvent8 event  */
-		Method(_L18) {
-			/* DBGO("\\_GPE\\_L18\n") */
-			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  GPM4 SCI event - Moved to USB.asl */
-		/* Method(_L19) {
-		* 	DBGO("\\_GPE\\_L19\n")
-		* }
-		*/
-
-		/*  GPM5 SCI event - Moved to USB.asl */
-		/* Method(_L1A) {
-		*	DBGO("\\_GPE\\_L1A\n")
-		* }
-		*/
-
-		/*  Azalia SCI event  */
-		Method(_L1B) {
-			/* DBGO("\\_GPE\\_L1B\n") */
-			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  GPM6 SCI event - Reassigned to _L06 */
-		/* Method(_L1C) {
-		*	DBGO("\\_GPE\\_L1C\n")
-		* }
-		*/
-
-		/*  GPM7 SCI event - Reassigned to _L07 */
-		/* Method(_L1D) {
-		*	DBGO("\\_GPE\\_L1D\n")
-		* }
-		*/
-
-		/*  GPIO2 or GPIO66 SCI event  */
-		/* Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
-		* }
-		*/
-
-		/*  SATA SCI event - Moved to sata.asl */
-		/* Method(_L1F) {
-		*	 DBGO("\\_GPE\\_L1F\n")
-		* }
-		*/
-
-	} 	/* End Scope GPE */
-
-	#include "acpi/usb.asl"
+#include "acpi/event.asl"	
+#include "acpi/routing.asl"
+#include "acpi/usb.asl"
 
 	/* South Bridge */
-	Scope(\_SB) { /* Start \_SB scope */
-		#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+	Scope(\_SB)
+	{
+		/* Start \_SB scope */
+	
+#include "acpi/globutil.asl"
 
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
 		/*  _SB.PCI0 */
 		/* Note: Only need HID on Primary Bus */
-		Device(PCI0) {
+		Device(PCI0)
+		{
+			External (MMIO)
 			External (TOM1)
-			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+			External (TOM2)
+
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			
 			Method(_BBN, 0) { /* Bus number = 0 */
 				Return(0)
-			}
+			}			
+
 			Method(_STA, 0) {
 				/* DBGO("\\_SB\\PCI0\\_STA\n") */
 				Return(0x0B)     /* Status is visible */
 			}
+	
+            Device (MEMR)
+            {
+                Name (_HID, EisaId ("PNP0C02"))
+                Name (MEM1, ResourceTemplate ()
+                {
+                    Memory32Fixed (ReadWrite,
+                        0x00000000,         // Address Base
+                        0x00000000,         // Address Length
+                        _Y1A)
+                    Memory32Fixed (ReadWrite,
+                        0x00000000,         // Address Base
+                        0x00000000,         // Address Length
+                        _Y1B)
+                })
+                Method (_CRS, 0, NotSerialized)
+                {
+                    CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._BAS, MB01)
+                    CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._LEN, ML01)
+                    CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._BAS, MB02)
+                    CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02)
+                    If (PCIF)
+                    {
+                        Store (0xFEC00000, MB01)
+                        Store (0xFEE00000, MB02)
+                        Store (0x1000, ML01)
+                        Store (0x1000, ML02)
+                    }
+
+                    Return (MEM1)
+                }
+            }
 
 			Method(_PRT,0) {
-				If(PMOD){ Return(APR0) }   /* APIC mode */
+				If(PCIF){ Return(APR0) }   /* APIC mode */
 				Return (PR0)                  /* PIC Mode */
 			} /* end _PRT */
-
+		
+            OperationRegion (BAR1, PCI_Config, 0x14, 0x04)
+            Field (BAR1, ByteAcc, NoLock, Preserve)
+            {
+                Z009,   32
+            }
+			
 			/* Describe the Northbridge devices */
 			Device(AMRT) {
 				Name(_ADR, 0x00000000)
 			} /* end AMRT */
-
+			
 			/* The internal GFX bridge */
 			Device(AGPB) {
 				Name(_ADR, 0x00010000)
 				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					Return (APR1)
-				}
+				Method(_PRT,0) { Return (APR1) }
+
+				Device (VGA)
+                {
+                    Name (_ADR, 0x00050000)
+					Method (_DOS, 1)
+					{
+						/* Windows 2000 and Windows XP call _DOS to enable/disable
+						 * Display Output Switching during init and while a switch
+						 * is already active
+						*/
+						Store (And(Arg0, 7), DSEN)
+					}
+                    Method (_STA, 0, NotSerialized)
+                    {
+                        Return (0x0F)
+                    }
+                }
 			}  /* end AGPB */
 
 			/* The external GFX bridge */
@@ -1164,18 +473,18 @@
 				Name(_ADR, 0x00020000)
 				Name(_PRW, Package() {0x18, 4})
 				Method(_PRT,0) {
-					If(PMOD){ Return(APS2) }   /* APIC mode */
+					If(PCIF){ Return(APS2) }   /* APIC mode */
 					Return (PS2)                  /* PIC Mode */
 				} /* end _PRT */
 			} /* end PBR2 */
 
-			/* Dev3 is also an external GFX bridge, not used in Herring */
+			/* Dev3 is also an external GFX bridge */
 
 			Device(PBR4) {
 				Name(_ADR, 0x00040000)
 				Name(_PRW, Package() {0x18, 4})
 				Method(_PRT,0) {
-					If(PMOD){ Return(APS4) }   /* APIC mode */
+					If(PCIF){ Return(APS4) }   /* APIC mode */
 					Return (PS4)                  /* PIC Mode */
 				} /* end _PRT */
 			} /* end PBR4 */
@@ -1184,8 +493,8 @@
 				Name(_ADR, 0x00050000)
 				Name(_PRW, Package() {0x18, 4})
 				Method(_PRT,0) {
-					If(PMOD){ Return(APS5) }   /* APIC mode */
-					Return (PS5)                  /* PIC Mode */
+					If(PCIF){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */  
 				} /* end _PRT */
 			} /* end PBR5 */
 
@@ -1193,7 +502,7 @@
 				Name(_ADR, 0x00060000)
 				Name(_PRW, Package() {0x18, 4})
 				Method(_PRT,0) {
-					If(PMOD){ Return(APS6) }   /* APIC mode */
+					If(PCIF){ Return(APS6) }   /* APIC mode */
 					Return (PS6)                  /* PIC Mode */
 				} /* end _PRT */
 			} /* end PBR6 */
@@ -1203,27 +512,26 @@
 				Name(_ADR, 0x00070000)
 				Name(_PRW, Package() {0x18, 4})
 				Method(_PRT,0) {
-					If(PMOD){ Return(APS7) }   /* APIC mode */
-					Return (PS7)                  /* PIC Mode */
+					If(PCIF){ Return(APS7) }   /* APIC mode */
+					Return (PS7)               /* PIC Mode */
 				} /* end _PRT */
 			} /* end PBR7 */
 
-
-			/* PCI slot 1, 2, 3 */
+			/* PCI slot 1 */
 			Device(PIBR) {
 				Name(_ADR, 0x00140004)
-				Name(_PRW, Package() {0x18, 4})
-
+				Name(_PRW, Package() {4, 5}) //  Phoenix doeas it so 
 				Method(_PRT, 0) {
-					Return (PCIB)
+					If(PCIF){ Return(AP2P) }  /* APIC Mode */
+					Return (PCIB)             /* PIC Mode */
 				}
 			}
 
 			/* Describe the Southbridge devices */
-			Device(STCR) {
+			Device(SATA) {
 				Name(_ADR, 0x00120000)
-				#include "acpi/sata.asl"
-			} /* end STCR */
+#include "acpi/sata.asl" 
+			} /* end SATA */
 
 			Device(UOH1) {
 				Name(_ADR, 0x00130000)
@@ -1292,7 +600,7 @@
 				}
 
 				Method(_INI) {
-					If(LEqual(OSTP,3)){   /* If we are running Linux */
+					If(LEqual(LINX,1)){   /* If we are running Linux */
 						Store(zero, NSEN)
 						Store(one, NSDO)
 						Store(one, NSDI)
@@ -1300,18 +608,350 @@
 				}
 			} /* end AZHD */
 
-			Device(LIBR) {
-				Name(_ADR, 0x00140003)
-				/* Method(_INI) {
-				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
-				} */ /* End Method(_SB.SBRDG._INI) */
+			Device(LPC0) 
+			{
+                Name (_ADR, 0x00140003)
+                Mutex (PSMX, 0x00)
+				
+				/* PIC IRQ mapping registers, C00h-C01h */
+				OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+				Field(PRQM, ByteAcc, NoLock, Preserve) {
+					PRQI, 0x00000008,
+					PRQD, 0x00000008,  /* Offset: 1h */
+				}
+	
+				IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+					PINA, 0x00000008,	/* Index 0  */
+					PINB, 0x00000008,	/* Index 1 */
+					PINC, 0x00000008,	/* Index 2 */
+					PIND, 0x00000008,	/* Index 3 */
+					SINT, 0x00000008,	/*  Index 4 */
+					Offset(0x09),
+					PINE, 0x00000008,	/* Index 9 */
+					PINF, 0x00000008,	/* Index A */
+					PING, 0x00000008,	/* Index B */
+					PINH, 0x00000008,	/* Index C */
+				}
+				
+				Method(CIRQ, 0x00, NotSerialized)
+				{
+					Store(0, PINA)
+					Store(0, PINB)
+					Store(0, PINC)
+					Store(0, PIND)
+					Store(0, SINT)
+					Store(0, PINE)
+					Store(0, PINF)
+					Store(0, PING)
+					Store(0, PINH)
+				}
+
+				Name(IRQB, ResourceTemplate(){
+					IRQ(Level,ActiveLow,Shared){10,11}
+				})
+
+				Name(IRQP, ResourceTemplate(){
+					IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7}
+				})
+				
+				Name(PITF, ResourceTemplate(){
+					IRQ(Level,ActiveLow,Exclusive){9}
+				})	
+				
+				Device(INTA) {
+					Name(_HID, EISAID("PNP0C0F"))
+					Name(_UID, 1)
+
+					Method(_STA, 0) {
+						if (PINA) {
+							Return(0x0B) /* sata is invisible */
+						} else {
+							Return(0x09) /* sata is disabled */
+						}
+					} /* End Method(_SB.INTA._STA) */
+
+					Method(_DIS ,0) {
+						Store(0, PINA)
+					} /* End Method(_SB.INTA._DIS) */
+
+					Method(_PRS ,0) {
+						Return(IRQB) // Return(IRQP)
+					} /* Method(_SB.INTA._PRS) */
+
+					Method(_CRS ,0) {
+						Store (IRQB, Local0) // 
+						CreateWordField(Local0, 0x1, IRQ0)
+						ShiftLeft(1, PINA, IRQ0)
+						Return(Local0)
+					} /* Method(_SB.INTA._CRS) */
+					Method(_SRS, 1) {
+						CreateWordField(ARG0, 1, IRQ0)
+						/* Use lowest available IRQ */
+						FindSetRightBit(IRQ0, Local0)
+						Decrement (Local0)
+						Store(Local0, PINA)
+					} /* End Method(_SB.INTA._SRS) */
+				} /* End Device(INTA) */
+
+				Device(INTB) {
+					Name(_HID, EISAID("PNP0C0F"))
+					Name(_UID, 2)
+
+					Method(_STA, 0) {
+						if (PINB) {
+							Return(0x0B) /* sata is invisible */
+						} else {
+							Return(0x09) /* sata is disabled */
+						}
+					} /* End Method(_SB.INTB._STA) */
+
+					Method(_DIS ,0) {
+						Store(0, PINB)
+					} /* End Method(_SB.INTB._DIS) */
+
+					Method(_PRS ,0) {
+						Return(IRQB) // Return(IRQP)
+					} /* Method(_SB.INTB._PRS) */
+
+					Method(_CRS ,0) {
+						Store (IRQB, Local0) // {10,11}
+						CreateWordField(Local0, 0x1, IRQ0)
+						ShiftLeft(1, PINB, IRQ0)
+						Return(Local0)
+					} /* Method(_SB.INTB._CRS) */
+
+					Method(_SRS, 1) {
+						CreateWordField(ARG0, 1, IRQ0)
+						/* Use lowest available IRQ */
+						FindSetRightBit(IRQ0, Local0)
+						Decrement(Local0)
+						Store(Local0, PINB)                    
+					} /* End Method(_SB.INTB._SRS) */
+				} /* End Device(INTB)  */
+
+				Device(INTC) {
+					Name(_HID, EISAID("PNP0C0F"))
+					Name(_UID, 3)
+
+					Method(_STA, 0) {
+						if (PINC) {
+							Return(0x0B) /* sata is invisible */
+						} else {
+							Return(0x09) /* sata is disabled */
+						}
+					} /* End Method(_SB.INTC._STA) */
+
+					Method(_DIS ,0) {
+						Store(0, PINC)
+					} /* End Method(_SB.INTC._DIS) */
+
+					Method(_PRS ,0) {
+						Return(IRQB) // Return(IRQP)
+					} /* Method(_SB.INTC._PRS) */
+
+					Method(_CRS ,0) {
+						Store (IRQB, Local0) // {10,11}
+						CreateWordField(Local0, 0x1, IRQ0)
+						ShiftLeft(1, PINC, IRQ0)
+						Return(Local0)
+					} /* Method(_SB.INTC._CRS) */
+
+					Method(_SRS, 1) {
+						CreateWordField(ARG0, 1, IRQ0)
+						/* Use lowest available IRQ */
+						FindSetRightBit(IRQ0, Local0)
+						Decrement(Local0)
+						Store(Local0, PINC)    
+					} /* End Method(_SB.INTC._SRS) */
+				} /* End Device(INTC)  */
+
+				Device(INTD) {
+					Name(_HID, EISAID("PNP0C0F"))
+					Name(_UID, 4)
+
+					Method(_STA, 0) {
+						if (PIND) {
+							Return(0x0B) /* sata is invisible */
+						} else {
+							Return(0x09) /* sata is disabled */
+						}
+					} /* End Method(_SB.INTD._STA) */
+
+					Method(_DIS ,0) {
+						Store(0, PIND)
+					} /* End Method(_SB.INTD._DIS) */
+
+					Method(_PRS ,0) {
+						Return(IRQB) // Return(IRQP)
+					} /* Method(_SB.INTD._PRS) */
+
+					Method(_CRS ,0) {
+						Store (IRQB, Local0) // {10,11}
+						CreateWordField(Local0, 0x1, IRQ0)
+						ShiftLeft(1, PIND, IRQ0)
+						Return(Local0)
+					} /* Method(_SB.INTD._CRS) */
+
+					Method(_SRS, 1) {
+						CreateWordField(ARG0, 1, IRQ0)
+						/* Use lowest available IRQ */
+						FindSetRightBit(IRQ0, Local0)
+						Decrement(Local0)
+						Store(Local0, PIND)
+					} /* End Method(_SB.INTD._SRS) */
+				} /* End Device(INTD)  */
+
+				Device(INTE) {
+					Name(_HID, EISAID("PNP0C0F"))
+					Name(_UID, 5)
+					
+					Method(_STA, 0) {
+						if (PINE) {
+							Return(0x0B) /* sata is invisible */
+						} else {
+							Return(0x09) /* sata is disabled */
+						}
+					} /* End Method(_SB.INTE._STA) */
+
+					Method(_DIS ,0) {
+						Store(0, PINE)
+					} /* End Method(_SB.INTE._DIS) */
+
+					Method(_PRS ,0) { 
+						Return(IRQB) // Return(IRQP)
+					}
+
+					Method(_CRS ,0) {
+						Store (IRQB, Local0) // {10,11}
+						CreateWordField(Local0, 0x1, IRQ0)
+						ShiftLeft(1, PINE, IRQ0)
+						Return(Local0)
+					} /* Method(_SB.INTE._CRS) */
+
+					Method(_SRS, 1) {
+						CreateWordField(ARG0, 1, IRQ0)
+						/* Use lowest available IRQ */
+						FindSetRightBit(IRQ0, Local0)
+						Decrement(Local0)
+						Store(Local0, PINE)
+					} /* End Method(_SB.INTE._SRS) */
+				} /* End Device(INTE)  */
+
+				Device(INTF) {
+					Name(_HID, EISAID("PNP0C0F"))
+					Name(_UID, 6)
+
+					Method(_STA, 0) {
+						if (PINF) {
+							Return(0x0B) /* sata is invisible */
+						} else {
+							Return(0x09) /* sata is disabled */
+						}
+					} /* End Method(_SB.INTF._STA) */
+
+					Method(_DIS ,0) {
+						Store(0, PINF)
+					} /* End Method(_SB.INTF._DIS) */
+
+					Method(_PRS ,0) {
+						Return(IRQB) // Return(PITF)
+					} /* Method(_SB.INTF._PRS) */
+
+					Method(_CRS ,0) {
+						Store (IRQB, Local0) // {10,11}
+						CreateWordField(Local0, 0x1, IRQ0)
+						ShiftLeft(1, PINF, IRQ0)
+						Return(Local0)
+					} /* Method(_SB.INTF._CRS) */
+
+					Method(_SRS, 1) {
+						CreateWordField(ARG0, 1, IRQ0)
+						/* Use lowest available IRQ */
+						FindSetRightBit(IRQ0, Local0)
+						Decrement(Local0)
+						Store(Local0, PINF)
+					} /*  End Method(_SB.INTF._SRS) */
+				} /* End Device(INTF)  */
+
+				Device(INTG) {
+					Name(_HID, EISAID("PNP0C0F"))
+					Name(_UID, 7)
+
+					Method(_STA, 0) {
+						if (PING) {
+							Return(0x0B) /* sata is invisible */
+						} else {
+							Return(0x09) /* sata is disabled */
+						}
+					} /* End Method(_SB.INTG._STA)  */
+
+					Method(_DIS ,0) {
+						Store(0, PING)
+					} /* End Method(_SB.INTG._DIS)  */
+
+					Method(_PRS ,0) {
+						Return(IRQB) // Return(IRQP)
+					} /* Method(_SB.INTG._CRS)  */
+
+					Method(_CRS ,0) {
+						Store (IRQB, Local0) // {10,11}
+						CreateWordField(Local0, 0x1, IRQ0)
+						ShiftLeft(1, PING, IRQ0)
+						Return(Local0)
+					} /* Method(_SB.INTG._CRS)  */
+
+					Method(_SRS, 1) {
+						CreateWordField(ARG0, 1, IRQ0)
+						/* Use lowest available IRQ */
+						FindSetRightBit(IRQ0, Local0)
+						Decrement(Local0)
+						Store(Local0, PING)
+					} /* End Method(_SB.INTG._SRS)  */
+				} /* End Device(INTG)  */
+
+				Device(INTH) {
+					Name(_HID, EISAID("PNP0C0F"))
+					Name(_UID, 8)
+
+					Method(_STA, 0) {
+						if (PINH) {
+							Return(0x0B) /* sata is invisible */
+						} else {
+							Return(0x09) /* sata is disabled */
+						}
+					} /* End Method(_SB.INTH._STA)  */
+
+					Method(_DIS ,0) {
+						Store(0, PINH)
+					} /* End Method(_SB.INTH._DIS)  */
+
+					Method(_PRS ,0) {
+						Return(IRQB) // Return(IRQP)
+					} /* Method(_SB.INTH._CRS)  */
+
+					Method(_CRS ,0) {
+						Store (IRQB, Local0) // {10,11}
+						CreateWordField(Local0, 0x1, IRQ0)
+						ShiftLeft(1, PINH, IRQ0)
+						Return(Local0)
+					} /* Method(_SB.INTH._CRS)  */
+
+					Method(_SRS, 1) {
+						CreateWordField(ARG0, 1, IRQ0)
+						/* Use lowest available IRQ */
+						FindSetRightBit(IRQ0, Local0)
+						Decrement(Local0)
+						Store(Local0, PINH)
+					} /* End Method(_SB.INTH._SRS)  */
+				} /* End Device(INTH)   */
+		
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible)*/
 					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){8}
-						IO(Decode16,0x0070, 0x0070, 0, 2)
+						IRQ (Edge, ActiveHigh, Exclusive, ) {8}
+						IO(Decode16,0x0070, 0x0070, 1, 2)
 						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
 					})
 				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
@@ -1319,8 +959,8 @@
 				Device(TMR) {	/* Timer */
 					Name(_HID,EISAID("PNP0100"))	/* System Timer */
 					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){0}
-						IO(Decode16, 0x0040, 0x0040, 0, 4)
+                        IRQ (Edge, ActiveHigh, Exclusive, ) {0}
+						IO(Decode16, 0x0040, 0x0040, 1, 4)
 						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
 					})
 				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
@@ -1328,15 +968,15 @@
 				Device(SPKR) {	/* Speaker */
 					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
 					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x0061, 0x0061, 0, 1)
+						IO(Decode16, 0x0061, 0x0061, 1, 1)
 					})
 				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
 
 				Device(PIC) {
 					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
 					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){2}
-						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IRQ (Edge, ActiveHigh, Exclusive, ) {2}
+						IO(Decode16,0x0020, 0x0020, 1, 2)
 						IO(Decode16,0x00A0, 0x00A0, 0, 2)
 						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
 						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
@@ -1346,7 +986,7 @@
 				Device(MAD) { /* 8257 DMA */
 					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
 					Name(_CRS, ResourceTemplate() {
-						DMA(Compatibility,BusMaster,Transfer8){4}
+						DMA(Compatibility,NotBusMaster,Transfer8_16){4}
 						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
 						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
 						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
@@ -1359,12 +999,12 @@
 				Device(COPR) {
 					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
 					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-						IRQNoFlags(){13}
+						IO(Decode16, 0x00F0, 0x00F0, 1, 0x10)
+						IRQ (Edge, ActiveHigh, Exclusive, ) {13} 
 					})
 				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
 
-				Device(HPTM) {
+				Device(HPET) {
 					Name(_HID,EISAID("PNP0103"))
 					Name(CRS,ResourceTemplate()	{
 						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
@@ -1377,19 +1017,55 @@
 						Store(HPBA, HPBA)
 						Return(CRS)
 					}
-				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-			} /* end LIBR */
-
-			Device(HPBR) {
-				Name(_ADR, 0x00140004)
-			} /* end HostPciBr */
+                }
+				
+                Device (KBC0)
+                {
+                    Name (_HID, EisaId ("PNP0303"))
+                    Name (_CRS, ResourceTemplate ()
+                    {
+                        IO (Decode16,
+                            0x0060,             // Range Minimum
+                            0x0060,             // Range Maximum
+                            0x01,               // Alignment
+                            0x01,               // Length
+                            )
+                        IO (Decode16,
+                            0x0064,             // Range Minimum
+                            0x0064,             // Range Maximum
+                            0x01,               // Alignment
+                            0x01,               // Length
+                            )
+                        IRQ (Edge, ActiveHigh, Exclusive, ) {1}
+                    })
+				}
+				
+                Device (MSE0)
+                {
+                    Name (_HID, EisaId ("PNP0F13"))
+                    Name (_CRS, ResourceTemplate ()
+                    {
+                        IRQ (Edge, ActiveHigh, Exclusive, ) {12}
+                    })
+				}
+			} /* end LPC0 */
 
 			Device(ACAD) {
 				Name(_ADR, 0x00140005)
+				Name (_PRW, Package (0x02)
+                {
+                    0x0C, 
+                    0x04
+                })
 			} /* end Ac97audio */
 
 			Device(ACMD) {
 				Name(_ADR, 0x00140006)
+				Name (_PRW, Package (0x02)
+                {
+                    0x0C, 
+                    0x04
+                })
 			} /* end Ac97modem */
 
 			/* ITE IT8712F Support */
@@ -1435,7 +1111,7 @@
 			 * Keyboard PME is routed to SB600 Gevent3. We can wake
 			 * up the system by pressing the key.
 			 */
-		        Method (SIOS, 1)
+	        Method (SIOS, 1)
 			{
 				/* We only enable KBD PME for S5. */
 				If (LLess (Arg0, 0x05))
@@ -1468,6 +1144,7 @@
 				XPNP()
 			}
 
+/* ############################################################################################### */
 			Name(CRES, ResourceTemplate() {
 				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
 
@@ -1487,133 +1164,39 @@
 					0xF300			/* length */
 				)
 
-				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
 				/* DRAM Memory from 1MB to TopMem */
-				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
-
-				/* BIOS space just below 4GB */
-				DWORDMemory(
-					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0x00,			/* Granularity */
-					0x00000000,		/* Min */
-					0x00000000,		/* Max */
-					0x00000000,		/* Translation */
-					0x00000001,		/* Max-Min, RLEN */
-					,,
-					PCBM
-				)
-
-				/* DRAM memory from 4GB to TopMem2 */
-				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0x00000000,		/* Granularity */
-					0x00000000,		/* Min */
-					0x00000000,		/* Max */
-					0x00000000,		/* Translation */
-					0x00000001,		/* Max-Min, RLEN */
-					,,
-					DMHI
-				)
-
-				/* BIOS space just below 16EB */
-				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0x00000000,		/* Granularity */
-					0x00000000,		/* Min */
-					0x00000000,		/* Max */
-					0x00000000,		/* Translation */
-					0x00000001,		/* Max-Min, RLEN */
-					,,
-					PEBM
-				)
-
+				DWORDMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0, 0, 0, 0x00, 1, ,, EMM2)
+				WORDIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00, 0x0D00, 0xffff, 0x00, 0xf300)
 			}) /* End Name(_SB.PCI0.CRES) */
 
 			Method(_CRS, 0) {
+
 				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
 
 				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
 				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
-				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
-				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
-				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
-				CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
-				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
-				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
-				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
-				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				CreateDWordField(CRES, ^EMM2._MIN, EM2B)
+				CreateDWordField(CRES, ^EMM2._MAX, EM2E)
+				CreateDWordField(CRES, ^EMM2._LEN, EM2L)
+				
+				Store(TOM1, EM2B)
+				Subtract(IOLM, 1, EM2E)
+				Subtract(IOLM, TOM1, EM2L)
 
 				If(LGreater(LOMH, 0xC0000)){
 					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
 					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
 				}
 
-				/* Set size of memory from 1MB to TopMem */
-				Subtract(TOM1, 0x100000, DMLL)
-
-				/*
-				* If(LNotEqual(TOM2, 0x00000000)){
-				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	ShiftLeft(TOM2, 20, Local0)
-				*	Subtract(Local0, 0x100000000, DMHL)
-				* }
-				*/
-
-				/* If there is no memory above 4GB, put the BIOS just below 4GB */
-				If(LEqual(TOM2, 0x00000000)){
-					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
-					Store(PBLN,PBML)
-				}
-				Else {  /* Otherwise, put the BIOS just below 16EB */
-					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
-					Store(PBLN,EBML)
-				}
-
 				Return(CRES) /* note to change the Name buffer */
-			}  /* end of Method(_SB.PCI0._CRS) */
-
-			/*
-			*
-			*               FIRST METHOD CALLED UPON BOOT
-			*
-			*  1. If debugging, print current OS and ACPI interpreter.
-			*  2. Get PCI Interrupt routing from ACPI VSM, this
-			*     value is based on user choice in BIOS setup.
-			*/
-			Method(_INI, 0) {
-				/* DBGO("\\_SB\\_INI\n") */
-				/* DBGO("   DSDT.ASL code from ") */
-				/* DBGO(__DATE__) */
-				/* DBGO(" ") */
-				/* DBGO(__TIME__) */
-				/* DBGO("\n   Sleep states supported: ") */
-				/* DBGO("\n") */
-				/* DBGO("   \\_OS=") */
-				/* DBGO(\_OS) */
-				/* DBGO("\n   \\_REV=") */
-				/* DBGO(\_REV) */
-				/* DBGO("\n") */
-
-				/* Determine the OS we're running on */
-				CkOT()
-
-				/* On older chips, clear PciExpWakeDisEn */
-				/*if (LLessEqual(\SBRI, 0x13)) {
-				*    	Store(0,\PWDE)
-				* }
-				*/
-			} /* End Method(_SB._INI) */
+			}
+/* ########################################################################################## */
 		} /* End Device(PCI0)  */
-
-		Device(PWRB) {	/* Start Power button device */
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
-			Name(_STA, 0x0B) /* sata is invisible */
-		}
 	} /* End \_SB scope */
 
 	Scope(\_SI) {
@@ -1626,7 +1209,7 @@
 	} /* End Scope SI */
 
 	Mutex (SBX0, 0x00)
-	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x10)  // 0x0C replace by 0x10
 		Field (SMB0, ByteAcc, NoLock, Preserve) {
 			HSTS,   8, /* SMBUS status */
 			SSTS,   8,  /* SMBUS slave status */
@@ -1639,7 +1222,11 @@
 			SCNT,   8,  /* SMBUS slave control */
 			SCMD,   8,  /* SMBUS shaow cmd */
 			SEVT,   8,  /* SMBUS slave event */
-			SDAT,   8  /* SMBUS slave data */
+			SDAT,   8,  /* SMBUS slave data */
+			SMK1,   8, 
+            SLMC,   8, 
+            RADD,   8, 
+            SADD,   8
 	}
 
 	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
@@ -1718,75 +1305,5 @@
 
 		Return (Local0)
 	}
-
-	/* THERMAL */
-	Scope(\_TZ) {
-		Name (KELV, 2732)
-		Name (THOT, 800)
-		Name (TCRT, 850)
-
-		ThermalZone(TZ00) {
-			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
-				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
-				Return(Add(0, 2730))
-			}
-			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
-				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
-				Return(Package() {\_TZ.TZ00.FAN0})
-			}
-			Device (FAN0) {
-				Name(_HID, EISAID("PNP0C0B"))
-				Name(_PR0, Package() {PFN0})
-			}
-
-			PowerResource(PFN0,0,0) {
-				Method(_STA) {
-					Store(0xF,Local0)
-					Return(Local0)
-				}
-				Method(_ON) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
-				}
-				Method(_OFF) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
-				}
-			}
-
-			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
-				Return (Add (THOT, KELV))
-			}
-			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
-				Return (Add (TCRT, KELV))
-			}
-			Method(_TMP,0) {	/* return current temp of this zone */
-				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
-				If (LGreater (Local0, 0x10)) {
-					Store (Local0, Local1)
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400, KELV))
-				}
-
-				Store (SMBR (0x07, 0x4C, 0x01), Local0)
-				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
-				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
-				If (LGreater (Local0, 0x10)) {
-					If (LGreater (Local0, Local1)) {
-						Store (Local0, Local1)
-					}
-
-					Multiply (Local1, 10, Local1)
-					Return (Add (Local1, KELV))
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400 , KELV))
-				}
-			} /* end of _TMP */
-		} /* end of TZ00 */
-	}
+#include "acpi/thermal.asl"
 }
-/* End of ASL file */

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/fadt.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/fadt.c	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/fadt.c	Wed May 11 09:47:43 2011	(r6567)
@@ -26,7 +26,7 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/device.h>
-#include "southbridge/amd/sb600/sb600.h"
+#include <../southbridge/amd/sb600/sb600.h>
 
 /*extern*/ u16 pm_base = 0x800;
 /* pm_base should be set in sb acpi */
@@ -56,7 +56,8 @@
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
+	header->oem_revision = 0x20101005;
+	header->asl_compiler_revision = 3;
 
 	fadt->firmware_ctrl = (u32) facs;
 	fadt->dsdt = (u32) dsdt;

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/get_bus_conf.c	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c	Wed May 11 09:47:43 2011	(r6567)
@@ -32,6 +32,7 @@
 /* Global variables for MB layouts and these will be shared by irqtable mptable
 * and acpi_tables busnum is default.
 */
+u8 bus_isa;
 u8 bus_rs690[8];
 u8 bus_sb600[2];
 u32 apicid_sb600;
@@ -53,6 +54,8 @@
 	0x20202020,
 };
 
+u32 bus_type[256];
+
 u32 sbdn_rs690;
 u32 sbdn_sb600;
 
@@ -64,7 +67,7 @@
 {
 	u32 apicid_base;
 	device_t dev;
-	int i;
+	int i, j;
 
 	if (get_bus_conf_done == 1)
 		return;		/* do it only once */
@@ -89,13 +92,25 @@
 		bus_rs690[i] = 0;
 	}
 
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+	bus_type[0] = 1;	/* pci */
+
 	bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 	bus_sb600[0] = bus_rs690[0];
 
+	bus_type[bus_rs690[0]] = 1;
+
 	/* sb600 */
 	dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
 	if (dev) {
 		bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb600[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
 	}
 
 	/* rs690 */
@@ -103,10 +118,16 @@
 		dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
 		if (dev) {
 			bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			if(255 != bus_rs690[i]) {
+				bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+				bus_isa++;
+				bus_type[bus_rs690[i]] = 1; /* PCI bus. */
+			}
 		}
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(1);
 #else

Added: trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.c	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2009 Libra Li <libra.li at technexion.com>
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+ 
+#include <stdint.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include <arch/interrupt.h>
+#include "int15_func.h"
+
+int sbios_INT15_handler(struct eregs *);
+/*extern*/ unsigned long vgainfo_addr;
+
+static INT15_function_extensions __int15_func;
+
+/* System BIOS int15 function */
+int sbios_INT15_handler(struct eregs *regs)
+{
+    int res = -1;
+
+    printk(BIOS_DEBUG, "System BIOS INT 15h\n");
+
+    switch (regs->eax & 0xffff) {
+#define BOOT_DISPLAY_DEFAULT    0
+#define BOOT_DISPLAY_CRT        (1 << 0)
+#define BOOT_DISPLAY_TV         (1 << 1)
+#define BOOT_DISPLAY_EFP        (1 << 2)
+#define BOOT_DISPLAY_LCD        (1 << 3)
+#define BOOT_DISPLAY_CRT2       (1 << 4)
+#define BOOT_DISPLAY_TV2        (1 << 5)
+#define BOOT_DISPLAY_EFP2       (1 << 6)
+#define BOOT_DISPLAY_LCD2       (1 << 7)
+	case 0x5f35:
+		regs->eax = 0x5f;
+		regs->ecx = BOOT_DISPLAY_DEFAULT;
+		res = 0;
+		break;
+	case 0x5f40:
+		regs->eax = 0x5f;
+		regs->ecx = 3; // This is mainboard specific
+		printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
+		res = 0;
+		break;
+    case 0x4e08:
+        switch (regs->ebx & 0xff) {
+        case 0x00:
+            regs->eax &= ~(0xff);
+            regs->ebx = (regs->ebx & ~(0xff)) | __int15_func.regs.func00_LCD_panel_id;
+			printk(BIOS_DEBUG, "DISPLAY = %x\n", regs->ebx & 0xff);
+            res = 0;
+			break;
+		case 0x02:
+			break;
+        case 0x05:
+            regs->eax &= ~(0xff);
+            regs->ebx = (regs->ebx & ~(0xff)) | __int15_func.regs.func05_TV_standard;
+			printk(BIOS_DEBUG, "TV = %x\n", regs->ebx & 0xff);
+            res = 0;
+			break;
+		case 0x80:
+			regs->eax &= ~(0xff);
+			regs->ebx &= ~(0xff);
+			printk(BIOS_DEBUG, "Integrated System Information = %x:%x\n", regs->edx, regs->edi);
+			vgainfo_addr = (regs->edx * 16) + regs->edi; 
+			res = 0;
+			break;
+		case 0x89:
+			regs->eax &= ~(0xff);
+			regs->ebx &= ~(0xff);
+			printk(BIOS_DEBUG, "Get supported display device information\n");
+			res = 0;
+			break;
+		default:
+			break;
+        }
+        break;
+	default:
+        printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff);
+		break;
+    }
+
+    return res;
+}
+
+/* Initialization VBIOS function extensions */
+void install_INT15_function_extensions(INT15_function_extensions *int15_func)
+{
+	printk(BIOS_DEBUG, "Initialize function extensions for Callback function number 04E08h ..\n");
+	__int15_func.regs.func00_LCD_panel_id = int15_func->regs.func00_LCD_panel_id;
+	__int15_func.regs.func05_TV_standard = int15_func->regs.func05_TV_standard;
+	mainboard_interrupt_handlers(0x15, &sbios_INT15_handler);
+}

Added: trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.h	Wed May 11 09:47:43 2011	(r6567)
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2009 Libra Li <libra.li at technexion.com>
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+typedef struct {
+        u8 func00_LCD_panel_id;      // Callback Sub-Function 00h - Get LCD Panel ID
+		u8 func02_set_expansion;
+        u8 func05_TV_standard;       // Callback Sub-Function 05h - Select Boot-up TV Standard
+		u16 func80_sysinfo_table;
+}INT15_regs;
+
+typedef struct {
+        INT15_regs        regs;
+}INT15_function_extensions;
+
+extern void install_INT15_function_extensions(INT15_function_extensions *);

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/irq_tables.c	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/irq_tables.c	Wed May 11 09:47:43 2011	(r6567)
@@ -23,6 +23,7 @@
 
    Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
 */
+
 #include <console/console.h>
 #include <device/pci.h>
 #include <string.h>
@@ -31,7 +32,23 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-
+/* Platform IRQs */
+#define PIRQA 10
+#define PIRQB 11
+#define PIRQC 5
+#define PIRQD 15
+
+/* Map */
+#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA	 1		/* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB	 2		/* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC	 3		/* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD	 4		/* Means Slot INTx# Connects To Chipset INTD# */
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
@@ -51,6 +68,7 @@
 	pirq_info->slot = slot;
 	pirq_info->rfu = rfu;
 }
+extern u8 bus_isa;
 extern u8 bus_rs690[8];
 extern u8 bus_sb600[2];
 extern unsigned long sbdn_sb600;
@@ -96,9 +114,7 @@
 	slot_num = 0;
 
 	/* pci bridge */
-	write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
+	write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 1,	0);
 	pirq_info++;
 	slot_num++;
 

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/mainboard.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/mainboard.c	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/mainboard.c	Wed May 11 09:47:43 2011	(r6567)
@@ -2,7 +2,9 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
+ * 
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -16,135 +18,393 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
-
+ 
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <delay.h>
 #include <boot/tables.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
+#include <pc80/mc146818rtc.h>
+#include <cpu/x86/lapic.h>
 #include <southbridge/amd/sb600/sb600.h>
+#include <southbridge/amd/rs690/chip.h>
+#include <southbridge/amd/rs690/rs690.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include "chip.h"
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include "int15_func.h"
+
+// ****LCD panel ID support: *****
+// Callback Sub-Function 00h - Get LCD Panel ID
+#define PANEL_TABLE_ID_NO 	0 // no LCD
+#define PANEL_TABLE_ID1 	1 // 1024x768_65MHz_Dual
+#define PANEL_TABLE_ID2 	2 // 920x1200_162MHz
+#define PANEL_TABLE_ID3 	3 // 600x1200_162MHz
+#define PANEL_TABLE_ID4 	4 // 1024x768_65MHz
+#define PANEL_TABLE_ID5 	5 // 1400x1050_108MHz
+#define PANEL_TABLE_ID6 	6 // 1680x1050_119MHz
+#define PANEL_TABLE_ID7 	7 // 2048x1536_164MHz
+#define PANEL_TABLE_ID8 	8 // 1280x1024_108MHz
+#define PANEL_TABLE_ID9 	9 // 1366x768_86MHz_chimei_V32B1L01
+
+// Callback Sub-Function 05h ? Select Boot-up TV Standard
+#define TV_MODE_00	0x00	/* NTSC */
+#define TV_MODE_01	0x01	/* PAL */
+#define TV_MODE_02	0x02	/* PALM */
+#define TV_MODE_03	0x03	/* PAL60 */
+#define TV_MODE_04	0x04	/* NTSCJ */
+#define TV_MODE_05	0x05	/* PALCN */
+#define TV_MODE_06	0x06	/* PALN */
+#define TV_MODE_09	0x09	/* SCART-RGB */
+#define TV_MODE_NO	0xff	/* No TV Support */
+
+#define PLX_VIDDID 0x861610b5
+
+/* 7475 Common Registers */
+#define REG_DEVREV2             0x12    /* ADT7490 only */
+#define REG_VTT                 0x1E    /* ADT7490 only */
+#define REG_EXTEND3             0x1F    /* ADT7490 only */
+#define REG_VOLTAGE_BASE        0x20
+#define REG_TEMP_BASE           0x25
+#define REG_TACH_BASE           0x28
+#define REG_PWM_BASE            0x30
+#define REG_PWM_MAX_BASE        0x38
+#define REG_DEVID               0x3D
+#define REG_VENDID              0x3E
+#define REG_DEVID2              0x3F
+#define REG_STATUS1             0x41
+#define REG_STATUS2             0x42
+#define REG_VID                 0x43    /* ADT7476 only */
+#define REG_VOLTAGE_MIN_BASE    0x44
+#define REG_VOLTAGE_MAX_BASE    0x45
+#define REG_TEMP_MIN_BASE       0x4E
+#define REG_TEMP_MAX_BASE       0x4F
+#define REG_TACH_MIN_BASE       0x54
+#define REG_PWM_CONFIG_BASE     0x5C
+#define REG_TEMP_TRANGE_BASE    0x5F
+#define REG_PWM_MIN_BASE        0x64
+#define REG_TEMP_TMIN_BASE      0x67
+#define REG_TEMP_THERM_BASE     0x6A
+#define REG_REMOTE1_HYSTERSIS   0x6D
+#define REG_REMOTE2_HYSTERSIS   0x6E
+#define REG_TEMP_OFFSET_BASE    0x70
+#define REG_CONFIG2             0x73
+#define REG_EXTEND1             0x76
+#define REG_EXTEND2             0x77
+#define REG_CONFIG1				0x40	// ADT7475
+#define REG_CONFIG3             0x78
+#define REG_CONFIG5             0x7C
+#define REG_CONFIG6				0x10	// ADT7475
+#define REG_CONFIG7				0x11	// ADT7475
+#define REG_CONFIG4             0x7D
+#define REG_STATUS4             0x81    /* ADT7490 only */
+#define REG_VTT_MIN             0x84    /* ADT7490 only */
+#define REG_VTT_MAX             0x86    /* ADT7490 only */
+
+#define VID_VIDSEL              0x80    /* ADT7476 only */
+
+#define CONFIG2_ATTN            0x20
+#define CONFIG3_SMBALERT        0x01
+#define CONFIG3_THERM           0x02
+#define CONFIG4_PINFUNC         0x03
+#define CONFIG4_MAXDUTY         0x08
+#define CONFIG4_ATTN_IN10       0x30
+#define CONFIG4_ATTN_IN43       0xC0
+#define CONFIG5_TWOSCOMP        0x01
+#define CONFIG5_TEMPOFFSET      0x02
+#define CONFIG5_VIDGPIO         0x10    /* ADT7476 only */
+#define REMOTE1					0
+#define LOCAL					1
+#define REMOTE2					2
+
+/* ADT7475 Settings */
+#define ADT7475_VOLTAGE_COUNT   5       /* Not counting Vtt */
+#define ADT7475_TEMP_COUNT      3
+#define ADT7475_TACH_COUNT      4
+#define ADT7475_PWM_COUNT       3
+
+/* Macros to easily index the registers */
+#define TACH_REG(idx) (REG_TACH_BASE + ((idx) * 2))
+#define TACH_MIN_REG(idx) (REG_TACH_MIN_BASE + ((idx) * 2))
+
+#define PWM_REG(idx) (REG_PWM_BASE + (idx))
+#define PWM_MAX_REG(idx) (REG_PWM_MAX_BASE + (idx))
+#define PWM_MIN_REG(idx) (REG_PWM_MIN_BASE + (idx))
+#define PWM_CONFIG_REG(idx) (REG_PWM_CONFIG_BASE + (idx))
+
+#define VOLTAGE_REG(idx) (REG_VOLTAGE_BASE + (idx))
+#define VOLTAGE_MIN_REG(idx) (REG_VOLTAGE_MIN_BASE + ((idx) * 2))
+#define VOLTAGE_MAX_REG(idx) (REG_VOLTAGE_MAX_BASE + ((idx) * 2))
+
+#define TEMP_REG(idx) (REG_TEMP_BASE + (idx))
+#define TEMP_MIN_REG(idx) (REG_TEMP_MIN_BASE + ((idx) * 2))
+#define TEMP_MAX_REG(idx) (REG_TEMP_MAX_BASE + ((idx) * 2))
+#define TEMP_TMIN_REG(idx) (REG_TEMP_TMIN_BASE + (idx))
+#define TEMP_THERM_REG(idx) (REG_TEMP_THERM_BASE + (idx))
+#define TEMP_OFFSET_REG(idx) (REG_TEMP_OFFSET_BASE + (idx))
+#define TEMP_TRANGE_REG(idx) (REG_TEMP_TRANGE_BASE + (idx))
 
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS     0x0C /* Alert Response Address */
 #define SMBUS_IO_BASE 0x1000
+#define ADT7475_ADDRESS 0x2E
+
+#define   D_OPEN	(1 << 6)
+#define   D_CLS		(1 << 5)
+#define   D_LCK		(1 << 4)
+#define   G_SMRAME	(1 << 3)
+#define   A_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0)) // 0x2: SMM space at 640KB-768KB
 
 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
-			       u8 val);
-#define ADT7461_read_byte(address) \
-	do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
-	do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
-	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
 
 uint64_t uma_memory_base, uma_memory_size;
+static u32 smbus_io_base = SMBUS_IO_BASE;
+static u32 adt7475_address = ADT7475_ADDRESS;
 
-/********************************************************
-* dbm690t uses a BCM5789 as on-board NIC.
-* It has a pin named LOW_POWER to enable it into LOW POWER state.
-* In order to run NIC, we should let it out of Low power state. This pin is
-* controlled by sb600 GPM3.
-* RRG4.2.3 GPM as GPIO
-* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
-* I/O C50, C51, C52, PM I/O94, 95, 96.
-* RRG4.2.3.1 GPM pins as Input
-* RRG4.2.3.2 GPM pins as Output
-********************************************************/
-static void enable_onboard_nic(void)
+/* Macro to read the registers */
+#define adt7475_read_byte(reg) \
+	do_smbus_read_byte(smbus_io_base, adt7475_address, reg)
+
+#define adt7475_write_byte(reg, val) \
+	do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val)
+	
+#define TWOS_COMPL 1
+
+struct __table__{
+	const char *info;
+	u8 val;
+};
+
+struct __table__ dutycycles[] = {
+	{"25%", 0x3f},{"30%", 0x4c},{"35%", 0x59},{"40%", 0x66},{"45%", 0x73},
+	{"50%", 0x80},{"55%", 0x8d},{"60%", 0x9a},{"65%", 0xa7},{"70%", 0xb4},
+	{"75%", 0xc1},{"80%", 0xce},{"85%", 0xdb},{"90%", 0xe8},{"95%", 0xf5},
+	{"100%", 0xff}
+};
+#define SIZEOF_DUTYCYCLES sizeof(dutycycles)/sizeof(struct __table__)
+#define DUTYCYCLE(i,d) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].val : dutycycles[d].val // hopefully d is a correct value !!! fix
+#define DUTYCYCLE_INFO(i) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].info : "out_of_range"
+#if TWOS_COMPL == 0
+struct __table__ temperatures[] = {
+	{"30?C", 0x5e},{"35?C", 0x63},{"40?C", 0x68},{"45?C", 0x6d},{"50?C", 0x72},
+	{"55?C", 0x77},{"60?C", 0x7c},{"65?C", 0x81},{"70?C", 0x86},{"75?C", 0x8b},
+	{"80?C", 0x90}
+};
+#else
+struct __table__ temperatures[] = {
+	{"30?C", 30},{"35?C", 35},{"40?C", 40},{"45?C", 45},{"50?C", 50},
+	{"55?C", 55},{"60?C", 60},{"65?C", 65},{"70?C", 70},{"75?C", 75},
+	{"80?C", 80}
+};
+#endif
+int trange[] = {2.0,2.5,3.33,4.0,5.0,6.67,8.0,10.0,13.33,16.0,20.0,26.67,32.0,40.0,53.33,80.0};
+
+#define SIZEOF_TEMPERATURES sizeof(temperatures)/sizeof(struct __table__)
+#define TEMPERATURE(i,d) (i < SIZEOF_TEMPERATURES) ? temperatures[i].val : temperatures[d].val // hopefully d is a correct value !!! fix
+#define TEMPERATURE_INFO(i) (i < SIZEOF_TEMPERATURES) ? temperatures[i].info : "out of range"
+
+struct fan_control {
+		unsigned int enable : 1;
+		u8 polarity;
+		u8 t_min;
+		u8 t_max;
+		u8 pwm_min;
+		u8 pwm_max;
+		u8 t_range;
+};
+/* ############################################################################################# */
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
 {
-	u8 byte;
+#define BOOT_DISPLAY_DEFAULT	0
+#define BOOT_DISPLAY_CRT	(1 << 0)
+#define BOOT_DISPLAY_TV		(1 << 1)
+#define BOOT_DISPLAY_EFP	(1 << 2)
+#define BOOT_DISPLAY_LCD	(1 << 3)
+#define BOOT_DISPLAY_CRT2	(1 << 4)
+#define BOOT_DISPLAY_TV2	(1 << 5)
+#define BOOT_DISPLAY_EFP2	(1 << 6)
+#define BOOT_DISPLAY_LCD2	(1 << 7)
+
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+	switch (M.x86.R_AX) {
+	case 0x4e08: /* Boot Display */
+	    switch (M.x86.R_BX) {
+		case 0x80:
+			M.x86.R_AX &= ~(0xff); // Success
+			M.x86.R_BX &= ~(0xff);
+			printk(BIOS_DEBUG, "Integrated System Information\n");
+			break;
+		case 0x00:
+			M.x86.R_AX &= ~(0xff);
+			M.x86.R_BX = 0x00;
+			printk(BIOS_DEBUG, "Panel ID = 0\n");
+			break;
+		case 0x05:
+			M.x86.R_AX &= ~(0xff);
+			M.x86.R_BX = 0xff;
+			printk(BIOS_DEBUG, "TV = off\n");
+			break;
+		default:
+			return 0;
+		}
+		break;
+	case 0x5f35: /* Boot Display */
+		M.x86.R_AX = 0x005f; // Success
+		M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
+		break;
+	case 0x5f40: /* Boot Panel Type */
+		// M.x86.R_AX = 0x015f; // Supported but failed
+		M.x86.R_AX = 0x005f; // Success
+		M.x86.R_CL = 3; // Display ID
+		break;
+	default:
+		/* Interrupt was not handled */
+		return 0;
+	}
 
-	printk(BIOS_INFO, "%s.\n", __func__);
+	/* Interrupt handled */
+	return 1;
+}
 
-	/* set index register 0C50h to 13h (miscellaneous control) */
-	outb(0x13, 0xC50);	/* CMIndex */
+static void int15_install(void)
+{
+	typedef int (* yabel_handleIntFunc)(void);
+	extern yabel_handleIntFunc yabel_intFuncArray[256];
+	yabel_intFuncArray[0x15] = int15_handler;
+}
+#endif
+/* ############################################################################################# */
+
+ /**
+ * @brief 
+ *
+ * @param 
+ */
 
-	/* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
-	byte = inb(0xC51);
-	byte &= 0x3F;
-	byte |= 0x40;
-	outb(byte, 0xC51);
-
-	/* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
-	byte = inb(0xC52);
-	byte &= ~0x8;
-	outb(byte, 0xC52);
-
-	/* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
-	byte = inb(0xC51);
-	byte &= 0x3F;
-	byte |= 0x80;		/* 7:6=10 */
-	outb(byte, 0xC51);
-
-	/* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
-	byte = inb(0xC52);
-	byte &= ~0x8;
-	outb(byte, 0xC52);
+static u8 calc_trange(u8 t_min, u8 t_max) {
+
+	u8 prev;
+	int i;
+	int diff = t_max - t_min;
+	
+	// walk through the trange table
+	for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) {
+		if( trange[i] < diff ) {
+			prev = i; // save last val
+			continue;
+		}
+		if( diff == trange[i] ) return i;
+		if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index
+		return i;
+	}		
+	return prev;
 }
 
 /********************************************************
-* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
+* sina uses SB600 GPIO9 to detect IDE_DMA66.
 * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
 * get the cable type, 40 pin or 80 pin?
 ********************************************************/
-static void get_ide_dma66(void)
+static void cable_detect(void)
 {
+
 	u8 byte;
 	struct device *sm_dev;
 	struct device *ide_dev;
-
-	printk(BIOS_INFO, "%s.\n", __func__);
+	
+	/* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */
+	printk(BIOS_DEBUG, "%s.\n", __func__);
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	byte = pci_read_config8(sm_dev, 0xA9);
 	byte |= (1 << 5);	/* Set Gpio9 as input */
 	pci_write_config8(sm_dev, 0xA9, byte);
-
+	
+	/* IDE Controller (Device 20, Function 1) on SB600 */
 	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+
+	byte = pci_read_config8(ide_dev, 9);
+	printk(BIOS_INFO, "IDE controller in %s Mode\n", byte & (1 << 0) ? "Native" : "Compatibility");
+
 	byte = pci_read_config8(ide_dev, 0x56);
 	byte &= ~(7 << 0);
-	if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+	if( pci_read_config8(sm_dev, 0xAA) & (1 << 5) )
 		byte |= 2 << 0;	/* mode 2 */
 	else
 		byte |= 5 << 0;	/* mode 5 */
+	printk(BIOS_INFO, "DMA mode %d selected\n", byte & (7 << 0));
 	pci_write_config8(ide_dev, 0x56, byte);
 }
 
-/*
- * set thermal config
+/**
+ * @brief Detect the ADT7475 device
+ *
+ * @param 
  */
-static void set_thermal_config(void)
+ 
+static const char * adt7475_detect( void ) {
+
+        int vendid, devid, devid2;
+        const char *name = NULL;
+		
+        vendid = adt7475_read_byte(REG_VENDID);
+        devid2 = adt7475_read_byte(REG_DEVID2);
+        if (vendid != 0x41 ||           /* Analog Devices */
+            (devid2 & 0xf8) != 0x68) {
+                return name;
+		}
+
+        devid = adt7475_read_byte(REG_DEVID);
+        if (devid == 0x73)
+                name = "adt7473";
+        else if (devid == 0x75 && adt7475_address == 0x2e)
+                name = "adt7475";
+        else if (devid == 0x76)
+                name = "adt7476";
+        else if ((devid2 & 0xfc) == 0x6c)
+                name = "adt7490";
+ 
+        return name;
+}
+
+// thermal control defaults
+const struct fan_control cpu_fan_control_defaults = {
+	.enable = 0, // disable by default
+	.polarity = 0, // high by default
+	.t_min = 3, // default = 45?C
+	.t_max = 7, // 65?C
+	.pwm_min = 1, // default dutycycle = 30%
+	.pwm_max = 13, // 90%
+};
+const struct fan_control case_fan_control_defaults = {
+	.enable = 0, // disable by default
+	.polarity = 0, // high by default
+	.t_min = 2, // default = 40?C
+	.t_max = 8, // 70?C
+	.pwm_min = 0, // default dutycycle = 25%
+	.pwm_max = 13, // 90%
+};
+
+static void pm_init( void )
 {
-	u8 byte;
 	u16 word;
-	device_t sm_dev;
-
-	/* set ADT 7461 */
-	ADT7461_write_byte(0x0B, 0x50);	/* Local Temperature Hight limit */
-	ADT7461_write_byte(0x0C, 0x00);	/* Local Temperature Low limit */
-	ADT7461_write_byte(0x0D, 0x50);	/* External Temperature Hight limit  High Byte */
-	ADT7461_write_byte(0x0E, 0x00);	/* External Temperature Low limit High Byte */
-
-	ADT7461_write_byte(0x19, 0x55);	/* External THERM limit */
-	ADT7461_write_byte(0x20, 0x55);	/* Local THERM limit */
-
-	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
-	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
-	printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+	u8 byte; 
+	device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
-	/* sb600 settings for thermal config */
 	/* set SB600 GPIO 64 to GPIO with pull-up */
 	byte = pm2_ioread(0x42);
 	byte &= 0x3f;
 	pm2_iowrite(0x42, byte);
 
-	/* set GPIO 64 to input */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	/* set GPIO 64 to tristate */
 	word = pci_read_config16(sm_dev, 0x56);
 	word |= 1 << 7;
 	pci_write_config16(sm_dev, 0x56, word);
@@ -163,41 +423,477 @@
 	byte = pm_ioread(0x3c);
 	byte &= 0xf3;
 	pm_iowrite(0x3c, byte);
+	
+	/* set GPM5 to not wake from s5 */
+	byte = pm_ioread(0x77);
+	byte &= ~(1 << 5);
+	pm_iowrite(0x77, byte);
+}
+
+ /**
+ * @brief Setup thermal config on SINA Mainboard
+ *
+ * @param 
+ */
+
+static void set_thermal_config(void)
+{
+	u8 byte, byte2;
+	u8 cpu_pwm_conf, case_pwm_conf;
+	device_t sm_dev;
+	struct fan_control cpu_fan_control, case_fan_control;
+	const char *name = NULL;
+	
+		
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE
+	
+	if( (name = adt7475_detect()) == NULL ) {
+		printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address);
+		return;
+	}
+	printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address);
+	
+	cpu_fan_control = cpu_fan_control_defaults;
+	case_fan_control = case_fan_control_defaults;
+
+	if( get_option(&byte, "cpu_fan_control") == -4 ) {
+		printk(BIOS_WARNING, "%s: CMOS checksum invalid, keeping default values\n",__func__);
+	} else {
+		// get all the options needed
+		if( get_option(&byte, "cpu_fan_control") == 0 )
+			cpu_fan_control.enable = byte ? 1 : 0;
+			
+		get_option(&cpu_fan_control.polarity, "cpu_fan_polarity");
+		get_option(&cpu_fan_control.t_min, "cpu_t_min");
+		get_option(&cpu_fan_control.t_max, "cpu_t_max");
+		get_option(&cpu_fan_control.pwm_min, "cpu_dutycycle_min");
+		get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max");
+
+		if( get_option(&byte, "chassis_fan_control") == 0)
+			case_fan_control.enable = byte ? 1 : 0;		
+		get_option(&case_fan_control.polarity, "chassis_fan_polarity");	
+		get_option(&case_fan_control.t_min, "chassis_t_min");
+		get_option(&case_fan_control.t_max, "chassis_t_max");
+		get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min");
+		get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max");
+	
+	}
+
+	printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable");
+	printk(BIOS_DEBUG, " cpu_fan_polarity:%s", cpu_fan_control.polarity ? "low" : "high");
+
+	printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min));
+	cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min);
+	
+	printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max));
+	cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max);
+	
+	printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min));
+	cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min);
+	
+	printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max));
+	cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max);
+	
+	cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max);
+	printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range);
+	cpu_fan_control.t_range <<= 4;
+	cpu_fan_control.t_range |= (4 << 0); // 35.3Hz
+	
+	printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable");
+	printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high");
+
+	printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min));
+	case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min);
+	
+	printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max));
+	case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max);
+	
+	printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min));
+	case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min);
+	
+	printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max));
+	case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max);
+	
+	case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max);
+	printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range);
+	case_fan_control.t_range <<= 4;
+	case_fan_control.t_range |= (4 << 0); // 35.3Hz
+	
+	cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
+	case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
+	cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5);  // manual control 
+	case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp
+	
+	/* set adt7475 */
+
+	adt7475_write_byte(REG_CONFIG1, 0x04);  // clear register, bit 2 is read only
+	
+	/* Config Register 6:  */
+	adt7475_write_byte(REG_CONFIG6, 0x00);
+	/* Config Register 7 */
+	adt7475_write_byte(REG_CONFIG7, 0x00);
+
+	/* Config Register 5: */
+	/* set Offset 64 format, enable THERM on Remote 1& Local */
+	adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60); 
+	/* No offset for remote 1 */
+	adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00);
+	/* No offset for local */
+	adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00);
+	/* No offset for remote 2 */
+	adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00);
+	
+	/* remote 1 low temp limit */
+	adt7475_write_byte(TEMP_MIN_REG(0), 0x00);
+	/* remote 1 High temp limit    (90C) */
+	adt7475_write_byte(TEMP_MAX_REG(0), 0x9a);
+
+	/* local Low Temp Limit */
+	adt7475_write_byte(TEMP_MIN_REG(1), 0x00);
+	/* local High Limit    (90C) */
+	adt7475_write_byte(TEMP_MAX_REG(1), 0x9a);
+
+	/*  remote 1 therm temp limit    (95C) */
+	adt7475_write_byte(TEMP_THERM_REG(0), 0x9f);
+	/* local therm temp limit    (95C) */
+	adt7475_write_byte(TEMP_THERM_REG(1), 0x9f);
+	
+	/* PWM 1 configuration register    CPU fan controlled by CPU Thermal Diode */
+	adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf);
+	/* PWM 3 configuration register    Case fan controlled by ADTxxxx temp */
+	adt7475_write_byte(PWM_CONFIG_REG(2), case_pwm_conf);
+
+	if( cpu_fan_control.enable ) {
+		/* PWM 1 minimum duty cycle     (37%) */
+		adt7475_write_byte(PWM_MIN_REG(0), cpu_fan_control.pwm_min);
+		/* PWM 1 Maximum duty cycle    (100%) */
+		adt7475_write_byte(PWM_MAX_REG(0), cpu_fan_control.pwm_max);
+		/*  Remote 1 temperature Tmin     (32C) */
+		adt7475_write_byte(TEMP_TMIN_REG(0), cpu_fan_control.t_min);
+		/* remote 1 Trange            (53C ramp range) */
+		adt7475_write_byte(TEMP_TRANGE_REG(0), cpu_fan_control.t_range);
+	} else {
+		adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max);
+	}
+	
+	if( case_fan_control.enable ) {
+		/* PWM 2 minimum duty cycle     (37%) */
+		adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min);
+		/* PWM 2 Maximum Duty Cycle    (100%) */
+		adt7475_write_byte(PWM_MAX_REG(2), case_fan_control.pwm_max);
+		/* local temperature Tmin     (32C) */
+		adt7475_write_byte(TEMP_TMIN_REG(1), case_fan_control.t_min);
+		/* local Trange            (53C ramp range) */
+		adt7475_write_byte(TEMP_TRANGE_REG(1), case_fan_control.t_range); // Local TRange
+		adt7475_write_byte(TEMP_TRANGE_REG(2), case_fan_control.t_range); // PWM2 Freq
+	} else {
+		adt7475_write_byte(PWM_REG(2), case_fan_control.pwm_max);
+	}
+
+	/* Config Register 3 - enable smbalert & therm */
+	adt7475_write_byte(0x78, 0x03);
+	/* Config Register 4 - enable therm output */
+	adt7475_write_byte(0x7d, 0x09);
+	/* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */
+	adt7475_write_byte(0x75, 0x2e);
+	
+	/* Config Register 1 Set Start bit */
+	adt7475_write_byte(0x40, 0x05);
+	
+	/* Read status register to clear any old errors */
+	byte2 = adt7475_read_byte(0x42);
+	byte = adt7475_read_byte(0x41);
+
+	printk(BIOS_DEBUG, "Init 'Thermal Monitor' end , status 0x42 = 0x%02x, status 0x41 = 0x%02x\n",
+		    byte2, byte);
+
+}
+
+ /**
+ * @brief 
+ *
+ * @param 
+ */
+
+static void patch_mmio_nonposted( void )
+{
+	unsigned reg, index;		
+	resource_t rbase, rend;
+	u32 base, limit;
+	struct resource *resource;
+	device_t dev;
+	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));
+	
+	printk(BIOS_DEBUG,"%s ...\n", __func__);
+
+	dev = dev_find_slot(1, PCI_DEVFN(5,0));
+	// the uma frame buffer
+	index = 0x10;
+	resource = probe_resource(dev, index);
+	if( resource ) {
+		// fixup resource nonposted in k8 mmio
+		/* Get the base address */
+		rbase = (resource->base >> 8) & ~(0xff);
+		/* Get the limit (rounded up) */
+		rend  = (resource_end(resource) >> 8) & ~(0xff);
+	
+		printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend);
+
+		for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
+			base = pci_read_config32(k8_f1,reg);
+			limit = pci_read_config32(k8_f1,reg+4);
+			printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit);
+			if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) {
+				limit |= (1 << 7); 
+				printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit);
+				pci_write_config32(k8_f1, reg+4, limit); 
+				break;
+			}
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+}
+
+ /**
+ * @brief 
+ *
+ * @param 
+ */
+ 
+static void wait_pepp( void ) {
+
+	int boot_delay = 0;
+	
+	if( get_option(&boot_delay, "boot_delay") < 0)
+		boot_delay = 5;
+		
+	printk(BIOS_DEBUG, "boot_delay = %d sec\n", boot_delay);
+	if ( boot_delay > 0 ) {
+		init_timer();
+		// wait for PEPP-Board 
+		printk(BIOS_INFO, "Give PEPP-Board %d sec(s) time to coming up ", boot_delay);
+		while ( boot_delay ) {
+			lapic_write(LAPIC_TMICT, 0xffffffff);
+			udelay(1000000); // delay time approx. 1 sec
+			printk(BIOS_INFO, ".");
+			boot_delay--;
+		}
+		printk(BIOS_INFO, "\n");
+	}
+}
+
+ /**
+ * @brief 
+ *
+ * @param 
+ */
+
+struct {
+	unsigned int bus;
+	unsigned int devfn;
+} slot[] = {
+	{0, PCI_DEVFN(0,0)},
+	{0, PCI_DEVFN(18,0)},
+	{0, PCI_DEVFN(19,0)},{0, PCI_DEVFN(19,1)},{0, PCI_DEVFN(19,2)},{0, PCI_DEVFN(19,3)},{0, PCI_DEVFN(19,4)},{0, PCI_DEVFN(19,5)},
+	{0, PCI_DEVFN(20,0)},{0, PCI_DEVFN(20,1)},{0, PCI_DEVFN(20,2)},{0, PCI_DEVFN(20,3)},{0, PCI_DEVFN(20,5)},{0, PCI_DEVFN(20,6)},
+	{0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)},
+	{255,0},
+};
+ 
+
+static void update_subsystemid( device_t dev ) {
+
+	int i;
+	struct mainboard_config *mb = dev->chip_info;
+	
+	dev->subsystem_vendor = 0x110a;
+	if( mb->plx_present ){
+		dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077
+	} else {
+		dev->subsystem_device = 0x4077; // U1P0 = 0x4077
+	}
+	printk(BIOS_INFO, "%s [%x/%x]\n", dev->chip_ops->name, dev->subsystem_vendor, dev->subsystem_device );
+	for( i=0; slot[i].bus < 255; i++) {
+		device_t d;
+		d = dev_find_slot(slot[i].bus,slot[i].devfn);
+		if( d ) {
+			printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device);
+			d->subsystem_device = dev->subsystem_device;
+		}
+	}
+}
+
+ /**
+ * @brief 
+ *
+ * @param 
+ */
 
-	/* THERMTRIP pin */
-	/* byte = pm_ioread(0x68);
-	 * byte |= 1 << 3;
-	 * pm_iowrite(0x68, byte);
-	 *
-	 * byte = pm_ioread(0x55);
-	 * byte |= 1 << 0;
-	 * pm_iowrite(0x55, byte);
-	 *
-	 * byte = pm_ioread(0x67);
-	 * byte &= ~( 1 << 6);
-	 * pm_iowrite(0x67, byte);
+static void detect_hw_variant( device_t dev ) {
+
+	device_t nb_dev =0, dev2 = 0;
+	struct southbridge_amd_rs690_config *cfg;
+	u32 lc_state, id = 0;
+	struct mainboard_config *mb = dev->chip_info;
+	
+	printk(BIOS_INFO, "Scan for PLX device ...\n");
+	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	if (!nb_dev) {
+		die("CAN NOT FIND RS690 DEVICE, HALT!\n");
+		/* NOT REACHED */
+	}
+
+	dev2 = dev_find_slot(0, PCI_DEVFN(2, 0));
+	if (!dev2) {
+		die("CAN NOT FIND GFX DEVICE 2, HALT!\n");
+		/* NOT REACHED */
+	}
+	PcieReleasePortTraining(nb_dev, dev2, 2); // we assume PLX is connected to port 2
+
+	mdelay(40);
+	lc_state = nbpcie_p_read_index(dev2, 0xa5);	/* lc_state */
+	printk(BIOS_DEBUG, "lc current state=%x\n", lc_state);
+	/* LC_CURRENT_STATE = bit0-5 */
+	switch( lc_state & 0x3f ){
+	case 0x00:
+	case 0x01:
+	case 0x02:
+	case 0x03:
+	case 0x04:
+		printk(BIOS_NOTICE, "No device present, skipping PLX scan ..\n");
+		break;
+	case 0x07:
+	case 0x10:
+	{
+		struct device dummy;
+		u32 pci_primary_bus, buses;
+		u16 secondary, subordinate;
+		
+		printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID));		
+		// save the existing primary/secondary/subordinate bus number configuration.
+		secondary = dev2->bus->secondary;
+		subordinate = dev2->bus->subordinate;
+		buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS);
+
+		// Configure the bus numbers for this bridge
+		// bus number 1 is for internal gfx device, so we start with busnumber 2 
+
+		buses &= 0xff000000;
+		buses |= ((2 << 8) | (0xff << 16));
+		// setup the buses in device 2		
+		pci_write_config32(dev2,PCI_PRIMARY_BUS, buses);
+
+		// fake a device descriptor for a device behind device 2
+		dummy.bus = dev2->bus;
+		dummy.bus->secondary = (buses >> 8) & 0xff;
+		dummy.bus->subordinate = (buses >> 16) & 0xff;
+		dummy.path.type = DEVICE_PATH_PCI;
+		dummy.path.pci.devfn = PCI_DEVFN(0,0); // PLX: device number 0, function 0
+
+		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
+		/* Have we found something?
+		 * Some broken boards return 0 if a slot is empty, but
+		 * the expected answer is 0xffffffff
+		 */	
+		if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) {
+			printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id);
+		} else {
+			printk(BIOS_DEBUG, "found device [%x]\n", id);
+		}
+		// restore changes made for device 2
+		dev2->bus->secondary = secondary;
+		dev2->bus->secondary = subordinate;
+		pci_write_config32(dev2, PCI_PRIMARY_BUS, pci_primary_bus);
+	}
+		break;
+	default:
+		break;
+	}
+	
+	mb->plx_present = 0;	
+	if( id == PLX_VIDDID ){
+		printk(BIOS_INFO, "found PLX device\n");
+		mb->plx_present = 1;
+		cfg = (struct southbridge_amd_rs690_config *)dev2->chip_info;
+		if( cfg->gfx_tmds ) {
+			printk(BIOS_INFO, "Disable 'gfx_tmds' support\n");
+			cfg->gfx_tmds = 0;
+			cfg->gfx_link_width = 4;
+		}
+		return;
+	} 
+}
+
+static void smm_lock( void )
+{
+	/* LOCK the SMM memory window and enable normal SMM.
+	 * After running this function, only a full reset can
+	 * make the SMM registers writable again.
 	 */
+	printk(BIOS_DEBUG, "Locking SMM.\n");
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x69,
+			D_LCK | G_SMRAME | A_BASE_SEG);
+}
+
+ /**
+ * @brief Init
+ *
+ * @param the root device
+ */
+ 
+static void init(device_t dev)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
+	INT15_function_extensions int15_func;
+#endif
+	
+	printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
+		dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
+	
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
+	if(	get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 )
+		int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;
+	int15_func.regs.func05_TV_standard = TV_MODE_NO;
+	install_INT15_function_extensions(&int15_func);
+#endif
+	set_thermal_config();
+	pm_init();
+	cable_detect();
+	patch_mmio_nonposted();
+	smm_lock();
 }
 
 /*************************************************
-* enable the dedicated function in dbm690t board.
+* enable the dedicated function in sina board.
 * This function called early than rs690_enable.
 *************************************************/
-static void dbm690t_enable(device_t dev)
+static void enable_dev(device_t dev)
 {
-	printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
+	
+	printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
+		dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+	/* Install custom int15 handler for VGA OPROM */
+	int15_install();
+#endif
 
+	detect_hw_variant(dev);
+	update_subsystemid(dev);
+	
 #if (CONFIG_GFXUMA == 1)
+	{
 	msr_t msr, msr2;
-
+	
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
-	printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	printk(BIOS_DEBUG, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 		    __func__, msr.lo, msr.hi);
-
+	
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	
+	printk(BIOS_DEBUG, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 		    __func__, msr2.lo, msr2.hi);
 
 	switch (msr.lo) {
@@ -219,35 +915,50 @@
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	
 	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
+	}
 #else
-	uma_memory_size = 0x8000000;	/* 128M recommended UMA */
-	uma_memory_base = 0x38000000;	/* 1GB  system memory supposed */
+	uma_memory_size = 0;
+	uma_memory_base = 0;
 #endif
 
-	enable_onboard_nic();
-	get_ide_dma66();
-	set_thermal_config();
+	wait_pepp();
+	dev->ops->init = init;  // rest of mainboard init later   
 }
 
+ /**
+ * @brief 
+ *
+ * @param 
+ */
+
 int add_mainboard_resources(struct lb_memory *mem)
 {
+	device_t dev;
+	struct resource *res;
+	
+	dev = dev_find_slot(0, PCI_DEVFN(0,0));
+	res = probe_resource(dev, 0x1C);
+	if( res ) {
+		printk(BIOS_INFO, "mmconf: base=%0llx size=%0llx\n", res->base, res->size);
+		lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size);
+	}
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
 #if (CONFIG_GFXUMA == 1)
 	printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
 	uma_memory_base, uma_memory_size);
-	lb_add_memory_range(mem, LB_MEM_RESERVED,
-		uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size);
 #endif
 	return 0;
 }
 
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("AMD DBM690T   Mainboard")
-	.enable_dev = dbm690t_enable,
+	CHIP_NAME(CONFIG_MAINBOARD_PART_NUMBER)
+	.enable_dev = enable_dev,
 };

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/mptable.c	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/mptable.c	Wed May 11 09:47:43 2011	(r6567)
@@ -23,135 +23,50 @@
 #include <arch/io.h>
 #include <string.h>
 #include <stdint.h>
+
 #include <cpu/amd/amdk8_sysconf.h>
 
+extern u8 bus_isa;
 extern u8 bus_rs690[8];
 extern u8 bus_sb600[2];
 
 extern u32 apicid_sb600;
 
+extern u32 bus_type[256];
 extern u32 sbdn_rs690;
 extern u32 sbdn_sb600;
 
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	int bus_isa;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
+	int isa_bus;
+	
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	mptable_init(mc, LAPIC_ADDR);
-
 	smp_write_processors(mc);
 
 	get_bus_conf();
+	printk(BIOS_DEBUG, "%s: bus_isa=%d, apic_id=0x%x\n", __func__, bus_isa, apicid_sb600);
 
-	mptable_write_buses(mc, NULL, &bus_isa);
-
+	mptable_write_buses(mc, NULL, &isa_bus);
+	if (isa_bus != bus_isa) {
+		printk(BIOS_ERR, "ISA bus numbering schemes differ! Please fix mptable.c\n");
+	}
 	/* I/O APICs:   APIC ID Version State   Address */
 	{
 		device_t dev;
-		u32 dword;
-		u8 byte;
 
-		dev =
-		    dev_find_slot(bus_sb600[0],
-				  PCI_DEVFN(sbdn_sb600 + 0x14, 0));
+		dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0));
 		if (dev) {
-			dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
-			smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
-
-			/* Initialize interrupt mapping */
-			/* aza */
-			byte = pci_read_config8(dev, 0x63);
-			byte &= 0xf8;
-			byte |= 0;	/* 0: INTA, ...., 7: INTH */
-			pci_write_config8(dev, 0x63, byte);
-
-			/* SATA */
-			dword = pci_read_config32(dev, 0xac);
-			dword &= ~(7 << 26);
-			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
-			pci_write_config32(dev, 0xac, dword);
-
-			/*
-			 * 00:12.0: PROG SATA : INT F
-			 * 00:13.0: INTA USB_0
-			 * 00:13.1: INTB USB_1
-			 * 00:13.2: INTC USB_2
-			 * 00:13.3: INTD USB_3
-			 * 00:13.4: INTC USB_4
-			 * 00:13.5: INTD USB2
-			 * 00:14.1: INTA IDE
-			 * 00:14.2: Prog HDA : INT E
-			 * 00:14.5: INTB ACI
-			 * 00:14.6: INTB MCI
-			 */
+			struct resource *res;
+			res = find_resource(dev, 0x74);
+			smp_write_ioapic(mc, apicid_sb600, 0x20, res->base);
 		}
 	}
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
-#define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
-
-	/* usb */
-	PCI_INT(0x0, 0x13, 0x0, 0x10);
-	PCI_INT(0x0, 0x13, 0x1, 0x11);
-	PCI_INT(0x0, 0x13, 0x2, 0x12);
-	PCI_INT(0x0, 0x13, 0x3, 0x13);
-
-	/* sata */
-	PCI_INT(0x0, 0x12, 0x0, 0x16);
-
-	/* HD Audio: b0:d20:f1:reg63 should be 0. */
-	PCI_INT(0x0, 0x14, 0x0, 0x10);
-
-	/* on board NIC & Slot PCIE.  */
-	PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
-	PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
-	PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
-	PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
-	PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
-	PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
-	PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
-	PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
-
-	/* PCI slots */
-	/* PCI_SLOT 0. */
-	PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
-
-	/* PCI_SLOT 1. */
-	PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
-
-	/* PCI_SLOT 2. */
-	PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
 
 	/* Compute the checksums */
 	mc->mpe_checksum =
@@ -162,9 +77,19 @@
 	return smp_next_mpe_entry(mc);
 }
 
+static void fixup_virtual_wire(void *v)
+{
+        struct intel_mp_floating *mf = v;
+
+        mf->mpf_checksum = 0;
+        mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
+        mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
+}
+
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
 	v = smp_write_floating_table(addr);
+	fixup_virtual_wire(v);
 	return (unsigned long)smp_write_config_table(v);
 }

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/resourcemap.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/resourcemap.c	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/resourcemap.c	Wed May 11 09:47:43 2011	(r6567)
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-static void setup_dbm690t_resource_map(void)
+static void setup_sitemp_resource_map(void)
 {
 	static const unsigned int register_values[] = {
 		/* Careful set limit registers before base registers which contain the enables */

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c	Tue May 10 23:53:13 2011	(r6565)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c	Wed May 11 09:47:43 2011	(r6567)
@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,10 +18,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
-
+ 
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
+#define DIMM0 0x50
+#define DIMM1 0x51
+
+#define ICS951462_ADDRESS	0x69
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -31,25 +37,36 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
+
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/early_serial.c"
-#include <spd.h>
-#include <usbdebug.h>
+
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
+
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+
 #include "southbridge/amd/rs690/early_setup.c"
 #include "southbridge/amd/sb600/early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
-static void memreset(int controllers, const struct mem_controller *ctrl) { }
-static void activate_spd_rom(const struct mem_controller *ctrl) { }
+/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
 
+/* called in raminit_f.c */
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+/*called in raminit_f.c */
 static inline int spd_read_byte(u32 device, u32 address)
 {
 	return smbus_read_byte(device, address);
@@ -67,6 +84,135 @@
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
+#define __WARNING__(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
+#define __DEBUG__(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
+#define __INFO__(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg)
+
+#if CONFIG_USE_OPTION_TABLE
+#define DUMP_CMOS_RAM 0
+static inline int cmos_error(void) {
+	unsigned char reg_d;
+	/* See if the cmos error condition has been flagged */
+	outb(0xd, 0x72);
+	reg_d = inb(0x73);
+#if DUMP_CMOS_RAM
+	__DEBUG__("RTC_VRT = %x\n", reg_d & RTC_VRT);
+#endif
+	return (reg_d & RTC_VRT) == 0;
+}
+
+static inline void set_chksum(int range_start, int range_end, int cks_loc)
+{
+	int addr;
+	unsigned sum;
+	sum = 0;
+	for( addr = range_start; addr <= range_end; addr++) {
+		outb(addr, 0x72);
+		sum += inb(0x73);
+	}
+	sum = ~(sum & 0x0ffff);
+	outb(cks_loc, 0x72);
+	outb(((sum >> 8) & 0x0ff),0x73);
+	outb(cks_loc+1,0x72);
+	outb((sum & 0x0ff),0x73);
+}
+
+static inline int cmos_chksum_valid(void) {
+	unsigned char addr, val;
+	unsigned long sum, old_sum;
+
+#if DUMP_CMOS_RAM
+	u8 i;
+	/* Compute the cmos checksum */
+	for (addr = 14, i = 0; addr < LB_CKS_RANGE_START; addr++,i++) {
+		outb(addr, 0x72);
+		val = inb(0x73);
+		if( i%16 == 0 ) __DEBUG__("%02x:", addr);
+		__DEBUG__(" %02x",val);
+		if( i%16 == 15 ) __DEBUG__("\n");
+	}
+#endif
+	sum = 0;
+	for(addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
+		outb(addr, 0x72);
+		val = inb(0x73);
+#if DUMP_CMOS_RAM
+		if( i%16 == 0 ) __DEBUG__("%02x:", addr);
+		__DEBUG__(" %02x",val);
+		if( i%16 == 15 ) __DEBUG__("\n");
+		i++;
+#endif
+		sum += val;
+	}
+#if DUMP_CMOS_RAM
+	__DEBUG__("\n");
+#endif
+	sum = (sum & 0xffff) ^ 0xffff;
+
+	/* Read the stored checksum */
+	outb(LB_CKS_LOC, 0x72);
+	old_sum = inb(0x73) << 8;
+	outb(LB_CKS_LOC+1, 0x72);
+	old_sum |=  inb(0x73);
+#if DUMP_CMOS_RAM
+	__DEBUG__("CMOS checksum: old = %lx, new = %lx\n", old_sum, sum);
+#endif
+	return sum == old_sum;
+}
+
+#include <cbfs.h>
+static inline void check_cmos( void ) {
+
+	char *cmos_default = NULL;
+	int i;
+#if DUMP_CMOS_RAM
+	u8 c = 0;
+#endif
+	if (cmos_error() || !cmos_chksum_valid()) {
+		cmos_default = cbfs_find_file("cmos.default", 0xaa);
+		if (cmos_default) {
+#if DUMP_CMOS_RAM
+			__DEBUG__("Write cmos default ...\n");
+#endif
+			outb(0x0a,0x72);
+			i = inb(0x73);
+			i &= ~(1 << 4);
+			outb(i,0x73);					
+
+			for (i = 14; i < 128; i++) {
+#if DUMP_CMOS_RAM
+				if( c%16 == 0 ) __DEBUG__("%02x:", i);
+				__DEBUG__(" %02x", (u8)cmos_default[i]);
+				if( c%16 == 15 ) __DEBUG__("\n");
+				c++;
+#endif
+				outb(i,0x72);
+				outb(cmos_default[i],0x73);
+			}
+
+#if DUMP_CMOS_RAM
+			__DEBUG__("\n");
+#endif
+			if( !cmos_chksum_valid() )
+				__DEBUG__("CMOS CHECKSUM ERROR\n");
+			/* Now reboot to run with default cmos. */
+			outb(0x06, 0xcf9);
+			for (;;) asm("hlt"); /* Wait for reset! */
+		} 
+	}
+
+	// update altcentury
+	outb(0x32, 0x72);
+	i = inb(0x73);
+	if ( i != 0x20 ) {
+		outb(0x20,0x73);
+		set_chksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC);
+	}
+
+}
+
+#endif
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
@@ -75,31 +221,41 @@
 	msr_t msr;
 	struct cpuid_result cpuid1;
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
+			
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
 		enumerate_ht_chain();
+
 		/* sb600_lpc_port80(); */
 		sb600_pci_port80();
 	}
 
-	if (bist == 0)
+	if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+	}
 
-	enable_rs690_dev8();
+	enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge
 	sb600_lpc_init();
-
+#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)	
+	check_cmos();  // rebooting in case of corrupted cmos !!!!!	
+#endif	
 	/* it8712f_enable_serial does not use its 1st parameter. */
 	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+	it8712f_kill_watchdog(); 
 
+	uart_init();
 	console_init();
-
+#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)
+	check_cmos();  // rebooting in case of corrupted cmos !!!!!		
+#endif
+	post_code(0x03);
+	
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
-	printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
+	__DEBUG__("bsp_apicid=0x%x\n", bsp_apicid);
 
-	setup_dbm690t_resource_map();
+	setup_sitemp_resource_map();
 
 	setup_coherent_ht_domain();
 
@@ -115,14 +271,17 @@
 	/* run _early_setup before soft-reset. */
 	rs690_early_setup();
 	sb600_early_setup();
-
+	
+	post_code(0x04);
+	
 	/* Check to see if processor is capable of changing FIDVID  */
 	/* otherwise it will throw a GP# when reading FIDVID_STATUS */
 	cpuid1 = cpuid(0x80000007);
-	if ((cpuid1.edx & 0x6) == 0x6) {
+	if( (cpuid1.edx & 0x6) == 0x6 ) {
+
 		/* Read FIDVID_STATUS */
 		msr=rdmsr(0xc0010042);
-		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		__DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
 		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -130,31 +289,47 @@
 
 		/* show final fid and vid */
 		msr=rdmsr(0xc0010042);
-		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		__DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
 	} else {
-		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
+		__DEBUG__("Changing FIDVID not supported\n");
 	}
-
+	
+	post_code(0x05);
+	
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	rs690_htinit();
-	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
-
+	__DEBUG__("needs_reset=0x%x\n", needs_reset);
+	
+	post_code(0x06);
+	
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		__INFO__("ht reset -\n");
 		soft_reset();
 	}
 
 	allow_all_aps_stop(bsp_apicid);
 
 	/* It's the time to set ctrl now; */
-	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
+	__DEBUG__("sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	
+	post_code(0x07);
+	
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-	rs690_before_pci_init();
+	
+	post_code(0x08);
+	
+	rs690_before_pci_init(); // does nothing
 	sb600_before_pci_init();
+	
+#if CONFIG_USE_OPTION_TABLE	
+	if( read_option(CMOS_VSTART_cmos_defaults_loaded, CMOS_VLEN_cmos_defaults_loaded, 0) )
+		__WARNING__("WARNING: CMOS DEFAULTS LOADED. PLEASE CHECK CMOS OPTION \"cmos_default_loaded\" !\n"); 
+#endif
 
 	post_cache_as_ram();
 }
+



From patrick at georgi-clan.de  Wed May 11 09:50:33 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 11 May 2011 09:50:33 +0200
Subject: [coreboot] support for siemens sitemp mainboard
In-Reply-To: <4DC97747.7070107@arcor.de>
References: <4DC97747.7070107@arcor.de>
Message-ID: <cd31e83ff87a81b6425dfb2463491ad1@mail.georgi-clan.de>

On Tue, 10 May 2011 19:35:03 +0200, Josef Kellermann wrote:
>  I adapt the code from the dbm690t according to customer requirement
> specification.
I copied amd/dbm690t first as a base, to preserve history. I hope 
that's okay.

>  I've been testing Linux as well as Windows XP booting on this board.
First, thank you for all your work to get this board running with 
coreboot.
Second, sorry that it took so long - you've been sending more patches 
than should have been necessary to get this in.

I had to change a couple of things for integrating the changes properly 
with a current tree:
- GENERATE_ACPI_TABLES -> HAVE_ACPI_TABLES in Kconfig
- Dropped cmos.default in Makefile.inc. Remedy: Enable 
CONFIG_HAVE_CMOS_DEFAULT and src/pc80/Makefile.inc will pick it up. This 
is necessary because otherwise our autobuilder fails (as there is no 
cmos.default file to use).
- updated mptable.c a bit: Use of mptable_init (which changes mpc_oem 
and mpc_productid, if you depend on these, please review!), 
mptable_write_buses instead of mptable_write_bus (which might change ISA 
bus numbering, look in the serial log, coreboot will complain in that 
case). These were necessary because the mptable APIs changed since you 
branched off of dbm690t.

I've seen more things that could/should be done, but these were the 
critical bits.

Committed as r6567.


Regards,
Patrick



From hamo.by at gmail.com  Wed May 11 14:51:45 2011
From: hamo.by at gmail.com (Hamo)
Date: Wed, 11 May 2011 20:51:45 +0800
Subject: [coreboot] Ok, let's move on. What shold we do to CBFS?
Message-ID: <BANLkTint3JxTZtHcGWzhQLXFPwdqLjekHQ@mail.gmail.com>

Dear lists,
I have got the idea on how to deal with xcompile script for ARM. Now,
let's move on to CBFS.
It is one of the most difficult part since CBFS is almost hard-coded
to X86 architecture. On ARM,
we need CBFS like this:


/---------------\ <-- Start of ROM
| /-----------\ |
| | Reset  | | <- 0x0
| |-----------| |
| |IVs      | |
| |-----------| |
| |Boot    | |
| |Block   | |
| \-----------/ |
|               |
| /-----------\ | --|
| | Header| |   |
| |-----------| |   |
| | Name  | |   |
| |-----------| |   |-- Component
| |Data    | |   |
| |..         | |   |
| \-----------/ | --|
|               |
| ...           |
| /-----------\ | --|
| | Header| |   |
| |-----------| |   |
| | Name  | |   |
| |-----------| |   |-- Component
| |Data    | |   |
| |..         | |   |
| \-----------/ | --|
\---------------/


Where should we put the CBFS master header and the pointer to it?
I have no idea of how to implement it and not break it on X86
architecture. Any comment or suggestion is very welcome.



From vikram186 at gmail.com  Wed May 11 18:46:18 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Wed, 11 May 2011 22:16:18 +0530
Subject: [coreboot] Alternate for serial port debug messages
In-Reply-To: <BANLkTincQm_=e-ZY1uWAUh2eXDcEQi3xbA@mail.gmail.com>
References: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>
	<BANLkTincQm_=e-ZY1uWAUh2eXDcEQi3xbA@mail.gmail.com>
Message-ID: <BANLkTinzTqYRyLW9ceQDuHLEzHv47zQAQA@mail.gmail.com>

On Wed, May 11, 2011 at 12:55 AM, Corey Osgood <corey.osgood at gmail.com> wrote:
> On Tue, May 10, 2011 at 2:10 PM, Vikram Narayanan <vikram186 at gmail.com> wrote:
>> Hi,
>>
>> I am using a DELL laptop. The superio used is
>> "Found Nuvoton WPCE775x / NPCE781x (id=0x03, rev=0x06) at 0x4e".
>>
>> Now the thing is there are no serial ports exposed outside in my laptop.
>> Is there any other way out to see the debug messages of coreboot.(If at
>> all coreboot supports my motherboard, or if I am planning to try if its
>> not there)
>
> Check lspci -v, you probably have a USB port that has debug port
> capability. You'll then need a USB debug cable.
I have an USB port that has debug capabilities (according to the lspci output)
Should I buy the one mentioned in this page
http://www.coreboot.org/EHCI_Debug_Port
or can I use a normal cable to debug?

-
Thanks
Vikram



From peter at stuge.se  Thu May 12 02:05:00 2011
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 May 2011 02:05:00 +0200
Subject: [coreboot] Hi from LinuxTag 2011
Message-ID: <20110512000501.14895.qmail@stuge.se>

Greetings from Berlin!


//Peter
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From wangqingpei at gmail.com  Thu May 12 05:11:31 2011
From: wangqingpei at gmail.com (Qing Pei Wang)
Date: Thu, 12 May 2011 11:11:31 +0800
Subject: [coreboot] Hi from LinuxTag 2011
In-Reply-To: <20110512000501.14895.qmail@stuge.se>
References: <20110512000501.14895.qmail@stuge.se>
Message-ID: <BANLkTim1c3h6__zEFJrXPg56ksh+hfz-CQ@mail.gmail.com>

Con...
great...
Best wishes
Wang Qing Pei
Phone: 86+018930528086


On Thu, May 12, 2011 at 8:05 AM, Peter Stuge <peter at stuge.se> wrote:

> Greetings from Berlin!
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From svn at coreboot.org  Thu May 12 08:53:53 2011
From: svn at coreboot.org (repository service)
Date: Thu, 12 May 2011 08:53:53 +0200
Subject: [coreboot] [commit] r6568 - trunk/src/mainboard/siemens/sitemp_g1p1
Message-ID: <E1QKPmT-0005ET-00@ra.coresystems.de>

Author: oxygene
Date: Thu May 12 08:53:52 2011
New Revision: 6568
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6568

Log:
Remove uart_init() in Siemens sitemp-g1p1

uart_init() was moved to common code in r6531, but I
missed that when integrating the new mainboard code.

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c
==============================================================================
--- trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c	Wed May 11 09:47:43 2011	(r6567)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c	Thu May 12 08:53:52 2011	(r6568)
@@ -244,7 +244,6 @@
 	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog(); 
 
-	uart_init();
 	console_init();
 #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)
 	check_cmos();  // rebooting in case of corrupted cmos !!!!!		



From seppk at arcor.de  Thu May 12 15:16:41 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Thu, 12 May 2011 15:16:41 +0200
Subject: [coreboot] read_option() in sitemp_g1p1/romstage.c
Message-ID: <4DCBDDB9.3080406@arcor.de>

attached patch changes read_option() in 
mainboard/siemens/sitemp_g1p1/romstage.c.

Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
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From patrick at georgi-clan.de  Thu May 12 17:40:38 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 12 May 2011 17:40:38 +0200
Subject: [coreboot] read_option() in sitemp_g1p1/romstage.c
In-Reply-To: <4DCBDDB9.3080406@arcor.de>
References: <4DCBDDB9.3080406@arcor.de>
Message-ID: <4DCBFF76.6040603@georgi-clan.de>

Am 12.05.2011 15:16, schrieb Josef Kellermann:
> attached patch changes read_option() in 
> mainboard/siemens/sitemp_g1p1/romstage.c.
Argh, I fixed that in an earlier iteration of managing the patch. Thanks!

> Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>


Patrick
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From mbertens at xs4all.nl  Thu May 12 21:54:49 2011
From: mbertens at xs4all.nl (Marc Bertens)
Date: Thu, 12 May 2011 21:54:49 +0200
Subject: [coreboot] Hi from LinuxTag 2011
In-Reply-To: <20110512000501.14895.qmail@stuge.se>
References: <20110512000501.14895.qmail@stuge.se>
Message-ID: <1305230089.5022.0.camel@mbertens-desktop>

Looks good Peter :-)

Greetz
Marc 


On Thu, 2011-05-12 at 02:05 +0200, Peter Stuge wrote:

> Greetings from Berlin!
> 
> 
> //Peter
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


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From svn at coreboot.org  Fri May 13 08:25:16 2011
From: svn at coreboot.org (repository service)
Date: Fri, 13 May 2011 08:25:16 +0200
Subject: [coreboot] [commit] r6569 - trunk/src/mainboard/siemens/sitemp_g1p1
Message-ID: <E1QKloK-0007rK-Oy@ra.coresystems.de>

Author: oxygene
Date: Fri May 13 08:25:16 2011
New Revision: 6569
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6569

Log:
siemens/sitemp_g1p1: Adapt read_option() to latest changes

Signed-off-by: Josef Kellermann <seppk at arcor.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c

Modified: trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c
==============================================================================
--- trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c	Thu May 12 08:53:52 2011	(r6568)
+++ trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c	Fri May 13 08:25:16 2011	(r6569)
@@ -325,7 +325,7 @@
 	sb600_before_pci_init();
 	
 #if CONFIG_USE_OPTION_TABLE	
-	if( read_option(CMOS_VSTART_cmos_defaults_loaded, CMOS_VLEN_cmos_defaults_loaded, 0) )
+	if( read_option(cmos_defaults_loaded, 0) )
 		__WARNING__("WARNING: CMOS DEFAULTS LOADED. PLEASE CHECK CMOS OPTION \"cmos_default_loaded\" !\n"); 
 #endif
 



From cristi.magherusan at net.utcluj.ro  Fri May 13 16:36:28 2011
From: cristi.magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Fri, 13 May 2011 17:36:28 +0300 (EEST)
Subject: [coreboot] Hi from LinuxTag 2011
In-Reply-To: <20110512000501.14895.qmail@stuge.se>
References: <20110512000501.14895.qmail@stuge.se>
Message-ID: <54769.192.100.130.7.1305297388.squirrel@intranet.utcluj.ro>

?n Joi, Mai 12, 2011 3:05, Peter Stuge a scris:
> Greetings from Berlin!
>
I'll join you guys tomorrow, if you're still there.

Regards,
Cristian




From smath at opal7.fsnet.co.uk  Fri May 13 17:59:18 2011
From: smath at opal7.fsnet.co.uk (Stephen Matthews)
Date: Fri, 13 May 2011 16:59:18 +0100
Subject: [coreboot] Hi from LinuxTag 2011
In-Reply-To: <20110512000501.14895.qmail@stuge.se>
References: <20110512000501.14895.qmail@stuge.se>
Message-ID: <4DCD5556.8080702@opal7.fsnet.co.uk>

What Mini-ITX motherboard is it in the first picture? It doesn't look
like any in the supported hardware list at coreboot.org.

Steve



From peter at stuge.se  Fri May 13 18:46:46 2011
From: peter at stuge.se (Peter Stuge)
Date: Fri, 13 May 2011 18:46:46 +0200
Subject: [coreboot] Hi from LinuxTag 2011
In-Reply-To: <54769.192.100.130.7.1305297388.squirrel@intranet.utcluj.ro>
References: <20110512000501.14895.qmail@stuge.se>
	<54769.192.100.130.7.1305297388.squirrel@intranet.utcluj.ro>
Message-ID: <20110513164646.18985.qmail@stuge.se>

Cristi Magherusan wrote:
> > Greetings from Berlin!
> 
> I'll join you guys tomorrow, if you're still there.

We will be here. Hall 7.2b booth 112 (next to Open Source Arena)

Looking forward to meeting you!


//Peter



From peter at stuge.se  Fri May 13 18:56:55 2011
From: peter at stuge.se (Peter Stuge)
Date: Fri, 13 May 2011 18:56:55 +0200
Subject: [coreboot] Hi from LinuxTag 2011
In-Reply-To: <4DCD5556.8080702@opal7.fsnet.co.uk>
References: <20110512000501.14895.qmail@stuge.se>
	<4DCD5556.8080702@opal7.fsnet.co.uk>
Message-ID: <20110513165655.19960.qmail@stuge.se>

Stephen Matthews wrote:
> What Mini-ITX motherboard is it in the first picture?

It's the ASRock E350M1 board that Scott has doing a marvellous job
with!


> It doesn't look like any in the supported hardware list at
> coreboot.org.

Yes, the board is actually in the list. It's very reasonably priced,
includes everything but DDR3 RAM on the board, costs 80-90 EUR,
DirectX 11 Pixel Shader 5.0 graphics, and the AMD E350 APU.

Visitors are indeed drooling all over the board here! Lots of fun. :)


//Peter



From thomas.jourdan at gmail.com  Fri May 13 17:57:45 2011
From: thomas.jourdan at gmail.com (Thomas JOURDAN)
Date: Fri, 13 May 2011 17:57:45 +0200
Subject: [coreboot] Win7 on Intel Eagle Heights
Message-ID: <BANLkTi=C0jFmaSLneHAFvYoURepiZoFt6Q@mail.gmail.com>

Hi guys

I'm trying to get Windows 7 booting on my Intel Eagle Heights evaluation
board. I tried to follow all the ACPI tips to get Window$ to boot but I
can't figure out the bug I'm facing. I'm using a checked build version of
Win 7 64-bits. When I start the installer, the first text screen is ok
(windows is copying files...) then it switches to graphics mode (green
progress bar with logo). Less than a second after switching from text to
graphics mode : BSOD.

With windbg I tried to dump as much as possible and the analyser tell me a
write operation occured at an invalid address. According to the stack frame,
the error occured in PowerPolicyProcessEvent when the kernel starts all
devices (enter D0 state).

Does the device states only applies to PCI devices, or all devices ? How can
I know which device causes this problem ? I can't even figure out if it's an
ACPI related problem, or something wrong in a device initialization
function.

Regards,
Thomas
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Microsoft (R) Windows Debugger Version 6.12.0002.633 X86
Copyright (c) Microsoft Corporation. All rights reserved.

Opened \\.\com1
Waiting to reconnect...
Connected to Windows 7 7600 x64 target at (Fri May 13 17:06:50.237 2011 (UTC + 2:00)), ptr64 TRUE
Kernel Debugger connection established.
Symbol search path is: C:\Symbols
Executable search path is: 
Windows 7 Kernel Version 7600 MP (1 procs) Checked x64
Built by: 7600.16385.amd64chk.win7_rtm.090713-1255
Machine Name:
Kernel base = 0xfffff800`0cc00000 PsLoadedModuleList = 0xfffff800`0d346e50
System Uptime: not available
NTOSPNP:Unable to setup Arbiter and Translators
NTOSPNP:IopAllocateBootResourcesInternal: Failed with status = C0000001

*** Fatal System Error: 0x0000000a
                       (0x0000000000000008,0x0000000000000002,0x0000000000000001,0xFFFFF8000CC8230B)

Break instruction exception - code 80000003 (first chance)

A fatal system error has occurred.
Debugger entered on first try; Bugcheck callbacks have not been invoked.

A fatal system error has occurred.

Connected to Windows 7 7600 x64 target at (Fri May 13 17:08:01.081 2011 (UTC + 2:00)), ptr64 TRUE
Loading Kernel Symbols
...............................................................
.............................................
Loading User Symbols

Loading unloaded module list
..
*******************************************************************************
*                                                                             *
*                        Bugcheck Analysis                                    *
*                                                                             *
*******************************************************************************

Use !analyze -v to get detailed debugging information.

BugCheck A, {8, 2, 1, fffff8000cc8230b}

Probably caused by : Wdf01000.sys ( Wdf01000!FxPkgPnp::PowerPolicyProcessEvent+3f8 )

Followup: MachineOwner
---------

nt!DbgBreakPointWithStatus:
fffff800`0ce06060 cc              int     3
1: kd> !analyze -v
*******************************************************************************
*                                                                             *
*                        Bugcheck Analysis                                    *
*                                                                             *
*******************************************************************************

IRQL_NOT_LESS_OR_EQUAL (a)
An attempt was made to access a pageable (or completely invalid) address at an
interrupt request level (IRQL) that is too high.  This is usually
caused by drivers using improper addresses.
If a kernel debugger is available get the stack backtrace.
Arguments:
Arg1: 0000000000000008, memory referenced
Arg2: 0000000000000002, IRQL
Arg3: 0000000000000001, bitfield :
	bit 0 : value 0 = read operation, 1 = write operation
	bit 3 : value 0 = not an execute operation, 1 = execute operation (only on chips which support this level of status)
Arg4: fffff8000cc8230b, address which referenced memory

Debugging Details:
------------------


WRITE_ADDRESS:  0000000000000008 

CURRENT_IRQL:  2

FAULTING_IP: 
nt!KiSignalThread+107
fffff800`0cc8230b 48894108        mov     qword ptr [rcx+8],rax

DEFAULT_BUCKET_ID:  VISTA_DRIVER_FAULT

BUGCHECK_STR:  0xA

PROCESS_NAME:  System

TRAP_FRAME:  fffff88002defab0 -- (.trap 0xfffff88002defab0)
NOTE: The trap frame does not contain all registers.
Some register values may be zeroed or incorrect.
rax=fffffa8000c73720 rbx=0000000000000000 rcx=0000000000000000
rdx=fffffa8000c71000 rsi=0000000000000000 rdi=0000000000000000
rip=fffff8000cc8230b rsp=fffff88002defc40 rbp=0000000000000000
 r8=fffffa800117efc0  r9=fffffa8000c71148 r10=0000000000004478
r11=fffff88002defc88 r12=0000000000000000 r13=0000000000000000
r14=0000000000000000 r15=0000000000000000
iopl=0         nv up ei pl zr na po nc
nt!KiSignalThread+0x107:
fffff800`0cc8230b 48894108        mov     qword ptr [rcx+8],rax ds:00000000`00000008=????????????????
Resetting default scope

LOCK_ADDRESS:  fffff8000d3af4c0 -- (!locks fffff8000d3af4c0)

Resource @ nt!PiEngineLock (0xfffff8000d3af4c0)    Exclusively owned
    Contention Count = 6
     Threads: fffffa8000c72680-01<*> 
1 total locks, 1 locks currently held

PNP_TRIAGE: 
	Lock address  : 0xfffff8000d3af4c0
	Thread Count  : 1
	Thread address: 0xfffffa8000c72680
	Thread wait   : 0x10657b3b

LAST_CONTROL_TRANSFER:  from fffff8000cc6e420 to fffff8000ce06060

STACK_TEXT:  
fffff880`02def208 fffff800`0cc6e420 : 00000000`40000082 00000000`0000000a 00000000`00000000 00000000`00000001 : nt!DbgBreakPointWithStatus
fffff880`02def210 fffff800`0cc6f138 : 00000000`00000003 fffff880`00000000 fffff800`0ce11620 00000000`0000000a : nt!KiBugCheckDebugBreak+0x14
fffff880`02def280 fffff800`0ce01d74 : 00000001`0000000a 00000000`00000008 00000000`00000002 00000000`00000001 : nt!KeBugCheck2+0x7c8
fffff880`02def930 fffff800`0ce0b129 : 00000000`0000000a 00000000`00000008 00000000`00000002 00000000`00000001 : nt!KeBugCheckEx+0x104
fffff880`02def970 fffff800`0ce09da0 : 00000000`00000001 00000000`00000008 00000000`00000000 fffff880`02defab0 : nt!KiBugCheckDispatch+0x69
fffff880`02defab0 fffff800`0cc8230b : fffff800`0ce15200 00000000`00000049 fffff880`00000020 fffff880`019d6180 : nt!KiPageFault+0x260
fffff880`02defc40 fffff800`0cc824c8 : fffff880`009e6180 fffffa80`00c71040 fffffa80`0117efc0 fffffa80`00c71148 : nt!KiSignalThread+0x107
fffff880`02defc90 fffff800`0cc744eb : fffff880`009e6180 fffffa80`00c71148 fffffa80`0117efc0 00000000`00000000 : nt!KiTryUnwaitThread+0xc8
fffff880`02defd00 fffff800`0cde24cf : fffff800`0d27abf8 fffffa80`0117efc0 fffffa80`01193c00 fffffa80`00000000 : nt!KiInsertQueue+0x143
fffff880`02defd70 fffff880`01096928 : fffffa80`0117efc0 fffff880`00000001 fffffa80`00000001 fffffa80`011932b8 : nt!ExQueueWorkItem+0x83
fffff880`02defdb0 fffff880`0108b3d5 : fffffa80`01193020 fffffa80`00000020 fffffa80`00000000 fffffa80`01193020 : Wdf01000!FxPkgPnp::PowerPolicyProcessEvent+0x3f8
fffff880`02defe60 fffff880`0108ad38 : fffffa80`01193020 fffffa80`01193c04 fffffa80`00000015 00000000`0000000f : Wdf01000!FxPkgPnp::PowerD0StartingStartSelfManagedIo+0x55
fffff880`02defe90 fffff880`0108aab8 : fffffa80`01193020 fffffa80`00000316 fffffa80`01193100 fffff880`010a5400 : Wdf01000!FxPkgPnp::PowerEnterNewState+0x1c4
fffff880`02deffd0 fffff880`0108a654 : fffffa80`01193020 fffff880`02df00a8 fffffa80`011931e8 fffffa80`011931e8 : Wdf01000!FxPkgPnp::PowerProcessEventInner+0x240
fffff880`02df0050 fffff880`01097158 : fffffa80`01193020 fffffa80`00000040 fffffa80`0118ee20 fffffa80`01193020 : Wdf01000!FxPkgPnp::PowerProcessEvent+0x274
fffff880`02df00f0 fffff880`01097028 : fffffa80`01193020 fffff880`010a2dc0 00000000`00000000 00000000`0000000e : Wdf01000!FxPkgPnp::PowerPolStarting+0x94
fffff880`02df0120 fffff880`01096c19 : fffffa80`01193020 fffffa80`00000501 fffffa80`01193200 fffff880`010a2da0 : Wdf01000!FxPkgPnp::PowerPolicyEnterNewState+0x1c4
fffff880`02df0260 fffff880`010967b0 : fffffa80`01193020 fffff880`02df0348 fffffa80`011932b8 fffffa80`011932b8 : Wdf01000!FxPkgPnp::PowerPolicyProcessEventInner+0x24d
fffff880`02df02f0 fffff880`01091bec : fffffa80`01193020 00000000`00000001 00000000`00000000 fffffa80`01193020 : Wdf01000!FxPkgPnp::PowerPolicyProcessEvent+0x280
fffff880`02df03a0 fffff880`0109195d : fffffa80`01193020 00000000`00000108 fffffa80`01193020 00000000`00000108 : Wdf01000!FxPkgPnp::PnpEventHardwareAvailable+0x170
fffff880`02df03f0 fffff880`010916c7 : fffffa80`01193020 00000000`00000108 00000000`00000000 fffffa80`01193020 : Wdf01000!FxPkgPnp::PnpEnterNewState+0x195
fffff880`02df0470 fffff880`010912ad : fffffa80`01193020 fffff880`02df0548 00000000`00000000 00000000`00000000 : Wdf01000!FxPkgPnp::PnpProcessEventInner+0x217
fffff880`02df04f0 fffff880`01086474 : fffffa80`01193020 fffff880`00000002 fffffa80`0118e900 00000000`00000000 : Wdf01000!FxPkgPnp::PnpProcessEvent+0x29d
fffff880`02df0590 fffff880`01085307 : fffffa80`01193020 fffff880`02df0620 00000000`0000000c 00000000`0000000e : Wdf01000!FxPkgPnp::_PnpStartDevice+0x28
fffff880`02df05c0 fffff880`01043f91 : fffffa80`01193020 fffffa80`01115010 fffffa80`01192610 00000000`00000001 : Wdf01000!FxPkgPnp::Dispatch+0x713
fffff880`02df0670 fffff880`01043e19 : fffffa80`01193c00 fffffa80`01115010 fffffa80`01115010 00000000`000005b6 : Wdf01000!FxDevice::Dispatch+0x125
fffff880`02df06a0 fffff800`0d4e9069 : fffffa80`01193c00 fffffa80`01115010 fffffa80`01115010 fffffa80`00ffde40 : Wdf01000!FxDevice::DispatchWithLock+0xf9
fffff880`02df06f0 fffff800`0cc5b196 : fffffa80`00ffde40 fffff880`02df0780 fffff800`0cc5af08 fffffa80`011d8190 : nt!PnpAsynchronousCall+0x159
fffff880`02df0730 fffff800`0d4f33b2 : fffffa80`00ffde40 fffff800`0cc5af08 fffffa80`011d8190 fffffa80`00ffd420 : nt!PnpStartDevice+0x1be
fffff880`02df07f0 fffff800`0d4f2659 : fffffa80`00ffd420 fffff800`00000000 fffffa80`00000000 00000000`00000001 : nt!PnpStartDeviceNode+0x312
fffff880`02df08a0 fffff800`0d4e3b94 : fffffa80`00ffd420 fffffa80`00000000 fffff880`00000001 00000000`00000000 : nt!PipProcessStartPhase1+0xe5
fffff880`02df08f0 fffff800`0d4e4933 : fffffa80`00d08430 fffffa80`010d7db0 fffff880`02df0bc0 fffff800`00000000 : nt!PipProcessDevNodeTree+0x240
fffff880`02df0b80 fffff800`0cc59338 : fffffa80`010d7db0 00000000`32706e50 00000000`00000000 fffff880`02df0c00 : nt!PiProcessStartSystemDevices+0xa3
fffff880`02df0be0 fffff800`0cde27c6 : 00000000`00000000 fffff800`0cc58f34 fffff800`0d27abf8 fffffa80`00c72680 : nt!PnpDeviceActionWorker+0x404
fffff880`02df0c80 fffff800`0d70fa3d : 00000000`00000001 fffffa80`00c72680 00000000`00000080 00000000`00000000 : nt!ExpWorkerThread+0x156
fffff880`02df0d10 fffff800`0ce05a26 : fffff800`0cde2670 00000000`00000001 fffff880`009e6180 b2c48b45`09244c8d : nt!PspSystemThreadStartup+0x1a9
fffff880`02df0d80 00000000`00000000 : fffff880`02df1000 fffff880`02deb000 fffff880`02dee280 00000000`00000000 : nt!KxStartSystemThread+0x16


STACK_COMMAND:  kb

FOLLOWUP_IP: 
Wdf01000!FxPkgPnp::PowerPolicyProcessEvent+3f8
fffff880`01096928 4883c470        add     rsp,70h

SYMBOL_STACK_INDEX:  a

SYMBOL_NAME:  Wdf01000!FxPkgPnp::PowerPolicyProcessEvent+3f8

FOLLOWUP_NAME:  MachineOwner

MODULE_NAME: Wdf01000

IMAGE_NAME:  Wdf01000.sys

DEBUG_FLR_IMAGE_TIMESTAMP:  4a5bccfd

FAILURE_BUCKET_ID:  X64_0xA_Wdf01000!FxPkgPnp::PowerPolicyProcessEvent+3f8

BUCKET_ID:  X64_0xA_Wdf01000!FxPkgPnp::PowerPolicyProcessEvent+3f8

Followup: MachineOwner
---------

1: kd> lmvm Wdf01000
start             end                 module name
fffff880`01000000 fffff880`010d3000   Wdf01000   (pdb symbols)          c:\symbols\Wdf01000.pdb\9831C00920594EC1A71E8D5C81C9DED61\Wdf01000.pdb
    Loaded symbol image file: Wdf01000.sys
    Image path: \SystemRoot\system32\drivers\Wdf01000.sys
    Image name: Wdf01000.sys
    Timestamp:        Tue Jul 14 02:10:37 2009 (4A5BCCFD)
    CheckSum:         000DA6E6
    ImageSize:        000D3000
    File version:     1.9.7600.16385
    Product version:  1.9.7600.16385
    File flags:       1 (Mask 3F) Debug
    File OS:          40004 NT Win32
    File type:        3.7 Driver
    File date:        00000000.00000000
    Translations:     0409.04b0
    CompanyName:      Microsoft Corporation
    ProductName:      Microsoft? Windows? Operating System
    InternalName:     wdf01000.sys
    OriginalFilename: wdf01000.sys
    ProductVersion:   1.9.7600.16385
    FileVersion:      1.9.7600.16385 (win7_rtm.090713-1255)
    FileDescription:  Kernel Mode Driver Framework Runtime
    LegalCopyright:   ? Microsoft Corporation. All rights reserved.

From jtd1959 at gmail.com  Fri May 13 20:25:02 2011
From: jtd1959 at gmail.com (J T Dsouza)
Date: Fri, 13 May 2011 23:55:02 +0530
Subject: [coreboot] Hi from LinuxTag 2011
In-Reply-To: <20110513165655.19960.qmail@stuge.se>
References: <20110512000501.14895.qmail@stuge.se>
	<4DCD5556.8080702@opal7.fsnet.co.uk>
	<20110513165655.19960.qmail@stuge.se>
Message-ID: <BANLkTi=ZFbajoCBuyH-=LQY-DodtGkRN9w@mail.gmail.com>

i have something similiar E350N-USB3 Gigabyte

On Fri, May 13, 2011 at 10:26 PM, Peter Stuge <peter at stuge.se> wrote:

> Stephen Matthews wrote:
> > What Mini-ITX motherboard is it in the first picture?
>
> It's the ASRock E350M1 board that Scott has doing a marvellous job
> with!
>
>
> > It doesn't look like any in the supported hardware list at
> > coreboot.org.
>
> Yes, the board is actually in the list. It's very reasonably priced,
> includes everything but DDR3 RAM on the board, costs 80-90 EUR,
> DirectX 11 Pixel Shader 5.0 graphics, and the AMD E350 APU.
>
> Visitors are indeed drooling all over the board here! Lots of fun. :)
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From yogev.ezra at gmail.com  Fri May 13 16:39:09 2011
From: yogev.ezra at gmail.com (Yogev Ezra)
Date: Fri, 13 May 2011 17:39:09 +0300
Subject: [coreboot] Hardware donation for porting Coreboot / FlashROM
Message-ID: <BANLkTinsRyh0d82=UMvOUVANb9MfVap4qg@mail.gmail.com>

Hello everyone,
My name is Yogev Ezra from Green Gadgets Ltd, Israel (
http://www.greengadgets.co.il/)

Our company specializes in assembly, integration and sales of small fanless
computers, thin clients and industrial systems.
We have two systems that we are willing to donate for porting Coreboot /
FlashROM on them:

1. DM&P / ICOP eBox-3300MX thin client / nettop (based on Vortex86MX CPU
that is x86 compatible - Pentium I MMX clone)
Product page is available at: http://www.compactpc.com.tw/ebox-3300MX.htm
CPU details are here: http://www.dmp.com.tw/tech/vortex86mx/

2. Compulab Fit-PC2 nettop (Intel Atom Z510 / Z530 CPU + US15W chipset).
Product page at: http://www.fit-pc.com/web/fit-pc2/fit-pc2-specifications/
Some datasheets are available here:
http://fit-pc2.com/wiki/index.php/Documentation and here:
http://www.compulab.co.il/fitpc2/html/fitpc2-developer.py

Why are we doing that? --- Having more choices for BIOS will benefit the
customers and increase possible usage options. Freeware BIOS will also mean
eventually cheaper systems. In addition, the factory BIOS in both systems
has some issues that we hope to solve with Coreboot:
a) The eBox-3300MX has ROM chip big enough (2MB) to start a small OS
directly from BIOS, so no external storage is needed (I am thinking of
KolibriOS). The factory BIOS can support this option, but the manufacturer
requests extra fee which is too high to justify it.
b) Fit-PC2 occasionally does not recognize SSD disks on boot. Normal
"mechanical" hard disks are always recognized fine. We believe the problem
is in factory BIOS or in bridge-chip BIOS (US15W chipset does not have
native SATA port so Fit-PC2 is using Marvell 88SA8052 PATA-to-SATA bridge
chip). The manufacturer Compulab does not even acknowledge the problem, yet
alone solve it.

Q&A and general terms:
1) The manufacturers of both systems currently do not support, endorse or
allow using Coreboot. We are doing this as our own initiative. Installing
Coreboot instead of factory BIOS will most likely void the manufacturer
warranty.
2) We do not try this ourselves because flash ROM chips in both systems are
soldered, and we just do not have the qualification and equipment for
de-soldering / re-soldering the chips. We already "bricked" a few systems in
the past, so we prefer to concentrate on our own work and let the
professionals try that.
3) We can supply non-NDA datasheets and more info on request. To receive NDA
datasheets, you will have to sign this directly with manufacturers. Not sure
if manufacturers will agree to that, when you tell them what it's needed for
(Coreboot)...
4) The systems we are donating cost us (a lot of) money, so we would like
them to get into "good" hands, of people that actually can invest time in
porting Coreboot/FlashROM to those systems. If you just want free hardware,
please do not bother.

We can donate up to 5 units of each system, in 3 phases:
Phase I - one unit, should go to someone very knowledgeable to start the
porting from scratch. JTAG knowledge and JTAG programmer is a big plus
(eBox-3300MX has on-board JTAG port. Not sure about Fit-PC2 but probably it
does have too).
Phase II - two more units, once the porting becomes WIP on Supported
Mainboards list (http://www.coreboot.org/Supported_Motherboards), to people
who can help the person from Phase I to fix major bugs
Phase III - two more units to two more people, to fix minor bugs once major
bugs are fixed
The reason we won't donate more than one unit from the beginning is because
of big hardware costs that we just cannot bear, so we would like to see at
least some progress before we can allow to donate more units.

Interested persons that are willing to work on Phase I (and have the
required skills and free time to actually work on this), are welcome to
e-mail me. Other comments are also welcome.

Best regards,
Yogev Ezra
Green Gadgets
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From peter at stuge.se  Sat May 14 02:07:08 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 14 May 2011 02:07:08 +0200
Subject: [coreboot] Hardware donation for porting Coreboot / FlashROM
In-Reply-To: <BANLkTinsRyh0d82=UMvOUVANb9MfVap4qg@mail.gmail.com>
References: <BANLkTinsRyh0d82=UMvOUVANb9MfVap4qg@mail.gmail.com>
Message-ID: <20110514000708.29899.qmail@stuge.se>

Hi Yogev,

Yogev Ezra wrote:
> We have two systems that we are willing to donate for porting
> Coreboot / FlashROM on them:
> 
> 1. DM&P / ICOP eBox-3300MX thin client / nettop (based on Vortex86MX CPU
> that is x86 compatible - Pentium I MMX clone)

This machine is not so advanced, so it would probably be a
comparatively easy target for you to port coreboot to.


> 2. Compulab Fit-PC2 nettop (Intel Atom Z510 / Z530 CPU + US15W chipset).

This however is a rather advanced platform.


coreboot supports none of the components on these platforms. I
realize that you have significant expense for this hardware, but it
is, mildly put, unrealistic to think that simply donating some custom
hardware will motivate any developer to spend the many months of work
that will benefit mostly yourselves, because the boards are not
common consumer boards.


> Why are we doing that?

I think this is obvious. You're unable to commit to investing in
coreboot yourselves, so you try to buy many months of expert work
paying with $5k worth of hardware. I doubt anyone will be interested.


> Freeware BIOS will also mean eventually cheaper systems.

Do not make the mistake to think that coreboot is freeware. Please
remember that coreboot is licensed under the terms of the GPL. This
is vastly different from what is commonly known as freeware.

Free software yes indeed, freeware certainly not.


> In addition, the factory BIOS in both systems has some issues that
> we hope to solve with Coreboot:

To be frank, it looks like you are hoping that someone else will
solve them for you.


> 2) We do not try this ourselves because flash ROM chips in both
> systems are soldered, and we just do not have the qualification and
> equipment for de-soldering / re-soldering the chips. We already
> "bricked" a few systems in the past, so we prefer to concentrate on
> our own work and let the professionals try that.

Now if this particular point is a significant problem for you, then
please ship the bricked boards and a few boards you want to develop
on to me; I will be happy to desolder flash chips, and solder sockets
into their place, to allow you to accelerate your effort in porting
coreboot to your mainboards. I might expect a microcontroller as
compensation.


> 3) We can supply non-NDA datasheets and more info on request. To
> receive NDA datasheets, you will have to sign this directly with
> manufacturers. Not sure if manufacturers will agree to that, when
> you tell them what it's needed for (Coreboot)...

Since you are buying their hardware you really need to be handling
the negotiation required to obtain relevant documentation from the
component vendors.


> 4) The systems we are donating cost us (a lot of) money, so we
> would like them to get into "good" hands, of people that actually
> can invest time in porting Coreboot/FlashROM to those systems.

I think there are no such people. There is zero motivation for the
community to work for you for free. It's actually the other way
around in this case; you have to work for the community for free.


> We can donate up to 5 units of each system, in 3 phases:

This is a great arrangement, for a system that would be relevant, or
a situation where you offered reasonable compensation.


Sorry.

I'll try to be constructive now:

I suggest that you throw out these non-supported boards and go to
AMD. Have a talk with them about your requirements. Maybe they can
suggest some off-the-shelf designs that are already supported by
coreboot.


//Peter



From stefan.reinauer at coreboot.org  Sat May 14 03:03:59 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Fri, 13 May 2011 18:03:59 -0700
Subject: [coreboot] Hardware donation for porting Coreboot / FlashROM
In-Reply-To: <20110514000708.29899.qmail@stuge.se>
References: <BANLkTinsRyh0d82=UMvOUVANb9MfVap4qg@mail.gmail.com>
	<20110514000708.29899.qmail@stuge.se>
Message-ID: <4DCDD4FF.9000405@coreboot.org>

On 5/13/11 5:07 PM, Peter Stuge wrote:
> Yogev Ezra wrote:
>> 2. Compulab Fit-PC2 nettop (Intel Atom Z510 / Z530 CPU + US15W chipset).
> This however is a rather advanced platform.
>
>
> coreboot supports none of the components on these platforms.
Actually there is support for the CPU and chipset in coreboot (intel/sch)

Stefan




From stefan.reinauer at coreboot.org  Sat May 14 03:21:51 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Fri, 13 May 2011 18:21:51 -0700
Subject: [coreboot] Win7 on Intel Eagle Heights
In-Reply-To: <BANLkTi=C0jFmaSLneHAFvYoURepiZoFt6Q@mail.gmail.com>
References: <BANLkTi=C0jFmaSLneHAFvYoURepiZoFt6Q@mail.gmail.com>
Message-ID: <4DCDD92F.5030006@coreboot.org>

On 5/13/11 8:57 AM, Thomas JOURDAN wrote:
> I'm trying to get Windows 7 booting on my Intel Eagle Heights 
> evaluation board. I tried to follow all the ACPI tips to get Window$ 
> to boot but I can't figure out the bug I'm facing. I'm using a checked 
> build version of Win 7 64-bits. When I start the installer, the first 
> text screen is ok (windows is copying files...) then it switches to 
> graphics mode (green progress bar with logo). Less than a second after 
> switching from text to graphics mode : BSOD.

Hi Thomas,

Looks like Windows 7 crashes in the "Windows Driver Foundation" with an 
illegal memory access. Possibly this is due to an incomplete ACPI 
implementation for the board.

Please have a look at the kontron/986lcd-m ACPI code for a modular 
sample implementation that can boot Windows 7 and 
http://www.coreboot.org/ACPI for more information on ACPI and ACPI 
debugging.

Stefan



From peter at stuge.se  Sat May 14 03:21:42 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 14 May 2011 03:21:42 +0200
Subject: [coreboot] Hardware donation for porting Coreboot / FlashROM
In-Reply-To: <4DCDD4FF.9000405@coreboot.org>
References: <BANLkTinsRyh0d82=UMvOUVANb9MfVap4qg@mail.gmail.com>
	<20110514000708.29899.qmail@stuge.se>
	<4DCDD4FF.9000405@coreboot.org>
Message-ID: <20110514012143.4743.qmail@stuge.se>

Stefan Reinauer wrote:
>>> 2. Compulab Fit-PC2 nettop (Intel Atom Z510 / Z530 CPU + US15W chipset).
>> This however is a rather advanced platform.
>>
>>
>> coreboot supports none of the components on these platforms.
> 
> Actually there is support for the CPU and chipset in coreboot (intel/sch)

D'oh, I managed to confuse it! Of course you are right.

A board port is what is needed; significantly less effort, but will
possibly still need to write new support for the EC, which often does
more things than usual within Atom systems.


//Peter



From andrew.goodbody at tadpole.com  Thu May 12 12:28:26 2011
From: andrew.goodbody at tadpole.com (Andrew Goodbody)
Date: Thu, 12 May 2011 03:28:26 -0700
Subject: [coreboot] Alternate for serial port debug messages
In-Reply-To: <BANLkTinzTqYRyLW9ceQDuHLEzHv47zQAQA@mail.gmail.com>
References: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>	<BANLkTincQm_=e-ZY1uWAUh2eXDcEQi3xbA@mail.gmail.com>
	<BANLkTinzTqYRyLW9ceQDuHLEzHv47zQAQA@mail.gmail.com>
Message-ID: <4DCBB64A.5050607@tadpole.com>

Vikram Narayanan wrote:
> I have an USB port that has debug capabilities (according to the lspci output)
> Should I buy the one mentioned in this page
> http://www.coreboot.org/EHCI_Debug_Port

Yes

> or can I use a normal cable to debug?

There is no normal cable to connect two host ports together and doing so 
would be a bad idea anyway.

> Thanks
> Vikram

Andrew



From gregg.drwho8 at gmail.com  Sat May 14 05:05:56 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Fri, 13 May 2011 23:05:56 -0400
Subject: [coreboot] Alternate for serial port debug messages
In-Reply-To: <4DCBB64A.5050607@tadpole.com>
References: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>
	<BANLkTincQm_=e-ZY1uWAUh2eXDcEQi3xbA@mail.gmail.com>
	<BANLkTinzTqYRyLW9ceQDuHLEzHv47zQAQA@mail.gmail.com>
	<4DCBB64A.5050607@tadpole.com>
Message-ID: <BANLkTi=PP61tJXfUMGhOoiA22Ws7VZ07Lg@mail.gmail.com>

On Thu, May 12, 2011 at 6:28 AM, Andrew Goodbody
<andrew.goodbody at tadpole.com> wrote:
> Vikram Narayanan wrote:
>>
>> I have an USB port that has debug capabilities (according to the lspci
>> output)
>> Should I buy the one mentioned in this page
>> http://www.coreboot.org/EHCI_Debug_Port
>
> Yes
>
>> or can I use a normal cable to debug?
>
> There is no normal cable to connect two host ports together and doing so
> would be a bad idea anyway.
>
>> Thanks
>> Vikram
>
> Andrew
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Hello!
Andrew is right. Don't do that. Track down and buy one of the devices
described on that Wiki page. Further along, it happens that the gadget
chips were originally used for a cable that enabled "simple file
transfer methods" for sending files from one computer to the other,
and I asked about them.

Turns out that the cable might have been perfect, except that it also
isn't the right one.

Naturally I am also looking for the classic USB gadget cable or in
this case card, as described in the 2.4.33.3 USB area.
-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From corey.osgood at gmail.com  Sat May 14 06:13:21 2011
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 14 May 2011 00:13:21 -0400
Subject: [coreboot] Hardware donation for porting Coreboot / FlashROM
In-Reply-To: <20110514012143.4743.qmail@stuge.se>
References: <BANLkTinsRyh0d82=UMvOUVANb9MfVap4qg@mail.gmail.com>
	<20110514000708.29899.qmail@stuge.se>
	<4DCDD4FF.9000405@coreboot.org>
	<20110514012143.4743.qmail@stuge.se>
Message-ID: <BANLkTikvbOAiMAW+Srd9jfXM+rmqub=RGA@mail.gmail.com>

On Fri, May 13, 2011 at 9:21 PM, Peter Stuge <peter at stuge.se> wrote:
> Stefan Reinauer wrote:
>>>> 2. Compulab Fit-PC2 nettop (Intel Atom Z510 / Z530 CPU + US15W chipset).
>>> This however is a rather advanced platform.
>>>
>>>
>>> coreboot supports none of the components on these platforms.
>>
>> Actually there is support for the CPU and chipset in coreboot (intel/sch)
>
> D'oh, I managed to confuse it! Of course you are right.
>
> A board port is what is needed; significantly less effort, but will
> possibly still need to write new support for the EC, which often does
> more things than usual within Atom systems.

Shouldn't be an EC, this is a nettop, not a netbook.

-Corey



From hamo.by at gmail.com  Sat May 14 07:07:58 2011
From: hamo.by at gmail.com (Hamo)
Date: Sat, 14 May 2011 13:07:58 +0800
Subject: [coreboot] Ok, let's move on. What shold we do to CBFS?
In-Reply-To: <BANLkTint3JxTZtHcGWzhQLXFPwdqLjekHQ@mail.gmail.com>
References: <BANLkTint3JxTZtHcGWzhQLXFPwdqLjekHQ@mail.gmail.com>
Message-ID: <BANLkTinop3EWscUf7c2ksb1t8fxxcUW=Wg@mail.gmail.com>

Ping...

On Wed, May 11, 2011 at 8:51 PM, Hamo <hamo.by at gmail.com> wrote:
> Dear lists,
> I have got the idea on how to deal with xcompile script for ARM. Now,
> let's move on to CBFS.
> It is one of the most difficult part since CBFS is almost hard-coded
> to X86 architecture. On ARM,
> we need CBFS like this:
>
>
> /---------------\ <-- Start of ROM
> | /-----------\ |
> | | Reset ?| | <- 0x0
> | |-----------| |
> | |IVs ? ? ?| |
> | |-----------| |
> | |Boot ? ?| |
> | |Block ? | |
> | \-----------/ |
> | ? ? ? ? ? ? ? |
> | /-----------\ | --|
> | | Header| | ? |
> | |-----------| | ? |
> | | Name ?| | ? |
> | |-----------| | ? |-- Component
> | |Data ? ?| | ? |
> | |.. ? ? ? ? | | ? |
> | \-----------/ | --|
> | ? ? ? ? ? ? ? |
> | ... ? ? ? ? ? |
> | /-----------\ | --|
> | | Header| | ? |
> | |-----------| | ? |
> | | Name ?| | ? |
> | |-----------| | ? |-- Component
> | |Data ? ?| | ? |
> | |.. ? ? ? ? | | ? |
> | \-----------/ | --|
> \---------------/
>
>
> Where should we put the CBFS master header and the pointer to it?
> I have no idea of how to implement it and not break it on X86
> architecture. Any comment or suggestion is very welcome.
>



-- 
? ? """
? ? Keep It Simple,Stupid.
? ? """

Chinese Name: ??
Nick Name: Hamo
Homepage: http://hamobai.com/
GPG KEY ID: 0xA4691A33
Key fingerprint = 09D5 2D78 8E2B 0995 CF8E? 4331 33C4 3D24 A469 1A33



From vikram186 at gmail.com  Sat May 14 09:14:23 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Sat, 14 May 2011 12:44:23 +0530
Subject: [coreboot] Alternate for serial port debug messages
In-Reply-To: <BANLkTi=PP61tJXfUMGhOoiA22Ws7VZ07Lg@mail.gmail.com>
References: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>
	<BANLkTincQm_=e-ZY1uWAUh2eXDcEQi3xbA@mail.gmail.com>
	<BANLkTinzTqYRyLW9ceQDuHLEzHv47zQAQA@mail.gmail.com>
	<4DCBB64A.5050607@tadpole.com>
	<BANLkTi=PP61tJXfUMGhOoiA22Ws7VZ07Lg@mail.gmail.com>
Message-ID: <BANLkTikbHU3sae8V2-2pNDbwZLkoV06DfA@mail.gmail.com>

On Sat, May 14, 2011 at 8:35 AM, Gregg Levine <gregg.drwho8 at gmail.com> wrote:
> On Thu, May 12, 2011 at 6:28 AM, Andrew Goodbody
> <andrew.goodbody at tadpole.com> wrote:
>> Vikram Narayanan wrote:
>>>
>>> I have an USB port that has debug capabilities (according to the lspci
>>> output)
>>> Should I buy the one mentioned in this page
>>> http://www.coreboot.org/EHCI_Debug_Port
>>
>> Yes
>>
>>> or can I use a normal cable to debug?
>>
>> There is no normal cable to connect two host ports together and doing so
>> would be a bad idea anyway.
>>
>>> Thanks
>>> Vikram
>>
>> Andrew
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
> Hello!
> Andrew is right. Don't do that. Track down and buy one of the devices
> described on that Wiki page. Further along, it happens that the gadget
> chips were originally used for a cable that enabled "simple file
> transfer methods" for sending files from one computer to the other,
> and I asked about them.
>
> Turns out that the cable might have been perfect, except that it also
> isn't the right one.
>
> Naturally I am also looking for the classic USB gadget cable or in
> this case card, as described in the 2.4.33.3 USB area.
ok. I am planning to buy one. Please share your thoughs on which one to buy.
In the links(in wiki page), it is mentioned that,
=== from the link (http://www.ajaystech.com/net20dc.htm)
System Requirements

    Target Computer: Windows Vista and later OS
    Host Computer: Windows 2000 and later OS
===
Does this mean anything? or this stuff can also be used for boot time
debugging (coreboot) ?

-
Thanks,
Vikram



From peter at stuge.se  Sat May 14 10:48:16 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 14 May 2011 10:48:16 +0200
Subject: [coreboot] Hardware donation for porting Coreboot / FlashROM
In-Reply-To: <BANLkTikvbOAiMAW+Srd9jfXM+rmqub=RGA@mail.gmail.com>
References: <BANLkTinsRyh0d82=UMvOUVANb9MfVap4qg@mail.gmail.com>
	<20110514000708.29899.qmail@stuge.se>
	<4DCDD4FF.9000405@coreboot.org>
	<20110514012143.4743.qmail@stuge.se>
	<BANLkTikvbOAiMAW+Srd9jfXM+rmqub=RGA@mail.gmail.com>
Message-ID: <20110514084816.16664.qmail@stuge.se>

Corey Osgood wrote:
> >> Actually there is support for the CPU and chipset in coreboot (intel/sch)
> >
> > D'oh, I managed to confuse it! Of course you are right.
> >
> > A board port is what is needed; significantly less effort, but will
> > possibly still need to write new support for the EC, which often does
> > more things than usual within Atom systems.
> 
> Shouldn't be an EC, this is a nettop, not a netbook.

Nettop, but Atom does a bit more power management stuff than usual,
and there was (at least originally) no EC designed in that could
manage it in the reference schematics so every design has a different
one. (One is supposedly always needed.)


//Peter



From prakash at punnoor.de  Sat May 14 12:17:48 2011
From: prakash at punnoor.de (Prakash Punnoor)
Date: Sat, 14 May 2011 12:17:48 +0200
Subject: [coreboot] Alternate for serial port debug messages
In-Reply-To: <4DCBB64A.5050607@tadpole.com>
References: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>	<BANLkTincQm_=e-ZY1uWAUh2eXDcEQi3xbA@mail.gmail.com>	<BANLkTinzTqYRyLW9ceQDuHLEzHv47zQAQA@mail.gmail.com>
	<4DCBB64A.5050607@tadpole.com>
Message-ID: <4DCE56CC.3090607@punnoor.de>

Hi,


On 12.05.2011 12:28, Andrew Goodbody wrote:
> Vikram Narayanan wrote:
>> I have an USB port that has debug capabilities (according to the
>> lspci output)
>> Should I buy the one mentioned in this page
>> http://www.coreboot.org/EHCI_Debug_Port
>
> Yes
>
>> or can I use a normal cable to debug?
>
> There is no normal cable to connect two host ports together and doing
> so would be a bad idea anyway.
>
Are you sure? I didn't try it yet, but according to
http://www.spinics.net/lists/linux-usb/msg32912.html
it should be possible to use a Linux machine as USB debug port device.

I haven't checked whether the patch (or something similar) landed in
mainline.

Once I find time I wanted to try it myself, as the Abit A-S78H I am
trying to port coreboot to, doesn't have serial ports, as well.

Cheers,

Prakash



From stefan.reinauer at coreboot.org  Sun May 15 04:43:46 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 14 May 2011 19:43:46 -0700
Subject: [coreboot] Alternate for serial port debug messages
In-Reply-To: <4DCE56CC.3090607@punnoor.de>
References: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>	<BANLkTincQm_=e-ZY1uWAUh2eXDcEQi3xbA@mail.gmail.com>	<BANLkTinzTqYRyLW9ceQDuHLEzHv47zQAQA@mail.gmail.com>	<4DCBB64A.5050607@tadpole.com>
	<4DCE56CC.3090607@punnoor.de>
Message-ID: <4DCF3DE2.3020404@coreboot.org>

On 5/14/11 3:17 AM, Prakash Punnoor wrote:
> Are you sure? I didn't try it yet, but according to
> http://www.spinics.net/lists/linux-usb/msg32912.html
> it should be possible to use a Linux machine as USB debug port device.
It might work if your controller has a USB device port. A USB host port 
won't work.





From deepmindster at gmail.com  Sun May 15 20:13:30 2011
From: deepmindster at gmail.com (=?UTF-8?B?0JDQvdC00YDQtdC5INCa0LvQsNGD0YE=?=)
Date: Sun, 15 May 2011 22:13:30 +0400
Subject: [coreboot] How long will take to add coreboot support for my
	motherboard?
Message-ID: <BANLkTi=6gpgr3Toxx7OXDgVV0Y2R41aMug@mail.gmail.com>

Hello everybody,

I'm a newbe in this question. And english is not my native language. So,
sorry for stupid and smooth questions..

I have a motherboard (epox 9NPA3I / 9NPA3J / 9NPAJ-3 / 9NPA3 Ultra Series)
which is not supported 4GB memory.. at least in 4x1GB variant.

I thinked may be it is software/bios problem. I updated bios to last
version, still nothing.

I thinked about coreboot (always wanted to try it).

Unfortunatly, my motherboard is not in supported list.

But looks like my chipset (CK804) and my superio (F71872F/FG) are in
supported list.

I have small expirience in C (about 1 year, about 5 years ago). So, i
thinked about the trying to add support for my motherboard.

My 1st question is: how long will take for proffessional coreboot developer
to add support of my motherboard?

I think i'll may be spend 5-10 times more. If for professional it will take
up to 4 hours, i think i'll try. If not - i'll just leave an idea and will
return memory.

2nd question (if 1st will positive, but anyway..): where should i start?

3rd question: actually, superiotool said me this (and is that ok?):
#superiotool -d
superiotool r5050
Found Fintek F71872F/FG / F71806F/FG (vid=0x3419, id=0x4103) at 0x4e
No dump available for this Super I/O

Thank you, guys.
Andrey.
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From r.marek at assembler.cz  Sun May 15 21:20:09 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 15 May 2011 21:20:09 +0200
Subject: [coreboot] U-Boot-x86 / coreboot Integration
In-Reply-To: <4DC94CD4.2050904@gmail.com>
References: <4DC94CD4.2050904@gmail.com>
Message-ID: <4DD02769.9050602@assembler.cz>

Hi all,

Sorry for the delay. I'm adding some of mine ideas for the discussion. What I 
like on u-boot is interactive command line ;) this is why I started to tickle this.

The coreboot + u-boot is a win for u-boot because it can run on then on any 
coreboot supported board (including QEMU).

 From the "target" application of use I would like to see the u-boot as kind of 
alternative bootloader/monitor, where the BIOS compatibility is NOT needed. This 
limit us most likely to just linux kernel or coreboot payloads for now. We can 
have a u-boot and SeaBIOS payload in same image.

Therefore its booting job should be just loading the image (from supported 
interfaces plus CBFS ROM image) and letting this execute.

I would go with the native drivers approach, there is a plenty of them already 
for IDE, AHCI, USB if they are usable. I discuss the libpayload stuff later. The 
BIOS emulation should be restricted as much as possible because it is not the 
goal. The VGA init can be done in coreboot, as there is similar x86 emulator for 
VGA option ROM.

Do we need interrupt system up and running? I guess there are no peripherals 
using IRQ besides PPC405?

To make u-boot and coreboot work and boot on legacy IDE, following extra code is 
needed:

x86/coreboot/sdram.c -> it just reads the coreboot tables in coreboto ROM/RAM 
stage and gets memsize for u-boot. The code can be taken from libpayload (2 
files, BSD lic) or from SeaBIOS (if relicensed to GPL v2 or later). Or written 
from scratch. This file should also move ACPI RSDP table, PIR table and MP-table 
to F0000 segment.

board/coreboot.c -> the PIC should be init before CPU irq or we get div 0
x86/coreboot/pci.c -> we tell the PCI subsystem that first usable PCI address is 
right after RAM (which is not true, but the PCI is setup already from coreboot, 
should be enough to make it work).

u-boot relocation fix:

So far my patches just put into 32MB RAM, I let it relocate to the end of memory 
which I read from coreboot tables. There is a small issue with the LMA/VMA 
problem for .bios and .realmode switch section.

This is OK so far, but both sections are loaded low and its content may be 
overwritten because they tend to be used just in the booting phase.

Maybe Graeme can fix this later.

So far not much else is needed, however for the future it would be nice to for 
example write u-boot env to flash (on x86 through upcoming libflashrom). Or 
setup coreboot CMOS variables (this can be done via libpayload).

Also not sure how advanced is the PCI SATA/IDE stuff or the USB keyboard in 
u-boot. Problem is that all this is already done in libpayload and it looks like 
a waste of time to duplicate it again.

Maybe for a start I will prepare the patches to have at least the minimal 
functionality ready, so other people might jump in. Current plan is to prepare 
patches during Coreboot hackaton in prague in two weeks.

I re-read the thread regarding the libpayload/libflashrom but could not find the 
decision how to solve this.

Thanks,
Rudolf






From svn at coreboot.org  Sun May 15 23:01:42 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:01:42 +0200
Subject: [coreboot] [commit] r6570 - trunk/src/cpu/amd/agesa_wrapper/family14
Message-ID: <E1QLiRa-0005X7-Fq@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:01:42 2011
New Revision: 6570
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6570

Log:
1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
2) Remove coreboot variable MTRR initialization because AMD reference code handles it.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c

Modified: trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c
==============================================================================
--- trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c	Fri May 13 08:25:16 2011	(r6569)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c	Sun May 15 23:01:42 2011	(r6570)
@@ -62,6 +62,7 @@
 
   u8 i;
   msr_t msr;
+  int msrno;
   struct node_core_id id;
 #if CONFIG_LOGICAL_CPUS == 1
   u32 siblings;
@@ -70,12 +71,24 @@
 //  id = get_node_core_id(read_nb_cfg_54());  /* nb_cfg_54 can not be set */
 //  printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
 
-  /* Turn on caching if we haven't already */
-  x86_enable_cache();
-  amd_setup_mtrrs();
-  x86_mtrr_check();
-
-  disable_cache();
+  disable_cache ();
+  /* Enable access to AMD RdDram and WrDram extension bits */
+  msr = rdmsr(SYSCFG_MSR);
+  msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+  wrmsr(SYSCFG_MSR, msr);
+
+   // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
+   msr.lo = msr.hi = 0;
+   wrmsr (0x259, msr);
+   msr.lo = msr.hi = 0x1e1e1e1e;
+   for (msrno = 0x268; msrno <= 0x26f; msrno++)
+      wrmsr (msrno, msr);
+
+  /* disable access to AMD RdDram and WrDram extension bits */
+  msr = rdmsr(SYSCFG_MSR);
+  msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+  wrmsr(SYSCFG_MSR, msr);
+  enable_cache ();
 
   /* zero the machine check error status registers */
   msr.lo = 0;
@@ -84,8 +97,6 @@
     wrmsr(MCI_STATUS + (i * 4), msr);
   }
 
-  enable_cache();
-
   /* Enable the local cpu apics */
   setup_lapic();
 



From svn at coreboot.org  Sun May 15 23:06:30 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:06:30 +0200
Subject: [coreboot] [commit] r6571 - trunk/src/cpu/amd/agesa_wrapper/family14
Message-ID: <E1QLiWE-0003cV-SO@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:06:30 2011
New Revision: 6571
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6571

Log:
Correct the number of MCA error reporting banks cleared.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c

Modified: trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c
==============================================================================
--- trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c	Sun May 15 23:01:42 2011	(r6570)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c	Sun May 15 23:06:30 2011	(r6571)
@@ -93,7 +93,7 @@
   /* zero the machine check error status registers */
   msr.lo = 0;
   msr.hi = 0;
-  for (i = 0; i < 5; i++) {
+  for (i = 0; i < 6; i++) {
     wrmsr(MCI_STATUS + (i * 4), msr);
   }
 



From svn at coreboot.org  Sun May 15 23:07:44 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:07:44 +0200
Subject: [coreboot] [commit] r6572 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLiXQ-0005Pe-7M@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:07:43 2011
New Revision: 6572
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6572

Log:
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/acpi_tables.c
   trunk/src/mainboard/amd/persimmon/get_bus_conf.c
   trunk/src/mainboard/amd/persimmon/mptable.c

Modified: trunk/src/mainboard/amd/persimmon/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/acpi_tables.c	Sun May 15 23:06:30 2011	(r6571)
+++ trunk/src/mainboard/amd/persimmon/acpi_tables.c	Sun May 15 23:07:43 2011	(r6572)
@@ -64,7 +64,7 @@
   current = acpi_create_madt_lapics(current);
 
   /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
              IO_APIC_ADDR, 0);
 
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

Modified: trunk/src/mainboard/amd/persimmon/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/get_bus_conf.c	Sun May 15 23:06:30 2011	(r6571)
+++ trunk/src/mainboard/amd/persimmon/get_bus_conf.c	Sun May 15 23:07:43 2011	(r6572)
@@ -138,7 +138,7 @@
 
   /* I/O APICs:   APIC ID Version State   Address */
   bus_isa = 10;
-  apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+  apicid_base = CONFIG_MAX_CPUS;
 //#if CONFIG_LOGICAL_CPUS==1
 //  apicid_base = get_apicid_base(1);
 //#endif

Modified: trunk/src/mainboard/amd/persimmon/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/mptable.c	Sun May 15 23:06:30 2011	(r6571)
+++ trunk/src/mainboard/amd/persimmon/mptable.c	Sun May 15 23:07:43 2011	(r6572)
@@ -69,7 +69,7 @@
   dword |= (pm_ioread(0x35) & 0xFF) << 8;
   dword |= (pm_ioread(0x36) & 0xFF) << 16;
   dword |= (pm_ioread(0x37) & 0xFF) << 24;
-  smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
 
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);



From svn at coreboot.org  Sun May 15 23:10:21 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:10:21 +0200
Subject: [coreboot] [commit] r6573 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLiZx-0001GN-BU@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:10:20 2011
New Revision: 6573
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6573

Log:
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/agesawrapper.c

Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/agesawrapper.c	Sun May 15 23:07:43 2011	(r6572)
+++ trunk/src/mainboard/amd/persimmon/agesawrapper.c	Sun May 15 23:10:20 2011	(r6573)
@@ -85,38 +85,39 @@
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  
-  /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+  /* Enable legacy video routing: D18F1xF4 VGA Enable */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+  PciData = 1;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+
+  /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+   * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+   * set to non-posted regions.
+   */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00000B00;
+  PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+  PciData |= 1 << 7;    // set NP (non-posted) bit
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = 0x00000A03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  
-  /* Set TOM-DFFFFFFF to Node0 Link0. */
+  PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+   
+  /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00DFFF00;
+  PciData = 0x00FECF00; // last address before non-posted range
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
-  PciData = 0x00FFFF00 | 0x80;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
-  PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+   
+  /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000013;
+  PciData = 0x00000003;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   Status = AGESA_SUCCESS;
   return (UINT32)Status;



From svn at coreboot.org  Sun May 15 23:11:42 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:11:42 +0200
Subject: [coreboot] [commit] r6574 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLibG-0003Jk-BO@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:11:41 2011
New Revision: 6574
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6574

Log:
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/agesawrapper.c

Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/agesawrapper.c	Sun May 15 23:10:20 2011	(r6573)
+++ trunk/src/mainboard/amd/persimmon/agesawrapper.c	Sun May 15 23:11:41 2011	(r6574)
@@ -138,7 +138,8 @@
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.
   */
-  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+
+  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
   
   /*



From svn at coreboot.org  Sun May 15 23:13:00 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:13:00 +0200
Subject: [coreboot] [commit] r6575 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLicW-0005Kl-MO@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:13:00 2011
New Revision: 6575
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6575

Log:
Match DIMM SPD addressing to implemented slots.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/dimmSpd.c

Modified: trunk/src/mainboard/amd/persimmon/dimmSpd.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/dimmSpd.c	Sun May 15 23:11:41 2011	(r6574)
+++ trunk/src/mainboard/amd/persimmon/dimmSpd.c	Sun May 15 23:13:00 2011	(r6575)
@@ -35,7 +35,7 @@
    // socket 0
       {
          {0xA0, 0xA2},  // channel 0 dimms
-         {0xA4, 0xA8},  // channel 1 dimms
+         {0x00, 0x00},  // channel 1 dimms
       },
    // socket 1
       {



From svn at coreboot.org  Sun May 15 23:18:59 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:18:59 +0200
Subject: [coreboot] [commit] r6576 -
	trunk/src/southbridge/amd/cimx_wrapper/sb800
Message-ID: <E1QLiiJ-0005vl-RT@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:18:59 2011
New Revision: 6576
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6576

Log:
Configure CIMx to use 33 MHz fast mode for SPD read.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h	Sun May 15 23:13:00 2011	(r6575)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h	Sun May 15 23:18:59 2011	(r6576)
@@ -116,8 +116,8 @@
 #define cimHpetTimerDefault             TRUE
 #define cimHpetMsiDisDefault            FALSE     // Enable
 #define cimIrConfigDefault              0x00      // Disable
-#define cimSpiFastReadEnableDefault     0x00      // Disable
-#define cimSpiFastReadSpeedDefault      0x00      // NULL
+#define cimSpiFastReadEnableDefault     0x01      // Enable
+#define cimSpiFastReadSpeedDefault      0x01      // 33 MHz
 // GPP/AB Controller 
 #define cimNbSbGen2Default              TRUE
 #define cimAlinkPhyPllPowerDownDefault  TRUE



From svn at coreboot.org  Sun May 15 23:19:55 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:19:55 +0200
Subject: [coreboot] [commit] r6577 - trunk/src/vendorcode/amd/cimx/sb800
Message-ID: <E1QLijD-0007FY-Ay@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:19:54 2011
New Revision: 6577
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6577

Log:
Fix ACPI shutdown function by removing reliance on SMI.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/vendorcode/amd/cimx/sb800/OEM.h

Modified: trunk/src/vendorcode/amd/cimx/sb800/OEM.h
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/OEM.h	Sun May 15 23:18:59 2011	(r6576)
+++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h	Sun May 15 23:19:54 2011	(r6577)
@@ -32,7 +32,7 @@
 
 #define BIOS_SIZE                      0x04   //04 - 1MB
 #define LEGACY_FREE                    0x00
-#define ACPI_SLEEP_TRAP                0x01
+//#define ACPI_SLEEP_TRAP                0x01
 //#define SPREAD_SPECTRUM_EPROM_LOAD     0x01
 
 /**



From svn at coreboot.org  Sun May 15 23:26:06 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:26:06 +0200
Subject: [coreboot] [commit] r6578 - in trunk/src: mainboard/amd/persimmon
	northbridge/amd/agesa_wrapper/family14 vendorcode/amd/cimx/sb800
Message-ID: <E1QLipC-00012B-2z@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:26:04 2011
New Revision: 6578
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6578

Log:
Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/dsdt.asl
   trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig
   trunk/src/vendorcode/amd/cimx/sb800/OEM.h

Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/persimmon/dsdt.asl	Sun May 15 23:19:54 2011	(r6577)
+++ trunk/src/mainboard/amd/persimmon/dsdt.asl	Sun May 15 23:26:04 2011	(r6578)
@@ -36,7 +36,7 @@
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
 
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(PCBA, 0xF8000000)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
 	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */

Modified: trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig	Sun May 15 23:19:54 2011	(r6577)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig	Sun May 15 23:26:04 2011	(r6578)
@@ -41,12 +41,12 @@
 
 config MMCONF_BASE_ADDRESS
 	hex
-	default 0xe0000000
+	default 0xf8000000
   depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
 
 config MMCONF_BUS_NUMBER
 	int
-	default 256
+ 	default 16
 	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
 
 config DIMM_DDR3

Modified: trunk/src/vendorcode/amd/cimx/sb800/OEM.h
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/OEM.h	Sun May 15 23:19:54 2011	(r6577)
+++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h	Sun May 15 23:26:04 2011	(r6578)
@@ -48,7 +48,7 @@
 #ifdef  MOVE_PCIEBAR_TO_F0000000
   #define PCIEX_BASE_ADDRESS           0xF7000000
 #else
-  #define PCIEX_BASE_ADDRESS           0xE0000000
+  #define PCIEX_BASE_ADDRESS           0xF8000000
 #endif
 
 /**



From svn at coreboot.org  Sun May 15 23:38:08 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:38:08 +0200
Subject: [coreboot] [commit] r6579 - in trunk/src: include/device
	southbridge/amd/cimx_wrapper/sb800
Message-ID: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:38:08 2011
New Revision: 6579
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6579

Log:
Enable AHCI mode and hide IDE controller to reduce boot time.
Note: enable AHCI in seabios and apply seabios patch:
http://www.mail-archive.com/seabios at seabios.org/msg00437.html

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/include/device/pci_ids.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c

Modified: trunk/src/include/device/pci_ids.h
==============================================================================
--- trunk/src/include/device/pci_ids.h	Sun May 15 23:26:04 2011	(r6578)
+++ trunk/src/include/device/pci_ids.h	Sun May 15 23:38:08 2011	(r6579)
@@ -314,6 +314,7 @@
 
 #define PCI_DEVICE_ID_ATI_SB800_LPC             0x439D
 #define PCI_DEVICE_ID_ATI_SB800_SATA            0x4390
+#define PCI_DEVICE_ID_ATI_SB800_SATA_AHCI       0x4391
 #define PCI_DEVICE_ID_ATI_SB800_IDE             0x439C
 #define PCI_DEVICE_ID_ATI_SB800_HDA             0x4383
 #define PCI_DEVICE_ID_ATI_SB800_PCI             0x4384

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c	Sun May 15 23:26:04 2011	(r6578)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c	Sun May 15 23:38:08 2011	(r6579)
@@ -83,7 +83,7 @@
   	sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
 	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
 								//TODO: set to secondary not take effect.
-	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
+	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 1; //IDE controllor is hidden
 	sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
 
   	/* Azalia HDA */

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h	Sun May 15 23:26:04 2011	(r6578)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h	Sun May 15 23:38:08 2011	(r6579)
@@ -109,7 +109,7 @@
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
 #ifndef SATA_MODE
-  #define SATA_MODE			NATIVE_IDE_MODE
+  #define SATA_MODE			AHCI_MODE
 #endif
 
 /**

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Sun May 15 23:26:04 2011	(r6578)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Sun May 15 23:38:08 2011	(r6579)
@@ -138,10 +138,9 @@
 static const struct pci_driver sata_driver __pci_driver = {
 	.ops = &sata_ops,
 	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390
+	.device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
 };
 
-
 #if CONFIG_USBDEBUG
 static void usb_set_resources(struct device *dev)
 {



From svn at coreboot.org  Sun May 15 23:41:01 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:41:01 +0200
Subject: [coreboot] [commit] r6580 -
	trunk/src/southbridge/amd/cimx_wrapper/sb800
Message-ID: <E1QLj3d-00041m-SM@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:41:00 2011
New Revision: 6580
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6580

Log:
Program the I/O APIC ID.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Sun May 15 23:38:08 2011	(r6579)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Sun May 15 23:41:00 2011	(r6580)
@@ -352,6 +352,25 @@
 		break;
 
 	case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
+        {
+	    u8 byte;
+	    u32 ioapic_base;
+
+	    printk(BIOS_INFO, "sm_init().\n");
+	    ioapic_base = 0xFEC00000;
+	    clear_ioapic(ioapic_base);
+	    /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
+	    #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
+	    /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+	    setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+	    #elif (CONFIG_APIC_ID_OFFSET > 0)
+	    /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ 
+	    setup_ioapic(ioapic_base, 0);
+	    #else
+	    #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
+	    #endif
+        }
+
 		break;
 
 	case (0x14 << 3) | 1: /* 0:14:1 IDE */



From svn at coreboot.org  Sun May 15 23:45:48 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:45:48 +0200
Subject: [coreboot] [commit] r6581 -
	trunk/src/northbridge/amd/agesa_wrapper/family14
Message-ID: <E1QLj8G-0001Dy-Pz@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:45:46 2011
New Revision: 6581
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6581

Log:
Build device paths for AP cores so that coreboot will report them to the OS.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c

Modified: trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c
==============================================================================
--- trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c	Sun May 15 23:41:00 2011	(r6580)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c	Sun May 15 23:45:46 2011	(r6581)
@@ -788,7 +788,22 @@
  
 static void cpu_bus_init(device_t dev)
 {
+	struct device_path cpu_path;
+	device_t cpu;
+    int apic_id;
+
     initialize_cpus(dev->link_list);
+
+	/* Build the AP cpu device path(s) */
+    for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) {
+	    cpu_path.type = DEVICE_PATH_APIC;
+	    cpu_path.apic.apic_id = apic_id;
+    	cpu = alloc_dev(dev->link_list, &cpu_path);
+        if (!cpu) return;
+        cpu->enabled = 1;
+    	cpu->path.apic.node_id = 0;
+    	cpu->path.apic.core_id = apic_id;
+    }
 }
 
 



From svn at coreboot.org  Sun May 15 23:48:24 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:48:24 +0200
Subject: [coreboot] [commit] r6582 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjAm-00048l-9u@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:48:22 2011
New Revision: 6582
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6582

Log:
Enable 33 MHz fast mode SPI read early to reduce boot time.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/romstage.c

Modified: trunk/src/mainboard/amd/persimmon/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:45:46 2011	(r6581)
+++ trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:48:22 2011	(r6582)
@@ -47,6 +47,19 @@
   u32 val;
   u8 reg8;
 
+  // early enable of SPI 33 MHz fast mode read
+  if (boot_cpu())
+    {
+    volatile u32 *spiBase = (void *) 0xa0000000;
+    u32 save;
+    __outdword (0xcf8, 0x8000a3a0);
+    save = __indword (0xcfc);
+    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+    spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
+    spiBase [0] |= 1 << 18; // fast read enable
+    __outdword (0xcfc, save); // clear temp base
+    }
+
   if (!cpu_init_detectedx && boot_cpu()) {
     post_code(0x30);
     sb_poweron_init();



From svn at coreboot.org  Sun May 15 23:51:32 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:51:32 +0200
Subject: [coreboot] [commit] r6583 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjDo-0007JM-2V@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:51:31 2011
New Revision: 6583
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6583

Log:
Switch processor cores to pstate 0 early to reduce boot time.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/romstage.c

Modified: trunk/src/mainboard/amd/persimmon/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:48:22 2011	(r6582)
+++ trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:51:31 2011	(r6583)
@@ -47,6 +47,9 @@
   u32 val;
   u8 reg8;
 
+  // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+  __writemsr (0xc0010062, 0);
+
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {



From svn at coreboot.org  Sun May 15 23:54:05 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:54:05 +0200
Subject: [coreboot] [commit] r6584 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjGH-0001OP-8d@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:54:04 2011
New Revision: 6584
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6584

Log:
Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/romstage.c

Modified: trunk/src/mainboard/amd/persimmon/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:51:31 2011	(r6583)
+++ trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:54:04 2011	(r6584)
@@ -50,6 +50,13 @@
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);
 
+  // early enable of PrefetchEnSPIFromHost
+  if (boot_cpu())
+    {
+    __outdword (0xcf8, 0x8000a3b8);
+    __outdword (0xcfc, __indword (0xcfc) | 0 << 24);
+    }
+
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {



From svn at coreboot.org  Sun May 15 23:56:04 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:56:04 +0200
Subject: [coreboot] [commit] r6585 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjIC-0003RW-5I@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:56:03 2011
New Revision: 6585
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6585

Log:
Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/romstage.c

Modified: trunk/src/mainboard/amd/persimmon/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:54:04 2011	(r6584)
+++ trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:56:03 2011	(r6585)
@@ -50,6 +50,21 @@
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);
 
+  if (boot_cpu())
+    {
+    u8 reg8;
+    // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
+    outb(0x24, 0xCD6);
+    reg8 = inb(0xCD7);
+    reg8 |= 1;
+    reg8 &= ~(1 << 1);
+    outb(reg8, 0xCD7);
+  
+    // program SB800 MiscCntrl
+    *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+    *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
+    }
+
   // early enable of PrefetchEnSPIFromHost
   if (boot_cpu())
     {
@@ -78,17 +93,6 @@
     f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
     console_init();
   }
-	//reg8 = pmio_read(0x24);
-  outb(0x24, 0xCD6);
-  reg8 = inb(0xCD7);
-	reg8 |= 1;
-	reg8 &= ~(1 << 1);
-	//pmio_write(0x24, reg8);
-	outb(0x24, 0xCD6);
-	outb(reg8, 0xCD7);
-
-	*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
-	*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
 
   /* Halt if there was a built in self test failure */
   post_code(0x34);



From svn at coreboot.org  Sun May 15 23:59:20 2011
From: svn at coreboot.org (repository service)
Date: Sun, 15 May 2011 23:59:20 +0200
Subject: [coreboot] [commit] r6586 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjLM-00066S-JW@ra.coresystems.de>

Author: mjones
Date: Sun May 15 23:59:19 2011
New Revision: 6586
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6586

Log:
Make fadt revision match its length. Solves Windows 7 checked build assert.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/fadt.c

Modified: trunk/src/mainboard/amd/persimmon/fadt.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/fadt.c	Sun May 15 23:56:03 2011	(r6585)
+++ trunk/src/mainboard/amd/persimmon/fadt.c	Sun May 15 23:59:19 2011	(r6586)
@@ -53,7 +53,7 @@
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = 244;
-	header->revision = 1;
+	header->revision = 3;
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);



From svn at coreboot.org  Mon May 16 00:00:24 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 00:00:24 +0200
Subject: [coreboot] [commit] r6587 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjMO-0007QA-CU@ra.coresystems.de>

Author: mjones
Date: Mon May 16 00:00:23 2011
New Revision: 6587
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6587

Log:
Declare RTC as not PIIX4 compatible to match AMD hardware.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/dsdt.asl

Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/persimmon/dsdt.asl	Sun May 15 23:59:19 2011	(r6586)
+++ trunk/src/mainboard/amd/persimmon/dsdt.asl	Mon May 16 00:00:23 2011	(r6587)
@@ -1379,7 +1379,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)



From svn at coreboot.org  Mon May 16 00:02:28 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 00:02:28 +0200
Subject: [coreboot] [commit] r6588 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjOO-0000ua-4M@ra.coresystems.de>

Author: mjones
Date: Mon May 16 00:02:27 2011
New Revision: 6588
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6588

Log:
Declare legacy video frame buffer so that Windows generic VGA driver will work.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/dsdt.asl

Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/persimmon/dsdt.asl	Mon May 16 00:00:23 2011	(r6587)
+++ trunk/src/mainboard/amd/persimmon/dsdt.asl	Mon May 16 00:02:27 2011	(r6588)
@@ -1483,9 +1483,8 @@
 					0xF300			/* length */
 				)
 
-#if 0
-				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+#if 0
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 



From svn at coreboot.org  Mon May 16 00:03:46 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 00:03:46 +0200
Subject: [coreboot] [commit] r6589 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjPe-0002HF-0p@ra.coresystems.de>

Author: mjones
Date: Mon May 16 00:03:45 2011
New Revision: 6589
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6589

Log:
Remove some non-essential agesa options to reduce boot time.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/buildOpts.c

Modified: trunk/src/mainboard/amd/persimmon/buildOpts.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/buildOpts.c	Mon May 16 00:02:27 2011	(r6588)
+++ trunk/src/mainboard/amd/persimmon/buildOpts.c	Mon May 16 00:03:45 2011	(r6589)
@@ -80,16 +80,16 @@
 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT     TRUE
 
 #define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
 #define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
 //#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
 #define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
 #define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
 #define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
 #define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
@@ -97,17 +97,17 @@
   #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
   #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-//#define BLDOPT_REMOVE_SRAT            TRUE
-//#define BLDOPT_REMOVE_SLIT            TRUE
-//#define BLDOPT_REMOVE_WHEA            TRUE
-//#define BLDOPT_REMOVE_DMI             TRUE
-//#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-//#define BLDOPT_REMOVE_ATM_MODE          TRUE
+#define BLDOPT_REMOVE_SRAT            TRUE
+#define BLDOPT_REMOVE_SLIT            TRUE
+#define BLDOPT_REMOVE_WHEA            TRUE
+#define BLDOPT_REMOVE_DMI             TRUE
+#define BLDOPT_REMOVE_HT_ASSIST         TRUE
+#define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
-//#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
+#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
 
 /*
@@ -123,7 +123,7 @@
 #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
 #define AGESA_ENTRY_INIT_RESUME                   TRUE
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 
 /* 
  * Agesa configuration values selection.  



From svn at coreboot.org  Mon May 16 00:05:00 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 00:05:00 +0200
Subject: [coreboot] [commit] r6590 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjQq-0003Ou-U9@ra.coresystems.de>

Author: mjones
Date: Mon May 16 00:05:00 2011
New Revision: 6590
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6590

Log:
Fix memory allocation problem in amdInitLate. Disabled until further debug.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/agesawrapper.c

Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/agesawrapper.c	Mon May 16 00:03:45 2011	(r6589)
+++ trunk/src/mainboard/amd/persimmon/agesawrapper.c	Mon May 16 00:05:00 2011	(r6590)
@@ -444,33 +444,32 @@
   )
 {
   AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
+  AMD_INTERFACE_PARAMS AmdParamStruct = {0};
+  AMD_LATE_PARAMS *AmdLateParams;
 
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
+  return 0; // this causes bad ACPI SSDT, need to debug
 
-  Status = AmdInitLate (&AmdLateParams);
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+  AmdParamStruct.AllocationMethod = PostMemDram;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdCreateStruct (&AmdParamStruct);
+  AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+  Status = AmdInitLate (AmdLateParams);
   if (Status != AGESA_SUCCESS) {
     agesawrapper_amdreadeventlog();
     ASSERT(Status == AGESA_SUCCESS);
   }
 
-  DmiTable       = AmdLateParams.DmiTable;
-  AcpiPstate     = AmdLateParams.AcpiPState;
-  AcpiSrat       = AmdLateParams.AcpiSrat;
-  AcpiSlit       = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib       = AmdLateParams.AcpiAlib;
+  DmiTable    = AmdLateParams->DmiTable;
+  AcpiPstate  = AmdLateParams->AcpiPState;
+  AcpiSrat    = AmdLateParams->AcpiSrat;
+  AcpiSlit    = AmdLateParams->AcpiSlit;
+
+  AcpiWheaMce = AmdLateParams->AcpiWheaMce;
+  AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
+  AcpiAlib    = AmdLateParams->AcpiAlib;
 
+  AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)Status;
 }
 



From svn at coreboot.org  Mon May 16 00:06:11 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 00:06:11 +0200
Subject: [coreboot] [commit] r6591 - trunk/src/mainboard/amd/persimmon
Message-ID: <E1QLjRz-0004mT-Cy@ra.coresystems.de>

Author: mjones
Date: Mon May 16 00:06:09 2011
New Revision: 6591
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6591

Log:
Enable rom cache early to reduce boot time.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/agesawrapper.c
   trunk/src/mainboard/amd/persimmon/romstage.c

Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/agesawrapper.c	Mon May 16 00:05:00 2011	(r6590)
+++ trunk/src/mainboard/amd/persimmon/agesawrapper.c	Mon May 16 00:06:09 2011	(r6591)
@@ -157,13 +157,6 @@
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   
-
-  /* Set ROM cache onto WP to decrease post time */
-  MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
-  LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-  MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
-  LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
-
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }

Modified: trunk/src/mainboard/amd/persimmon/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/romstage.c	Mon May 16 00:05:00 2011	(r6590)
+++ trunk/src/mainboard/amd/persimmon/romstage.c	Mon May 16 00:06:09 2011	(r6591)
@@ -47,6 +47,11 @@
   u32 val;
   u8 reg8;
 
+  // all cores: allow caching of flash chip code and data
+  // (there are no cache-as-ram reliability concerns with family 14h)
+  __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+  __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);
 



From svn at coreboot.org  Mon May 16 00:07:57 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 00:07:57 +0200
Subject: [coreboot] [commit] r6592 - in trunk/src: mainboard/amd/persimmon
	southbridge/amd/cimx_wrapper/sb800
Message-ID: <E1QLjTh-0006ZX-Dg@ra.coresystems.de>

Author: mjones
Date: Mon May 16 00:07:56 2011
New Revision: 6592
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6592

Log:
Update gpp port configuration.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/devicetree.cb
   trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c

Modified: trunk/src/mainboard/amd/persimmon/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/persimmon/devicetree.cb	Mon May 16 00:06:09 2011	(r6591)
+++ trunk/src/mainboard/amd/persimmon/devicetree.cb	Mon May 16 00:07:56 2011	(r6592)
@@ -81,13 +81,13 @@
 							end
                                                 end # f81865f
 					end #LPC
-  					device pci 14.4 on end # PCI 0x4384
-	  				device pci 14.5 on end # USB 2
-					device pci 15.0 on end # PCIe PortA
-					device pci 15.1 on end # PCIe PortB
-					device pci 15.2 on end # PCIe PortC
-					device pci 15.3 on end # PCIe PortD
-					register "gpp_configuration" = "4" #1:1:1:1
+  					device pci 14.4 on  end # PCI 0x4384
+	  				device pci 14.5 on  end # USB 2
+					device pci 15.0 off end # PCIe PortA
+					device pci 15.1 off end # PCIe PortB
+					device pci 15.2 off end # PCIe PortC
+					device pci 15.3 off end # PCIe PortD
+					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx_wrapper/sb800
 #                       end #  device pci 18.0

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c	Mon May 16 00:06:09 2011	(r6591)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c	Mon May 16 00:07:56 2011	(r6592)
@@ -99,10 +99,6 @@
 	sb_config->GppFunctionEnable = GPP_CONTROLLER;
 	sb_config->GppLinkConfig = GPP_CFGMODE;
 	//sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
-	sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED;
-	sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED;
-	sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED;
-	sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED;
 	sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
 	//sb_config->NbSbGen2 = TRUE;
 	//sb_config->GppGen2 = TRUE;

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Mon May 16 00:06:09 2011	(r6591)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Mon May 16 00:07:56 2011	(r6592)
@@ -315,7 +315,6 @@
  */
 static void sb800_enable(device_t dev)
 {
-	u8 gpp_port = 0;
 	struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
 		(struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
 
@@ -414,15 +413,16 @@
 		break;
 
 	case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
+       sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
+       return;
 	case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
+       sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
+       return;
 	case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
+       sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
+       return;
 	case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
-		gpp_port = (dev->path.pci.devfn) & 0x03;
-		if (dev->enabled) {
-			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
-		} else {
-			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
-		}
+       sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
 
 		/*
 		 * GPP_CFGMODE_X4000: PortA Lanes[3:0]



From svn at coreboot.org  Mon May 16 00:09:11 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 00:09:11 +0200
Subject: [coreboot] [commit] r6593 - in trunk/src: mainboard/amd/persimmon
	northbridge/amd/agesa_wrapper/family14
Message-ID: <E1QLjUt-0007sP-DF@ra.coresystems.de>

Author: mjones
Date: Mon May 16 00:09:09 2011
New Revision: 6593
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6593

Log:
1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/Kconfig
   trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig

Modified: trunk/src/mainboard/amd/persimmon/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/persimmon/Kconfig	Mon May 16 00:07:56 2011	(r6592)
+++ trunk/src/mainboard/amd/persimmon/Kconfig	Mon May 16 00:09:09 2011	(r6593)
@@ -22,8 +22,6 @@
 config BOARD_SPECIFIC_OPTIONS # dummy
         def_bool y
   select ARCH_X86
-        select DIMM_DDR3
-        select DIMM_UNREGISTERED
   select CPU_AMD_AGESA_WRAPPER_FAMILY14
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
@@ -42,7 +40,6 @@
   select AMDMCT
         select HAVE_ACPI_TABLES
   select BOARD_ROMSIZE_KB_4096
-  select ENABLE_APIC_EXT_ID
   select TINY_BOOTBLOCK
         select GFXUMA
 
@@ -86,18 +83,6 @@
         int
         default 2
 
-config SB_HT_CHAIN_ON_BUS0
-        int
-        default 1
-
-config HT_CHAIN_END_UNITID_BASE
-        hex
-        default 0x1
-
-config HT_CHAIN_UNITID_BASE
-        hex
-        default 0x0
-
 config IRQ_SLOT_COUNT
         int
         default 11
@@ -130,10 +115,9 @@
 	bool
 	default y
 
-#define CONFIG_VGA_BIOS_ID "1002,9804"
 config VGA_BIOS_ID
         string
-        default "1002,9804"
+        default "1002,9802"
 
 config DRIVERS_PS2_KEYBOARD
 	bool

Modified: trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig	Mon May 16 00:07:56 2011	(r6592)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig	Mon May 16 00:09:09 2011	(r6593)
@@ -18,17 +18,9 @@
 ##
 config NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
 	bool
-	select HAVE_DEBUG_RAM_SETUP
-	select HAVE_DEBUG_SMBUS
-	select HYPERTRANSPORT_PLUGIN_SUPPORT
 	select MMCONF_SUPPORT
 	select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
 
-config HT3_SUPPORT
-	bool
-	default y
-	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
@@ -49,30 +41,6 @@
  	default 16
 	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
 
-config DIMM_DDR3
-	bool
-	default n
-	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
-
-config DIMM_REGISTERED
-	bool
-	default n
-	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
-
-if !DIMM_REGISTERED
-	config DIMM_SUPPORT
-		hex
-		default 0x0004
-endif
-
-if DIMM_DDR3
-	if DIMM_REGISTERED
-	  config DIMM_SUPPORT
-		  hex
-		  default 0x0005
-	endif
-endif
-
 config BOOTBLOCK_NORTHBRIDGE_INIT
   string
   default "northbridge/amd/agesa_wrapper/family14/bootblock.c"



From svn at coreboot.org  Mon May 16 00:10:16 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 00:10:16 +0200
Subject: [coreboot] [commit] r6594 - in trunk/src:
	cpu/amd/agesa_wrapper/family14 include/cpu/amd
	mainboard/amd/persimmon northbridge/amd/agesa_wrapper/family14
Message-ID: <E1QLjVw-0000d3-HW@ra.coresystems.de>

Author: mjones
Date: Mon May 16 00:10:15 2011
New Revision: 6594
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6594

Log:
Cosmetic cleanup.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c
   trunk/src/include/cpu/amd/amdfam14.h
   trunk/src/mainboard/amd/persimmon/get_bus_conf.c
   trunk/src/mainboard/amd/persimmon/mainboard.c
   trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c

Modified: trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c
==============================================================================
--- trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c	Mon May 16 00:09:09 2011	(r6593)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c	Mon May 16 00:10:15 2011	(r6594)
@@ -31,7 +31,6 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/amd/multicore.h>
 #include <cpu/amd/amdfam14.h>
 
 #define MCI_STATUS 0x401
@@ -58,19 +57,15 @@
 
 static void model_14_init(device_t dev)
 {
-  printk(BIOS_DEBUG, "Model 14 Init - a no-op.\n");
+  printk(BIOS_DEBUG, "Model 14 Init.\n");
 
   u8 i;
   msr_t msr;
   int msrno;
-  struct node_core_id id;
 #if CONFIG_LOGICAL_CPUS == 1
   u32 siblings;
 #endif
 
-//  id = get_node_core_id(read_nb_cfg_54());  /* nb_cfg_54 can not be set */
-//  printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
-
   disable_cache ();
   /* Enable access to AMD RdDram and WrDram extension bits */
   msr = rdmsr(SYSCFG_MSR);
@@ -100,10 +95,6 @@
   /* Enable the local cpu apics */
   setup_lapic();
 
-  /* Set the processor name string */
-//  init_processor_name();
-
-
 #if CONFIG_LOGICAL_CPUS == 1
   siblings = cpuid_ecx(0x80000008) & 0xff;
 

Modified: trunk/src/include/cpu/amd/amdfam14.h
==============================================================================
--- trunk/src/include/cpu/amd/amdfam14.h	Mon May 16 00:09:09 2011	(r6593)
+++ trunk/src/include/cpu/amd/amdfam14.h	Mon May 16 00:10:15 2011	(r6594)
@@ -36,18 +36,11 @@
 msr_t rdmsr_amd(u32 index);
 void wrmsr_amd(u32 index, msr_t msr);
 
-//#if defined(__GNUC__)
-//// it can be used to get unitid and coreid it running only
-//struct node_core_id get_node_core_id(u32 nb_cfg_54);
-//struct node_core_id get_node_core_id_x(void);
-//#endif
-
 #if defined(__PRE_RAM__)
 void wait_all_core0_started(void);
 void wait_all_other_cores_started(u32 bsp_apicid);
 void wait_all_aps_started(u32 bsp_apicid);
 void allow_all_aps_stop(u32 bsp_apicid);
 #endif
-u32 get_initial_apicid(void);
 
 #endif /* CPU_AMD_FAM14_H */

Modified: trunk/src/mainboard/amd/persimmon/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/get_bus_conf.c	Mon May 16 00:09:09 2011	(r6593)
+++ trunk/src/mainboard/amd/persimmon/get_bus_conf.c	Mon May 16 00:10:15 2011	(r6594)
@@ -42,25 +42,12 @@
   0x0000ff0,
 };
 
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
-  0x20202020,
-};
-
 u32 bus_type[256];
-
 u32 sbdn_sb800;
 
-//KZ [092110]extern void get_pci1234(void);
-
 static u32 get_bus_conf_done = 0;
 
 
-
-
 void get_bus_conf(void)
 {
   u32 apicid_base;
@@ -139,8 +126,5 @@
   /* I/O APICs:   APIC ID Version State   Address */
   bus_isa = 10;
   apicid_base = CONFIG_MAX_CPUS;
-//#if CONFIG_LOGICAL_CPUS==1
-//  apicid_base = get_apicid_base(1);
-//#endif
-  apicid_sb800 = apicid_base + 0;
+  apicid_sb800 = apicid_base;
 }

Modified: trunk/src/mainboard/amd/persimmon/mainboard.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/mainboard.c	Mon May 16 00:09:09 2011	(r6593)
+++ trunk/src/mainboard/amd/persimmon/mainboard.c	Mon May 16 00:10:15 2011	(r6594)
@@ -53,7 +53,8 @@
 *************************************************/
 static void persimmon_enable(device_t dev)
 {
-	printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 	uint32_t sys_mem;
@@ -110,6 +111,6 @@
 	return 0;
 }
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("AMD PERSIMMON Mainboard")
+	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
 	.enable_dev = persimmon_enable,
 };

Modified: trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c
==============================================================================
--- trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c	Mon May 16 00:09:09 2011	(r6593)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c	Mon May 16 00:10:15 2011	(r6594)
@@ -849,7 +849,7 @@
     .set_resources    = cpu_bus_set_resources,
     .enable_resources = NULL,
     .init             = cpu_bus_init,
-    .scan_bus         = 0,
+    .scan_bus         = NULL,
 };
 
 



From marcj303 at gmail.com  Mon May 16 00:15:48 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Sun, 15 May 2011 16:15:48 -0600
Subject: [coreboot] AMD Persimmon update
In-Reply-To: <B0FDAE3158B74F6497F657AD6D0408C4@m3a78>
References: <AcwHFoUqRoIXoGvWQa+u/zj10boGfw==>
	<B0FDAE3158B74F6497F657AD6D0408C4@m3a78>
Message-ID: <BANLkTinzzh9owDSPQ7mcNoktjuX_Bdve4Q@mail.gmail.com>

On Sat, Apr 30, 2011 at 3:10 AM, Scott Duplichan <scott at notabs.org> wrote:
> The attached changes for the AMD Persimmon board improve OS support and reduce boot time.
> DOS boot from SSD drive is 640 ms. Windows 7, Windows XP, and linux can install from
> DVD and boot from hard disk.
>
> Signed-off-by: Scott Duplichan <scott at notabs.org>

Hi Scott,

I'm acking and committing all except the LTO patch, which should wait
for the crossgcc changes for gcc4.6. i only made a minor tweak to the
AHCI patch to add a #define for the PCI DID.

02-26 - Acked-by: Marc Jones <marcj303 at gmail.com>

r6571 - r6594

Marc

-- 
http://se-eng.com



From svn at coreboot.org  Mon May 16 00:40:41 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 00:40:41 +0200
Subject: [coreboot] [commit] r6595 -
	trunk/src/northbridge/amd/agesa_wrapper/family14
Message-ID: <E1QLjzN-0002Yj-4z@ra.coresystems.de>

Author: stuge
Date: Mon May 16 00:40:40 2011
New Revision: 6595
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6595

Log:
agesa_wrapper: Avoid repetitive Kconfig depends, trivial

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig

Modified: trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig	Mon May 16 00:10:15 2011	(r6594)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig	Mon May 16 00:40:40 2011	(r6595)
@@ -21,27 +21,26 @@
 	select MMCONF_SUPPORT
 	select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
 
+if NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
-	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
-	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
 
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xf8000000
-  depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
 
 config MMCONF_BUS_NUMBER
 	int
  	default 16
-	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
 
 config BOOTBLOCK_NORTHBRIDGE_INIT
   string
   default "northbridge/amd/agesa_wrapper/family14/bootblock.c"
-	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+
+endif



From peter at stuge.se  Mon May 16 00:51:35 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 00:51:35 +0200
Subject: [coreboot] [commit] r6578 - in
	trunk/src:	mainboard/amd/persimmon
	northbridge/amd/agesa_wrapper/family14	vendorcode/amd/cimx/sb800
In-Reply-To: <E1QLipC-00012B-2z@ra.coresystems.de>
References: <E1QLipC-00012B-2z@ra.coresystems.de>
Message-ID: <20110515225135.12838.qmail@stuge.se>

repository service wrote:
> Move mmconf base from e0000000 to f8000000
..
> +++ trunk/src/mainboard/amd/persimmon/dsdt.asl	Sun May 15 23:26:04 2011	(r6578)
> @@ -36,7 +36,7 @@
>  	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
>  	Name(PBLN, 0x0)	/* Length of BIOS area */
>  
> -	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
> +	Name(PCBA, 0xF8000000)	/* Base address of PCIe config space */
>  	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
..

> +++ trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig	Sun May 15 23:26:04 2011	(r6578)
> @@ -41,12 +41,12 @@
>  
>  config MMCONF_BASE_ADDRESS
>  	hex
> -	default 0xe0000000
> +	default 0xf8000000
..

> +++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h	Sun May 15 23:26:04 2011	(r6578)
> @@ -48,7 +48,7 @@
>  #ifdef  MOVE_PCIEBAR_TO_F0000000
>    #define PCIEX_BASE_ADDRESS           0xF7000000
>  #else
> -  #define PCIEX_BASE_ADDRESS           0xE0000000
> +  #define PCIEX_BASE_ADDRESS           0xF8000000

Magic numbers. Nomnom! Can we at the very least get away from the
duplication?


//Peter



From peter at stuge.se  Mon May 16 00:54:34 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 00:54:34 +0200
Subject: [coreboot] [commit] r6582 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <E1QLjAm-00048l-9u@ra.coresystems.de>
References: <E1QLjAm-00048l-9u@ra.coresystems.de>
Message-ID: <20110515225434.13162.qmail@stuge.se>

repository service wrote:
> +++ trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:48:22 2011	(r6582)
..
> +    volatile u32 *spiBase = (void *) 0xa0000000;
> +    u32 save;
> +    __outdword (0xcf8, 0x8000a3a0);
> +    save = __indword (0xcfc);
> +    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
> +    spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
> +    spiBase [0] |= 1 << 18; // fast read enable
> +    __outdword (0xcfc, save); // clear temp base

Are there some PCI access functions available also in romstage?


//Peter



From peter at stuge.se  Mon May 16 00:57:24 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 00:57:24 +0200
Subject: [coreboot] [commit] r6584 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <E1QLjGH-0001OP-8d@ra.coresystems.de>
References: <E1QLjGH-0001OP-8d@ra.coresystems.de>
Message-ID: <20110515225724.13527.qmail@stuge.se>

repository service wrote:
> +++ trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:54:04 2011	(r6584)
..
> +  // early enable of PrefetchEnSPIFromHost
> +  if (boot_cpu())
> +    {
> +    __outdword (0xcf8, 0x8000a3b8);
> +    __outdword (0xcfc, __indword (0xcfc) | 0 << 24);
> +    }

PCI function? And maybe this, as well as the 33MHz setup, is good to
have in the chipset code, as opposed to duplicated per mainboard?


//Peter



From peter at stuge.se  Mon May 16 01:00:36 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 01:00:36 +0200
Subject: [coreboot] [commit] r6589 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <E1QLjPe-0002HF-0p@ra.coresystems.de>
References: <E1QLjPe-0002HF-0p@ra.coresystems.de>
Message-ID: <20110515230036.13852.qmail@stuge.se>

repository service wrote:
> Log:
> .. agesa options

> +++ trunk/src/mainboard/amd/persimmon/buildOpts.c	Mon May 16 00:03:45 2011	(r6589)
> @@ -80,16 +80,16 @@
>  #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT     TRUE
>  
>  #define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
> -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
> +#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
>  #define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
>  #define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
>  //#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
>  #define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
> -//#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
> +#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
>  #define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
>  #define BLDOPT_REMOVE_DQS_TRAINING            FALSE

... long list ...

I think it would be absolutely lovely to have these in Kconfig
instead.


//Peter



From peter at stuge.se  Mon May 16 01:04:26 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 01:04:26 +0200
Subject: [coreboot] [commit] r6590 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <E1QLjQq-0003Ou-U9@ra.coresystems.de>
References: <E1QLjQq-0003Ou-U9@ra.coresystems.de>
Message-ID: <20110515230427.14239.qmail@stuge.se>

Good example of whitespace changes making it a bit difficult to see
the actual change. :\

repository service wrote:
> +++ trunk/src/mainboard/amd/persimmon/agesawrapper.c	Mon May 16 00:05:00 2011	(r6590)


//Peter



From svn at coreboot.org  Mon May 16 01:13:56 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 01:13:56 +0200
Subject: [coreboot] [commit] r6596 - in trunk/src: mainboard/amd/persimmon
	vendorcode/amd/cimx/sb800
Message-ID: <E1QLkVY-0007W4-23@ra.coresystems.de>

Author: mjones
Date: Mon May 16 01:13:54 2011
New Revision: 6596
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6596

Log:
Remove multiple mmconf settings and just use kconfig setting.

Signed-off-by: Marc Jones <marcj303 at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/dsdt.asl
   trunk/src/vendorcode/amd/cimx/sb800/OEM.h

Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/persimmon/dsdt.asl	Mon May 16 00:40:40 2011	(r6595)
+++ trunk/src/mainboard/amd/persimmon/dsdt.asl	Mon May 16 01:13:54 2011	(r6596)
@@ -36,7 +36,7 @@
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
 
-	Name(PCBA, 0xF8000000)	/* Base address of PCIe config space */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
 	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */

Modified: trunk/src/vendorcode/amd/cimx/sb800/OEM.h
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/OEM.h	Mon May 16 00:40:40 2011	(r6595)
+++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h	Mon May 16 01:13:54 2011	(r6596)
@@ -48,7 +48,7 @@
 #ifdef  MOVE_PCIEBAR_TO_F0000000
   #define PCIEX_BASE_ADDRESS           0xF7000000
 #else
-  #define PCIEX_BASE_ADDRESS           0xF8000000
+  #define PCIEX_BASE_ADDRESS           CONFIG_MMCONF_BASE_ADDRESS
 #endif
 
 /**



From marcj303 at gmail.com  Mon May 16 01:18:02 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Sun, 15 May 2011 17:18:02 -0600
Subject: [coreboot] [commit] r6578 - in trunk/src:
 mainboard/amd/persimmon northbridge/amd/agesa_wrapper/family14
 vendorcode/amd/cimx/sb800
In-Reply-To: <20110515225135.12838.qmail@stuge.se>
References: <E1QLipC-00012B-2z@ra.coresystems.de>
	<20110515225135.12838.qmail@stuge.se>
Message-ID: <BANLkTimxvbU9a+hGVQbYGG+Ac2-kV8T0SQ@mail.gmail.com>

On Sun, May 15, 2011 at 4:51 PM, Peter Stuge <peter at stuge.se> wrote:
> repository service wrote:
>> Move mmconf base from e0000000 to f8000000
> ..
>> +++ trunk/src/mainboard/amd/persimmon/dsdt.asl ? ? ? ?Sun May 15 23:26:04 2011 ? ? ? ?(r6578)
>> @@ -36,7 +36,7 @@
>> ? ? ? Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
>> ? ? ? Name(PBLN, 0x0) /* Length of BIOS area */
>>
>> - ? ? Name(PCBA, 0xE0000000) ?/* Base address of PCIe config space */
>> + ? ? Name(PCBA, 0xF8000000) ?/* Base address of PCIe config space */
>> ? ? ? Name(HPBA, 0xFED00000) ?/* Base address of HPET table */
> ..
>
>> +++ trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig ?Sun May 15 23:26:04 2011 ? ? ? ?(r6578)
>> @@ -41,12 +41,12 @@
>>
>> ?config MMCONF_BASE_ADDRESS
>> ? ? ? hex
>> - ? ? default 0xe0000000
>> + ? ? default 0xf8000000
> ..
>
>> +++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h Sun May 15 23:26:04 2011 ? ? ? ?(r6578)
>> @@ -48,7 +48,7 @@
>> ?#ifdef ?MOVE_PCIEBAR_TO_F0000000
>> ? ?#define PCIEX_BASE_ADDRESS ? ? ? ? ? 0xF7000000
>> ?#else
>> - ?#define PCIEX_BASE_ADDRESS ? ? ? ? ? 0xE0000000
>> + ?#define PCIEX_BASE_ADDRESS ? ? ? ? ? 0xF8000000
>
> Magic numbers. Nomnom! Can we at the very least get away from the
> duplication?
>
>
> //Peter

sounds good.

r6596


-- 
http://se-eng.com



From peter at stuge.se  Mon May 16 01:42:52 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 01:42:52 +0200
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>
Message-ID: <20110515234252.18124.qmail@stuge.se>

Hi,

repository service wrote:
> Enable AHCI mode and hide IDE controller
..

> +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c	Sun May 15 23:38:08 2011	(r6579)
> @@ -83,7 +83,7 @@
>    	sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
>  	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
>  								//TODO: set to secondary not take effect.
> -	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
> +	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 1; //IDE controllor is hidden
..

> +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h	Sun May 15 23:38:08 2011	(r6579)
> @@ -109,7 +109,7 @@
>   *   NOTE: DO NOT ALLOW SATA & IDE use same mode
>   */
>  #ifndef SATA_MODE
> -  #define SATA_MODE			NATIVE_IDE_MODE
> +  #define SATA_MODE			AHCI_MODE
>  #endif
..

> +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Sun May 15 23:38:08 2011	(r6579)
> @@ -138,10 +138,9 @@
>  static const struct pci_driver sata_driver __pci_driver = {
>  	.ops = &sata_ops,
>  	.vendor = PCI_VENDOR_ID_ATI,
> -	.device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390
> +	.device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
>  };

Reading this I think that there should be a Kconfig option to choose
if the chipset should be set up as SATA IDE or AHCI.

Talking to a lot of visitors at LinuxTag it is absolutely clear that
this is an example of what should actually be an NVRAM option.

Do we have some policy for where to place an option? I don't think we
do. Do we want to create one?

The purpose is to have a perfectly streamlined user experience across
all different mainboards. Of course all boards don't support all
options, but when two different boards *do* support an option, that
option must be in the same place, working the same way.

The balance between compile time options and NVRAM options is not so
easy. :\


//Peter



From peter at stuge.se  Mon May 16 01:52:07 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 01:52:07 +0200
Subject: [coreboot] [commit] r6591 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <E1QLjRz-0004mT-Cy@ra.coresystems.de>
References: <E1QLjRz-0004mT-Cy@ra.coresystems.de>
Message-ID: <20110515235207.19241.qmail@stuge.se>

repository service wrote:
> Log:
> Enable rom cache early to reduce boot time.

> +++ trunk/src/mainboard/amd/persimmon/romstage.c	Mon May 16 00:06:09 2011	(r6591)
> @@ -47,6 +47,11 @@
>    u32 val;
>    u8 reg8;
>  
> +  // all cores: allow caching of flash chip code and data
> +  // (there are no cache-as-ram reliability concerns with family 14h)
> +  __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
> +  __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);

Is this something that we should have in component code rather than
mainboard code?

And when would it be suitable to *not* allow caching, if ever? I'm
thinking if this should be an option anywhere, or not.


//Peter



From peter at stuge.se  Mon May 16 01:57:26 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 01:57:26 +0200
Subject: [coreboot] [commit] r6592 - in
	trunk/src:	mainboard/amd/persimmon
	southbridge/amd/cimx_wrapper/sb800
In-Reply-To: <E1QLjTh-0006ZX-Dg@ra.coresystems.de>
References: <E1QLjTh-0006ZX-Dg@ra.coresystems.de>
Message-ID: <20110515235726.19747.qmail@stuge.se>

repository service wrote:
> +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Mon May 16 00:07:56 2011	(r6592)
..
> @@ -414,15 +413,16 @@
>  		break;
>  
>  	case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
> +       sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
> +       return;
>  	case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
> +       sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
> +       return;
>  	case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
> +       sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
> +       return;

coreboot uses tab indent, right?

That said, this reading of devicetree is a great improvement!


>  	case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
> -		gpp_port = (dev->path.pci.devfn) & 0x03;
> -		if (dev->enabled) {
> -			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
> -		} else {
> -			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
> -		}
> +       sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;

Is it guaranteed that ENABLED == dev->enabled and DISABLED == !dev-enabled?


//Peter



From svn at coreboot.org  Mon May 16 02:05:51 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 02:05:51 +0200
Subject: [coreboot] [commit] r6597 -
	trunk/src/southbridge/amd/cimx_wrapper/sb800
Message-ID: <E1QLlJn-0007D4-EZ@ra.coresystems.de>

Author: stuge
Date: Mon May 16 02:05:50 2011
New Revision: 6597
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6597

Log:
cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Mon May 16 01:13:54 2011	(r6596)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Mon May 16 02:05:50 2011	(r6597)
@@ -413,16 +413,16 @@
 		break;
 
 	case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
-       sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
-       return;
+		sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
+		return;
 	case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
-       sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
-       return;
+		sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
+		return;
 	case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
-       sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
-       return;
+		sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
+		return;
 	case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
-       sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
+		sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
 
 		/*
 		 * GPP_CFGMODE_X4000: PortA Lanes[3:0]



From stefan.reinauer at coreboot.org  Mon May 16 02:52:04 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sun, 15 May 2011 17:52:04 -0700
Subject: [coreboot] [commit] r6591 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <20110515235207.19241.qmail@stuge.se>
References: <E1QLjRz-0004mT-Cy@ra.coresystems.de>
	<20110515235207.19241.qmail@stuge.se>
Message-ID: <4DD07534.9050507@coreboot.org>

On 5/15/11 4:52 PM, Peter Stuge wrote:
> repository service wrote:
>> Log:
>> Enable rom cache early to reduce boot time.
>> +++ trunk/src/mainboard/amd/persimmon/romstage.c	Mon May 16 00:06:09 2011	(r6591)
>> @@ -47,6 +47,11 @@
>>     u32 val;
>>     u8 reg8;
>>
>> +  // all cores: allow caching of flash chip code and data
>> +  // (there are no cache-as-ram reliability concerns with family 14h)
>> +  __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
>> +  __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
> Is this something that we should have in component code rather than
> mainboard code?
>
> And when would it be suitable to *not* allow caching, if ever? I'm
> thinking if this should be an option anywhere, or not.

Yes, I think this should be added to the cache as ram code instead.



From peter at stuge.se  Mon May 16 02:52:47 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 02:52:47 +0200
Subject: [coreboot] [commit] r6585 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <E1QLjIC-0003RW-5I@ra.coresystems.de>
References: <E1QLjIC-0003RW-5I@ra.coresystems.de>
Message-ID: <20110516005247.25231.qmail@stuge.se>

repository service wrote:
> Log:
> Enable SPI cacheline prefetch early to reduce boot time.

This is the same commit message as the previous commit, r6584.

..

> +++ trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:56:03 2011	(r6585)
> @@ -50,6 +50,21 @@
>    // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
>    __writemsr (0xc0010062, 0);
>  
> +  if (boot_cpu())
> +    {
> +    u8 reg8;
> +    // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
> +    outb(0x24, 0xCD6);
> +    reg8 = inb(0xCD7);
> +    reg8 |= 1;
> +    reg8 &= ~(1 << 1);
> +    outb(reg8, 0xCD7);
> +  
> +    // program SB800 MiscCntrl
> +    *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
> +    *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
> +    }

..but the code does something else?


//Peter



From stefan.reinauer at coreboot.org  Mon May 16 02:57:31 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sun, 15 May 2011 17:57:31 -0700
Subject: [coreboot] [commit] r6584 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <20110515225724.13527.qmail@stuge.se>
References: <E1QLjGH-0001OP-8d@ra.coresystems.de>
	<20110515225724.13527.qmail@stuge.se>
Message-ID: <4DD0767B.9060000@coreboot.org>

On 5/15/11 3:57 PM, Peter Stuge wrote:
> repository service wrote:
>> +++ trunk/src/mainboard/amd/persimmon/romstage.c	Sun May 15 23:54:04 2011	(r6584)
> ..
>> +  // early enable of PrefetchEnSPIFromHost
>> +  if (boot_cpu())
>> +    {
>> +    __outdword (0xcf8, 0x8000a3b8);
>> +    __outdword (0xcfc, __indword (0xcfc) | 0<<  24);
>> +    }
> PCI function? And maybe this, as well as the 33MHz setup, is good to
> have in the chipset code, as opposed to duplicated per mainboard?
>
and in coreboot there already is a function to do a dword IO access: 
outl(). At least while not under vendorcode/ that should be used (if 
it's not a PCI access in which case pci_config... should be used)

It took me a long time to get rid of 6 instances of printk. I don't 
really want to have to do the same again for outb/outw/outl ;-)

Stefan



From cristi.magherusan at net.utcluj.ro  Mon May 16 03:17:35 2011
From: cristi.magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Mon, 16 May 2011 04:17:35 +0300 (EEST)
Subject: [coreboot] [patch] crossgcc make target
Message-ID: <23238.89.247.128.65.1305508655.squirrel@mail.utcluj.ro>

Please see the patch below.

Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan at gmail.com>

diff --git a/Makefile b/Makefile
index ac7115d..69e32a4 100644
--- a/Makefile
+++ b/Makefile
@@ -242,6 +242,12 @@ $(shell mkdir -p $(obj) $(objutil)/kconfig/lxdialog
$(additional-dirs) $(alldirs
 cscope:
 	cscope -bR

+crossgcc: clean-for-update
+	$(MAKE) -C util/crossgcc build
+
+crossgcc-clean: clean-for-update
+	$(MAKE) -C util/crossgcc clean
+
 doxy: doxygen
 doxygen:
 	$(DOXYGEN) documentation/Doxyfile.coreboot
diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile
new file mode 100644
index 0000000..ea19e6f
--- /dev/null
+++ b/util/crossgcc/Makefile
@@ -0,0 +1,12 @@
+all: build
+
+build:
+	./buildgcc
+
+clean:
+	rm -rf xgcc
+
+distclean: clean
+	rm -rf tarballs/*
+
+.PHONY: all clean distclean build









From svn at coreboot.org  Mon May 16 03:35:05 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 03:35:05 +0200
Subject: [coreboot] [commit] r6598 - in trunk: . util/crossgcc
Message-ID: <E1QLmi9-0004yn-RC@ra.coresystems.de>

Author: stuge
Date: Mon May 16 03:35:03 2011
New Revision: 6598
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6598

Log:
Add crossgcc target to automatically build reference toolchain

This means that a simple:

$ make crossgcc

creates the reference toolchain in the correct directory. Thanks to the
dependency on the clean-for-update target, an existing .xcompile along
with any compiled objects in build/ will be cleaned out, so the next
build will automatically use the newly created reference toolchain.

Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>

Added:
   trunk/util/crossgcc/Makefile
Modified:
   trunk/Makefile

Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile	Mon May 16 02:05:50 2011	(r6597)
+++ trunk/Makefile	Mon May 16 03:35:03 2011	(r6598)
@@ -242,6 +242,12 @@
 cscope:
 	cscope -bR
 
+crossgcc: clean-for-update
+	$(MAKE) -C util/crossgcc build
+
+crossgcc-clean: clean-for-update
+	$(MAKE) -C util/crossgcc clean
+
 doxy: doxygen
 doxygen:
 	$(DOXYGEN) documentation/Doxyfile.coreboot

Added: trunk/util/crossgcc/Makefile
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/util/crossgcc/Makefile	Mon May 16 03:35:03 2011	(r6598)
@@ -0,0 +1,9 @@
+all: build
+
+build:
+	./buildgcc
+
+clean:
+	rm -rf xgcc
+
+.PHONY: all build clean



From peter at stuge.se  Mon May 16 03:35:41 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 16 May 2011 03:35:41 +0200
Subject: [coreboot] [patch] crossgcc make target
In-Reply-To: <23238.89.247.128.65.1305508655.squirrel@mail.utcluj.ro>
References: <23238.89.247.128.65.1305508655.squirrel@mail.utcluj.ro>
Message-ID: <20110516013541.30104.qmail@stuge.se>

Cristi Magherusan wrote:
> Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan at gmail.com>

Skip the distclean target for now since it's not being called anyway,
and since the unpacked tarballs should also be cleaned up somehow.
(How?)

Acked-by: Peter Stuge <peter at stuge.se>

r6598



From scott at notabs.org  Mon May 16 06:46:46 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 15 May 2011 23:46:46 -0500
Subject: [coreboot] [commit] r6584 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <20110515225724.13527.qmail@stuge.se>
References: <E1QLjGH-0001OP-8d@ra.coresystems.de>
	<20110515225724.13527.qmail@stuge.se>
Message-ID: <825F5BC368374783897D19882A3857FE@asusp67>

Peter Stuge wrote:

]> +    __outdword (0xcf8, 0x8000a3b8);
]> +    __outdword (0xcfc, __indword (0xcfc) | 0 << 24);
]> +    }
]
]PCI function? And maybe this, as well as the 33MHz setup, is good to
]have in the chipset code, as opposed to duplicated per mainboard?

Hello Peter,

I will try improve this and some of the others, hopefully this week.
Yes, the code above looks odd, so I should at least explain why. This
and the other newly added early settings indeed duplicate settings made
later. The justification is/was 'early as possible' for boot time
reduction. With another change or two, both persimmon and asrock e350m1
boot to DOS time drop to 600 ms.

Maybe a bigger question is why the unusual pci config write coding?
Certainly a function call is just as good (and I will submit a change).
The code is a quick and dirty way to paste in a pci config write and
have it work for amd agesa as well as for all phases of UEFI. I used to
get frustrated over how complicated UEFI makes something as simple as a
write to base pci config space. A single function call? More like a
couple dozen lines of code: Call the OpenProtocol function pointer from
a global structure, passing half a dozen items including the GUID for PCI
protocol. Check for errors then call the write() member of the structure
it returns. Of course integer constants are often passed by address, so
separate allocation is needed for those. Check for and handle any error
returned by the write function, then call another function to close the
protocol. The code sequence above was my silent protest over this ordeal,
and it ended up in coreboot. I/O functions named like __outdword are 
supported by the Microsoft compilers used for UEFI, and can even be used
with no prototype.

Thanks,
Scott





From scott at notabs.org  Mon May 16 07:18:35 2011
From: scott at notabs.org (Scott Duplichan)
Date: Mon, 16 May 2011 00:18:35 -0500
Subject: [coreboot] [commit] r6591 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <4DD07534.9050507@coreboot.org>
References: <E1QLjRz-0004mT-Cy@ra.coresystems.de><20110515235207.19241.qmail@stuge.se>
	<4DD07534.9050507@coreboot.org>
Message-ID: <CD87FE6E545B4681888E5D0DEBD8F475@asusp67>

Stefan Reinauer wrote:

]>> +  // all cores: allow caching of flash chip code and data
]>> +  // (there are no cache-as-ram reliability concerns with family 14h)
]>> +  __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
]>> +  __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
]> Is this something that we should have in component code rather than
]> mainboard code?
]>
]> And when would it be suitable to *not* allow caching, if ever? I'm
]> thinking if this should be an option anywhere, or not.

Hello Peter,
This is a good question. For amd family 14h, caching of the flash chip
is appropriate at all times (though we could remove it before OS launch
to free an MTRR pair). 

The situation on family 10h is different. For family 10h, cached rom code
goes into L1, and then into L2 also. Because L2 is used for cache as
ram, excessive instruction caching can cause cache as ram failure.
For family 10h, agesa code provides an AllocateExecutionCache function
that limits instruction caching to a safe amount if too much is requested.
The function does not clear cache before enabling it, so the rule is
no instruction caching before calling AllocateExecutionCache.

For family 14h (and also 15h), rom code is cached in L1 only. This solves
the problem of rom chip caching causing cache as ram problems. It is 
important to use attribute WP when caching the rom chip, because that
is what causes the new L1-only behavior to be invoked.

Note that family 12h (Llano) has the family 10h behavior.

]Yes, I think this should be added to the cache as ram code instead.

Hello Stefan,

The code already exists in agesa function AllocateExecutionCache. The
early code is an attempt reduce boot time. In the past, I found systems
with many cores are where early cache enable really helps. Agesa and
some BIOS launch the cores serially, and launching 48 cores could take
significantly longer without the early cache enable. Even if cores 
are launched in parallel, uncached flash memory reads could cause a
flood of requests to the flash chip.

Thanks,
Scott





From scott at notabs.org  Mon May 16 07:51:16 2011
From: scott at notabs.org (Scott Duplichan)
Date: Mon, 16 May 2011 00:51:16 -0500
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <20110515234252.18124.qmail@stuge.se>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>
	<20110515234252.18124.qmail@stuge.se>
Message-ID: <65E8F18FA6CB4888B4AC4915F3845230@asusp67>

]Peter Stuge wrote:
]
]Reading this I think that there should be a Kconfig option to choose
]if the chipset should be set up as SATA IDE or AHCI.
]
]Talking to a lot of visitors at LinuxTag it is absolutely clear that
]this is an example of what should actually be an NVRAM option.
]
]Do we have some policy for where to place an option? I don't think we
]do. Do we want to create one?
]
]The purpose is to have a perfectly streamlined user experience across
]all different mainboards. Of course all boards don't support all
]options, but when two different boards *do* support an option, that
]option must be in the same place, working the same way.
]
]The balance between compile time options and NVRAM options is not so
]easy. :\

Hello Peter,

Right now, the sata controller is hard-coded to use the AHCI software
interface, and the IDE controller is hidden. I think for the most
part, AHCI mode should be OK for every use. But certainly at least a
compile option for the IDE software interface is needed. Would a 
kconfig option make sense? I am not familiar with coreboot nvram 
use.

In what situation is AHCI undesirable? For me, the answer is older
editions of windows. If you happen to want to test windows xp setup
using a standard setup CD, windows will not find the drives because
it has no AHCI support. The standard solution is the F6 floppy method
of adding an AHCI driver, but lack of floppy support on new boards 
makes this method difficult. I use the http://www.nliteos.com/ tool
to make a custom setup CD. But this method requires a new custom CD
for each chipset. The ability to disable AHCI is certainly a good
feature to have when doing a quick test of an older OS. The OS I use
for my own development machine is windows server 2003 x64 edition.
This OS has no in-box AHCI driver, so I am familiar with the hassle.

Thanks,
Scott





From scott at notabs.org  Mon May 16 07:55:46 2011
From: scott at notabs.org (Scott Duplichan)
Date: Mon, 16 May 2011 00:55:46 -0500
Subject: [coreboot] AMD Persimmon update
In-Reply-To: <BANLkTinzzh9owDSPQ7mcNoktjuX_Bdve4Q@mail.gmail.com>
References: <AcwHFoUqRoIXoGvWQa+u/zj10boGfw==><B0FDAE3158B74F6497F657AD6D0408C4@m3a78>
	<BANLkTinzzh9owDSPQ7mcNoktjuX_Bdve4Q@mail.gmail.com>
Message-ID: <01A112D9226A441F89D3900F5227C7F2@asusp67>

Marc Jones wrote:

]Hi Scott,
]
]I'm acking and committing all except the LTO patch, which should wait
]for the crossgcc changes for gcc4.6. i only made a minor tweak to the
]AHCI patch to add a #define for the PCI DID.

Thanks Marc. I noticed the PCI ID also, how embarrassing! I will test
everything and try to make some of the changes suggested by Peter and
Stefan. After that, I need to do the same for asrock e350m1.

Thanks,
Scott




From patrick at georgi-clan.de  Mon May 16 09:18:09 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 16 May 2011 09:18:09 +0200
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <20110515234252.18124.qmail@stuge.se>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>
	<20110515234252.18124.qmail@stuge.se>
Message-ID: <4DD0CFB1.8090805@georgi-clan.de>

Am 16.05.2011 01:42, schrieb Peter Stuge:
> Talking to a lot of visitors at LinuxTag it is absolutely clear that
> this is an example of what should actually be an NVRAM option.
> 
> Do we have some policy for where to place an option? I don't think we
> do. Do we want to create one?
My idea for a long term plan:
- move most stuff to NVRAM
- allow defaults in NVRAM config (per chip component)
- allow boards to override these defaults
- allow boards to lock down options (so they're compiled out in our code
and present as "hard coded values" in cbtable)
- probably/eventually: allow user to change defaults/lock them down in
Kconfig

That way we can make everything flexible, yet lock down options that
make no sense (eg. disable IDE/SATA option on boards with IDE function
on chip but no connector on board).
The hard part will be (again) how to extend Kconfig, and I guess this
will require automatic Kconfig file creation (ie. Makefile magic).
But since this is the last step (right after Infrastructure
Projects/CMOS), this can wait.


Patrick



From tjourdan at interfaceconcept.com  Mon May 16 09:54:49 2011
From: tjourdan at interfaceconcept.com (Thomas Jourdan)
Date: Mon, 16 May 2011 09:54:49 +0200
Subject: [coreboot] Win7 on Intel Eagle Heights
In-Reply-To: <4DCDD92F.5030006@coreboot.org>
References: <BANLkTi=C0jFmaSLneHAFvYoURepiZoFt6Q@mail.gmail.com>
	<4DCDD92F.5030006@coreboot.org>
Message-ID: <1305532489.2332.7.camel@thje6600>

Hi

Le vendredi 13 mai 2011 ? 18:21 -0700, Stefan Reinauer a ?crit : 
> On 5/13/11 8:57 AM, Thomas JOURDAN wrote:
> > I'm trying to get Windows 7 booting on my Intel Eagle Heights 
> > evaluation board. I tried to follow all the ACPI tips to get Window$ 
> > to boot but I can't figure out the bug I'm facing. I'm using a checked 
> > build version of Win 7 64-bits. When I start the installer, the first 
> > text screen is ok (windows is copying files...) then it switches to 
> > graphics mode (green progress bar with logo). Less than a second after 
> > switching from text to graphics mode : BSOD.
> 
> Hi Thomas,
> 
> Looks like Windows 7 crashes in the "Windows Driver Foundation" with an 
> illegal memory access. Possibly this is due to an incomplete ACPI 
> implementation for the board.

Yes that what I suspect too but so far I can't figure out which ACPI
part could be missing. According to my probe, after the page
translation, the guilty address seems to point to valid memory area
(DDR). 

> Please have a look at the kontron/986lcd-m ACPI code for a modular 
> sample implementation that can boot Windows 7 and 
> http://www.coreboot.org/ACPI for more information on ACPI and ACPI 
> debugging.

When I said I followed ACPI tips I mean I refered to kontron/986lcd-m,
the coreboot acpi page, and also some tricks disccussed on the mailing
list (64-bits alignment, fadt correct size according to version...).

I was hoping someone already met this issue and could give me a clue.

Regards, 
Thomas




From andrew.goodbody at tadpole.com  Mon May 16 11:50:10 2011
From: andrew.goodbody at tadpole.com (Andrew Goodbody)
Date: Mon, 16 May 2011 02:50:10 -0700
Subject: [coreboot] Alternate for serial port debug messages
In-Reply-To: <BANLkTikbHU3sae8V2-2pNDbwZLkoV06DfA@mail.gmail.com>
References: <1305051059.5265.6.camel@ubuntu.ubuntu-domain>	<BANLkTincQm_=e-ZY1uWAUh2eXDcEQi3xbA@mail.gmail.com>	<BANLkTinzTqYRyLW9ceQDuHLEzHv47zQAQA@mail.gmail.com>	<4DCBB64A.5050607@tadpole.com>	<BANLkTi=PP61tJXfUMGhOoiA22Ws7VZ07Lg@mail.gmail.com>
	<BANLkTikbHU3sae8V2-2pNDbwZLkoV06DfA@mail.gmail.com>
Message-ID: <4DD0F352.8000500@tadpole.com>

Vikram Narayanan wrote:
> On Sat, May 14, 2011 at 8:35 AM, Gregg Levine <gregg.drwho8 at gmail.com> wrote:
>> On Thu, May 12, 2011 at 6:28 AM, Andrew Goodbody
>> <andrew.goodbody at tadpole.com> wrote:
>>> Vikram Narayanan wrote:
> ok. I am planning to buy one. Please share your thoughs on which one to buy.

NET20DC, it is the simplest, the cheapest by far and will work.

> In the links(in wiki page), it is mentioned that,
> === from the link (http://www.ajaystech.com/net20dc.htm)
> System Requirements
> 
>     Target Computer: Windows Vista and later OS
>     Host Computer: Windows 2000 and later OS
> ===
> Does this mean anything? or this stuff can also be used for boot time
> debugging (coreboot) ?

It is only relevant for debugging Windows using the kernel debugger, as 
that is not what you are doing you can ignore those requirements.
As for debugging coreboot I believe that it is supposed to work but I 
have not tried it myself so cannot tell you how functional the support 
actually is.

Andrew



From vidwer at gmail.com  Mon May 16 13:51:34 2011
From: vidwer at gmail.com (Idwer Vollering)
Date: Mon, 16 May 2011 13:51:34 +0200
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <65E8F18FA6CB4888B4AC4915F3845230@asusp67>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>
	<20110515234252.18124.qmail@stuge.se>
	<65E8F18FA6CB4888B4AC4915F3845230@asusp67>
Message-ID: <BANLkTinedjeuNxqvSkeNztH63Z-hQbxY7g@mail.gmail.com>

2011/5/16 Scott Duplichan <scott at notabs.org>:
> If you happen to want to test windows xp setup
> using a standard setup CD, windows will not find the drives because
> it has no AHCI support. The standard solution is the F6 floppy method
> of adding an AHCI driver, but lack of floppy support on new boards
> makes this method difficult. I use the http://www.nliteos.com/ tool
> to make a custom setup CD. But this method requires a new custom CD
> for each chipset.

Have you though of using an USB flash drive, to install Windows from?
http://www.windowsvalley.com/install-windows-2000-xp-2003-using-usb-storage-device-pen-drive/



From svn at coreboot.org  Mon May 16 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 16 May 2011 16:00:02 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1QLyL4-0002xs-51@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110516/1c6b2d0e/attachment.html>

From marcj303 at gmail.com  Mon May 16 17:16:43 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 16 May 2011 09:16:43 -0600
Subject: [coreboot] [commit] r6582 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <20110515225434.13162.qmail@stuge.se>
References: <E1QLjAm-00048l-9u@ra.coresystems.de>
	<20110515225434.13162.qmail@stuge.se>
Message-ID: <BANLkTi=-VHpwLW7n0QfHN=C-1cMnjJ=HRw@mail.gmail.com>

On Sun, May 15, 2011 at 4:54 PM, Peter Stuge <peter at stuge.se> wrote:
> repository service wrote:
>> +++ trunk/src/mainboard/amd/persimmon/romstage.c ? ? ?Sun May 15 23:48:22 2011 ? ? ? ?(r6582)
> ..
>> + ? ?volatile u32 *spiBase = (void *) 0xa0000000;
>> + ? ?u32 save;
>> + ? ?__outdword (0xcf8, 0x8000a3a0);
>> + ? ?save = __indword (0xcfc);
>> + ? ?__outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
>> + ? ?spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
>> + ? ?spiBase [0] |= 1 << 18; // fast read enable
>> + ? ?__outdword (0xcfc, save); // clear temp base
>
> Are there some PCI access functions available also in romstage?

Yes indeed there are. We will fix these up.

Marc



-- 
http://se-eng.com



From vikram186 at gmail.com  Mon May 16 16:54:26 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Mon, 16 May 2011 20:24:26 +0530
Subject: [coreboot] Issue #16: I2C driver and mainboard Config.lb
Message-ID: <1305557666.2415.38.camel@ubuntu.ubuntu-domain>

Hi,

Can any one share the latest info on this ticket? While discussing this
with Stefan Reinauer, he shared me some info on this. I am also adding
this here.

>From Ollie Lho:
>There are a lot of mainboards using driver/generic/generic as the i2c
driver of their HW monitor. They should be changed to driver/i2c/*.
Stefan Reinauer: 
And it seems drivers/generic/generic does not exist anymore or
potentially never existed.

>Rename driver/i2c/i2cmux to driver/i2c/pca9556
Stefan Reinauer: 
I think the problem was that i2cmux was not a generic i2cmux driver but
instead a driver for the pca9556 but i am not sure anymore. it would
take someone to look into that.

-
Thanks,
Vikram




From svn at coreboot.org  Mon May 16 17:32:29 2011
From: svn at coreboot.org (repository service)
Date: Mon, 16 May 2011 17:32:29 +0200
Subject: [coreboot] [commit] r6599 - trunk
Message-ID: <E1QLzmX-00063F-8C@ra.coresystems.de>

Author: oxygene
Date: Mon May 16 17:32:28 2011
New Revision: 6599
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6599

Log:
Move crossgcc rules to coreboot specific Makefile

Toplevel Makefile should (as far as possible) be coreboot-agnostic,
we have Makefile.inc for that.

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/Makefile
   trunk/Makefile.inc

Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile	Mon May 16 03:35:03 2011	(r6598)
+++ trunk/Makefile	Mon May 16 17:32:28 2011	(r6599)
@@ -242,12 +242,6 @@
 cscope:
 	cscope -bR
 
-crossgcc: clean-for-update
-	$(MAKE) -C util/crossgcc build
-
-crossgcc-clean: clean-for-update
-	$(MAKE) -C util/crossgcc clean
-
 doxy: doxygen
 doxygen:
 	$(DOXYGEN) documentation/Doxyfile.coreboot

Modified: trunk/Makefile.inc
==============================================================================
--- trunk/Makefile.inc	Mon May 16 03:35:03 2011	(r6598)
+++ trunk/Makefile.inc	Mon May 16 17:32:28 2011	(r6599)
@@ -230,3 +230,10 @@
 	done; \
 	test $$FAILED -eq 0 || { echo "ERROR: $$FAILED test(s) failed." &&  exit 1; }; \
 	rm -f $$LINTLOG
+
+crossgcc: clean-for-update
+	$(MAKE) -C util/crossgcc build
+
+crossgcc-clean: clean-for-update
+	$(MAKE) -C util/crossgcc clean
+



From marcj303 at gmail.com  Mon May 16 18:37:00 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 16 May 2011 10:37:00 -0600
Subject: [coreboot] Win7 on Intel Eagle Heights
In-Reply-To: <1305532489.2332.7.camel@thje6600>
References: <BANLkTi=C0jFmaSLneHAFvYoURepiZoFt6Q@mail.gmail.com>
	<4DCDD92F.5030006@coreboot.org> <1305532489.2332.7.camel@thje6600>
Message-ID: <BANLkTi=ddOGPOG4c89OS_4tewY42u-=7vQ@mail.gmail.com>

On Mon, May 16, 2011 at 1:54 AM, Thomas Jourdan
<tjourdan at interfaceconcept.com> wrote:
> Hi
>
> Le vendredi 13 mai 2011 ? 18:21 -0700, Stefan Reinauer a ?crit :
>> On 5/13/11 8:57 AM, Thomas JOURDAN wrote:
>> > I'm trying to get Windows 7 booting on my Intel Eagle Heights
>> > evaluation board. I tried to follow all the ACPI tips to get Window$
>> > to boot but I can't figure out the bug I'm facing. I'm using a checked
>> > build version of Win 7 64-bits. When I start the installer, the first
>> > text screen is ok (windows is copying files...) then it switches to
>> > graphics mode (green progress bar with logo). Less than a second after
>> > switching from text to graphics mode : BSOD.
>>
>> Hi Thomas,
>>
>> Looks like Windows 7 crashes in the "Windows Driver Foundation" with an
>> illegal memory access. Possibly this is due to an incomplete ACPI
>> implementation for the board.
>
> Yes that what I suspect too but so far I can't figure out which ACPI
> part could be missing. According to my probe, after the page
> translation, the guilty address seems to point to valid memory area
> (DDR).
>
>> Please have a look at the kontron/986lcd-m ACPI code for a modular
>> sample implementation that can boot Windows 7 and
>> http://www.coreboot.org/ACPI for more information on ACPI and ACPI
>> debugging.
>
> When I said I followed ACPI tips I mean I refered to kontron/986lcd-m,
> the coreboot acpi page, and also some tricks disccussed on the mailing
> list (64-bits alignment, fadt correct size according to version...).
>
> I was hoping someone already met this issue and could give me a clue.
>
> Regards,
> Thomas

Hi Thomas,

ScottD had a FADT fix for checked build on Persimmon that might be
related to your issue.

http://www.coreboot.org/pipermail/coreboot/2011-May/065115.html

Marc


-- 
http://se-eng.com



From marcj303 at gmail.com  Mon May 16 18:31:55 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 16 May 2011 10:31:55 -0600
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <4DD0CFB1.8090805@georgi-clan.de>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>
	<20110515234252.18124.qmail@stuge.se>
	<4DD0CFB1.8090805@georgi-clan.de>
Message-ID: <BANLkTimrUE8qPKJaMsCzxYDzTCb0LhCyGQ@mail.gmail.com>

On Mon, May 16, 2011 at 1:18 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 16.05.2011 01:42, schrieb Peter Stuge:
>> Talking to a lot of visitors at LinuxTag it is absolutely clear that
>> this is an example of what should actually be an NVRAM option.
>>
>> Do we have some policy for where to place an option? I don't think we
>> do. Do we want to create one?
> My idea for a long term plan:
> - move most stuff to NVRAM
> - allow defaults in NVRAM config (per chip component)
> - allow boards to override these defaults
> - allow boards to lock down options (so they're compiled out in our code
> and present as "hard coded values" in cbtable)
> - probably/eventually: allow user to change defaults/lock them down in
> Kconfig
>
> That way we can make everything flexible, yet lock down options that
> make no sense (eg. disable IDE/SATA option on boards with IDE function
> on chip but no connector on board).
> The hard part will be (again) how to extend Kconfig, and I guess this
> will require automatic Kconfig file creation (ie. Makefile magic).
> But since this is the last step (right after Infrastructure
> Projects/CMOS), this can wait.
>

These are hard problems and I don't know that there is a good answer.
Each option seems like a good place to configure the platform, but all
have drawbacks.

1. Kconfig is a poor place for device and platform configuration
options. Kconfig is the right place for coreboot build options and
standard features. The advantage of Kconfig is that the options are
available in romstage.

2. CMOS is not a good place for platform options either. It is good
for runtime options, but I don't think that there are many options for
users to change. What options users would change and how will they
change them? CMOS options could even go into the device tree.

3. Devicetree is a good place for platform configuration, but the
allocator is complicated and not documented. Options are not available
in the romstage.

We should come up with some guidelines on what types of coreboot
configuration belongs where. Each developer guesses each time or does
what is easy for them at the time.

Marc


-- 
http://se-eng.com



From patrick at georgi-clan.de  Mon May 16 19:26:51 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 16 May 2011 19:26:51 +0200
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <BANLkTimrUE8qPKJaMsCzxYDzTCb0LhCyGQ@mail.gmail.com>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>
	<20110515234252.18124.qmail@stuge.se>
	<4DD0CFB1.8090805@georgi-clan.de>
	<BANLkTimrUE8qPKJaMsCzxYDzTCb0LhCyGQ@mail.gmail.com>
Message-ID: <4DD15E5B.60607@georgi-clan.de>

Am 16.05.2011 18:31, schrieb Marc Jones:
> These are hard problems and I don't know that there is a good answer.
> Each option seems like a good place to configure the platform, but all
> have drawbacks.
Right now CMOS is somewhat unpopular because it's strictly per-board.
Once we're able to move definitions for options to chipsets (if they
belong there), they're actually useful.

> 1. Kconfig is a poor place for device and platform configuration
> options. Kconfig is the right place for coreboot build options and
> standard features. The advantage of Kconfig is that the options are
> available in romstage.
Kconfig would be proper for user overrides of options. Definitely a
nicer way than requiring users to manage custom Kconfig _and_ custom
$whatever files. Hence Kconfig, but that should come last, once
everything else works properly.

> 2. CMOS is not a good place for platform options either. It is good
> for runtime options, but I don't think that there are many options for
> users to change. What options users would change and how will they
> change them? CMOS options could even go into the device tree.
The problem is that these overlap. See the example IDE/SATA. They ought
to be user configurable (so users can disable IDE on boards that provide
both), but they're also platform options, in case the board has no
connector (in which case it's useless to provide such an option).

So chipset defines that IDE and SATA (and their config options exist),
board overrides that and disables IDE (because no IDE exists).


> 3. Devicetree is a good place for platform configuration, but the
> allocator is complicated and not documented. Options are not available
> in the romstage.
For some things, yes. Others not so. This is really hard, but I'll
concentrate on getting CMOS handling in shape so we can actually make
use of it, instead of the poor job we're doing now.

> We should come up with some guidelines on what types of coreboot
> configuration belongs where. Each developer guesses each time or does
> what is easy for them at the time.
Because our tools suck. IMHO Guidelines are useless at this point.


Patrick



From marcj303 at gmail.com  Mon May 16 19:27:40 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 16 May 2011 11:27:40 -0600
Subject: [coreboot] Ok, let's move on. What shold we do to CBFS?
In-Reply-To: <BANLkTinop3EWscUf7c2ksb1t8fxxcUW=Wg@mail.gmail.com>
References: <BANLkTint3JxTZtHcGWzhQLXFPwdqLjekHQ@mail.gmail.com>
	<BANLkTinop3EWscUf7c2ksb1t8fxxcUW=Wg@mail.gmail.com>
Message-ID: <BANLkTikujBMFPkLrZOAdhd6wu97MLRqifQ@mail.gmail.com>

Hi Hamo,


On Fri, May 13, 2011 at 11:07 PM, Hamo <hamo.by at gmail.com> wrote:
> Ping...
>
> On Wed, May 11, 2011 at 8:51 PM, Hamo <hamo.by at gmail.com> wrote:
>> Dear lists,
>> I have got the idea on how to deal with xcompile script for ARM. Now,
>> let's move on to CBFS.
>> It is one of the most difficult part since CBFS is almost hard-coded
>> to X86 architecture. On ARM,
>> we need CBFS like this:
>>
>>
>> /---------------\ <-- Start of ROM
>> | /-----------\ |
>> | | Reset ?| | <- 0x0
>> | |-----------| |
>> | |IVs ? ? ?| |
>> | |-----------| |
>> | |Boot ? ?| |
>> | |Block ? | |
>> | \-----------/ |
>> | ? ? ? ? ? ? ? |
>> | /-----------\ | --|
>> | | Header| | ? |
>> | |-----------| | ? |
>> | | Name ?| | ? |
>> | |-----------| | ? |-- Component
>> | |Data ? ?| | ? |
>> | |.. ? ? ? ? | | ? |
>> | \-----------/ | --|
>> | ? ? ? ? ? ? ? |
>> | ... ? ? ? ? ? |
>> | /-----------\ | --|
>> | | Header| | ? |
>> | |-----------| | ? |
>> | | Name ?| | ? |
>> | |-----------| | ? |-- Component
>> | |Data ? ?| | ? |
>> | |.. ? ? ? ? | | ? |
>> | \-----------/ | --|
>> \---------------/
>>
>>
>> Where should we put the CBFS master header and the pointer to it?
>> I have no idea of how to implement it and not break it on X86
>> architecture. Any comment or suggestion is very welcome.
>>
>
>

It is good that you are starting to plan this. I think that the main
thing is to get an entrypoint that works for ARM. I would try to leave
the cbfs architecture in place and just add another entrypoint. The
x86 entrypoint starts at the top and jumps down, the ARM entrypoint
cold be located at 0x0 and jump to the same location that x86
entrypoint uses. I don't know if there is a problem with that.  What
are your ideas about this?

Stefan and Patrick might have some thoughts on this too.

Marc

-- 
http://se-eng.com



From marcj303 at gmail.com  Mon May 16 19:56:32 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 16 May 2011 11:56:32 -0600
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <4DD15E5B.60607@georgi-clan.de>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>
	<20110515234252.18124.qmail@stuge.se>
	<4DD0CFB1.8090805@georgi-clan.de>
	<BANLkTimrUE8qPKJaMsCzxYDzTCb0LhCyGQ@mail.gmail.com>
	<4DD15E5B.60607@georgi-clan.de>
Message-ID: <BANLkTiktWx2JCGUb_hAQ0naC+jWxGMN2QQ@mail.gmail.com>

On Mon, May 16, 2011 at 11:26 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 16.05.2011 18:31, schrieb Marc Jones:
>> These are hard problems and I don't know that there is a good answer.
>> Each option seems like a good place to configure the platform, but all
>> have drawbacks.
> Right now CMOS is somewhat unpopular because it's strictly per-board.
> Once we're able to move definitions for options to chipsets (if they
> belong there), they're actually useful.
>
>> 1. Kconfig is a poor place for device and platform configuration
>> options. Kconfig is the right place for coreboot build options and
>> standard features. The advantage of Kconfig is that the options are
>> available in romstage.
> Kconfig would be proper for user overrides of options. Definitely a
> nicer way than requiring users to manage custom Kconfig _and_ custom
> $whatever files. Hence Kconfig, but that should come last, once
> everything else works properly.
>

I think that Kconfig should be about building the platform (make). We
have overloaded it with platform configurations that I feel don't
really belong there.  There are a few items for where the make needs
to understand the the code size requirement etc, but options about
memory types, and CPU or slot numbers etc, don't belong there.

>> 2. CMOS is not a good place for platform options either. It is good
>> for runtime options, but I don't think that there are many options for
>> users to change. What options users would change and how will they
>> change them? CMOS options could even go into the device tree.
> The problem is that these overlap. See the example IDE/SATA. They ought
> to be user configurable (so users can disable IDE on boards that provide
> both), but they're also platform options, in case the board has no
> connector (in which case it's useless to provide such an option).
>
> So chipset defines that IDE and SATA (and their config options exist),
> board overrides that and disables IDE (because no IDE exists).
>

I agree, but I think that there are few options that might be useful
for an end user to change, but there are many platform config that are
not appropriate CMOS options.

>
>> 3. Devicetree is a good place for platform configuration, but the
>> allocator is complicated and not documented. Options are not available
>> in the romstage.
> For some things, yes. Others not so. This is really hard, but I'll
> concentrate on getting CMOS handling in shape so we can actually make
> use of it, instead of the poor job we're doing now.
>

CMOS options should only be for runtime options. I think that there
are far more build time and platform configurations than there are
runtime. But, I'll be interested to see what your thoughts are.

>> We should come up with some guidelines on what types of coreboot
>> configuration belongs where. Each developer guesses each time or does
>> what is easy for them at the time.
> Because our tools suck. IMHO Guidelines are useless at this point.
>
>
> Patrick

I think that any guidance we could provide would be an improvement.

Marc


-- 
http://se-eng.com



From nitr0 at seti.kr.ua  Mon May 16 19:02:03 2011
From: nitr0 at seti.kr.ua (Andrew)
Date: Mon, 16 May 2011 20:02:03 +0300
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <BANLkTimrUE8qPKJaMsCzxYDzTCb0LhCyGQ@mail.gmail.com>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de>	<20110515234252.18124.qmail@stuge.se>	<4DD0CFB1.8090805@georgi-clan.de>
	<BANLkTimrUE8qPKJaMsCzxYDzTCb0LhCyGQ@mail.gmail.com>
Message-ID: <4DD1588B.4070108@seti.kr.ua>

16.05.2011 19:31, Marc Jones ?????:
>
> 2. CMOS is not a good place for platform options either. It is good
> for runtime options, but I don't think that there are many options for
> users to change. What options users would change and how will they
> change them? CMOS options could even go into the device tree.
>
IMHO device operation modes (for ex., AHCI/legacy IDE for SATA, LPT port 
modes, etc) should be in CMOS. Also switches for enabling/disabling 
devices (LPT, FDD, IDE/SATA, etc) should be in CMOS.



From anders at jenbo.dk  Mon May 16 22:01:31 2011
From: anders at jenbo.dk (=?utf-8?B?QW5kZXJzIGplbmJv?=)
Date: Mon, 16 May 2011 22:01:31 +0200
Subject: [coreboot]
	=?utf-8?q?Kconfig_vs=2E_devicetree_vs=2E_CMOS_policy_f?=
	=?utf-8?q?or_options=3F?=
Message-ID: <20110516200217.215882413A0D@csmtp3.one.com>

Is there any benefit to actually disabling this stuff?

Mvh Anders

----- Reply message -----
Fra: "Andrew" <nitr0 at seti.kr.ua>
Dato: man., maj 16, 2011 19:02
Emne: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
Til: <coreboot at coreboot.org>

16.05.2011 19:31, Marc Jones ?????:
>
> 2. CMOS is not a good place for platform options either. It is good
> for runtime options, but I don't think that there are many options for
> users to change. What options users would change and how will they
> change them? CMOS options could even go into the device tree.
>
IMHO device operation modes (for ex., AHCI/legacy IDE for SATA, LPT port 
modes, etc) should be in CMOS. Also switches for enabling/disabling 
devices (LPT, FDD, IDE/SATA, etc) should be in CMOS.

-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
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From anders at jenbo.dk  Mon May 16 22:02:25 2011
From: anders at jenbo.dk (=?utf-8?B?QW5kZXJzIGplbmJv?=)
Date: Mon, 16 May 2011 22:02:25 +0200
Subject: [coreboot]
	=?utf-8?q?Kconfig_vs=2E_devicetree_vs=2E_CMOS_policy_f?=
	=?utf-8?q?or_options=3F?=
Message-ID: <20110516200257.93361180A2C33@csmtp1.one.com>

Is there any benefit to actually disabling this stuff?

Mvh Anders

----- Reply message -----
Fra: "Andrew" <nitr0 at seti.kr.ua>
Dato: man., maj 16, 2011 19:02
Emne: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
Til: <coreboot at coreboot.org>

16.05.2011 19:31, Marc Jones ?????:
>
> 2. CMOS is not a good place for platform options either. It is good
> for runtime options, but I don't think that there are many options for
> users to change. What options users would change and how will they
> change them? CMOS options could even go into the device tree.
>
IMHO device operation modes (for ex., AHCI/legacy IDE for SATA, LPT port 
modes, etc) should be in CMOS. Also switches for enabling/disabling 
devices (LPT, FDD, IDE/SATA, etc) should be in CMOS.

-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
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From marcj303 at gmail.com  Mon May 16 23:27:39 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 16 May 2011 15:27:39 -0600
Subject: [coreboot] [commit] r6592 - in trunk/src:
	mainboard/amd/persimmon southbridge/amd/cimx_wrapper/sb800
In-Reply-To: <20110515235726.19747.qmail@stuge.se>
References: <E1QLjTh-0006ZX-Dg@ra.coresystems.de>
	<20110515235726.19747.qmail@stuge.se>
Message-ID: <BANLkTimggugnUcELi9uwMY+Xtuz-O7+jsQ@mail.gmail.com>

On Sun, May 15, 2011 at 5:57 PM, Peter Stuge <peter at stuge.se> wrote:
> repository service wrote:
>> +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c ? ? ? Mon May 16 00:07:56 2011 ? ? ? ?(r6592)
> ..
>> @@ -414,15 +413,16 @@
>> ? ? ? ? ? ? ? break;
>>
>> ? ? ? case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
>> + ? ? ? sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
>> + ? ? ? return;
>> ? ? ? case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
>> + ? ? ? sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
>> + ? ? ? return;
>> ? ? ? case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
>> + ? ? ? sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
>> + ? ? ? return;
>
> coreboot uses tab indent, right?
>
> That said, this reading of devicetree is a great improvement!

Thanks for the tab fix.
>
>
>> ? ? ? case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
>> - ? ? ? ? ? ? gpp_port = (dev->path.pci.devfn) & 0x03;
>> - ? ? ? ? ? ? if (dev->enabled) {
>> - ? ? ? ? ? ? ? ? ? ? sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
>> - ? ? ? ? ? ? } else {
>> - ? ? ? ? ? ? ? ? ? ? sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
>> - ? ? ? ? ? ? }
>> + ? ? ? sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
>
> Is it guaranteed that ENABLED == dev->enabled and DISABLED == !dev-enabled?
>
>

Yes, it is an enable bit in the register and POR defaults to disabled.

-- 
http://se-eng.com



From marcj303 at gmail.com  Mon May 16 23:48:19 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 16 May 2011 15:48:19 -0600
Subject: [coreboot] [commit] r6585 - trunk/src/mainboard/amd/persimmon
In-Reply-To: <20110516005247.25231.qmail@stuge.se>
References: <E1QLjIC-0003RW-5I@ra.coresystems.de>
	<20110516005247.25231.qmail@stuge.se>
Message-ID: <BANLkTin_j7k8pdeY9m61xV_t_Q-DTCZ2pg@mail.gmail.com>

On Sun, May 15, 2011 at 6:52 PM, Peter Stuge <peter at stuge.se> wrote:
> repository service wrote:
>> Log:
>> Enable SPI cacheline prefetch early to reduce boot time.
>
> This is the same commit message as the previous commit, r6584.
>
> ..
>
>> +++ trunk/src/mainboard/amd/persimmon/romstage.c ? ? ?Sun May 15 23:56:03 2011 ? ? ? ?(r6585)
>> @@ -50,6 +50,21 @@
>> ? ?// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
>> ? ?__writemsr (0xc0010062, 0);
>>
>> + ?if (boot_cpu())
>> + ? ?{
>> + ? ?u8 reg8;
>> + ? ?// SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
>> + ? ?outb(0x24, 0xCD6);
>> + ? ?reg8 = inb(0xCD7);
>> + ? ?reg8 |= 1;
>> + ? ?reg8 &= ~(1 << 1);
>> + ? ?outb(reg8, 0xCD7);
>> +
>> + ? ?// program SB800 MiscCntrl
>> + ? ?*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
>> + ? ?*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
>> + ? ?}
>
> ..but the code does something else?
>

Ugh, Sorry, I put the wrong commit message. It should be the following.


> Move SB800 clock init earlier to fix problem where initial serial port
> output is garbled.
>
> Signed-off-by: Scott Duplichan <scott at notabs.org>

Does anyone have a recommendation to update,fix, or otherwise improve
the svn history?

Thanks,
Marc

-- 
http://se-eng.com



From corey.osgood at gmail.com  Tue May 17 06:44:24 2011
From: corey.osgood at gmail.com (Corey Osgood)
Date: Tue, 17 May 2011 00:44:24 -0400
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <20110516200217.215882413A0D@csmtp3.one.com>
References: <20110516200217.215882413A0D@csmtp3.one.com>
Message-ID: <BANLkTi=UZ9u2CrCSqCKWe9kZzNrX1Tt1rw@mail.gmail.com>

On Mon, May 16, 2011 at 4:01 PM, Anders jenbo <anders at jenbo.dk> wrote:
> Is there any benefit to actually disabling this stuff?
>
> Mvh Anders

Sometimes it's necessary, like in the case of disabling integrated
graphics to allow a PCI/AGP/PCIe card to work. Other times, like
disabling ps2 and floppy devices, it shaves a little time off bootup,
because neither coreboot nor the guest OS have to do init for
non-existent devices. Still others it's just convenient, like
disabling a problematic or slow onboard NIC or poor quality audio
device, again in favor of another board.

-Corey

>
> ----- Reply message -----
> Fra: "Andrew" <nitr0 at seti.kr.ua>
> Dato: man., maj 16, 2011 19:02
> Emne: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
> Til: <coreboot at coreboot.org>
>
> 16.05.2011 19:31, Marc Jones ?????:
>>
>> 2. CMOS is not a good place for platform options either. It is good
>> for runtime options, but I don't think that there are many options for
>> users to change. What options users would change and how will they
>> change them? CMOS options could even go into the device tree.
>>
> IMHO device operation modes (for ex., AHCI/legacy IDE for SATA, LPT port
> modes, etc) should be in CMOS. Also switches for enabling/disabling
> devices (LPT, FDD, IDE/SATA, etc) should be in CMOS.
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From deepmindster at gmail.com  Tue May 17 10:41:41 2011
From: deepmindster at gmail.com (=?UTF-8?B?0JDQvdC00YDQtdC5INCa0LvQsNGD0YE=?=)
Date: Tue, 17 May 2011 12:41:41 +0400
Subject: [coreboot] How long will take to add coreboot support for my
 motherboard? Please, expert roughly estimation needed.
Message-ID: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>

Hello everybody,

I'm thinking about porting coreboot to my motherboard (epox 9NPA3I / 9NPA3J
/ 9NPAJ-3 / 9NPA3 Ultra Series). My chipset (CK804) and my superio
(F71872F/FG) are in supported list. According to this page (
http://www.coreboot.org/Support) port "might be easy" (exactly: "If you find
those in our list of Supported Chipsets and
Devices<http://www.coreboot.org/Supported_Chipsets_and_Devices>a port
might be easy").

I need roughly estimation for "easy" to decide is it possible for me to port
coreboot or not (in time-consuming terms). So, is "easy" up to 8 hours for
coreboot expert, or is it up to 40 hours for coreboot expert? Will be great
if you could give me estimation for 'worst' and 'best' variant.

Thank you very much,
Andrey
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From anton.kochkov at gmail.com  Tue May 17 10:59:30 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Tue, 17 May 2011 12:59:30 +0400
Subject: [coreboot] BIOS Protection Guidelines from NIST
Message-ID: <BANLkTin+KTSYLJk6utTxmPMrjDj_zRDahA@mail.gmail.com>

April 2011:

http://csrc.nist.gov/publications/nistpubs/800-147/NIST-SP800-147-April2011.pdf



From anders at jenbo.dk  Tue May 17 12:36:07 2011
From: anders at jenbo.dk (Anders Jenbo)
Date: Tue, 17 May 2011 12:36:07 +0200
Subject: [coreboot] How long will take to add coreboot support for my
 motherboard? Please, expert roughly estimation needed.
In-Reply-To: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>
References: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>
Message-ID: <4DD24F97.2020606@jenbo.dk>

Den 17-05-2011 10:41, ?????? ????? skrev:
>
> Hello everybody,
>
> I'm thinking about porting coreboot to my motherboard (epox 9NPA3I / 
> 9NPA3J / 9NPAJ-3 / 9NPA3 Ultra Series). My chipset (CK804) and my 
> superio (F71872F/FG) are in supported list. According to this page 
> (http://www.coreboot.org/Support) port "might be easy" (exactly: "If 
> you find those in our list of Supported Chipsets and Devices 
> <http://www.coreboot.org/Supported_Chipsets_and_Devices> a port might 
> be easy").
>
> I need roughlyestimation for "easy" to decide is it possible for me to 
> port coreboot or not (in time-consuming terms). So, is "easy" up to 8 
> hours for coreboot expert, or is it up to 40 hours for coreboot 
> expert? Will be great if you could give me estimation for 'worst' and 
> 'best' variant.
>
> Thank you very much,
> Andrey
>
It took me less then 8 hours to make my first port, and I'm not even a C 
programmer, mine was a best case senario as there was a sibling board 
already ported. I have also ported some where just the component where 
supported, that didn't take to long either, probably 7-10 hours.

Working on a board where only legacy code and docs are available I have 
probably spend around 12 hours to get to ram init.

I think the key to sussess is to have an easy way to reflash the bios 
when your image failes.

-Anders
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From paulepanter at users.sourceforge.net  Tue May 17 13:03:05 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 17 May 2011 13:03:05 +0200
Subject: [coreboot] BIOS Protection Guidelines from NIST
In-Reply-To: <BANLkTin+KTSYLJk6utTxmPMrjDj_zRDahA@mail.gmail.com>
References: <BANLkTin+KTSYLJk6utTxmPMrjDj_zRDahA@mail.gmail.com>
Message-ID: <1305630185.4065.53.camel@mattotaupa>

Am Dienstag, den 17.05.2011, 12:59 +0400 schrieb ????? ??????:
> April 2011:
> 
> http://csrc.nist.gov/publications/nistpubs/800-147/NIST-SP800-147-April2011.pdf

Thank you for the URL.

coreboot is not even mentioned. Searching for ?source? or ?closed? did
not turn anything up either, so I guess having access to the source code
is not mentioned as an essential way of protection.

I guess you guys (adding flashrom to CC) will have more comments. Will
you post them in your answers? Maybe we can contact the authors of this
article too.


Thanks,

Paul
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From vikram186 at gmail.com  Tue May 17 16:50:57 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Tue, 17 May 2011 20:20:57 +0530
Subject: [coreboot] How long will take to add coreboot support for my
 motherboard? Please, expert roughly estimation needed.
In-Reply-To: <4DD24F97.2020606@jenbo.dk>
References: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>
	<4DD24F97.2020606@jenbo.dk>
Message-ID: <BANLkTik2O7Kyu1rwzUvp4BwHWCo0zqqqLA@mail.gmail.com>

On Tue, May 17, 2011 at 4:06 PM, Anders Jenbo <anders at jenbo.dk> wrote:
> Den 17-05-2011 10:41, ?????? ????? skrev:
>
> Hello everybody,
>
> I'm thinking about porting coreboot to my motherboard (epox 9NPA3I / 9NPA3J
> / 9NPAJ-3 / 9NPA3 Ultra Series). My chipset (CK804) and my superio
> (F71872F/FG) are in supported list. According to this page
> (http://www.coreboot.org/Support) port "might be easy" (exactly: "If you
> find those in our list of Supported Chipsets and Devices a port might be
> easy").
>
> I need roughly estimation for "easy" to decide is it possible for me to port
> coreboot or not (in time-consuming terms). So, is "easy" up to 8 hours for
> coreboot expert, or is it up to 40 hours for coreboot expert? Will be great
> if you could give me estimation for 'worst' and 'best' variant.
>
> Thank you very much,
> Andrey
>
> It took me less then 8 hours to make my first port, and I'm not even a C
> programmer, mine was a best case senario as there was a sibling board
> already ported. I have also ported some where just the component where
> supported, that didn't take to long either, probably 7-10 hours.
>
> Working on a board where only legacy code and docs are available I have
> probably spend around 12 hours to get to ram init.
>
> I think the key to sussess is to have an easy way to reflash the bios when
> your image failes.
Seems quite inspirational to the people who wanted to port for new boards.
@ Stefan: Can you please share your opinions on this?

-
Thanks,
Vikram



From scott at notabs.org  Tue May 17 18:17:32 2011
From: scott at notabs.org (Scott Duplichan)
Date: Tue, 17 May 2011 11:17:32 -0500
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <BANLkTinedjeuNxqvSkeNztH63Z-hQbxY7g@mail.gmail.com>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de><20110515234252.18124.qmail@stuge.se><65E8F18FA6CB4888B4AC4915F3845230@asusp67>
	<BANLkTinedjeuNxqvSkeNztH63Z-hQbxY7g@mail.gmail.com>
Message-ID: <D8BACDD7E3ED47319A4A2DAD5565DC65@asusp67>

Idwer Vollering wtote:


]Have you though of using an USB flash drive, to install Windows from?
]http://www.windowsvalley.com/install-windows-2000-xp-2003-using-usb-]storag
e-device-pen-drive/

Hello Idwer,

Thanks for the suggestion and information. That could be useful in 
situations where no CD drive is available. I think it does not directly
solve the AHCI driver problem though. The Windows XP F6 driver mechanism
seems to be completely hard-coded for floppy drive only (tradition or USB).
For example, BIOS can make a USB flash drive appear as floppy drive A: to
DOS. The Windows XP F6 method is happy with this for the early access
where BIOS calls are used to read drive A:. But later in the setup process,
execution switches to native mode drivers for floppy access, at which time
only a real floppy or a limited number of models of USB floppy will work.
Somehow an AHCI driver has to get loaded in order for Windows XP setup to
find the hard disk. Probably nliteos could be used in combination with
the tool you mention though.

Thanks,
Scott




From peter at stuge.se  Tue May 17 19:22:39 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 17 May 2011 19:22:39 +0200
Subject: [coreboot] How long will take to add coreboot support for
	my	motherboard? Please, expert roughly estimation needed.
In-Reply-To: <BANLkTik2O7Kyu1rwzUvp4BwHWCo0zqqqLA@mail.gmail.com>
References: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>
	<4DD24F97.2020606@jenbo.dk>
	<BANLkTik2O7Kyu1rwzUvp4BwHWCo0zqqqLA@mail.gmail.com>
Message-ID: <20110517172239.23843.qmail@stuge.se>

Vikram Narayanan wrote:
> > It took me less then 8 hours to make my first port, and I'm not even a C
> > programmer, mine was a best case senario as there was a sibling board
> > already ported. I have also ported some where just the component where
> > supported, that didn't take to long either, probably 7-10 hours.
> >
> > Working on a board where only legacy code and docs are available I have
> > probably spend around 12 hours to get to ram init.
> >
> > I think the key to sussess is to have an easy way to reflash the bios when
> > your image failes.
> 
> Seems quite inspirational to the people who wanted to port for new
> boards.
> @ Stefan: Can you please share your opinions on this?

The time required of course depends on many factors. In general
terms, these are:

1. Ability to understand or learn C and programming languages in
   general, and hardware structure.
2. Hardware differences.
3. How much similar code there already exists in coreboot.
4. How readable the code is that does exist in coreboot and is
   relevant for the project.

In concrete terms, they are:

1. Programming and electronics experience, and abstract thinking
2. How similar your mainboard is to another already supported
   mainboard.
3. If *any* similar mainboard is already supported by coreboot.
   By similar I mean exact same relevant components; cpu north south
   superio.
4. Quality of coreboot code for cpu north south superio.

These are just the factors to consider *when all components are
supported already*. In ideal circumstances a board port needs to take
only one hour. In reality, circumstances are never ideal and the time
needed per board grows exponentially or even steeper still with the
number of less than ideal points to consider.

Worst case is so far 8-12 man-months for a coreboot expert.


//Peter



From deepmindster at gmail.com  Tue May 17 20:06:42 2011
From: deepmindster at gmail.com (=?UTF-8?B?0JDQvdC00YDQtdC5INCa0LvQsNGD0YE=?=)
Date: Tue, 17 May 2011 22:06:42 +0400
Subject: [coreboot] How long will take to add coreboot support for my
 motherboard? Please, expert roughly estimation needed.
In-Reply-To: <20110517172239.23843.qmail@stuge.se>
References: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>
	<4DD24F97.2020606@jenbo.dk>
	<BANLkTik2O7Kyu1rwzUvp4BwHWCo0zqqqLA@mail.gmail.com>
	<20110517172239.23843.qmail@stuge.se>
Message-ID: <BANLkTim=P0p121h_xdzWEtBGKim8Rq-qWg@mail.gmail.com>

I see, thank you very much.

2011/5/17 Peter Stuge <peter at stuge.se>

> Vikram Narayanan wrote:
> > > It took me less then 8 hours to make my first port, and I'm not even a
> C
> > > programmer, mine was a best case senario as there was a sibling board
> > > already ported. I have also ported some where just the component where
> > > supported, that didn't take to long either, probably 7-10 hours.
> > >
> > > Working on a board where only legacy code and docs are available I have
> > > probably spend around 12 hours to get to ram init.
> > >
> > > I think the key to sussess is to have an easy way to reflash the bios
> when
> > > your image failes.
> >
> > Seems quite inspirational to the people who wanted to port for new
> > boards.
> > @ Stefan: Can you please share your opinions on this?
>
> The time required of course depends on many factors. In general
> terms, these are:
>
> 1. Ability to understand or learn C and programming languages in
>   general, and hardware structure.
> 2. Hardware differences.
> 3. How much similar code there already exists in coreboot.
> 4. How readable the code is that does exist in coreboot and is
>   relevant for the project.
>
> In concrete terms, they are:
>
> 1. Programming and electronics experience, and abstract thinking
> 2. How similar your mainboard is to another already supported
>   mainboard.
> 3. If *any* similar mainboard is already supported by coreboot.
>   By similar I mean exact same relevant components; cpu north south
>   superio.
> 4. Quality of coreboot code for cpu north south superio.
>
> These are just the factors to consider *when all components are
> supported already*. In ideal circumstances a board port needs to take
> only one hour. In reality, circumstances are never ideal and the time
> needed per board grows exponentially or even steeper still with the
> number of less than ideal points to consider.
>
> Worst case is so far 8-12 man-months for a coreboot expert.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From anders at jenbo.dk  Tue May 17 21:07:24 2011
From: anders at jenbo.dk (Anders Jenbo)
Date: Tue, 17 May 2011 21:07:24 +0200
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <D8BACDD7E3ED47319A4A2DAD5565DC65@asusp67>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de><20110515234252.18124.qmail@stuge.se><65E8F18FA6CB4888B4AC4915F3845230@asusp67>
	<BANLkTinedjeuNxqvSkeNztH63Z-hQbxY7g@mail.gmail.com>
	<D8BACDD7E3ED47319A4A2DAD5565DC65@asusp67>
Message-ID: <4DD2C76C.1050404@jenbo.dk>

Den 17-05-2011 18:17, Scott Duplichan skrev:
> Idwer Vollering wtote:
>
>
> ]Have you though of using an USB flash drive, to install Windows from?
> ]http://www.windowsvalley.com/install-windows-2000-xp-2003-using-usb-]storag
> e-device-pen-drive/
>
> Hello Idwer,
>
> Thanks for the suggestion and information. That could be useful in
> situations where no CD drive is available. I think it does not directly
> solve the AHCI driver problem though. The Windows XP F6 driver mechanism
> seems to be completely hard-coded for floppy drive only (tradition or USB).
> For example, BIOS can make a USB flash drive appear as floppy drive A: to
> DOS. The Windows XP F6 method is happy with this for the early access
> where BIOS calls are used to read drive A:. But later in the setup process,
> execution switches to native mode drivers for floppy access, at which time
> only a real floppy or a limited number of models of USB floppy will work.
> Somehow an AHCI driver has to get loaded in order for Windows XP setup to
> find the hard disk. Probably nliteos could be used in combination with
> the tool you mention though.
>
> Thanks,
> Scott
You could use http://driverpacks.net/ to incorporate the AHCI driveres 
on your cd.



From peter at stuge.se  Wed May 18 03:40:36 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 18 May 2011 03:40:36 +0200
Subject: [coreboot] How long will take to add coreboot support for
	my	motherboard? Please, expert roughly estimation needed.
In-Reply-To: <BANLkTikzAE7aiy4Mmgk5C8+u6N8bqgzzBA@mail.gmail.com>
References: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>
	<4DD24F97.2020606@jenbo.dk>
	<BANLkTik2O7Kyu1rwzUvp4BwHWCo0zqqqLA@mail.gmail.com>
	<20110517172239.23843.qmail@stuge.se>
	<BANLkTikzAE7aiy4Mmgk5C8+u6N8bqgzzBA@mail.gmail.com>
Message-ID: <20110518014036.31531.qmail@stuge.se>

Vikram Narayanan wrote:
> Thank you. I think this can also be in Developer wiki. This might
> give an insight of how much work is involved.
> (or is it already there in the wiki?)

Dunno..? Isn't it mostly common sense? (That development can be fast
or slow, and depends on how much can be reused.) I'm not saying I am
opposed to it being in the wiki, but it's also easy to spam the FAQ..


//Peter



From vikram186 at gmail.com  Wed May 18 03:48:05 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Wed, 18 May 2011 07:18:05 +0530
Subject: [coreboot] How long will take to add coreboot support for my
 motherboard? Please, expert roughly estimation needed.
In-Reply-To: <20110518014036.31531.qmail@stuge.se>
References: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>
	<4DD24F97.2020606@jenbo.dk>
	<BANLkTik2O7Kyu1rwzUvp4BwHWCo0zqqqLA@mail.gmail.com>
	<20110517172239.23843.qmail@stuge.se>
	<BANLkTikzAE7aiy4Mmgk5C8+u6N8bqgzzBA@mail.gmail.com>
	<20110518014036.31531.qmail@stuge.se>
Message-ID: <BANLkTinDvvQCo-3csmSddv7Gu2SsjYiE5w@mail.gmail.com>

On Wed, May 18, 2011 at 7:10 AM, Peter Stuge <peter at stuge.se> wrote:
> Vikram Narayanan wrote:
>> Thank you. I think this can also be in Developer wiki. This might
>> give an insight of how much work is involved.
>> (or is it already there in the wiki?)
>
> Dunno..? Isn't it mostly common sense? (That development can be fast
> or slow, and depends on how much can be reused.) I'm not saying I am
> opposed to it being in the wiki, but it's also easy to spam the FAQ..
I agree with you. But for people who are new to the porting, this may
be helpful. I don't know how many of the newbies to coreboot are aware
of the fact that many things can be reused, and sometimes porting is
very easy.
Just a thought (to include this in wiki).

-
Thanks,
Vikram



From vikram186 at gmail.com  Wed May 18 03:38:02 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Wed, 18 May 2011 07:08:02 +0530
Subject: [coreboot] How long will take to add coreboot support for my
 motherboard? Please, expert roughly estimation needed.
In-Reply-To: <20110517172239.23843.qmail@stuge.se>
References: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>
	<4DD24F97.2020606@jenbo.dk>
	<BANLkTik2O7Kyu1rwzUvp4BwHWCo0zqqqLA@mail.gmail.com>
	<20110517172239.23843.qmail@stuge.se>
Message-ID: <BANLkTikzAE7aiy4Mmgk5C8+u6N8bqgzzBA@mail.gmail.com>

On Tue, May 17, 2011 at 10:52 PM, Peter Stuge <peter at stuge.se> wrote:
> Vikram Narayanan wrote:
>> > It took me less then 8 hours to make my first port, and I'm not even a C
>> > programmer, mine was a best case senario as there was a sibling board
>> > already ported. I have also ported some where just the component where
>> > supported, that didn't take to long either, probably 7-10 hours.
>> >
>> > Working on a board where only legacy code and docs are available I have
>> > probably spend around 12 hours to get to ram init.
>> >
>> > I think the key to sussess is to have an easy way to reflash the bios when
>> > your image failes.
>>
>> Seems quite inspirational to the people who wanted to port for new
>> boards.
>> @ Stefan: Can you please share your opinions on this?
>
> The time required of course depends on many factors. In general
> terms, these are:
>
> 1. Ability to understand or learn C and programming languages in
> ? general, and hardware structure.
> 2. Hardware differences.
> 3. How much similar code there already exists in coreboot.
> 4. How readable the code is that does exist in coreboot and is
> ? relevant for the project.
>
> In concrete terms, they are:
>
> 1. Programming and electronics experience, and abstract thinking
> 2. How similar your mainboard is to another already supported
> ? mainboard.
> 3. If *any* similar mainboard is already supported by coreboot.
> ? By similar I mean exact same relevant components; cpu north south
> ? superio.
> 4. Quality of coreboot code for cpu north south superio.
>
> These are just the factors to consider *when all components are
> supported already*. In ideal circumstances a board port needs to take
> only one hour. In reality, circumstances are never ideal and the time
> needed per board grows exponentially or even steeper still with the
> number of less than ideal points to consider.
>
> Worst case is so far 8-12 man-months for a coreboot expert.
Thank you. I think this can also be in Developer wiki. This might give
an insight of how much work is involved.
(or is it already there in the wiki?)

-
Thanks,
Vikram



From scott at notabs.org  Wed May 18 07:48:31 2011
From: scott at notabs.org (Scott Duplichan)
Date: Wed, 18 May 2011 00:48:31 -0500
Subject: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
In-Reply-To: <4DD2C76C.1050404@jenbo.dk>
References: <E1QLj0q-0008Rq-MJ@ra.coresystems.de><20110515234252.18124.qmail@stuge.se><65E8F18FA6CB4888B4AC4915F3845230@asusp67><BANLkTinedjeuNxqvSkeNztH63Z-hQbxY7g@mail.gmail.com><D8BACDD7E3ED47319A4A2DAD5565DC65@asusp67>
	<4DD2C76C.1050404@jenbo.dk>
Message-ID: <C5BB8B6D2558476B992F0423D71387E8@asusp67>

Anders Jenbo wrote:

]You could use http://driverpacks.net/ to incorporate the AHCI driveres 
]on your cd.

Hello Anders,

Thanks for the suggestion. I did find that site the other day. At first
it looked like what I needed. But when I went to choose a download, I
I could find x64 packs only for Vista/7. I use the x64 edition of XP
or Server 2003.

Thanks,
Scott





From scott at notabs.org  Wed May 18 08:40:08 2011
From: scott at notabs.org (Scott Duplichan)
Date: Wed, 18 May 2011 01:40:08 -0500
Subject: [coreboot] [PATCH] workaround for "An unexpected error (805262864)
	occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c"
Message-ID: <EA29AB5623234450BF6A861986753B34@asusp67>

The attached patch works around a Windows XP or Server 2003 setup
failure where an error message such as:
"An unexpected error (805262864) occurred at line 1768 of
d:\xpclient\base\boot\setup\arcdisp.c"
The value 805262864 varies, and is the physical address, in decimal,
of one of the ACPI tables.

Tested on Persimmon. Others abuild tested only.
Signed-off-by: Scott Duplichan <scott at notabs.org>

Detailed explanation: The error message is displayed when a 1024 dword
page table array used by setupldr runs out of space. This table is used
for mapping various physical addresses, such as those of ACPI tables
(a separate table identity maps the lower 16MB used by setupldr code
and data). Setupldr only looks at ACPI tables (FACP) to determine make
and model of the system. The make and model of the system is needed when
setupldr scans the good/bad bios lists contained in txtsetup.sif. The
good/bad bios lists are used to bypass installation of the ACPI enabled
kernel on certain systems known to have ACPI problems. The code loop
that scans the lists creates a new mapping each time it reads an ACPI
table, and never frees mappings. The code uses FACP OEM ID to determine
the system model. The code sequentially reads tables listed in the RSDT
array until the FACP is found. Each read consumes one page table entry.
If more that 4 tables precede the FACP in the RSDT array, the 1024
entry page table array will run out of space before the good/bad bios
list processing completes. BIOS can work around this Windows XP/Server
2003 limitation by placing the FACP early in the RSDT array.

Thanks,
Scott



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From stefan.tauner at student.tuwien.ac.at  Wed May 18 15:25:43 2011
From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner)
Date: Wed, 18 May 2011 15:25:43 +0200
Subject: [coreboot] [RFC] usb flashing protocol (was: cheapish and free usb
 spi flashing device)
In-Reply-To: <20110507145904.7599.qmail@stuge.se>
References: <201104220134.p3M1Y7sP015027@mail2.student.tuwien.ac.at>
	<20110422030832.21364.qmail@stuge.se>
	<201104272042.p3RKgaCQ021700@mail2.student.tuwien.ac.at>
	<20110507145904.7599.qmail@stuge.se>
Message-ID: <201105181325.p4IDPMmo009990@mail2.student.tuwien.ac.at>

hey!

peter and i have started to discuss and lay out the details of a native
usb flashing protocol. the WIP document can be found at
http://titanpad.com/x8M9ZvNeMN

we need to design abstract representations of a few things like erase
blocks, instruction sequences for various operations etc. some of which
are (probably) already implemented in flashrom in one form or another
while others might be useful to have in there and have been discussed
or at least thought through already by someone. so feel free to
contribute please. ;)

-- 
Kind regards/Mit freundlichen Gr??en, Stefan Tauner



From stefan.reinauer at coreboot.org  Wed May 18 17:13:20 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 18 May 2011 08:13:20 -0700
Subject: [coreboot] Fwd: Is there anything I can do to make coreboot better?
Message-ID: <4DD3E210.2010700@coreboot.org>

this accidently went to the coreboot-announce list, resending.

-------- Original Message --------
Subject: 	Is there anything I can do to make coreboot better?
Date: 	Wed, 18 May 2011 14:31:53 +0000
From: 	shawn Bai <programassem at hotmail.com>
To: 	<coreboot-announce at coresystems.de>



Hello, guys,

I am very pleased to have the chance to talk with you.
I hope I do not bother you.
My name is Shawn Bai, and you can call me Shawn, it's OK.

I am very interested both in the low-level in embedded system, and in
BIOS level in desktop computer or server.
I get to know this open source project while I browse the internet.

I think it's a very good project to help me understand what happens
within the system, even more.

Is there anything I can do to make coreboot better?
I have some work experience in embedded system low-level development,
mainly in Board support package.

Hope to hear from you soon.


Best Regards,

Shawn Bai



From stefan.reinauer at coreboot.org  Wed May 18 22:38:27 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 18 May 2011 22:38:27 +0200
Subject: [coreboot] How long will take to add coreboot support for my
 motherboard? Please, expert roughly estimation needed.
In-Reply-To: <BANLkTik2O7Kyu1rwzUvp4BwHWCo0zqqqLA@mail.gmail.com>
References: <BANLkTinh+A2H3V-OU8WdhqbZYsD3tXcC-w@mail.gmail.com>
	<4DD24F97.2020606@jenbo.dk>
	<BANLkTik2O7Kyu1rwzUvp4BwHWCo0zqqqLA@mail.gmail.com>
Message-ID: <20110518203827.GA21525@coreboot.org>

* Vikram Narayanan <vikram186 at gmail.com> [110517 16:50]:
> On Tue, May 17, 2011 at 4:06 PM, Anders Jenbo <anders at jenbo.dk> wrote:
> > Den 17-05-2011 10:41, ?????? ????? skrev:
> >
> > Hello everybody,
> >
> > I'm thinking about porting coreboot to my motherboard (epox 9NPA3I / 9NPA3J
> > / 9NPAJ-3 / 9NPA3 Ultra Series). My chipset (CK804) and my superio
> > (F71872F/FG) are in supported list. According to this page
> > (http://www.coreboot.org/Support) port "might be easy" (exactly: "If you
> > find those in our list of Supported Chipsets and Devices a port might be
> > easy").
> >
> > I need roughly estimation for "easy" to decide is it possible for me to port
> > coreboot or not (in time-consuming terms). So, is "easy" up to 8 hours for
> > coreboot expert, or is it up to 40 hours for coreboot expert? Will be great
> > if you could give me estimation for 'worst' and 'best' variant.
> >
> > Thank you very much,
> > Andrey
> >
> > It took me less then 8 hours to make my first port, and I'm not even a C
> > programmer, mine was a best case senario as there was a sibling board
> > already ported. I have also ported some where just the component where
> > supported, that didn't take to long either, probably 7-10 hours.
> >
> > Working on a board where only legacy code and docs are available I have
> > probably spend around 12 hours to get to ram init.
> >
> > I think the key to sussess is to have an easy way to reflash the bios when
> > your image failes.
> Seems quite inspirational to the people who wanted to port for new boards.
> @ Stefan: Can you please share your opinions on this?

Those values vary widely on the quality of the port, the number of
features and the amount of testing you put into this. Getting an OS
booted on a new mainboard can be a thing of 15 minutes, if you are
lucky and just copy an existing mainboard and maybe change the SuperI/O. 

However, doing a port to a new board is usually a lot more than that.

There are many board ports in coreboots tree these days, and frankly,
not all of them are production level quality and/or tested on a large
number of different configurations. Something you whip up in a dat most
certainly is not. It might still be a great port and do everything the
author wanted it to do.

Stefan




From marcj303 at gmail.com  Wed May 18 23:29:06 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 18 May 2011 15:29:06 -0600
Subject: [coreboot] [PATCH] workaround for "An unexpected error
 (805262864) occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c"
In-Reply-To: <EA29AB5623234450BF6A861986753B34@asusp67>
References: <AcwVJm4X1CRQ0Nm8S4KXHsxC7KS5Fw==>
	<EA29AB5623234450BF6A861986753B34@asusp67>
Message-ID: <BANLkTikpN+n89xg4LRhs4QgMuwiVtGqzFw@mail.gmail.com>

On Wed, May 18, 2011 at 12:40 AM, Scott Duplichan <scott at notabs.org> wrote:
> The attached patch works around a Windows XP or Server 2003 setup
> failure where an error message such as:
> "An unexpected error (805262864) occurred at line 1768 of
> d:\xpclient\base\boot\setup\arcdisp.c"
> The value 805262864 varies, and is the physical address, in decimal,
> of one of the ACPI tables.
>
> Tested on Persimmon. Others abuild tested only.
> Signed-off-by: Scott Duplichan <scott at notabs.org>
>
> Detailed explanation: The error message is displayed when a 1024 dword
> page table array used by setupldr runs out of space. This table is used
> for mapping various physical addresses, such as those of ACPI tables
> (a separate table identity maps the lower 16MB used by setupldr code
> and data). Setupldr only looks at ACPI tables (FACP) to determine make
> and model of the system. The make and model of the system is needed when
> setupldr scans the good/bad bios lists contained in txtsetup.sif. The
> good/bad bios lists are used to bypass installation of the ACPI enabled
> kernel on certain systems known to have ACPI problems. The code loop
> that scans the lists creates a new mapping each time it reads an ACPI
> table, and never frees mappings. The code uses FACP OEM ID to determine
> the system model. The code sequentially reads tables listed in the RSDT
> array until the FACP is found. Each read consumes one page table entry.
> If more that 4 tables precede the FACP in the RSDT array, the 1024
> entry page table array will run out of space before the good/bad bios
> list processing completes. BIOS can work around this Windows XP/Server
> 2003 limitation by placing the FACP early in the RSDT array.
>
> Thanks,
> Scott

Hi Scott,

Good find. This must have been a difficult debug.

It looks like src/mainboard/amd/mahogany/acpi_tables.c has a double
paste issue. Fix that and it looks good.

Acked-by: Marc Jones <marcj303 at gmail.com>


Marc

-- 
http://se-eng.com



From paulepanter at users.sourceforge.net  Thu May 19 00:14:49 2011
Fr