[coreboot] [PATCH] Add option 'compress ramstage'
Stefan Reinauer
stefan.reinauer at coreboot.org
Tue May 3 01:04:15 CEST 2011
* Stefan Reinauer <stefan.reinauer at coreboot.org> [110502 20:34]:
> * Sven Schnelle <svens at stackframe.org> [110502 16:13]:
> > Add an option to make compression of ramstage configurable. Right now
> > it is always compressed. On my Thinkpad, the complete boot to grub takes
> > 4s, with around 1s required for decompressing ramstage. This is probably
> > caused by the fact the decompression does a lot of single byte/word/qword
> > accesses, which are really slow on SPI buses. So give the user the option
> > to store ramstage uncompressed, if he has enough memory.
>
> Hi Sven,
>
> can you try whether your thinkpad can boot faster if you enable spi
> prefetching in src/southbridge/intel/i82801gx/bootblock.c
>
> i.e.
>
> static void enable_spi_prefetch(void)
> {
> u8 reg8;
> device_t dev;
>
> dev = PCI_DEV(0, 0x1f, 0);
>
> reg8 = pci_read_config8(dev, 0xdc);
> reg8 &= ~(3 << 2);
> reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
> pci_write_config8(dev, 0xdc, reg8);
> }
>
> static void bootblock_southbridge_init(void)
> {
> ...
> enable_spi_prefetch();
> ...
> }
And in addition you need to set up MTRRs correctly by doing something
like this: (sorry, wrong CPU type but the code should be fairly similar)
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
--- src/cpu/intel/model_106cx/cache_as_ram.inc
+++ src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -195,13 +195,27 @@ clear_mtrrs:
post_code(0x38)
- /* Enable Write Back and Speculative Reads for the first 1MB. */
+ /* Enable Write Back and Speculative Reads for the first MB
+ * and coreboot_ram.
+ */
movl $MTRRphysBase_MSR(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax
+ movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ /* Enable Caching and speculative Reads for the
+ * complete ROM now that we actually have RAM.
+ */
+ movl $MTRRphysBase_MSR(1), %ecx
+ movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+ xorl %edx, %edx
+ wrmsr
+ movl $MTRRphysMask_MSR(1), %ecx
+ movl $(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
xorl %edx, %edx
wrmsr
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