[coreboot] [commit] r6592 - in trunk/src: mainboard/amd/persimmon southbridge/amd/cimx_wrapper/sb800

[repository service]

Author: mjones
Date: Mon May 16 00:07:56 2011
New Revision: 6592
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6592

Log:
Update gpp port configuration.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/persimmon/devicetree.cb
   trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c

Modified: trunk/src/mainboard/amd/persimmon/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/persimmon/devicetree.cb	Mon May 16 00:06:09 2011	(r6591)
+++ trunk/src/mainboard/amd/persimmon/devicetree.cb	Mon May 16 00:07:56 2011	(r6592)
@@ -81,13 +81,13 @@
 							end
                                                 end # f81865f
 					end #LPC
-  					device pci 14.4 on end # PCI 0x4384
-	  				device pci 14.5 on end # USB 2
-					device pci 15.0 on end # PCIe PortA
-					device pci 15.1 on end # PCIe PortB
-					device pci 15.2 on end # PCIe PortC
-					device pci 15.3 on end # PCIe PortD
-					register "gpp_configuration" = "4" #1:1:1:1
+  					device pci 14.4 on  end # PCI 0x4384
+	  				device pci 14.5 on  end # USB 2
+					device pci 15.0 off end # PCIe PortA
+					device pci 15.1 off end # PCIe PortB
+					device pci 15.2 off end # PCIe PortC
+					device pci 15.3 off end # PCIe PortD
+					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx_wrapper/sb800
 #                       end #  device pci 18.0

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c	Mon May 16 00:06:09 2011	(r6591)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c	Mon May 16 00:07:56 2011	(r6592)
@@ -99,10 +99,6 @@
 	sb_config->GppFunctionEnable = GPP_CONTROLLER;
 	sb_config->GppLinkConfig = GPP_CFGMODE;
 	//sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
-	sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED;
-	sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED;
-	sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED;
-	sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED;
 	sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
 	//sb_config->NbSbGen2 = TRUE;
 	//sb_config->GppGen2 = TRUE;

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Mon May 16 00:06:09 2011	(r6591)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Mon May 16 00:07:56 2011	(r6592)
@@ -315,7 +315,6 @@
  */
 static void sb800_enable(device_t dev)
 {
-	u8 gpp_port = 0;
 	struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
 		(struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
 
@@ -414,15 +413,16 @@
 		break;
 
 	case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
+       sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
+       return;
 	case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
+       sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
+       return;
 	case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
+       sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
+       return;
 	case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
-		gpp_port = (dev->path.pci.devfn) & 0x03;
-		if (dev->enabled) {
-			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
-		} else {
-			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
-		}
+       sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
 
 		/*
 		 * GPP_CFGMODE_X4000: PortA Lanes[3:0]