From gerrit at coreboot.org Tue Nov 1 08:48:26 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 1 Nov 2011 08:48:26 +0100 Subject: [coreboot] New patch to review for coreboot: 2c703c1 libpayload: Fix OHCI some more References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/365 -gerrit commit 2c703c13954fcef101135ffd7113889f4c22e3ca Author: Patrick Georgi Date: Thu Oct 27 13:08:13 2011 +0200 libpayload: Fix OHCI some more OHCI works when USB_DEBUG is disabled, but not, when disabled. This is because the controller requires some more time after a schedule has finished. Also improve compliance with the OHCI spec. Change-Id: I4685cc485ff9c52b489fbaa352ab889671cff876 Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/usb/ohci.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 290f782..ef33bd9 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -27,7 +27,7 @@ * SUCH DAMAGE. */ -#define USB_DEBUG +//#define USB_DEBUG #include #include @@ -141,9 +141,6 @@ ohci_init (pcidev_t addr) OHCI_INST (controller)->opreg->HcHCCA = virt_to_phys(OHCI_INST (controller)->hcca); OHCI_INST (controller)->opreg->HcControl &= ~IsochronousEnable; // unused by this driver - OHCI_INST (controller)->opreg->HcControl |= BulkListEnable; // always enabled. OHCI still sleeps on BulkListFilled - OHCI_INST (controller)->opreg->HcControl |= ControlListEnable; // dito - OHCI_INST (controller)->opreg->HcControl |= PeriodicListEnable; // FIXME: setup interrupt data structures and enable all the time // disable everything, contrary to what OHCI spec says in 5.1.1.4, as we don't need IRQs OHCI_INST (controller)->opreg->HcInterruptEnable = 1<<31; OHCI_INST (controller)->opreg->HcInterruptDisable = ~(1<<31); @@ -191,9 +188,9 @@ dump_td(td_t *cur, int level) #ifdef USB_DEBUG static const char *spaces=" "; const char *spc=spaces+(10-level); -#endif debug("%std at %x (%s), condition code: %s\n", spc, cur, direction[cur->direction], completion_codes[cur->condition_code & 0xf]); debug("%s toggle: %x\n", spc, cur->toggle); +#endif } static int @@ -215,6 +212,7 @@ wait_for_ed(usbdev_t *dev, ed_t *head) ((td_t*)phys_to_virt(head->head_pointer & ~3))->condition_code); mdelay(1); } + mdelay(5); if (OHCI_INST(dev->controller)->opreg->HcInterruptStatus & WritebackDoneHead) { debug("done queue:\n"); debug("%x, %x\n", OHCI_INST(dev->controller)->hcca->HccaDoneHead, phys_to_virt(OHCI_INST(dev->controller)->hcca->HccaDoneHead)); @@ -223,7 +221,6 @@ wait_for_ed(usbdev_t *dev, ed_t *head) } td_t *done_queue = NULL; td_t *done_head = (td_t*)phys_to_virt(OHCI_INST(dev->controller)->hcca->HccaDoneHead); - OHCI_INST(dev->controller)->opreg->HcInterruptStatus = WritebackDoneHead; while (1) { td_t *oldnext = (td_t*)phys_to_virt(done_head->next_td); if (oldnext == done_queue) break; /* last element refers to second to last, ie. endless loop */ @@ -236,6 +233,7 @@ wait_for_ed(usbdev_t *dev, ed_t *head) for (cur = done_queue; cur != 0; cur = (td_t*)cur->next_td) { dump_td(cur, 1); } + OHCI_INST(dev->controller)->opreg->HcInterruptStatus &= ~WritebackDoneHead; } if (head->head_pointer & 1) { @@ -340,9 +338,11 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen /* activate schedule */ OHCI_INST(dev->controller)->opreg->HcControlHeadED = virt_to_phys(head); + OHCI_INST(dev->controller)->opreg->HcControl |= ControlListEnable; OHCI_INST(dev->controller)->opreg->HcCommandStatus = ControlListFilled; int failure = wait_for_ed(dev, head); + OHCI_INST(dev->controller)->opreg->HcControl &= ~ControlListEnable; /* free memory */ free((void*)tds); @@ -430,9 +430,11 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize) /* activate schedule */ OHCI_INST(ep->dev->controller)->opreg->HcBulkHeadED = virt_to_phys(head); + OHCI_INST(ep->dev->controller)->opreg->HcControl |= BulkListEnable; OHCI_INST(ep->dev->controller)->opreg->HcCommandStatus = BulkListFilled; int failure = wait_for_ed(ep->dev, head); + OHCI_INST(ep->dev->controller)->opreg->HcControl &= ~BulkListEnable; ep->toggle = head->toggle; From svn at coreboot.org Tue Nov 1 10:00:43 2011 From: svn at coreboot.org (coreboot) Date: Tue, 01 Nov 2011 09:00:43 -0000 Subject: [coreboot] #162: Move SYSTEM_TYPE to Kconfig In-Reply-To: <043.597d39f9c64761f08194d46ef312edec@coreboot.org> References: <043.597d39f9c64761f08194d46ef312edec@coreboot.org> Message-ID: <058.b2b85bb37327387834966c9649d74684@coreboot.org> #162: Move SYSTEM_TYPE to Kconfig ----------------------------------+------------------------ Reporter: oxygene | Owner: oxygene Type: enhancement | Status: new Priority: minor | Milestone: Component: coreboot | Resolution: Keywords: | Dependencies: Patch Status: there is no patch | ----------------------------------+------------------------ Comment (by christophg+cb@?): AFAIK there are two spots where the system type is given to the OS: in the DMI table (chassis type) and in the ACPI FADT table (Preferred_PM_Profile) I don't know where (or even if) coreboot writes the DMI table, and currently the FADT PM profile is hardcoded in the mainboards' fadt.c. I also think, SYSTEM_TYPE should be moved to Kconfig, be combined with DMI chassis type (if applicable) and also an option for the preferred PM profile should be added (of course defaulting to the SYSTEM_TYPE if not changed by user) IMHO there are various advantages: * users can change the reported system/chassis type dependant on the real usage of the board without meddling with the mainboards C code * the PM profile could be equally changed (hardcoding this for a board type IMO is absurd as it equally depends on the mainboard and the real usage) * it would be easier to maintain consistency between all these settings. Also they now are mostly set with their numerical representation (#define SYSTEM_TYPE 1; fadt->preferred_pm_profile = 1; etc.) which would change with integration in Kconfig -- Ticket URL: coreboot From svn at coreboot.org Tue Nov 1 10:01:44 2011 From: svn at coreboot.org (coreboot) Date: Tue, 01 Nov 2011 09:01:44 -0000 Subject: [coreboot] #178: linux kernel hang while boot from SATA SSD on EPIA CN In-Reply-To: <058.daf9558ffa70e511e5d4f56acf817853@coreboot.org> References: <058.daf9558ffa70e511e5d4f56acf817853@coreboot.org> Message-ID: <073.9247f249f1db08501bcdeb3a4f5bdc15@coreboot.org> #178: linux kernel hang while boot from SATA SSD on EPIA CN ----------------------------------+------------------------- Reporter: ryzhovsergey@? | Owner: stepan@? Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Resolution: Keywords: SATA SSD EPIA CN | Dependencies: Patch Status: there is no patch | ----------------------------------+------------------------- Comment (by ryzhovsergey@?): Is any news here ? -- Ticket URL: coreboot From svn at coreboot.org Tue Nov 1 10:04:28 2011 From: svn at coreboot.org (coreboot) Date: Tue, 01 Nov 2011 09:04:28 -0000 Subject: [coreboot] #5: Add license header to all source files In-Reply-To: <039.246ef13c76c21ab71549ef1d0aaeb503@coreboot.org> References: <039.246ef13c76c21ab71549ef1d0aaeb503@coreboot.org> Message-ID: <054.71ccc73e031699066c41981242a0d470@coreboot.org> #5: Add license header to all source files ----------------------------------+--------------------------------------- Reporter: uwe | Owner: uwe Type: task | Status: new Priority: blocker | Milestone: Resolve license issues Component: coreboot | Resolution: Keywords: | Dependencies: Patch Status: there is no patch | ----------------------------------+--------------------------------------- Comment (by oxygene): One of our lint tests ("make lint") looks for proper license headers. -- Ticket URL: coreboot From svn at coreboot.org Tue Nov 1 10:07:00 2011 From: svn at coreboot.org (coreboot) Date: Tue, 01 Nov 2011 09:07:00 -0000 Subject: [coreboot] #177: Not compiling coreBoot In-Reply-To: <056.6f073e77965858dd8a29aefa6f41f5dc@coreboot.org> References: <056.6f073e77965858dd8a29aefa6f41f5dc@coreboot.org> Message-ID: <071.12e05ddc8b473caf56da062581e96a22@coreboot.org> #177: Not compiling coreBoot ----------------------------------+--------------------------- Reporter: darkshvein@? | Owner: stepan@? Type: defect | Status: closed Priority: major | Milestone: Component: coreboot | Resolution: worksforme Keywords: compile error | Dependencies: Patch Status: there is no patch | ----------------------------------+--------------------------- Changes (by oxygene): * status: new => closed * resolution: => worksforme Comment: We should have fixed all such issues by now. -- Ticket URL: coreboot From svn at coreboot.org Tue Nov 1 11:00:57 2011 From: svn at coreboot.org (coreboot) Date: Tue, 01 Nov 2011 10:00:57 -0000 Subject: [coreboot] #179: Coreboot on GigaByte GA-8IEXP ver. 1.2 In-Reply-To: <054.9b9dacfb5c934b38d077f3638d7b6066@coreboot.org> References: <054.9b9dacfb5c934b38d077f3638d7b6066@coreboot.org> Message-ID: <069.d6424878856036a8061a10151b5052a3@coreboot.org> #179: Coreboot on GigaByte GA-8IEXP ver. 1.2 ----------------------------------+--------------------------------- Reporter: BlackSheep0@? | Owner: stepan@? Type: enhancement | Status: closed Priority: minor | Milestone: Going mainstream Component: coreboot | Resolution: invalid Keywords: | Dependencies: Patch Status: there is no patch | ----------------------------------+--------------------------------- Changes (by oxygene): * status: new => closed * resolution: => invalid Comment: First, "do that for me" won't work without access to the hardware. Second, "do that for me" is quite a request when porting to a board can take an experienced developer up to 6 months (or more, if the developer faces extraordinary problems) Third, Dual BIOS usually don't help because we completely strip the recovery routines (though Gigabyte might have some hardware circuit using a watchdog, or something) Due to all this, closed as invalid. -- Ticket URL: coreboot From svn at coreboot.org Tue Nov 1 11:12:07 2011 From: svn at coreboot.org (coreboot) Date: Tue, 01 Nov 2011 10:12:07 -0000 Subject: [coreboot] #169: ASUS P4PE-X/SE. In-Reply-To: <045.cf70f2b96472ced4cab49eb429057509@coreboot.org> References: <045.cf70f2b96472ced4cab49eb429057509@coreboot.org> Message-ID: <060.3a1732fcc7426b7ee2288724c9720088@coreboot.org> #169: ASUS P4PE-X/SE. ----------------------------------+-------------------------------- Reporter: anonymous | Owner: stepan@? Type: defect | Status: closed Priority: major | Milestone: Component: coreboot | Resolution: invalid Keywords: ASUS P4PE-X/SE. | Dependencies: ASUS P4PE-X/SE. Patch Status: there is no patch | ----------------------------------+-------------------------------- Changes (by oxygene): * status: new => closed * resolution: => invalid -- Ticket URL: coreboot From svn at coreboot.org Tue Nov 1 11:36:25 2011 From: svn at coreboot.org (coreboot) Date: Tue, 01 Nov 2011 10:36:25 -0000 Subject: [coreboot] #170: Need coreboot for ASUS P4PE_X/SE In-Reply-To: <045.1c8ab5657f6c362b91c8afdbfe40c16f@coreboot.org> References: <045.1c8ab5657f6c362b91c8afdbfe40c16f@coreboot.org> Message-ID: <060.eec72c30c7323a27986f53d5b1a60856@coreboot.org> #170: Need coreboot for ASUS P4PE_X/SE ---------------------------------------+------------------------- Reporter: aav@? | Owner: stepan@? Type: defect | Status: closed Priority: major | Milestone: Component: coreboot | Resolution: invalid Keywords: corebootASUS P4PE_X/SE | Dependencies: Patch Status: there is no patch | ---------------------------------------+------------------------- Changes (by oxygene): * status: new => closed * resolution: => invalid Comment: Don't dump board support requests on us. Boards are done when people step up to implement support for them. -- Ticket URL: coreboot From kyosti.malkki at gmail.com Tue Nov 1 14:02:30 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Tue, 01 Nov 2011 15:02:30 +0200 Subject: [coreboot] Trouble with cbfstool when attempting dualboot In-Reply-To: <4EAEAEAD.8000004@georgi-clan.de> References: <1319779116.14926.32.camel@obelix> <4EAB1705.8040605@georgi-clan.de> <1320042770.14926.77.camel@obelix> <4EAEAEAD.8000004@georgi-clan.de> Message-ID: <1320152550.14926.1164.camel@obelix> On Mon, 2011-10-31 at 15:20 +0100, Patrick Georgi wrote: > Am Montag, 31. Oktober 2011 07:32:50 schrieb Ky?sti M?lkki: > > If my new normal/romstage is built with GCC for Cache-As-Ram, the same > > alignment does not apply and on boot it halts before any serial output. > Does it "halt" or is it just _very_ slow (several minutes until the > first life sign on serial)? The latter would indicate wrong MTRR setup, > while the former is a more fundamental problem. > It isn't only slow. I did experience the slow version with bad MTRR setup when I did the big->tiny bootblock switch and MTRR setup missed one ~. My Cache-As-Ram boot enters intel/car/cache_as_ram.inc but never reaches LogicalAP_SIPINotdone in it. I found a note in this file saying LAPIC ID logic works only for processors with two threads, so does a dual Xeon P4/HT setup require re-writing this logic? The car.inc was earlier used for Tyan s2735 that is also dual-Xeon board with same socket. I happen to have normal/romstage that does not cross CONFIG_XIP_ROM_SIZE boundary. I think it is a bug in cbfstool that normal/romstage placement is unaligned, since early_mtrr_init does not cover cases where normal/romstage crosses said boundary. One would witness the very slow boot effect then, too. Updated image with normal/romstage compiled with ROMCC: coreboot.rom: 512 kB, bootblocksize 978, romsize 524288, offset 0x0 Alignment: 64 bytes Name Offset Type Size fallback/romstage 0x0 stage 43801 fallback/coreboot_ram 0xab80 stage 163868 fallback/payload 0x32c00 payload 33141 (empty) 0x3adc0 null 20888 normal/romstage 0x3ff80 stage 43789 normal/coreboot_ram 0x4ab00 stage 163868 normal/payload 0x72b80 payload 33141 (empty) 0x7ad40 null 20134 Updated image with normal/romstage compiled with GCC: coreboot.rom: 512 kB, bootblocksize 978, romsize 524288, offset 0x0 Alignment: 64 bytes Name Offset Type Size fallback/romstage 0x0 stage 43801 fallback/coreboot_ram 0xab80 stage 163868 fallback/payload 0x32c00 payload 33141 normal/romstage 0x3adc0 stage 15121 normal/coreboot_ram 0x3e900 stage 163868 normal/payload 0x66980 payload 33141 (empty) 0x6eb40 null 69798 KM From patrick at georgi-clan.de Tue Nov 1 18:27:12 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Tue, 01 Nov 2011 18:27:12 +0100 Subject: [coreboot] Trouble with cbfstool when attempting dualboot In-Reply-To: <1320152550.14926.1164.camel@obelix> References: <1319779116.14926.32.camel@obelix> <4EAB1705.8040605@georgi-clan.de> <1320042770.14926.77.camel@obelix> <4EAEAEAD.8000004@georgi-clan.de> <1320152550.14926.1164.camel@obelix> Message-ID: <4EB02BF0.2040202@georgi-clan.de> Am 01.11.2011 14:02, schrieb Ky?sti M?lkki: > My Cache-As-Ram boot enters intel/car/cache_as_ram.inc but never reaches > LogicalAP_SIPINotdone in it. I found a note in this file saying LAPIC ID > logic works only for processors with two threads, so does a dual Xeon > P4/HT setup require re-writing this logic? Possibly. Comparing the code to the datasheets will give you a definitive answer. > I happen to have normal/romstage that does not cross CONFIG_XIP_ROM_SIZE > boundary. I think it is a bug in cbfstool that normal/romstage placement > is unaligned, It is aligned... > since early_mtrr_init does not cover cases where > normal/romstage crosses said boundary. ... which is why this works. Patrick From gerrit at coreboot.org Tue Nov 1 18:41:26 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 1 Nov 2011 18:41:26 +0100 Subject: [coreboot] New patch to review for coreboot: c23f922 Remove XIP_ROM_BASE References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/366 -gerrit commit c23f922f4a25f3f270390eb490934486d3df27f2 Author: Patrick Georgi Date: Mon Oct 31 17:07:52 2011 +0100 Remove XIP_ROM_BASE The base is now calculated automatically, and all mentions of that config option were typical anyway (4GB - XIP_ROM_SIZE). Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40 Signed-off-by: Patrick Georgi --- src/cpu/amd/agesa/family10/Kconfig | 4 ---- src/cpu/amd/agesa/family12/Kconfig | 5 ----- src/cpu/amd/agesa/family14/Kconfig | 5 ----- src/cpu/amd/car/cache_as_ram.inc | 4 ++-- src/cpu/amd/socket_AM2r2/Kconfig | 5 ----- src/cpu/amd/socket_AM3/Kconfig | 5 ----- src/cpu/amd/socket_ASB2/Kconfig | 5 ----- src/cpu/amd/socket_C32/Kconfig | 5 ----- src/cpu/amd/socket_F_1207/Kconfig | 5 ----- src/cpu/intel/car/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_106cx/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_6ex/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_6fx/cache_as_ram.inc | 4 ++-- src/cpu/via/car/cache_as_ram.inc | 2 +- src/cpu/x86/Kconfig | 4 ---- src/include/cpu/x86/mtrr.h | 12 +----------- src/mainboard/supermicro/h8dmr_fam10/README | 5 ----- 17 files changed, 12 insertions(+), 70 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 81070e5..abaa898 100755 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -40,10 +40,6 @@ config CDB hex default 0x18 -config XIP_ROM_BASE - hex - default 0xfff80000 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 5679396..c53ee57 100755 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -57,11 +57,6 @@ config CDB default 0x18 depends on CPU_AMD_AGESA_FAMILY12 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_AGESA_FAMILY12 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 8f3e766..702270c 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -57,11 +57,6 @@ config CDB default 0x18 depends on CPU_AMD_AGESA_FAMILY14 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_AGESA_FAMILY14 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index b9e02f3..955aec9 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -279,7 +279,7 @@ clear_fixed_var_mtrr_out: movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable write base caching so we can do execute in place (XIP) * on the flash ROM. @@ -302,7 +302,7 @@ clear_fixed_var_mtrr_out: wbcache_post_fam10_setup: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig index c7cff14..ae4d458 100644 --- a/src/cpu/amd/socket_AM2r2/Kconfig +++ b/src/cpu/amd/socket_AM2r2/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_AM2R2 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_AM2R2 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig index c718ead..ed656f1 100644 --- a/src/cpu/amd/socket_AM3/Kconfig +++ b/src/cpu/amd/socket_AM3/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_AM3 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_AM3 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig index 964a59f..7784a8d 100644 --- a/src/cpu/amd/socket_ASB2/Kconfig +++ b/src/cpu/amd/socket_ASB2/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_ASB2 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_ASB2 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig index 7ffa374..56324dc 100644 --- a/src/cpu/amd/socket_C32/Kconfig +++ b/src/cpu/amd/socket_C32/Kconfig @@ -30,11 +30,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_C32 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_C32 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig index 224059a..df98566 100644 --- a/src/cpu/amd/socket_F_1207/Kconfig +++ b/src/cpu/amd/socket_F_1207/Kconfig @@ -29,11 +29,6 @@ config CDB default 0x18 depends on CPU_AMD_SOCKET_F_1207 -config XIP_ROM_BASE - hex - default 0xfff80000 - depends on CPU_AMD_SOCKET_F_1207 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 26fec6e..7742a68 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -229,7 +229,7 @@ clear_fixed_var_mtrr_out: simplemask CacheSize, 0 wrmsr -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* * Enable write base caching so we can do execute in place (XIP) @@ -250,7 +250,7 @@ clear_fixed_var_mtrr_out: movl $0x0000000f, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Enable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 9f7ceaf..eb3d650 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -98,7 +98,7 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx @@ -115,7 +115,7 @@ clear_mtrrs: xorl %edx, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Enable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 3a12cf6..18ada29 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -98,7 +98,7 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx @@ -115,7 +115,7 @@ clear_mtrrs: movl $0x0000000f, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Enable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 2ba1872..dfc4f3b 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -105,7 +105,7 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx @@ -122,7 +122,7 @@ clear_mtrrs: movl $0x0000000f, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Enable cache. */ movl %cr0, %eax diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index ad2805e..aad2369 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -240,7 +240,7 @@ testok: movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax wrmsr - /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ + /* Cache XIP_ROM area to speedup coreboot code. */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx /* diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index eed7d8f..348f0ef 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -27,10 +27,6 @@ config TSC_CALIBRATE_WITH_IO bool default n -config XIP_ROM_BASE - hex - default 0xffff0000 - config XIP_ROM_SIZE hex default 0x10000 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index dc238e7..c3b3e22 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -45,23 +45,13 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res); void x86_setup_fixed_mtrrs(void); #endif -/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */ -#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE) -# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE" -#endif -#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) -# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE" -#endif #if !defined(CONFIG_RAMTOP) # error "CONFIG_RAMTOP not defined" #endif -#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) +#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) # error "CONFIG_XIP_ROM_SIZE is not a power of 2" #endif -#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0) -# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" -#endif #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README index 040c244..485e7c8 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/README +++ b/src/mainboard/supermicro/h8dmr_fam10/README @@ -21,8 +21,3 @@ See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/ Ward, 2009-09-22 -mansoor at iwavesystems.com said, about the last issue: - - Try enabling CONFIG_XIP_ROM_BASE. It solved the same problem for me in my board. - -So, that's a todo. From gerrit at coreboot.org Tue Nov 1 19:06:24 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 1 Nov 2011 19:06:24 +0100 Subject: [coreboot] Patch merged into coreboot/master: c23f922 Remove XIP_ROM_BASE References: Message-ID: the following patch was just integrated into master: commit c23f922f4a25f3f270390eb490934486d3df27f2 Author: Patrick Georgi Date: Mon Oct 31 17:07:52 2011 +0100 Remove XIP_ROM_BASE The base is now calculated automatically, and all mentions of that config option were typical anyway (4GB - XIP_ROM_SIZE). Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Tue Nov 1 18:52:20 2011, giving +1 Reviewed-By: Stefan Reinauer at Tue Nov 1 19:06:22 2011, giving +2 See http://review.coreboot.org/366 for details. -gerrit From gerrit at coreboot.org Tue Nov 1 19:07:48 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 1 Nov 2011 19:07:48 +0100 Subject: [coreboot] Patch merged into coreboot/master: f3958db remove trailing whitespace References: Message-ID: the following patch was just integrated into master: commit f3958db817a9b896da4a2ec2a4717d27b50946f9 Author: Stefan Reinauer Date: Mon Oct 31 12:56:45 2011 -0700 remove trailing whitespace Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer Reviewed-By: Patrick Georgi at Tue Nov 1 19:07:26 2011, giving +2 See http://review.coreboot.org/364 for details. -gerrit From gerrit at coreboot.org Tue Nov 1 19:07:49 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 1 Nov 2011 19:07:49 +0100 Subject: [coreboot] Patch merged into coreboot/master: 2c703c1 libpayload: Fix OHCI some more References: Message-ID: the following patch was just integrated into master: commit 2c703c13954fcef101135ffd7113889f4c22e3ca Author: Patrick Georgi Date: Thu Oct 27 13:08:13 2011 +0200 libpayload: Fix OHCI some more OHCI works when USB_DEBUG is disabled, but not, when disabled. This is because the controller requires some more time after a schedule has finished. Also improve compliance with the OHCI spec. Change-Id: I4685cc485ff9c52b489fbaa352ab889671cff876 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Tue Nov 1 09:00:32 2011, giving +1 Reviewed-By: Stefan Reinauer at Tue Nov 1 19:07:39 2011, giving +2 See http://review.coreboot.org/365 for details. -gerrit From gerrit at coreboot.org Tue Nov 1 19:08:27 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 1 Nov 2011 19:08:27 +0100 Subject: [coreboot] Patch merged into coreboot/master: 2f9da80 libpayload: remove trailing whitespace and run dos2unix References: Message-ID: the following patch was just integrated into master: commit 2f9da8083fec5eb20b9c79d474c16ab3de13e5b7 Author: Stefan Reinauer Date: Mon Oct 31 12:54:00 2011 -0700 libpayload: remove trailing whitespace and run dos2unix Change-Id: Iffed3602456f5306711c65f06c873c58d4086e11 Signed-off-by: Stefan Reinauer Reviewed-By: Patrick Georgi at Tue Nov 1 19:08:10 2011, giving +2 See http://review.coreboot.org/363 for details. -gerrit From patrick at georgi-clan.de Tue Nov 1 20:13:31 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Tue, 01 Nov 2011 20:13:31 +0100 Subject: [coreboot] Patch set updated for coreboot: 7849219 Update coreboot cross toolchain to gcc 4.6.1 In-Reply-To: <1319920444.32412.19.camel@Debian.lan> References: <1319920444.32412.19.camel@Debian.lan> Message-ID: <4EB044DB.3050200@georgi-clan.de> Am 29.10.2011 22:34, schrieb Nils: > CC wasn't set and bison and flex were not instaled. > > The acpica-unix-20110922/README states that the Makefiles contain > CC = gcc but only the main acpica-unix-20110922/generate/ > unix/Makefile.config contains it and it is not used by coreboot. We better pass CC in from the outside - I want to add ccache support to buildgcc. Also the bison/flex tests: I regularily have the build fail on m4 and gawk (iirc), too. Maybe all these should be tested for in the buildgcc script instead. Patrick From wmkamp at datakamp.de Tue Nov 1 20:06:28 2011 From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp) Date: Tue, 1 Nov 2011 20:06:28 +0100 Subject: [coreboot] AGESA Port Message-ID: <4738C8CE0A30FF47AACA9C624746E3E208BA27C48B@DATAKAMPONE.datakamp2008.local> Hello, I have a question. The current AMD AGESA code in the coreboot project is a relatively old one. Things like LVDS output for F14 Ontario are not supported. Actually there is a new version from October release OntarioPI 1.1.9.0. Can anyone tell me who did the porting of AGESA to the coreboot project? Thanks Wolfgang -------------- next part -------------- An HTML attachment was scrubbed... URL: From lists at e4L.es Tue Nov 1 20:25:43 2011 From: lists at e4L.es (Elisenda Cuadros) Date: Tue, 01 Nov 2011 20:25:43 +0100 Subject: [coreboot] Coreboot and Epia M-II Message-ID: <4EB047B7.5000907@e4L.es> Hello, First of all I am new to the list. Congratulations to all developers for this great work. I have an Epia M-II and I want to install coreboot on it. This board is supported, great news!. I extracted the vga rom with bios_extract (CLE1622A.rom) and I put it inside menuconfig (pci 1106,3122). I built Seabios with Coreboot and attached a bootorder file with cbfstool. When I try boot the board with the resulting rom it seems like it?s in a loop. The VGA output is not good. I am not able to view any payload messages. I am using coreboot v4 from git. Because of it is my first experience with coreboot I don?t have any ideas for what is causing of the problem. I attach you it if you want to take a look. Thanks in advance. Best regards, Elisenda -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot-v4 epia MII log.zip Type: application/octet-stream Size: 155819 bytes Desc: not available URL: From marcj303 at gmail.com Tue Nov 1 20:44:01 2011 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 1 Nov 2011 13:44:01 -0600 Subject: [coreboot] AGESA Port In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E208BA27C48B@DATAKAMPONE.datakamp2008.local> References: <4738C8CE0A30FF47AACA9C624746E3E208BA27C48B@DATAKAMPONE.datakamp2008.local> Message-ID: On Tue, Nov 1, 2011 at 1:06 PM, Wolfgang Kamp - datakamp wrote: > Hello, > > > > I have a question. > > The current AMD AGESA code in the coreboot project is a relatively old one. > Things like LVDS output for F14 Ontario are not supported. Actually there is > a new version from October release OntarioPI 1.1.9.0. > > Can anyone tell me who did the porting of AGESA to the coreboot project? Hi Wolfgang, AMD provides the AGESA drops. Marc -- http://se-eng.com From gerrit at coreboot.org Tue Nov 1 22:42:23 2011 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Tue, 1 Nov 2011 22:42:23 +0100 Subject: [coreboot] New patch to review for coreboot: d1f7cf4 buildgcc: Update coreboot reference toolchain to gcc 4.6.2 References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/367 -gerrit commit d1f7cf4195bf3b1cca86f2b78eb0625411479706 Author: Stefan Reinauer Date: Tue Nov 1 22:39:41 2011 +0100 buildgcc: Update coreboot reference toolchain to gcc 4.6.2 In addition: - drop some unneeded patches - make the scripting support depend on SKIPPYTHON not SKIPGDB so it is possible to build GDB with and without scripting support - rename the repository checkout version of GCC trunk, not X+1 so we don't have to change it on every version upgrade. Change-Id: I1b7d5b8921187c1c1d39b04f20bb715ddba72fe8 Signed-off-by: Stefan Reinauer --- util/crossgcc/buildgcc | 16 +- .../patches/binutils-2.20.1_no-bfd-doc.patch | 11 - util/crossgcc/patches/gcc-4.5.2_pragma.patch | 10 - .../patches/mpfr-3.0.0_allpatches_20101216.patch | 1945 -------------------- 4 files changed, 8 insertions(+), 1974 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index b0918c0..8918191 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -21,7 +21,7 @@ # CROSSGCC_DATE="November 1st, 2011" -CROSSGCC_VERSION="1.06" +CROSSGCC_VERSION="1.07" # default settings TARGETDIR=`pwd`/xgcc @@ -33,7 +33,7 @@ GMP_VERSION=5.0.2 MPFR_VERSION=3.1.0 MPC_VERSION=0.9 LIBELF_VERSION=0.8.13 -GCC_VERSION=4.6.1 +GCC_VERSION=4.6.2 GCC_AUTOCONF_VERSION=2.64 BINUTILS_VERSION=2.21.1 GDB_VERSION=7.3.1 @@ -225,7 +225,7 @@ fi USE_GOLD="" GCC_OPTIONS="--enable-lto" -if [ ${GCC_VERSION} = "4.6.2" ]; then +if [ ${GCC_VERSION} = "trunk" ]; then if [ ! -r tarballs/gcc-core-${GCC_VERSION}.tar.bz2 ]; then printf "Pre-Release GCC ${GCC_VERSION}, checking out subversion trunk\n" mkdir -p tarballs/.tmp @@ -499,8 +499,8 @@ fi if [ -f build-expat/.success ]; then printf "Skipping Expat as it is already built\n" -elif [ $SKIPGDB -eq 1 ]; then - printf "Skipping Expat as requested by command line (skip GDB)\n" +elif [ $SKIPPYTHON -eq 1 ]; then + printf "Skipping Expat (Python scripting not enabled)\n" else printf "Building Expat ${EXPAT_VERSION} ... " ( @@ -521,8 +521,8 @@ fi if [ -f build-python/.success ]; then printf "Skipping Python as it is already built\n" -elif [ $SKIPGDB -eq 1 ]; then - printf "Skipping Python as requested by command line (skip GDB)\n" +elif [ $SKIPPYTHON -eq 1 ]; then + printf "Skipping Python (Python scripting not enabled)\n" else printf "Building Python ${PYTHON_VERSION} ... " ( @@ -544,7 +544,7 @@ fi if [ -f build-gdb/.success ]; then printf "Skipping GDB as it is already built\n" elif [ $SKIPGDB -eq 1 ]; then - printf "Skipping GDB as requested by command line\n" + printf "Skipping GDB (GDB support not enabled)\n" else printf "Building GDB ${GDB_VERSION} ... " ( diff --git a/util/crossgcc/patches/binutils-2.20.1_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.20.1_no-bfd-doc.patch deleted file mode 100644 index a75a402..0000000 --- a/util/crossgcc/patches/binutils-2.20.1_no-bfd-doc.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- binutils-2.20.1/bfd/Makefile.in~ 2010-07-25 10:56:45 +0000 -+++ binutils-2.20.1/bfd/Makefile.in 2010-07-25 10:19:24 +0000 -@@ -320,7 +320,7 @@ - # RELEASE=y - INCDIR = $(srcdir)/../include - CSEARCH = -I. -I$(srcdir) -I$(INCDIR) --SUBDIRS = doc po -+SUBDIRS = po - bfddocdir = doc - libbfd_la_LDFLAGS = $(am__append_1) -release `cat libtool-soversion` \ - @SHARED_LDFLAGS@ $(am__empty) diff --git a/util/crossgcc/patches/gcc-4.5.2_pragma.patch b/util/crossgcc/patches/gcc-4.5.2_pragma.patch deleted file mode 100644 index d36f489..0000000 --- a/util/crossgcc/patches/gcc-4.5.2_pragma.patch +++ /dev/null @@ -1,10 +0,0 @@ -diff -ur gcc-4.5.2.orig/gcc/config/i386/i386elf.h gcc-4.5.1/gcc/config/i386/i386elf.h ---- gcc-4.5.2.orig/gcc/config/i386/i386elf.h 2010-11-17 19:48:16.184401200 -0700 -+++ gcc-4.5.2/gcc/config/i386/i386elf.h 2010-11-17 20:52:54.443969900 -0700 -@@ -123,3 +123,6 @@ - #undef ASM_OUTPUT_ALIGNED_BSS - #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ - asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) -+ -+/* Enable parsing of #pragma pack(push,) and #pragma pack(pop). */ -+#define HANDLE_PRAGMA_PACK_PUSH_POP 1 diff --git a/util/crossgcc/patches/mpfr-3.0.0_allpatches_20101216.patch b/util/crossgcc/patches/mpfr-3.0.0_allpatches_20101216.patch deleted file mode 100644 index 2fdcfdd..0000000 --- a/util/crossgcc/patches/mpfr-3.0.0_allpatches_20101216.patch +++ /dev/null @@ -1,1945 +0,0 @@ -diff -Naurd mpfr-3.0.0.orig/PATCHES mpfr-3.0.0/PATCHES ---- mpfr-3.0.0.orig/PATCHES 2010-06-23 11:02:49.000000000 +0000 -+++ mpfr-3.0.0/PATCHES 2010-06-23 11:03:36.000000000 +0000 -@@ -0,0 +1 @@ -+mpfr_out_str -diff -Naurd mpfr-3.0.0.orig/VERSION mpfr-3.0.0/VERSION ---- mpfr-3.0.0.orig/VERSION 2010-06-10 11:00:14.000000000 +0000 -+++ mpfr-3.0.0/VERSION 2010-06-23 11:03:20.000000000 +0000 -@@ -1 +1 @@ --3.0.0 -+3.0.0-p1 -diff -Naurd mpfr-3.0.0.orig/mpfr.h mpfr-3.0.0/mpfr.h ---- mpfr-3.0.0.orig/mpfr.h 2010-06-10 11:00:14.000000000 +0000 -+++ mpfr-3.0.0/mpfr.h 2010-06-23 11:03:20.000000000 +0000 -@@ -27,7 +27,7 @@ - #define MPFR_VERSION_MAJOR 3 - #define MPFR_VERSION_MINOR 0 - #define MPFR_VERSION_PATCHLEVEL 0 --#define MPFR_VERSION_STRING "3.0.0" -+#define MPFR_VERSION_STRING "3.0.0-p1" - - /* Macros dealing with MPFR VERSION */ - #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c)) -diff -Naurd mpfr-3.0.0.orig/mpfr.texi mpfr-3.0.0/mpfr.texi ---- mpfr-3.0.0.orig/mpfr.texi 2010-06-10 11:00:14.000000000 +0000 -+++ mpfr-3.0.0/mpfr.texi 2010-06-23 11:03:12.000000000 +0000 -@@ -2050,7 +2050,7 @@ - are printed. If @var{base} is greater than 10, @samp{@@} will be used - instead of @samp{e} as exponent delimiter. - --Return the number of bytes written, or if an error occurred, return 0. -+Return the number of characters written, or if an error occurred, return 0. - @end deftypefun - - @deftypefun size_t mpfr_inp_str (mpfr_t @var{rop}, FILE *@var{stream}, int @var{base}, mpfr_rnd_t @var{rnd}) -diff -Naurd mpfr-3.0.0.orig/out_str.c mpfr-3.0.0/out_str.c ---- mpfr-3.0.0.orig/out_str.c 2010-06-10 11:00:14.000000000 +0000 -+++ mpfr-3.0.0/out_str.c 2010-06-23 11:03:12.000000000 +0000 -@@ -22,6 +22,16 @@ - - #include "mpfr-impl.h" - -+/* Warning! S should not contain "%". */ -+#define OUT_STR_RET(S) \ -+ do \ -+ { \ -+ int r; \ -+ r = fprintf (stream, (S)); \ -+ return r < 0 ? 0 : r; \ -+ } \ -+ while (0) -+ - size_t - mpfr_out_str (FILE *stream, int base, size_t n_digits, mpfr_srcptr op, - mpfr_rnd_t rnd_mode) -@@ -29,6 +39,7 @@ - char *s, *s0; - size_t l; - mpfr_exp_t e; -+ int err; - - MPFR_ASSERTN (base >= 2 && base <= 62); - -@@ -36,37 +47,16 @@ - if (stream == NULL) - stream = stdout; - -- if (MPFR_IS_NAN(op)) -- { -- fprintf (stream, "@NaN@"); -- return 3; -- } -- -- if (MPFR_IS_INF(op)) -- { -- if (MPFR_SIGN(op) > 0) -- { -- fprintf (stream, "@Inf@"); -- return 3; -- } -- else -- { -- fprintf (stream, "- at Inf@"); -- return 4; -- } -- } -- -- if (MPFR_IS_ZERO(op)) -+ if (MPFR_UNLIKELY (MPFR_IS_SINGULAR (op))) - { -- if (MPFR_SIGN(op) > 0) -- { -- fprintf(stream, "0"); -- return 1; -- } -+ if (MPFR_IS_NAN (op)) -+ OUT_STR_RET ("@NaN@"); -+ else if (MPFR_IS_INF (op)) -+ OUT_STR_RET (MPFR_IS_POS (op) ? "@Inf@" : "- at Inf@"); - else - { -- fprintf(stream, "-0"); -- return 2; -+ MPFR_ASSERTD (MPFR_IS_ZERO (op)); -+ OUT_STR_RET (MPFR_IS_POS (op) ? "0" : "-0"); - } - } - -@@ -77,21 +67,31 @@ - - l = strlen (s) + 1; /* size of allocated block returned by mpfr_get_str - - may be incorrect, as only an upper bound? */ -- if (*s == '-') -- fputc (*s++, stream); - -- /* outputs mantissa */ -- fputc (*s++, stream); e--; /* leading digit */ -- fputc ((unsigned char) MPFR_DECIMAL_POINT, stream); -- fputs (s, stream); /* rest of mantissa */ -+ /* outputs possible sign and significand */ -+ err = (*s == '-' && fputc (*s++, stream) == EOF) -+ || fputc (*s++, stream) == EOF /* leading digit */ -+ || fputc ((unsigned char) MPFR_DECIMAL_POINT, stream) == EOF -+ || fputs (s, stream) == EOF; /* trailing significand */ - (*__gmp_free_func) (s0, l); -+ if (MPFR_UNLIKELY (err)) -+ return 0; -+ -+ e--; /* due to the leading digit */ - - /* outputs exponent */ - if (e) - { -+ int r; -+ - MPFR_ASSERTN(e >= LONG_MIN); - MPFR_ASSERTN(e <= LONG_MAX); -- l += fprintf (stream, (base <= 10 ? "e%ld" : "@%ld"), (long) e); -+ -+ r = fprintf (stream, (base <= 10 ? "e%ld" : "@%ld"), (long) e); -+ if (MPFR_UNLIKELY (r < 0)) -+ return 0; -+ -+ l += r; - } - - return l; -diff -Naurd mpfr-3.0.0.orig/tests/tout_str.c mpfr-3.0.0/tests/tout_str.c ---- mpfr-3.0.0.orig/tests/tout_str.c 2010-06-10 11:00:13.000000000 +0000 -+++ mpfr-3.0.0/tests/tout_str.c 2010-06-23 11:03:12.000000000 +0000 -@@ -46,22 +46,54 @@ - special (void) - { - mpfr_t x; -+ unsigned int n; - - mpfr_init (x); - - mpfr_set_nan (x); -- mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ n = mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ if (n != 5) -+ { -+ printf ("Error: mpfr_out_str (file, 10, 0, NaN, MPFR_RNDN) wrote %u " -+ "characters instead of 5.\n", n); -+ exit (1); -+ } - - mpfr_set_inf (x, 1); -- mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ n = mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ if (n != 5) -+ { -+ printf ("Error: mpfr_out_str (file, 10, 0, +Inf, MPFR_RNDN) wrote %u " -+ "characters instead of 5.\n", n); -+ exit (1); -+ } - - mpfr_set_inf (x, -1); -- mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ n = mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ if (n != 6) -+ { -+ printf ("Error: mpfr_out_str (file, 10, 0, -Inf, MPFR_RNDN) wrote %u " -+ "characters instead of 6.\n", n); -+ exit (1); -+ } - - mpfr_set_ui (x, 0, MPFR_RNDN); -- mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ n = mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ if (n != 1) -+ { -+ printf ("Error: mpfr_out_str (file, 10, 0, +0, MPFR_RNDN) wrote %u " -+ "characters instead of 1.\n", n); -+ exit (1); -+ } -+ - mpfr_neg (x, x, MPFR_RNDN); -- mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ n = mpfr_out_str (fout, 10, 0, x, MPFR_RNDN); -+ if (n != 2) -+ { -+ printf ("Error: mpfr_out_str (file, 10, 0, -0, MPFR_RNDN) wrote %u " -+ "characters instead of 2.\n", n); -+ exit (1); -+ } - - mpfr_clear (x); - } -diff -Naurd mpfr-3.0.0.orig/version.c mpfr-3.0.0/version.c ---- mpfr-3.0.0.orig/version.c 2010-06-10 11:00:14.000000000 +0000 -+++ mpfr-3.0.0/version.c 2010-06-23 11:03:20.000000000 +0000 -@@ -25,5 +25,5 @@ - const char * - mpfr_get_version (void) - { -- return "3.0.0"; -+ return "3.0.0-p1"; - } -diff -Naurd mpfr-3.0.0.orig/Makefile.in mpfr-3.0.0/Makefile.in ---- mpfr-3.0.0.orig/Makefile.in 2010-06-10 11:00:52.000000000 +0000 -+++ mpfr-3.0.0/Makefile.in 2010-06-10 11:00:52.000000000 +0000 -@@ -239,6 +239,7 @@ - distuninstallcheck_listfiles = find . -type f -print - distcleancheck_listfiles = find . -type f -print - ACLOCAL = @ACLOCAL@ -+ALLOCA = @ALLOCA@ - AMTAR = @AMTAR@ - AR = @AR@ - AS = @AS@ -diff -Naurd mpfr-3.0.0.orig/PATCHES mpfr-3.0.0/PATCHES ---- mpfr-3.0.0.orig/PATCHES 2010-06-23 11:03:36.000000000 +0000 -+++ mpfr-3.0.0/PATCHES 2010-06-25 13:23:13.000000000 +0000 -@@ -0,0 +1 @@ -+alloca -diff -Naurd mpfr-3.0.0.orig/VERSION mpfr-3.0.0/VERSION ---- mpfr-3.0.0.orig/VERSION 2010-06-23 11:03:20.000000000 +0000 -+++ mpfr-3.0.0/VERSION 2010-06-25 13:23:13.000000000 +0000 -@@ -1 +1 @@ --3.0.0-p1 -+3.0.0-p2 -diff -Naurd mpfr-3.0.0.orig/acinclude.m4 mpfr-3.0.0/acinclude.m4 ---- mpfr-3.0.0.orig/acinclude.m4 2010-06-10 11:00:14.000000000 +0000 -+++ mpfr-3.0.0/acinclude.m4 2010-06-10 11:00:14.000000000 +0000 -@@ -59,6 +59,9 @@ - dnl sys/fpu.h - MIPS specific - AC_CHECK_HEADERS([sys/time.h sys/fpu.h]) - -+dnl Check how to get `alloca' -+AC_FUNC_ALLOCA -+ - dnl SIZE_MAX macro - gl_SIZE_MAX - -diff -Naurd mpfr-3.0.0.orig/configure mpfr-3.0.0/configure ---- mpfr-3.0.0.orig/configure 2010-06-10 11:00:51.000000000 +0000 -+++ mpfr-3.0.0/configure 2010-06-25 13:23:05.000000000 +0000 -@@ -783,6 +783,7 @@ - OBJDUMP - DLLTOOL - AS -+ALLOCA - MPFR_LIBM - ANSI2KNR - U -@@ -5622,6 +5623,197 @@ - done - - -+# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works -+# for constant arguments. Useless! -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for working alloca.h" >&5 -+$as_echo_n "checking for working alloca.h... " >&6; } -+if test "${ac_cv_working_alloca_h+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext -+/* end confdefs.h. */ -+#include -+int -+main () -+{ -+char *p = (char *) alloca (2 * sizeof (int)); -+ if (p) return 0; -+ ; -+ return 0; -+} -+_ACEOF -+if ac_fn_c_try_link "$LINENO"; then : -+ ac_cv_working_alloca_h=yes -+else -+ ac_cv_working_alloca_h=no -+fi -+rm -f core conftest.err conftest.$ac_objext \ -+ conftest$ac_exeext conftest.$ac_ext -+fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_working_alloca_h" >&5 -+$as_echo "$ac_cv_working_alloca_h" >&6; } -+if test $ac_cv_working_alloca_h = yes; then -+ -+$as_echo "#define HAVE_ALLOCA_H 1" >>confdefs.h -+ -+fi -+ -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for alloca" >&5 -+$as_echo_n "checking for alloca... " >&6; } -+if test "${ac_cv_func_alloca_works+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext -+/* end confdefs.h. */ -+#ifdef __GNUC__ -+# define alloca __builtin_alloca -+#else -+# ifdef _MSC_VER -+# include -+# define alloca _alloca -+# else -+# ifdef HAVE_ALLOCA_H -+# include -+# else -+# ifdef _AIX -+ #pragma alloca -+# else -+# ifndef alloca /* predefined by HP cc +Olibcalls */ -+char *alloca (); -+# endif -+# endif -+# endif -+# endif -+#endif -+ -+int -+main () -+{ -+char *p = (char *) alloca (1); -+ if (p) return 0; -+ ; -+ return 0; -+} -+_ACEOF -+if ac_fn_c_try_link "$LINENO"; then : -+ ac_cv_func_alloca_works=yes -+else -+ ac_cv_func_alloca_works=no -+fi -+rm -f core conftest.err conftest.$ac_objext \ -+ conftest$ac_exeext conftest.$ac_ext -+fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_func_alloca_works" >&5 -+$as_echo "$ac_cv_func_alloca_works" >&6; } -+ -+if test $ac_cv_func_alloca_works = yes; then -+ -+$as_echo "#define HAVE_ALLOCA 1" >>confdefs.h -+ -+else -+ # The SVR3 libPW and SVR4 libucb both contain incompatible functions -+# that cause trouble. Some versions do not even contain alloca or -+# contain a buggy version. If you still want to use their alloca, -+# use ar to extract alloca.o from them instead of compiling alloca.c. -+ -+ALLOCA=\${LIBOBJDIR}alloca.$ac_objext -+ -+$as_echo "#define C_ALLOCA 1" >>confdefs.h -+ -+ -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether \`alloca.c' needs Cray hooks" >&5 -+$as_echo_n "checking whether \`alloca.c' needs Cray hooks... " >&6; } -+if test "${ac_cv_os_cray+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext -+/* end confdefs.h. */ -+#if defined CRAY && ! defined CRAY2 -+webecray -+#else -+wenotbecray -+#endif -+ -+_ACEOF -+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | -+ $EGREP "webecray" >/dev/null 2>&1; then : -+ ac_cv_os_cray=yes -+else -+ ac_cv_os_cray=no -+fi -+rm -f conftest* -+ -+fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_os_cray" >&5 -+$as_echo "$ac_cv_os_cray" >&6; } -+if test $ac_cv_os_cray = yes; then -+ for ac_func in _getb67 GETB67 getb67; do -+ as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` -+ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" -+eval as_val=\$$as_ac_var -+ if test "x$as_val" = x""yes; then : -+ -+cat >>confdefs.h <<_ACEOF -+#define CRAY_STACKSEG_END $ac_func -+_ACEOF -+ -+ break -+fi -+ -+ done -+fi -+ -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking stack direction for C alloca" >&5 -+$as_echo_n "checking stack direction for C alloca... " >&6; } -+if test "${ac_cv_c_stack_direction+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ if test "$cross_compiling" = yes; then : -+ ac_cv_c_stack_direction=0 -+else -+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext -+/* end confdefs.h. */ -+$ac_includes_default -+int -+find_stack_direction () -+{ -+ static char *addr = 0; -+ auto char dummy; -+ if (addr == 0) -+ { -+ addr = &dummy; -+ return find_stack_direction (); -+ } -+ else -+ return (&dummy > addr) ? 1 : -1; -+} -+ -+int -+main () -+{ -+ return find_stack_direction () < 0; -+} -+_ACEOF -+if ac_fn_c_try_run "$LINENO"; then : -+ ac_cv_c_stack_direction=1 -+else -+ ac_cv_c_stack_direction=-1 -+fi -+rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ -+ conftest.$ac_objext conftest.beam conftest.$ac_ext -+fi -+ -+fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_stack_direction" >&5 -+$as_echo "$ac_cv_c_stack_direction" >&6; } -+cat >>confdefs.h <<_ACEOF -+#define STACK_DIRECTION $ac_cv_c_stack_direction -+_ACEOF -+ -+ -+fi -+ -+ - - for ac_header in stdint.h - do : -@@ -7564,13 +7756,13 @@ - else - lt_cv_nm_interface="BSD nm" - echo "int some_variable = 0;" > conftest.$ac_ext -- (eval echo "\"\$as_me:7567: $ac_compile\"" >&5) -+ (eval echo "\"\$as_me:7759: $ac_compile\"" >&5) - (eval "$ac_compile" 2>conftest.err) - cat conftest.err >&5 -- (eval echo "\"\$as_me:7570: $NM \\\"conftest.$ac_objext\\\"\"" >&5) -+ (eval echo "\"\$as_me:7762: $NM \\\"conftest.$ac_objext\\\"\"" >&5) - (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out) - cat conftest.err >&5 -- (eval echo "\"\$as_me:7573: output\"" >&5) -+ (eval echo "\"\$as_me:7765: output\"" >&5) - cat conftest.out >&5 - if $GREP 'External.*some_variable' conftest.out > /dev/null; then - lt_cv_nm_interface="MS dumpbin" -@@ -8772,7 +8964,7 @@ - ;; - *-*-irix6*) - # Find out which ABI we are using. -- echo '#line 8775 "configure"' > conftest.$ac_ext -+ echo '#line 8967 "configure"' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 - (eval $ac_compile) 2>&5 - ac_status=$? -@@ -10032,11 +10224,11 @@ - -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ - -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ - -e 's:$: $lt_compiler_flag:'` -- (eval echo "\"\$as_me:10035: $lt_compile\"" >&5) -+ (eval echo "\"\$as_me:10227: $lt_compile\"" >&5) - (eval "$lt_compile" 2>conftest.err) - ac_status=$? - cat conftest.err >&5 -- echo "$as_me:10039: \$? = $ac_status" >&5 -+ echo "$as_me:10231: \$? = $ac_status" >&5 - if (exit $ac_status) && test -s "$ac_outfile"; then - # The compiler can only warn and ignore the option if not recognized - # So say no if there are warnings other than the usual output. -@@ -10371,11 +10563,11 @@ - -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ - -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ - -e 's:$: $lt_compiler_flag:'` -- (eval echo "\"\$as_me:10374: $lt_compile\"" >&5) -+ (eval echo "\"\$as_me:10566: $lt_compile\"" >&5) - (eval "$lt_compile" 2>conftest.err) - ac_status=$? - cat conftest.err >&5 -- echo "$as_me:10378: \$? = $ac_status" >&5 -+ echo "$as_me:10570: \$? = $ac_status" >&5 - if (exit $ac_status) && test -s "$ac_outfile"; then - # The compiler can only warn and ignore the option if not recognized - # So say no if there are warnings other than the usual output. -@@ -10476,11 +10668,11 @@ - -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ - -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ - -e 's:$: $lt_compiler_flag:'` -- (eval echo "\"\$as_me:10479: $lt_compile\"" >&5) -+ (eval echo "\"\$as_me:10671: $lt_compile\"" >&5) - (eval "$lt_compile" 2>out/conftest.err) - ac_status=$? - cat out/conftest.err >&5 -- echo "$as_me:10483: \$? = $ac_status" >&5 -+ echo "$as_me:10675: \$? = $ac_status" >&5 - if (exit $ac_status) && test -s out/conftest2.$ac_objext - then - # The compiler can only warn and ignore the option if not recognized -@@ -10531,11 +10723,11 @@ - -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ - -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ - -e 's:$: $lt_compiler_flag:'` -- (eval echo "\"\$as_me:10534: $lt_compile\"" >&5) -+ (eval echo "\"\$as_me:10726: $lt_compile\"" >&5) - (eval "$lt_compile" 2>out/conftest.err) - ac_status=$? - cat out/conftest.err >&5 -- echo "$as_me:10538: \$? = $ac_status" >&5 -+ echo "$as_me:10730: \$? = $ac_status" >&5 - if (exit $ac_status) && test -s out/conftest2.$ac_objext - then - # The compiler can only warn and ignore the option if not recognized -@@ -12915,7 +13107,7 @@ - lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 - lt_status=$lt_dlunknown - cat > conftest.$ac_ext <<_LT_EOF --#line 12918 "configure" -+#line 13110 "configure" - #include "confdefs.h" - - #if HAVE_DLFCN_H -@@ -13011,7 +13203,7 @@ - lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 - lt_status=$lt_dlunknown - cat > conftest.$ac_ext <<_LT_EOF --#line 13014 "configure" -+#line 13206 "configure" - #include "confdefs.h" - - #if HAVE_DLFCN_H -diff -Naurd mpfr-3.0.0.orig/mpfr.h mpfr-3.0.0/mpfr.h ---- mpfr-3.0.0.orig/mpfr.h 2010-06-23 11:03:20.000000000 +0000 -+++ mpfr-3.0.0/mpfr.h 2010-06-25 13:23:13.000000000 +0000 -@@ -27,7 +27,7 @@ - #define MPFR_VERSION_MAJOR 3 - #define MPFR_VERSION_MINOR 0 - #define MPFR_VERSION_PATCHLEVEL 0 --#define MPFR_VERSION_STRING "3.0.0-p1" -+#define MPFR_VERSION_STRING "3.0.0-p2" - - /* Macros dealing with MPFR VERSION */ - #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c)) -diff -Naurd mpfr-3.0.0.orig/tests/Makefile.in mpfr-3.0.0/tests/Makefile.in ---- mpfr-3.0.0.orig/tests/Makefile.in 2010-06-10 11:00:52.000000000 +0000 -+++ mpfr-3.0.0/tests/Makefile.in 2010-06-10 11:00:52.000000000 +0000 -@@ -960,6 +960,7 @@ - red=; grn=; lgn=; blu=; std= - DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) - ACLOCAL = @ACLOCAL@ -+ALLOCA = @ALLOCA@ - AMTAR = @AMTAR@ - AR = @AR@ - AS = @AS@ -diff -Naurd mpfr-3.0.0.orig/version.c mpfr-3.0.0/version.c ---- mpfr-3.0.0.orig/version.c 2010-06-23 11:03:20.000000000 +0000 -+++ mpfr-3.0.0/version.c 2010-06-25 13:23:13.000000000 +0000 -@@ -25,5 +25,5 @@ - const char * - mpfr_get_version (void) - { -- return "3.0.0-p1"; -+ return "3.0.0-p2"; - } -diff -Naurd mpfr-3.0.0.orig/PATCHES mpfr-3.0.0/PATCHES ---- mpfr-3.0.0.orig/PATCHES 2010-07-10 00:11:19.000000000 +0000 -+++ mpfr-3.0.0/PATCHES 2010-07-10 00:12:50.000000000 +0000 -@@ -0,0 +1 @@ -+gamma_underflow -diff -Naurd mpfr-3.0.0.orig/VERSION mpfr-3.0.0/VERSION ---- mpfr-3.0.0.orig/VERSION 2010-06-25 13:23:13.000000000 +0000 -+++ mpfr-3.0.0/VERSION 2010-07-10 00:11:53.000000000 +0000 -@@ -1 +1 @@ --3.0.0-p2 -+3.0.0-p3 -diff -Naurd mpfr-3.0.0.orig/gamma.c mpfr-3.0.0/gamma.c ---- mpfr-3.0.0.orig/gamma.c 2010-06-10 11:00:14.000000000 +0000 -+++ mpfr-3.0.0/gamma.c 2010-07-10 00:11:46.000000000 +0000 -@@ -274,7 +274,7 @@ - /* we want an upper bound for x * [log(2-x)-1]. - since x < 0, we need a lower bound on log(2-x) */ - mpfr_ui_sub (xp, 2, x, MPFR_RNDD); -- mpfr_log (xp, xp, MPFR_RNDD); -+ mpfr_log2 (xp, xp, MPFR_RNDD); - mpfr_sub_ui (xp, xp, 1, MPFR_RNDD); - mpfr_mul (xp, xp, x, MPFR_RNDU); - -@@ -303,8 +303,8 @@ - { - mpfr_sub (tmp, tmp, tmp2, MPFR_RNDZ); /* low bnd on |sin(Pi*(2-x))| */ - mpfr_ui_div (tmp, 12, tmp, MPFR_RNDU); /* upper bound */ -- mpfr_log (tmp, tmp, MPFR_RNDU); -- mpfr_add (tmp, tmp, xp, MPFR_RNDU); -+ mpfr_log2 (tmp, tmp, MPFR_RNDU); -+ mpfr_add (xp, tmp, xp, MPFR_RNDU); - underflow = mpfr_cmp_si (xp, expo.saved_emin - 2) <= 0; - } - -diff -Naurd mpfr-3.0.0.orig/mpfr.h mpfr-3.0.0/mpfr.h ---- mpfr-3.0.0.orig/mpfr.h 2010-06-25 13:23:13.000000000 +0000 -+++ mpfr-3.0.0/mpfr.h 2010-07-10 00:11:53.000000000 +0000 -@@ -27,7 +27,7 @@ - #define MPFR_VERSION_MAJOR 3 - #define MPFR_VERSION_MINOR 0 - #define MPFR_VERSION_PATCHLEVEL 0 --#define MPFR_VERSION_STRING "3.0.0-p2" -+#define MPFR_VERSION_STRING "3.0.0-p3" - - /* Macros dealing with MPFR VERSION */ - #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c)) -diff -Naurd mpfr-3.0.0.orig/tests/tgamma.c mpfr-3.0.0/tests/tgamma.c ---- mpfr-3.0.0.orig/tests/tgamma.c 2010-06-10 11:00:13.000000000 +0000 -+++ mpfr-3.0.0/tests/tgamma.c 2010-07-10 00:11:46.000000000 +0000 -@@ -461,6 +461,20 @@ - mpfr_clear (x); - } - -+/* bug found by Stathis, only occurs on 32-bit machines */ -+static void -+test20100709 (void) -+{ -+ mpfr_t x; -+ int inex; -+ -+ mpfr_init2 (x, 100); -+ mpfr_set_str (x, "-4.6308260837372266e+07", 10, MPFR_RNDN); -+ inex = mpfr_gamma (x, x, MPFR_RNDN); -+ MPFR_ASSERTN(MPFR_IS_ZERO(x) && MPFR_IS_NEG(x) && inex > 0); -+ mpfr_clear (x); -+} -+ - int - main (int argc, char *argv[]) - { -@@ -471,6 +485,7 @@ - test_generic (2, 100, 2); - gamma_integer (); - test20071231 (); -+ test20100709 (); - - data_check ("data/gamma", mpfr_gamma, "mpfr_gamma"); - -diff -Naurd mpfr-3.0.0.orig/version.c mpfr-3.0.0/version.c ---- mpfr-3.0.0.orig/version.c 2010-06-25 13:23:13.000000000 +0000 -+++ mpfr-3.0.0/version.c 2010-07-10 00:11:53.000000000 +0000 -@@ -25,5 +25,5 @@ - const char * - mpfr_get_version (void) - { -- return "3.0.0-p2"; -+ return "3.0.0-p3"; - } -diff -Naurd mpfr-3.0.0.orig/PATCHES mpfr-3.0.0/PATCHES ---- mpfr-3.0.0.orig/PATCHES 2010-09-07 08:44:01.000000000 +0000 -+++ mpfr-3.0.0/PATCHES 2010-09-07 08:48:46.000000000 +0000 -@@ -0,0 +1 @@ -+mpfr_cmp/set_ui/si -diff -Naurd mpfr-3.0.0.orig/VERSION mpfr-3.0.0/VERSION ---- mpfr-3.0.0.orig/VERSION 2010-07-10 00:11:53.000000000 +0000 -+++ mpfr-3.0.0/VERSION 2010-09-07 08:46:06.000000000 +0000 -@@ -1 +1 @@ --3.0.0-p3 -+3.0.0-p4 -diff -Naurd mpfr-3.0.0.orig/mpfr.h mpfr-3.0.0/mpfr.h ---- mpfr-3.0.0.orig/mpfr.h 2010-07-10 00:11:53.000000000 +0000 -+++ mpfr-3.0.0/mpfr.h 2010-09-07 08:46:06.000000000 +0000 -@@ -27,7 +27,7 @@ - #define MPFR_VERSION_MAJOR 3 - #define MPFR_VERSION_MINOR 0 - #define MPFR_VERSION_PATCHLEVEL 0 --#define MPFR_VERSION_STRING "3.0.0-p3" -+#define MPFR_VERSION_STRING "3.0.0-p4" - - /* Macros dealing with MPFR VERSION */ - #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c)) -@@ -798,35 +798,45 @@ - anyway. Checking with other ICC versions is needed. Possibly detect - whether warnings are produced or not with a configure test. - + Remove C++ too, since it complains too much. */ -+/* Added casts to improve robustness in case of undefined behavior and -+ compiler extensions based on UB (in particular -fwrapv). MPFR doesn't -+ use such extensions, but these macros will be used by 3rd-party code, -+ where such extensions may be required. -+ Moreover casts to unsigned long have been added to avoid warnings in -+ programs that use MPFR and are compiled with -Wconversion; such casts -+ are OK since if X is a constant expression, then (unsigned long) X is -+ also a constant expression, so that the optimizations still work. */ - #if defined (__GNUC__) && !defined(__ICC) && !defined(__cplusplus) - #if (__GNUC__ >= 2) - #undef mpfr_cmp_ui --/* We use the fact that mpfr_sgn on NaN sets the erange flag and returns 0. */ --#define mpfr_cmp_ui(_f,_u) \ -- (__builtin_constant_p (_u) && (_u) == 0 ? \ -- mpfr_sgn (_f) : \ -- mpfr_cmp_ui_2exp ((_f),(_u),0)) -+/* We use the fact that mpfr_sgn on NaN sets the erange flag and returns 0. -+ But warning! mpfr_sgn is specified as a macro in the API, thus the macro -+ mustn't be used if side effects are possible, like here. */ -+#define mpfr_cmp_ui(_f,_u) \ -+ (__builtin_constant_p (_u) && (unsigned long) (_u) == 0 ? \ -+ (mpfr_sgn) (_f) : \ -+ mpfr_cmp_ui_2exp ((_f), (unsigned long) (_u), 0)) - #undef mpfr_cmp_si --#define mpfr_cmp_si(_f,_s) \ -- (__builtin_constant_p (_s) && (_s) >= 0 ? \ -- mpfr_cmp_ui ((_f), (_s)) : \ -- mpfr_cmp_si_2exp ((_f), (_s), 0)) -+#define mpfr_cmp_si(_f,_s) \ -+ (__builtin_constant_p (_s) && (long) (_s) >= 0 ? \ -+ mpfr_cmp_ui ((_f), (unsigned long) (long) (_s)) : \ -+ mpfr_cmp_si_2exp ((_f), (long) (_s), 0)) - #if __GNUC__ > 2 || __GNUC_MINOR__ >= 95 - #undef mpfr_set_ui --#define mpfr_set_ui(_f,_u,_r) \ -- (__builtin_constant_p (_u) && (_u) == 0 ? \ -- __extension__ ({ \ -- mpfr_ptr _p = (_f); \ -- _p->_mpfr_sign = 1; \ -- _p->_mpfr_exp = __MPFR_EXP_ZERO; \ -- (void) (_r); 0; }) : \ -- mpfr_set_ui_2exp ((_f), (_u), 0, (_r))) -+#define mpfr_set_ui(_f,_u,_r) \ -+ (__builtin_constant_p (_u) && (unsigned long) (_u) == 0 ? \ -+ __extension__ ({ \ -+ mpfr_ptr _p = (_f); \ -+ _p->_mpfr_sign = 1; \ -+ _p->_mpfr_exp = __MPFR_EXP_ZERO; \ -+ (void) (_r); 0; }) : \ -+ mpfr_set_ui_2exp ((_f), (unsigned long) (_u), 0, (_r))) - #endif - #undef mpfr_set_si --#define mpfr_set_si(_f,_s,_r) \ -- (__builtin_constant_p (_s) && (_s) >= 0 ? \ -- mpfr_set_ui ((_f), (_s), (_r)) : \ -- mpfr_set_si_2exp ((_f), (_s), 0, (_r))) -+#define mpfr_set_si(_f,_s,_r) \ -+ (__builtin_constant_p (_s) && (long) (_s) >= 0 ? \ -+ mpfr_set_ui ((_f), (unsigned long) (long) (_s), (_r)) : \ -+ mpfr_set_si_2exp ((_f), (long) (_s), 0, (_r))) - #endif - #endif - -diff -Naurd mpfr-3.0.0.orig/tests/tcmp_ui.c mpfr-3.0.0/tests/tcmp_ui.c ---- mpfr-3.0.0.orig/tests/tcmp_ui.c 2010-06-10 11:00:13.000000000 +0000 -+++ mpfr-3.0.0/tests/tcmp_ui.c 2010-09-07 08:45:12.000000000 +0000 -@@ -88,6 +88,126 @@ - mpfr_clear (x); - } - -+/* Since mpfr_cmp_ui and mpfr_cmp_si are also implemented by a macro -+ with __builtin_constant_p for GCC, check that side effects are -+ handled correctly. */ -+static void -+check_macros (void) -+{ -+ mpfr_t x; -+ int c; -+ -+ mpfr_init2 (x, 32); -+ -+ c = 0; -+ mpfr_set_ui (x, 17, MPFR_RNDN); -+ if (mpfr_cmp_ui (x, 17) != 0) -+ { -+ printf ("Error 1 on mpfr_cmp_ui(x,17) in check_macros\n"); -+ exit (1); -+ } -+ if (mpfr_cmp_ui (x, (c++, 17)) != 0) -+ { -+ printf ("Error 2 on mpfr_cmp_ui(x,17) in check_macros\n"); -+ exit (1); -+ } -+ if (c != 1) -+ { -+ printf ("Error 3 on mpfr_cmp_ui(x,17) in check_macros\n" -+ "(c = %d instead of 1)\n", c); -+ exit (1); -+ } -+ if (mpfr_cmp_si (x, 17) != 0) -+ { -+ printf ("Error 1 on mpfr_cmp_si(x,17) in check_macros\n"); -+ exit (1); -+ } -+ if (mpfr_cmp_si (x, (c++, 17)) != 0) -+ { -+ printf ("Error 2 on mpfr_cmp_si(x,17) in check_macros\n"); -+ exit (1); -+ } -+ if (c != 2) -+ { -+ printf ("Error 3 on mpfr_cmp_si(x,17) in check_macros\n" -+ "(c = %d instead of 2)\n", c); -+ exit (1); -+ } -+ -+ c = 0; -+ mpfr_set_ui (x, 0, MPFR_RNDN); -+ if (mpfr_cmp_ui (x, 0) != 0) -+ { -+ printf ("Error 1 on mpfr_cmp_ui(x,0) in check_macros\n"); -+ exit (1); -+ } -+ if (mpfr_cmp_ui (x, (c++, 0)) != 0) -+ { -+ printf ("Error 2 on mpfr_cmp_ui(x,0) in check_macros\n"); -+ exit (1); -+ } -+ if (c != 1) -+ { -+ printf ("Error 3 on mpfr_cmp_ui(x,0) in check_macros\n" -+ "(c = %d instead of 1)\n", c); -+ exit (1); -+ } -+ if (mpfr_cmp_si (x, 0) != 0) -+ { -+ printf ("Error 1 on mpfr_cmp_si(x,0) in check_macros\n"); -+ exit (1); -+ } -+ if (mpfr_cmp_si (x, (c++, 0)) != 0) -+ { -+ printf ("Error 2 on mpfr_cmp_si(x,0) in check_macros\n"); -+ exit (1); -+ } -+ if (c != 2) -+ { -+ printf ("Error 3 on mpfr_cmp_si(x,0) in check_macros\n" -+ "(c = %d instead of 2)\n", c); -+ exit (1); -+ } -+ -+ mpfr_clear (x); -+} -+ -+/* Bug in r7114 */ -+static void -+test_macros (void) -+{ -+ mpfr_t x[3]; -+ mpfr_ptr p; -+ -+ mpfr_inits (x[0], x[1], x[2], (mpfr_ptr) 0); -+ mpfr_set_ui (x[0], 0, MPFR_RNDN); -+ p = x[0]; -+ if (mpfr_cmp_ui (p++, 0) != 0) -+ { -+ printf ("Error in mpfr_cmp_ui macro: result should be 0.\n"); -+ exit (1); -+ } -+ if (p != x[1]) -+ { -+ printf ("Error in mpfr_cmp_ui macro: p - x[0] = %d (expecting 1)\n", -+ (int) (p - x[0])); -+ exit (1); -+ } -+ p = x[0]; -+ if (mpfr_cmp_si (p++, 0) != 0) -+ { -+ printf ("Error in mpfr_cmp_si macro: result should be 0.\n"); -+ exit (1); -+ } -+ if (p != x[1]) -+ { -+ printf ("Error in mpfr_cmp_si macro: p - x[0] = %d (expecting 1)\n", -+ (int) (p - x[0])); -+ exit (1); -+ } -+ mpfr_clears (x[0], x[1], x[2], (mpfr_ptr) 0); -+} -+ - int - main (void) - { -@@ -216,6 +336,8 @@ - mpfr_clear (x); - - check_nan (); -+ check_macros (); -+ test_macros (); - - tests_end_mpfr (); - return 0; -diff -Naurd mpfr-3.0.0.orig/version.c mpfr-3.0.0/version.c ---- mpfr-3.0.0.orig/version.c 2010-07-10 00:11:53.000000000 +0000 -+++ mpfr-3.0.0/version.c 2010-09-07 08:46:06.000000000 +0000 -@@ -25,5 +25,5 @@ - const char * - mpfr_get_version (void) - { -- return "3.0.0-p3"; -+ return "3.0.0-p4"; - } -diff -Naurd mpfr-3.0.0.orig/PATCHES mpfr-3.0.0/PATCHES ---- mpfr-3.0.0.orig/PATCHES 2010-10-21 20:28:38.000000000 +0000 -+++ mpfr-3.0.0/PATCHES 2010-10-21 20:28:38.000000000 +0000 -@@ -0,0 +1 @@ -+tcan_round -diff -Naurd mpfr-3.0.0.orig/VERSION mpfr-3.0.0/VERSION ---- mpfr-3.0.0.orig/VERSION 2010-09-07 08:46:06.000000000 +0000 -+++ mpfr-3.0.0/VERSION 2010-10-21 20:28:38.000000000 +0000 -@@ -1 +1 @@ --3.0.0-p4 -+3.0.0-p5 -diff -Naurd mpfr-3.0.0.orig/mpfr.h mpfr-3.0.0/mpfr.h ---- mpfr-3.0.0.orig/mpfr.h 2010-09-07 08:46:06.000000000 +0000 -+++ mpfr-3.0.0/mpfr.h 2010-10-21 20:28:38.000000000 +0000 -@@ -27,7 +27,7 @@ - #define MPFR_VERSION_MAJOR 3 - #define MPFR_VERSION_MINOR 0 - #define MPFR_VERSION_PATCHLEVEL 0 --#define MPFR_VERSION_STRING "3.0.0-p4" -+#define MPFR_VERSION_STRING "3.0.0-p5" - - /* Macros dealing with MPFR VERSION */ - #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c)) -diff -Naurd mpfr-3.0.0.orig/tests/tcan_round.c mpfr-3.0.0/tests/tcan_round.c ---- mpfr-3.0.0.orig/tests/tcan_round.c 2010-06-10 11:00:13.000000000 +0000 -+++ mpfr-3.0.0/tests/tcan_round.c 2010-10-21 20:28:38.000000000 +0000 -@@ -41,7 +41,7 @@ - /* avoid mpn_random which leaks memory */ - for (i = 0; i < n; i++) - buf[i] = randlimb (); -- p = (mpfr_prec_t) randlimb() % ((n-1) * GMP_NUMB_BITS) + MPFR_PREC_MIN; -+ p = randlimb() % ((n-1) * GMP_NUMB_BITS) + MPFR_PREC_MIN; - err = p + randlimb () % GMP_NUMB_BITS; - r1 = mpfr_round_p (buf, n, err, p); - r2 = mpfr_can_round_raw (buf, n, MPFR_SIGN_POS, err, -diff -Naurd mpfr-3.0.0.orig/version.c mpfr-3.0.0/version.c ---- mpfr-3.0.0.orig/version.c 2010-09-07 08:46:06.000000000 +0000 -+++ mpfr-3.0.0/version.c 2010-10-21 20:28:38.000000000 +0000 -@@ -25,5 +25,5 @@ - const char * - mpfr_get_version (void) - { -- return "3.0.0-p4"; -+ return "3.0.0-p5"; - } -diff -Naurd mpfr-3.0.0.orig/PATCHES mpfr-3.0.0/PATCHES ---- mpfr-3.0.0.orig/PATCHES 2010-10-21 20:59:32.000000000 +0000 -+++ mpfr-3.0.0/PATCHES 2010-10-21 20:59:32.000000000 +0000 -@@ -0,0 +1 @@ -+mpfr_sub1 -diff -Naurd mpfr-3.0.0.orig/VERSION mpfr-3.0.0/VERSION ---- mpfr-3.0.0.orig/VERSION 2010-10-21 20:28:38.000000000 +0000 -+++ mpfr-3.0.0/VERSION 2010-10-21 20:59:32.000000000 +0000 -@@ -1 +1 @@ --3.0.0-p5 -+3.0.0-p6 -diff -Naurd mpfr-3.0.0.orig/mpfr.h mpfr-3.0.0/mpfr.h ---- mpfr-3.0.0.orig/mpfr.h 2010-10-21 20:28:38.000000000 +0000 -+++ mpfr-3.0.0/mpfr.h 2010-10-21 20:59:32.000000000 +0000 -@@ -27,7 +27,7 @@ - #define MPFR_VERSION_MAJOR 3 - #define MPFR_VERSION_MINOR 0 - #define MPFR_VERSION_PATCHLEVEL 0 --#define MPFR_VERSION_STRING "3.0.0-p5" -+#define MPFR_VERSION_STRING "3.0.0-p6" - - /* Macros dealing with MPFR VERSION */ - #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c)) -diff -Naurd mpfr-3.0.0.orig/sub1.c mpfr-3.0.0/sub1.c ---- mpfr-3.0.0.orig/sub1.c 2010-06-10 11:00:14.000000000 +0000 -+++ mpfr-3.0.0/sub1.c 2010-10-21 20:59:32.000000000 +0000 -@@ -37,7 +37,9 @@ - mp_size_t cancel2, an, bn, cn, cn0; - mp_limb_t *ap, *bp, *cp; - mp_limb_t carry, bb, cc, borrow = 0; -- int inexact, shift_b, shift_c, is_exact = 1, down = 0, add_exp = 0; -+ int inexact, shift_b, shift_c, add_exp = 0; -+ int cmp_low = 0; /* used for rounding to nearest: 0 if low(b) = low(c), -+ negative if low(b) < low(c), positive if low(b)>low(c) */ - int sh, k; - MPFR_TMP_DECL(marker); - -@@ -196,7 +198,8 @@ - } - - #ifdef DEBUG -- printf ("shift_b=%d shift_c=%d diffexp=%lu\n", shift_b, shift_c, -+ printf ("rnd=%s shift_b=%d shift_c=%d diffexp=%lu\n", -+ mpfr_print_rnd_mode (rnd_mode), shift_b, shift_c, - (unsigned long) diff_exp); - #endif - -@@ -307,17 +310,18 @@ - { - if (MPFR_LIKELY(sh)) - { -- is_exact = (carry == 0); - /* can decide except when carry = 2^(sh-1) [middle] - or carry = 0 [truncate, but cannot decide inexact flag] */ -- down = (carry < (MPFR_LIMB_ONE << (sh - 1))); - if (carry > (MPFR_LIMB_ONE << (sh - 1))) - goto add_one_ulp; -- else if ((0 < carry) && down) -+ else if ((0 < carry) && (carry < (MPFR_LIMB_ONE << (sh - 1)))) - { - inexact = -1; /* result if smaller than exact value */ - goto truncate; - } -+ /* now carry = 2^(sh-1), in which case cmp_low=2, -+ or carry = 0, in which case cmp_low=0 */ -+ cmp_low = (carry == 0) ? 0 : 2; - } - } - else /* directed rounding: set rnd_mode to RNDZ iff toward zero */ -@@ -344,12 +348,32 @@ - cn -= (long int) an + cancel2; - - #ifdef DEBUG -- printf ("last %d bits from a are %lu, bn=%ld, cn=%ld\n", -+ printf ("last sh=%d bits from a are %lu, bn=%ld, cn=%ld\n", - sh, (unsigned long) carry, (long) bn, (long) cn); - #endif - -+ /* for rounding to nearest, we couldn't conclude up to here in the following -+ cases: -+ 1. sh = 0, then cmp_low=0: we can either truncate, subtract one ulp -+ or add one ulp: -1 ulp < low(b)-low(c) < 1 ulp -+ 2. sh > 0 but the low sh bits from high(b)-high(c) equal 2^(sh-1): -+ -0.5 ulp <= -1/2^sh < low(b)-low(c)-0.5 < 1/2^sh <= 0.5 ulp -+ we can't decide the rounding, in that case cmp_low=2: -+ either we truncate and flag=-1, or we add one ulp and flag=1 -+ 3. the low sh>0 bits from high(b)-high(c) equal 0: we know we have to -+ truncate but we can't decide the ternary value, here cmp_low=0: -+ -0.5 ulp <= -1/2^sh < low(b)-low(c) < 1/2^sh <= 0.5 ulp -+ we always truncate and inexact can be any of -1,0,1 -+ */ -+ -+ /* note: here cn might exceed cn0, in which case we consider a zero limb */ - for (k = 0; (bn > 0) || (cn > 0); k = 1) - { -+ /* if cmp_low < 0, we know low(b) - low(c) < 0 -+ if cmp_low > 0, we know low(b) - low(c) > 0 -+ (more precisely if cmp_low = 2, low(b) - low(c) = 0.5 ulp so far) -+ if cmp_low = 0, so far low(b) - low(c) = 0 */ -+ - /* get next limbs */ - bb = (bn > 0) ? bp[--bn] : 0; - if ((cn > 0) && (cn-- <= cn0)) -@@ -357,76 +381,115 @@ - else - cc = 0; - -- /* down is set when low(b) < low(c) */ -- if (down == 0) -- down = (bb < cc); -+ /* cmp_low compares low(b) and low(c) */ -+ if (cmp_low == 0) /* case 1 or 3 */ -+ cmp_low = (bb < cc) ? -2+k : (bb > cc) ? 1 : 0; -+ -+ /* Case 1 for k=0 splits into 7 subcases: -+ 1a: bb > cc + half -+ 1b: bb = cc + half -+ 1c: 0 < bb - cc < half -+ 1d: bb = cc -+ 1e: -half < bb - cc < 0 -+ 1f: bb - cc = -half -+ 1g: bb - cc < -half -+ -+ Case 2 splits into 3 subcases: -+ 2a: bb > cc -+ 2b: bb = cc -+ 2c: bb < cc -+ -+ Case 3 splits into 3 subcases: -+ 3a: bb > cc -+ 3b: bb = cc -+ 3c: bb < cc -+ */ - - /* the case rounding to nearest with sh=0 is special since one couldn't - subtract above 1/2 ulp in the trailing limb of the result */ -- if ((rnd_mode == MPFR_RNDN) && sh == 0 && k == 0) -+ if (rnd_mode == MPFR_RNDN && sh == 0 && k == 0) /* case 1 for k=0 */ - { - mp_limb_t half = MPFR_LIMB_HIGHBIT; - -- is_exact = (bb == cc); -- - /* add one ulp if bb > cc + half - truncate if cc - half < bb < cc + half - sub one ulp if bb < cc - half - */ - -- if (down) -+ if (cmp_low < 0) /* bb < cc: -1 ulp < low(b) - low(c) < 0, -+ cases 1e, 1f and 1g */ - { - if (cc >= half) - cc -= half; -- else -+ else /* since bb < cc < half, bb+half < 2*half */ - bb += half; -+ /* now we have bb < cc + half: -+ we have to subtract one ulp if bb < cc, -+ and truncate if bb > cc */ - } -- else /* bb >= cc */ -+ else if (cmp_low >= 0) /* bb >= cc, cases 1a to 1d */ - { - if (cc < half) - cc += half; -- else -+ else /* since bb >= cc >= half, bb - half >= 0 */ - bb -= half; -+ /* now we have bb > cc - half: we have to add one ulp if bb > cc, -+ and truncate if bb < cc */ -+ if (cmp_low > 0) -+ cmp_low = 2; - } - } - - #ifdef DEBUG -- printf (" bb=%lu cc=%lu down=%d is_exact=%d\n", -- (unsigned long) bb, (unsigned long) cc, down, is_exact); -+ printf ("k=%u bb=%lu cc=%lu cmp_low=%d\n", k, -+ (unsigned long) bb, (unsigned long) cc, cmp_low); - #endif -- if (bb < cc) -+ if (cmp_low < 0) /* low(b) - low(c) < 0: either truncate or subtract -+ one ulp */ - { - if (rnd_mode == MPFR_RNDZ) -- goto sub_one_ulp; -+ goto sub_one_ulp; /* set inexact=-1 */ - else if (rnd_mode != MPFR_RNDN) /* round away */ - { - inexact = 1; - goto truncate; - } -- else /* round to nearest: special case here since for sh=k=0 -- bb = bb0 - MPFR_LIMB_HIGHBIT */ -+ else /* round to nearest */ - { -- if (is_exact && sh == 0) -- { -- /* For k=0 we can't decide exactness since it may depend -- from low order bits. -- For k=1, the first low limbs matched: low(b)-low(c)<0. */ -- if (k) -- { -- inexact = 1; -- goto truncate; -- } -- } -- else if (down && sh == 0) -- goto sub_one_ulp; -- else -- { -- inexact = (is_exact) ? 1 : -1; -+ /* If cmp_low < 0 and bb > cc, then -0.5 ulp < low(b)-low(c) < 0, -+ whatever the value of sh. -+ If sh>0, then cmp_low < 0 implies that the initial neglected -+ sh bits were 0 (otherwise cmp_low=2 initially), thus the -+ weight of the new bits is less than 0.5 ulp too. -+ If k > 0 (and sh=0) this means that either the first neglected -+ limbs bb and cc were equal (thus cmp_low was 0 for k=0), -+ or we had bb - cc = -0.5 ulp or 0.5 ulp. -+ The last case is not possible here since we would have -+ cmp_low > 0 which is sticky. -+ In the first case (where we have cmp_low = -1), we truncate, -+ whereas in the 2nd case we have cmp_low = -2 and we subtract -+ one ulp. -+ */ -+ if (bb > cc || sh > 0 || cmp_low == -1) -+ { /* -0.5 ulp < low(b)-low(c) < 0, -+ bb > cc corresponds to cases 1e and 1f1 -+ sh > 0 corresponds to cases 3c and 3b3 -+ cmp_low = -1 corresponds to case 1d3 (also 3b3) */ -+ inexact = 1; - goto truncate; - } -+ else if (bb < cc) /* here sh = 0 and low(b)-low(c) < -0.5 ulp, -+ this corresponds to cases 1g and 1f3 */ -+ goto sub_one_ulp; -+ /* the only case where we can't conclude is sh=0 and bb=cc, -+ i.e., we have low(b) - low(c) = -0.5 ulp (up to now), thus -+ we don't know if we must truncate or subtract one ulp. -+ Note: for sh=0 we can't have low(b) - low(c) = -0.5 ulp up to -+ now, since low(b) - low(c) > 1/2^sh */ - } - } -- else if (bb > cc) -+ else if (cmp_low > 0) /* 0 < low(b) - low(c): either truncate or -+ add one ulp */ - { - if (rnd_mode == MPFR_RNDZ) - { -@@ -437,34 +500,70 @@ - goto add_one_ulp; - else /* round to nearest */ - { -- if (is_exact) -+ if (bb > cc) - { -- inexact = -1; -- goto truncate; -+ /* if sh=0, then bb>cc means that low(b)-low(c) > 0.5 ulp, -+ and similarly when cmp_low=2 */ -+ if (cmp_low == 2) /* cases 1a, 1b1, 2a and 2b1 */ -+ goto add_one_ulp; -+ /* sh > 0 and cmp_low > 0: this implies that the sh initial -+ neglected bits were 0, and the remaining low(b)-low(c)>0, -+ but its weight is less than 0.5 ulp */ -+ else /* 0 < low(b) - low(c) < 0.5 ulp, this corresponds to -+ cases 3a, 1d1 and 3b1 */ -+ { -+ inexact = -1; -+ goto truncate; -+ } - } -- else if (down) -+ else if (bb < cc) /* 0 < low(b) - low(c) < 0.5 ulp, cases 1c, -+ 1b3, 2b3 and 2c */ - { -- inexact = 1; -+ inexact = -1; - goto truncate; - } -- else -- goto add_one_ulp; -+ /* the only case where we can't conclude is bb=cc, i.e., -+ low(b) - low(c) = 0.5 ulp (up to now), thus we don't know -+ if we must truncate or add one ulp. */ - } - } -+ /* after k=0, we cannot conclude in the following cases, we split them -+ according to the values of bb and cc for k=1: -+ 1b. sh=0 and cmp_low = 1 and bb-cc = half [around 0.5 ulp] -+ 1b1. bb > cc: add one ulp, inex = 1 -+ 1b2: bb = cc: cannot conclude -+ 1b3: bb < cc: truncate, inex = -1 -+ 1d. sh=0 and cmp_low = 0 and bb-cc = 0 [around 0] -+ 1d1: bb > cc: truncate, inex = -1 -+ 1d2: bb = cc: cannot conclude -+ 1d3: bb < cc: truncate, inex = +1 -+ 1f. sh=0 and cmp_low = -1 and bb-cc = -half [around -0.5 ulp] -+ 1f1: bb > cc: truncate, inex = +1 -+ 1f2: bb = cc: cannot conclude -+ 1f3: bb < cc: sub one ulp, inex = -1 -+ 2b. sh > 0 and cmp_low = 2 and bb=cc [around 0.5 ulp] -+ 2b1. bb > cc: add one ulp, inex = 1 -+ 2b2: bb = cc: cannot conclude -+ 2b3: bb < cc: truncate, inex = -1 -+ 3b. sh > 0 and cmp_low = 0 [around 0] -+ 3b1. bb > cc: truncate, inex = -1 -+ 3b2: bb = cc: cannot conclude -+ 3b3: bb < cc: truncate, inex = +1 -+ */ - } - -- if ((rnd_mode == MPFR_RNDN) && !is_exact) -+ if ((rnd_mode == MPFR_RNDN) && cmp_low != 0) - { - /* even rounding rule */ - if ((ap[0] >> sh) & 1) - { -- if (down) -+ if (cmp_low < 0) - goto sub_one_ulp; - else - goto add_one_ulp; - } - else -- inexact = (down) ? 1 : -1; -+ inexact = (cmp_low > 0) ? -1 : 1; - } - else - inexact = 0; -diff -Naurd mpfr-3.0.0.orig/tests/tfma.c mpfr-3.0.0/tests/tfma.c ---- mpfr-3.0.0.orig/tests/tfma.c 2010-06-10 11:00:13.000000000 +0000 -+++ mpfr-3.0.0/tests/tfma.c 2010-10-21 20:59:32.000000000 +0000 -@@ -337,6 +337,94 @@ - mpfr_clears (x, y, z, r, (mpfr_ptr) 0); - } - -+static void -+bug20101018 (void) -+{ -+ mpfr_t x, y, z, t, u; -+ int i; -+ -+ mpfr_init2 (x, 64); -+ mpfr_init2 (y, 64); -+ mpfr_init2 (z, 64); -+ mpfr_init2 (t, 64); -+ mpfr_init2 (u, 64); -+ -+ mpfr_set_str (x, "0xf.fffffffffffffffp-14766", 16, MPFR_RNDN); -+ mpfr_set_str (y, "-0xf.fffffffffffffffp+317", 16, MPFR_RNDN); -+ mpfr_set_str (z, "0x8.3ffffffffffe3ffp-14443", 16, MPFR_RNDN); -+ mpfr_set_str (t, "0x8.7ffffffffffc7ffp-14444", 16, MPFR_RNDN); -+ i = mpfr_fma (u, x, y, z, MPFR_RNDN); -+ if (mpfr_cmp (u, t) != 0) -+ { -+ printf ("Wrong result in bug20101018 (a)\n"); -+ printf ("Expected "); -+ mpfr_out_str (stdout, 16, 0, t, MPFR_RNDN); -+ printf ("\nGot "); -+ mpfr_out_str (stdout, 16, 0, u, MPFR_RNDN); -+ printf ("\n"); -+ exit (1); -+ } -+ if (i <= 0) -+ { -+ printf ("Wrong ternary value in bug20101018 (a)\n"); -+ printf ("Expected > 0\n"); -+ printf ("Got %d\n", i); -+ exit (1); -+ } -+ -+ mpfr_set_str (x, "-0xf.fffffffffffffffp-11420", 16, MPFR_RNDN); -+ mpfr_set_str (y, "0xf.fffffffffffffffp+9863", 16, MPFR_RNDN); -+ mpfr_set_str (z, "0x8.fffff80ffffffffp-1551", 16, MPFR_RNDN); -+ mpfr_set_str (t, "0x9.fffff01ffffffffp-1552", 16, MPFR_RNDN); -+ i = mpfr_fma (u, x, y, z, MPFR_RNDN); -+ if (mpfr_cmp (u, t) != 0) -+ { -+ printf ("Wrong result in bug20101018 (b)\n"); -+ printf ("Expected "); -+ mpfr_out_str (stdout, 16, 0, t, MPFR_RNDN); -+ printf ("\nGot "); -+ mpfr_out_str (stdout, 16, 0, u, MPFR_RNDN); -+ printf ("\n"); -+ exit (1); -+ } -+ if (i <= 0) -+ { -+ printf ("Wrong ternary value in bug20101018 (b)\n"); -+ printf ("Expected > 0\n"); -+ printf ("Got %d\n", i); -+ exit (1); -+ } -+ -+ mpfr_set_str (x, "0xf.fffffffffffffffp-2125", 16, MPFR_RNDN); -+ mpfr_set_str (y, "-0xf.fffffffffffffffp-6000", 16, MPFR_RNDN); -+ mpfr_set_str (z, "0x8p-8119", 16, MPFR_RNDN); -+ mpfr_set_str (t, "0x8.000000000000001p-8120", 16, MPFR_RNDN); -+ i = mpfr_fma (u, x, y, z, MPFR_RNDN); -+ if (mpfr_cmp (u, t) != 0) -+ { -+ printf ("Wrong result in bug20101018 (c)\n"); -+ printf ("Expected "); -+ mpfr_out_str (stdout, 16, 0, t, MPFR_RNDN); -+ printf ("\nGot "); -+ mpfr_out_str (stdout, 16, 0, u, MPFR_RNDN); -+ printf ("\n"); -+ exit (1); -+ } -+ if (i <= 0) -+ { -+ printf ("Wrong ternary value in bug20101018 (c)\n"); -+ printf ("Expected > 0\n"); -+ printf ("Got %d\n", i); -+ exit (1); -+ } -+ -+ mpfr_clear (x); -+ mpfr_clear (y); -+ mpfr_clear (z); -+ mpfr_clear (t); -+ mpfr_clear (u); -+} -+ - int - main (int argc, char *argv[]) - { -@@ -345,6 +433,8 @@ - - tests_start_mpfr (); - -+ bug20101018 (); -+ - mpfr_init (x); - mpfr_init (s); - mpfr_init (y); -diff -Naurd mpfr-3.0.0.orig/tests/tsub.c mpfr-3.0.0/tests/tsub.c ---- mpfr-3.0.0.orig/tests/tsub.c 2010-06-10 11:00:13.000000000 +0000 -+++ mpfr-3.0.0/tests/tsub.c 2010-10-21 20:59:32.000000000 +0000 -@@ -201,6 +201,8 @@ - if (mpfr_cmp (z, x)) - { - printf ("Error in mpfr_sub (2)\n"); -+ printf ("Expected "); mpfr_print_binary (x); puts (""); -+ printf ("Got "); mpfr_print_binary (z); puts (""); - exit (1); - } - mpfr_set_str_binary (x, "1.1110111011110001110111011111111111101000011001011100101100101101"); -@@ -478,6 +480,156 @@ - mpfr_clear (u); - } - -+/* Bug found by Jakub Jelinek -+ * http://bugzilla.redhat.com/643657 -+ * https://gforge.inria.fr/tracker/index.php?func=detail&aid=11301 -+ * The consequence can be either an assertion failure (i = 2 in the -+ * testcase below, in debug mode) or an incorrectly rounded value. -+ */ -+static void -+bug20101017 (void) -+{ -+ mpfr_t a, b, c; -+ int inex; -+ int i; -+ -+ mpfr_init2 (a, GMP_NUMB_BITS * 2); -+ mpfr_init2 (b, GMP_NUMB_BITS); -+ mpfr_init2 (c, GMP_NUMB_BITS); -+ -+ /* a = 2^(2N) + k.2^(2N-1) + 2^N and b = 1 -+ with N = GMP_NUMB_BITS and k = 0 or 1. -+ c = a - b should round to the same value as a. */ -+ -+ for (i = 2; i <= 3; i++) -+ { -+ mpfr_set_ui_2exp (a, i, GMP_NUMB_BITS - 1, MPFR_RNDN); -+ mpfr_add_ui (a, a, 1, MPFR_RNDN); -+ mpfr_mul_2ui (a, a, GMP_NUMB_BITS, MPFR_RNDN); -+ mpfr_set_ui (b, 1, MPFR_RNDN); -+ inex = mpfr_sub (c, a, b, MPFR_RNDN); -+ mpfr_set (b, a, MPFR_RNDN); -+ if (! mpfr_equal_p (c, b)) -+ { -+ printf ("Error in bug20101017 for i = %d.\n", i); -+ printf ("Expected "); -+ mpfr_out_str (stdout, 16, 0, b, MPFR_RNDN); -+ putchar ('\n'); -+ printf ("Got "); -+ mpfr_out_str (stdout, 16, 0, c, MPFR_RNDN); -+ putchar ('\n'); -+ exit (1); -+ } -+ if (inex >= 0) -+ { -+ printf ("Error in bug20101017 for i = %d: bad inex value.\n", i); -+ printf ("Expected negative, got %d.\n", inex); -+ exit (1); -+ } -+ } -+ -+ mpfr_set_prec (a, 64); -+ mpfr_set_prec (b, 129); -+ mpfr_set_prec (c, 2); -+ mpfr_set_str_binary (b, "0.100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001E65"); -+ mpfr_set_str_binary (c, "0.10E1"); -+ inex = mpfr_sub (a, b, c, MPFR_RNDN); -+ if (mpfr_cmp_ui_2exp (a, 1, 64) != 0 || inex >= 0) -+ { -+ printf ("Error in mpfr_sub for b-c for b=2^64+1+2^(-64), c=1\n"); -+ printf ("Expected result 2^64 with inex < 0\n"); -+ printf ("Got "); mpfr_print_binary (a); -+ printf (" with inex=%d\n", inex); -+ exit (1); -+ } -+ -+ mpfr_clears (a, b, c, (mpfr_ptr) 0); -+} -+ -+/* hard test of rounding */ -+static void -+check_rounding (void) -+{ -+ mpfr_t a, b, c, res; -+ mpfr_prec_t p; -+ long k, l; -+ int i; -+ -+#define MAXKL (2 * GMP_NUMB_BITS) -+ for (p = MPFR_PREC_MIN; p <= GMP_NUMB_BITS; p++) -+ { -+ mpfr_init2 (a, p); -+ mpfr_init2 (res, p); -+ mpfr_init2 (b, p + 1 + MAXKL); -+ mpfr_init2 (c, MPFR_PREC_MIN); -+ -+ /* b = 2^p + 1 + 2^(-k), c = 2^(-l) */ -+ for (k = 0; k <= MAXKL; k++) -+ for (l = 0; l <= MAXKL; l++) -+ { -+ mpfr_set_ui_2exp (b, 1, p, MPFR_RNDN); -+ mpfr_add_ui (b, b, 1, MPFR_RNDN); -+ mpfr_mul_2ui (b, b, k, MPFR_RNDN); -+ mpfr_add_ui (b, b, 1, MPFR_RNDN); -+ mpfr_div_2ui (b, b, k, MPFR_RNDN); -+ mpfr_set_ui_2exp (c, 1, -l, MPFR_RNDN); -+ i = mpfr_sub (a, b, c, MPFR_RNDN); -+ /* b - c = 2^p + 1 + 2^(-k) - 2^(-l), should be rounded to -+ 2^p for l <= k, and 2^p+2 for l < k */ -+ if (l <= k) -+ { -+ if (mpfr_cmp_ui_2exp (a, 1, p) != 0) -+ { -+ printf ("Wrong result in check_rounding\n"); -+ printf ("p=%lu k=%ld l=%ld\n", p, k, l); -+ printf ("b="); mpfr_print_binary (b); puts (""); -+ printf ("c="); mpfr_print_binary (c); puts (""); -+ printf ("Expected 2^%lu\n", p); -+ printf ("Got "); mpfr_print_binary (a); puts (""); -+ exit (1); -+ } -+ if (i >= 0) -+ { -+ printf ("Wrong ternary value in check_rounding\n"); -+ printf ("p=%lu k=%ld l=%ld\n", p, k, l); -+ printf ("b="); mpfr_print_binary (b); puts (""); -+ printf ("c="); mpfr_print_binary (c); puts (""); -+ printf ("a="); mpfr_print_binary (a); puts (""); -+ printf ("Expected < 0, got %d\n", i); -+ exit (1); -+ } -+ } -+ else /* l < k */ -+ { -+ mpfr_set_ui_2exp (res, 1, p, MPFR_RNDN); -+ mpfr_add_ui (res, res, 2, MPFR_RNDN); -+ if (mpfr_cmp (a, res) != 0) -+ { -+ printf ("Wrong result in check_rounding\n"); -+ printf ("b="); mpfr_print_binary (b); puts (""); -+ printf ("c="); mpfr_print_binary (c); puts (""); -+ printf ("Expected "); mpfr_print_binary (res); puts (""); -+ printf ("Got "); mpfr_print_binary (a); puts (""); -+ exit (1); -+ } -+ if (i <= 0) -+ { -+ printf ("Wrong ternary value in check_rounding\n"); -+ printf ("b="); mpfr_print_binary (b); puts (""); -+ printf ("c="); mpfr_print_binary (c); puts (""); -+ printf ("Expected > 0, got %d\n", i); -+ exit (1); -+ } -+ } -+ } -+ -+ mpfr_clear (a); -+ mpfr_clear (res); -+ mpfr_clear (b); -+ mpfr_clear (c); -+ } -+} -+ - #define TEST_FUNCTION test_sub - #define TWO_ARGS - #define RAND_FUNCTION(x) mpfr_random2(x, MPFR_LIMB_SIZE (x), randlimb () % 100, RANDS) -@@ -491,6 +643,8 @@ - - tests_start_mpfr (); - -+ bug20101017 (); -+ check_rounding (); - check_diverse (); - check_inexact (); - bug_ddefour (); -diff -Naurd mpfr-3.0.0.orig/version.c mpfr-3.0.0/version.c ---- mpfr-3.0.0.orig/version.c 2010-10-21 20:28:38.000000000 +0000 -+++ mpfr-3.0.0/version.c 2010-10-21 20:59:32.000000000 +0000 -@@ -25,5 +25,5 @@ - const char * - mpfr_get_version (void) - { -- return "3.0.0-p5"; -+ return "3.0.0-p6"; - } -diff -Naurd mpfr-3.0.0.orig/PATCHES mpfr-3.0.0/PATCHES ---- mpfr-3.0.0.orig/PATCHES 2010-10-21 21:18:26.000000000 +0000 -+++ mpfr-3.0.0/PATCHES 2010-10-21 21:18:26.000000000 +0000 -@@ -0,0 +1 @@ -+mpfr_set_ld -diff -Naurd mpfr-3.0.0.orig/VERSION mpfr-3.0.0/VERSION ---- mpfr-3.0.0.orig/VERSION 2010-10-21 20:59:32.000000000 +0000 -+++ mpfr-3.0.0/VERSION 2010-10-21 21:18:26.000000000 +0000 -@@ -1 +1 @@ --3.0.0-p6 -+3.0.0-p7 -diff -Naurd mpfr-3.0.0.orig/mpfr.h mpfr-3.0.0/mpfr.h ---- mpfr-3.0.0.orig/mpfr.h 2010-10-21 20:59:32.000000000 +0000 -+++ mpfr-3.0.0/mpfr.h 2010-10-21 21:18:26.000000000 +0000 -@@ -27,7 +27,7 @@ - #define MPFR_VERSION_MAJOR 3 - #define MPFR_VERSION_MINOR 0 - #define MPFR_VERSION_PATCHLEVEL 0 --#define MPFR_VERSION_STRING "3.0.0-p6" -+#define MPFR_VERSION_STRING "3.0.0-p7" - - /* Macros dealing with MPFR VERSION */ - #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c)) -diff -Naurd mpfr-3.0.0.orig/set_ld.c mpfr-3.0.0/set_ld.c ---- mpfr-3.0.0.orig/set_ld.c 2010-06-10 11:00:14.000000000 +0000 -+++ mpfr-3.0.0/set_ld.c 2010-10-21 21:18:26.000000000 +0000 -@@ -102,21 +102,25 @@ - { - x /= div13; /* exact */ - shift_exp += 8192; -+ mpfr_div_2si (t, t, 8192, MPFR_RNDZ); - } - if (ABS (x) >= div12) - { - x /= div12; /* exact */ - shift_exp += 4096; -+ mpfr_div_2si (t, t, 4096, MPFR_RNDZ); - } - if (ABS (x) >= div11) - { - x /= div11; /* exact */ - shift_exp += 2048; -+ mpfr_div_2si (t, t, 2048, MPFR_RNDZ); - } - if (ABS (x) >= div10) - { - x /= div10; /* exact */ - shift_exp += 1024; -+ mpfr_div_2si (t, t, 1024, MPFR_RNDZ); - } - /* warning: we may have DBL_MAX=2^1024*(1-2^(-53)) < x < 2^1024, - therefore we have one extra exponent reduction step */ -@@ -124,9 +128,10 @@ - { - x /= div9; /* exact */ - shift_exp += 512; -+ mpfr_div_2si (t, t, 512, MPFR_RNDZ); - } - } /* Check overflow of double */ -- else -+ else /* no overflow on double */ - { - long double div9, div10, div11; - -@@ -149,29 +154,34 @@ - { - x /= div13; /* exact */ - shift_exp -= 8192; -+ mpfr_mul_2si (t, t, 8192, MPFR_RNDZ); - } - if (ABS (x) <= div12) - { - x /= div12; /* exact */ - shift_exp -= 4096; -+ mpfr_mul_2si (t, t, 4096, MPFR_RNDZ); - } - if (ABS (x) <= div11) - { - x /= div11; /* exact */ - shift_exp -= 2048; -+ mpfr_mul_2si (t, t, 2048, MPFR_RNDZ); - } - if (ABS (x) <= div10) - { - x /= div10; /* exact */ - shift_exp -= 1024; -+ mpfr_mul_2si (t, t, 1024, MPFR_RNDZ); - } - if (ABS(x) <= div9) - { - x /= div9; /* exact */ - shift_exp -= 512; -+ mpfr_mul_2si (t, t, 512, MPFR_RNDZ); - } - } -- else -+ else /* no underflow */ - { - inexact = mpfr_set_d (u, (double) x, MPFR_RNDZ); - MPFR_ASSERTD (inexact == 0); -diff -Naurd mpfr-3.0.0.orig/tests/tset_ld.c mpfr-3.0.0/tests/tset_ld.c ---- mpfr-3.0.0.orig/tests/tset_ld.c 2010-06-10 11:00:13.000000000 +0000 -+++ mpfr-3.0.0/tests/tset_ld.c 2010-10-21 21:18:26.000000000 +0000 -@@ -147,12 +147,39 @@ - test_fixed_bugs (void) - { - mpfr_t x; -- long double d; -+ long double l, m; - - /* bug found by Steve Kargl (2009-03-14) */ - mpfr_init2 (x, 64); - mpfr_set_ui_2exp (x, 1, -16447, MPFR_RNDN); -- d = mpfr_get_ld (x, MPFR_RNDN); /* an assertion failed in init2.c:50 */ -+ mpfr_get_ld (x, MPFR_RNDN); /* an assertion failed in init2.c:50 */ -+ -+ /* bug reported by Jakub Jelinek (2010-10-17) -+ https://gforge.inria.fr/tracker/?func=detail&aid=11300 */ -+ mpfr_set_prec (x, MPFR_LDBL_MANT_DIG); -+ /* l = 0x1.23456789abcdef0123456789abcdp-914L; */ -+ l = 8.215640181713713164092636634579e-276; -+ mpfr_set_ld (x, l, MPFR_RNDN); -+ m = mpfr_get_ld (x, MPFR_RNDN); -+ if (m != l) -+ { -+ printf ("Error in get_ld o set_ld for l=%Le\n", l); -+ printf ("Got m=%Le instead of l\n", m); -+ exit (1); -+ } -+ -+ /* another similar test which failed with extended double precision and the -+ generic code for mpfr_set_ld */ -+ /* l = 0x1.23456789abcdef0123456789abcdp-968L; */ -+ l = 4.560596445887084662336528403703e-292; -+ mpfr_set_ld (x, l, MPFR_RNDN); -+ m = mpfr_get_ld (x, MPFR_RNDN); -+ if (m != l) -+ { -+ printf ("Error in get_ld o set_ld for l=%Le\n", l); -+ printf ("Got m=%Le instead of l\n", m); -+ exit (1); -+ } - - mpfr_clear (x); - } -diff -Naurd mpfr-3.0.0.orig/version.c mpfr-3.0.0/version.c ---- mpfr-3.0.0.orig/version.c 2010-10-21 20:59:32.000000000 +0000 -+++ mpfr-3.0.0/version.c 2010-10-21 21:18:26.000000000 +0000 -@@ -25,5 +25,5 @@ - const char * - mpfr_get_version (void) - { -- return "3.0.0-p6"; -+ return "3.0.0-p7"; - } -diff -Naurd mpfr-3.0.0.orig/PATCHES mpfr-3.0.0/PATCHES ---- mpfr-3.0.0.orig/PATCHES 2010-11-09 15:15:07.000000000 +0000 -+++ mpfr-3.0.0/PATCHES 2010-11-09 15:15:07.000000000 +0000 -@@ -0,0 +1 @@ -+macros -diff -Naurd mpfr-3.0.0.orig/VERSION mpfr-3.0.0/VERSION ---- mpfr-3.0.0.orig/VERSION 2010-10-21 21:18:26.000000000 +0000 -+++ mpfr-3.0.0/VERSION 2010-11-09 15:15:07.000000000 +0000 -@@ -1 +1 @@ --3.0.0-p7 -+3.0.0-p8 -diff -Naurd mpfr-3.0.0.orig/mpfr.h mpfr-3.0.0/mpfr.h ---- mpfr-3.0.0.orig/mpfr.h 2010-10-21 21:18:26.000000000 +0000 -+++ mpfr-3.0.0/mpfr.h 2010-11-09 15:15:07.000000000 +0000 -@@ -27,7 +27,7 @@ - #define MPFR_VERSION_MAJOR 3 - #define MPFR_VERSION_MINOR 0 - #define MPFR_VERSION_PATCHLEVEL 0 --#define MPFR_VERSION_STRING "3.0.0-p7" -+#define MPFR_VERSION_STRING "3.0.0-p8" - - /* Macros dealing with MPFR VERSION */ - #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c)) -@@ -67,6 +67,16 @@ - # define _MPFR_H_HAVE_INTMAX_T 1 - #endif - -+/* Avoid some problems with macro expansion if the user defines macros -+ with the same name as keywords. By convention, identifiers and macro -+ names starting with mpfr_ are reserved by MPFR. */ -+typedef void mpfr_void; -+typedef int mpfr_int; -+typedef unsigned int mpfr_uint; -+typedef long mpfr_long; -+typedef unsigned long mpfr_ulong; -+typedef size_t mpfr_size_t; -+ - /* Definition of rounding modes (DON'T USE MPFR_RNDNA!). - Warning! Changing the contents of this enum should be seen as an - interface change since the old and the new types are not compatible -@@ -136,7 +146,7 @@ - typedef mp_exp_t mpfr_exp_t; - - /* Definition of the standard exponent limits */ --#define MPFR_EMAX_DEFAULT ((mpfr_exp_t) (((unsigned long) 1 << 30) - 1)) -+#define MPFR_EMAX_DEFAULT ((mpfr_exp_t) (((mpfr_ulong) 1 << 30) - 1)) - #define MPFR_EMIN_DEFAULT (-(MPFR_EMAX_DEFAULT)) - - /* Definition of the main structure */ -@@ -725,13 +735,13 @@ - unexpected results with future compilers and aggressive optimisations. - Why not working only with signed types, using INT_MIN and LONG_MIN? */ - #if __GMP_MP_SIZE_T_INT --#define __MPFR_EXP_NAN ((mpfr_exp_t)((~((~(unsigned int)0)>>1))+2)) --#define __MPFR_EXP_ZERO ((mpfr_exp_t)((~((~(unsigned int)0)>>1))+1)) --#define __MPFR_EXP_INF ((mpfr_exp_t)((~((~(unsigned int)0)>>1))+3)) -+#define __MPFR_EXP_NAN ((mpfr_exp_t)((~((~(mpfr_uint)0)>>1))+2)) -+#define __MPFR_EXP_ZERO ((mpfr_exp_t)((~((~(mpfr_uint)0)>>1))+1)) -+#define __MPFR_EXP_INF ((mpfr_exp_t)((~((~(mpfr_uint)0)>>1))+3)) - #else --#define __MPFR_EXP_NAN ((mpfr_exp_t)((~((~(unsigned long)0)>>1))+2)) --#define __MPFR_EXP_ZERO ((mpfr_exp_t)((~((~(unsigned long)0)>>1))+1)) --#define __MPFR_EXP_INF ((mpfr_exp_t)((~((~(unsigned long)0)>>1))+3)) -+#define __MPFR_EXP_NAN ((mpfr_exp_t)((~((~(mpfr_ulong)0)>>1))+2)) -+#define __MPFR_EXP_ZERO ((mpfr_exp_t)((~((~(mpfr_ulong)0)>>1))+1)) -+#define __MPFR_EXP_INF ((mpfr_exp_t)((~((~(mpfr_ulong)0)>>1))+3)) - #endif - - /* Define MPFR_USE_EXTENSION to avoid "gcc -pedantic" warnings. */ -@@ -760,9 +770,9 @@ - #define mpfr_inf_p(_x) ((_x)->_mpfr_exp == __MPFR_EXP_INF) - #define mpfr_zero_p(_x) ((_x)->_mpfr_exp == __MPFR_EXP_ZERO) - #define mpfr_regular_p(_x) ((_x)->_mpfr_exp > __MPFR_EXP_INF) --#define mpfr_sgn(_x) \ -- ((_x)->_mpfr_exp < __MPFR_EXP_INF ? \ -- (mpfr_nan_p (_x) ? mpfr_set_erangeflag () : (void) 0), 0 : \ -+#define mpfr_sgn(_x) \ -+ ((_x)->_mpfr_exp < __MPFR_EXP_INF ? \ -+ (mpfr_nan_p (_x) ? mpfr_set_erangeflag () : (mpfr_void) 0), 0 : \ - MPFR_SIGN (_x)) - - /* Prevent them from using as lvalues */ -@@ -805,7 +815,19 @@ - Moreover casts to unsigned long have been added to avoid warnings in - programs that use MPFR and are compiled with -Wconversion; such casts - are OK since if X is a constant expression, then (unsigned long) X is -- also a constant expression, so that the optimizations still work. */ -+ also a constant expression, so that the optimizations still work. The -+ warnings are probably related to the following two bugs: -+ http://gcc.gnu.org/bugzilla/show_bug.cgi?id=4210 -+ http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38470 (possibly a variant) -+ and the casts could be removed once these bugs are fixed. -+ Casts shouldn't be used on the generic calls (to the ..._2exp functions), -+ where implicit conversions are performed. Indeed, having at least one -+ implicit conversion in the macro allows the compiler to emit diagnostics -+ when normally expected, for instance in the following call: -+ mpfr_set_ui (x, "foo", MPFR_RNDN); -+ If this is not possible (for future macros), one of the tricks described -+ on http://groups.google.com/group/comp.std.c/msg/e92abd24bf9eaf7b could -+ be used. */ - #if defined (__GNUC__) && !defined(__ICC) && !defined(__cplusplus) - #if (__GNUC__ >= 2) - #undef mpfr_cmp_ui -@@ -813,45 +835,45 @@ - But warning! mpfr_sgn is specified as a macro in the API, thus the macro - mustn't be used if side effects are possible, like here. */ - #define mpfr_cmp_ui(_f,_u) \ -- (__builtin_constant_p (_u) && (unsigned long) (_u) == 0 ? \ -+ (__builtin_constant_p (_u) && (mpfr_ulong) (_u) == 0 ? \ - (mpfr_sgn) (_f) : \ -- mpfr_cmp_ui_2exp ((_f), (unsigned long) (_u), 0)) -+ mpfr_cmp_ui_2exp ((_f), (_u), 0)) - #undef mpfr_cmp_si --#define mpfr_cmp_si(_f,_s) \ -- (__builtin_constant_p (_s) && (long) (_s) >= 0 ? \ -- mpfr_cmp_ui ((_f), (unsigned long) (long) (_s)) : \ -- mpfr_cmp_si_2exp ((_f), (long) (_s), 0)) -+#define mpfr_cmp_si(_f,_s) \ -+ (__builtin_constant_p (_s) && (mpfr_long) (_s) >= 0 ? \ -+ mpfr_cmp_ui ((_f), (mpfr_ulong) (mpfr_long) (_s)) : \ -+ mpfr_cmp_si_2exp ((_f), (_s), 0)) - #if __GNUC__ > 2 || __GNUC_MINOR__ >= 95 - #undef mpfr_set_ui - #define mpfr_set_ui(_f,_u,_r) \ -- (__builtin_constant_p (_u) && (unsigned long) (_u) == 0 ? \ -+ (__builtin_constant_p (_u) && (mpfr_ulong) (_u) == 0 ? \ - __extension__ ({ \ - mpfr_ptr _p = (_f); \ - _p->_mpfr_sign = 1; \ - _p->_mpfr_exp = __MPFR_EXP_ZERO; \ -- (void) (_r); 0; }) : \ -- mpfr_set_ui_2exp ((_f), (unsigned long) (_u), 0, (_r))) -+ (mpfr_void) (_r); 0; }) : \ -+ mpfr_set_ui_2exp ((_f), (_u), 0, (_r))) - #endif - #undef mpfr_set_si - #define mpfr_set_si(_f,_s,_r) \ -- (__builtin_constant_p (_s) && (long) (_s) >= 0 ? \ -- mpfr_set_ui ((_f), (unsigned long) (long) (_s), (_r)) : \ -- mpfr_set_si_2exp ((_f), (long) (_s), 0, (_r))) -+ (__builtin_constant_p (_s) && (mpfr_long) (_s) >= 0 ? \ -+ mpfr_set_ui ((_f), (mpfr_ulong) (mpfr_long) (_s), (_r)) : \ -+ mpfr_set_si_2exp ((_f), (_s), 0, (_r))) - #endif - #endif - - /* Macro version of mpfr_stack interface for fast access */ --#define mpfr_custom_get_size(p) ((size_t) \ -+#define mpfr_custom_get_size(p) ((mpfr_size_t) \ - (((p)+GMP_NUMB_BITS-1)/GMP_NUMB_BITS*sizeof (mp_limb_t))) - #define mpfr_custom_init(m,p) do {} while (0) --#define mpfr_custom_get_significand(x) ((void*)((x)->_mpfr_d)) -+#define mpfr_custom_get_significand(x) ((mpfr_void*)((x)->_mpfr_d)) - #define mpfr_custom_get_exp(x) ((x)->_mpfr_exp) - #define mpfr_custom_move(x,m) do { ((x)->_mpfr_d = (mp_limb_t*)(m)); } while (0) - #define mpfr_custom_init_set(x,k,e,p,m) do { \ - mpfr_ptr _x = (x); \ - mpfr_exp_t _e; \ - mpfr_kind_t _t; \ -- int _s, _k; \ -+ mpfr_int _s, _k; \ - _k = (k); \ - if (_k >= 0) { \ - _t = (mpfr_kind_t) _k; \ -@@ -868,11 +890,13 @@ - _x->_mpfr_exp = _e; \ - _x->_mpfr_d = (mp_limb_t*) (m); \ - } while (0) --#define mpfr_custom_get_kind(x) \ -- ( (x)->_mpfr_exp > __MPFR_EXP_INF ? (int)MPFR_REGULAR_KIND*MPFR_SIGN (x) \ -- : (x)->_mpfr_exp == __MPFR_EXP_INF ? (int)MPFR_INF_KIND*MPFR_SIGN (x) \ -- : (x)->_mpfr_exp == __MPFR_EXP_NAN ? (int)MPFR_NAN_KIND \ -- : (int) MPFR_ZERO_KIND * MPFR_SIGN (x) ) -+#define mpfr_custom_get_kind(x) \ -+ ( (x)->_mpfr_exp > __MPFR_EXP_INF ? \ -+ (mpfr_int) MPFR_REGULAR_KIND * MPFR_SIGN (x) \ -+ : (x)->_mpfr_exp == __MPFR_EXP_INF ? \ -+ (mpfr_int) MPFR_INF_KIND * MPFR_SIGN (x) \ -+ : (x)->_mpfr_exp == __MPFR_EXP_NAN ? (mpfr_int) MPFR_NAN_KIND \ -+ : (mpfr_int) MPFR_ZERO_KIND * MPFR_SIGN (x) ) - - - #endif /* MPFR_USE_NO_MACRO */ -diff -Naurd mpfr-3.0.0.orig/version.c mpfr-3.0.0/version.c ---- mpfr-3.0.0.orig/version.c 2010-10-21 21:18:26.000000000 +0000 -+++ mpfr-3.0.0/version.c 2010-11-09 15:15:07.000000000 +0000 -@@ -25,5 +25,5 @@ - const char * - mpfr_get_version (void) - { -- return "3.0.0-p7"; -+ return "3.0.0-p8"; - } From gerrit at coreboot.org Tue Nov 1 22:42:24 2011 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Tue, 1 Nov 2011 22:42:24 +0100 Subject: [coreboot] Patch set updated for coreboot: aa1faf7 Add Python scripting to GDB. References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/153 -gerrit commit aa1faf7d39989817bb30b161d692647c8deac36f Author: Stefan Reinauer Date: Tue Nov 1 21:43:50 2011 +0100 Add Python scripting to GDB. This allows GDB to run Python scripts. The Python build is dependant on the GDB build flag. Changes by Stefan Reinauer: - update to latest buildgcc script - disable GDB per default - disable python scripting, if GDB is not enabled - bump version number to 1.06 Change-Id: Ie7fc8706deec41c804870415d3c79d225c98cd31 Signed-off-by: Marc Jones --- util/crossgcc/buildgcc | 153 +++++++++++++++++----- util/crossgcc/patches/gdb-7.3.1_pythonhome.patch | 27 ++++ 2 files changed, 148 insertions(+), 32 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index ee2a81b..b0918c0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -17,11 +17,11 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA # -CROSSGCC_DATE="October 10th, 2011" -CROSSGCC_VERSION="1.05" +CROSSGCC_DATE="November 1st, 2011" +CROSSGCC_VERSION="1.06" # default settings TARGETDIR=`pwd`/xgcc @@ -41,6 +41,8 @@ W32API_VERSION=3.17-2 W32API_VERSION_SHORT=3.17 MINGWRT_VERSION=3.18 IASL_VERSION=20110922 +PYTHON_VERSION=2.7.2 +EXPAT_VERSION=2.0.1 # archive locations GMP_ARCHIVE="ftp://ftp.gmplib.org/pub/gmp-${GMP_VERSION}/gmp-${GMP_VERSION}.tar.bz2" @@ -53,6 +55,8 @@ GDB_ARCHIVE="http://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.bz2" W32API_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW/BaseSystem/RuntimeLibrary/Win32-API/w32api-${W32API_VERSION_SHORT}/w32api-${W32API_VERSION}-mingw32-src.tar.lzma" MINGWRT_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW/BaseSystem/RuntimeLibrary/MinGW-RT/mingwrt-${MINGWRT_VERSION}/mingwrt-${MINGWRT_VERSION}-mingw32-src.tar.gz" IASL_ARCHIVE="http://www.acpica.org/download/acpica-unix-${IASL_VERSION}.tar.gz" +PYTHON_ARCHIVE="http://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.bz2" +EXPAT_ARCHIVE="http://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.gz" GMP_DIR="gmp-${GMP_VERSION}" MPFR_DIR="mpfr-${MPFR_VERSION}" @@ -64,9 +68,12 @@ GDB_DIR="gdb-${GDB_VERSION}" W32API_DIR="w32api-${W32API_VERSION}-mingw32" MINGWRT_DIR="mingwrt-${MINGWRT_VERSION}-mingw32" IASL_DIR="acpica-unix-${IASL_VERSION}" +PYTHON_DIR="Python-${PYTHON_VERSION}" +EXPAT_DIR="expat-${EXPAT_VERSION}" SAVETEMPS=0 -SKIPGDB=0 +SKIPGDB=1 +SKIPPYTHON=1 red='\033[0;31m' RED='\033[1;31m' @@ -85,7 +92,8 @@ searchgnu() # or no output if no GNU version was found for i in "$1" "g$1" "gnu$1"; do if test -x "`which $i 2>/dev/null`"; then - if test `$i --version 2>/dev/null |grep -c GNU` -gt 0; then + if test `$i --version 2>/dev/null |grep -c GNU` \ + -gt 0; then echo $i return fi @@ -102,13 +110,14 @@ MAKE=`searchgnu make` || exit $? cleanup() { printf "Cleaning up temporary files... " - rm -rf build-* combined gcc-* gmp-* mpfr-* mpc-* libelf-* binutils-* gdb-* w32api-* mingwrt-* acpica-* + rm -rf build-* combined gcc-* gmp-* mpfr-* mpc-* libelf-* binutils-* + rm -rf gdb-* w32api-* mingwrt-* acpica-* python-* expat-* printf "${green}ok${NC}\n" } myhelp() { - printf "Usage: $0 [-V] [-c] [-p ] [-d ] [-D ] [-G]\n" + printf "Usage: $0 [-V] [-c] [-p ] [-d ] [-D ] [-G] [-S]\n" printf " $0 [-V|--version]\n" printf " $0 [-h|--help]\n\n" @@ -123,8 +132,9 @@ myhelp() printf " [-d|--directory ] target directory to install cross compiler to\n" printf " (defaults to $TARGETDIR)\n\n" printf " [-D|--destdir ] destination directory to install cross compiler to\n" - printf " (for RPM builds, default unset)\n\n" - printf " [-G|--skip-gdb] don't build GNU debugger\n" + printf " (for RPM builds, default unset)\n" + printf " [-G|--gdb] build GNU debugger\n" + printf " [-S|--scripting] build scripting support for GDB\n\n" } myversion() @@ -180,7 +190,8 @@ while true ; do -p|--platform) shift; TARGETARCH="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;; -j|--jobs) shift; JOBS="-j $1"; shift;; - -G|--skip-gdb) shift; SKIPGDB=1;; + -G|--gdb) shift; SKIPGDB=0;; + -S|--scripting) shift; SKIPPYTHON=0;; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;; @@ -188,10 +199,20 @@ while true ; do done GDB_PACKAGE="GDB" +PYTHON_PACKAGE="PYTHON" +EXPAT_PACKAGE="EXPAT" if [ $SKIPGDB -eq 1 ]; then printf "Will skip GDB ... ${green}ok${NC}\n" GDB_ARCHIVE="" GDB_PACKAGE="" + if [ $SKIPPYTHON -eq 0 ]; then + printf "Python scripting needs GDB ... disabling ... ${green}ok${NC}\n" + SKIPPYTHON=1 + fi +fi +if [ $SKIPPYTHON -eq 1 ]; then + PYTHON_PACKAGE="" + EXPAT_PACKAGE="" fi MINGW_ARCHIVES="" @@ -223,7 +244,9 @@ fi printf "Downloading tar balls ... \n" mkdir -p tarballs -for ARCHIVE in $GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $MINGW_ARCHIVES $IASL_ARCHIVE; do +for ARCHIVE in $GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE \ + $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $MINGW_ARCHIVES \ + $IASL_ARCHIVE $PYTHON_ARCHIVE $EXPAT_ARCHIVE; do FILE=`basename $ARCHIVE` printf " * $FILE " test -f tarballs/$FILE && printf "(cached)" || ( @@ -231,7 +254,8 @@ for ARCHIVE in $GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE $GCC_ARCH cd tarballs wget -q $ARCHIVE ) - test -f tarballs/$FILE || printf "\n${RED}Failed to download $FILE.${red}\n" + test -f tarballs/$FILE || \ + printf "\n${RED}Failed to download $FILE.${red}\n" test -f tarballs/$FILE || exit 1 printf "\n" done @@ -244,7 +268,8 @@ if [ "$TARGETARCH" = "i386-mingw32" ]; then fi printf "Unpacking and patching ... \n" -for PACKAGE in GMP MPFR MPC LIBELF GCC BINUTILS $GDB_PACKAGE $MINGW_PACKAGES IASL; do +for PACKAGE in GMP MPFR MPC LIBELF GCC BINUTILS $PYTHON_PACKAGE \ + $EXPAT_PACKAGE $GDB_PACKAGE $MINGW_PACKAGES IASL; do archive=$PACKAGE"_ARCHIVE" archive="`eval echo '$'$archive`" dir=$PACKAGE"_DIR" @@ -260,7 +285,8 @@ for PACKAGE in GMP MPFR MPC LIBELF GCC BINUTILS $GDB_PACKAGE $MINGW_PACKAGES IAS for patch in patches/${dir}_*.patch; do test -r $patch || continue printf " o `basename $patch`\n" - $PATCH -s -N -p0 < `echo $patch` + $PATCH -s -N -p0 < `echo $patch` || \ + printf "\n${RED}Failed $patch.${red}\n" done ) done @@ -269,7 +295,8 @@ printf "${green}ok${NC}\n" if [ "$TARGETARCH" = "i386-mingw32" ]; then mkdir -p $TARGETDIR/i386-mingw32/sys-include - mv $MINGWRT_DIR/include/* $W32API_DIR/include/* $TARGETDIR/i386-mingw32/sys-include + mv $MINGWRT_DIR/include/* $W32API_DIR/include/* \ + $TARGETDIR/i386-mingw32/sys-include fi CC=cc @@ -296,7 +323,8 @@ if [ `uname` = "Darwin" ]; then fi fi -mkdir -p build-gmp build-mpfr build-mpc build-libelf build-binutils build-gcc +mkdir -p build-gmp build-mpfr build-mpc build-libelf build-binutils \ + build-gcc build-python build-expat if [ $SKIPGDB -eq 0 ]; then mkdir -p build-gdb fi @@ -313,7 +341,8 @@ printf "Building GMP ${GMP_VERSION} ... " $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) > build-gmp/crossgcc-build.log 2>&1 -test -r build-gmp/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok${NC}\n" +test -r build-gmp/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" test -r build-gmp/.failed && exit 1 fi @@ -337,7 +366,8 @@ printf "Building MPFR ${MPFR_VERSION} ... " rm -f .failed ../${MPFR_DIR}/configure --disable-shared --prefix=$TARGETDIR \ --infodir=$TARGETDIR/info \ - --with-gmp=$DESTDIR$TARGETDIR CFLAGS="$HOSTCFLAGS" || touch .failed + --with-gmp=$DESTDIR$TARGETDIR CFLAGS="$HOSTCFLAGS" || \ + touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -348,7 +378,8 @@ printf "Building MPFR ${MPFR_VERSION} ... " if [ ! -f .failed ]; then touch .success; fi ) > build-mpfr/crossgcc-build.log 2>&1 -test -r build-mpfr/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok${NC}\n" +test -r build-mpfr/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" test -r build-mpfr/.failed && exit 1 fi @@ -362,13 +393,15 @@ printf "Building MPC ${MPC_VERSION} ... " rm -f .failed ../${MPC_DIR}/configure --disable-shared --prefix=$TARGETDIR \ --infodir=$TARGETDIR/info --with-mpfr=$DESTDIR$TARGETDIR \ - --with-gmp=$DESTDIR$TARGETDIR CFLAGS="$HOSTCFLAGS" || touch .failed + --with-gmp=$DESTDIR$TARGETDIR CFLAGS="$HOSTCFLAGS" || \ + touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) > build-mpc/crossgcc-build.log 2>&1 -test -r build-mpc/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok${NC}\n" +test -r build-mpc/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" test -r build-mpc/.failed && exit 1 fi @@ -380,14 +413,16 @@ printf "Building libelf ${LIBELF_VERSION} ... " cd build-libelf rm -f .failed echo "$HOSTCFLAGS" - CFLAGS="$HOSTCFLAGS" libelf_cv_elf_h_works=no ../${LIBELF_DIR}/configure --disable-shared --prefix=$TARGETDIR \ + CFLAGS="$HOSTCFLAGS" libelf_cv_elf_h_works=no \ + ../${LIBELF_DIR}/configure --disable-shared --prefix=$TARGETDIR \ --infodir=$TARGETDIR/info CFLAGS="$HOSTCFLAGS" || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) > build-libelf/crossgcc-build.log 2>&1 -test -r build-libelf/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok${NC}\n" +test -r build-libelf/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" test -r build-libelf/.failed && exit 1 fi @@ -404,14 +439,15 @@ printf "Building binutils ${BINUTILS_VERSION} ... " # Now build binutils cd build-binutils rm -f .failed - ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR --target=${TARGETARCH} \ - --disable-werror --disable-nls $USE_GOLD \ - CFLAGS="$HOSTCFLAGS" || touch .failed + ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR \ + --target=${TARGETARCH} --disable-werror --disable-nls \ + $USE_GOLD CFLAGS="$HOSTCFLAGS" || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) > build-binutils/crossgcc-build.log 2>&1 -test -r build-binutils/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok${NC}\n" +test -r build-binutils/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" test -r build-binutils/.failed && exit 1 fi @@ -456,10 +492,55 @@ printf "Building GCC ${GCC_VERSION} ... " $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) > build-gcc/crossgcc-build.log 2>&1 -test -r build-gcc/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok${NC}\n" +test -r build-gcc/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" test -r build-gcc/.failed && exit 1 fi +if [ -f build-expat/.success ]; then + printf "Skipping Expat as it is already built\n" +elif [ $SKIPGDB -eq 1 ]; then + printf "Skipping Expat as requested by command line (skip GDB)\n" +else +printf "Building Expat ${EXPAT_VERSION} ... " +( + cd build-expat + export PATH=$PATH:$DESTDIR$TARGETDIR/bin + rm -f .failed + CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ + --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed + $MAKE || touch .failed + $MAKE install DESTDIR=$DESTDIR || touch .failed + if [ ! -f .failed ]; then touch .success; fi +) &> build-expat/crossgcc-build.log +test -r build-expat/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" +test -r build-expat/.failed && exit 1 +fi + + +if [ -f build-python/.success ]; then + printf "Skipping Python as it is already built\n" +elif [ $SKIPGDB -eq 1 ]; then + printf "Skipping Python as requested by command line (skip GDB)\n" +else +printf "Building Python ${PYTHON_VERSION} ... " +( + cd build-python + export PATH=$PATH:$DESTDIR$TARGETDIR/bin + rm -f .failed + CFLAGS="$HOSTCFLAGS" ../${PYTHON_DIR}/configure --prefix=$TARGETDIR \ + --target=${TARGETARCH} || touch .failed + $MAKE $JOBS || touch .failed + $MAKE install DESTDIR=$DESTDIR || touch .failed + if [ ! -f .failed ]; then touch .success; fi +) &> build-gdb/crossgcc-build.log +test -r build-python/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" +test -r build-python/.failed && exit 1 +fi + + if [ -f build-gdb/.success ]; then printf "Skipping GDB as it is already built\n" elif [ $SKIPGDB -eq 1 ]; then @@ -469,14 +550,19 @@ printf "Building GDB ${GDB_VERSION} ... " ( cd build-gdb export PATH=$PATH:$DESTDIR$TARGETDIR/bin + export PYTHONHOME=$DESTDIR$TARGETDIR rm -f .failed - CFLAGS="$HOSTCFLAGS" ../gdb-${GDB_VERSION}/configure --prefix=$TARGETDIR --target=${TARGETARCH} \ - --without-python --disable-werror --disable-nls + LDFLAGS="-Wl,-rpath,\$\$ORIGIN/../lib/ -L$DESTDIR$TARGETDIR/lib \ + -lpthread -ldl -lutil" \ + CFLAGS="$HOSTCFLAGS -I$DESTDIR$TARGETDIR/include" \ + ../gdb-${GDB_VERSION}/configure --prefix=$TARGETDIR \ + --target=${TARGETARCH} --disable-werror --disable-nls $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) > build-gdb/crossgcc-build.log 2>&1 -test -r build-gdb/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok${NC}\n" +test -r build-gdb/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" test -r build-gdb/.failed && exit 1 fi @@ -494,7 +580,8 @@ printf "Building IASL ${IASL_VERSION} ... " cp iasl $DESTDIR$TARGETDIR/bin || touch .failed if [ ! -f .failed ]; then touch .success; fi ) > $IASL_DIR/compiler/crossgcc-build.log 2>&1 -test -r $IASL_DIR/compiler/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok${NC}\n" +test -r $IASL_DIR/compiler/.failed && printf "${RED}failed${NC}\n" || \ + printf "${green}ok${NC}\n" test -r $IASL_DIR/compiler/.failed && exit 1 fi @@ -507,6 +594,8 @@ if [ $SAVETEMPS -eq 0 ]; then rm -rf ${BINUTILS_DIR} build-binutils rm -rf ${GCC_DIR} build-gcc rm -rf ${GDB_DIR} build-gdb + rm -rf ${EXPAT_DIR} build-expat + rm -rf ${PYTHON_DIR} build-python rm -rf ${IASL_DIR} printf "${green}ok${NC}\n" else diff --git a/util/crossgcc/patches/gdb-7.3.1_pythonhome.patch b/util/crossgcc/patches/gdb-7.3.1_pythonhome.patch new file mode 100644 index 0000000..90da2d9 --- /dev/null +++ b/util/crossgcc/patches/gdb-7.3.1_pythonhome.patch @@ -0,0 +1,27 @@ +diff -ur gdb-7.3.1.orig/gdb/python/python.c gdb-7.3.1/gdb/python/python.c +--- gdb-7.3.1.orig/gdb/python/python.c 2011-07-02 21:33:10.000000000 +0200 ++++ gdb-7.3.1/gdb/python/python.c 2011-11-01 21:07:25.000000000 +0100 +@@ -33,6 +33,7 @@ + #include "python.h" + + #include ++#include + + /* True if we should print the stack when catching a Python error, + false otherwise. */ +@@ -1010,6 +1011,15 @@ + SLASH_STRING, "python", NULL)); + #endif + ++ char readlinkbuffer[BUFSIZ]; ++ int readlinks = readlink("/proc/self/exe", readlinkbuffer, BUFSIZ - 1); ++ readlinkbuffer[readlinks] = 0; ++ char *executeablepath = dirname(readlinkbuffer); ++ char *pythonhome = malloc(strlen(executeablepath) + strlen("/../") + 2); ++ strcpy(pythonhome, executeablepath); ++ strcat(pythonhome, "/../"); ++ setenv("PYTHONHOME", pythonhome, 1); ++ + Py_Initialize (); + PyEval_InitThreads (); + From gerrit at coreboot.org Tue Nov 1 23:23:04 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 1 Nov 2011 23:23:04 +0100 Subject: [coreboot] Patch merged into coreboot/master: aa1faf7 Add Python scripting to GDB. References: Message-ID: the following patch was just integrated into master: commit aa1faf7d39989817bb30b161d692647c8deac36f Author: Stefan Reinauer Date: Tue Nov 1 21:43:50 2011 +0100 Add Python scripting to GDB. This allows GDB to run Python scripts. The Python build is dependant on the GDB build flag. Changes by Stefan Reinauer: - update to latest buildgcc script - disable GDB per default - disable python scripting, if GDB is not enabled - bump version number to 1.06 Change-Id: Ie7fc8706deec41c804870415d3c79d225c98cd31 Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Nov 1 23:08:24 2011, giving +1 Reviewed-By: Stefan Reinauer at Tue Nov 1 22:42:55 2011, giving +2 See http://review.coreboot.org/153 for details. -gerrit From wangqingpei at gmail.com Wed Nov 2 04:33:54 2011 From: wangqingpei at gmail.com (QingPei Wang) Date: Wed, 2 Nov 2011 11:33:54 +0800 Subject: [coreboot] Coreboot and Epia M-II In-Reply-To: <4EB047B7.5000907@e4L.es> References: <4EB047B7.5000907@e4L.es> Message-ID: hi elisenda, how did you build the seabios? what do you mean by "attached a bootorder file with cbfstool"? the log shows that the payload could not be executed correctly. Best wishes QingPei Wang Phone: 86+018930528086 On Wed, Nov 2, 2011 at 3:25 AM, Elisenda Cuadros wrote: > Hello, > > First of all I am new to the list. Congratulations to all developers for > this great work. > > I have an Epia M-II and I want to install coreboot on it. This board is > supported, great news!. > > I extracted the vga rom with bios_extract (CLE1622A.rom) and I put it > inside menuconfig (pci 1106,3122). > > I built Seabios with Coreboot and attached a bootorder file with cbfstool. > > When I try boot the board with the resulting rom it seems like it?s in a > loop. The VGA output is not good. I am not able to view any payload > messages. > > I am using coreboot v4 from git. > > Because of it is my first experience with coreboot I don?t have any ideas > for what is causing of the problem. I attach you it if you want to take a > look. > > Thanks in advance. > > Best regards, > > Elisenda > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: From lists at e4L.es Wed Nov 2 07:29:34 2011 From: lists at e4L.es (Elisenda Cuadros) Date: Wed, 02 Nov 2011 07:29:34 +0100 Subject: [coreboot] Coreboot and Epia M-II In-Reply-To: References: <4EB047B7.5000907@e4L.es> Message-ID: <4EB0E34E.7060909@e4L.es> Hello QingPei, I built seabios (stable) from menuconfig. After reading the documentation I thought I have to add a bootorder file for Seabios. I wrote a file named "mybootlist.txt" and I added it to coreboot.rom with the following command: cbfstool coreboot.rom add mybootlist.txt bootorder raw Thank you very much. Regards, Elisenda On 02/11/2011 4:33, QingPei Wang wrote: > hi elisenda, > how did you build the seabios? what do you mean by "attached a > bootorder file with cbfstool"? > the log shows that the payload could not be executed correctly. > > > > Best wishes > QingPei Wang > Phone: 86+018930528086 -------------- next part -------------- An HTML attachment was scrubbed... URL: From wangqingpei at gmail.com Wed Nov 2 07:55:47 2011 From: wangqingpei at gmail.com (QingPei Wang) Date: Wed, 2 Nov 2011 14:55:47 +0800 Subject: [coreboot] Coreboot and Epia M-II In-Reply-To: <4EB0E34E.7060909@e4L.es> References: <4EB047B7.5000907@e4L.es> <4EB0E34E.7060909@e4L.es> Message-ID: what's the structure of cbfs? how about the output of command: ./build/cbfstool coreboot.rom print ? Best wishes QingPei Wang Phone: 86+018930528086 On Wed, Nov 2, 2011 at 2:29 PM, Elisenda Cuadros wrote: > bootorder -------------- next part -------------- An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Wed Nov 2 09:32:48 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:48 +0100 Subject: [coreboot] New patch to review for coreboot: 2624076 in vt8237r_enable(), write function enables only to ISA bridge config space References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/368 -gerrit commit 26240769d6dac8bc6606e839daafbabd06474a0b Author: Florian Zumbiehl Date: Tue Nov 1 20:16:16 2011 +0100 in vt8237r_enable(), write function enables only to ISA bridge config space vt8237r_enable() so far wrote the function enable values to the same offset in the config space of every one of the vt8237's functions, even though the register is located in the ISA bridge only. Change-Id: I639586dc238132f5b8d2f320b794948718281b9c Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/vt8237r.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 5ba3815..a0aafa7 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -69,8 +69,10 @@ static void vt8237r_enable(struct device *dev) struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; - pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); - pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == PCI_DEVFN(0x11,0)) { + pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); + pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + } /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ } From gerrit at coreboot.org Wed Nov 2 09:32:49 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:49 +0100 Subject: [coreboot] New patch to review for coreboot: f07282e don't scan beyond end of CBFS References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/369 -gerrit commit f07282efab87037a54cf0f48c0ab835cbbd39efe Author: Florian Zumbiehl Date: Tue Nov 1 20:17:11 2011 +0100 don't scan beyond end of CBFS Change-Id: I66e535f77e513dbfa5fc906ecf288193af78ae62 Signed-off-by: Florian Zumbiehl --- payloads/libpayload/libcbfs/cbfs_core.c | 3 ++- src/lib/cbfs_core.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 596fa3f..4bf755b 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -97,6 +97,7 @@ struct cbfs_file *cbfs_find(const char *name) data = (void*)phys_to_virt(romstart()) + ntohl(header->offset); dataend = (void*)phys_to_virt(romstart()) + ntohl(header->romsize); } + dataend -= ntohl(header->bootblocksize); int align = ntohl(header->align); @@ -106,7 +107,7 @@ struct cbfs_file *cbfs_find(const char *name) if (memcmp(CBFS_FILE_MAGIC, file->magic, strlen(CBFS_FILE_MAGIC)) != 0) { // no file header found. corruption? // proceed in aligned steps to resynchronize - LOG("No file header found at %p, searching for header\n", data); + LOG("ERROR: No file header found at %p, attempting to recover by searching for header\n", data); data = phys_to_virt(CBFS_ALIGN_UP(virt_to_phys(data), align)); continue; } diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 596fa3f..4bf755b 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -97,6 +97,7 @@ struct cbfs_file *cbfs_find(const char *name) data = (void*)phys_to_virt(romstart()) + ntohl(header->offset); dataend = (void*)phys_to_virt(romstart()) + ntohl(header->romsize); } + dataend -= ntohl(header->bootblocksize); int align = ntohl(header->align); @@ -106,7 +107,7 @@ struct cbfs_file *cbfs_find(const char *name) if (memcmp(CBFS_FILE_MAGIC, file->magic, strlen(CBFS_FILE_MAGIC)) != 0) { // no file header found. corruption? // proceed in aligned steps to resynchronize - LOG("No file header found at %p, searching for header\n", data); + LOG("ERROR: No file header found at %p, attempting to recover by searching for header\n", data); data = phys_to_virt(CBFS_ALIGN_UP(virt_to_phys(data), align)); continue; } From gerrit at coreboot.org Wed Nov 2 09:32:49 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:49 +0100 Subject: [coreboot] New patch to review for coreboot: e47de27 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/370 -gerrit commit e47de274deb976f8953101d5894910a8bf1956ab Author: Florian Zumbiehl Date: Tue Nov 1 20:17:12 2011 +0100 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit_f.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 319293b..dc3addb 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i 18, /* *Supported CAS Latencies */ 9, /* *Cycle time at highest CAS Latency CL=X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ - 26, /* *Cycle time at CAS Latency (CLX - 2) */ + 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; u8 common_cl; From gerrit at coreboot.org Wed Nov 2 09:32:50 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:50 +0100 Subject: [coreboot] New patch to review for coreboot: 0d22c91 simplify IDE cable detection for Asus M2V References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/371 -gerrit commit 0d22c9143f78aad039a364b15e651baf98e37a2f Author: Florian Zumbiehl Date: Tue Nov 1 20:17:13 2011 +0100 simplify IDE cable detection for Asus M2V Change-Id: If8e4dcf405e24b744ac34f581c5609fcce96fd07 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/m2v/mainboard.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c index 76d3cf6..2f20fe0 100644 --- a/src/mainboard/asus/m2v/mainboard.c +++ b/src/mainboard/asus/m2v/mainboard.c @@ -37,10 +37,9 @@ u32 vt8237_ide_80pin_detect(struct device *dev) if (!lpc_dev) return 0; - acpi_io_base = pci_read_config16(lpc_dev, 0x88); - if (!acpi_io_base || (acpi_io_base & ~1) == 0) + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) return 0; - acpi_io_base &= ~1; gpio_in = inl(acpi_io_base + 0x48); /* bit 9 for primary port, clear if unconnected or 80-pin cable */ @@ -49,9 +48,9 @@ u32 vt8237_ide_80pin_detect(struct device *dev) res |= gpio_in & (1<<4) ? 0 : VT8237R_IDE1_80PIN_CABLE; printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", - gpio_in & (1<<9) ? 40 : 80); + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", - gpio_in & (1<<4) ? 40 : 80); + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); return res; } From gerrit at coreboot.org Wed Nov 2 09:32:51 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:51 +0100 Subject: [coreboot] New patch to review for coreboot: c77d232 add support for reading from SMBus with vt8237 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/372 -gerrit commit c77d2321f5dd78f70b591c995aeb28beac45c2b3 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:13 2011 +0100 add support for reading from SMBus with vt8237 Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/early_smbus.c | 31 +++++++++++++++++++--------- src/southbridge/via/vt8237r/vt8237r.h | 1 + 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index a298e84..0caf93d 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -87,17 +87,12 @@ static void smbus_reset(void) PRINT_DEBUG("\n"); } -/** - * Read a byte from the SMBus. - * - * @param dimm The address location of the DIMM on the SMBus. - * @param offset The offset the data is located at. - */ -u8 smbus_read_byte(u8 dimm, u8 offset) +static u8 smbus_transaction(u8 dimm, u8 offset, int data) { u8 val; - PRINT_DEBUG("DIMM "); + PRINT_DEBUG((data < 0) ? "RD: " : "WR: "); + PRINT_DEBUG("ADDR "); PRINT_DEBUG_HEX16(dimm); PRINT_DEBUG(" OFFSET "); PRINT_DEBUG_HEX16(offset); @@ -106,13 +101,13 @@ u8 smbus_read_byte(u8 dimm, u8 offset) smbus_reset(); /* Clear host data port. */ - outb(0x00, SMBHSTDAT0); + outb((data < 0) ? 0x00 : data, SMBHSTDAT0); SMBUS_DELAY(); smbus_wait_until_ready(); /* Actual addr to reg format. */ dimm = (dimm << 1); - dimm |= 1; + dimm |= (data < 0); outb(dimm, SMBXMITADD); outb(offset, SMBHSTCMD); @@ -132,6 +127,22 @@ u8 smbus_read_byte(u8 dimm, u8 offset) return val; } +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 smbus_read_byte(u8 dimm, u8 offset) +{ + return smbus_transaction(dimm, offset, -1); +} + +void smbus_write_byte(u8 dimm, u8 offset, u8 data) +{ + smbus_transaction(dimm, offset, data); +} + #define PSONREADY_TIMEOUT 0x7fffffff static device_t get_vt8237_lpc(void) diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 94b1840..9d5a1fc 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -148,6 +148,7 @@ __attribute__ ((packed)) #ifdef __PRE_RAM__ #ifndef __ROMCC__ u8 smbus_read_byte(u8 dimm, u8 offset); +void smbus_write_byte(u8 dimm, u8 offset, u8 data); void enable_smbus(void); void smbus_fixup(const struct mem_controller *ctrl); // these are in vt8237_early_smbus.c - do they really belong there? From gerrit at coreboot.org Wed Nov 2 09:32:52 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:52 +0100 Subject: [coreboot] New patch to review for coreboot: 309034f support for different location of HT registers in old version of K8T800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/373 -gerrit commit 309034f5a0fa9f90cc725be2b5e8f5da9692dcb8 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:14 2011 +0100 support for different location of HT registers in old version of K8T800 Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/early_car.c | 30 ++++++++++++++++++++++-------- 1 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index c554c49..da7b4db 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -35,6 +35,12 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#define K8X8XX_HT_CFG_BASE 0xc0 +#else +#define K8X8XX_HT_CFG_BASE 0x60 +#endif + /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init. * This will not work for K8T800_OLD, which has a slightly different @@ -43,10 +49,13 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; u8 k8t890_early_setup_ht(void) { - u8 awidth, afreq, cldtfreq, reg; + u8 awidth, afreq, cldtfreq; u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + u8 reg; + /* hack, enable NVRAM in chipset */ pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); @@ -58,6 +67,7 @@ u8 k8t890_early_setup_ht(void) reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); reg |= 0x1; pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); +#endif /* check if connected non coherent, initcomplete (find the SB on K8 side) */ ldtnr = 0; @@ -73,6 +83,10 @@ u8 k8t890_early_setup_ht(void) print_debug("K8M800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800 print_debug("K8T800 found at LDT "); +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + print_debug("K8T800_OLD found at LDT "); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO print_debug("K8T800 Pro found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8M890 @@ -87,19 +101,19 @@ u8 k8t890_early_setup_ht(void) /* get the maximum widths for both sides */ cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7; - vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7; - vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7; + vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) & 0x7; + vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7; width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); print_debug(" Agreed on width: "); print_debug_hex8(width); - awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7); /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */ width = (width == 0x01) ? 0x11 : 0x00; - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7, width); /* Get programmed HT freq at base 0x89 */ cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; @@ -107,15 +121,15 @@ u8 k8t890_early_setup_ht(void) print_debug_hex8(cldtfreq); print_debug(" VIA HT caps: "); - vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e); + vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe); print_debug_hex16(vldtcaps); if (!(vldtcaps & (1 << cldtfreq ))) { die("Chipset does not support desired HT frequency\n"); } - afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq); + afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq); print_debug("\n"); /* no reset needed */ From gerrit at coreboot.org Wed Nov 2 09:32:53 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:53 +0100 Subject: [coreboot] New patch to review for coreboot: 7706088 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/374 -gerrit commit 77060882c64143228a6058b4686fb102bc6526d7 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:41 2011 +0100 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/romstrap.inc | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc index 5b24948..a3814b0 100644 --- a/src/southbridge/via/k8t890/romstrap.inc +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -33,7 +33,7 @@ __romstrap_start: * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ -#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD tblpointer: .long 0x50220000, 0X619707C2 diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index e599517..b1e1afe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_K8T800 + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */ From gerrit at coreboot.org Wed Nov 2 09:32:54 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:54 +0100 Subject: [coreboot] New patch to review for coreboot: 861b306 configure VT8237R ROM decode according to CONFIG_ROM_SIZE References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/375 -gerrit commit 861b306c9f63f5a7ff075a94d07c21fb2645cf5f Author: Florian Zumbiehl Date: Tue Nov 1 20:18:27 2011 +0100 configure VT8237R ROM decode according to CONFIG_ROM_SIZE Change-Id: I217813f42a52f759bf1010f4c5af62f3c6e5ec6b Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/lpc.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..4b3064a 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -447,7 +447,10 @@ static void vt8237_common_init(struct device *dev) * 0 FFC00000h-FFC7FFFFh * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. */ - pci_write_config8(dev, 0x41, 0x7f); +#if CONFIG_ROM_SIZE > 0x400000 +#error ROMs larger than 4MB are not supported by VT8237 +#endif + pci_write_config8(dev, 0x41, (~(0xff>>((CONFIG_ROM_SIZE+(512*1024-1))/(512*1024))))&0x7f); #endif /* From gerrit at coreboot.org Wed Nov 2 09:32:55 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:55 +0100 Subject: [coreboot] New patch to review for coreboot: 36dc86c fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/376 -gerrit commit 36dc86c3f86adcb9df2f64752c3ceccb334e6b58 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 3583dc3..237272c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1399,7 +1399,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) #define DDR400 (NBCAP_MEMCLK_200MHZ + 1) #define DDR_2T 0x80 -#define DDR_MASK 0x3 +#define DDR_MASK 0x7 #define DDR200_2T (DDR_2T | DDR200) #define DDR333_2T (DDR_2T | DDR333) From gerrit at coreboot.org Wed Nov 2 09:32:56 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:56 +0100 Subject: [coreboot] New patch to review for coreboot: b1c91b4 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit b1c91b40a96724587a147b6f3f97dc92a10fe5e7 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 338 ++++++++++++++++------------------- 1 files changed, 156 insertions(+), 182 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..944517b 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1231,7 +1231,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 25, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,10 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) { #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1440,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos =0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1474,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1483,182 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table are to be understood: */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ +#else /* CONFIG_CPU_AMD_SOCKET_* */ + + #error load dependent memory clock limiting is not implemented for this socket + + /* see BKDG 4.1.3--if you just want to test a setup that doesn't require + * limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what would be + * intuitive. 200 MHz has the lowest constant, 100 MHz the highest. Thus, all + * comparisons and traversal directions having to do with frequencies are/ + * have to be the opposite of what would be intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); // the CLs supported by the controller + memset(cl_at_freq, 0x00, (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle shorter, select that + * (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#ifdef CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1680,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; From gerrit at coreboot.org Wed Nov 2 09:32:57 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:57 +0100 Subject: [coreboot] New patch to review for coreboot: 7c82505 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/378 -gerrit commit 7c82505931f249435fe89bf03a596ffb87488802 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 49 ++++++---------------------------- src/southbridge/via/k8t890/dram.c | 18 ++++++------ src/southbridge/via/k8t890/k8x8xx.h | 25 ++++++++++++++++++ 3 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 42676b1..7363510 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -31,31 +31,8 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - if(!devfun3) - die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); + u8 regm3; + struct k8x8xx_vt8237_mirrored_regs mregs; pci_write_config8(dev, 0x70, 0xc2); @@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); + k8x8xx_vt8237_mirrored_regs_fill(&mregs); - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); + pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */ + pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */ + pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */ - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! @@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) regm3 = 0x0; /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F)); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e..294e387 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index a0fb57a..425aaeb 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -21,6 +21,31 @@ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#include +#include #include "k8t890.h" +struct k8x8xx_vt8237_mirrored_regs { + u16 low_top_address; + u8 rom_shadow_ctrl_pg_c, + rom_shadow_ctrl_pg_d, + rom_shadow_ctrl_pg_e_memhole_smi_decoding, + rom_shadow_ctrl_pg_f_memhole, + smm_apic_decoding, + shadow_mem_ctrl; +}; + +static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Wed Nov 2 09:32:58 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:58 +0100 Subject: [coreboot] New patch to review for coreboot: 6398991 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit 639899110fc22d60e45a6e59bc9275bffcf5932a Author: Florian Zumbiehl Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include #include +#ifndef __PRE_RAM__ +#include +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Wed Nov 2 09:32:58 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:58 +0100 Subject: [coreboot] New patch to review for coreboot: f600317 mark w83697hf_set_clksel_48() as potentially unused References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit f60031755fb2867bebb3ed62ee9bca1599f5dac3 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 mark w83697hf_set_clksel_48() as potentially unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/early_serial.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..cc647a7 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +static void __attribute__ ((unused)) w83697hf_set_clksel_48(device_t dev) { u8 reg8; From gerrit at coreboot.org Wed Nov 2 09:32:59 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:32:59 +0100 Subject: [coreboot] New patch to review for coreboot: 33c753a add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit 33c753a26a73e60b3df9914473e21b4b2d2327d4 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, From gerrit at coreboot.org Wed Nov 2 09:33:00 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:33:00 +0100 Subject: [coreboot] New patch to review for coreboot: c5a14a9 support for setting the Memory DQ Drive Strength register in amdk8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit c5a14a9500962628913ed77d52fe86b16d500b04 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 944517b..9fdda2a 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2192,6 +2192,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; From gerrit at coreboot.org Wed Nov 2 09:33:01 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:33:01 +0100 Subject: [coreboot] New patch to review for coreboot: 39c11a8 add support for setting the vt8237 to uncond. power on after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 39c11a8aa6da368436a48f183764c26eb63096ba Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 4b3064a..ad0327a 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -511,6 +511,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Wed Nov 2 09:33:02 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:33:02 +0100 Subject: [coreboot] New patch to review for coreboot: d3b9110 implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit d3b91106c06225c2bb179326ff2bbcda9ce8d6fd Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Wed Nov 2 09:33:04 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:33:04 +0100 Subject: [coreboot] New patch to review for coreboot: 3e27bde implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit 3e27bdedf8802738e72ab531bbc37296bce02430 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..35530b4 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,22 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, (pci_read_config8(dev, 0x5c) & ~0x70) | (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Wed Nov 2 09:33:05 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:33:05 +0100 Subject: [coreboot] New patch to review for coreboot: ecbe2b0 make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit ecbe2b0979711d5de7dfccafbf375f4d6e8eeeac Author: Florian Zumbiehl Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index ad0327a..baf3f93 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -509,7 +520,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */ From gerrit at coreboot.org Wed Nov 2 09:33:06 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:33:06 +0100 Subject: [coreboot] New patch to review for coreboot: e31e5e0 make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit e31e5e0554f44c4ac22438e5d6ae2212ea51303b Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index baf3f93..c7d1378 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Wed Nov 2 09:33:07 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:33:07 +0100 Subject: [coreboot] New patch to review for coreboot: 099afa0 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 099afa03d6887be7c480584a5b6d9fbb3c4fecfd Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From gerrit at coreboot.org Wed Nov 2 09:33:07 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:33:07 +0100 Subject: [coreboot] New patch to review for coreboot: 51ff257 copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit 51ff25733f1cad47d2c3db61450503e0c08576bf Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Wed Nov 2 09:33:09 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:33:09 +0100 Subject: [coreboot] New patch to review for coreboot: 3c4ed77 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 3c4ed77f4ce9578c895d4b5efe6fa1ff6623a412 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 22 +++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 117 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..31d8564 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,26 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select K8_DQ_DRIVE_STRENGTH_0 + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +44,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +74,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Wed Nov 2 09:49:07 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:49:07 +0100 Subject: [coreboot] New patch to review for coreboot: e108b6d fix superiotool for NCT6776F References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/391 -gerrit commit e108b6d924cffe8634faffb599f2309039dbcb28 Author: Florian Zumbiehl Date: Wed Nov 2 09:46:34 2011 +0100 fix superiotool for NCT6776F The current code exits config mode of the NCT6776F immediately after detection, so the register dump shows all 0xffs. This patch adds code to re-enter config mode for the register dump so that the register contents can be read. Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7 Signed-off-by: Florian Zumbiehl --- util/superiotool/nuvoton.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 6a1a75c..ed2eabc 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -255,7 +255,9 @@ void probe_idregs_nuvoton(uint16_t port) printf("Found Nuvoton %s (id=0x%02x) at 0x%x\n", get_superio_name(reg_table, chip_id), chip_id, port); chip_found = 1; + enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_winbond_fintek_ite_8787(port); return; } From gerrit at coreboot.org Wed Nov 2 09:58:25 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:25 +0100 Subject: [coreboot] Patch set updated for coreboot: 2664633 support for different location of HT registers in old version of K8T800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/373 -gerrit commit 2664633fe8204c17c1ee01bdc9d9793195b1e2ab Author: Florian Zumbiehl Date: Tue Nov 1 20:17:14 2011 +0100 support for different location of HT registers in old version of K8T800 Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/early_car.c | 30 ++++++++++++++++++++++-------- 1 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index c554c49..da7b4db 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -35,6 +35,12 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#define K8X8XX_HT_CFG_BASE 0xc0 +#else +#define K8X8XX_HT_CFG_BASE 0x60 +#endif + /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init. * This will not work for K8T800_OLD, which has a slightly different @@ -43,10 +49,13 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; u8 k8t890_early_setup_ht(void) { - u8 awidth, afreq, cldtfreq, reg; + u8 awidth, afreq, cldtfreq; u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + u8 reg; + /* hack, enable NVRAM in chipset */ pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); @@ -58,6 +67,7 @@ u8 k8t890_early_setup_ht(void) reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); reg |= 0x1; pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); +#endif /* check if connected non coherent, initcomplete (find the SB on K8 side) */ ldtnr = 0; @@ -73,6 +83,10 @@ u8 k8t890_early_setup_ht(void) print_debug("K8M800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800 print_debug("K8T800 found at LDT "); +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + print_debug("K8T800_OLD found at LDT "); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO print_debug("K8T800 Pro found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8M890 @@ -87,19 +101,19 @@ u8 k8t890_early_setup_ht(void) /* get the maximum widths for both sides */ cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7; - vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7; - vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7; + vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) & 0x7; + vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7; width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); print_debug(" Agreed on width: "); print_debug_hex8(width); - awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7); /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */ width = (width == 0x01) ? 0x11 : 0x00; - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7, width); /* Get programmed HT freq at base 0x89 */ cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; @@ -107,15 +121,15 @@ u8 k8t890_early_setup_ht(void) print_debug_hex8(cldtfreq); print_debug(" VIA HT caps: "); - vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e); + vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe); print_debug_hex16(vldtcaps); if (!(vldtcaps & (1 << cldtfreq ))) { die("Chipset does not support desired HT frequency\n"); } - afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq); + afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq); print_debug("\n"); /* no reset needed */ From gerrit at coreboot.org Wed Nov 2 09:58:29 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:29 +0100 Subject: [coreboot] Patch set updated for coreboot: d2281f7 add support for writing to SMBus with vt8237 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/372 -gerrit commit d2281f7f6110ae2382678d525baee68984b0d315 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:13 2011 +0100 add support for writing to SMBus with vt8237 Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/early_smbus.c | 31 +++++++++++++++++++--------- src/southbridge/via/vt8237r/vt8237r.h | 1 + 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index a298e84..0caf93d 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -87,17 +87,12 @@ static void smbus_reset(void) PRINT_DEBUG("\n"); } -/** - * Read a byte from the SMBus. - * - * @param dimm The address location of the DIMM on the SMBus. - * @param offset The offset the data is located at. - */ -u8 smbus_read_byte(u8 dimm, u8 offset) +static u8 smbus_transaction(u8 dimm, u8 offset, int data) { u8 val; - PRINT_DEBUG("DIMM "); + PRINT_DEBUG((data < 0) ? "RD: " : "WR: "); + PRINT_DEBUG("ADDR "); PRINT_DEBUG_HEX16(dimm); PRINT_DEBUG(" OFFSET "); PRINT_DEBUG_HEX16(offset); @@ -106,13 +101,13 @@ u8 smbus_read_byte(u8 dimm, u8 offset) smbus_reset(); /* Clear host data port. */ - outb(0x00, SMBHSTDAT0); + outb((data < 0) ? 0x00 : data, SMBHSTDAT0); SMBUS_DELAY(); smbus_wait_until_ready(); /* Actual addr to reg format. */ dimm = (dimm << 1); - dimm |= 1; + dimm |= (data < 0); outb(dimm, SMBXMITADD); outb(offset, SMBHSTCMD); @@ -132,6 +127,22 @@ u8 smbus_read_byte(u8 dimm, u8 offset) return val; } +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 smbus_read_byte(u8 dimm, u8 offset) +{ + return smbus_transaction(dimm, offset, -1); +} + +void smbus_write_byte(u8 dimm, u8 offset, u8 data) +{ + smbus_transaction(dimm, offset, data); +} + #define PSONREADY_TIMEOUT 0x7fffffff static device_t get_vt8237_lpc(void) diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 94b1840..9d5a1fc 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -148,6 +148,7 @@ __attribute__ ((packed)) #ifdef __PRE_RAM__ #ifndef __ROMCC__ u8 smbus_read_byte(u8 dimm, u8 offset); +void smbus_write_byte(u8 dimm, u8 offset, u8 data); void enable_smbus(void); void smbus_fixup(const struct mem_controller *ctrl); // these are in vt8237_early_smbus.c - do they really belong there? From gerrit at coreboot.org Wed Nov 2 09:58:31 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:31 +0100 Subject: [coreboot] Patch set updated for coreboot: 365b40e configure VT8237R ROM decode according to CONFIG_ROM_SIZE References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/375 -gerrit commit 365b40e2392e3f0bbc57297daf5daa79c3b5d223 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:27 2011 +0100 configure VT8237R ROM decode according to CONFIG_ROM_SIZE Change-Id: I217813f42a52f759bf1010f4c5af62f3c6e5ec6b Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/lpc.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..4b3064a 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -447,7 +447,10 @@ static void vt8237_common_init(struct device *dev) * 0 FFC00000h-FFC7FFFFh * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. */ - pci_write_config8(dev, 0x41, 0x7f); +#if CONFIG_ROM_SIZE > 0x400000 +#error ROMs larger than 4MB are not supported by VT8237 +#endif + pci_write_config8(dev, 0x41, (~(0xff>>((CONFIG_ROM_SIZE+(512*1024-1))/(512*1024))))&0x7f); #endif /* From gerrit at coreboot.org Wed Nov 2 09:58:32 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:32 +0100 Subject: [coreboot] Patch set updated for coreboot: 222716b compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/374 -gerrit commit 222716b03e7f0eb2f09929c5860e7d45e749f73c Author: Florian Zumbiehl Date: Tue Nov 1 20:17:41 2011 +0100 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/romstrap.inc | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc index 5b24948..a3814b0 100644 --- a/src/southbridge/via/k8t890/romstrap.inc +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -33,7 +33,7 @@ __romstrap_start: * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ -#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD tblpointer: .long 0x50220000, 0X619707C2 diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index e599517..b1e1afe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_K8T800 + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */ From gerrit at coreboot.org Wed Nov 2 09:58:33 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:33 +0100 Subject: [coreboot] Patch set updated for coreboot: dd9f3b2 add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit dd9f3b2f575dd1dd0e205a8160f008f89e8ebb8a Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, From gerrit at coreboot.org Wed Nov 2 09:58:34 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:34 +0100 Subject: [coreboot] Patch set updated for coreboot: 7068233 mark w83697hf_set_clksel_48() as potentially unused References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit 70682339d4954b5d62ce31cfc4de075291bc6129 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 mark w83697hf_set_clksel_48() as potentially unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/early_serial.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..cc647a7 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +static void __attribute__ ((unused)) w83697hf_set_clksel_48(device_t dev) { u8 reg8; From gerrit at coreboot.org Wed Nov 2 09:58:35 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:35 +0100 Subject: [coreboot] Patch set updated for coreboot: 7ffbce8 add support for setting the vt8237 to uncond. power on after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 7ffbce8021e7368637ef3581dffa88ce475e186b Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 4b3064a..ad0327a 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -511,6 +511,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Wed Nov 2 09:58:35 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:35 +0100 Subject: [coreboot] Patch set updated for coreboot: f19b7d3 support for setting the Memory DQ Drive Strength register in amdk8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit f19b7d311da7ee134b77d9e1e98d7c6d4ffe5e27 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 944517b..9fdda2a 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2192,6 +2192,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; From gerrit at coreboot.org Wed Nov 2 09:58:36 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:36 +0100 Subject: [coreboot] Patch set updated for coreboot: 44d9571 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit 44d95718f3667f4bda658da9728155b4da39299b Author: Florian Zumbiehl Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 338 ++++++++++++++++------------------- 1 files changed, 156 insertions(+), 182 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..944517b 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1231,7 +1231,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 25, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,10 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) { #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1440,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos =0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1474,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1483,182 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table are to be understood: */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ +#else /* CONFIG_CPU_AMD_SOCKET_* */ + + #error load dependent memory clock limiting is not implemented for this socket + + /* see BKDG 4.1.3--if you just want to test a setup that doesn't require + * limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what would be + * intuitive. 200 MHz has the lowest constant, 100 MHz the highest. Thus, all + * comparisons and traversal directions having to do with frequencies are/ + * have to be the opposite of what would be intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); // the CLs supported by the controller + memset(cl_at_freq, 0x00, (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle shorter, select that + * (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#ifdef CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1680,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; From gerrit at coreboot.org Wed Nov 2 09:58:37 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:37 +0100 Subject: [coreboot] Patch set updated for coreboot: 006792c fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/376 -gerrit commit 006792c80f5350b6d6309bdc377665a23594663d Author: Florian Zumbiehl Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 3583dc3..237272c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1399,7 +1399,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) #define DDR400 (NBCAP_MEMCLK_200MHZ + 1) #define DDR_2T 0x80 -#define DDR_MASK 0x3 +#define DDR_MASK 0x7 #define DDR200_2T (DDR_2T | DDR200) #define DDR333_2T (DDR_2T | DDR333) From gerrit at coreboot.org Wed Nov 2 09:58:37 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:37 +0100 Subject: [coreboot] Patch set updated for coreboot: 9498eb5 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit 9498eb5f30dea8e037c90dd29a9e9460f529b164 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include #include +#ifndef __PRE_RAM__ +#include +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Wed Nov 2 09:58:37 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:37 +0100 Subject: [coreboot] Patch set updated for coreboot: cb06461 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/378 -gerrit commit cb06461c716bd825f3d781f441ffde71b61bfcbf Author: Florian Zumbiehl Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 49 ++++++---------------------------- src/southbridge/via/k8t890/dram.c | 18 ++++++------ src/southbridge/via/k8t890/k8x8xx.h | 25 ++++++++++++++++++ 3 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 42676b1..7363510 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -31,31 +31,8 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - if(!devfun3) - die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); + u8 regm3; + struct k8x8xx_vt8237_mirrored_regs mregs; pci_write_config8(dev, 0x70, 0xc2); @@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); + k8x8xx_vt8237_mirrored_regs_fill(&mregs); - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); + pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */ + pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */ + pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */ - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! @@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) regm3 = 0x0; /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F)); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e..294e387 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index a0fb57a..425aaeb 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -21,6 +21,31 @@ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#include +#include #include "k8t890.h" +struct k8x8xx_vt8237_mirrored_regs { + u16 low_top_address; + u8 rom_shadow_ctrl_pg_c, + rom_shadow_ctrl_pg_d, + rom_shadow_ctrl_pg_e_memhole_smi_decoding, + rom_shadow_ctrl_pg_f_memhole, + smm_apic_decoding, + shadow_mem_ctrl; +}; + +static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Wed Nov 2 09:58:38 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:38 +0100 Subject: [coreboot] Patch set updated for coreboot: e59aebd make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit e59aebd0e233cef84171c96133ba360844c290f7 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index baf3f93..c7d1378 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Wed Nov 2 09:58:39 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:39 +0100 Subject: [coreboot] Patch set updated for coreboot: befd4f0 make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit befd4f04f57d4afaff1b94cfda0d54483eb3d9ff Author: Florian Zumbiehl Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index ad0327a..baf3f93 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -509,7 +520,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */ From gerrit at coreboot.org Wed Nov 2 09:58:41 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:41 +0100 Subject: [coreboot] Patch set updated for coreboot: 5913598 implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit 5913598fe2a3600b4bac7584feb49bdcb2c582a1 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..35530b4 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,22 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, (pci_read_config8(dev, 0x5c) & ~0x70) | (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Wed Nov 2 09:58:42 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:42 +0100 Subject: [coreboot] Patch set updated for coreboot: ca854b1 implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit ca854b1a44f02f88df003d4d3b459a00b727b68f Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Wed Nov 2 09:58:43 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:43 +0100 Subject: [coreboot] Patch set updated for coreboot: d05adc2 fix superiotool for NCT6776F References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/391 -gerrit commit d05adc204c1b1090c4ebf4c2fde3a94415d2cf56 Author: Florian Zumbiehl Date: Wed Nov 2 09:46:34 2011 +0100 fix superiotool for NCT6776F The current code exits config mode of the NCT6776F immediately after detection, so the register dump shows all 0xffs. This patch adds code to re-enter config mode for the register dump so that the register contents can be read. Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7 Signed-off-by: Florian Zumbiehl --- util/superiotool/nuvoton.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 6a1a75c..ed2eabc 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -255,7 +255,9 @@ void probe_idregs_nuvoton(uint16_t port) printf("Found Nuvoton %s (id=0x%02x) at 0x%x\n", get_superio_name(reg_table, chip_id), chip_id, port); chip_found = 1; + enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_winbond_fintek_ite_8787(port); return; } From gerrit at coreboot.org Wed Nov 2 09:58:44 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:44 +0100 Subject: [coreboot] Patch set updated for coreboot: 34309c9 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 34309c971d1f513b90b5964319378d69a40d9617 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 22 +++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 117 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..31d8564 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,26 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select K8_DQ_DRIVE_STRENGTH_0 + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +44,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +74,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Wed Nov 2 09:58:44 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:44 +0100 Subject: [coreboot] Patch set updated for coreboot: 75198d8 copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit 75198d8342a20c7e4590dcc461b25d2f4fa52a2f Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Wed Nov 2 09:58:45 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 09:58:45 +0100 Subject: [coreboot] Patch set updated for coreboot: 38c32d5 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 38c32d5ebe74a0c7980849f5998bdc2597ea366d Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From gerrit at coreboot.org Wed Nov 2 10:49:27 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 2 Nov 2011 10:49:27 +0100 Subject: [coreboot] Patch merged into coreboot/master: f07282e don't scan beyond end of CBFS References: Message-ID: the following patch was just integrated into master: commit f07282efab87037a54cf0f48c0ab835cbbd39efe Author: Florian Zumbiehl Date: Tue Nov 1 20:17:11 2011 +0100 don't scan beyond end of CBFS Change-Id: I66e535f77e513dbfa5fc906ecf288193af78ae62 Signed-off-by: Florian Zumbiehl Reviewed-By: Patrick Georgi at Wed Nov 2 10:49:24 2011, giving +2 See http://review.coreboot.org/369 for details. -gerrit From gerrit at coreboot.org Wed Nov 2 10:51:04 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 2 Nov 2011 10:51:04 +0100 Subject: [coreboot] Patch merged into coreboot/master: d1f7cf4 buildgcc: Update coreboot reference toolchain to gcc 4.6.2 References: Message-ID: the following patch was just integrated into master: commit d1f7cf4195bf3b1cca86f2b78eb0625411479706 Author: Stefan Reinauer Date: Tue Nov 1 22:39:41 2011 +0100 buildgcc: Update coreboot reference toolchain to gcc 4.6.2 In addition: - drop some unneeded patches - make the scripting support depend on SKIPPYTHON not SKIPGDB so it is possible to build GDB with and without scripting support - rename the repository checkout version of GCC trunk, not X+1 so we don't have to change it on every version upgrade. Change-Id: I1b7d5b8921187c1c1d39b04f20bb715ddba72fe8 Signed-off-by: Stefan Reinauer Reviewed-By: Patrick Georgi at Wed Nov 2 10:51:01 2011, giving +2 See http://review.coreboot.org/367 for details. -gerrit From gerrit at coreboot.org Wed Nov 2 12:27:39 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:39 +0100 Subject: [coreboot] Patch set updated for coreboot: 3466ecc add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit 3466ecc1be4c32f4399ddb206a7a821eb501e575 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, From gerrit at coreboot.org Wed Nov 2 12:27:40 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:40 +0100 Subject: [coreboot] Patch set updated for coreboot: 97b52bd mark w83697hf_set_clksel_48() as potentially unused References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit 97b52bd86de0d75edf466eacd71a21cd3d3aa8da Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 mark w83697hf_set_clksel_48() as potentially unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/early_serial.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..cc647a7 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +static void __attribute__ ((unused)) w83697hf_set_clksel_48(device_t dev) { u8 reg8; From gerrit at coreboot.org Wed Nov 2 12:27:41 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:41 +0100 Subject: [coreboot] Patch set updated for coreboot: 514140a add support for setting the vt8237 to uncond. power on after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 514140a110bb009a5d6398e9214ead97fea35324 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 4b3064a..ad0327a 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -511,6 +511,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Wed Nov 2 12:27:41 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:41 +0100 Subject: [coreboot] Patch set updated for coreboot: b4dc640 support for setting the Memory DQ Drive Strength register in amdk8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit b4dc6403bb1ab307ab331ea1b0a985d61d9d2f4a Author: Florian Zumbiehl Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index f618a53..a016fec 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2192,6 +2192,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; From gerrit at coreboot.org Wed Nov 2 12:27:42 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:42 +0100 Subject: [coreboot] Patch set updated for coreboot: 3c9771a k8 raminit: fix bug, improve clock selection, add clock limit for sock754 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit 3c9771aad068611f3fedb8506c4ac2faafbf250c Author: Florian Zumbiehl Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 338 ++++++++++++++++------------------- 1 files changed, 156 insertions(+), 182 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..f618a53 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1231,7 +1231,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 25, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,10 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) { #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1440,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos =0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1474,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1483,182 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table are to be understood: */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ +#else /* CONFIG_CPU_AMD_SOCKET_* */ + + #error load dependent memory clock limiting is not implemented for this socket + + /* see BKDG 4.1.3--if you just want to test a setup that doesn't require + * limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what would be + * intuitive. 200 MHz has the lowest constant, 100 MHz the highest. Thus, all + * comparisons and traversal directions having to do with frequencies are/ + * have to be the opposite of what would be intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); // the CLs supported by the controller + memset(cl_at_freq, 0x00, (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle shorter, select that + * (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#if CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1680,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; From gerrit at coreboot.org Wed Nov 2 12:27:44 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:44 +0100 Subject: [coreboot] Patch set updated for coreboot: cbedcb3 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit cbedcb39422e30edc89a5c0d0a138910e139f56f Author: Florian Zumbiehl Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include #include +#ifndef __PRE_RAM__ +#include +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Wed Nov 2 12:27:45 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:45 +0100 Subject: [coreboot] Patch set updated for coreboot: edc3439 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/378 -gerrit commit edc3439f4f5f2f1e4e2ba7f95e13f29407dd2281 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 49 ++++++---------------------------- src/southbridge/via/k8t890/dram.c | 18 ++++++------ src/southbridge/via/k8t890/k8x8xx.h | 25 ++++++++++++++++++ 3 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 42676b1..7363510 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -31,31 +31,8 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - if(!devfun3) - die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); + u8 regm3; + struct k8x8xx_vt8237_mirrored_regs mregs; pci_write_config8(dev, 0x70, 0xc2); @@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); + k8x8xx_vt8237_mirrored_regs_fill(&mregs); - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); + pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */ + pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */ + pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */ - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! @@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) regm3 = 0x0; /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F)); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e..294e387 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index a0fb57a..425aaeb 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -21,6 +21,31 @@ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#include +#include #include "k8t890.h" +struct k8x8xx_vt8237_mirrored_regs { + u16 low_top_address; + u8 rom_shadow_ctrl_pg_c, + rom_shadow_ctrl_pg_d, + rom_shadow_ctrl_pg_e_memhole_smi_decoding, + rom_shadow_ctrl_pg_f_memhole, + smm_apic_decoding, + shadow_mem_ctrl; +}; + +static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Wed Nov 2 12:27:46 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:46 +0100 Subject: [coreboot] Patch set updated for coreboot: 6c1769b make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 6c1769b7824a34cecdd94fab9e54e61c963543a0 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index baf3f93..c7d1378 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Wed Nov 2 12:27:47 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:47 +0100 Subject: [coreboot] Patch set updated for coreboot: 886cd05 make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 886cd0521b006089576995fa4612dfa19fb5320b Author: Florian Zumbiehl Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index ad0327a..baf3f93 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -509,7 +520,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */ From gerrit at coreboot.org Wed Nov 2 12:27:48 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:48 +0100 Subject: [coreboot] Patch set updated for coreboot: a4b13bc implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit a4b13bcb1bf58ae13f089826e8a29d720ecc5742 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..35530b4 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,22 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, (pci_read_config8(dev, 0x5c) & ~0x70) | (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Wed Nov 2 12:27:49 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:49 +0100 Subject: [coreboot] Patch set updated for coreboot: ac4136b implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit ac4136b199a8968963b139506ef5b4d5cb6324e6 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Wed Nov 2 12:27:51 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:51 +0100 Subject: [coreboot] Patch set updated for coreboot: 613b77e fix superiotool for NCT6776F References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/391 -gerrit commit 613b77e870e0e4cf1da874e9d0a4a1e02425683b Author: Florian Zumbiehl Date: Wed Nov 2 09:46:34 2011 +0100 fix superiotool for NCT6776F The current code exits config mode of the NCT6776F immediately after detection, so the register dump shows all 0xffs. This patch adds code to re-enter config mode for the register dump so that the register contents can be read. Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7 Signed-off-by: Florian Zumbiehl --- util/superiotool/nuvoton.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 6a1a75c..ed2eabc 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -255,7 +255,9 @@ void probe_idregs_nuvoton(uint16_t port) printf("Found Nuvoton %s (id=0x%02x) at 0x%x\n", get_superio_name(reg_table, chip_id), chip_id, port); chip_found = 1; + enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_winbond_fintek_ite_8787(port); return; } From gerrit at coreboot.org Wed Nov 2 12:27:52 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:52 +0100 Subject: [coreboot] Patch set updated for coreboot: 2407feb adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 2407febc4f91f891e9b5d8685a2f3938be6a7a55 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 22 +++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 117 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..31d8564 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,26 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select K8_DQ_DRIVE_STRENGTH_0 + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +44,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +74,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Wed Nov 2 12:27:55 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:55 +0100 Subject: [coreboot] Patch set updated for coreboot: da03f83 copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit da03f8309625e123f14652380b1cd4e6d3b31b6e Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Wed Nov 2 12:27:56 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 12:27:56 +0100 Subject: [coreboot] Patch set updated for coreboot: e5286a1 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit e5286a168640317cacefa778b6c99178074006ab Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From lists at e4L.es Wed Nov 2 12:55:46 2011 From: lists at e4L.es (Elisenda Cuadros) Date: Wed, 02 Nov 2011 12:55:46 +0100 Subject: [coreboot] Coreboot and Epia M-II In-Reply-To: References: <4EB047B7.5000907@e4L.es> <4EB0E34E.7060909@e4L.es> Message-ID: <4EB12FC2.8010805@e4L.es> Hello QingPei, This is the output of this command: Name Offset Type Size cmos_layout.bin 0x0 unknown 1159 pci1106,3122.rom 0x4c0 optionrom 57344 config 0xe500 raw 2581 bootorder 0xef40 raw 86 (empty) 0xefc0 null 3992 fallback/romstage 0xff80 stage 33837 fallback/coreboot_ram 0x18440 stage 36544 fallback/payload 0x21340 payload 51429 (empty) 0x2dc80 null 73878 Regards, Elisenda On 02/11/2011 7:55, QingPei Wang wrote: > what's the structure of cbfs? > how about the output of command: > ./build/cbfstool coreboot.rom print > ? > > > > Best wishes > QingPei Wang > Phone: 86+018930528086 From enok at lysator.liu.se Wed Nov 2 13:37:07 2011 From: enok at lysator.liu.se (Oskar Enoksson) Date: Wed, 02 Nov 2011 13:37:07 +0100 Subject: [coreboot] How to change clockchip frequency? Message-ID: <4EB13973.6070404@lysator.liu.se> I have a chip called CDC960 on my motherboard. It is responsible for generating the bus frequency for the cpu, the pci bus etc. I downloaded the datasheet and noticed that I can change the base frequency by +/-10% by sending an smbus command to the cdc960. When I sent the smbus commands from a running linux the system froze for a few seconds and then rebooted. But after reboot the frequency was indeed changed (overclocked) and everything worked just fine. I tried to add the smbus command to romstage.c in my coreboot, but that didn't work. The boot process just hanged immediately after the smbus command had been sent. I guess the running CPU (or something else in the system) cannot handle the frequency change and needs to be reset immediately after the command is sent. Perhaps some watchdog under Linux resets the system after a few seconds of irresponsiveness. But what is the recommended way in coreboot? From gerrit at coreboot.org Wed Nov 2 16:50:06 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 2 Nov 2011 16:50:06 +0100 Subject: [coreboot] Patch merged into coreboot/master: 0d22c91 simplify IDE cable detection for Asus M2V References: Message-ID: the following patch was just integrated into master: commit 0d22c9143f78aad039a364b15e651baf98e37a2f Author: Florian Zumbiehl Date: Tue Nov 1 20:17:13 2011 +0100 simplify IDE cable detection for Asus M2V Change-Id: If8e4dcf405e24b744ac34f581c5609fcce96fd07 Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Wed Nov 2 10:27:32 2011, giving +1 Reviewed-By: Stefan Reinauer at Wed Nov 2 16:50:04 2011, giving +2 See http://review.coreboot.org/371 for details. -gerrit From marcj303 at gmail.com Wed Nov 2 16:31:17 2011 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 2 Nov 2011 09:31:17 -0600 Subject: [coreboot] How to change clockchip frequency? In-Reply-To: <4EB13973.6070404@lysator.liu.se> References: <4EB13973.6070404@lysator.liu.se> Message-ID: On Wed, Nov 2, 2011 at 6:37 AM, Oskar Enoksson wrote: > I have a chip called CDC960 on my motherboard. It is responsible for > generating the bus frequency for the cpu, the pci bus etc. I downloaded the > datasheet and noticed that I can change the base frequency by +/-10% by > sending an smbus command to the cdc960. > > When I sent the smbus commands from a running linux the system froze for a > few seconds and then rebooted. But after reboot the frequency was indeed > changed (overclocked) and everything worked just fine. > > I tried to add the smbus command to romstage.c in my coreboot, but that > didn't work. The boot process just hanged immediately after the smbus > command had been sent. > > I guess the running CPU (or something else in the system) cannot handle the > frequency change and needs to be reset immediately after the command is > sent. Perhaps some watchdog under Linux resets the system after a few > seconds of irresponsiveness. But what is the recommended way in coreboot? It would be hard to tell why Linux resets, but you can look in the southbridge for a watchdog. You should also read the CPU spec about changing clock speed etc. Marc -- http://se-eng.com From enok at lysator.liu.se Wed Nov 2 17:26:15 2011 From: enok at lysator.liu.se (Oskar Enoksson) Date: Wed, 02 Nov 2011 17:26:15 +0100 Subject: [coreboot] How to change clockchip frequency? In-Reply-To: References: <4EB13973.6070404@lysator.liu.se> Message-ID: <4EB16F27.5030609@lysator.liu.se> On 11/02/2011 04:31 PM, Marc Jones wrote: > On Wed, Nov 2, 2011 at 6:37 AM, Oskar Enoksson wrote: >> I have a chip called CDC960 on my motherboard. It is responsible for >> generating the bus frequency for the cpu, the pci bus etc. I downloaded the >> datasheet and noticed that I can change the base frequency by +/-10% by >> sending an smbus command to the cdc960. >> >> When I sent the smbus commands from a running linux the system froze for a >> few seconds and then rebooted. But after reboot the frequency was indeed >> changed (overclocked) and everything worked just fine. >> >> I tried to add the smbus command to romstage.c in my coreboot, but that >> didn't work. The boot process just hanged immediately after the smbus >> command had been sent. >> >> I guess the running CPU (or something else in the system) cannot handle the >> frequency change and needs to be reset immediately after the command is >> sent. Perhaps some watchdog under Linux resets the system after a few >> seconds of irresponsiveness. But what is the recommended way in coreboot? > It would be hard to tell why Linux resets, but you can look in the > southbridge for a watchdog. You should also read the CPU spec about > changing clock speed etc. Thanks. There is a watchdog in the southbridge (amd 8111) and it could be set up to reset the system after a specified number of seconds, but it requires memory mapped I/O to work and I'm not sure how to do that in coreboot. Do you (or someone else) think it's a doable way? If so I'll give it a try ... From gerrit at coreboot.org Wed Nov 2 19:43:49 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:49 +0100 Subject: [coreboot] Patch set updated for coreboot: f76086e add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit f76086e6289c3aa50ca9f50116984d150e6a5544 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, From gerrit at coreboot.org Wed Nov 2 19:43:49 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:49 +0100 Subject: [coreboot] Patch set updated for coreboot: b728c65 mark w83697hf_set_clksel_48() as potentially unused References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit b728c65becdaec4d1d1c57876d104cace8ee6fa5 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 mark w83697hf_set_clksel_48() as potentially unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/early_serial.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..cc647a7 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +static void __attribute__ ((unused)) w83697hf_set_clksel_48(device_t dev) { u8 reg8; From gerrit at coreboot.org Wed Nov 2 19:43:50 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:50 +0100 Subject: [coreboot] Patch set updated for coreboot: 275c049 add support for setting the vt8237 to uncond. power on after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 275c04970eda963c76188c88968f08d1b508da0e Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..0e757fe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Wed Nov 2 19:43:50 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:50 +0100 Subject: [coreboot] Patch set updated for coreboot: c8e6c0d support for setting the Memory DQ Drive Strength register in amdk8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit c8e6c0dbff35eaa9b4ebe7ef4103ecf75ca7172b Author: Florian Zumbiehl Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 11288da..d8dcab8 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2193,6 +2193,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; From gerrit at coreboot.org Wed Nov 2 19:43:51 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:51 +0100 Subject: [coreboot] Patch set updated for coreboot: da28c9e k8 raminit: fix bug, improve clock selection, add clock limit for sock754 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit da28c9eb48fb76a142566fc595614bbe9e265914 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 339 ++++++++++++++++------------------- 1 files changed, 157 insertions(+), 182 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..11288da 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1231,7 +1231,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 25, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,10 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) { #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1440,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos =0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1474,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1483,183 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table are to be understood: */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ +#else /* CONFIG_CPU_AMD_SOCKET_* */ + +// well, there are socket 940 boards supported which obviously fail to compile with this +// #error load dependent memory clock limiting is not implemented for this socket + + /* see BKDG 4.1.3--if you just want to test a setup that doesn't require + * limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what would be + * intuitive. 200 MHz has the lowest constant, 100 MHz the highest. Thus, all + * comparisons and traversal directions having to do with frequencies are/ + * have to be the opposite of what would be intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); // the CLs supported by the controller + memset(cl_at_freq, 0x00, (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle shorter, select that + * (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#if CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1681,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; From gerrit at coreboot.org Wed Nov 2 19:43:51 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:51 +0100 Subject: [coreboot] Patch set updated for coreboot: 679ebf7 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/376 -gerrit commit 679ebf74463706fef8d91cdf05bc816af2730d73 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 3583dc3..237272c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1399,7 +1399,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) #define DDR400 (NBCAP_MEMCLK_200MHZ + 1) #define DDR_2T 0x80 -#define DDR_MASK 0x3 +#define DDR_MASK 0x7 #define DDR200_2T (DDR_2T | DDR200) #define DDR333_2T (DDR_2T | DDR333) From gerrit at coreboot.org Wed Nov 2 19:43:52 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:52 +0100 Subject: [coreboot] Patch set updated for coreboot: f9ea54d rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit f9ea54db581318930f864e50c2ee3b3e813468da Author: Florian Zumbiehl Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include #include +#ifndef __PRE_RAM__ +#include +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Wed Nov 2 19:43:53 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:53 +0100 Subject: [coreboot] Patch set updated for coreboot: 24e70cf factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/378 -gerrit commit 24e70cf2a2594bda06b4e6de943a75a27d0256f8 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 49 ++++++---------------------------- src/southbridge/via/k8t890/dram.c | 18 ++++++------ src/southbridge/via/k8t890/k8x8xx.h | 25 ++++++++++++++++++ 3 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 42676b1..7363510 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -31,31 +31,8 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - if(!devfun3) - die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); + u8 regm3; + struct k8x8xx_vt8237_mirrored_regs mregs; pci_write_config8(dev, 0x70, 0xc2); @@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); + k8x8xx_vt8237_mirrored_regs_fill(&mregs); - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); + pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */ + pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */ + pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */ - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! @@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) regm3 = 0x0; /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F)); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e..294e387 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index a0fb57a..425aaeb 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -21,6 +21,31 @@ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#include +#include #include "k8t890.h" +struct k8x8xx_vt8237_mirrored_regs { + u16 low_top_address; + u8 rom_shadow_ctrl_pg_c, + rom_shadow_ctrl_pg_d, + rom_shadow_ctrl_pg_e_memhole_smi_decoding, + rom_shadow_ctrl_pg_f_memhole, + smm_apic_decoding, + shadow_mem_ctrl; +}; + +static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Wed Nov 2 19:43:54 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:54 +0100 Subject: [coreboot] Patch set updated for coreboot: 31de04d make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 31de04d87ffc93f1bc28ef93b39b65110e1766be Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index d4f7820..7d7326c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Wed Nov 2 19:43:54 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:54 +0100 Subject: [coreboot] Patch set updated for coreboot: 13fc22c make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 13fc22c262c608540989c8af241440da2f4b638a Author: Florian Zumbiehl Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 0e757fe..d4f7820 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -506,7 +517,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */ From gerrit at coreboot.org Wed Nov 2 19:43:55 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:55 +0100 Subject: [coreboot] Patch set updated for coreboot: f5023c4 implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit f5023c413fceb8ddbe361c96e283de0927d278b0 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..35530b4 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,22 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, (pci_read_config8(dev, 0x5c) & ~0x70) | (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Wed Nov 2 19:43:56 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:56 +0100 Subject: [coreboot] Patch set updated for coreboot: e58524a implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit e58524afb555780feddc24fec1f2125340a4d666 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Wed Nov 2 19:43:58 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:58 +0100 Subject: [coreboot] Patch set updated for coreboot: c31d869 fix superiotool for NCT6776F References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/391 -gerrit commit c31d8690fb0a5060fe59ee30b04739c000d6accb Author: Florian Zumbiehl Date: Wed Nov 2 09:46:34 2011 +0100 fix superiotool for NCT6776F The current code exits config mode of the NCT6776F immediately after detection, so the register dump shows all 0xffs. This patch adds code to re-enter config mode for the register dump so that the register contents can be read. Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7 Signed-off-by: Florian Zumbiehl --- util/superiotool/nuvoton.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 6a1a75c..ed2eabc 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -255,7 +255,9 @@ void probe_idregs_nuvoton(uint16_t port) printf("Found Nuvoton %s (id=0x%02x) at 0x%x\n", get_superio_name(reg_table, chip_id), chip_id, port); chip_found = 1; + enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_winbond_fintek_ite_8787(port); return; } From gerrit at coreboot.org Wed Nov 2 19:43:59 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:43:59 +0100 Subject: [coreboot] Patch set updated for coreboot: 2e725e2 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 2e725e2c4399c177f7371de0b567c7e3328f9b5b Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 22 +++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 117 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..31d8564 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,26 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select K8_DQ_DRIVE_STRENGTH_0 + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +44,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +74,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Wed Nov 2 19:44:00 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:44:00 +0100 Subject: [coreboot] Patch set updated for coreboot: e85069f copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit e85069ffb48e9be2bc2469e34167fa86e043ee3d Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Wed Nov 2 19:44:01 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 19:44:01 +0100 Subject: [coreboot] Patch set updated for coreboot: b838977 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit b838977c3554e0775a0fea4ad6c09a9132db2ce7 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From marcj303 at gmail.com Wed Nov 2 20:04:02 2011 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 2 Nov 2011 13:04:02 -0600 Subject: [coreboot] How to change clockchip frequency? In-Reply-To: <4EB16F27.5030609@lysator.liu.se> References: <4EB13973.6070404@lysator.liu.se> <4EB16F27.5030609@lysator.liu.se> Message-ID: On Wed, Nov 2, 2011 at 10:26 AM, Oskar Enoksson wrote: > On 11/02/2011 04:31 PM, Marc Jones wrote: >> >> On Wed, Nov 2, 2011 at 6:37 AM, Oskar Enoksson >> ?wrote: >>> >>> I have a chip called CDC960 on my motherboard. It is responsible for >>> generating the bus frequency for the cpu, the pci bus etc. I downloaded >>> the >>> datasheet and noticed that I can change the base frequency by +/-10% by >>> sending an smbus command to the cdc960. >>> >>> When I sent the smbus commands from a running linux the system froze for >>> a >>> few seconds and then rebooted. But after reboot the frequency was indeed >>> changed (overclocked) and everything worked just fine. >>> >>> I tried to add the smbus command to romstage.c in my coreboot, but that >>> didn't work. The boot process just hanged immediately after the smbus >>> command had been sent. >>> >>> I guess the running CPU (or something else in the system) cannot handle >>> the >>> frequency change and needs to be reset immediately after the command is >>> sent. Perhaps some watchdog under Linux resets the system after a few >>> seconds of irresponsiveness. But what is the recommended way in coreboot? >> >> It would be hard to tell why Linux resets, but you can look in the >> southbridge for a watchdog. You should also read the CPU spec about >> changing clock speed etc. > > Thanks. There is a watchdog in the southbridge (amd 8111) and it could be > set up to reset the system after a specified number of seconds, but it > requires memory mapped I/O to work and I'm not sure how to do that in > coreboot. > > Do you (or someone else) think it's a doable way? If so I'll give it a try Seems doable. You should be able to refer to similar register accesses in the 8111 code for reference. I assume that there is a way to change the clocking without needing the watchdog though. The watchdog would be a failsafe. Marc -- http://se-eng.com From lists at e4L.es Wed Nov 2 22:07:36 2011 From: lists at e4L.es (Elisenda Cuadros) Date: Wed, 02 Nov 2011 22:07:36 +0100 Subject: [coreboot] Coreboot and Epia M-II In-Reply-To: References: <4EB047B7.5000907@e4L.es> <4EB0E34E.7060909@e4L.es> <4EB12FC2.8010805@e4L.es> Message-ID: <4EB1B118.20704@e4L.es> Hi, I?m using the default seabios config. I think it has debug level set to 8. Now I compiled Seabios with debug set to 10. I attach you a new log. I tried compiling coreboot with FILO (from menuconfig) and it works perfect. I can boot linux with this rom. I tried to compile seabios outside coreboot menuconfig, adding it like an elf executable. Same problem. The problem for me it?s that I want to use this board with FreeBSD and If I?m not wrong Seabios is the only way to do it. Thanks for all. Regards, Elisenda On 02/11/2011 16:19, QingPei Wang wrote: > the coreboot.rom seems fine, do you use the default seabios config, > try to set the debug level of seabios to 8 to show more messages. > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: coreboot-seabios_debug10.log URL: From gerrit at coreboot.org Wed Nov 2 23:10:37 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:37 +0100 Subject: [coreboot] Patch set updated for coreboot: c7bbf3f make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit c7bbf3f298bff33c7616596a3303914453db929e Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index d4f7820..7d7326c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Wed Nov 2 23:10:38 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:38 +0100 Subject: [coreboot] Patch set updated for coreboot: 23c6cac add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit 23c6cac22b58626f9ec1a3293e01a3ffa9856244 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, From gerrit at coreboot.org Wed Nov 2 23:10:38 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:38 +0100 Subject: [coreboot] Patch set updated for coreboot: 3242e7d make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 3242e7dbf75f5e5d7d828dd07356a767e3112ca2 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 0e757fe..d4f7820 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -506,7 +517,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */ From gerrit at coreboot.org Wed Nov 2 23:10:39 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:39 +0100 Subject: [coreboot] Patch set updated for coreboot: 883fc87 make w83697hf_set_clksel_48() non-static and add a prototype References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit 883fc87875a0e7ad7107ee65310c2d5724023ac6 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 make w83697hf_set_clksel_48() non-static and add a prototype make w83697hf_set_clksel_48() non-static and add a prototype so as to get rid of warnings about it being unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/early_serial.c | 2 +- src/superio/winbond/w83697hf/w83697hf.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..2825eeb 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(device_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 0eeb37c..e1251c2 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -32,4 +32,6 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ +void w83697hf_set_clksel_48(device_t); + #endif From gerrit at coreboot.org Wed Nov 2 23:10:39 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:39 +0100 Subject: [coreboot] Patch set updated for coreboot: e67962f implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit e67962f4d2245e3eabae43c1cee1b1fe3f7f930e Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..35530b4 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,22 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, (pci_read_config8(dev, 0x5c) & ~0x70) | (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Wed Nov 2 23:10:39 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:39 +0100 Subject: [coreboot] Patch set updated for coreboot: cf7dc41 add support for setting the vt8237 to uncond. power on after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit cf7dc41c3e80e96f763f7bbb39a820dbfd8fab3b Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..0e757fe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Wed Nov 2 23:10:40 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:40 +0100 Subject: [coreboot] Patch set updated for coreboot: ddf36ef implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit ddf36efd1d7dcf7173b3d1758821fe5775c27ae2 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Wed Nov 2 23:10:40 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:40 +0100 Subject: [coreboot] Patch set updated for coreboot: 2f3d4e4 support for setting the Memory DQ Drive Strength register in amdk8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit 2f3d4e4016a9b12c669e13a9b3e4978cbaec4c94 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 11288da..d8dcab8 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2193,6 +2193,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; From gerrit at coreboot.org Wed Nov 2 23:10:41 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:41 +0100 Subject: [coreboot] Patch set updated for coreboot: 214e7e7 fix superiotool for NCT6776F References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/391 -gerrit commit 214e7e721ea3aba2be006dd8142fcadaa9573a2a Author: Florian Zumbiehl Date: Wed Nov 2 09:46:34 2011 +0100 fix superiotool for NCT6776F The current code exits config mode of the NCT6776F immediately after detection, so the register dump shows all 0xffs. This patch adds code to re-enter config mode for the register dump so that the register contents can be read. Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7 Signed-off-by: Florian Zumbiehl --- util/superiotool/nuvoton.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 6a1a75c..ed2eabc 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -255,7 +255,9 @@ void probe_idregs_nuvoton(uint16_t port) printf("Found Nuvoton %s (id=0x%02x) at 0x%x\n", get_superio_name(reg_table, chip_id), chip_id, port); chip_found = 1; + enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_winbond_fintek_ite_8787(port); return; } From gerrit at coreboot.org Wed Nov 2 23:10:41 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:41 +0100 Subject: [coreboot] Patch set updated for coreboot: acabbda adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit acabbdafbe43ca3f485b6551fb677a3bbe2b1356 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 22 +++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 117 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..31d8564 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,26 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select K8_DQ_DRIVE_STRENGTH_0 + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +44,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +74,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Wed Nov 2 23:10:42 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:42 +0100 Subject: [coreboot] Patch set updated for coreboot: ba952ea copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit ba952ea34899057bebdc4617012acf44ffb05511 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Wed Nov 2 23:10:43 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:10:43 +0100 Subject: [coreboot] Patch set updated for coreboot: 0e13c45 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 0e13c45d8e6afa30175a1658b77a24ec651314cf Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From gerrit at coreboot.org Wed Nov 2 23:42:28 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:28 +0100 Subject: [coreboot] Patch set updated for coreboot: 293e0f7 make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 293e0f720d87fe761f67889b994af6d62c406823 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index d4f7820..7d7326c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Wed Nov 2 23:42:33 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:33 +0100 Subject: [coreboot] Patch set updated for coreboot: c43aa71 add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit c43aa71254edb8a16d9ba3e28826b9c822e9f398 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, From gerrit at coreboot.org Wed Nov 2 23:42:34 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:34 +0100 Subject: [coreboot] Patch set updated for coreboot: 13fa866 make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 13fa866d6212a87a1361f17142f51d462beee932 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 0e757fe..d4f7820 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -506,7 +517,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */ From gerrit at coreboot.org Wed Nov 2 23:42:35 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:35 +0100 Subject: [coreboot] Patch set updated for coreboot: cbd3405 make w83697hf_set_clksel_48() non-static and add a prototype References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit cbd3405e6bf6e1c5bfdeb81b7638d986855f7333 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 make w83697hf_set_clksel_48() non-static and add a prototype make w83697hf_set_clksel_48() non-static and add a prototype so as to get rid of warnings about it being unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/early_serial.c | 2 +- src/superio/winbond/w83697hf/w83697hf.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..2825eeb 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(device_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 0eeb37c..6488dd3 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -32,4 +32,8 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ +#ifndef __ROMCC__ +void w83697hf_set_clksel_48(device_t); +#endif + #endif From gerrit at coreboot.org Wed Nov 2 23:42:37 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:37 +0100 Subject: [coreboot] Patch set updated for coreboot: 6ea0297 implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit 6ea029757eec8814b9587774c64f101d3ad74259 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..35530b4 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,22 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, (pci_read_config8(dev, 0x5c) & ~0x70) | (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Wed Nov 2 23:42:38 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:38 +0100 Subject: [coreboot] Patch set updated for coreboot: 752eb6d add support for setting the vt8237 to uncond. power on after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 752eb6dbf6779c461aac55b12a9407a0f92eac59 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..0e757fe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Wed Nov 2 23:42:39 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:39 +0100 Subject: [coreboot] Patch set updated for coreboot: 8ef90ac implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit 8ef90ac314cea7d02631d62baaa8b2bfd7b076c5 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Wed Nov 2 23:42:40 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:40 +0100 Subject: [coreboot] Patch set updated for coreboot: 957934e support for setting the Memory DQ Drive Strength register in amdk8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit 957934ed3e56437cadc5c99d80149b2c7d35c0b4 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 11288da..d8dcab8 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2193,6 +2193,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; From gerrit at coreboot.org Wed Nov 2 23:42:42 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:42 +0100 Subject: [coreboot] Patch set updated for coreboot: 1f2aab2 fix superiotool for NCT6776F References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/391 -gerrit commit 1f2aab2500227d50b5f5f141207c61b2a3e3e92e Author: Florian Zumbiehl Date: Wed Nov 2 09:46:34 2011 +0100 fix superiotool for NCT6776F The current code exits config mode of the NCT6776F immediately after detection, so the register dump shows all 0xffs. This patch adds code to re-enter config mode for the register dump so that the register contents can be read. Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7 Signed-off-by: Florian Zumbiehl --- util/superiotool/nuvoton.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 6a1a75c..ed2eabc 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -255,7 +255,9 @@ void probe_idregs_nuvoton(uint16_t port) printf("Found Nuvoton %s (id=0x%02x) at 0x%x\n", get_superio_name(reg_table, chip_id), chip_id, port); chip_found = 1; + enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_winbond_fintek_ite_8787(port); return; } From gerrit at coreboot.org Wed Nov 2 23:42:43 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:43 +0100 Subject: [coreboot] Patch set updated for coreboot: 07d3132 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 07d3132dc7c3b71ca1ae9b14ad9d22ca4842c361 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 22 +++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 117 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..31d8564 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,26 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select K8_DQ_DRIVE_STRENGTH_0 + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +44,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +74,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Wed Nov 2 23:42:44 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:44 +0100 Subject: [coreboot] Patch set updated for coreboot: 1bb2ad2 copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit 1bb2ad2b3f93c720ad2cb36cae45c27b772874fa Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Wed Nov 2 23:42:44 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 2 Nov 2011 23:42:44 +0100 Subject: [coreboot] Patch set updated for coreboot: 495a2b3 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 495a2b3456468a92066e32b4e9db2965250ebe16 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From gerrit at coreboot.org Thu Nov 3 06:30:16 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:30:16 +0100 Subject: [coreboot] Patch set updated for coreboot: 99e767b in vt8237r_enable(), write function enables only to ISA bridge config space References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/368 -gerrit commit 99e767bfc0b2c9ee8fac96fbb66644161f0ea39a Author: Florian Zumbiehl Date: Tue Nov 1 20:16:16 2011 +0100 in vt8237r_enable(), write function enables only to ISA bridge config space vt8237r_enable() so far wrote the function enable values to the same offset in the config space of every one of the vt8237's functions, even though the register is located in the ISA bridge only. Change-Id: I639586dc238132f5b8d2f320b794948718281b9c Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/vt8237r.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 5ba3815..586df66 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -66,11 +66,21 @@ void dump_south(device_t dev) static void vt8237r_enable(struct device *dev) { + u16 vid, did; struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; - pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); - pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + if (dev->path.type == DEVICE_PATH_PCI) { + vid = pci_read_config16(dev, PCI_VENDOR_ID); + did = pci_read_config16(dev, PCI_DEVICE_ID); + if (vid == PCI_VENDOR_ID_VIA && + (did == PCI_DEVICE_ID_VIA_VT8237R_LPC || + did == PCI_DEVICE_ID_VIA_VT8237A_LPC || + did == PCI_DEVICE_ID_VIA_VT8237S_LPC)) { + pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); + pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + } + } /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ } From gerrit at coreboot.org Thu Nov 3 06:37:35 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:35 +0100 Subject: [coreboot] Patch set updated for coreboot: b70e085 support for different location of HT registers in old version of K8T800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/373 -gerrit commit b70e085bb55e0ca898733018cc87510628fcff1e Author: Florian Zumbiehl Date: Tue Nov 1 20:17:14 2011 +0100 support for different location of HT registers in old version of K8T800 Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/early_car.c | 30 ++++++++++++++++++++++-------- 1 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index c554c49..da7b4db 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -35,6 +35,12 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#define K8X8XX_HT_CFG_BASE 0xc0 +#else +#define K8X8XX_HT_CFG_BASE 0x60 +#endif + /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init. * This will not work for K8T800_OLD, which has a slightly different @@ -43,10 +49,13 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; u8 k8t890_early_setup_ht(void) { - u8 awidth, afreq, cldtfreq, reg; + u8 awidth, afreq, cldtfreq; u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + u8 reg; + /* hack, enable NVRAM in chipset */ pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); @@ -58,6 +67,7 @@ u8 k8t890_early_setup_ht(void) reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); reg |= 0x1; pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); +#endif /* check if connected non coherent, initcomplete (find the SB on K8 side) */ ldtnr = 0; @@ -73,6 +83,10 @@ u8 k8t890_early_setup_ht(void) print_debug("K8M800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800 print_debug("K8T800 found at LDT "); +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + print_debug("K8T800_OLD found at LDT "); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO print_debug("K8T800 Pro found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8M890 @@ -87,19 +101,19 @@ u8 k8t890_early_setup_ht(void) /* get the maximum widths for both sides */ cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7; - vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7; - vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7; + vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) & 0x7; + vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7; width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); print_debug(" Agreed on width: "); print_debug_hex8(width); - awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7); /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */ width = (width == 0x01) ? 0x11 : 0x00; - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7, width); /* Get programmed HT freq at base 0x89 */ cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; @@ -107,15 +121,15 @@ u8 k8t890_early_setup_ht(void) print_debug_hex8(cldtfreq); print_debug(" VIA HT caps: "); - vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e); + vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe); print_debug_hex16(vldtcaps); if (!(vldtcaps & (1 << cldtfreq ))) { die("Chipset does not support desired HT frequency\n"); } - afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq); + afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq); print_debug("\n"); /* no reset needed */ From gerrit at coreboot.org Thu Nov 3 06:37:47 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:47 +0100 Subject: [coreboot] Patch set updated for coreboot: 1eebc29 add support for writing to SMBus with vt8237 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/372 -gerrit commit 1eebc2948d93462056bfd2690132e18f2e1ed0dc Author: Florian Zumbiehl Date: Tue Nov 1 20:17:13 2011 +0100 add support for writing to SMBus with vt8237 Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/early_smbus.c | 31 +++++++++++++++++++--------- src/southbridge/via/vt8237r/vt8237r.h | 1 + 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index a298e84..e25535b 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -87,17 +87,12 @@ static void smbus_reset(void) PRINT_DEBUG("\n"); } -/** - * Read a byte from the SMBus. - * - * @param dimm The address location of the DIMM on the SMBus. - * @param offset The offset the data is located at. - */ -u8 smbus_read_byte(u8 dimm, u8 offset) +static u8 smbus_transaction(u8 dimm, u8 offset, u8 data, int do_read) { u8 val; - PRINT_DEBUG("DIMM "); + PRINT_DEBUG(do_read ? "RD: " : "WR: "); + PRINT_DEBUG("ADDR "); PRINT_DEBUG_HEX16(dimm); PRINT_DEBUG(" OFFSET "); PRINT_DEBUG_HEX16(offset); @@ -106,13 +101,13 @@ u8 smbus_read_byte(u8 dimm, u8 offset) smbus_reset(); /* Clear host data port. */ - outb(0x00, SMBHSTDAT0); + outb(do_read ? 0x00 : data, SMBHSTDAT0); SMBUS_DELAY(); smbus_wait_until_ready(); /* Actual addr to reg format. */ dimm = (dimm << 1); - dimm |= 1; + dimm |= !!do_read; outb(dimm, SMBXMITADD); outb(offset, SMBHSTCMD); @@ -132,6 +127,22 @@ u8 smbus_read_byte(u8 dimm, u8 offset) return val; } +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 smbus_read_byte(u8 dimm, u8 offset) +{ + return smbus_transaction(dimm, offset, 0, 1); +} + +void smbus_write_byte(u8 dimm, u8 offset, u8 data) +{ + smbus_transaction(dimm, offset, data, 0); +} + #define PSONREADY_TIMEOUT 0x7fffffff static device_t get_vt8237_lpc(void) diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 94b1840..9d5a1fc 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -148,6 +148,7 @@ __attribute__ ((packed)) #ifdef __PRE_RAM__ #ifndef __ROMCC__ u8 smbus_read_byte(u8 dimm, u8 offset); +void smbus_write_byte(u8 dimm, u8 offset, u8 data); void enable_smbus(void); void smbus_fixup(const struct mem_controller *ctrl); // these are in vt8237_early_smbus.c - do they really belong there? From gerrit at coreboot.org Thu Nov 3 06:37:48 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:48 +0100 Subject: [coreboot] Patch set updated for coreboot: 08d627b compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/374 -gerrit commit 08d627bbecef1178921e16b45ed83538c1d35ccd Author: Florian Zumbiehl Date: Tue Nov 1 20:17:41 2011 +0100 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/romstrap.inc | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc index 5b24948..a3814b0 100644 --- a/src/southbridge/via/k8t890/romstrap.inc +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -33,7 +33,7 @@ __romstrap_start: * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ -#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD tblpointer: .long 0x50220000, 0X619707C2 diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index e599517..b1e1afe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_K8T800 + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */ From gerrit at coreboot.org Thu Nov 3 06:37:51 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:51 +0100 Subject: [coreboot] Patch set updated for coreboot: 52522b3 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/370 -gerrit commit 52522b3ff384051595fe209c678937e9c5ed8710 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:12 2011 +0100 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit_f.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 319293b..dc3addb 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i 18, /* *Supported CAS Latencies */ 9, /* *Cycle time at highest CAS Latency CL=X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ - 26, /* *Cycle time at CAS Latency (CLX - 2) */ + 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; u8 common_cl; From gerrit at coreboot.org Thu Nov 3 06:37:52 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:52 +0100 Subject: [coreboot] Patch set updated for coreboot: 68c5545 add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit 68c554550f59bd96caace96260ae2e30ed55ceb4 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, From gerrit at coreboot.org Thu Nov 3 06:37:53 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:53 +0100 Subject: [coreboot] Patch set updated for coreboot: c4c21e6 make w83697hf_set_clksel_48() non-static and add a prototype References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit c4c21e6701b72830ce291197d92e9aeef5395297 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 make w83697hf_set_clksel_48() non-static and add a prototype make w83697hf_set_clksel_48() non-static and add a prototype so as to get rid of warnings about it being unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/early_serial.c | 2 +- src/superio/winbond/w83697hf/w83697hf.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..2825eeb 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(device_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 0eeb37c..6488dd3 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -32,4 +32,8 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ +#ifndef __ROMCC__ +void w83697hf_set_clksel_48(device_t); +#endif + #endif From gerrit at coreboot.org Thu Nov 3 06:37:56 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:56 +0100 Subject: [coreboot] Patch set updated for coreboot: 74e888f add support for setting the vt8237 to uncond. power on after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 74e888f9402d11d52a4053df475cd6c9731c167d Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..0e757fe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Thu Nov 3 06:37:57 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:57 +0100 Subject: [coreboot] Patch set updated for coreboot: caf6207 support for setting the Memory DQ Drive Strength register in amdk8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit caf6207137afddd79b7d3051ccf4139a958f16b5 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit make sure DRAM drive strength is not reduced Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 12 ++++++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 02c764d..e09075f 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2201,6 +2201,18 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + + if (!is_cpu_pre_e0()) { + uint32_t dch; + + // see also erratum 114, essentially: never ever + // set to anything but 0 + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= DCH_DQ_DRV_STRENGTH_0 << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; From gerrit at coreboot.org Thu Nov 3 06:37:59 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:59 +0100 Subject: [coreboot] Patch set updated for coreboot: 8b31a0a k8 raminit: fix bug, improve clock selection, add clock limit for sock754 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit 8b31a0acc8ee489c2020dfa4d48da3623e8e8d76 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 349 +++++++++++++++++------------------ 1 files changed, 166 insertions(+), 183 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..02c764d 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1230,8 +1230,8 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 17, /* *Logical Banks */ 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ - 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 23, /* *Cycle time at CAS Latency (CLX - 0.5) */ + 25, /* *Cycle time at CAS Latency (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,11 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) +{ #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1441,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos = 0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1475,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1484,190 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table + * are to be understood: + */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; + +#else /* CONFIG_CPU_AMD_SOCKET_* */ + +// well, there are socket 940 boards supported which obviously fail to +// compile with this +// #error load dependent memory clock limiting is not implemented for this socket -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ + /* see BKDG 4.1.3--if you just want to test a setup that doesn't + * require limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what + * would be intuitive. 200 MHz has the lowest constant, 100 MHz the + * highest. Thus, all comparisons and traversal directions having to + * do with frequencies are/have to be the opposite of what would be + * intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + // the CLs supported by the controller: + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); + memset(cl_at_freq, 0x00, + (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> + NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle + * shorter, select that (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#if CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1689,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; From gerrit at coreboot.org Thu Nov 3 06:37:59 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:37:59 +0100 Subject: [coreboot] Patch set updated for coreboot: c4442b0 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/376 -gerrit commit c4442b09fe86633117fb38de81ab9a4a0b27a2ed Author: Florian Zumbiehl Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 3583dc3..237272c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1399,7 +1399,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) #define DDR400 (NBCAP_MEMCLK_200MHZ + 1) #define DDR_2T 0x80 -#define DDR_MASK 0x3 +#define DDR_MASK 0x7 #define DDR200_2T (DDR_2T | DDR200) #define DDR333_2T (DDR_2T | DDR333) From gerrit at coreboot.org Thu Nov 3 06:38:00 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:00 +0100 Subject: [coreboot] Patch set updated for coreboot: 5bce613 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit 5bce613dc0082308c8d7212acee73d640ae8ebcd Author: Florian Zumbiehl Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include #include +#ifndef __PRE_RAM__ +#include +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Thu Nov 3 06:38:02 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:02 +0100 Subject: [coreboot] Patch set updated for coreboot: 1b45f67 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/378 -gerrit commit 1b45f67513650eb6ef3885b244422c86bcc1dff4 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 49 ++++++---------------------------- src/southbridge/via/k8t890/dram.c | 18 ++++++------ src/southbridge/via/k8t890/k8x8xx.h | 25 ++++++++++++++++++ 3 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 42676b1..7363510 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -31,31 +31,8 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - if(!devfun3) - die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); + u8 regm3; + struct k8x8xx_vt8237_mirrored_regs mregs; pci_write_config8(dev, 0x70, 0xc2); @@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); + k8x8xx_vt8237_mirrored_regs_fill(&mregs); - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); + pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */ + pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */ + pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */ - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! @@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) regm3 = 0x0; /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F)); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e..294e387 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index a0fb57a..425aaeb 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -21,6 +21,31 @@ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#include +#include #include "k8t890.h" +struct k8x8xx_vt8237_mirrored_regs { + u16 low_top_address; + u8 rom_shadow_ctrl_pg_c, + rom_shadow_ctrl_pg_d, + rom_shadow_ctrl_pg_e_memhole_smi_decoding, + rom_shadow_ctrl_pg_f_memhole, + smm_apic_decoding, + shadow_mem_ctrl; +}; + +static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Thu Nov 3 06:38:03 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:03 +0100 Subject: [coreboot] Patch set updated for coreboot: 919545c make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 919545cd90723e21927793dbd0da9c42e6e2ef61 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index d4f7820..7d7326c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Thu Nov 3 06:38:07 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:07 +0100 Subject: [coreboot] Patch set updated for coreboot: 33220b1 make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 33220b1e4080177f5f78810ab2e0c0630b9e2ebd Author: Florian Zumbiehl Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 0e757fe..d4f7820 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -506,7 +517,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */ From gerrit at coreboot.org Thu Nov 3 06:38:08 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:08 +0100 Subject: [coreboot] Patch set updated for coreboot: ebc5b92 implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit ebc5b921fba6e032f18350a9f62adbc1df2db1f2 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..2bdcf9d 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | + (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | + (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | + (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | + (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, + (pci_read_config8(dev, 0x5c) & ~0x70) | + (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Thu Nov 3 06:38:09 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:09 +0100 Subject: [coreboot] Patch set updated for coreboot: 77ab4aa implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit 77ab4aa21b80760b3505534a62b6d07db50dd50f Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Thu Nov 3 06:38:10 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:10 +0100 Subject: [coreboot] Patch set updated for coreboot: 315999f fix superiotool for NCT6776F References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/391 -gerrit commit 315999f3700f52c724577374237f1a4b6e8508d5 Author: Florian Zumbiehl Date: Wed Nov 2 09:46:34 2011 +0100 fix superiotool for NCT6776F The current code exits config mode of the NCT6776F immediately after detection, so the register dump shows all 0xffs. This patch adds code to re-enter config mode for the register dump so that the register contents can be read. Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7 Signed-off-by: Florian Zumbiehl --- util/superiotool/nuvoton.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 6a1a75c..ed2eabc 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -255,7 +255,9 @@ void probe_idregs_nuvoton(uint16_t port) printf("Found Nuvoton %s (id=0x%02x) at 0x%x\n", get_superio_name(reg_table, chip_id), chip_id, port); chip_found = 1; + enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_winbond_fintek_ite_8787(port); return; } From gerrit at coreboot.org Thu Nov 3 06:38:11 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:11 +0100 Subject: [coreboot] Patch set updated for coreboot: e0abe02 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit e0abe02b52eb149960b746d4e4c07e518d324ca3 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 21 ++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 116 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..6b32ea3 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,25 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +43,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +73,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Thu Nov 3 06:38:13 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:13 +0100 Subject: [coreboot] Patch set updated for coreboot: 4e47e39 copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit 4e47e39367332170e423eabde4ff16e776a9fb59 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Thu Nov 3 06:38:14 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Thu, 3 Nov 2011 06:38:14 +0100 Subject: [coreboot] Patch set updated for coreboot: 63f25b4 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 63f25b440b2cb8d6b246e4870626dfbf75b8e703 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From gerrit at coreboot.org Thu Nov 3 09:48:17 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 3 Nov 2011 09:48:17 +0100 Subject: [coreboot] Patch set updated for coreboot: 2aec95c Add support for A-Open DXPL Plus-U motherboard References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/303 -gerrit commit 2aec95c60ee53e4c7a39d5f553ccf5072a7f50a6 Author: Ky?sti M?lkki Date: Thu Nov 3 10:30:06 2011 +0200 Add support for A-Open DXPL Plus-U motherboard This is an old (pre-2005) entry-level server mainboard. The code is adapted from mainboard/intel/xe7501devkit. Featured chips: - Dual socket604 - E7505 northbridge - 82801DB southbridge (with EHCI debug port) - 82870p2 PCI-X bridge - LPC47M102S-MC super-io - 512kB FWH flash (flashrom does the job well) What works: - Dual-Xeon P4/HT boot with microcode update - RAM: registered ECC DDR266 in dual-channel - PCI-X slot interrupts with ACPI and I/O apic - On-board PCI-X GbE and SCSI - ACPI power-off and wakeup with PME# Notes : - Current ACPI is more or less a mess - Interrupts do not route correctly with PIRQ - MP-table is not implemented - Issues with reboots remain (cold and warm) - Many superio devices are disabled by default - Audio codec is not investigated Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011 Signed-off-by: Ky?sti M?lkki --- src/mainboard/Kconfig | 3 + src/mainboard/aopen/Kconfig | 17 ++ src/mainboard/aopen/dxplplusu/Kconfig | 64 ++++++++ src/mainboard/aopen/dxplplusu/Makefile.inc | 1 + src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl | 86 ++++++++++ src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 70 ++++++++ src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 171 ++++++++++++++++++++ src/mainboard/aopen/dxplplusu/acpi/p64h2.asl | 97 ++++++++++++ src/mainboard/aopen/dxplplusu/acpi/power.asl | 95 +++++++++++ src/mainboard/aopen/dxplplusu/acpi/scsi.asl | 63 ++++++++ src/mainboard/aopen/dxplplusu/acpi/superio.asl | 183 ++++++++++++++++++++++ src/mainboard/aopen/dxplplusu/acpi_tables.c | 165 +++++++++++++++++++ src/mainboard/aopen/dxplplusu/bus.h | 40 +++++ src/mainboard/aopen/dxplplusu/chip.h | 4 + src/mainboard/aopen/dxplplusu/devicetree.cb | 85 ++++++++++ src/mainboard/aopen/dxplplusu/dsdt.asl | 113 +++++++++++++ src/mainboard/aopen/dxplplusu/fadt.c | 166 ++++++++++++++++++++ src/mainboard/aopen/dxplplusu/irq_tables.c | 61 +++++++ src/mainboard/aopen/dxplplusu/mainboard.c | 7 + src/mainboard/aopen/dxplplusu/romstage.c | 97 ++++++++++++ 20 files changed, 1588 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 13032a6..549962f 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -14,6 +14,8 @@ config VENDOR_ADVANTECH bool "Advantech" config VENDOR_AMD bool "AMD" +config VENDOR_AOPEN + bool "AOpen" config VENDOR_ARIMA bool "Arima" config VENDOR_ARTEC_GROUP @@ -131,6 +133,7 @@ source "src/mainboard/abit/Kconfig" source "src/mainboard/advansus/Kconfig" source "src/mainboard/advantech/Kconfig" source "src/mainboard/amd/Kconfig" +source "src/mainboard/aopen/Kconfig" source "src/mainboard/arima/Kconfig" source "src/mainboard/artecgroup/Kconfig" source "src/mainboard/asi/Kconfig" diff --git a/src/mainboard/aopen/Kconfig b/src/mainboard/aopen/Kconfig new file mode 100644 index 0000000..5b5497c --- /dev/null +++ b/src/mainboard/aopen/Kconfig @@ -0,0 +1,17 @@ +if VENDOR_AOPEN + +choice + prompt "Mainboard model" + +config BOARD_AOPEN_DXPLPLUSU + bool "DXPL Plus-U" + +endchoice + +source "src/mainboard/aopen/dxplplusu/Kconfig" + +config MAINBOARD_VENDOR + string + default "AOpen" + +endif # VENDOR_AOPEN diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig new file mode 100644 index 0000000..3b9f2d6 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -0,0 +1,64 @@ +if BOARD_AOPEN_DXPLPLUSU + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7505 + select SOUTHBRIDGE_INTEL_I82870 + select SOUTHBRIDGE_INTEL_I82801DX + select SUPERIO_SMSC_LPC47M10X +# select CACHE_AS_RAM + select ROMCC + select HAVE_HARD_RESET +# select HAVE_PIRQ_TABLE +# select PIRQ_ROUTE + select UDELAY_TSC + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_512 + +config MAINBOARD_DIR + string + default aopen/dxplplusu + +config MAINBOARD_PART_NUMBER + string + default "DXPL Plus-U" + +config DCACHE_RAM_BASE + hex + default 0xcf000 + +config DCACHE_RAM_SIZE + hex + default 0x1000 + +config IRQ_SLOT_COUNT + int + default 12 + +config BOARD_HAS_FADT + bool + default y + +config LOGICAL_CPUS + bool + default n + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x0 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x0 + +endif # BOARD_AOPEN_DXPLPLUSU diff --git a/src/mainboard/aopen/dxplplusu/Makefile.inc b/src/mainboard/aopen/dxplplusu/Makefile.inc new file mode 100644 index 0000000..0f285cd --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Makefile.inc @@ -0,0 +1 @@ +ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl new file mode 100644 index 0000000..0e84d44 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (MBRS) +{ + Name (_HID, EisaId ("PNP0C01")) + Name (_UID, 0x01) + Name (MSBF, ResourceTemplate () + { + /* System memory */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, + MaxNotFixed, Prefetchable, ReadWrite, + 0x0, 0x100000000, 0x400000000, 0x0, 0x0, ,, _Y1C, + AddressRangeMemory, TypeStatic) + + /* Top Of Low Memory */ + Memory32 (ReadOnly, 0x0, 0x0, 0x1, 0x0, _Y1D) + + /* 640kB who wants more? */ + Memory32Fixed (ReadWrite, 0x0, 0xA0000, ) + + /* 64k BIOS bootblock */ + Memory32Fixed (ReadOnly, 0xF0000, 0x10000,) + + /* ISA memory hole 15-16 MB ? */ + /* Memory32Fixed (ReadOnly, 0x100000, 0xF00000,) */ + /* ISA memory hole 14-15 MB ? */ + /* Memory32Fixed (ReadOnly, 0x100000, 0xE00000,) */ + + /* Local APIC */ + Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000,) + }) + + Method (_CRS, 0, NotSerialized) + { + CreateQWordField (MSBF, \_SB.MBRS._Y1C._MIN, MEML) + CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM) + CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM) + + And (\_SB.PCI0.RLAR, 0x03FF, Local1) + Increment (Local1) + If (LGreater (Local1, 0x40)) + { + ShiftLeft (Local1, 0x1A, LELM) + } + + + CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00) + CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01) + CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2) + And (\_SB.PCI0.TOLM, 0xF800, Local1) + ShiftRight (Local1, 0x04, Local1) + Decrement (Local1) + If (LGreater (Local1, 0x10)) + { + Subtract (Local1, 0x0F, Local1) + Store (ShiftLeft (Local1, 0x14), MEM2) + Store (0x01000000, MS00) + Store (MS00, MS01) + } + + Return (MSBF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl new file mode 100644 index 0000000..0effe93 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name (PBRS, ResourceTemplate () +{ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100, ,, ) + + /* System IO */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0, 0x0, 0xffff, 0x0000, 0x10000, ,,, TypeStatic) + IO (Decode16, 0x0CF8, 0x0CF8, 0x08, 0x08, ) + + /* Video RAM */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x000A0000, 0x000BFFFF, + 0x00000000, 0x00020000, ,,, AddressRangeMemory, TypeStatic) + + /* Video ROM */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x000C0000, 0x000C7FFF, + 0x00000000, 0x00008000, ,,, AddressRangeMemory, TypeStatic) + + /* Option ROMs ? */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x000C8000, 0x000DFFFF, + 0x00000000, 0x00018000, ,,, AddressRangeMemory, TypeStatic) + + /* Top Of Lowmemory to IOAPIC */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x02000000, 0xFEBFFFFF, + 0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic) +}) + + +Method (_CRS, 0, NotSerialized) +{ + + /* Top Of Lowmemory to IOAPIC */ + CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML) + CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM) + And (\_SB.PCI0.TOLM, 0xF800, Local1) + ShiftRight (Local1, 0x04, Local1) + ShiftLeft (Local1, 0x14, MEML) + Subtract (0xFEC00000, MEML, LENM) + + Return (PBRS) +} + +Method (_STA, 0, NotSerialized) +{ + Return (0x0F) +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl new file mode 100644 index 0000000..bb8c321 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (USB0) +{ + Name (_ADR, 0x001D0000) + Name (_PRW, Package () { 0x03, 0x05 }) + + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device (USB1) +{ + Name (_ADR, 0x001D0001) + Name (_PRW, Package () { 0x04, 0x05 }) + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device (USB2) +{ + Name (_ADR, 0x001D0002) + Name (_PRW, Package () { 0x0C, 0x05 }) + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device (USB3) +{ + Name (_ADR, 0x001D0007) + Name (_PRW, Package () { 0x0D, 0x05 }) /* PME_B0_STS any 0:1d or 0:1f device */ + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device(PCI5) +{ + Name (_ADR, 0x001E0000) + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + Name (_PRT, Package() { + Package() { 0x0003ffff, 0, 0, 20 }, + Package() { 0x0003ffff, 1, 0, 21 }, + Package() { 0x0003ffff, 2, 0, 22 }, + Package() { 0x0003ffff, 3, 0, 23 }, + }) +} + +Device (ICH0) +{ + Name (_ADR, 0x001F0000) + OperationRegion (D310, PCI_Config, 0x00, 0xFF) + Field (D310, ByteAcc, NoLock, Preserve) + { + Offset (0x40), PBAR, 16, + Offset (0x58), GBAR, 16, + } + + OperationRegion (ACPI, SystemIO, 0x0400, 0xC0) + Field (ACPI, ByteAcc, NoLock, Preserve) + { + Offset (0x00), PS1L,8, PS1H,8, PE1L,8, PE1H,8, + Offset (0x28), GS0L,8, GS0H,8, GSPL,8, GSPH,8, + Offset (0x2C), GE0L,8, GE0H,8, GEPL,8, GEPH,8, + Offset (0xB8), GPLV,8 + } + + Name (MSBF, ResourceTemplate () + { + /* IOAPIC 0 */ + Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,) + + IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO) + IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO) + + /* 8254 legacy irq */ + IO (Decode16, 0x04D0, 0x04D0, 0x02, 0x02,) + + /* reset generator */ + IO (Decode16, 0x0092, 0x0092, 0x01, 0x01, ) + }) + + Method (_CRS, 0, NotSerialized) + { + CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MIN, IOA1) + CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MAX, IOA2) + CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL) + + Store (PBAR, Local0) + If ( Land(Local0, 0x01) ) + { + And (Local0, 0xFFFE, Local0) + Store (Local0, IOA1) + Store (Local0, IOA2) + Store (0x80, IOAL) + } Else { + Store (0x00, IOAL) + } + + CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MIN, IOS1) + CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MAX, IOS2) + CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL) + + Store (GBAR, Local0) + If ( Land(Local0, 0x01) ) { + And (Local0, 0xFFFE, Local0) + Store (Local0, IOS1) + Store (Local0, IOS2) + Store (0x40, IOSL) + } Else { + Store (0x00, IOSL) + } + Return (MSBF) + } + + Device (FWH) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + + Name (MSBG, ResourceTemplate () { + Memory32Fixed (ReadOnly, 0xFFF00000, 0x00080000,) + Memory32Fixed (ReadOnly, 0xFFF80000, 0x00080000,) + }) + + Method (_CRS, 0, NotSerialized) + { + Return (MSBG) + } + } + + Device (SMSC) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) + #include "acpi/superio.asl" + } + +} + + + diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl new file mode 100644 index 0000000..3958699 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Interrupt routing for PCI 03:xx.x */ + +/* I/O APIC id 0x3 */ +Device(PBIO) +{ + Name (_HID, "ACPI000A") + Name (_ADR, 0x001c0000) +} + +/* PCI-X bridge */ +Device(P64B) +{ + Name (_ADR, 0x001d0000) + Name (_PRT, Package() { + Package() { 0x0002ffff, 0, 0, 24 }, /* PCI-X slot 1 */ + Package() { 0x0002ffff, 1, 0, 25 }, + Package() { 0x0002ffff, 2, 0, 26 }, + Package() { 0x0002ffff, 3, 0, 27 }, + Package() { 0x0003ffff, 0, 0, 28 }, /* PCI-X slot 2 */ + Package() { 0x0003ffff, 1, 0, 29 }, + Package() { 0x0003ffff, 2, 0, 30 }, + Package() { 0x0003ffff, 3, 0, 31 }, + Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */ + }) + + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + OperationRegion (PBPC, PCI_Config, 0x00, 0xFF) + Field (PBPC, ByteAcc, NoLock, Preserve) + { + Offset (0x3E), BCRL, 8, BCRH, 8 + } + + + Device (ETH0) + { + Name (_ADR, 0x00040000) + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + } +} + + +/* Interrupt routing for PCI 04:xx.x */ + +/* I/O APIC id 0x4 */ +Device(PAIO) +{ + Name (_HID, "ACPI000A") + Name (_ADR, 0x001e0000) +} + +/* PCI-X bridge */ +Device(P64A) +{ + Name (_ADR, 0x001f0000) + Name (_PRT, Package() { + Package() { 0x0002ffff, 0, 0, 48 }, /* PCI-X slot 3 */ + Package() { 0x0002ffff, 1, 0, 49 }, + Package() { 0x0002ffff, 2, 0, 50 }, + Package() { 0x0002ffff, 3, 0, 51 }, + Package() { 0x0003ffff, 0, 0, 52 }, /* PCI-X slot 4 */ + Package() { 0x0003ffff, 1, 0, 53 }, + Package() { 0x0003ffff, 2, 0, 54 }, + Package() { 0x0003ffff, 3, 0, 55 }, + Package() { 0x0004ffff, 0, 0, 54 }, /* On-board SCSI, GSI not 56 ? */ + Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */ + }) + + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + OperationRegion (PBPC, PCI_Config, 0x00, 0xFF) + Field (PBPC, ByteAcc, NoLock, Preserve) + { + Offset (0x3E), BCRL, 8, BCRH, 8 + } + + #include "acpi/scsi.asl" +} + + diff --git a/src/mainboard/aopen/dxplplusu/acpi/power.asl b/src/mainboard/aopen/dxplplusu/acpi/power.asl new file mode 100644 index 0000000..92db59e --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/power.asl @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* Board powers on with button or PME# from on-board GbE wake-on-lan. + * Board shuts down to S5/G2. Any other power management is untested. + */ + +Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) +Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 }) +Name (\_S3, Package () { 0x05, 0x05, 0x00, 0x00 }) +Name (\_S4, Package () { 0x06, 0x06, 0x00, 0x00 }) +Name (\_S5, Package () { 0x07, 0x07, 0x00, 0x00 }) + +Scope (\_GPE) +{ + Method (_L03, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB0, 0x02) + } + Method (_L04, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB1, 0x02) + } + + /* WOL header */ + Method (_L08, 0, NotSerialized) + { + Notify (\_SB.PCI0.PCI5, 0x02) + Notify (\_SB.SLBT, 0x02) + } + + /* PME# */ + Method (_L0B, 0, NotSerialized) + { +#if 1 + Notify (\_SB.LID0, 0x02) +#else + Notify (\_SB.PCI0.HLIB.P64B.ETH0, 0x02) + Notify (\_SB.PCI0.HLIB.P64B, 0x02) + Notify (\_SB.PCI0.HLIB.P64A, 0x02) +#endif + } + + Method (_L0C, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB2, 0x02) + } + + /* PME_B0_STS# */ + Method (_L0D, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB3, 0x02) + } +} + +/* Clear power buttons */ +Method (\_INI, 0, NotSerialized) +{ + Or (\_SB.PCI0.ICH0.PS1H, 0x09, \_SB.PCI0.ICH0.PS1H) + Or (\_SB.PCI0.ICH0.PE1H, 0x01, \_SB.PCI0.ICH0.PE1H) +} + +/* Prepare To Sleep */ +Method (\_PTS, 1, NotSerialized) +{ + Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H) + Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L) +} + +/* System Wake */ +Method (\_WAK, 1, NotSerialized) +{ + Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H) + Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L) + + Return ( Package() { 0x0, 0x0 } ) +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl new file mode 100644 index 0000000..3ab9b8b --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* PCI-X devices 04:04.0 and 04:04.1 : AIC-7902W + * U320 SCSI dual-channel controller + */ + +Device (SCS0) +{ + Name (_ADR, 0x00040000) + OperationRegion (SCSC, PCI_Config, 0x00, 0x0100) + Field (SCSC, ByteAcc, NoLock, Preserve) + { + Offset (0x2C), SID, 32, + Offset (0xE0), PMC, 8, + Offset (0xFF), IDW, 8 + } +} + +Device (SCS1) +{ + Name (_ADR, 0x00040001) + OperationRegion (SCSC, PCI_Config, 0x00, 0x0100) + Field (SCSC, ByteAcc, NoLock, Preserve) + { + Offset (0x2C), SID, 32, + Offset (0xE0), PMC, 8, + Offset (0xFF), IDW, 8 + } +} + +#if 0 +/* Set subsystem id for both SCSI devices. + * It may require some delay on wake-up before this can be done. + */ + Method ( ) + { + Or (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS0.IDW) + Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS0.SID) + And (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS0.IDW) + + Or (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS1.IDW) + Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS1.SID) + And (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS1.IDW) + } +#endif + diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl new file mode 100644 index 0000000..15b5e08 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/superio.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* SuperIO GPIO configuration via logical device 0x0A */ + +Name (MSBF, ResourceTemplate () +{ + IO (Decode16, 0x0000, 0x0000, 0x01, 0x80, _Y1B) +}) + +OperationRegion (LPC0, SystemIO, 0x0E00, 0x60) +Field (LPC0, ByteAcc, NoLock, Preserve) +{ + PME0, 8, + Offset (0x02), PME2,8, + Offset (0x04), PME4,8, + Offset (0x0A), PMEA,8, + Offset (0x23), + GC10,8, GC11,8, GC12,8, GC13,8, GC14,8, GC15,8, GC16,8, GC17,8, + GC20,8, GC21,8, GC22,8, GC23,8, GC24,8, GC25,8, GC26,8, GC27,8, + GC30,8, GC31,8, GC32,8, GC33,8, GC34,8, GC35,8, GC36,8, GC37,8, + GC40,8, GC41,8, GC42,8, GC43,8, + + Offset (0x3F), + GC50,8, GC51,8, GC52,8, GC53,8, GC54,8, GC55,8, GC56,8, GC57,8, + GC60,8, GC61,8, + + Offset (0x4B), + GP_1,8, GP_2,8, GP_3,8, GP_4,8, GP_5,8, GP_6,8, + Offset (0x56), FAN1,8, + Offset (0x5D), LED1,8, LED2,8, +} + +OperationRegion (SMC1, SystemIO, 0x2E, 0x02) +Field (SMC1, ByteAcc, NoLock, Preserve) +{ + INDX, 8, DATA, 8 +} + +IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) +{ + Offset (0x07), LDN, 8, + Offset (0x22), PWRC, 8, + Offset (0x30), ACTR, 8, + Offset (0x60), + IOAH, 8, IOAL, 8, + IOBH, 8, IOBL, 8, + + Offset (0x70), INTR, 8, + Offset (0x72), INT1, 8, + Offset (0x74), DMCH, 8, + Offset (0xB2), SPS1, 8, SPS2, 8, + Offset (0xB8), D2TS, 8, + Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8, + Offset (0xF4), WDTC, 8, + Offset (0xF6), GP01, 8, GP02, 8, GP04, 8 +} + +Method (ECFG, 0, NotSerialized) +{ + Store (0x55, INDX) +} +Method (XCFG, 0, NotSerialized) +{ + Store (0xAA, INDX) +} + +Method (_CRS, 0, NotSerialized) +{ + CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MIN, IOM1) + CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MAX, IOM2) + CreateByteField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._LEN, IOML) + + ECFG () + Store (0x0A, \_SB.PCI0.ICH0.SMSC.LDN) + Store (0x00, IOM1) + Store (0x00, IOM2) + Or (\_SB.PCI0.ICH0.SMSC.IOAH, IOM1, IOM1) + ShiftLeft (IOM1, 0x08, IOM1) + Or (\_SB.PCI0.ICH0.SMSC.IOAL, IOM1, IOM1) + Store (IOM1, IOM2) + If (LNotEqual (IOM1, 0x00)) + { + Store (0x80, IOML) + } + XCFG () + + Return (MSBF) +} + + +Method (_INI, 0, NotSerialized) +{ + /* GPIO configuration */ + Store (0x00, GC10) + Store (0x81, GC11) + Store (0x00, GC17) + Store (0x0c, GC21) + Store (0x00, GC22) + Store (0x04, GC27) + Store (0x04, GC30) + Store (0x01, GC31) + Store (0x01, GC32) + Store (0x01, GC33) + Store (0x01, GC34) /* GPI password jumper */ + Store (0x01, GC35) /* GPI scsi enable jumper */ +#if 1 + Store (0x01, GC42) /* GPI */ +#else + Store (0x84, GC42) /* nIO_PME */ +#endif + Store (0x86, GC60) /* led 1 */ + Store (0x81, GC61) /* led 2 ?? */ + + /* GPIO initial output levels */ + Store (GP_1, Local0) + And( Local0, 0x7C, Local0) + Or ( Local0, 0x81, Local0) + Store (Local0, GP_1) + + Store (GP_2, Local0) + And( Local0, 0xFE, Local0) + Or ( Local0, 0x00, Local0) + Store (Local0, GP_2) + + Store (GP_3, Local0) + And( Local0, 0x7F, Local0) + Or ( Local0, 0x80, Local0) + Store (Local0, GP_3) + + Store (GP_4, Local0) + And( Local0, 0x7F, Local0) + Or ( Local0, 0x00, Local0) + Store (Local0, GP_4) + + /* Power Led */ + Store (LED1, Local0) + And( Local0, 0xfc, Local0) + Or ( Local0, 0x01, Local0) + Store (Local0, LED1) + +} + +Method (MLED, 1, NotSerialized) +{ + If (LEqual (Arg0, 0x00)) + { + Store (0x00, LED1) + } + + If (LOr (LEqual (Arg0, 0x01), LEqual (Arg0, 0x02))) + { + Store (0x01, LED1) + } + + If (LEqual (Arg0, 0x03)) + { + Store (0x02, LED1) + } + + If (LOr (LEqual (Arg0, 0x04), LEqual (Arg0, 0x05))) + { + Store (0x03, LED1) + } +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c new file mode 100644 index 0000000..a3bc766 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer + * (C) 2005 Stefan Reinauer + * (C) 2005 Digital Design Corporation + * + * Ported to Intel XE7501DEVKIT by Agami Aruma + * Ported to AOpen DXPL Plus-U by Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "bus.h" + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int irq_start = 0; + device_t dev = 0; + struct resource* res = NULL; + + // SJM: Hard-code CPU LAPIC entries for now + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7); + + // Southbridge IOAPIC + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + + // P64H2 Bus B IOAPIC + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); + if (!dev) + BUG(); // Config.lb error? + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + + // P64H2 Bus A IOAPIC + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); + if (!dev) + BUG(); // Config.lb error? + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + + + // Map ISA IRQ 0 to IRQ 2 + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0); + + // IRQ9 differs from ISA standard - ours is active high, level-triggered + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD); + + return current; +} + +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_facs_t *facs; + acpi_fadt_t *fadt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current+=madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp,madt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + memcpy(dsdt,(void *)AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + ALIGN_CURRENT; + memcpy(dsdt,(void *)AmlCode, dsdt->length); + + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt,dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdp,fadt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} + diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h new file mode 100644 index 0000000..9afe10c --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/bus.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DXPLPLUSU_BUS_H_INCLUDED +#define DXPLPLUSU_BUS_H_INCLUDED + +// These were determined by seeing how coreboot enumerates the various +// PCI (and PCI-like) buses on the board. + +#define PCI_BUS_ROOT 0 +#define PCI_BUS_AGP 1 // AGP +#define PCI_BUS_E7501_HI_B 2 // P64H2#1 +#define PCI_BUS_P64H2_B 3 // P64H2#1 bus B +#define PCI_BUS_P64H2_A 4 // P64H2#1 bus A +#define PCI_BUS_ICH4 5 // ICH4 + +// IOAPIC addresses determined by coreboot enumeration. +// Someday add functions to get APIC IDs and versions from the chips themselves. + +#define IOAPIC_ICH4 2 +#define IOAPIC_P64H2_BUS_B 3 // IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 +#define IOAPIC_P64H2_BUS_A 4 // IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 + +#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-4 and P64-H2 + +#endif diff --git a/src/mainboard/aopen/dxplplusu/chip.h b/src/mainboard/aopen/dxplplusu/chip.h new file mode 100644 index 0000000..06f11d0 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config { +}; diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb new file mode 100644 index 0000000..a4cd9a8 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -0,0 +1,85 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/e7505 + + device lapic_cluster 0 on + chip cpu/intel/socket_mPGA604 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 0.0 on end # Chipset host controller + device pci 0.1 on end # Host RASUM controller + device pci 2.0 on # Hub interface B + chip southbridge/intel/i82870 # P64H2 + device pci 1c.0 on end # IOAPIC - bus B + device pci 1d.0 on end # Hub to PCI-B bridge + device pci 1e.0 on end # IOAPIC - bus A + device pci 1f.0 on end # Hub to PCI-A bridge + end + end + device pci 4.0 off end # (undocumented) + device pci 6.0 off end # (undocumented) + chip southbridge/intel/i82801dx + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.7 on end # USB EHCI + device pci 1e.0 on # Hub to PCI bridge + device pci 2.0 off end + end + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47m10x + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.a on # ACPI + io 0x60 = 0x0e00 + end + end + end + device pci 1f.1 on end # IDE + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # AC97 Audio + device pci 1f.6 off end # AC97 Modem + end # SB + end # PCI_DOMAIN +end diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl new file mode 100644 index 0000000..31cfa88 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x04, // DSDT revision: ACPI v4.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20111103 // OEM revision +) { + +Scope(\_SB) +{ + Device(PCI0) { + Name (_HID, EISAID("PNP0A03")) + Name (_ADR, 0x00) + Name (_PRT, Package() { + Package() { 0x001dffff, 0, 0, 16 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 23 }, + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 17 }, + }) + + #include "acpi/e7505_sec.asl" + + OperationRegion (I750, PCI_Config, 0x00, 0x0100) + Field (I750, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), + TOLM, 16, /* Top of Low Memory */ + RBAR, 16, /* REMAP_BASE */ + RLAR, 16 /* REMAP_LIMIT */ + } + } + + #include "acpi/e7505_pri.asl" + + + Device (PWBT) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { 0x08, 0x05 }) + } + + Device (SLBT) + { + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { 0x0B, 0x05 }) + } + + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { 0x0B, 0x05 }) + } + +} + +Scope(\_SB.PCI0) +{ + + Device(PCI1) + { + Name (_ADR, 0x00010000) + Name (_PRT, Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + }) + } + + Device(HLIB) + { + Name (_ADR, 0x00020000) + Name (_PRT, Package() { + Package() { 0x001dffff, 0, 0, 18 }, + Package() { 0x001dffff, 1, 0, 18 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 18 }, + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 18 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + + #include "acpi/p64h2.asl" + } + + #include "acpi/i82801db.asl" +} + +#include "acpi/power.asl" + +} + diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c new file mode 100644 index 0000000..8db121e --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ +#define APM_CNT 0x0 /* ACPI mode only */ +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x0 +#define ACPI_DISABLE 0xAA +#define ACPI_ENABLE 0x55 +#define S4_BIOS 0x77 +#define GNVS_UPDATE 0xea + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->s4bios_req = S4_BIOS; + fadt->pstate_cnt = PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; /* CST_CONTROL; */ + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/aopen/dxplplusu/irq_tables.c b/src/mainboard/aopen/dxplplusu/irq_tables.c new file mode 100644 index 0000000..73294c4 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/irq_tables.c @@ -0,0 +1,61 @@ +/* Run checkpir to verify any changes to this table... + Documentation at : http://www.microsoft.com/whdc/archive/pciirq.mspx +*/ + +#include +#include +#include +#include "bus.h" + +#define UNUSED_INTERRUPT {0, 0} +#define PIRQ_A 0x60 +#define PIRQ_B 0x61 +#define PIRQ_C 0x62 +#define PIRQ_D 0x63 +#define PIRQ_E 0x68 +#define PIRQ_F 0x69 +#define PIRQ_G 0x6A +#define PIRQ_H 0x6B + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, // Size of this struct in bytes + 0, // PCI bus number on which the interrupt router resides + PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router + 0, // PCI-exclusive IRQ bitmap + PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router + PCI_DEVICE_ID_INTEL_82801DB_LPC, // Device ID of compatible PCI interrupt router + 0, // Additional miniport information + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero + 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0) + { + // NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space + // This was determined from linux-2.6.11/arch/i386/pci/irq.c + // bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 + // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 + // Not sure why IRQ9 isn't routable (inherited from Tyan S2735) + + // INTA# INTB# INTC# INTD# + // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu + + {PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus + {PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // USB 1.1 + + {PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // GbE + + {PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // SCSI + + {PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // 32-bit slot + + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/aopen/dxplplusu/mainboard.c b/src/mainboard/aopen/dxplplusu/mainboard.c new file mode 100644 index 0000000..2d41509 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/mainboard.c @@ -0,0 +1,7 @@ +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("AOpen DXPL Plus-U Mainboard") +}; + diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c new file mode 100644 index 0000000..6a4cfc2 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/early_smbus.c" +#include "southbridge/intel/i82801dx/reset.c" +#include "northbridge/intel/e7505/raminit.h" +#include "northbridge/intel/e7505/debug.c" +#include "superio/smsc/lpc47m10x/early_serial.c" + +#if !CONFIG_CACHE_AS_RAM +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#endif +#include "cpu/x86/bist.h" + +#include + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#if CONFIG_CACHE_AS_RAM +#define BOARD_MAIN(x) void main(x) +#define early_mtrr_init() do {} while (0) +#else +#define BOARD_MAIN(x) static void main(x) +#endif + +#include "northbridge/intel/e7505/raminit.c" +#include "northbridge/intel/e7505/reset_test.c" +#include "lib/generic_sdram.c" + +// This function MUST appear last (ROMCC limitation) +BOARD_MAIN(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .d0f1 = PCI_DEV(0, 0, 1), + .channel0 = { 0x50, 0x52, 0, 0 }, + .channel1 = { 0x51, 0x53, 0, 0 }, + }, + }; + + if (bist == 0) { + // Skip this if there was a built in self test failure + early_mtrr_init(); + enable_lapic(); + } + + // Get the serial port running and print a welcome banner + lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + // Halt if there was a built in self test failure + report_bist_failure(bist); + + // If this is a warm boot, some initialization can be skipped + if (!bios_reset_detected()) { + enable_smbus(); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); + } + + // NOTE: ROMCC dies with an internal compiler error + // if the following line is removed. + print_debug("SDRAM is up.\r\n"); + +} From gerrit at coreboot.org Thu Nov 3 12:18:40 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Thu, 3 Nov 2011 12:18:40 +0100 Subject: [coreboot] New patch to review for coreboot: 02418b7 libpayload: Reduce verbosity in USB stack References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/393 -gerrit commit 02418b7f4316fc8b3f0ba48a853d5dce702cff08 Author: Mathias Krause Date: Wed Jun 8 15:36:55 2011 +0200 libpayload: Reduce verbosity in USB stack The USB stack is pretty noisy. Reduce the output to a sane level. Change-Id: I250949e5cf74a8c6d43822b2e7487143b2ae1c65 Signed-off-by: Mathias Krause --- payloads/libpayload/drivers/usb/ehci.c | 8 ++-- payloads/libpayload/drivers/usb/ehci_rh.c | 8 ++-- payloads/libpayload/drivers/usb/uhci.c | 42 +++++++++++----------- payloads/libpayload/drivers/usb/uhci_rh.c | 4 +- payloads/libpayload/drivers/usb/usb.c | 54 ++++++++++++++-------------- payloads/libpayload/drivers/usb/usbhid.c | 8 ++--- payloads/libpayload/drivers/usb/usbinit.c | 16 ++++---- payloads/libpayload/drivers/usb/usbmsc.c | 27 +++++++------- payloads/libpayload/include/usb/usb.h | 4 +- 9 files changed, 85 insertions(+), 86 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index d979121..f258e07 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -34,9 +34,9 @@ static void dump_td(u32 addr) { qtd_t *td = phys_to_virt(addr); - printf("td at phys(%x): active: %x, halted: %x, data_buf_err: %x\n babble: %x, xact_err: %x, missed_mframe: %x\n splitxstate: %x, perr: %x\n\n", + debug("td at phys(%x): active: %x, halted: %x, data_buf_err: %x\n babble: %x, xact_err: %x, missed_mframe: %x\n splitxstate: %x, perr: %x\n\n", addr, td->active, td->halted, td->data_buf_err, td->babble, td->xact_err, td->missed_mframe, td->splitxstate, td->perr); - printf("- cerr: %x, total_len: %x\n\n", td->cerr, td->total_len); + debug("- cerr: %x, total_len: %x\n\n", td->cerr, td->total_len); } static void ehci_start (hci_t *controller) @@ -122,7 +122,7 @@ int wait_for_tds(qtd_t *head) if (cur->halted) { printf("ERROR with packet\n"); dump_td(virt_to_phys(cur)); - printf("-----------------\n"); + debug("-----------------\n"); return 1; } if (cur->next_qtd & 1) { @@ -130,7 +130,7 @@ int wait_for_tds(qtd_t *head) } if (0) dump_td(virt_to_phys(cur)); /* helps debugging the TD chain */ - if (0) printf("\nmoving from %x to %x\n", cur, phys_to_virt(cur->next_qtd)); + if (0) debug("\nmoving from %x to %x\n", cur, phys_to_virt(cur->next_qtd)); cur = phys_to_virt(cur->next_qtd); } return result; diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 5f0db94..22476c1 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -56,7 +56,7 @@ ehci_rh_hand_over_port (usbdev_t *dev, int port) volatile portsc_t *p = &(RH_INST(dev)->ports[port]); volatile portsc_t tmp; - printf("giving up port %x, it's USB1\n", port+1); + debug("giving up port %x, it's USB1\n", port+1); /* Lowspeed device. Hand over to companion */ tmp = *p; @@ -76,7 +76,7 @@ ehci_rh_scanport (usbdev_t *dev, int port) volatile portsc_t *p = &(RH_INST(dev)->ports[port]); volatile portsc_t tmp; if (RH_INST(dev)->devices[port]!=-1) { - printf("Unregister device at port %x\n", port+1); + debug("Unregister device at port %x\n", port+1); usb_detach_device(dev->controller, RH_INST(dev)->devices[port]); RH_INST(dev)->devices[port]=-1; } @@ -109,7 +109,7 @@ ehci_rh_scanport (usbdev_t *dev, int port) ehci_rh_hand_over_port(dev, port); return; } - printf("port %x hosts a USB2 device\n", port+1); + debug("port %x hosts a USB2 device\n", port+1); RH_INST(dev)->devices[port] = usb_attach_device(dev->controller, dev->address, port, 2); } /* RW/C register, so clear it by writing 1 */ @@ -153,7 +153,7 @@ ehci_rh_init (usbdev_t *dev) RH_INST(dev)->n_ports = EHCI_INST(dev->controller)->capabilities->n_ports; RH_INST(dev)->ports = EHCI_INST(dev->controller)->operation->portsc; - printf("root hub has %x ports\n", RH_INST(dev)->n_ports); + debug("root hub has %x ports\n", RH_INST(dev)->n_ports); RH_INST(dev)->devices = malloc(RH_INST(dev)->n_ports * sizeof(int)); for (i=0; i < RH_INST(dev)->n_ports; i++) { diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index 1f80c6a..4484e17 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -50,14 +50,14 @@ static u8* uhci_poll_intr_queue (void *queue); static void uhci_dump (hci_t *controller) { - printf ("dump:\nUSBCMD: %x\n", uhci_reg_read16 (controller, USBCMD)); - printf ("USBSTS: %x\n", uhci_reg_read16 (controller, USBSTS)); - printf ("USBINTR: %x\n", uhci_reg_read16 (controller, USBINTR)); - printf ("FRNUM: %x\n", uhci_reg_read16 (controller, FRNUM)); - printf ("FLBASEADD: %x\n", uhci_reg_read32 (controller, FLBASEADD)); - printf ("SOFMOD: %x\n", uhci_reg_read8 (controller, SOFMOD)); - printf ("PORTSC1: %x\n", uhci_reg_read16 (controller, PORTSC1)); - printf ("PORTSC2: %x\n", uhci_reg_read16 (controller, PORTSC2)); + debug ("dump:\nUSBCMD: %x\n", uhci_reg_read16 (controller, USBCMD)); + debug ("USBSTS: %x\n", uhci_reg_read16 (controller, USBSTS)); + debug ("USBINTR: %x\n", uhci_reg_read16 (controller, USBINTR)); + debug ("FRNUM: %x\n", uhci_reg_read16 (controller, FRNUM)); + debug ("FLBASEADD: %x\n", uhci_reg_read32 (controller, FLBASEADD)); + debug ("SOFMOD: %x\n", uhci_reg_read8 (controller, SOFMOD)); + debug ("PORTSC1: %x\n", uhci_reg_read16 (controller, PORTSC1)); + debug ("PORTSC2: %x\n", uhci_reg_read16 (controller, PORTSC2)); } #endif @@ -80,21 +80,21 @@ td_dump (td_t *td) sprintf(td_value, "%x", td->pid); td_type=td_value; } - printf ("%s packet (at %lx) to %x.%x failed\n", td_type, + debug ("%s packet (at %lx) to %x.%x failed\n", td_type, virt_to_phys (td), td->dev_addr, td->endp); - printf ("td (counter at %x) returns: ", td->counter); - printf (" bitstuff err: %x, ", td->status_bitstuff_err); - printf (" CRC err: %x, ", td->status_crc_err); - printf (" NAK rcvd: %x, ", td->status_nakrcvd); - printf (" Babble: %x, ", td->status_babble); - printf (" Data Buffer err: %x, ", td->status_databuf_err); - printf (" Stalled: %x, ", td->status_stalled); - printf (" Active: %x\n", td->status_active); + debug ("td (counter at %x) returns: ", td->counter); + debug (" bitstuff err: %x, ", td->status_bitstuff_err); + debug (" CRC err: %x, ", td->status_crc_err); + debug (" NAK rcvd: %x, ", td->status_nakrcvd); + debug (" Babble: %x, ", td->status_babble); + debug (" Data Buffer err: %x, ", td->status_databuf_err); + debug (" Stalled: %x, ", td->status_stalled); + debug (" Active: %x\n", td->status_active); if (td->status_babble) - printf (" Babble because of %s\n", + debug (" Babble because of %s\n", td->status_bitstuff_err ? "host" : "device"); if (td->status_active) - printf (" still active - timeout?\n"); + debug (" still active - timeout?\n"); } static void @@ -112,7 +112,7 @@ uhci_reset (hci_t *controller) uhci_reg_write32 (controller, FLBASEADD, (u32) virt_to_phys (UHCI_INST (controller)-> framelistptr)); - //printf ("framelist at %p\n",UHCI_INST(controller)->framelistptr); + //debug ("framelist at %p\n",UHCI_INST(controller)->framelistptr); /* disable irqs */ uhci_reg_write16 (controller, USBINTR, 0); @@ -367,7 +367,7 @@ uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen if (td == 0) { result = 0; } else { - printf ("control packet, req %x\n", req); + debug ("control packet, req %x\n", req); td_dump (td); result = 1; } diff --git a/payloads/libpayload/drivers/usb/uhci_rh.c b/payloads/libpayload/drivers/usb/uhci_rh.c index cf5d5a7..bd3fb42 100644 --- a/payloads/libpayload/drivers/usb/uhci_rh.c +++ b/payloads/libpayload/drivers/usb/uhci_rh.c @@ -49,7 +49,7 @@ uhci_rh_enable_port (usbdev_t *dev, int port) else if (port == 2) port = PORTSC2; else { - printf("Invalid port %d\n", port); + debug("Invalid port %d\n", port); return; } @@ -94,7 +94,7 @@ uhci_rh_scanport (usbdev_t *dev, int port) portsc = PORTSC2; offset = 1; } else { - printf("Invalid port %d\n", port); + debug("Invalid port %d\n", port); return; } int devno = RH_INST (dev)->port[offset]; diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index d5f47e4..6995cef 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -91,7 +91,7 @@ void init_device_entry (hci_t *controller, int i) { if (controller->devices[i] != 0) - printf("warning: device %d reassigned?\n", i); + debug("warning: device %d reassigned?\n", i); controller->devices[i] = malloc(sizeof(usbdev_t)); controller->devices[i]->controller = controller; controller->devices[i]->address = -1; @@ -145,7 +145,7 @@ get_descriptor (usbdev_t *dev, unsigned char bmRequestType, int descType, dr.wIndex = langID; dr.wLength = 8; if (dev->controller->control (dev, IN, sizeof (dr), &dr, 8, buf)) { - printf ("getting descriptor size (type %x) failed\n", + debug ("getting descriptor size (type %x) failed\n", descType); } @@ -169,7 +169,7 @@ get_descriptor (usbdev_t *dev, unsigned char bmRequestType, int descType, dr.wLength = size; if (dev->controller-> control (dev, IN, sizeof (dr), &dr, size, result)) { - printf ("getting descriptor (type %x, size %x) failed\n", + debug ("getting descriptor (type %x, size %x) failed\n", descType, size); } @@ -218,7 +218,7 @@ get_free_address (hci_t *controller) if (controller->devices[i] == 0) return i; } - printf ("no free address found\n"); + debug ("no free address found\n"); return -1; // no free address } @@ -251,7 +251,7 @@ set_address (hci_t *controller, int speed) dev->endpoints[0].direction = SETUP; mdelay (50); if (dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0)) { - printf ("set_address failed\n"); + debug ("set_address failed\n"); return -1; } mdelay (50); @@ -260,7 +260,7 @@ set_address (hci_t *controller, int speed) (device_to_host, standard_type, dev_recp), 1, 0, 0); dd = (device_descriptor_t *) dev->descriptor; - printf ("device 0x%04x:0x%04x is USB %x.%x ", + printf ("* found device (0x%04x:0x%04x, USB %x.%x)", dd->idVendor, dd->idProduct, dd->bcdUSB >> 8, dd->bcdUSB & 0xff); dev->quirks = usb_quirk_check(dd->idVendor, dd->idProduct); @@ -364,70 +364,70 @@ set_address (hci_t *controller, int speed) wireless_device = 0xe0, misc_device = 0xef, }; - + printf(", class: "); switch (class) { case audio_device: - printf("(Audio)\n"); + printf("audio\n"); break; case comm_device: - printf("(Communication)\n"); + printf("communication\n"); break; case hid_device: - printf ("(HID)\n"); + printf ("HID\n"); #ifdef CONFIG_USB_HID controller->devices[adr]->init = usb_hid_init; #else - printf ("NOTICE: USB HID support not compiled in\n"); + debug ("NOTICE: USB HID support not compiled in\n"); #endif break; case physical_device: - printf("(Physical)\n"); + printf("physical\n"); break; case imaging_device: - printf("(Camera)\n"); + printf("camera\n"); break; case printer_device: - printf("(Printer)\n"); + printf("printer\n"); break; case msc_device: - printf ("(MSC)\n"); + printf ("MSC\n"); #ifdef CONFIG_USB_MSC controller->devices[adr]->init = usb_msc_init; #else - printf ("NOTICE: USB MSC support not compiled in\n"); + debug ("NOTICE: USB MSC support not compiled in\n"); #endif break; case hub_device: - printf ("(Hub)\n"); + printf ("hub\n"); #ifdef CONFIG_USB_HUB controller->devices[adr]->init = usb_hub_init; #else - printf ("NOTICE: USB hub support not compiled in.\n"); + debug ("NOTICE: USB hub support not compiled in.\n"); #endif break; case cdc_device: - printf("(CDC)\n"); + printf("CDC\n"); break; case ccid_device: - printf ("(Smart Card / CCID)\n"); + printf("smartcard / CCID\n"); break; case security_device: - printf("(Content Security)\n"); + printf("content security\n"); break; case video_device: - printf("(Video)\n"); + printf("video\n"); break; case healthcare_device: - printf("(Healthcare)\n"); + printf("healthcare\n"); break; case diagnostic_device: - printf("(Diagnostic)\n"); + printf("diagnostic\n"); break; case wireless_device: - printf("(Wireless)\n"); + printf("wireless\n"); break; default: - printf ("(unsupported class %x)\n", class); + printf("unsupported class %x\n", class); break; } return adr; @@ -445,7 +445,7 @@ int usb_attach_device(hci_t *controller, int hubaddress, int port, int speed) { static const char* speeds[] = { "full", "low", "high" }; - printf ("%sspeed device\n", (speed <= 2) ? speeds[speed] : "invalid value - no"); + debug ("%sspeed device\n", (speed <= 2) ? speeds[speed] : "invalid value - no"); int newdev = set_address (controller, speed); if (newdev == -1) return -1; diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c index bf3ec1e..57f60cf 100644 --- a/payloads/libpayload/drivers/usb/usbhid.c +++ b/payloads/libpayload/drivers/usb/usbhid.c @@ -37,9 +37,7 @@ typedef enum { hid_proto_boot = 0, hid_proto_report = 1 } hid_proto; enum { hid_boot_proto_none = 0, hid_boot_proto_keyboard = 1, hid_boot_proto_mouse = 2 }; -#ifdef USB_DEBUG static const char *boot_protos[3] = { "(none)", "keyboard", "mouse" }; -#endif enum { GET_REPORT = 0x1, GET_IDLE = 0x2, GET_PROTOCOL = 0x3, SET_REPORT = 0x9, SET_IDLE = 0xa, SET_PROTOCOL = 0xb }; @@ -394,7 +392,7 @@ static int usb_hid_set_layout (const char *country) return 0; } - printf("Keyboard layout '%s' not found, using '%s'\n", + printf(" Keyboard layout '%s' not found, using '%s'\n", country, map->country); /* Nothing found, not changed */ @@ -438,7 +436,7 @@ usb_hid_init (usbdev_t *dev) /* 35 countries defined: */ if (countrycode > 35) countrycode = 0; - printf (" Keyboard has %s layout (country code %02x)\n", + debug (" Keyboard has %s layout (country code %02x)\n", countries[countrycode][0], countrycode); /* Set keyboard layout accordingly */ @@ -464,7 +462,7 @@ usb_hid_init (usbdev_t *dev) debug (" configuration done.\n"); break; case hid_boot_proto_mouse: - printf("NOTICE: USB mice are not supported.\n"); + debug("NOTICE: USB mice are not supported.\n"); break; } } diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index d3cfbb7..3964197 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -72,38 +72,38 @@ usb_controller_initialize (int bus, int dev, int func) pciid >> 16, pciid & 0xFFFF, func); switch(prog_if) { case 0x00: - printf ("UHCI controller\n"); #ifdef CONFIG_USB_UHCI + printf ("UHCI controller\n"); uhci_init (addr); #else - printf ("Not supported.\n"); + printf ("UHCI controller (not supported)\n"); #endif break; case 0x10: - printf ("OHCI controller\n"); #ifdef CONFIG_USB_OHCI + printf ("OHCI controller\n"); ohci_init(addr); #else - printf ("Not supported.\n"); + printf ("OHCI controller (not supported)\n"); #endif break; case 0x20: - printf ("EHCI controller\n"); #ifdef CONFIG_USB_EHCI + printf ("EHCI controller\n"); ehci_init(addr); #else - printf ("Not supported.\n"); + printf ("EHCI controller (not supported)\n"); #endif break; case 0x30: - printf ("xHCI controller\n"); #ifdef CONFIG_USB_XHCI + printf ("xHCI controller\n"); xhci_init(addr); #else - printf ("Not supported.\n"); + printf ("xHCI controller (not supported)\n"); #endif break; diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 6658f2c..729bf91 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -343,7 +343,7 @@ read_capacity (usbdev_t *dev) cb.command = 0x25; // read capacity u8 buf[8]; - printf ("Reading capacity of mass storage device.\n"); + debug ("Reading capacity of mass storage device.\n"); int count = 0; while ((count++ < 20) && @@ -352,15 +352,16 @@ read_capacity (usbdev_t *dev) 8) == 1)); if (count >= 20) { // still not successful, assume 2tb in 512byte sectors, which is just the same garbage as any other number, but probably more usable. - printf ("Assuming 2TB in 512byte sectors as READ CAPACITY didn't answer.\n"); + printf (" assuming 2 TB with 512-byte sectors as READ CAPACITY didn't answer.\n"); MSC_INST (dev)->numblocks = 0xffffffff; MSC_INST (dev)->blocksize = 512; } else { MSC_INST (dev)->numblocks = ntohl (*(u32 *) buf) + 1; MSC_INST (dev)->blocksize = ntohl (*(u32 *) (buf + 4)); } - printf (" has %d blocks sized %db\n", MSC_INST (dev)->numblocks, - MSC_INST (dev)->blocksize); + printf (" %d %d-byte sectors (%d MB)\n", MSC_INST (dev)->numblocks, + MSC_INST (dev)->blocksize, + MSC_INST (dev)->numblocks * MSC_INST (dev)->blocksize / 1000 / 1000); } void @@ -376,9 +377,9 @@ usb_msc_init (usbdev_t *dev) interface_descriptor_t *interface = (interface_descriptor_t *) (((char *) cd) + cd->bLength); - printf (" it uses %s command set\n", + debug (" it uses %s command set\n", msc_subclass_strings[interface->bInterfaceSubClass]); - printf (" it uses %s protocol\n", + debug (" it uses %s protocol\n", msc_protocol_strings[interface->bInterfaceProtocol]); @@ -420,13 +421,13 @@ usb_msc_init (usbdev_t *dev) fatal ("couldn't find bulk-in endpoint"); if (MSC_INST (dev)->bulk_out == 0) fatal ("couldn't find bulk-out endpoint"); - printf (" using endpoint %x as in, %x as out\n", + debug (" using endpoint %x as in, %x as out\n", MSC_INST (dev)->bulk_in->endpoint, MSC_INST (dev)->bulk_out->endpoint); - printf (" has %d luns\n", get_max_luns (dev) + 1); + debug (" has %d luns\n", get_max_luns (dev) + 1); - printf (" Waiting for device to become ready... "); + printf (" Waiting for device to become ready..."); timeout = 30 * 10; /* SCSI/ATA specs say we have to wait up to 30s. Ugh */ while (test_unit_ready (dev) && --timeout) { mdelay (100); @@ -439,16 +440,16 @@ usb_msc_init (usbdev_t *dev) printf ("ok.\n"); } - printf (" spin up"); + debug (" spin up"); for (i = 0; i < 30; i++) { - printf ("."); + debug ("."); if (!spin_up (dev)) { - printf (" OK."); + debug (" OK."); break; } mdelay (100); } - printf ("\n"); + debug ("\n"); read_capacity (dev); if (usbdisk_create) diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index daad493..2cd9c55 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -252,9 +252,9 @@ int usb_interface_check(u16 vendor, u16 device); #define USB_QUIRK_NONE 0 #ifdef USB_DEBUG -#define debug(x...) printf(x); +# define debug(fmt, ...) printf(fmt, ##__VA_ARGS__) #else -#define debug(x...) +# define debug(fmt, ...) while (0) { printf(fmt, ##__VA_ARGS__); } #endif void usb_fatal(const char *message) __attribute__ ((noreturn)); From gerrit at coreboot.org Thu Nov 3 12:18:55 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Thu, 3 Nov 2011 12:18:55 +0100 Subject: [coreboot] New patch to review for coreboot: 2daa28a libpayload: Put coreboot version into lib_sysinfo References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/394 -gerrit commit 2daa28a3b187d92eb9ad11534f6b96e65e83225f Author: Mathias Krause Date: Thu Oct 20 14:06:26 2011 +0200 libpayload: Put coreboot version into lib_sysinfo Change-Id: I22319efe90e475c66b9556f734a7a5e54f7c59bc Signed-off-by: Patrick Georgi --- payloads/libpayload/arch/i386/coreboot.c | 9 +++++++++ payloads/libpayload/include/sysinfo.h | 2 ++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index bdef4e8..365445e 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -82,6 +82,12 @@ static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info) info->ser_ioport = ser->baseaddr; } +static void cb_parse_version(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_string *ver = (struct cb_string *)ptr; + info->cb_version = (char *)ver->string; +} + #ifdef CONFIG_NVRAM static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info) { @@ -148,6 +154,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_SERIAL: cb_parse_serial(ptr, info); break; + case CB_TAG_VERSION: + cb_parse_version(ptr, info); + break; #ifdef CONFIG_NVRAM case CB_TAG_CMOS_OPTION_TABLE: cb_parse_optiontable(ptr, info); diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index e357704..c1d2002 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -51,6 +51,8 @@ struct sysinfo_t { u32 cmos_range_end; u32 cmos_checksum_location; + char *cb_version; + struct cb_framebuffer *framebuffer; unsigned long *mbtable; /** Pointer to the multiboot table */ From gerrit at coreboot.org Thu Nov 3 13:57:47 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 3 Nov 2011 13:57:47 +0100 Subject: [coreboot] Patch merged into coreboot/master: 315999f fix superiotool for NCT6776F References: Message-ID: the following patch was just integrated into master: commit 315999f3700f52c724577374237f1a4b6e8508d5 Author: Florian Zumbiehl Date: Wed Nov 2 09:46:34 2011 +0100 fix superiotool for NCT6776F The current code exits config mode of the NCT6776F immediately after detection, so the register dump shows all 0xffs. This patch adds code to re-enter config mode for the register dump so that the register contents can be read. Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7 Signed-off-by: Florian Zumbiehl Reviewed-By: Patrick Georgi at Thu Nov 3 13:57:46 2011, giving +2 See http://review.coreboot.org/391 for details. -gerrit From gerrit at coreboot.org Thu Nov 3 14:33:44 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 3 Nov 2011 14:33:44 +0100 Subject: [coreboot] Patch set updated for coreboot: d7775ef Add support for A-Open DXPL Plus-U motherboard References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/303 -gerrit commit d7775efdcbeb08dcc24f9f145f2020f1310b768c Author: Ky?sti M?lkki Date: Thu Nov 3 15:22:01 2011 +0200 Add support for A-Open DXPL Plus-U motherboard This is an old (pre-2005) entry-level server mainboard. The code is adapted from mainboard/intel/xe7501devkit. Featured chips: - Dual socket604 - E7505 northbridge - 82801DB southbridge (with EHCI debug port) - 82870p2 PCI-X bridge - LPC47M102S-MC super-io - 512kB FWH flash (flashrom does the job well) What works: - Dual-Xeon P4/HT boot with microcode update - RAM: registered ECC DDR266 in dual-channel - PCI-X slot interrupts with ACPI and I/O apic - On-board PCI-X GbE and SCSI - ACPI power-off and wakeup with PME# Notes : - Current ACPI is more or less a mess - Interrupts do not route correctly with PIRQ - MP-table is not implemented - Issues with reboots remain (cold and warm) - Many superio devices are disabled by default - Audio codec is not investigated Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011 Signed-off-by: Ky?sti M?lkki --- src/mainboard/Kconfig | 3 + src/mainboard/aopen/Kconfig | 17 ++ src/mainboard/aopen/dxplplusu/Kconfig | 63 ++++++++ src/mainboard/aopen/dxplplusu/Makefile.inc | 1 + src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl | 86 ++++++++++ src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 70 ++++++++ src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 171 ++++++++++++++++++++ src/mainboard/aopen/dxplplusu/acpi/p64h2.asl | 97 ++++++++++++ src/mainboard/aopen/dxplplusu/acpi/power.asl | 95 +++++++++++ src/mainboard/aopen/dxplplusu/acpi/scsi.asl | 63 ++++++++ src/mainboard/aopen/dxplplusu/acpi/superio.asl | 183 ++++++++++++++++++++++ src/mainboard/aopen/dxplplusu/acpi_tables.c | 163 +++++++++++++++++++ src/mainboard/aopen/dxplplusu/bus.h | 42 +++++ src/mainboard/aopen/dxplplusu/chip.h | 4 + src/mainboard/aopen/dxplplusu/devicetree.cb | 87 ++++++++++ src/mainboard/aopen/dxplplusu/dsdt.asl | 113 +++++++++++++ src/mainboard/aopen/dxplplusu/fadt.c | 166 ++++++++++++++++++++ src/mainboard/aopen/dxplplusu/irq_tables.c | 76 +++++++++ src/mainboard/aopen/dxplplusu/mainboard.c | 7 + src/mainboard/aopen/dxplplusu/romstage.c | 103 ++++++++++++ 20 files changed, 1610 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 13032a6..549962f 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -14,6 +14,8 @@ config VENDOR_ADVANTECH bool "Advantech" config VENDOR_AMD bool "AMD" +config VENDOR_AOPEN + bool "AOpen" config VENDOR_ARIMA bool "Arima" config VENDOR_ARTEC_GROUP @@ -131,6 +133,7 @@ source "src/mainboard/abit/Kconfig" source "src/mainboard/advansus/Kconfig" source "src/mainboard/advantech/Kconfig" source "src/mainboard/amd/Kconfig" +source "src/mainboard/aopen/Kconfig" source "src/mainboard/arima/Kconfig" source "src/mainboard/artecgroup/Kconfig" source "src/mainboard/asi/Kconfig" diff --git a/src/mainboard/aopen/Kconfig b/src/mainboard/aopen/Kconfig new file mode 100644 index 0000000..5b5497c --- /dev/null +++ b/src/mainboard/aopen/Kconfig @@ -0,0 +1,17 @@ +if VENDOR_AOPEN + +choice + prompt "Mainboard model" + +config BOARD_AOPEN_DXPLPLUSU + bool "DXPL Plus-U" + +endchoice + +source "src/mainboard/aopen/dxplplusu/Kconfig" + +config MAINBOARD_VENDOR + string + default "AOpen" + +endif # VENDOR_AOPEN diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig new file mode 100644 index 0000000..c3025d1 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -0,0 +1,63 @@ +if BOARD_AOPEN_DXPLPLUSU + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7505 + select SOUTHBRIDGE_INTEL_I82870 + select SOUTHBRIDGE_INTEL_I82801DX + select SUPERIO_SMSC_LPC47M10X + select ROMCC + select HAVE_HARD_RESET +# select HAVE_PIRQ_TABLE +# select PIRQ_ROUTE + select UDELAY_TSC + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_512 + +config MAINBOARD_DIR + string + default aopen/dxplplusu + +config MAINBOARD_PART_NUMBER + string + default "DXPL Plus-U" + +config DCACHE_RAM_BASE + hex + default 0xcf000 + +config DCACHE_RAM_SIZE + hex + default 0x1000 + +config IRQ_SLOT_COUNT + int + default 12 + +config BOARD_HAS_FADT + bool + default y + +config LOGICAL_CPUS + bool + default n + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x0 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x0 + +endif # BOARD_AOPEN_DXPLPLUSU diff --git a/src/mainboard/aopen/dxplplusu/Makefile.inc b/src/mainboard/aopen/dxplplusu/Makefile.inc new file mode 100644 index 0000000..0f285cd --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Makefile.inc @@ -0,0 +1 @@ +ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl new file mode 100644 index 0000000..0e84d44 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (MBRS) +{ + Name (_HID, EisaId ("PNP0C01")) + Name (_UID, 0x01) + Name (MSBF, ResourceTemplate () + { + /* System memory */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, + MaxNotFixed, Prefetchable, ReadWrite, + 0x0, 0x100000000, 0x400000000, 0x0, 0x0, ,, _Y1C, + AddressRangeMemory, TypeStatic) + + /* Top Of Low Memory */ + Memory32 (ReadOnly, 0x0, 0x0, 0x1, 0x0, _Y1D) + + /* 640kB who wants more? */ + Memory32Fixed (ReadWrite, 0x0, 0xA0000, ) + + /* 64k BIOS bootblock */ + Memory32Fixed (ReadOnly, 0xF0000, 0x10000,) + + /* ISA memory hole 15-16 MB ? */ + /* Memory32Fixed (ReadOnly, 0x100000, 0xF00000,) */ + /* ISA memory hole 14-15 MB ? */ + /* Memory32Fixed (ReadOnly, 0x100000, 0xE00000,) */ + + /* Local APIC */ + Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000,) + }) + + Method (_CRS, 0, NotSerialized) + { + CreateQWordField (MSBF, \_SB.MBRS._Y1C._MIN, MEML) + CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM) + CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM) + + And (\_SB.PCI0.RLAR, 0x03FF, Local1) + Increment (Local1) + If (LGreater (Local1, 0x40)) + { + ShiftLeft (Local1, 0x1A, LELM) + } + + + CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00) + CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01) + CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2) + And (\_SB.PCI0.TOLM, 0xF800, Local1) + ShiftRight (Local1, 0x04, Local1) + Decrement (Local1) + If (LGreater (Local1, 0x10)) + { + Subtract (Local1, 0x0F, Local1) + Store (ShiftLeft (Local1, 0x14), MEM2) + Store (0x01000000, MS00) + Store (MS00, MS01) + } + + Return (MSBF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl new file mode 100644 index 0000000..0effe93 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name (PBRS, ResourceTemplate () +{ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100, ,, ) + + /* System IO */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0, 0x0, 0xffff, 0x0000, 0x10000, ,,, TypeStatic) + IO (Decode16, 0x0CF8, 0x0CF8, 0x08, 0x08, ) + + /* Video RAM */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x000A0000, 0x000BFFFF, + 0x00000000, 0x00020000, ,,, AddressRangeMemory, TypeStatic) + + /* Video ROM */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x000C0000, 0x000C7FFF, + 0x00000000, 0x00008000, ,,, AddressRangeMemory, TypeStatic) + + /* Option ROMs ? */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x000C8000, 0x000DFFFF, + 0x00000000, 0x00018000, ,,, AddressRangeMemory, TypeStatic) + + /* Top Of Lowmemory to IOAPIC */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x02000000, 0xFEBFFFFF, + 0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic) +}) + + +Method (_CRS, 0, NotSerialized) +{ + + /* Top Of Lowmemory to IOAPIC */ + CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML) + CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM) + And (\_SB.PCI0.TOLM, 0xF800, Local1) + ShiftRight (Local1, 0x04, Local1) + ShiftLeft (Local1, 0x14, MEML) + Subtract (0xFEC00000, MEML, LENM) + + Return (PBRS) +} + +Method (_STA, 0, NotSerialized) +{ + Return (0x0F) +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl new file mode 100644 index 0000000..bb8c321 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (USB0) +{ + Name (_ADR, 0x001D0000) + Name (_PRW, Package () { 0x03, 0x05 }) + + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device (USB1) +{ + Name (_ADR, 0x001D0001) + Name (_PRW, Package () { 0x04, 0x05 }) + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device (USB2) +{ + Name (_ADR, 0x001D0002) + Name (_PRW, Package () { 0x0C, 0x05 }) + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device (USB3) +{ + Name (_ADR, 0x001D0007) + Name (_PRW, Package () { 0x0D, 0x05 }) /* PME_B0_STS any 0:1d or 0:1f device */ + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device(PCI5) +{ + Name (_ADR, 0x001E0000) + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + Name (_PRT, Package() { + Package() { 0x0003ffff, 0, 0, 20 }, + Package() { 0x0003ffff, 1, 0, 21 }, + Package() { 0x0003ffff, 2, 0, 22 }, + Package() { 0x0003ffff, 3, 0, 23 }, + }) +} + +Device (ICH0) +{ + Name (_ADR, 0x001F0000) + OperationRegion (D310, PCI_Config, 0x00, 0xFF) + Field (D310, ByteAcc, NoLock, Preserve) + { + Offset (0x40), PBAR, 16, + Offset (0x58), GBAR, 16, + } + + OperationRegion (ACPI, SystemIO, 0x0400, 0xC0) + Field (ACPI, ByteAcc, NoLock, Preserve) + { + Offset (0x00), PS1L,8, PS1H,8, PE1L,8, PE1H,8, + Offset (0x28), GS0L,8, GS0H,8, GSPL,8, GSPH,8, + Offset (0x2C), GE0L,8, GE0H,8, GEPL,8, GEPH,8, + Offset (0xB8), GPLV,8 + } + + Name (MSBF, ResourceTemplate () + { + /* IOAPIC 0 */ + Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,) + + IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO) + IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO) + + /* 8254 legacy irq */ + IO (Decode16, 0x04D0, 0x04D0, 0x02, 0x02,) + + /* reset generator */ + IO (Decode16, 0x0092, 0x0092, 0x01, 0x01, ) + }) + + Method (_CRS, 0, NotSerialized) + { + CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MIN, IOA1) + CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MAX, IOA2) + CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL) + + Store (PBAR, Local0) + If ( Land(Local0, 0x01) ) + { + And (Local0, 0xFFFE, Local0) + Store (Local0, IOA1) + Store (Local0, IOA2) + Store (0x80, IOAL) + } Else { + Store (0x00, IOAL) + } + + CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MIN, IOS1) + CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MAX, IOS2) + CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL) + + Store (GBAR, Local0) + If ( Land(Local0, 0x01) ) { + And (Local0, 0xFFFE, Local0) + Store (Local0, IOS1) + Store (Local0, IOS2) + Store (0x40, IOSL) + } Else { + Store (0x00, IOSL) + } + Return (MSBF) + } + + Device (FWH) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + + Name (MSBG, ResourceTemplate () { + Memory32Fixed (ReadOnly, 0xFFF00000, 0x00080000,) + Memory32Fixed (ReadOnly, 0xFFF80000, 0x00080000,) + }) + + Method (_CRS, 0, NotSerialized) + { + Return (MSBG) + } + } + + Device (SMSC) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) + #include "acpi/superio.asl" + } + +} + + + diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl new file mode 100644 index 0000000..3958699 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Interrupt routing for PCI 03:xx.x */ + +/* I/O APIC id 0x3 */ +Device(PBIO) +{ + Name (_HID, "ACPI000A") + Name (_ADR, 0x001c0000) +} + +/* PCI-X bridge */ +Device(P64B) +{ + Name (_ADR, 0x001d0000) + Name (_PRT, Package() { + Package() { 0x0002ffff, 0, 0, 24 }, /* PCI-X slot 1 */ + Package() { 0x0002ffff, 1, 0, 25 }, + Package() { 0x0002ffff, 2, 0, 26 }, + Package() { 0x0002ffff, 3, 0, 27 }, + Package() { 0x0003ffff, 0, 0, 28 }, /* PCI-X slot 2 */ + Package() { 0x0003ffff, 1, 0, 29 }, + Package() { 0x0003ffff, 2, 0, 30 }, + Package() { 0x0003ffff, 3, 0, 31 }, + Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */ + }) + + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + OperationRegion (PBPC, PCI_Config, 0x00, 0xFF) + Field (PBPC, ByteAcc, NoLock, Preserve) + { + Offset (0x3E), BCRL, 8, BCRH, 8 + } + + + Device (ETH0) + { + Name (_ADR, 0x00040000) + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + } +} + + +/* Interrupt routing for PCI 04:xx.x */ + +/* I/O APIC id 0x4 */ +Device(PAIO) +{ + Name (_HID, "ACPI000A") + Name (_ADR, 0x001e0000) +} + +/* PCI-X bridge */ +Device(P64A) +{ + Name (_ADR, 0x001f0000) + Name (_PRT, Package() { + Package() { 0x0002ffff, 0, 0, 48 }, /* PCI-X slot 3 */ + Package() { 0x0002ffff, 1, 0, 49 }, + Package() { 0x0002ffff, 2, 0, 50 }, + Package() { 0x0002ffff, 3, 0, 51 }, + Package() { 0x0003ffff, 0, 0, 52 }, /* PCI-X slot 4 */ + Package() { 0x0003ffff, 1, 0, 53 }, + Package() { 0x0003ffff, 2, 0, 54 }, + Package() { 0x0003ffff, 3, 0, 55 }, + Package() { 0x0004ffff, 0, 0, 54 }, /* On-board SCSI, GSI not 56 ? */ + Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */ + }) + + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + OperationRegion (PBPC, PCI_Config, 0x00, 0xFF) + Field (PBPC, ByteAcc, NoLock, Preserve) + { + Offset (0x3E), BCRL, 8, BCRH, 8 + } + + #include "acpi/scsi.asl" +} + + diff --git a/src/mainboard/aopen/dxplplusu/acpi/power.asl b/src/mainboard/aopen/dxplplusu/acpi/power.asl new file mode 100644 index 0000000..92db59e --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/power.asl @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* Board powers on with button or PME# from on-board GbE wake-on-lan. + * Board shuts down to S5/G2. Any other power management is untested. + */ + +Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) +Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 }) +Name (\_S3, Package () { 0x05, 0x05, 0x00, 0x00 }) +Name (\_S4, Package () { 0x06, 0x06, 0x00, 0x00 }) +Name (\_S5, Package () { 0x07, 0x07, 0x00, 0x00 }) + +Scope (\_GPE) +{ + Method (_L03, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB0, 0x02) + } + Method (_L04, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB1, 0x02) + } + + /* WOL header */ + Method (_L08, 0, NotSerialized) + { + Notify (\_SB.PCI0.PCI5, 0x02) + Notify (\_SB.SLBT, 0x02) + } + + /* PME# */ + Method (_L0B, 0, NotSerialized) + { +#if 1 + Notify (\_SB.LID0, 0x02) +#else + Notify (\_SB.PCI0.HLIB.P64B.ETH0, 0x02) + Notify (\_SB.PCI0.HLIB.P64B, 0x02) + Notify (\_SB.PCI0.HLIB.P64A, 0x02) +#endif + } + + Method (_L0C, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB2, 0x02) + } + + /* PME_B0_STS# */ + Method (_L0D, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB3, 0x02) + } +} + +/* Clear power buttons */ +Method (\_INI, 0, NotSerialized) +{ + Or (\_SB.PCI0.ICH0.PS1H, 0x09, \_SB.PCI0.ICH0.PS1H) + Or (\_SB.PCI0.ICH0.PE1H, 0x01, \_SB.PCI0.ICH0.PE1H) +} + +/* Prepare To Sleep */ +Method (\_PTS, 1, NotSerialized) +{ + Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H) + Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L) +} + +/* System Wake */ +Method (\_WAK, 1, NotSerialized) +{ + Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H) + Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L) + + Return ( Package() { 0x0, 0x0 } ) +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl new file mode 100644 index 0000000..7215a33 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* PCI-X devices 04:04.0 and 04:04.1 : AIC-7902W + * U320 SCSI dual-channel controller + */ + +Device (SCS0) +{ + Name (_ADR, 0x00040000) + OperationRegion (SCSC, PCI_Config, 0x00, 0x0100) + Field (SCSC, ByteAcc, NoLock, Preserve) + { + Offset (0x2C), SID, 32, + Offset (0xE0), PMC, 8, + Offset (0xFF), IDW, 8 + } +} + +Device (SCS1) +{ + Name (_ADR, 0x00040001) + OperationRegion (SCSC, PCI_Config, 0x00, 0x0100) + Field (SCSC, ByteAcc, NoLock, Preserve) + { + Offset (0x2C), SID, 32, + Offset (0xE0), PMC, 8, + Offset (0xFF), IDW, 8 + } +} + +#if 0 +/* Set subsystem id for both SCSI devices. + * It may require some delay on wake-up before this can be done. + */ + Method ( ) + { + Or (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS0.IDW) + Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS0.SID) + And (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS0.IDW) + + Or (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS1.IDW) + Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS1.SID) + And (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS1.IDW) + } +#endif + diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl new file mode 100644 index 0000000..15b5e08 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/superio.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* SuperIO GPIO configuration via logical device 0x0A */ + +Name (MSBF, ResourceTemplate () +{ + IO (Decode16, 0x0000, 0x0000, 0x01, 0x80, _Y1B) +}) + +OperationRegion (LPC0, SystemIO, 0x0E00, 0x60) +Field (LPC0, ByteAcc, NoLock, Preserve) +{ + PME0, 8, + Offset (0x02), PME2,8, + Offset (0x04), PME4,8, + Offset (0x0A), PMEA,8, + Offset (0x23), + GC10,8, GC11,8, GC12,8, GC13,8, GC14,8, GC15,8, GC16,8, GC17,8, + GC20,8, GC21,8, GC22,8, GC23,8, GC24,8, GC25,8, GC26,8, GC27,8, + GC30,8, GC31,8, GC32,8, GC33,8, GC34,8, GC35,8, GC36,8, GC37,8, + GC40,8, GC41,8, GC42,8, GC43,8, + + Offset (0x3F), + GC50,8, GC51,8, GC52,8, GC53,8, GC54,8, GC55,8, GC56,8, GC57,8, + GC60,8, GC61,8, + + Offset (0x4B), + GP_1,8, GP_2,8, GP_3,8, GP_4,8, GP_5,8, GP_6,8, + Offset (0x56), FAN1,8, + Offset (0x5D), LED1,8, LED2,8, +} + +OperationRegion (SMC1, SystemIO, 0x2E, 0x02) +Field (SMC1, ByteAcc, NoLock, Preserve) +{ + INDX, 8, DATA, 8 +} + +IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) +{ + Offset (0x07), LDN, 8, + Offset (0x22), PWRC, 8, + Offset (0x30), ACTR, 8, + Offset (0x60), + IOAH, 8, IOAL, 8, + IOBH, 8, IOBL, 8, + + Offset (0x70), INTR, 8, + Offset (0x72), INT1, 8, + Offset (0x74), DMCH, 8, + Offset (0xB2), SPS1, 8, SPS2, 8, + Offset (0xB8), D2TS, 8, + Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8, + Offset (0xF4), WDTC, 8, + Offset (0xF6), GP01, 8, GP02, 8, GP04, 8 +} + +Method (ECFG, 0, NotSerialized) +{ + Store (0x55, INDX) +} +Method (XCFG, 0, NotSerialized) +{ + Store (0xAA, INDX) +} + +Method (_CRS, 0, NotSerialized) +{ + CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MIN, IOM1) + CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MAX, IOM2) + CreateByteField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._LEN, IOML) + + ECFG () + Store (0x0A, \_SB.PCI0.ICH0.SMSC.LDN) + Store (0x00, IOM1) + Store (0x00, IOM2) + Or (\_SB.PCI0.ICH0.SMSC.IOAH, IOM1, IOM1) + ShiftLeft (IOM1, 0x08, IOM1) + Or (\_SB.PCI0.ICH0.SMSC.IOAL, IOM1, IOM1) + Store (IOM1, IOM2) + If (LNotEqual (IOM1, 0x00)) + { + Store (0x80, IOML) + } + XCFG () + + Return (MSBF) +} + + +Method (_INI, 0, NotSerialized) +{ + /* GPIO configuration */ + Store (0x00, GC10) + Store (0x81, GC11) + Store (0x00, GC17) + Store (0x0c, GC21) + Store (0x00, GC22) + Store (0x04, GC27) + Store (0x04, GC30) + Store (0x01, GC31) + Store (0x01, GC32) + Store (0x01, GC33) + Store (0x01, GC34) /* GPI password jumper */ + Store (0x01, GC35) /* GPI scsi enable jumper */ +#if 1 + Store (0x01, GC42) /* GPI */ +#else + Store (0x84, GC42) /* nIO_PME */ +#endif + Store (0x86, GC60) /* led 1 */ + Store (0x81, GC61) /* led 2 ?? */ + + /* GPIO initial output levels */ + Store (GP_1, Local0) + And( Local0, 0x7C, Local0) + Or ( Local0, 0x81, Local0) + Store (Local0, GP_1) + + Store (GP_2, Local0) + And( Local0, 0xFE, Local0) + Or ( Local0, 0x00, Local0) + Store (Local0, GP_2) + + Store (GP_3, Local0) + And( Local0, 0x7F, Local0) + Or ( Local0, 0x80, Local0) + Store (Local0, GP_3) + + Store (GP_4, Local0) + And( Local0, 0x7F, Local0) + Or ( Local0, 0x00, Local0) + Store (Local0, GP_4) + + /* Power Led */ + Store (LED1, Local0) + And( Local0, 0xfc, Local0) + Or ( Local0, 0x01, Local0) + Store (Local0, LED1) + +} + +Method (MLED, 1, NotSerialized) +{ + If (LEqual (Arg0, 0x00)) + { + Store (0x00, LED1) + } + + If (LOr (LEqual (Arg0, 0x01), LEqual (Arg0, 0x02))) + { + Store (0x01, LED1) + } + + If (LEqual (Arg0, 0x03)) + { + Store (0x02, LED1) + } + + If (LOr (LEqual (Arg0, 0x04), LEqual (Arg0, 0x05))) + { + Store (0x03, LED1) + } +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c new file mode 100644 index 0000000..b7c789a --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer + * (C) 2005 Stefan Reinauer + * (C) 2005 Digital Design Corporation + * + * Ported to Intel XE7501DEVKIT by Agami Aruma + * Ported to AOpen DXPL Plus-U by Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "bus.h" + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int irq_start = 0; + device_t dev = 0; + struct resource* res = NULL; + + // SJM: Hard-code CPU LAPIC entries for now + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7); + + // Southbridge IOAPIC + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + + // P64H2 Bus B IOAPIC + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); + if (!dev) + BUG(); // Config.lb error? + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + + // P64H2 Bus A IOAPIC + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); + if (!dev) + BUG(); // Config.lb error? + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + + + // Map ISA IRQ 0 to IRQ 2 + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0); + + // IRQ9 differs from ISA standard - ours is active high, level-triggered + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD); + + return current; +} + +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_facs_t *facs; + acpi_fadt_t *fadt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt,(void *)AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + ALIGN_CURRENT; + memcpy(dsdt,(void *)AmlCode, dsdt->length); + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt,dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdp,fadt); + + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current+=madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp,madt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} + diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h new file mode 100644 index 0000000..7cb188d --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/bus.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DXPLPLUSU_BUS_H_INCLUDED +#define DXPLPLUSU_BUS_H_INCLUDED + +// These were determined by seeing how coreboot enumerates the various +// PCI (and PCI-like) buses on the board. + +#define PCI_BUS_ROOT 0 +#define PCI_BUS_AGP 1 // AGP +#define PCI_BUS_E7501_HI_B 2 // P64H2#1 +#define PCI_BUS_P64H2_B 3 // P64H2#1 bus B +#define PCI_BUS_P64H2_A 4 // P64H2#1 bus A +#define PCI_BUS_ICH4 5 // ICH4 + +// IOAPIC addresses determined by coreboot enumeration. +// Someday add functions to get APIC IDs and versions from the chips themselves. + +#define IOAPIC_ICH4 2 +#define IOAPIC_P64H2_BUS_B 3 // IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 +#define IOAPIC_P64H2_BUS_A 4 // IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 + +#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-4 and P64-H2 + +#endif diff --git a/src/mainboard/aopen/dxplplusu/chip.h b/src/mainboard/aopen/dxplplusu/chip.h new file mode 100644 index 0000000..06f11d0 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config { +}; diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb new file mode 100644 index 0000000..d465a82 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Ky?sti M?lkki +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/e7505 + + device lapic_cluster 0 on + chip cpu/intel/socket_mPGA604 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 0.0 on end # Chipset host controller + device pci 0.1 on end # Host RASUM controller + device pci 2.0 on # Hub interface B + chip southbridge/intel/i82870 # P64H2 + device pci 1c.0 on end # IOAPIC - bus B + device pci 1d.0 on end # Hub to PCI-B bridge + device pci 1e.0 on end # IOAPIC - bus A + device pci 1f.0 on end # Hub to PCI-A bridge + end + end + device pci 4.0 off end # (undocumented) + device pci 6.0 off end # (undocumented) + chip southbridge/intel/i82801dx + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.7 on end # USB EHCI + device pci 1e.0 on # Hub to PCI bridge + device pci 2.0 off end + end + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47m10x + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.a on # ACPI + io 0x60 = 0x0e00 + end + end + end + device pci 1f.1 on end # IDE + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # AC97 Audio + device pci 1f.6 off end # AC97 Modem + end # SB + end # PCI_DOMAIN +end diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl new file mode 100644 index 0000000..31cfa88 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x04, // DSDT revision: ACPI v4.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20111103 // OEM revision +) { + +Scope(\_SB) +{ + Device(PCI0) { + Name (_HID, EISAID("PNP0A03")) + Name (_ADR, 0x00) + Name (_PRT, Package() { + Package() { 0x001dffff, 0, 0, 16 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 23 }, + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 17 }, + }) + + #include "acpi/e7505_sec.asl" + + OperationRegion (I750, PCI_Config, 0x00, 0x0100) + Field (I750, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), + TOLM, 16, /* Top of Low Memory */ + RBAR, 16, /* REMAP_BASE */ + RLAR, 16 /* REMAP_LIMIT */ + } + } + + #include "acpi/e7505_pri.asl" + + + Device (PWBT) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { 0x08, 0x05 }) + } + + Device (SLBT) + { + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { 0x0B, 0x05 }) + } + + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { 0x0B, 0x05 }) + } + +} + +Scope(\_SB.PCI0) +{ + + Device(PCI1) + { + Name (_ADR, 0x00010000) + Name (_PRT, Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + }) + } + + Device(HLIB) + { + Name (_ADR, 0x00020000) + Name (_PRT, Package() { + Package() { 0x001dffff, 0, 0, 18 }, + Package() { 0x001dffff, 1, 0, 18 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 18 }, + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 18 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + + #include "acpi/p64h2.asl" + } + + #include "acpi/i82801db.asl" +} + +#include "acpi/power.asl" + +} + diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c new file mode 100644 index 0000000..9707b9d --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ +#define APM_CNT 0x0 /* ACPI mode only */ +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x0 +#define ACPI_DISABLE 0xAA +#define ACPI_ENABLE 0x55 +#define S4_BIOS 0x77 +#define GNVS_UPDATE 0xea + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 4; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->s4bios_req = S4_BIOS; + fadt->pstate_cnt = PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; /* CST_CONTROL; */ + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/aopen/dxplplusu/irq_tables.c b/src/mainboard/aopen/dxplplusu/irq_tables.c new file mode 100644 index 0000000..9f3315b --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/irq_tables.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include "bus.h" + +#define UNUSED_INTERRUPT {0, 0} +#define PIRQ_A 0x60 +#define PIRQ_B 0x61 +#define PIRQ_C 0x62 +#define PIRQ_D 0x63 +#define PIRQ_E 0x68 +#define PIRQ_F 0x69 +#define PIRQ_G 0x6A +#define PIRQ_H 0x6B + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, // Size of this struct in bytes + 0, // PCI bus number on which the interrupt router resides + PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router + 0, // PCI-exclusive IRQ bitmap + PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router + PCI_DEVICE_ID_INTEL_82801DB_LPC, // Device ID of compatible PCI interrupt router + 0, // Additional miniport information + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero + 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0) + { + // NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space + // This was determined from linux-2.6.11/arch/i386/pci/irq.c + // bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 + // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 + // Not sure why IRQ9 isn't routable (inherited from Tyan S2735) + + // INTA# INTB# INTC# INTD# + // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu + + {PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus + {PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // USB 1.1 + + {PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // GbE + + {PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // SCSI + + {PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // 32-bit slot + + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/aopen/dxplplusu/mainboard.c b/src/mainboard/aopen/dxplplusu/mainboard.c new file mode 100644 index 0000000..2d41509 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/mainboard.c @@ -0,0 +1,7 @@ +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("AOpen DXPL Plus-U Mainboard") +}; + diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c new file mode 100644 index 0000000..92ce896 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/early_smbus.c" +#include "southbridge/intel/i82801dx/reset.c" +#include "northbridge/intel/e7505/raminit.h" +#include "northbridge/intel/e7505/debug.c" +#include "superio/smsc/lpc47m10x/early_serial.c" + +#if !CONFIG_CACHE_AS_RAM +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#endif +#include "cpu/x86/bist.h" + +#include + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +/* Cache-As-Ram compiles for this board, but with the CPUs I have, + * it halts on boot while in Local Apic ID negotiation. + */ + +#if CONFIG_CACHE_AS_RAM +#define BOARD_MAIN(x) void main(x) +#define early_mtrr_init() do {} while (0) +#else +#define BOARD_MAIN(x) static void main(x) +#endif + +#include "northbridge/intel/e7505/raminit.c" +#include "northbridge/intel/e7505/reset_test.c" +#include "lib/generic_sdram.c" + +// This function MUST appear last (ROMCC limitation) +BOARD_MAIN(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .d0f1 = PCI_DEV(0, 0, 1), + .channel0 = { 0x50, 0x52, 0, 0 }, + .channel1 = { 0x51, 0x53, 0, 0 }, + }, + }; + + if (bist == 0) { + // Skip this if there was a built in self test failure + early_mtrr_init(); + enable_lapic(); + } + + // Get the serial port running and print a welcome banner + lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + // Halt if there was a built in self test failure + report_bist_failure(bist); + + // If this is a warm boot, some initialization can be skipped + if (!bios_reset_detected()) { + enable_smbus(); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); + } + + // NOTE: ROMCC dies with an internal compiler error + // if the following line is removed. + print_debug("SDRAM is up.\r\n"); + +} From wangqingpei at gmail.com Thu Nov 3 16:14:23 2011 From: wangqingpei at gmail.com (QingPei Wang) Date: Thu, 3 Nov 2011 23:14:23 +0800 Subject: [coreboot] Coreboot and Epia M-II In-Reply-To: <4EB1B118.20704@e4L.es> References: <4EB047B7.5000907@e4L.es> <4EB0E34E.7060909@e4L.es> <4EB12FC2.8010805@e4L.es> <4EB1B118.20704@e4L.es> Message-ID: the default seabios config level is 1. the log which you updated still have no more message about seabios. Maybe post your problems to seabios mail list can bring more great suggestions. seabios at seabios.org Best wishes QingPei Wang Phone: 86+018930528086 On Thu, Nov 3, 2011 at 5:07 AM, Elisenda Cuadros wrote: > Hi, > > I?m using the default seabios config. I think it has debug level set to 8. > Now I compiled Seabios with debug set to 10. I attach you a new log. > > I tried compiling coreboot with FILO (from menuconfig) and it works > perfect. I can boot linux with this rom. > > I tried to compile seabios outside coreboot menuconfig, adding it like an > elf executable. Same problem. > > The problem for me it?s that I want to use this board with FreeBSD and If > I?m not wrong Seabios is the only way to do it. > > Thanks for all. > > Regards, > > Elisenda > > > > On 02/11/2011 16:19, QingPei Wang wrote: > > the coreboot.rom seems fine, do you use the default seabios config, try to > set the debug level of seabios to 8 to show more messages. > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Thu Nov 3 19:02:59 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 3 Nov 2011 19:02:59 +0100 Subject: [coreboot] Patch merged into coreboot/master: 2daa28a libpayload: Put coreboot version into lib_sysinfo References: Message-ID: the following patch was just integrated into master: commit 2daa28a3b187d92eb9ad11534f6b96e65e83225f Author: Mathias Krause Date: Thu Oct 20 14:06:26 2011 +0200 libpayload: Put coreboot version into lib_sysinfo Change-Id: I22319efe90e475c66b9556f734a7a5e54f7c59bc Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Thu Nov 3 12:38:56 2011, giving +1 Reviewed-By: Stefan Reinauer at Thu Nov 3 19:02:52 2011, giving +2 See http://review.coreboot.org/394 for details. -gerrit From gerrit at coreboot.org Thu Nov 3 19:14:34 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 3 Nov 2011 19:14:34 +0100 Subject: [coreboot] Patch merged into coreboot/master: 02418b7 libpayload: Reduce verbosity in USB stack References: Message-ID: the following patch was just integrated into master: commit 02418b7f4316fc8b3f0ba48a853d5dce702cff08 Author: Mathias Krause Date: Wed Jun 8 15:36:55 2011 +0200 libpayload: Reduce verbosity in USB stack The USB stack is pretty noisy. Reduce the output to a sane level. Change-Id: I250949e5cf74a8c6d43822b2e7487143b2ae1c65 Signed-off-by: Mathias Krause Build-Tested: build bot (Jenkins) at Thu Nov 3 12:28:35 2011, giving +1 Reviewed-By: Stefan Reinauer at Thu Nov 3 19:14:06 2011, giving +2 See http://review.coreboot.org/393 for details. -gerrit From gerrit at coreboot.org Thu Nov 3 21:32:41 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 3 Nov 2011 21:32:41 +0100 Subject: [coreboot] Patch merged into coreboot/master: 68c5545 add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: the following patch was just integrated into master: commit 68c554550f59bd96caace96260ae2e30ed55ceb4 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Thu Nov 3 07:37:29 2011, giving +1 Reviewed-By: Rudolf Marek at Thu Nov 3 21:32:39 2011, giving +2 See http://review.coreboot.org/381 for details. -gerrit From gerrit at coreboot.org Thu Nov 3 21:39:07 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 3 Nov 2011 21:39:07 +0100 Subject: [coreboot] Patch merged into coreboot/master: 1eebc29 add support for writing to SMBus with vt8237 References: Message-ID: the following patch was just integrated into master: commit 1eebc2948d93462056bfd2690132e18f2e1ed0dc Author: Florian Zumbiehl Date: Tue Nov 1 20:17:13 2011 +0100 add support for writing to SMBus with vt8237 Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Thu Nov 3 07:06:02 2011, giving +1 Reviewed-By: Rudolf Marek at Thu Nov 3 21:39:03 2011, giving +2 See http://review.coreboot.org/372 for details. -gerrit From gerrit at coreboot.org Fri Nov 4 01:14:21 2011 From: gerrit at coreboot.org (Christoph Grenz (christophg+cb@grenz-bonn.de)) Date: Fri, 4 Nov 2011 01:14:21 +0100 Subject: [coreboot] Patch set updated for coreboot: c60b3f5 w83627hf: drop Scope(\_SB) from ASL include References: Message-ID: Christoph Grenz (christophg+cb at grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/298 -gerrit commit c60b3f56365d089cd3aa2c744d8944efd49360a2 Author: Christoph Grenz Date: Fri Nov 4 01:11:27 2011 +0100 w83627hf: drop Scope(\_SB) from ASL include Drop explicit Scope(\_SB) from devtree.asl as it forces the SuperIO to appear as child of the root device. devtree.asl then needs to be included at a reasonable position inside the \_SB device tree. Change-Id: I72a57eddc5ec5f9763fdf789094a7be042758256 Signed-off-by: Christoph Grenz --- src/superio/winbond/w83627hf/devtree.asl | 2496 +++++++++++++++--------------- 1 files changed, 1246 insertions(+), 1250 deletions(-) diff --git a/src/superio/winbond/w83627hf/devtree.asl b/src/superio/winbond/w83627hf/devtree.asl index aa18841..ddac22e 100644 --- a/src/superio/winbond/w83627hf/devtree.asl +++ b/src/superio/winbond/w83627hf/devtree.asl @@ -18,8 +18,8 @@ */ /* - * include this file into a mainboard's DSDT and it will expose the W83627HF - * SuperIO and its functionality in the _SB device tree. + * include this file into a mainboard's DSDT _SB device tree and it will expose the + * W83627HF SuperIO and its functionality. * * Devices are marked as nonexistant if they got 0x00000000 as I/O base address * (compatibility with legacy bios, which disables logical devices that way) @@ -56,960 +56,827 @@ * http://www.itox.com/pages/support/wdt/W83627HF.pdf */ -Scope (\_SB) -{ +Device(SIO) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Winbond W83627HF SuperIO")) + Name (_UID, "w83627hf") - Device(SIO) { - Name (_HID, EisaId("PNP0A05")) - Name (_STR, Unicode("Winbond W83627HF SuperIO")) - Name (_UID, "w83627hf") + /* Mutex for accesses to the configuration ports (prolog and epilog commands are used, so synchronization is useful) */ + Mutex(CRMX, 1) - /* Mutex for accesses to the configuration ports (prolog and epilog commands are used, so synchronization is useful) */ - Mutex(CRMX, 1) + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, 0x2E, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + ADDR, 8, + DATA, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + RST, 1, /* Soft reset */ + , 7, + Offset (0x07), + LDN, 8, /* Logical device selector */ + Offset (0x20), + DID, 8, /* Device ID */ + DREV, 8, /* Device Revision */ + FDPW, 1, /* FDC Power Down */ + , 2, + PRPW, 1, /* PRT Power Down */ + UAPW, 1, /* UART A Power Down */ + UBPW, 1, /* UART B Power Down */ + HWPW, 1, /* HWM Power Down */ + , 1, + IPD, 1, /* Immediate Chip Power Down */ + , 7, + PNPS, 1, /* PnP Address Select Register Default Value Mode */ + , 1, + KBCR, 1, /* KBC enabled after system reset (read-only) */ + , 3, + CLKS, 1, /* Clock select */ + AQ16, 1, /* 16bit Address Qualification */ + FDCT, 1, /* Tristate FDC (?) */ + , 2, + PRTT, 1, /* Tristate parallel port (?) */ + URAT, 1, /* Tristate UART A (?) */ + URBT, 1, /* Tristate UART B (?) */ + , 2, + URAI, 1, /* UART A Legacy IRQ Select Disable */ + URBI, 1, /* UART B Legacy IRQ Select Disable */ + PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ + FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ + , 1, + LCKC, 1, /* Lock Configuration Registers */ + Offset (0x29), + IO3S, 8, /* GPIO3 pin selection register */ + ACTR, 1, /* Logical device activation */ + ACT1, 1, /* Logical part activation 1 (mostly unused) */ + ACT2, 1, /* Logical part activation 2 (mostly unused) */ + , 5, + Offset (0x60), + IO1H, 8, /* First I/O port base - high byte */ + IO1L, 8, /* First I/O port base - low byte */ + IO2H, 8, /* Second I/O port base - high byte */ + IO2L, 8, /* Second I/O port base - low byte */ + Offset (0x70), + IRQ0, 8, /* First IRQ */ + Offset (0x72), + IRQ1, 8, /* First IRQ */ + Offset (0x74), + DMA0, 8, /* DMA */ + Offset (0xE0), + /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ + CRE0, 8, + CRE1, 8, + CRE2, 8, + CRE3, 8, + CRE4, 8, + Offset (0xF0), + /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ + OPT1, 8, + OPT2, 8, + OPT3, 8, + OPT4, 8, + OPT5, 8, + OPT6, 8, + OPT7, 8, + OPT8, 8, + OPT9, 8, + OPTA, 8 + } - /* SuperIO configuration ports */ - OperationRegion (CREG, SystemIO, 0x2E, 0x02) - Field (CREG, ByteAcc, NoLock, Preserve) - { - ADDR, 8, - DATA, 8 - } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) - { - Offset (0x02), - RST, 1, /* Soft reset */ - , 7, - Offset (0x07), - LDN, 8, /* Logical device selector */ - Offset (0x20), - DID, 8, /* Device ID */ - DREV, 8, /* Device Revision */ - FDPW, 1, /* FDC Power Down */ - , 2, - PRPW, 1, /* PRT Power Down */ - UAPW, 1, /* UART A Power Down */ - UBPW, 1, /* UART B Power Down */ - HWPW, 1, /* HWM Power Down */ - , 1, - IPD, 1, /* Immediate Chip Power Down */ - , 7, - PNPS, 1, /* PnP Address Select Register Default Value Mode */ - , 1, - KBCR, 1, /* KBC enabled after system reset (read-only) */ - , 3, - CLKS, 1, /* Clock select */ - AQ16, 1, /* 16bit Address Qualification */ - FDCT, 1, /* Tristate FDC (?) */ - , 2, - PRTT, 1, /* Tristate parallel port (?) */ - URAT, 1, /* Tristate UART A (?) */ - URBT, 1, /* Tristate UART B (?) */ - , 2, - URAI, 1, /* UART A Legacy IRQ Select Disable */ - URBI, 1, /* UART B Legacy IRQ Select Disable */ - PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ - FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ - , 1, - LCKC, 1, /* Lock Configuration Registers */ - Offset (0x29), - IO3S, 8, /* GPIO3 pin selection register */ - ACTR, 1, /* Logical device activation */ - ACT1, 1, /* Logical part activation 1 (mostly unused) */ - ACT2, 1, /* Logical part activation 2 (mostly unused) */ - , 5, - Offset (0x60), - IO1H, 8, /* First I/O port base - high byte */ - IO1L, 8, /* First I/O port base - low byte */ - IO2H, 8, /* Second I/O port base - high byte */ - IO2L, 8, /* Second I/O port base - low byte */ - Offset (0x70), - IRQ0, 8, /* First IRQ */ - Offset (0x72), - IRQ1, 8, /* First IRQ */ - Offset (0x74), - DMA0, 8, /* DMA */ - Offset (0xE0), - /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ - CRE0, 8, - CRE1, 8, - CRE2, 8, - CRE3, 8, - CRE4, 8, - Offset (0xF0), - /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ - OPT1, 8, - OPT2, 8, - OPT3, 8, - OPT4, 8, - OPT5, 8, - OPT6, 8, - OPT7, 8, - OPT8, 8, - OPT9, 8, - OPTA, 8 - } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) /* Announce the used I/O ports to the OS */ + IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) /* this port is used in some configurations, so announce it to be sure */ + }) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) /* Announce the used I/O ports to the OS */ - IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) /* this port is used in some configurations, so announce it to be sure */ - }) + /* Enter configuration mode (and aquire mutex) + Method must be run before accesssing the configuration region. + */ + Method (ENCM) + { + Acquire (CRMX, 0xFFFF) + Store (0x87, ADDR) + Store (0x87, ADDR) + } - /* Enter configuration mode (and aquire mutex) - Method must be run before accesssing the configuration region. - */ - Method (ENCM) - { - Acquire (CRMX, 0xFFFF) - Store (0x87, ADDR) - Store (0x87, ADDR) + /* Exit configuration mode (and release mutex) + Method must be run after accessing the configuration region. + */ + Method (EXCM) + { + Release (CRMX) + Store (0xAA, ADDR) + } + + /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ + Method (_PSC) { + ENCM () + Store (IPD, Local0) + EXCM () + If (Local0) { Return (2) } + Else { Return (0) } + } + + /* PM: Switch to D0 by setting IPD low */ + Method (_PS0) { + ENCM () + Store (Zero, IPD) + EXCM () + } + + /* PM: Switch to D2 by setting IPD high */ + Method (_PS2) { + ENCM () + Store (One, IPD) + EXCM () + } + + #ifndef NO_W83627HF_FDC + /* =================== Floppy Disk Controller ================ */ + Device (FDC0) { + Name (_HID, EisaId ("PNP0700")) + Name (_STR, Unicode ("W83627HF Floppy Disk Controller")) + Name (_UID, "w83627hf-fdc") + + #ifndef NO_W83627HF_FDC_ENUM + /* Initialization method: Should be run once on boot + If FDC is active, enumerate all connected devices */ + Method (_INI) { + ENCM () + Store (0x00, LDN) + Store (ACTR, Local0) + Store (IO1H, Local1) + Store (IO1L, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or(Local1, Local2, Local1) + If (Local0) { + /* Try probing drives and save result in _FDE */ + PROB(Local1) + } } + #endif - /* Exit configuration mode (and release mutex) - Method must be run after accessing the configuration region. - */ - Method (EXCM) + Method (_STA) { - Release (CRMX) - Store (0xAA, ADDR) + Store (0x00, Local0) + ENCM () + Store (0x00, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) } - /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } ENCM () - Store (IPD, Local0) + Store (FDPW, Local0) EXCM () - If (Local0) { Return (2) } + If (Local0) { Return (1) } Else { Return (0) } } - - /* PM: Switch to D0 by setting IPD low */ Method (_PS0) { ENCM () - Store (Zero, IPD) + Store (Zero, FDPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, FDPW) EXCM () } - /* PM: Switch to D2 by setting IPD high */ - Method (_PS2) { + Method (_DIS) + { ENCM () - Store (One, IPD) + Store (0x00, LDN) + Store (Zero, ACTR) EXCM () } - #ifndef NO_W83627HF_FDC - /* =================== Floppy Disk Controller ================ */ - Device (FDC0) { - Name (_HID, EisaId ("PNP0700")) - Name (_STR, Unicode ("W83627HF Floppy Disk Controller")) - Name (_UID, "w83627hf-fdc") + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x06, IO0) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + ENCM () + Store (0x00, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - #ifndef NO_W83627HF_FDC_ENUM - /* Initialization method: Should be run once on boot - If FDC is active, enumerate all connected devices */ - Method (_INI) { - ENCM () - Store (0x00, LDN) - Store (ACTR, Local0) - Store (IO1H, Local1) - Store (IO1L, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or(Local1, Local2, Local1) - If (Local0) { - /* Try probing drives and save result in _FDE */ - PROB(Local1) - } - } - #endif + Return (CRS) + } - Method (_STA) + Name (_PRS, ResourceTemplate () + { + StartDependentFnNoPri () { - Store (0x00, Local0) - ENCM () - Store (0x00, LDN) - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} } + EndDependentFn () + }) - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (FDPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, FDPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, FDPW) - EXCM () - } + #ifndef NO_W83627HF_FDC_ENUM + Name(_FDE, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + #endif - Method (_DIS) + Method (PROB, 1) { + #ifndef NO_W83627HF_FDC_ENUM + /* Try probing drives and save result in _FDE + Probing is done through selecting and activating a drive + and reading 0x03F7 aka the "shared IDE and floppy register" + as any value there besides zero seems to indicate a + connected drive. + */ + OperationRegion (FIO1, SystemIO, Arg0, 0x06) + Field (FIO1, ByteAcc, NoLock, Preserve) { - ENCM () - Store (0x00, LDN) - Store (Zero, ACTR) - EXCM () + Offset(0x02), + SELE, 2, + RSTL, 1, + IDMA, 1, + ACT1, 1, + ACT2, 1, + ACT3, 1, + ACT4, 1, + Offset(0x04), + BSY1, 1, + BSY2, 1, + BSY3, 1, + BSY4, 1, + BUSY, 1, + NDMA, 1, + IODI, 1, + RDY, 1, + DATA, 8, } + OperationRegion (FIO2, SystemIO, 0x3F7, 0x01) - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x06, IO0) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - ENCM () - Store (0x00, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + CreateByteField (_FDE, 3, FD1) + CreateByteField (_FDE, 7, FD2) + CreateByteField (_FDE, 11, FD3) + CreateByteField (_FDE, 15, FD4) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + Store(One, ACT1) + Store(0, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD1) } - Return (CRS) - } + Store(Zero, ACT1) + Store(One, ACT2) + Store(1, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD2) } - Name (_PRS, ResourceTemplate () - { - StartDependentFnNoPri () - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - } - EndDependentFn () - }) + Store(Zero, ACT2) + Store(One, ACT3) + Store(2, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD3) } - #ifndef NO_W83627HF_FDC_ENUM - Name(_FDE, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + Store(Zero, ACT3) + Store(One, ACT4) + Store(3, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD4) } + Store(Zero, ACT4) + Store(Zero, SELE) #endif - - Method (PROB, 1) { - #ifndef NO_W83627HF_FDC_ENUM - /* Try probing drives and save result in _FDE - Probing is done through selecting and activating a drive - and reading 0x03F7 aka the "shared IDE and floppy register" - as any value there besides zero seems to indicate a - connected drive. - */ - OperationRegion (FIO1, SystemIO, Arg0, 0x06) - Field (FIO1, ByteAcc, NoLock, Preserve) - { - Offset(0x02), - SELE, 2, - RSTL, 1, - IDMA, 1, - ACT1, 1, - ACT2, 1, - ACT3, 1, - ACT4, 1, - Offset(0x04), - BSY1, 1, - BSY2, 1, - BSY3, 1, - BSY4, 1, - BUSY, 1, - NDMA, 1, - IODI, 1, - RDY, 1, - DATA, 8, - } - OperationRegion (FIO2, SystemIO, 0x3F7, 0x01) - - CreateByteField (_FDE, 3, FD1) - CreateByteField (_FDE, 7, FD2) - CreateByteField (_FDE, 11, FD3) - CreateByteField (_FDE, 15, FD4) - - Store(One, ACT1) - Store(0, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD1) } - - Store(Zero, ACT1) - Store(One, ACT2) - Store(1, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD2) } - - Store(Zero, ACT2) - Store(One, ACT3) - Store(2, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD3) } - - Store(Zero, ACT3) - Store(One, ACT4) - Store(3, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD4) } - Store(Zero, ACT4) - Store(Zero, SELE) - #endif - } + } - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 6, IO0) - IO (Decode16, 0, 0, 1, 1, IO1) - IRQNoFlags (IRQ0) {} - DMA (Compatibility, NotBusMaster, Transfer8, DMA0) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO1._MIN, IOA1) - CreateByteField (Arg0, IRQ0._INT, IRQL) - CreateByteField (Arg0, DMA0._DMA, DMCH) + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 6, IO0) + IO (Decode16, 0, 0, 1, 1, IO1) + IRQNoFlags (IRQ0) {} + DMA (Compatibility, NotBusMaster, Transfer8, DMA0) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO1._MIN, IOA1) + CreateByteField (Arg0, IRQ0._INT, IRQL) + CreateByteField (Arg0, DMA0._DMA, DMCH) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - ENCM () - Store (0, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (One, ACTR) - EXCM () + ENCM () + Store (0, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (One, ACTR) + EXCM () - /* Try probing drives and save result in _FDE */ - PROB(IOA0) - } + /* Try probing drives and save result in _FDE */ + PROB(IOA0) } - #endif + } + #endif - #ifndef NO_W83627HF_PPORT - /* ======================== Parallel Port ======================== */ - /* Currently no ECP support */ - Device (PAR0) { - Name (_HID, EisaId ("PNP0400")) - Name (_DDN, "LPT1") - Name (_UID, "w83627hf-pport") + #ifndef NO_W83627HF_PPORT + /* ======================== Parallel Port ======================== */ + /* Currently no ECP support */ + Device (PAR0) { + Name (_HID, EisaId ("PNP0400")) + Name (_DDN, "LPT1") + Name (_UID, "w83627hf-pport") - Method (MODE, 1) { - And(Arg0, 0x07, Local0) - ENCM () - Store (0x01, LDN) - And(OPT1, 0x3, Local1) - Or(Local1, Local0, OPT1) - EXCM() - } + Method (MODE, 1) { + And(Arg0, 0x07, Local0) + ENCM () + Store (0x01, LDN) + And(OPT1, 0x3, Local1) + Or(Local1, Local0, OPT1) + EXCM() + } - Method (_INI) - { - /* Deactivate DMA, even if set by BIOS. We don't announce it - through _CRS and it's only useful in ECP mode which we - don't support at the moment. */ - ENCM () - Store (0x01, LDN) - Store (0x04, DMA0) - EXCM () - } + Method (_INI) + { + /* Deactivate DMA, even if set by BIOS. We don't announce it + through _CRS and it's only useful in ECP mode which we + don't support at the moment. */ + ENCM () + Store (0x01, LDN) + Store (0x04, DMA0) + EXCM () + } - Method (_STA) - { - Store (0x00, Local0) - ENCM () - Store (0x01, LDN) - And(OPT1, 0x3, Local1) - If (ACTR) { - If (LNotEqual(Local1, 2)) { - Store (0x0D, Local0) - } Else { - Store (0x0D, Local0) - } - } - ElseIf (LOr (IO1H, IO1L)) - { + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x01, LDN) + And(OPT1, 0x3, Local1) + If (ACTR) { + If (LNotEqual(Local1, 2)) { + Store (0x0D, Local0) + } Else { Store (0x0D, Local0) } - EXCM () - Return (Local0) - } - - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (PRPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, PRPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, PRPW) - EXCM () } - - Method (_DIS) { - ENCM () - Store (0x01, LDN) - Store (Zero, ACTR) - EXCM () - } - - Method (_CRS) + ElseIf (LOr (IO1H, IO1L)) { - Name (CRS, ResourceTemplate () - { - IO (Decode16, 0x0000, 0x0000, 0x04, 0x08, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (CRS, IO0._MIN, IOP0) - CreateWordField (CRS, IO0._MAX, IOR0) - CreateByteField (CRS, IO0._ALN, IOAL) - CreateByteField (CRS, IO0._LEN, IOLE) - CreateWordField (CRS, IRQX._INT, IRQW) - - ENCM () - Store (0x01, LDN) - Store (IO1L, Local0) - Store (IO1H, Local1) - Store (OPT1, Local2) - Store (IRQ0, Local5) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local1) + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } - And(Local2, 0x3, Local3) - And(Local2, 0x4, Local4) - If (Local4) { - Store(0x04, IOAL) - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (PRPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, PRPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, PRPW) + EXCM () + } - Store(Local1, IOP0) - Store(Local1, IOR0) + Method (_DIS) { + ENCM () + Store (0x01, LDN) + Store (Zero, ACTR) + EXCM () + } - If (LEqual (Local0, 0xBC)) - { - Store (0x04, IOLE) - } - Else - { - Store (0x08, IOLE) - } + Method (_CRS) + { + Name (CRS, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x04, 0x08, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (CRS, IO0._MIN, IOP0) + CreateWordField (CRS, IO0._MAX, IOR0) + CreateByteField (CRS, IO0._ALN, IOAL) + CreateByteField (CRS, IO0._LEN, IOLE) + CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local0) - ShiftLeft (Local0, Local5, IRQW) + ENCM () + Store (0x01, LDN) + Store (IO1L, Local0) + Store (IO1H, Local1) + Store (OPT1, Local2) + Store (IRQ0, Local5) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local1) - Return (CRS) + And(Local2, 0x3, Local3) + And(Local2, 0x4, Local4) + If (Local4) { + Store(0x04, IOAL) } - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,1) - { - IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,1) - { - IO (Decode16, 0x0278, 0x0278, 0x04, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,1) - { - IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) - { - IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) - { - IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) - { - IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,1) - { - IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn () - }) + Store(Local1, IOP0) + Store(Local1, IOR0) - Method (_SRS, 1, Serialized) + If (LEqual (Local0, 0xBC)) { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 4, 4, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO0._MIN, IOA1) - CreateByteField (Arg0, IO0._ALN, IOAL) - CreateByteField (Arg0, IO0._LEN, IOLE) - CreateWordField (Arg0, IRQX._INT, IRQL) - - If (LEqual(IOAL, 4)) { - Store(0x0, Local2) - } else { - Store(0x1, Local2) - } + Store (0x04, IOLE) + } + Else + { + Store (0x08, IOLE) + } - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Store (One, Local0) + ShiftLeft (Local0, Local5, IRQW) - ENCM () - Store (0x01, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - /*Mode*/ - Store (OPT1, Local3) - And (Local3, 0xF8, Local3) - Or (Local2, Local3, OPT1) - /*DMA off*/ - Store (0x04, DMA0) - /*IRQ*/ - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) - Store (Local3, IRQ0) - /*Activate*/ - Store (One, ACTR) - EXCM () - } + Return (CRS) } - #endif - - #ifndef NO_W83627HF_UARTA - /* =========================== UART A ============================ */ - Device (SER0) { - Name (_HID, EisaId ("PNP0501")) - Name (_UID, "w83627hf-uarta") - Name (_DDN, "COM1") - Method (_STA) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,1) { - Store (0x00, Local0) - ENCM () - Store (0x02, LDN) - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (UAPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } + StartDependentFn (0,1) + { + IO (Decode16, 0x0278, 0x0278, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - Method (_PS0) { - ENCM () - Store (Zero, UAPW) - EXCM () + StartDependentFn (0,1) + { + IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - Method (_PS1) { - ENCM () - Store (One, UAPW) - EXCM () + StartDependentFn (0,0) + { + IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Method (_DIS) + StartDependentFn (0,0) { - ENCM () - Store (0x02, LDN) - Store (Zero, ACTR) - EXCM () + IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Method (_CRS) + StartDependentFn (2,0) { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x02, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) - - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) - - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - - Return (CRS) + IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Name (_PRS, ResourceTemplate () + StartDependentFn (2,1) { - StartDependentFn (0,0) { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() - }) + IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn () + }) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 6, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 4, 4, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO0._MIN, IOA1) + CreateByteField (Arg0, IO0._ALN, IOAL) + CreateByteField (Arg0, IO0._LEN, IOLE) + CreateWordField (Arg0, IRQX._INT, IRQL) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + If (LEqual(IOAL, 4)) { + Store(0x0, Local2) + } else { + Store(0x1, Local2) + } - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - ENCM () - Store (2, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (0x01, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + /*Mode*/ + Store (OPT1, Local3) + And (Local3, 0xF8, Local3) + Or (Local2, Local3, OPT1) + /*DMA off*/ + Store (0x04, DMA0) + /*IRQ*/ + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) + Store (Local3, IRQ0) + /*Activate*/ + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_UARTB - /* =========================== UART B ============================ */ - Device (SER1) { - Name (_HID, EisaId ("PNP0501")) - Name (_UID, "w83627hf-uartb") - Name (_DDN, "COM2") + #ifndef NO_W83627HF_UARTA + /* =========================== UART A ============================ */ + Device (SER0) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, "w83627hf-uarta") + Name (_DDN, "COM1") - Method (_STA) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x02, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) { - Store (0x00, Local0) - ENCM () - Store (0x03, LDN) - If (LNot(And(OPT2, 0x30))) - { - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } - } - EXCM () - Return (Local0) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (UBPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, UBPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, UBPW) - EXCM () - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UAPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UAPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UAPW) + EXCM () + } - Method (_DIS) - { - ENCM () - Store (0x03, LDN) - Store (Zero, ACTR) - EXCM () - } + Method (_DIS) + { + ENCM () + Store (0x02, LDN) + Store (Zero, ACTR) + EXCM () + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x02, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + StartDependentFn (1,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 6, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 8, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) - - ENCM () - Store (3, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (2, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_IRDA - /* ======================== UART B (IRDA) ======================== */ - Device (IRDA) { - Name (_HID, EisaId ("PNP0510")) - Name (_UID, "w83627hf-irda") - Name (_STR, Unicode("IrDA Port")) + #ifndef NO_W83627HF_UARTB + /* =========================== UART B ============================ */ + Device (SER1) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, "w83627hf-uartb") + Name (_DDN, "COM2") - Method (_STA) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x03, LDN) + If (LNot(And(OPT2, 0x30))) { - Store (0x00, Local0) - ENCM () - Store (0x03, LDN) - If (And(OPT2, 0x30)) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) { - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } + Store (0x0D, Local0) } - EXCM () - Return (Local0) } + EXCM () + Return (Local0) + } - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (UBPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, UBPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, UBPW) - EXCM () - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UBPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UBPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UBPW) + EXCM () + } - Method (_DIS) - { - ENCM () - Store (0x03, LDN) - Store (Zero, ACTR) - EXCM () - } + Method (_DIS) + { + ENCM () + Store (0x03, LDN) + Store (Zero, ACTR) + EXCM () + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) - Return (CRS) + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + StartDependentFn (1,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 8, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) - - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - ENCM () - Store (3, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (3, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_CIR - /* ========================= Consumer IR ========================= */ - Device (CIR0) { - Name (_HID, EisaId ("WEC1022")) /* Should be the correct one */ - Name (_UID, "w83627hf-cir") - Name (_STR, Unicode("Winbond Consumer Infrared Transceiver")) + #ifndef NO_W83627HF_IRDA + /* ======================== UART B (IRDA) ======================== */ + Device (IRDA) { + Name (_HID, EisaId ("PNP0510")) + Name (_UID, "w83627hf-irda") + Name (_STR, Unicode("IrDA Port")) - Method (_STA) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x03, LDN) + If (And(OPT2, 0x30)) { - Store (0x00, Local0) - ENCM () - Store (0x06, LDN) If (ACTR) { Store (0x0F, Local0) } @@ -1017,508 +884,637 @@ Scope (\_SB) { Store (0x0D, Local0) } - EXCM () - Return (Local0) } + EXCM () + Return (Local0) + } - Method (_DIS) - { - ENCM () - Store (0x06, LDN) - Store (Zero, ACTR) - EXCM () - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UBPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UBPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UBPW) + EXCM () + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Method (_DIS) + { + ENCM () + Store (0x03, LDN) + Store (Zero, ACTR) + EXCM () + } - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 8, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) - - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - ENCM () - Store (6, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (3, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_KBC - /* ===================== Keyboard Controller ===================== */ - Device (KBD0) { - Name (_HID, EisaId ("PNP0303")) - Name (_CID, 0x0B03D041) - Name (_UID, "w83627hf-kbc") + #ifndef NO_W83627HF_CIR + /* ========================= Consumer IR ========================= */ + Device (CIR0) { + Name (_HID, EisaId ("WEC1022")) /* Should be the correct one */ + Name (_UID, "w83627hf-cir") + Name (_STR, Unicode("Winbond Consumer Infrared Transceiver")) - Method (_STA) - { - Store (0x00, Local0) - ENCM () - Store (0x05, LDN) - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x06, LDN) + If (ACTR) { + Store (0x0F, Local0) } - - Method (_DIS) + ElseIf (LOr (IO1H, IO1L)) { - ENCM () - Store (0x05, LDN) - Store (Zero, ACTR) - EXCM () - Notify(PS2M, 1) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x05, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IO2H, Local2) - Store(IO2L, Local3) - Store(IRQ0, Local4) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + Method (_DIS) + { + ENCM () + Store (0x06, LDN) + Store (Zero, ACTR) + EXCM () + } - ShiftLeft(Local2, 8, Local2) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IO1._MIN, I1MI) - Store (Local2, I1MI) - CreateWordField (CRS, IO1._MAX, I1MA) - Store (Local2, I1MA) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local5) - ShiftLeft (Local5, Local4, IRQW) + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 1, IO0) - IO (Decode16, 0, 0, 1, 1, IO1) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO1._MIN, IOA1) - CreateByteField (Arg0, IRQX._INT, IRQL) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - Divide(IOA1, 256, Local2, Local3) - ShiftRight(Local1, 8, Local1) + ENCM () + Store (6, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #endif - FindSetLeftBit (IRQL, Local4) - Subtract (Local4, 0x01, Local4) + #ifndef NO_W83627HF_KBC + /* ===================== Keyboard Controller ===================== */ + Device (KBD0) { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, 0x0B03D041) + Name (_UID, "w83627hf-kbc") - ENCM () - Store (5, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IO2H) - Store (Local2, IO2L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x05, LDN) + If (ACTR) { + Store (0x0F, Local0) } - } - #ifndef NO_W83627HF_PS2M - Device (PS2M) { - Name (_HID, EisaId ("PNP0F13")) - Name (_UID, "w83627hf-ps2m") - - Method (_STA) + ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) { - Store (0x00, Local0) - ENCM () - Store (0x05, LDN) - If (LAnd(ACTR, IRQ1) ) { - Store (0x0F, Local0) - } - ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } - Method (_DIS) - { - ENCM () - Store (0x05, LDN) - Store (Zero, IRQ1) - EXCM () - } + Method (_DIS) + { + ENCM () + Store (0x05, LDN) + Store (Zero, ACTR) + EXCM () + Notify(PS2M, 1) + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IRQNoFlags (IRQX) {} - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) - }) - ENCM () - Store (0x05, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IO2H, Local2) - Store(IO2L, Local3) - Store(IRQ1, Local4) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x05, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IO2H, Local2) + Store(IO2L, Local3) + Store(IRQ0, Local4) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) - ShiftLeft(Local2, 8, Local2) - Or (Local1, Local0, Local0) + ShiftLeft(Local2, 8, Local2) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IO1._MIN, I1MI) - Store (Local2, I1MI) - CreateWordField (CRS, IO1._MAX, I1MA) - Store (Local2, I1MA) + CreateWordField (CRS, IO1._MIN, I1MI) + Store (Local2, I1MI) + CreateWordField (CRS, IO1._MAX, I1MA) + Store (Local2, I1MA) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local5) - ShiftLeft (Local5, Local4, IRQW) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local5) + ShiftLeft (Local5, Local4, IRQW) + + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IRQNoFlags () {12} - } - StartDependentFn (2,0) { - IRQNoFlags () {1,3,4,5,6,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 1, IO0) + IO (Decode16, 0, 0, 1, 1, IO1) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO1._MIN, IOA1) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IRQNoFlags (IRQX) {} - }) - CreateByteField (Arg0, IRQX._INT, IRQL) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local0) - Subtract (Local0, 0x01, Local0) + Divide(IOA1, 256, Local2, Local3) + ShiftRight(Local1, 8, Local1) - ENCM () - Store (5, LDN) - Store (Local0, IRQ1) - /* Only activates if KBD is active */ - Store (One, ACTR) - EXCM () - } - } - #endif - #endif + FindSetLeftBit (IRQL, Local4) + Subtract (Local4, 0x01, Local4) - #ifndef NO_W83627HF_GAME - /* ========================== Game Port ========================== */ - Device (GAME) { - Name (_HID, EisaId ("PNPB02F")) - Name (_STR, Unicode ("Joystick/Game Port")) - Name (_UID, "w83627hf-game") + ENCM () + Store (5, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IO2H) + Store (Local2, IO2L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #ifndef NO_W83627HF_PS2M + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_UID, "w83627hf-ps2m") - Method (_STA) { - ENCM () - Store(0, Local0) - Store (0x07, LDN) - If (LOr(IO1L, IO1H)) { - If (LOr(ACTR, ACT1)) { - Store (0x0F, Local0) - } - Else { - Store (0x0D, Local0) - } - } - EXCM () - Return (Local0) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x05, LDN) + If (LAnd(ACTR, IRQ1) ) { + Store (0x0F, Local0) } - - Method (_CRS) + ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x07, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) - - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) - - If (Local2) { - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - } - - Return (CRS) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } + Method (_DIS) + { + ENCM () + Store (0x05, LDN) + Store (Zero, IRQ1) + EXCM () } - #endif - #ifndef NO_W83627HF_MIDI - /* ========================== MIDI Port ========================== */ - Device (MIDI) { - Name (_HID, EisaId ("PNPB006")) - Name (_STR, Unicode ("MPU-401 Compatible MIDI Port")) - Name (_UID, "w83627hf-midi") + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IRQNoFlags (IRQX) {} + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + }) + ENCM () + Store (0x05, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IO2H, Local2) + Store(IO2L, Local3) + Store(IRQ1, Local4) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + ShiftLeft(Local2, 8, Local2) + Or (Local1, Local0, Local0) - Method (_STA) { - ENCM () - Store(0, Local0) - Store (0x07, LDN) - If (LOr(IO2L, IO2H)) { - If (LOr(ACTR, ACT2)) { - Store (0x0F, Local0) - } - Else { - Store (0x0D, Local0) - } - } - EXCM () - Return (Local0) - } + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x02, 0x02, IO0) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x07, LDN) - Store(IO2H, Local0) - Store(IO2L, Local1) - Store(IRQ1, Local2) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + CreateWordField (CRS, IO1._MIN, I1MI) + Store (Local2, I1MI) + CreateWordField (CRS, IO1._MAX, I1MA) + Store (Local2, I1MA) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local5) + ShiftLeft (Local5, Local4, IRQW) - If (Local2) { - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - } + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IRQNoFlags () {12} + } + StartDependentFn (2,0) { + IRQNoFlags () {1,3,4,5,6,7,9,10,11,12} } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IRQNoFlags (IRQX) {} + }) + CreateByteField (Arg0, IRQX._INT, IRQL) + FindSetLeftBit (IRQL, Local0) + Subtract (Local0, 0x01, Local0) + + ENCM () + Store (5, LDN) + Store (Local0, IRQ1) + /* Only activates if KBD is active */ + Store (One, ACTR) + EXCM () } - #endif + } + #endif + #endif + + #ifndef NO_W83627HF_GAME + /* ========================== Game Port ========================== */ + Device (GAME) { + Name (_HID, EisaId ("PNPB02F")) + Name (_STR, Unicode ("Joystick/Game Port")) + Name (_UID, "w83627hf-game") - /* ==== Suspend LED control if it is connected to the SuperIO ==== */ - Method (SLED, 1) { + Method (_STA) { ENCM () - Store (9, LDN) - Store(OPT4, Local0) - And(Local0, 63, Local0) - Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + Store(0, Local0) + Store (0x07, LDN) + If (LOr(IO1L, IO1H)) { + If (LOr(ACTR, ACT1)) { + Store (0x0F, Local0) + } + Else { + Store (0x0D, Local0) + } + } EXCM () + Return (Local0) } - /* ===== Power LED control if it is connected to the SuperIO ===== */ - Method (PLED, 1) { + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IRQNoFlags (IRQX) {} + }) ENCM () - Store (8, LDN) - Store(OPT4, Local0) - And(Local0, 63, Local0) - Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + Store (0x07, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IRQ0, Local2) EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + } + + Return (CRS) } - #ifndef NO_W83627HF_HWMON - /* ====================== Hardware Monitor ======================= */ - Device (HMON) { - Name (_HID, EisaId ("PNP0C02")) // TODO: find better matching ID - Name (_STR, Unicode("W83627 Hardware Monitor")) - Name (_UID, "w83627hf-hwmon") + } + #endif + + #ifndef NO_W83627HF_MIDI + /* ========================== MIDI Port ========================== */ + Device (MIDI) { + Name (_HID, EisaId ("PNPB006")) + Name (_STR, Unicode ("MPU-401 Compatible MIDI Port")) + Name (_UID, "w83627hf-midi") - Method (_STA) - { - Store (0x00, Local0) - ENCM () - Store (0x0B, LDN) - If (ACTR) { + Method (_STA) { + ENCM () + Store(0, Local0) + Store (0x07, LDN) + If (LOr(IO2L, IO2H)) { + If (LOr(ACTR, ACT2)) { Store (0x0F, Local0) } - ElseIf (LOr (IO1H, IO1L)) - { + Else { Store (0x0D, Local0) } - EXCM () - Return (Local0) } + EXCM () + Return (Local0) + } - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (HWPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, HWPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, HWPW) - EXCM () + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x02, 0x02, IO0) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x07, LDN) + Store(IO2H, Local0) + Store(IO2L, Local1) + Store(IRQ1, Local2) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x0B, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IRQ1, Local2) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + Return (CRS) + } - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + } + #endif - If (Local2) { - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - } - Return (CRS) + /* ==== Suspend LED control if it is connected to the SuperIO ==== */ + Method (SLED, 1) { + ENCM () + Store (9, LDN) + Store(OPT4, Local0) + And(Local0, 63, Local0) + Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + EXCM () + } + + /* ===== Power LED control if it is connected to the SuperIO ===== */ + Method (PLED, 1) { + ENCM () + Store (8, LDN) + Store(OPT4, Local0) + And(Local0, 63, Local0) + Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + EXCM () + } + + #ifndef NO_W83627HF_HWMON + /* ====================== Hardware Monitor ======================= */ + Device (HMON) { + Name (_HID, EisaId ("PNP0C02")) // TODO: find better matching ID + Name (_STR, Unicode("W83627 Hardware Monitor")) + Name (_UID, "w83627hf-hwmon") + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x0B, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) } + EXCM () + Return (Local0) } - #endif - /* Returns the wake source register. - It is cleared after reading. - Bit 0: Keyboard wake-up event - Bit 1: Mouse wake-up event - Bit 2: Power button event - Bit 3: CIR wake-up event - Bit 4: Power loss event - Bit 5: VSB power loss status - */ - Method (WAKS) { + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } ENCM () - Store (0x0A, LDN) - Store (CRE3, Local0) + Store (HWPW, Local0) EXCM () - Return (Local0) + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, HWPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, HWPW) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x0B, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IRQ1, Local2) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + } + Return (CRS) } } + #endif + + /* Returns the wake source register. + It is cleared after reading. + Bit 0: Keyboard wake-up event + Bit 1: Mouse wake-up event + Bit 2: Power button event + Bit 3: CIR wake-up event + Bit 4: Power loss event + Bit 5: VSB power loss status + */ + Method (WAKS) { + ENCM () + Store (0x0A, LDN) + Store (CRE3, Local0) + EXCM () + Return (Local0) + } } From gerrit at coreboot.org Fri Nov 4 04:48:28 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:28 +0100 Subject: [coreboot] Patch set updated for coreboot: 82354c2 support for different location of HT registers in old version of K8T800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/373 -gerrit commit 82354c2cd625874c92657024e5d2d0c3c4e5e3b9 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:14 2011 +0100 support for different location of HT registers in old version of K8T800 Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/early_car.c | 30 ++++++++++++++++++++++-------- 1 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index c554c49..da7b4db 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -35,6 +35,12 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#define K8X8XX_HT_CFG_BASE 0xc0 +#else +#define K8X8XX_HT_CFG_BASE 0x60 +#endif + /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init. * This will not work for K8T800_OLD, which has a slightly different @@ -43,10 +49,13 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; u8 k8t890_early_setup_ht(void) { - u8 awidth, afreq, cldtfreq, reg; + u8 awidth, afreq, cldtfreq; u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + u8 reg; + /* hack, enable NVRAM in chipset */ pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); @@ -58,6 +67,7 @@ u8 k8t890_early_setup_ht(void) reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); reg |= 0x1; pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); +#endif /* check if connected non coherent, initcomplete (find the SB on K8 side) */ ldtnr = 0; @@ -73,6 +83,10 @@ u8 k8t890_early_setup_ht(void) print_debug("K8M800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800 print_debug("K8T800 found at LDT "); +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + print_debug("K8T800_OLD found at LDT "); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO print_debug("K8T800 Pro found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8M890 @@ -87,19 +101,19 @@ u8 k8t890_early_setup_ht(void) /* get the maximum widths for both sides */ cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7; - vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7; - vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7; + vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) & 0x7; + vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7; width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); print_debug(" Agreed on width: "); print_debug_hex8(width); - awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7); /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */ width = (width == 0x01) ? 0x11 : 0x00; - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7, width); /* Get programmed HT freq at base 0x89 */ cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; @@ -107,15 +121,15 @@ u8 k8t890_early_setup_ht(void) print_debug_hex8(cldtfreq); print_debug(" VIA HT caps: "); - vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e); + vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe); print_debug_hex16(vldtcaps); if (!(vldtcaps & (1 << cldtfreq ))) { die("Chipset does not support desired HT frequency\n"); } - afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq); + afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq); print_debug("\n"); /* no reset needed */ From gerrit at coreboot.org Fri Nov 4 04:48:28 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:28 +0100 Subject: [coreboot] Patch set updated for coreboot: 96dfc09 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/374 -gerrit commit 96dfc09211bb3353570754ca67f3820cf0b50ec0 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:41 2011 +0100 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/romstrap.inc | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc index 5b24948..a3814b0 100644 --- a/src/southbridge/via/k8t890/romstrap.inc +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -33,7 +33,7 @@ __romstrap_start: * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ -#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD tblpointer: .long 0x50220000, 0X619707C2 diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index e599517..b1e1afe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_K8T800 + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */ From gerrit at coreboot.org Fri Nov 4 04:48:29 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:29 +0100 Subject: [coreboot] Patch set updated for coreboot: 5efd84c in vt8237r_enable(), write function enables only to ISA bridge config space References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/368 -gerrit commit 5efd84c282f8f82ab562577c9efbb78c21a0e799 Author: Florian Zumbiehl Date: Tue Nov 1 20:16:16 2011 +0100 in vt8237r_enable(), write function enables only to ISA bridge config space vt8237r_enable() so far wrote the function enable values to the same offset in the config space of every one of the vt8237's functions, even though the register is located in the ISA bridge only. Change-Id: I639586dc238132f5b8d2f320b794948718281b9c Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/vt8237r.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 5ba3815..586df66 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -66,11 +66,21 @@ void dump_south(device_t dev) static void vt8237r_enable(struct device *dev) { + u16 vid, did; struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; - pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); - pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + if (dev->path.type == DEVICE_PATH_PCI) { + vid = pci_read_config16(dev, PCI_VENDOR_ID); + did = pci_read_config16(dev, PCI_DEVICE_ID); + if (vid == PCI_VENDOR_ID_VIA && + (did == PCI_DEVICE_ID_VIA_VT8237R_LPC || + did == PCI_DEVICE_ID_VIA_VT8237A_LPC || + did == PCI_DEVICE_ID_VIA_VT8237S_LPC)) { + pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); + pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + } + } /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ } From gerrit at coreboot.org Fri Nov 4 04:48:29 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:29 +0100 Subject: [coreboot] Patch set updated for coreboot: 3e13da8 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/370 -gerrit commit 3e13da8aa63cd8ec6e4657e7bbc0a23b45a76257 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:12 2011 +0100 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit_f.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 319293b..dc3addb 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i 18, /* *Supported CAS Latencies */ 9, /* *Cycle time at highest CAS Latency CL=X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ - 26, /* *Cycle time at CAS Latency (CLX - 2) */ + 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; u8 common_cl; From gerrit at coreboot.org Fri Nov 4 04:48:30 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:30 +0100 Subject: [coreboot] Patch set updated for coreboot: 51f9635 make w83697hf_set_clksel_48() non-static and add a prototype References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit 51f9635f0b78f025b09c9745eec7a6768ae2649e Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 make w83697hf_set_clksel_48() non-static and add a prototype make w83697hf_set_clksel_48() non-static and add a prototype so as to get rid of warnings about it being unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/early_serial.c | 2 +- src/superio/winbond/w83697hf/w83697hf.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..2825eeb 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(device_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 0eeb37c..6488dd3 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -32,4 +32,8 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ +#ifndef __ROMCC__ +void w83697hf_set_clksel_48(device_t); +#endif + #endif From gerrit at coreboot.org Fri Nov 4 04:48:31 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:31 +0100 Subject: [coreboot] Patch set updated for coreboot: 70d2309 add support for setting the vt8237 to uncond. power on after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 70d2309014db84e3cdd0a19eeb0a69416ac8c90a Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..0e757fe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Fri Nov 4 04:48:31 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:31 +0100 Subject: [coreboot] Patch set updated for coreboot: c7f56fd support for setting the Memory DQ Drive Strength register in amdk8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit c7f56fd75e8ad765d575d7d151ebf69fb6f884fe Author: Florian Zumbiehl Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit make sure DRAM drive strength is not reduced Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 12 ++++++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 02c764d..e09075f 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2201,6 +2201,18 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + + if (!is_cpu_pre_e0()) { + uint32_t dch; + + // see also erratum 114, essentially: never ever + // set to anything but 0 + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= DCH_DQ_DRV_STRENGTH_0 << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; From gerrit at coreboot.org Fri Nov 4 04:48:32 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:32 +0100 Subject: [coreboot] Patch set updated for coreboot: fbba27f k8 raminit: fix bug, improve clock selection, add clock limit for sock754 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit fbba27f37ebe6eba14e1dc9c593cda1b6e8717d9 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 349 +++++++++++++++++------------------ 1 files changed, 166 insertions(+), 183 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..02c764d 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1230,8 +1230,8 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 17, /* *Logical Banks */ 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ - 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 23, /* *Cycle time at CAS Latency (CLX - 0.5) */ + 25, /* *Cycle time at CAS Latency (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,11 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) +{ #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1441,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos = 0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1475,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1484,190 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table + * are to be understood: + */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; + +#else /* CONFIG_CPU_AMD_SOCKET_* */ + +// well, there are socket 940 boards supported which obviously fail to +// compile with this +// #error load dependent memory clock limiting is not implemented for this socket -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ + /* see BKDG 4.1.3--if you just want to test a setup that doesn't + * require limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what + * would be intuitive. 200 MHz has the lowest constant, 100 MHz the + * highest. Thus, all comparisons and traversal directions having to + * do with frequencies are/have to be the opposite of what would be + * intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + // the CLs supported by the controller: + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); + memset(cl_at_freq, 0x00, + (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> + NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle + * shorter, select that (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#if CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1689,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; From gerrit at coreboot.org Fri Nov 4 04:48:33 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:33 +0100 Subject: [coreboot] Patch set updated for coreboot: 5569f9b fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/376 -gerrit commit 5569f9bce7ac3e254ffaf379985ad4e58f509a0a Author: Florian Zumbiehl Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 3583dc3..237272c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1399,7 +1399,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) #define DDR400 (NBCAP_MEMCLK_200MHZ + 1) #define DDR_2T 0x80 -#define DDR_MASK 0x3 +#define DDR_MASK 0x7 #define DDR200_2T (DDR_2T | DDR200) #define DDR333_2T (DDR_2T | DDR333) From gerrit at coreboot.org Fri Nov 4 04:48:34 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:34 +0100 Subject: [coreboot] Patch set updated for coreboot: 9b62c5c rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit 9b62c5c0c4093d8439ed1560f2834fe7b7d4cc25 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include #include +#ifndef __PRE_RAM__ +#include +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Fri Nov 4 04:48:35 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:35 +0100 Subject: [coreboot] Patch set updated for coreboot: 4d52be8 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/378 -gerrit commit 4d52be8fe84e9e52dbd4ba9849fb559dd18dcb29 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 49 ++++++---------------------------- src/southbridge/via/k8t890/dram.c | 18 ++++++------ src/southbridge/via/k8t890/k8x8xx.h | 25 ++++++++++++++++++ 3 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 42676b1..7363510 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -31,31 +31,8 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - if(!devfun3) - die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); + u8 regm3; + struct k8x8xx_vt8237_mirrored_regs mregs; pci_write_config8(dev, 0x70, 0xc2); @@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); + k8x8xx_vt8237_mirrored_regs_fill(&mregs); - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); + pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */ + pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */ + pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */ - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! @@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) regm3 = 0x0; /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F)); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e..294e387 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index a0fb57a..425aaeb 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -21,6 +21,31 @@ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#include +#include #include "k8t890.h" +struct k8x8xx_vt8237_mirrored_regs { + u16 low_top_address; + u8 rom_shadow_ctrl_pg_c, + rom_shadow_ctrl_pg_d, + rom_shadow_ctrl_pg_e_memhole_smi_decoding, + rom_shadow_ctrl_pg_f_memhole, + smm_apic_decoding, + shadow_mem_ctrl; +}; + +static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Fri Nov 4 04:48:35 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:35 +0100 Subject: [coreboot] Patch set updated for coreboot: 87884bb make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 87884bb73ee2f3a1928db84e57abb44ce23dc55a Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index d4f7820..7d7326c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Fri Nov 4 04:48:36 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:36 +0100 Subject: [coreboot] Patch set updated for coreboot: 5c4d94e make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 5c4d94e1fae52729a682d9129bb1310f09aae9dc Author: Florian Zumbiehl Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 0e757fe..d4f7820 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -506,7 +517,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */ From gerrit at coreboot.org Fri Nov 4 04:48:36 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:36 +0100 Subject: [coreboot] Patch set updated for coreboot: 39b2dba implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit 39b2dba740c9dcb1ae8ac320b37959f7a4bff1d7 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..2bdcf9d 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | + (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | + (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | + (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | + (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, + (pci_read_config8(dev, 0x5c) & ~0x70) | + (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Fri Nov 4 04:48:37 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:37 +0100 Subject: [coreboot] Patch set updated for coreboot: 5576e65 implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit 5576e6584fad657aefc978320b84defe1fc26e1e Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Fri Nov 4 04:48:38 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:38 +0100 Subject: [coreboot] Patch set updated for coreboot: c58e866 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit c58e8668506398159d6830c276fcc133d77da709 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 21 ++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 116 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..6b32ea3 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,25 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +43,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +73,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Fri Nov 4 04:48:39 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:39 +0100 Subject: [coreboot] Patch set updated for coreboot: 0757b35 copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit 0757b35e372abefe23195c0044c9cf74b4d73488 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Fri Nov 4 04:48:41 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 04:48:41 +0100 Subject: [coreboot] Patch set updated for coreboot: b287f71 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit b287f71c5dfa8f39afb7e5d50ab584dd169e2c65 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From gerrit at coreboot.org Fri Nov 4 12:37:24 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 4 Nov 2011 12:37:24 +0100 Subject: [coreboot] New patch to review for coreboot: 95f5a4a libpayload: Drop usb_fatal() References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/395 -gerrit commit 95f5a4a01add4fcfb6db42fd9509a2ecc7b35c88 Author: Patrick Georgi Date: Fri Nov 4 11:50:03 2011 +0100 libpayload: Drop usb_fatal() We have fatal(), which is just as good. Coccinelle script: @@ expression E; @@ -usb_fatal(E) +fatal(E) Change-Id: Iabecbcc7d068cc0f82687bf51d89c2626642cd86 Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/usb/ehci.c | 4 ++-- payloads/libpayload/drivers/usb/ohci.c | 4 ++-- payloads/libpayload/drivers/usb/ohci_rh.c | 2 +- payloads/libpayload/drivers/usb/uhci.c | 16 ++++++++-------- payloads/libpayload/drivers/usb/uhci_rh.c | 2 +- payloads/libpayload/drivers/usb/usb.c | 6 ------ payloads/libpayload/drivers/usb/usbhid.c | 2 +- payloads/libpayload/drivers/usb/usbhub.c | 4 ++-- payloads/libpayload/drivers/usb/usbmsc.c | 2 +- payloads/libpayload/drivers/usb/xhci.c | 10 +++++----- payloads/libpayload/drivers/usb/xhci_rh.c | 2 +- payloads/libpayload/include/usb/usb.h | 1 - 12 files changed, 24 insertions(+), 31 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index d979121..92e4911 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -312,11 +312,11 @@ ehci_init (pcidev_t addr) hci_t *controller = new_controller (); if (!controller) - usb_fatal("Could not create USB controller instance.\n"); + fatal("Could not create USB controller instance.\n"); controller->instance = malloc (sizeof (ehci_t)); if(!controller->instance) - usb_fatal("Not enough memory creating USB controller instance.\n"); + fatal("Not enough memory creating USB controller instance.\n"); #define PCI_COMMAND 4 #define PCI_COMMAND_IO 1 diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index ef33bd9..60866d8 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -88,11 +88,11 @@ ohci_init (pcidev_t addr) hci_t *controller = new_controller (); if (!controller) - usb_fatal("Could not create USB controller instance.\n"); + fatal("Could not create USB controller instance.\n"); controller->instance = malloc (sizeof (ohci_t)); if(!controller->instance) - usb_fatal("Not enough memory creating USB controller instance.\n"); + fatal("Not enough memory creating USB controller instance.\n"); controller->start = ohci_start; controller->stop = ohci_stop; diff --git a/payloads/libpayload/drivers/usb/ohci_rh.c b/payloads/libpayload/drivers/usb/ohci_rh.c index da74340..5cf7ee8 100644 --- a/payloads/libpayload/drivers/usb/ohci_rh.c +++ b/payloads/libpayload/drivers/usb/ohci_rh.c @@ -143,7 +143,7 @@ ohci_rh_init (usbdev_t *dev) dev->data = malloc (sizeof (rh_inst_t)); if (!dev->data) - usb_fatal ("Not enough memory for OHCI RH.\n"); + fatal("Not enough memory for OHCI RH.\n"); RH_INST (dev)->numports = OHCI_INST (dev->controller)->opreg->HcRhDescriptorA & NumberDownstreamPortsMask; RH_INST (dev)->port = malloc(sizeof(int) * RH_INST (dev)->numports); diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index 1f80c6a..3710872 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -134,11 +134,11 @@ uhci_init (pcidev_t addr) hci_t *controller = new_controller (); if (!controller) - usb_fatal("Could not create USB controller instance.\n"); + fatal("Could not create USB controller instance.\n"); controller->instance = malloc (sizeof (uhci_t)); if(!controller->instance) - usb_fatal("Not enough memory creating USB controller instance.\n"); + fatal("Not enough memory creating USB controller instance.\n"); controller->start = uhci_start; controller->stop = uhci_stop; @@ -168,7 +168,7 @@ uhci_init (pcidev_t addr) UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t *)); /* 4kb aligned to 4kb */ if (! UHCI_INST (controller)->framelistptr) - usb_fatal("Not enough memory for USB frame list pointer.\n"); + fatal("Not enough memory for USB frame list pointer.\n"); memset (UHCI_INST (controller)->framelistptr, 0, 1024 * sizeof (flistp_t)); @@ -182,7 +182,7 @@ uhci_init (pcidev_t addr) */ td_t *antiberserk = memalign(16, sizeof(td_t)); if (!antiberserk) - usb_fatal("Not enough memory for chipset workaround.\n"); + fatal("Not enough memory for chipset workaround.\n"); memset(antiberserk, 0, sizeof(td_t)); UHCI_INST (controller)->qh_prei = memalign (16, sizeof (qh_t)); @@ -194,7 +194,7 @@ uhci_init (pcidev_t addr) ! UHCI_INST (controller)->qh_intr || ! UHCI_INST (controller)->qh_data || ! UHCI_INST (controller)->qh_last) - usb_fatal ("Not enough memory for USB controller queues.\n"); + fatal("Not enough memory for USB controller queues.\n"); UHCI_INST (controller)->qh_prei->headlinkptr.ptr = virt_to_phys (UHCI_INST (controller)->qh_intr); @@ -443,7 +443,7 @@ uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize) { int maxpsize = ep->maxpacketsize; if (maxpsize == 0) - usb_fatal ("MaxPacketSize == 0!!!"); + fatal("MaxPacketSize == 0!!!"); int numpackets = (size + maxpsize - 1 + finalize) / maxpsize; if (numpackets == 0) return 0; @@ -486,7 +486,7 @@ uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming qh_t *qh = memalign(16, sizeof(qh_t)); if (!data || !tds || !qh) - usb_fatal ("Not enough memory to create USB intr queue prerequisites.\n"); + fatal("Not enough memory to create USB intr queue prerequisites.\n"); qh->elementlinkptr.ptr = virt_to_phys(tds); qh->elementlinkptr.queue_head = 0; @@ -494,7 +494,7 @@ uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming intr_q *q = malloc(sizeof(intr_q)); if (!q) - usb_fatal ("Not enough memory to create USB intr queue.\n"); + fatal("Not enough memory to create USB intr queue.\n"); q->qh = qh; q->tds = tds; q->data = data; diff --git a/payloads/libpayload/drivers/usb/uhci_rh.c b/payloads/libpayload/drivers/usb/uhci_rh.c index cf5d5a7..479293b 100644 --- a/payloads/libpayload/drivers/usb/uhci_rh.c +++ b/payloads/libpayload/drivers/usb/uhci_rh.c @@ -178,7 +178,7 @@ uhci_rh_init (usbdev_t *dev) uhci_rh_enable_port (dev, 2); dev->data = malloc (sizeof (rh_inst_t)); if (!dev->data) - usb_fatal ("Not enough memory for UHCI RH.\n"); + fatal("Not enough memory for UHCI RH.\n"); RH_INST (dev)->port[0] = -1; RH_INST (dev)->port[1] = -1; diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index d5f47e4..8028d17 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -459,9 +459,3 @@ usb_attach_device(hci_t *controller, int hubaddress, int port, int speed) return newdev; } -void -usb_fatal (const char *message) -{ - printf(message); - for (;;) ; -} diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c index bf3ec1e..b9ea238 100644 --- a/payloads/libpayload/drivers/usb/usbhid.c +++ b/payloads/libpayload/drivers/usb/usbhid.c @@ -423,7 +423,7 @@ usb_hid_init (usbdev_t *dev) case hid_boot_proto_keyboard: dev->data = malloc (sizeof (usbhid_inst_t)); if (!dev->data) - usb_fatal("Not enough memory for USB HID device.\n"); + fatal("Not enough memory for USB HID device.\n"); debug (" configuring...\n"); usb_hid_set_protocol(dev, interface, hid_proto_boot); usb_hid_set_idle(dev, interface, KEYBOARD_REPEAT_MS); diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index fcf4f36..08042a2 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -135,7 +135,7 @@ usb_hub_init (usbdev_t *dev) dev->data = malloc (sizeof (usbhub_inst_t)); if (!dev->data) - usb_fatal("Not enough memory for USB hub.\n"); + fatal("Not enough memory for USB hub.\n"); HUB_INST (dev)->descriptor = (hub_descriptor_t *) get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, dev_recp), 0x29, 0, 0); @@ -143,7 +143,7 @@ usb_hub_init (usbdev_t *dev) HUB_INST (dev)->ports = malloc (sizeof (int) * (HUB_INST (dev)->num_ports + 1)); if (! HUB_INST (dev)->ports) - usb_fatal("Not enough memory for USB hub ports.\n"); + fatal("Not enough memory for USB hub ports.\n"); for (i = 1; i <= HUB_INST (dev)->num_ports; i++) HUB_INST (dev)->ports[i] = -1; diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 6658f2c..55443b8 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -397,7 +397,7 @@ usb_msc_init (usbdev_t *dev) dev->data = malloc (sizeof (usbmsc_inst_t)); if (!dev->data) - usb_fatal ("Not enough memory for USB MSC device.\n"); + fatal("Not enough memory for USB MSC device.\n"); MSC_INST (dev)->protocol = interface->bInterfaceSubClass; MSC_INST (dev)->bulk_in = 0; diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 0aca63d..a25cf40 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -57,11 +57,11 @@ xhci_init (pcidev_t addr) hci_t *controller = new_controller (); if (!controller) - usb_fatal("Could not create USB controller instance.\n"); + fatal("Could not create USB controller instance.\n"); controller->instance = malloc (sizeof (xhci_t)); if(!controller->instance) - usb_fatal("Not enough memory creating USB controller instance.\n"); + fatal("Not enough memory creating USB controller instance.\n"); controller->start = xhci_start; controller->stop = xhci_stop; @@ -82,7 +82,7 @@ xhci_init (pcidev_t addr) controller->reg_base = (u32)phys_to_virt(pci_read_config32 (controller->bus_address, 0x10) & ~0xf); //controller->reg_base = pci_read_config32 (controller->bus_address, 0x14) & ~0xf; if (pci_read_config32 (controller->bus_address, 0x14) > 0) { - usb_fatal("We don't do 64bit addressing.\n"); + fatal("We don't do 64bit addressing.\n"); } debug("regbase: %lx\n", controller->reg_base); @@ -94,7 +94,7 @@ xhci_init (pcidev_t addr) debug("caplength: %x\n", XHCI_INST (controller)->capreg->caplength); debug("hciversion: %x.%x\n", XHCI_INST (controller)->capreg->hciver_hi, XHCI_INST (controller)->capreg->hciver_lo); if ((XHCI_INST (controller)->capreg->hciversion < 0x96) || (XHCI_INST (controller)->capreg->hciversion > 0x100)) { - usb_fatal("Unsupported xHCI version\n"); + fatal("Unsupported xHCI version\n"); } debug("maxslots: %x\n", XHCI_INST (controller)->capreg->MaxSlots); debug("maxports: %x\n", XHCI_INST (controller)->capreg->MaxPorts); @@ -233,7 +233,7 @@ xhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize) { int maxpsize = ep->maxpacketsize; if (maxpsize == 0) - usb_fatal ("MaxPacketSize == 0!!!"); + fatal("MaxPacketSize == 0!!!"); return 1; } diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index 2817f04..1547ef6 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -112,7 +112,7 @@ xhci_rh_init (usbdev_t *dev) dev->data = malloc (sizeof (rh_inst_t)); if (!dev->data) - usb_fatal ("Not enough memory for XHCI RH.\n"); + fatal("Not enough memory for XHCI RH.\n"); RH_INST (dev)->numports = XHCI_INST (dev->controller)->capreg->MaxPorts; RH_INST (dev)->port = malloc(sizeof(int) * RH_INST (dev)->numports); diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index daad493..0c68379 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -257,5 +257,4 @@ int usb_interface_check(u16 vendor, u16 device); #define debug(x...) #endif -void usb_fatal(const char *message) __attribute__ ((noreturn)); #endif From gerrit at coreboot.org Fri Nov 4 12:37:25 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 4 Nov 2011 12:37:25 +0100 Subject: [coreboot] New patch to review for coreboot: 30ce4bb libpayload: Tell EHCI to re-enable USB1 controllers References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/396 -gerrit commit 30ce4bb498a57324f205fc410ed30e4dfba95d3e Author: Patrick Georgi Date: Fri Nov 4 11:57:46 2011 +0100 libpayload: Tell EHCI to re-enable USB1 controllers EHCI can take over all ports (and then reroute devices to companion controllers if needs be). We do that, and then never reset it. Consequence: Systems with only USB1 HC drivers (OHCI/UHCI) never see any devices. Change-Id: If1d91e9142a6618289b0b3f6b56587ec857158e3 Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/usb/ehci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 92e4911..e20bacd 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -56,7 +56,7 @@ static void ehci_reset (hci_t *controller) static void ehci_shutdown (hci_t *controller) { - + EHCI_INST(controller)->operation->configflag = 0; } enum { EHCI_OUT=0, EHCI_IN=1, EHCI_SETUP=2 }; From gerrit at coreboot.org Fri Nov 4 12:37:25 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 4 Nov 2011 12:37:25 +0100 Subject: [coreboot] New patch to review for coreboot: a77bd25 libpayload: Implement usb_exit References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/397 -gerrit commit a77bd2597723266a82d50fd76ffe7c305731ce59 Author: Patrick Georgi Date: Fri Nov 4 12:06:06 2011 +0100 libpayload: Implement usb_exit So far it was empty and never published. It now exists and shuts down all controllers (esp. EHCI which resets the port routers). Change-Id: I81e355e8a05778d6397675417b085a094a6f48ee Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/usb/usb.c | 16 ++++++++++++++++ payloads/libpayload/drivers/usb/usbinit.c | 5 ----- payloads/libpayload/include/libpayload.h | 1 + 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 8028d17..b60a463 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -68,6 +68,22 @@ detach_controller (hci_t *controller) } /** + * Shut down all controllers + */ +int +usb_exit (void) +{ + if (usb_hcs == 0) + return 0; + hci_t *controller = usb_hcs; + while (controller != 0) { + controller->shutdown(controller); + controller = controller->next; + } + return 0; +} + +/** * Polls all hubs on all USB controllers, to find out about device changes */ void diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index d3cfbb7..e8c7a78 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -139,8 +139,3 @@ usb_initialize (void) return 0; } -int -usb_exit (void) -{ - return 0; -} diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 80eaaa4..0e892c8 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -123,6 +123,7 @@ void rtc_read_clock(struct tm *tm); * @{ */ int usb_initialize(void); +int usb_exit (void); int usbhid_havechar(void); int usbhid_getchar(void); /** @} */ From gerrit at coreboot.org Fri Nov 4 13:18:26 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 4 Nov 2011 13:18:26 +0100 Subject: [coreboot] New patch to review for coreboot: 353bd36 Revert "add support for 1106:3188 (host controller of the old version of k8t800)" due to dependency issues. References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/398 -gerrit commit 353bd36b008f489a972c7c656d7ad07416f01387 Author: Patrick Georgi Date: Fri Nov 4 13:18:26 2011 +0100 Revert "add support for 1106:3188 (host controller of the old version of k8t800)" due to dependency issues. This reverts commit 68c554550f59bd96caace96260ae2e30ed55ceb4 --- src/southbridge/via/k8t890/host.c | 45 ------------------------------------- 1 files changed, 0 insertions(+), 45 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 700a637..13bd693 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,36 +25,6 @@ #include #include "k8x8xx.h" -static void host_old_enable(struct device *dev) -{ - int agp3; - - /* some HT tweaking */ - pci_write_config8(dev, 0x50, 0x03); - pci_write_config8(dev, 0x55, 0x2c); - - /* AGP setup */ - pci_write_config8(dev, 0xac, 0x06); - pci_write_config8(dev, 0xad, 0x08); - pci_write_config8(dev, 0xfd, 0x02); - pci_write_config8(dev, 0x85, 0xb0); - pci_write_config8(dev, 0x87, 0x07); - pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work - pci_write_config8(dev, 0xaf, 0x88); - pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 - agp3 = pci_read_config8(dev, 0x84) & 0x08; - pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); - pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); - pci_write_config8(dev, 0xb0, 0x40); - pci_write_config8(dev, 0xb2, 0x11); - pci_write_config8(dev, 0xed, 0x40); -} - -static void host_old_init(struct device *dev) -{ - k8x8xx_vt8237r_cfg(dev, NULL); -} - static void host_enable(struct device *dev) { /* Multiple function control */ @@ -86,15 +56,6 @@ static void host_init(struct device *dev) } -static const struct device_operations host_ops_old = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = host_old_enable, - .init = host_old_init, - .ops_pci = 0, -}; - static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -112,12 +73,6 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t800_old __pci_driver = { - .ops = &host_ops_old, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T800_AGP, -}; - static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, From gerrit at coreboot.org Fri Nov 4 16:44:55 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 4 Nov 2011 16:44:55 +0100 Subject: [coreboot] Patch merged into coreboot/master: 353bd36 Revert "add support for 1106:3188 (host controller of the old version of k8t800)" due to dependency issues. References: Message-ID: the following patch was just integrated into master: commit 353bd36b008f489a972c7c656d7ad07416f01387 Author: Patrick Georgi Date: Fri Nov 4 13:18:26 2011 +0100 Revert "add support for 1106:3188 (host controller of the old version of k8t800)" due to dependency issues. This reverts commit 68c554550f59bd96caace96260ae2e30ed55ceb4 Build-Tested: build bot (Jenkins) at Fri Nov 4 13:28:19 2011, giving +1 Reviewed-By: Stefan Reinauer at Fri Nov 4 16:44:53 2011, giving +2 See http://review.coreboot.org/398 for details. -gerrit From gerrit at coreboot.org Fri Nov 4 21:28:14 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 4 Nov 2011 21:28:14 +0100 Subject: [coreboot] Patch set updated for coreboot: 7abb7c9 libpayload: Drop usb_fatal() References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/395 -gerrit commit 7abb7c9925a2daab92538796aaf64e84e5a47114 Author: Patrick Georgi Date: Fri Nov 4 11:50:03 2011 +0100 libpayload: Drop usb_fatal() We have fatal(), which is just as good. Coccinelle script: @@ expression E; @@ -usb_fatal(E) +fatal(E) Change-Id: Iabecbcc7d068cc0f82687bf51d89c2626642cd86 Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/usb/ehci.c | 4 ++-- payloads/libpayload/drivers/usb/ohci.c | 4 ++-- payloads/libpayload/drivers/usb/ohci_rh.c | 2 +- payloads/libpayload/drivers/usb/uhci.c | 16 ++++++++-------- payloads/libpayload/drivers/usb/uhci_rh.c | 2 +- payloads/libpayload/drivers/usb/usb.c | 6 ------ payloads/libpayload/drivers/usb/usbhid.c | 2 +- payloads/libpayload/drivers/usb/usbhub.c | 4 ++-- payloads/libpayload/drivers/usb/usbmsc.c | 2 +- payloads/libpayload/drivers/usb/xhci.c | 10 +++++----- payloads/libpayload/drivers/usb/xhci_rh.c | 2 +- payloads/libpayload/include/usb/usb.h | 1 - 12 files changed, 24 insertions(+), 31 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index f258e07..b1ccb0b 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -312,11 +312,11 @@ ehci_init (pcidev_t addr) hci_t *controller = new_controller (); if (!controller) - usb_fatal("Could not create USB controller instance.\n"); + fatal("Could not create USB controller instance.\n"); controller->instance = malloc (sizeof (ehci_t)); if(!controller->instance) - usb_fatal("Not enough memory creating USB controller instance.\n"); + fatal("Not enough memory creating USB controller instance.\n"); #define PCI_COMMAND 4 #define PCI_COMMAND_IO 1 diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index ef33bd9..60866d8 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -88,11 +88,11 @@ ohci_init (pcidev_t addr) hci_t *controller = new_controller (); if (!controller) - usb_fatal("Could not create USB controller instance.\n"); + fatal("Could not create USB controller instance.\n"); controller->instance = malloc (sizeof (ohci_t)); if(!controller->instance) - usb_fatal("Not enough memory creating USB controller instance.\n"); + fatal("Not enough memory creating USB controller instance.\n"); controller->start = ohci_start; controller->stop = ohci_stop; diff --git a/payloads/libpayload/drivers/usb/ohci_rh.c b/payloads/libpayload/drivers/usb/ohci_rh.c index da74340..5cf7ee8 100644 --- a/payloads/libpayload/drivers/usb/ohci_rh.c +++ b/payloads/libpayload/drivers/usb/ohci_rh.c @@ -143,7 +143,7 @@ ohci_rh_init (usbdev_t *dev) dev->data = malloc (sizeof (rh_inst_t)); if (!dev->data) - usb_fatal ("Not enough memory for OHCI RH.\n"); + fatal("Not enough memory for OHCI RH.\n"); RH_INST (dev)->numports = OHCI_INST (dev->controller)->opreg->HcRhDescriptorA & NumberDownstreamPortsMask; RH_INST (dev)->port = malloc(sizeof(int) * RH_INST (dev)->numports); diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index 4484e17..779098b 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -134,11 +134,11 @@ uhci_init (pcidev_t addr) hci_t *controller = new_controller (); if (!controller) - usb_fatal("Could not create USB controller instance.\n"); + fatal("Could not create USB controller instance.\n"); controller->instance = malloc (sizeof (uhci_t)); if(!controller->instance) - usb_fatal("Not enough memory creating USB controller instance.\n"); + fatal("Not enough memory creating USB controller instance.\n"); controller->start = uhci_start; controller->stop = uhci_stop; @@ -168,7 +168,7 @@ uhci_init (pcidev_t addr) UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t *)); /* 4kb aligned to 4kb */ if (! UHCI_INST (controller)->framelistptr) - usb_fatal("Not enough memory for USB frame list pointer.\n"); + fatal("Not enough memory for USB frame list pointer.\n"); memset (UHCI_INST (controller)->framelistptr, 0, 1024 * sizeof (flistp_t)); @@ -182,7 +182,7 @@ uhci_init (pcidev_t addr) */ td_t *antiberserk = memalign(16, sizeof(td_t)); if (!antiberserk) - usb_fatal("Not enough memory for chipset workaround.\n"); + fatal("Not enough memory for chipset workaround.\n"); memset(antiberserk, 0, sizeof(td_t)); UHCI_INST (controller)->qh_prei = memalign (16, sizeof (qh_t)); @@ -194,7 +194,7 @@ uhci_init (pcidev_t addr) ! UHCI_INST (controller)->qh_intr || ! UHCI_INST (controller)->qh_data || ! UHCI_INST (controller)->qh_last) - usb_fatal ("Not enough memory for USB controller queues.\n"); + fatal("Not enough memory for USB controller queues.\n"); UHCI_INST (controller)->qh_prei->headlinkptr.ptr = virt_to_phys (UHCI_INST (controller)->qh_intr); @@ -443,7 +443,7 @@ uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize) { int maxpsize = ep->maxpacketsize; if (maxpsize == 0) - usb_fatal ("MaxPacketSize == 0!!!"); + fatal("MaxPacketSize == 0!!!"); int numpackets = (size + maxpsize - 1 + finalize) / maxpsize; if (numpackets == 0) return 0; @@ -486,7 +486,7 @@ uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming qh_t *qh = memalign(16, sizeof(qh_t)); if (!data || !tds || !qh) - usb_fatal ("Not enough memory to create USB intr queue prerequisites.\n"); + fatal("Not enough memory to create USB intr queue prerequisites.\n"); qh->elementlinkptr.ptr = virt_to_phys(tds); qh->elementlinkptr.queue_head = 0; @@ -494,7 +494,7 @@ uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming intr_q *q = malloc(sizeof(intr_q)); if (!q) - usb_fatal ("Not enough memory to create USB intr queue.\n"); + fatal("Not enough memory to create USB intr queue.\n"); q->qh = qh; q->tds = tds; q->data = data; diff --git a/payloads/libpayload/drivers/usb/uhci_rh.c b/payloads/libpayload/drivers/usb/uhci_rh.c index bd3fb42..53b32f6 100644 --- a/payloads/libpayload/drivers/usb/uhci_rh.c +++ b/payloads/libpayload/drivers/usb/uhci_rh.c @@ -178,7 +178,7 @@ uhci_rh_init (usbdev_t *dev) uhci_rh_enable_port (dev, 2); dev->data = malloc (sizeof (rh_inst_t)); if (!dev->data) - usb_fatal ("Not enough memory for UHCI RH.\n"); + fatal("Not enough memory for UHCI RH.\n"); RH_INST (dev)->port[0] = -1; RH_INST (dev)->port[1] = -1; diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 6995cef..4f42332 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -459,9 +459,3 @@ usb_attach_device(hci_t *controller, int hubaddress, int port, int speed) return newdev; } -void -usb_fatal (const char *message) -{ - printf(message); - for (;;) ; -} diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c index 57f60cf..840b298 100644 --- a/payloads/libpayload/drivers/usb/usbhid.c +++ b/payloads/libpayload/drivers/usb/usbhid.c @@ -421,7 +421,7 @@ usb_hid_init (usbdev_t *dev) case hid_boot_proto_keyboard: dev->data = malloc (sizeof (usbhid_inst_t)); if (!dev->data) - usb_fatal("Not enough memory for USB HID device.\n"); + fatal("Not enough memory for USB HID device.\n"); debug (" configuring...\n"); usb_hid_set_protocol(dev, interface, hid_proto_boot); usb_hid_set_idle(dev, interface, KEYBOARD_REPEAT_MS); diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index fcf4f36..08042a2 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -135,7 +135,7 @@ usb_hub_init (usbdev_t *dev) dev->data = malloc (sizeof (usbhub_inst_t)); if (!dev->data) - usb_fatal("Not enough memory for USB hub.\n"); + fatal("Not enough memory for USB hub.\n"); HUB_INST (dev)->descriptor = (hub_descriptor_t *) get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, dev_recp), 0x29, 0, 0); @@ -143,7 +143,7 @@ usb_hub_init (usbdev_t *dev) HUB_INST (dev)->ports = malloc (sizeof (int) * (HUB_INST (dev)->num_ports + 1)); if (! HUB_INST (dev)->ports) - usb_fatal("Not enough memory for USB hub ports.\n"); + fatal("Not enough memory for USB hub ports.\n"); for (i = 1; i <= HUB_INST (dev)->num_ports; i++) HUB_INST (dev)->ports[i] = -1; diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 729bf91..f90acb1 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -398,7 +398,7 @@ usb_msc_init (usbdev_t *dev) dev->data = malloc (sizeof (usbmsc_inst_t)); if (!dev->data) - usb_fatal ("Not enough memory for USB MSC device.\n"); + fatal("Not enough memory for USB MSC device.\n"); MSC_INST (dev)->protocol = interface->bInterfaceSubClass; MSC_INST (dev)->bulk_in = 0; diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 0aca63d..a25cf40 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -57,11 +57,11 @@ xhci_init (pcidev_t addr) hci_t *controller = new_controller (); if (!controller) - usb_fatal("Could not create USB controller instance.\n"); + fatal("Could not create USB controller instance.\n"); controller->instance = malloc (sizeof (xhci_t)); if(!controller->instance) - usb_fatal("Not enough memory creating USB controller instance.\n"); + fatal("Not enough memory creating USB controller instance.\n"); controller->start = xhci_start; controller->stop = xhci_stop; @@ -82,7 +82,7 @@ xhci_init (pcidev_t addr) controller->reg_base = (u32)phys_to_virt(pci_read_config32 (controller->bus_address, 0x10) & ~0xf); //controller->reg_base = pci_read_config32 (controller->bus_address, 0x14) & ~0xf; if (pci_read_config32 (controller->bus_address, 0x14) > 0) { - usb_fatal("We don't do 64bit addressing.\n"); + fatal("We don't do 64bit addressing.\n"); } debug("regbase: %lx\n", controller->reg_base); @@ -94,7 +94,7 @@ xhci_init (pcidev_t addr) debug("caplength: %x\n", XHCI_INST (controller)->capreg->caplength); debug("hciversion: %x.%x\n", XHCI_INST (controller)->capreg->hciver_hi, XHCI_INST (controller)->capreg->hciver_lo); if ((XHCI_INST (controller)->capreg->hciversion < 0x96) || (XHCI_INST (controller)->capreg->hciversion > 0x100)) { - usb_fatal("Unsupported xHCI version\n"); + fatal("Unsupported xHCI version\n"); } debug("maxslots: %x\n", XHCI_INST (controller)->capreg->MaxSlots); debug("maxports: %x\n", XHCI_INST (controller)->capreg->MaxPorts); @@ -233,7 +233,7 @@ xhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize) { int maxpsize = ep->maxpacketsize; if (maxpsize == 0) - usb_fatal ("MaxPacketSize == 0!!!"); + fatal("MaxPacketSize == 0!!!"); return 1; } diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index 2817f04..1547ef6 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -112,7 +112,7 @@ xhci_rh_init (usbdev_t *dev) dev->data = malloc (sizeof (rh_inst_t)); if (!dev->data) - usb_fatal ("Not enough memory for XHCI RH.\n"); + fatal("Not enough memory for XHCI RH.\n"); RH_INST (dev)->numports = XHCI_INST (dev->controller)->capreg->MaxPorts; RH_INST (dev)->port = malloc(sizeof(int) * RH_INST (dev)->numports); diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index 2cd9c55..e38aa78 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -257,5 +257,4 @@ int usb_interface_check(u16 vendor, u16 device); # define debug(fmt, ...) while (0) { printf(fmt, ##__VA_ARGS__); } #endif -void usb_fatal(const char *message) __attribute__ ((noreturn)); #endif From gerrit at coreboot.org Fri Nov 4 21:28:15 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 4 Nov 2011 21:28:15 +0100 Subject: [coreboot] Patch set updated for coreboot: c080577 libpayload: Implement usb_exit References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/397 -gerrit commit c0805779c25bb3819eb9d244fdfd7d7ca894516f Author: Patrick Georgi Date: Fri Nov 4 12:06:06 2011 +0100 libpayload: Implement usb_exit So far it was empty and never published. It now exists and shuts down all controllers (esp. EHCI which resets the port routers). Change-Id: I81e355e8a05778d6397675417b085a094a6f48ee Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/usb/usb.c | 16 ++++++++++++++++ payloads/libpayload/drivers/usb/usbinit.c | 5 ----- payloads/libpayload/include/libpayload.h | 1 + 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 4f42332..995b4c2 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -68,6 +68,22 @@ detach_controller (hci_t *controller) } /** + * Shut down all controllers + */ +int +usb_exit (void) +{ + if (usb_hcs == 0) + return 0; + hci_t *controller = usb_hcs; + while (controller != 0) { + controller->shutdown(controller); + controller = controller->next; + } + return 0; +} + +/** * Polls all hubs on all USB controllers, to find out about device changes */ void diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 3964197..8499b82 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -139,8 +139,3 @@ usb_initialize (void) return 0; } -int -usb_exit (void) -{ - return 0; -} diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 80eaaa4..0e892c8 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -123,6 +123,7 @@ void rtc_read_clock(struct tm *tm); * @{ */ int usb_initialize(void); +int usb_exit (void); int usbhid_havechar(void); int usbhid_getchar(void); /** @} */ From gerrit at coreboot.org Fri Nov 4 21:28:15 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 4 Nov 2011 21:28:15 +0100 Subject: [coreboot] Patch set updated for coreboot: 1e8fe33 libpayload: Tell EHCI to re-enable USB1 controllers References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/396 -gerrit commit 1e8fe33efe3939a79b8f9236b260a02e3505abee Author: Patrick Georgi Date: Fri Nov 4 11:57:46 2011 +0100 libpayload: Tell EHCI to re-enable USB1 controllers EHCI can take over all ports (and then reroute devices to companion controllers if needs be). We do that, and then never reset it. Consequence: Systems with only USB1 HC drivers (OHCI/UHCI) never see any devices. Change-Id: If1d91e9142a6618289b0b3f6b56587ec857158e3 Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/usb/ehci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index b1ccb0b..71fbd7a 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -56,7 +56,7 @@ static void ehci_reset (hci_t *controller) static void ehci_shutdown (hci_t *controller) { - + EHCI_INST(controller)->operation->configflag = 0; } enum { EHCI_OUT=0, EHCI_IN=1, EHCI_SETUP=2 }; From gerrit at coreboot.org Fri Nov 4 22:11:10 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 4 Nov 2011 22:11:10 +0100 Subject: [coreboot] Patch merged into coreboot/master: 7abb7c9 libpayload: Drop usb_fatal() References: Message-ID: the following patch was just integrated into master: commit 7abb7c9925a2daab92538796aaf64e84e5a47114 Author: Patrick Georgi Date: Fri Nov 4 11:50:03 2011 +0100 libpayload: Drop usb_fatal() We have fatal(), which is just as good. Coccinelle script: @@ expression E; @@ -usb_fatal(E) +fatal(E) Change-Id: Iabecbcc7d068cc0f82687bf51d89c2626642cd86 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Nov 4 21:50:59 2011, giving +1 Reviewed-By: Stefan Reinauer at Fri Nov 4 21:45:26 2011, giving +2 See http://review.coreboot.org/395 for details. -gerrit From gerrit at coreboot.org Fri Nov 4 22:13:57 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 4 Nov 2011 22:13:57 +0100 Subject: [coreboot] Patch merged into coreboot/master: 1e8fe33 libpayload: Tell EHCI to re-enable USB1 controllers References: Message-ID: the following patch was just integrated into master: commit 1e8fe33efe3939a79b8f9236b260a02e3505abee Author: Patrick Georgi Date: Fri Nov 4 11:57:46 2011 +0100 libpayload: Tell EHCI to re-enable USB1 controllers EHCI can take over all ports (and then reroute devices to companion controllers if needs be). We do that, and then never reset it. Consequence: Systems with only USB1 HC drivers (OHCI/UHCI) never see any devices. Change-Id: If1d91e9142a6618289b0b3f6b56587ec857158e3 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Nov 4 22:12:18 2011, giving +1 Reviewed-By: Stefan Reinauer at Fri Nov 4 21:45:54 2011, giving +2 See http://review.coreboot.org/396 for details. -gerrit From gerrit at coreboot.org Fri Nov 4 22:15:06 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 4 Nov 2011 22:15:06 +0100 Subject: [coreboot] Patch merged into coreboot/master: c080577 libpayload: Implement usb_exit References: Message-ID: the following patch was just integrated into master: commit c0805779c25bb3819eb9d244fdfd7d7ca894516f Author: Patrick Georgi Date: Fri Nov 4 12:06:06 2011 +0100 libpayload: Implement usb_exit So far it was empty and never published. It now exists and shuts down all controllers (esp. EHCI which resets the port routers). Change-Id: I81e355e8a05778d6397675417b085a094a6f48ee Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Nov 4 22:01:20 2011, giving +1 Reviewed-By: Stefan Reinauer at Fri Nov 4 22:14:17 2011, giving +2 See http://review.coreboot.org/397 for details. -gerrit From gerrit at coreboot.org Fri Nov 4 22:16:50 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 4 Nov 2011 22:16:50 +0100 Subject: [coreboot] New patch to review for coreboot: fbbbb4a buildgcc: Explicitely state CC everywhere References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/399 -gerrit commit fbbbb4a66ab9b1c2c22f75b673a7aa233de6e5e0 Author: Patrick Georgi Date: Fri Nov 4 21:30:49 2011 +0100 buildgcc: Explicitely state CC everywhere This should fix issues with the iasl Makefile on Debian and prepares ccache support for buildgcc. Change-Id: Id9e6b2044b159b19bf013ec5c47b60ca1c2f2991 Signed-off-by: Patrick Georgi --- util/crossgcc/buildgcc | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 8918191..748b944 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -335,7 +335,7 @@ printf "Building GMP ${GMP_VERSION} ... " ( cd build-gmp rm -f .failed - ../${GMP_DIR}/configure --disable-shared --prefix=$TARGETDIR $OPTIONS \ + CC="$CC" ../${GMP_DIR}/configure --disable-shared --prefix=$TARGETDIR $OPTIONS \ || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -364,7 +364,7 @@ printf "Building MPFR ${MPFR_VERSION} ... " test `uname` = "Darwin" && CFLAGS="$CFLAGS -force_cpusubtype_ALL" cd build-mpfr rm -f .failed - ../${MPFR_DIR}/configure --disable-shared --prefix=$TARGETDIR \ + CC="$CC" ../${MPFR_DIR}/configure --disable-shared --prefix=$TARGETDIR \ --infodir=$TARGETDIR/info \ --with-gmp=$DESTDIR$TARGETDIR CFLAGS="$HOSTCFLAGS" || \ touch .failed @@ -391,7 +391,7 @@ printf "Building MPC ${MPC_VERSION} ... " #test `uname` = "Darwin" && CFLAGS="$CFLAGS -force_cpusubtype_ALL" cd build-mpc rm -f .failed - ../${MPC_DIR}/configure --disable-shared --prefix=$TARGETDIR \ + CC="$CC" ../${MPC_DIR}/configure --disable-shared --prefix=$TARGETDIR \ --infodir=$TARGETDIR/info --with-mpfr=$DESTDIR$TARGETDIR \ --with-gmp=$DESTDIR$TARGETDIR CFLAGS="$HOSTCFLAGS" || \ touch .failed @@ -413,7 +413,7 @@ printf "Building libelf ${LIBELF_VERSION} ... " cd build-libelf rm -f .failed echo "$HOSTCFLAGS" - CFLAGS="$HOSTCFLAGS" libelf_cv_elf_h_works=no \ + CC="$CC" CFLAGS="$HOSTCFLAGS" libelf_cv_elf_h_works=no \ ../${LIBELF_DIR}/configure --disable-shared --prefix=$TARGETDIR \ --infodir=$TARGETDIR/info CFLAGS="$HOSTCFLAGS" || touch .failed $MAKE $JOBS || touch .failed @@ -439,7 +439,7 @@ printf "Building binutils ${BINUTILS_VERSION} ... " # Now build binutils cd build-binutils rm -f .failed - ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR \ + CC="$CC" ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR \ --target=${TARGETARCH} --disable-werror --disable-nls \ $USE_GOLD CFLAGS="$HOSTCFLAGS" || touch .failed $MAKE $JOBS || touch .failed @@ -507,7 +507,7 @@ printf "Building Expat ${EXPAT_VERSION} ... " cd build-expat export PATH=$PATH:$DESTDIR$TARGETDIR/bin rm -f .failed - CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ + CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed $MAKE || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -529,7 +529,7 @@ printf "Building Python ${PYTHON_VERSION} ... " cd build-python export PATH=$PATH:$DESTDIR$TARGETDIR/bin rm -f .failed - CFLAGS="$HOSTCFLAGS" ../${PYTHON_DIR}/configure --prefix=$TARGETDIR \ + CC="$CC" CFLAGS="$HOSTCFLAGS" ../${PYTHON_DIR}/configure --prefix=$TARGETDIR \ --target=${TARGETARCH} || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -554,7 +554,7 @@ printf "Building GDB ${GDB_VERSION} ... " rm -f .failed LDFLAGS="-Wl,-rpath,\$\$ORIGIN/../lib/ -L$DESTDIR$TARGETDIR/lib \ -lpthread -ldl -lutil" \ - CFLAGS="$HOSTCFLAGS -I$DESTDIR$TARGETDIR/include" \ + CC="$CC" CFLAGS="$HOSTCFLAGS -I$DESTDIR$TARGETDIR/include" \ ../gdb-${GDB_VERSION}/configure --prefix=$TARGETDIR \ --target=${TARGETARCH} --disable-werror --disable-nls $MAKE $JOBS || touch .failed @@ -575,7 +575,7 @@ printf "Building IASL ${IASL_VERSION} ... " export PATH=$PATH:$DESTDIR$TARGETDIR/bin rm -f .failed CFLAGS="$HOSTCFLAGS" - $MAKE || touch .failed + $MAKE CC="$CC" || touch .failed rm -f $DESTDIR$TARGETDIR/bin/iasl || touch .failed cp iasl $DESTDIR$TARGETDIR/bin || touch .failed if [ ! -f .failed ]; then touch .success; fi From gerrit at coreboot.org Fri Nov 4 22:17:09 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 4 Nov 2011 22:17:09 +0100 Subject: [coreboot] New patch to review for coreboot: df9f463 buildgcc: Add option to use ccache References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/400 -gerrit commit df9f463a6b06ec69d65decb47c583c1e74cbadb9 Author: Patrick Georgi Date: Fri Nov 4 21:37:14 2011 +0100 buildgcc: Add option to use ccache This mimicks abuild: -y enables ccache. Change-Id: I3ac1f809729af816efbc64f5789ab430e1a6a6b2 Signed-off-by: Patrick Georgi --- util/crossgcc/buildgcc | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 748b944..217de27 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -126,6 +126,7 @@ myhelp() printf " [-h|--help] print this help and exit\n" printf " [-c|--clean] remove temporary files before build\n" printf " [-t|--savetemps] don't remove temporary files after build\n" + printf " [-y|--ccache] Use ccache when building cross compiler\n" printf " [-j|--jobs ] run jobs in parallel in make\n" printf " [-p|--platform ] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" @@ -167,11 +168,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="`getopt -V | sed -e '1!d' -e 's,^\(......\).*,\1,'`" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps,skip-gdb Vhcd:p:j:D:tG -- "$@"` + args=`getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps,skip-gdb,ccache Vhcd:p:j:D:tGy -- "$@"` eval set "$args" else # Detected non-GNU getopt - args=`getopt Vhcd:p:j:D:tG $*` + args=`getopt Vhcd:p:j:D:tGy $*` set -- $args fi @@ -192,6 +193,7 @@ while true ; do -j|--jobs) shift; JOBS="-j $1"; shift;; -G|--gdb) shift; SKIPGDB=0;; -S|--scripting) shift; SKIPPYTHON=0;; + -y|--ccache) shift; USECCACHE=1;; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;; @@ -323,6 +325,10 @@ if [ `uname` = "Darwin" ]; then fi fi +if [ "$USECCACHE" = 1 ]; then + CC="ccache $CC" +fi + mkdir -p build-gmp build-mpfr build-mpc build-libelf build-binutils \ build-gcc build-python build-expat if [ $SKIPGDB -eq 0 ]; then From gerrit at coreboot.org Fri Nov 4 23:12:40 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:40 +0100 Subject: [coreboot] New patch to review for coreboot: 57f3190 add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/401 -gerrit commit 57f31907876dc6ea941ca53547e22b655ac22179 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: Id61678f03e1f7d964f7180a062dd6a689852d4ac Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, From gerrit at coreboot.org Fri Nov 4 23:12:41 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:41 +0100 Subject: [coreboot] Patch set updated for coreboot: c5293fc support for different location of HT registers in old version of K8T800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/373 -gerrit commit c5293fc080bcb311e1277b2034051f4d22382745 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:14 2011 +0100 support for different location of HT registers in old version of K8T800 Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/early_car.c | 30 ++++++++++++++++++++++-------- 1 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index c554c49..da7b4db 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -35,6 +35,12 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#define K8X8XX_HT_CFG_BASE 0xc0 +#else +#define K8X8XX_HT_CFG_BASE 0x60 +#endif + /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init. * This will not work for K8T800_OLD, which has a slightly different @@ -43,10 +49,13 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; u8 k8t890_early_setup_ht(void) { - u8 awidth, afreq, cldtfreq, reg; + u8 awidth, afreq, cldtfreq; u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + u8 reg; + /* hack, enable NVRAM in chipset */ pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); @@ -58,6 +67,7 @@ u8 k8t890_early_setup_ht(void) reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); reg |= 0x1; pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); +#endif /* check if connected non coherent, initcomplete (find the SB on K8 side) */ ldtnr = 0; @@ -73,6 +83,10 @@ u8 k8t890_early_setup_ht(void) print_debug("K8M800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800 print_debug("K8T800 found at LDT "); +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + print_debug("K8T800_OLD found at LDT "); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO print_debug("K8T800 Pro found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8M890 @@ -87,19 +101,19 @@ u8 k8t890_early_setup_ht(void) /* get the maximum widths for both sides */ cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7; - vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7; - vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7; + vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) & 0x7; + vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7; width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); print_debug(" Agreed on width: "); print_debug_hex8(width); - awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7); /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */ width = (width == 0x01) ? 0x11 : 0x00; - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7, width); /* Get programmed HT freq at base 0x89 */ cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; @@ -107,15 +121,15 @@ u8 k8t890_early_setup_ht(void) print_debug_hex8(cldtfreq); print_debug(" VIA HT caps: "); - vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e); + vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe); print_debug_hex16(vldtcaps); if (!(vldtcaps & (1 << cldtfreq ))) { die("Chipset does not support desired HT frequency\n"); } - afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq); + afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq); print_debug("\n"); /* no reset needed */ From gerrit at coreboot.org Fri Nov 4 23:12:41 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:41 +0100 Subject: [coreboot] Patch set updated for coreboot: 8509f26 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/374 -gerrit commit 8509f2694fd0b03a15eadcbfe10e3c07e0d63cb3 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:41 2011 +0100 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/romstrap.inc | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc index 5b24948..a3814b0 100644 --- a/src/southbridge/via/k8t890/romstrap.inc +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -33,7 +33,7 @@ __romstrap_start: * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ -#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD tblpointer: .long 0x50220000, 0X619707C2 diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index e599517..b1e1afe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_K8T800 + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */ From gerrit at coreboot.org Fri Nov 4 23:12:42 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:42 +0100 Subject: [coreboot] Patch set updated for coreboot: 16f7f24 in vt8237r_enable(), write function enables only to ISA bridge config space References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/368 -gerrit commit 16f7f242b6f4c7d3bdd8d4f41a1f2366a861d06f Author: Florian Zumbiehl Date: Tue Nov 1 20:16:16 2011 +0100 in vt8237r_enable(), write function enables only to ISA bridge config space vt8237r_enable() so far wrote the function enable values to the same offset in the config space of every one of the vt8237's functions, even though the register is located in the ISA bridge only. Change-Id: I639586dc238132f5b8d2f320b794948718281b9c Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/vt8237r.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 5ba3815..586df66 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -66,11 +66,21 @@ void dump_south(device_t dev) static void vt8237r_enable(struct device *dev) { + u16 vid, did; struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; - pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); - pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + if (dev->path.type == DEVICE_PATH_PCI) { + vid = pci_read_config16(dev, PCI_VENDOR_ID); + did = pci_read_config16(dev, PCI_DEVICE_ID); + if (vid == PCI_VENDOR_ID_VIA && + (did == PCI_DEVICE_ID_VIA_VT8237R_LPC || + did == PCI_DEVICE_ID_VIA_VT8237A_LPC || + did == PCI_DEVICE_ID_VIA_VT8237S_LPC)) { + pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); + pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + } + } /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ } From gerrit at coreboot.org Fri Nov 4 23:12:42 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:42 +0100 Subject: [coreboot] Patch set updated for coreboot: c593fc8 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/370 -gerrit commit c593fc823a5a2bc3de327fea5f1d44cfec8aec15 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:12 2011 +0100 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit_f.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 319293b..dc3addb 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i 18, /* *Supported CAS Latencies */ 9, /* *Cycle time at highest CAS Latency CL=X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ - 26, /* *Cycle time at CAS Latency (CLX - 2) */ + 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; u8 common_cl; From gerrit at coreboot.org Fri Nov 4 23:12:44 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:44 +0100 Subject: [coreboot] Patch set updated for coreboot: b4270b5 make w83697hf_set_clksel_48() non-static and add a prototype References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit b4270b5a2814290f48386e6e1639fac5f84a469b Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 make w83697hf_set_clksel_48() non-static and add a prototype make w83697hf_set_clksel_48() non-static and add a prototype so as to get rid of warnings about it being unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/early_serial.c | 2 +- src/superio/winbond/w83697hf/w83697hf.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..2825eeb 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(device_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 0eeb37c..6488dd3 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -32,4 +32,8 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ +#ifndef __ROMCC__ +void w83697hf_set_clksel_48(device_t); +#endif + #endif From gerrit at coreboot.org Fri Nov 4 23:12:45 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:45 +0100 Subject: [coreboot] Patch set updated for coreboot: e8b777e add support for setting the vt8237 to uncond. power on after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit e8b777ea30ccfdc2e9d3028ac1e74a4dd8796aa4 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..0e757fe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Fri Nov 4 23:12:46 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:46 +0100 Subject: [coreboot] Patch set updated for coreboot: f3b36f4 support for setting the Memory DQ Drive Strength register in amdk8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit f3b36f4d36c5be1c7f7f7e29ba5ceaa1df055a6c Author: Florian Zumbiehl Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit make sure DRAM drive strength is not reduced Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 12 ++++++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 02c764d..e09075f 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2201,6 +2201,18 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + + if (!is_cpu_pre_e0()) { + uint32_t dch; + + // see also erratum 114, essentially: never ever + // set to anything but 0 + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= DCH_DQ_DRV_STRENGTH_0 << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; From gerrit at coreboot.org Fri Nov 4 23:12:48 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:48 +0100 Subject: [coreboot] Patch set updated for coreboot: c1ee4a7 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit c1ee4a7aab4d3cf958551e89bdefdddda07231f0 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 349 +++++++++++++++++------------------ 1 files changed, 166 insertions(+), 183 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..02c764d 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1230,8 +1230,8 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 17, /* *Logical Banks */ 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ - 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 23, /* *Cycle time at CAS Latency (CLX - 0.5) */ + 25, /* *Cycle time at CAS Latency (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,11 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) +{ #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1441,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos = 0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1475,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1484,190 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table + * are to be understood: + */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; + +#else /* CONFIG_CPU_AMD_SOCKET_* */ + +// well, there are socket 940 boards supported which obviously fail to +// compile with this +// #error load dependent memory clock limiting is not implemented for this socket -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ + /* see BKDG 4.1.3--if you just want to test a setup that doesn't + * require limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what + * would be intuitive. 200 MHz has the lowest constant, 100 MHz the + * highest. Thus, all comparisons and traversal directions having to + * do with frequencies are/have to be the opposite of what would be + * intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + // the CLs supported by the controller: + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); + memset(cl_at_freq, 0x00, + (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> + NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle + * shorter, select that (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#if CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1689,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; From gerrit at coreboot.org Fri Nov 4 23:12:48 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:48 +0100 Subject: [coreboot] Patch set updated for coreboot: 4dbddae fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/376 -gerrit commit 4dbddae0403b2cbe227820ee2dedf498f5f149e3 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 3583dc3..237272c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1399,7 +1399,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) #define DDR400 (NBCAP_MEMCLK_200MHZ + 1) #define DDR_2T 0x80 -#define DDR_MASK 0x3 +#define DDR_MASK 0x7 #define DDR200_2T (DDR_2T | DDR200) #define DDR333_2T (DDR_2T | DDR333) From gerrit at coreboot.org Fri Nov 4 23:12:49 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:49 +0100 Subject: [coreboot] Patch set updated for coreboot: a3f5358 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit a3f5358e99e8b04932137a79ba1448e0cca16259 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include #include +#ifndef __PRE_RAM__ +#include +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Fri Nov 4 23:12:50 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:50 +0100 Subject: [coreboot] Patch set updated for coreboot: 28be6c6 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/378 -gerrit commit 28be6c68a96a99a6e85cc3fc878a2ce748ea7637 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/ctrl.c | 49 ++++++---------------------------- src/southbridge/via/k8t890/dram.c | 18 ++++++------ src/southbridge/via/k8t890/k8x8xx.h | 25 ++++++++++++++++++ 3 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 42676b1..7363510 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -31,31 +31,8 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - if(!devfun3) - die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); + u8 regm3; + struct k8x8xx_vt8237_mirrored_regs mregs; pci_write_config8(dev, 0x70, 0xc2); @@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); + k8x8xx_vt8237_mirrored_regs_fill(&mregs); - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); + pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */ + pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */ + pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */ - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! @@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) regm3 = 0x0; /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F)); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e..294e387 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index a0fb57a..425aaeb 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -21,6 +21,31 @@ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#include +#include #include "k8t890.h" +struct k8x8xx_vt8237_mirrored_regs { + u16 low_top_address; + u8 rom_shadow_ctrl_pg_c, + rom_shadow_ctrl_pg_d, + rom_shadow_ctrl_pg_e_memhole_smi_decoding, + rom_shadow_ctrl_pg_f_memhole, + smm_apic_decoding, + shadow_mem_ctrl; +}; + +static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */ From gerrit at coreboot.org Fri Nov 4 23:12:50 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:50 +0100 Subject: [coreboot] Patch set updated for coreboot: a5e9824 make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit a5e982479fa85fb6508659c28f29c61102e59195 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index d4f7820..7d7326c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Fri Nov 4 23:12:51 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:51 +0100 Subject: [coreboot] Patch set updated for coreboot: 60343fb make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 60343fb2dc6efad562f99664a6b5a69d6ff2ee70 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 0e757fe..d4f7820 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -506,7 +517,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */ From gerrit at coreboot.org Fri Nov 4 23:12:52 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:52 +0100 Subject: [coreboot] Patch set updated for coreboot: 73148db implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit 73148db4fe36c5546519d32dd63cc05dbc33fdd6 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..2bdcf9d 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | + (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | + (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | + (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | + (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, + (pci_read_config8(dev, 0x5c) & ~0x70) | + (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Fri Nov 4 23:12:53 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:53 +0100 Subject: [coreboot] Patch set updated for coreboot: 3afdb6e implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit 3afdb6e178425a312c3d1cc19fa27338be341d04 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Fri Nov 4 23:12:55 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:55 +0100 Subject: [coreboot] Patch set updated for coreboot: 7a15606 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 7a1560696dcb93a6582091ac6740cc7fb7058eac Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 21 ++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 116 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..6b32ea3 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,25 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +43,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +73,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Fri Nov 4 23:12:57 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:57 +0100 Subject: [coreboot] Patch set updated for coreboot: 4a0e335 copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit 4a0e335eec61cbb53a20c173778b0176b18ce0ff Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Fri Nov 4 23:12:59 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Fri, 4 Nov 2011 23:12:59 +0100 Subject: [coreboot] Patch set updated for coreboot: b2b3215 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit b2b3215c6b5a37be1ed5b4501f7e2bd619ea0adb Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From gerrit at coreboot.org Sat Nov 5 01:11:15 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 01:11:15 +0100 Subject: [coreboot] New patch to review for filo: 2d71835 Shut down USB before starting Linux References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/402 -gerrit commit 2d718354199266b4f919b38e68386f0c92dc8d01 Author: Patrick Georgi Date: Sat Nov 5 01:09:47 2011 +0100 Shut down USB before starting Linux Otherwise, if FILO knows EHCI and Linux only knows USB1 controllers, Linux won't find any devices as they're routed to EHCI. Change-Id: I06d046056b9807d660127c28c364abf3852b32a5 Signed-off-by: Patrick Georgi --- i386/linux_load.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/i386/linux_load.c b/i386/linux_load.c index 07855bd..aa2f27e 100644 --- a/i386/linux_load.c +++ b/i386/linux_load.c @@ -792,6 +792,9 @@ int linux_load(const char *file, const char *cmdline) } file_close(); +#if defined(CONFIG_USB) + usb_exit(); +#endif hardware_setup(); From gerrit at coreboot.org Sat Nov 5 01:20:06 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 01:20:06 +0100 Subject: [coreboot] New patch to review for filo: c880651 Allow using binary libpayload References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/403 -gerrit commit c8806514e6001bf0acadbd3427fb5b1df861fec2 Author: Patrick Georgi Date: Sat Nov 5 01:18:53 2011 +0100 Allow using binary libpayload We already test for LIBPAYLOAD_PREFIX in the Makefile's build codepath. Also test for it in the configuration codepath, so a prebuilt libpayload can be used for FILO. Change-Id: I8f2aa102f1e41f698bfd4061c5e7e7b8082c885e Signed-off-by: Patrick Georgi --- util/kconfig/Makefile | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile index 70c3870..e95dac0 100644 --- a/util/kconfig/Makefile +++ b/util/kconfig/Makefile @@ -18,10 +18,16 @@ LIB_CONFIG := $(src)/lib.config HAVE_FILO_CONFIG := $(wildcard $(FILO_CONFIG)) HAVE_LIB_CONFIG := $(wildcard $(LIB_CONFIG)) +LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_PREFIX)/lib/libpayload.a) +ifeq ($(LIBPAYLOAD),) libpayload_config_%: echo "Libpayload config for FILO." $(MAKE) -C $(LIBCONFIG_PATH) KCONFIG_CONFIG=$(LIB_CONFIG) $(patsubst libpayload_config_%,%,$@) echo "Libpayload config done." +else +libpayload_config_%: + echo "Using binary libpayload, nothing to configure" +endif xconfig: prepare $(objk)/qconf libpayload_config_xconfig $(objk)/qconf $(Kconfig) From gerrit at coreboot.org Sat Nov 5 12:35:00 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 12:35:00 +0100 Subject: [coreboot] New patch to review for coreboot: bfbba64 Inline Makefile.bootblock.inc References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/404 -gerrit commit bfbba6462f66aaf91af3c59fdb89ee91676351b4 Author: Patrick Georgi Date: Tue Nov 1 18:55:59 2011 +0100 Inline Makefile.bootblock.inc This was split out when we had separate rules for big bootblock. Change-Id: Id0a117f6996fb6bdef7bf97e7d80c36f5dec0ad7 Signed-off-by: Patrick Georgi --- src/arch/x86/Makefile.bootblock.inc | 110 ----------------------------------- src/arch/x86/Makefile.inc | 110 ++++++++++++++++++++++++++++++++++- 2 files changed, 109 insertions(+), 111 deletions(-) diff --git a/src/arch/x86/Makefile.bootblock.inc b/src/arch/x86/Makefile.bootblock.inc deleted file mode 100644 index 9787032..0000000 --- a/src/arch/x86/Makefile.bootblock.inc +++ /dev/null @@ -1,110 +0,0 @@ -####################################################################### -# Build the final rom image - -$(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) - @printf " CBFS $(subst $(obj)/,,$(@))\n" - rm -f $@ - cp $(obj)/coreboot.pre1 $@ - $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) -#FIXME: location.txt might require an offset of header size - -####################################################################### -# Build the bootblock - -$(obj)/coreboot.bootblock: $(obj)/bootblock.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - $(OBJCOPY) -O binary $< $@ - -bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb -bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds -bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds -bootblock_lds += $(src)/arch/x86/lib/id.lds -bootblock_lds += $(chipset_bootblock_lds) - -bootblock_inc = $(src)/arch/x86/init/prologue.inc -bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc -bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc -bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc -bootblock_inc += $(src)/arch/x86/lib/id.inc -bootblock_inc += $(chipset_bootblock_inc) - -ifeq ($(CONFIG_SSE),y) -bootblock_inc += $(src)/cpu/x86/sse_enable.inc -endif -bootblock_inc += $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc -bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S - -bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -ifeq ($(CONFIG_SSE),y) -bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -endif - -$(obj)/bootblock/ldscript.ld: $$(bootblock_lds) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/bootblock - printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ - -$(obj)/bootblock/bootblock.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/bootblock - printf '$(foreach crt0,config.h $(bootblock_inc),#include "$(crt0)"\n)' > $@ - -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm - -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ - -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) - @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ - $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d - $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ - -$(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/bootblock/ldscript.ld $< - $(NM) -n $(obj)/bootblock.elf | sort > $(obj)/bootblock.map - $(OBJCOPY) --only-keep-debug $@ $(obj)/bootblock.debug - $(OBJCOPY) --strip-debug $@ - $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@ - -####################################################################### -# Build the romstage -$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" - printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) - $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin - printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt - cat $(obj)/location.txt >> $(obj)/location.ld - printf ';\n' >> $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) - $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map - $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug - $(OBJCOPY) --strip-debug $(obj)/romstage.elf - $(OBJCOPY) --add-gnu-debuglink=$(obj)/romstage.debug $(obj)/romstage.elf - $(OBJCOPY) -O binary $(obj)/romstage.elf $@ - -$(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/romstage - printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' > $@ - -$(obj)/romstage/crt0.S: $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/romstage - printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ - -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm - -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@ - diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 50238c5..7bba44e 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -271,7 +271,115 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -include $(src)/arch/x86/Makefile.bootblock.inc +####################################################################### +# Build the final rom image + +$(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) + @printf " CBFS $(subst $(obj)/,,$(@))\n" + rm -f $@ + cp $(obj)/coreboot.pre1 $@ + $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ + $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) +#FIXME: location.txt might require an offset of header size + +####################################################################### +# Build the bootblock + +$(obj)/coreboot.bootblock: $(obj)/bootblock.elf + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -O binary $< $@ + +bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb +bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds +bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds +bootblock_lds += $(src)/arch/x86/lib/id.lds +bootblock_lds += $(chipset_bootblock_lds) + +bootblock_inc = $(src)/arch/x86/init/prologue.inc +bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc +bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc +bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc +bootblock_inc += $(src)/arch/x86/lib/id.inc +bootblock_inc += $(chipset_bootblock_inc) + +ifeq ($(CONFIG_SSE),y) +bootblock_inc += $(src)/cpu/x86/sse_enable.inc +endif +bootblock_inc += $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc +bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S + +bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ +ifeq ($(CONFIG_SSE),y) +bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ +endif + +$(obj)/bootblock/ldscript.ld: $$(bootblock_lds) $(obj)/ldoptions + @printf " GEN $(subst $(obj)/,,$(@))\n" + mkdir -p $(obj)/bootblock + printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ + +$(obj)/bootblock/bootblock.S: $$(bootblock_inc) + @printf " GEN $(subst $(obj)/,,$(@))\n" + mkdir -p $(obj)/bootblock + printf '$(foreach crt0,config.h $(bootblock_inc),#include "$(crt0)"\n)' > $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) + @printf " ROMCC $(subst $(obj)/,,$(@))\n" + $(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ + $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d + $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ + +$(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/bootblock/ldscript.ld $< + $(NM) -n $(obj)/bootblock.elf | sort > $(obj)/bootblock.map + $(OBJCOPY) --only-keep-debug $@ $(obj)/bootblock.debug + $(OBJCOPY) --strip-debug $@ + $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@ + +####################################################################### +# Build the romstage +$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) + $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin + printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt + cat $(obj)/location.txt >> $(obj)/location.ld + printf ';\n' >> $(obj)/location.ld + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) + $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map + $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug + $(OBJCOPY) --strip-debug $(obj)/romstage.elf + $(OBJCOPY) --add-gnu-debuglink=$(obj)/romstage.debug $(obj)/romstage.elf + $(OBJCOPY) -O binary $(obj)/romstage.elf $@ + +$(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions + @printf " GEN $(subst $(obj)/,,$(@))\n" + mkdir -p $(obj)/romstage + printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' > $@ + +$(obj)/romstage/crt0.S: $$(crt0s) + @printf " GEN $(subst $(obj)/,,$(@))\n" + mkdir -p $(obj)/romstage + printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm + +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@ seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ From gerrit at coreboot.org Sat Nov 5 14:48:10 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 14:48:10 +0100 Subject: [coreboot] New patch to review for coreboot: 4e95b5a abuild: Avoid race condition when running abuild parallely References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/405 -gerrit commit 4e95b5a8d0a0c82705ff8cadf1f316278dc02dd1 Author: Patrick Georgi Date: Sat Nov 5 12:47:13 2011 +0100 abuild: Avoid race condition when running abuild parallely By moving the just-created file away, parallel runs of abuild might break. Change-Id: I03368f00e9b11dad4c80d41279970e28debc7ed5 Signed-off-by: Patrick Georgi --- util/abuild/abuild | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 0ed295f..ba144aa 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -289,7 +289,7 @@ function compile_target eval $MAKE $silent -j $cpus DOTCONFIG=${build_dir}/config.build obj=${build_dir} objutil=$TARGET/sharedutils \ &> ${build_dir}/make.log ret=$? - mv .xcompile ${build_dir}/xcompile.build + cp .xcompile ${build_dir}/xcompile.build cd $TARGET/${VENDOR}_${MAINBOARD} etime=`perl -e 'print time();' 2>/dev/null || date +%s` From gerrit at coreboot.org Sat Nov 5 14:48:10 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 14:48:10 +0100 Subject: [coreboot] New patch to review for coreboot: ee5a22c abuild: Refactor parallelization support References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/406 -gerrit commit ee5a22cce013e20eda3fb39152584382327c1065 Author: Patrick Georgi Date: Sat Nov 5 12:55:18 2011 +0100 abuild: Refactor parallelization support Use MAKEFLAGS to propagate the parallelization configuration to the build Change-Id: If90ed446edd8e6dc679d284ee9db7a24269edd36 Signed-off-by: Patrick Georgi --- util/abuild/abuild | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index ba144aa..4ab0230 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -222,7 +222,7 @@ function create_config fi fi - #yes "" | $MAKE oldconfig -j $cpus obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log + #yes "" | $MAKE oldconfig obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log yes "" | $MAKE oldconfig DOTCONFIG=${build_dir}/config.build obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log ret=$? if [ $ret -eq 0 ]; then @@ -286,7 +286,7 @@ function compile_target CURR=$( pwd ) #stime=`perl -e 'print time();' 2>/dev/null || date +%s` build_dir=$TARGET/${VENDOR}_${MAINBOARD} - eval $MAKE $silent -j $cpus DOTCONFIG=${build_dir}/config.build obj=${build_dir} objutil=$TARGET/sharedutils \ + eval $MAKE $silent DOTCONFIG=${build_dir}/config.build obj=${build_dir} objutil=$TARGET/sharedutils \ &> ${build_dir}/make.log ret=$? cp .xcompile ${build_dir}/xcompile.build @@ -624,6 +624,10 @@ while true ; do esac done +if [ "$cpus" != "1" ]; then + export MAKEFLAGS="-j $cpus" +fi + # /path/to/freebios2/ test -z "$1" || ROOT=$1 From gerrit at coreboot.org Sat Nov 5 14:48:11 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 14:48:11 +0100 Subject: [coreboot] New patch to review for coreboot: 6e67db0 abuild: Write XML/JUnit files per board References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/407 -gerrit commit 6e67db0f0212f219c0eca3cae45ceff0a1abd79a Author: Patrick Georgi Date: Sat Nov 5 13:21:14 2011 +0100 abuild: Write XML/JUnit files per board Write them per-board and merge them after everything is done. This prepares for build parallelization. Change-Id: Ia4e7ce03473bcf8861fb9ae06e9c1270292401ac Signed-off-by: Patrick Georgi --- util/abuild/abuild | 12 +++++++++++- 1 files changed, 11 insertions(+), 1 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 4ab0230..8b81ea1 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -17,9 +17,12 @@ ABUILD_DATE="December 10th, 2010" ABUILD_VERSION="0.9.1" +TOP=$PWD + # Where shall we place all the build trees? TARGET=coreboot-builds -XMLFILE=$( pwd )/abuild.xml +XMLFILE=$TOP/abuild.xml +REAL_XMLFILE=$XMLFILE # path to payload. Should be more generic PAYLOAD=/dev/null @@ -363,6 +366,7 @@ function build_target HOSTCC='gcc' printf "Building $VENDOR/$MAINBOARD; " + XMLFILE=$TOP/$TARGET/${VENDOR}_${MAINBOARD}/abuild.xml xml "" xml "" @@ -652,6 +656,8 @@ if [ "$target" != "" ]; then fi build_target $VENDOR $MAINBOARD $CONFIG test_target $VENDOR $MAINBOARD + cat $TARGET/${VENDOR}_${MAINBOARD}/abuild.xml >> $REAL_XMLFILE + XMLFILE=$REAL_XMLFILE else # build all boards per default for VENDOR in $( vendors ); do @@ -661,6 +667,10 @@ else remove_target $VENDOR $MAINBOARD done done + for xmlfile in $TARGET/*_*/abuild.xml; do + cat $xmlfile >> $REAL_XMLFILE + done + XMLFILE=$REAL_XMLFILE fi xml '' junit '' From gerrit at coreboot.org Sat Nov 5 14:48:11 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 14:48:11 +0100 Subject: [coreboot] New patch to review for coreboot: 8258504 kconfig: Use more collision resistant temporary filenames References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/408 -gerrit commit 82585042cc979c553aee4d9e88665b4b401d342f Author: Patrick Georgi Date: Sat Nov 5 14:39:56 2011 +0100 kconfig: Use more collision resistant temporary filenames kconfig creates reasonably safe filenames for its temporary files except for two of them. Change-Id: I6861f55ae2a5311e3fb7919333ce9af1e39ce78b Signed-off-by: Patrick Georgi --- util/kconfig/confdata.c | 11 +++++++---- 1 files changed, 7 insertions(+), 4 deletions(-) diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 946b8a9..79e0b35 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -682,6 +682,7 @@ int conf_write_autoconf(void) FILE *out, *out_h; time_t now; int i, l; + char tmpname[128], tmpname_h[128]; sym_clear_all_valid(); @@ -692,11 +693,13 @@ int conf_write_autoconf(void) return 1; #endif - out = fopen(".tmpconfig", "w"); + sprintf(tmpname, ".tmpconfig.%d", (int)getpid()); + out = fopen(tmpname, "w"); if (!out) return 1; - out_h = fopen(".tmpconfig.h", "w"); + sprintf(tmpname_h, ".tmpconfig.h.%d", (int)getpid()); + out_h = fopen(tmpname_h, "w"); if (!out_h) { fclose(out); return 1; @@ -791,7 +794,7 @@ int conf_write_autoconf(void) if (!name) name = "include/linux/autoconf.h"; UNLINK_IF_NECESSARY(name); - if (rename(".tmpconfig.h", name)) + if (rename(tmpname_h, name)) return 1; name = getenv("KCONFIG_AUTOCONFIG"); if (!name) @@ -801,7 +804,7 @@ int conf_write_autoconf(void) * and this marks the successful completion of the previous steps. */ UNLINK_IF_NECESSARY(name); - if (rename(".tmpconfig", name)) + if (rename(tmpname, name)) return 1; return 0; From gerrit at coreboot.org Sat Nov 5 14:48:12 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 14:48:12 +0100 Subject: [coreboot] New patch to review for coreboot: 991d040 abuild: Build boards in parallel if possible References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/409 -gerrit commit 991d0403fc05ab37d61078d98a6edd9245137c54 Author: Patrick Georgi Date: Sat Nov 5 14:44:41 2011 +0100 abuild: Build boards in parallel if possible Determine if xargs -P works. If yes, use that to build multiple boards in parallel, instead of relying on make -j X, when doing a full abuild run (instead of single boards). make -j X isn't able to make use of several cores at various serialization points in our build process, so this change results in a >25% speed up for a full abuild run in my tests. Change-Id: Id484a4211c84a3a24115278e0fbe92345f346596 Signed-off-by: Patrick Georgi --- util/abuild/abuild | 49 ++++++++++++++++++++++++++++++++++++++++--------- 1 files changed, 40 insertions(+), 9 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 8b81ea1..5228cdb 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -583,6 +583,9 @@ test -f util/sconfig/sconfig.l && ROOT=$( pwd ) test -f ../util/sconfig/sconfig.l && ROOT=$( cd ..; pwd ) test "$ROOT" = "" && ROOT=$( cd ../..; pwd ) +# command line for xargs parallelization. Thus overwrite -c X +cmdline="$* -c 1" + # parse parameters.. try to find out whether we're running GNU getopt getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then @@ -628,8 +631,43 @@ while true ; do esac done +USE_XARGS=0 if [ "$cpus" != "1" ]; then - export MAKEFLAGS="-j $cpus" + if [ "$target" = "" ]; then + # Test if xargs supports the non-standard -P flag + echo | xargs -P 0$cpus -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1 + fi +fi + +if [ "$USE_XARGS" = "0" ]; then +export MAKEFLAGS="-j $cpus" +build_all_targets() +{ + for VENDOR in $( vendors ); do + for MAINBOARD in $( mainboards $VENDOR ); do + build_target $VENDOR $MAINBOARD + test_target $VENDOR $MAINBOARD + remove_target $VENDOR $MAINBOARD + done + done +} +else +# Limit to 32 parallel builds for now. +# Thrashing all caches because we run +# 160 abuilds in parallel is no fun. +if [ "$cpus" = "" ]; then + cpus=32 +fi +build_all_targets() +{ + # seed shared utils + MAKEFLAGS="-j $cpus" $0 $cmdline -t emulation/qemu-x86 + for VENDOR in $( vendors ); do + for MAINBOARD in $( mainboards $VENDOR ); do + echo $VENDOR/$MAINBOARD + done + done | xargs -P 0$cpus -n 1 $0 $cmdline -t +} fi # /path/to/freebios2/ @@ -659,14 +697,7 @@ if [ "$target" != "" ]; then cat $TARGET/${VENDOR}_${MAINBOARD}/abuild.xml >> $REAL_XMLFILE XMLFILE=$REAL_XMLFILE else - # build all boards per default - for VENDOR in $( vendors ); do - for MAINBOARD in $( mainboards $VENDOR ); do - build_target $VENDOR $MAINBOARD - test_target $VENDOR $MAINBOARD - remove_target $VENDOR $MAINBOARD - done - done + build_all_targets for xmlfile in $TARGET/*_*/abuild.xml; do cat $xmlfile >> $REAL_XMLFILE done From gerrit at coreboot.org Sat Nov 5 14:56:54 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 14:56:54 +0100 Subject: [coreboot] Patch set updated for filo: 4162c3b Allow using binary libpayload References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/403 -gerrit commit 4162c3bbf3d0be1cf2cf71ab408d3b65de75a0bc Author: Patrick Georgi Date: Sat Nov 5 01:18:53 2011 +0100 Allow using binary libpayload We already test for LIBPAYLOAD_PREFIX in the Makefile's build codepath. Also test for it in the configuration codepath, so a prebuilt libpayload can be used for FILO. Change-Id: I8f2aa102f1e41f698bfd4061c5e7e7b8082c885e Signed-off-by: Patrick Georgi --- util/kconfig/Makefile | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile index 70c3870..1d519b2 100644 --- a/util/kconfig/Makefile +++ b/util/kconfig/Makefile @@ -18,10 +18,16 @@ LIB_CONFIG := $(src)/lib.config HAVE_FILO_CONFIG := $(wildcard $(FILO_CONFIG)) HAVE_LIB_CONFIG := $(wildcard $(LIB_CONFIG)) +LIBPAYLOAD ?= $(wildcard $(LIBPAYLOAD_PREFIX)/lib/libpayload.a) +ifeq ($(LIBPAYLOAD),) libpayload_config_%: echo "Libpayload config for FILO." $(MAKE) -C $(LIBCONFIG_PATH) KCONFIG_CONFIG=$(LIB_CONFIG) $(patsubst libpayload_config_%,%,$@) echo "Libpayload config done." +else +libpayload_config_%: + echo "Using binary libpayload, nothing to configure" +endif xconfig: prepare $(objk)/qconf libpayload_config_xconfig $(objk)/qconf $(Kconfig) From gerrit at coreboot.org Sat Nov 5 16:54:15 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 16:54:15 +0100 Subject: [coreboot] Patch set updated for coreboot: ff379c8 abuild: Build boards in parallel if possible References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/409 -gerrit commit ff379c8f24cebaf789311838e3c9fcdfd7ef198d Author: Patrick Georgi Date: Sat Nov 5 14:44:41 2011 +0100 abuild: Build boards in parallel if possible Determine if xargs -P works. If yes, use that to build multiple boards in parallel, instead of relying on make -j X, when doing a full abuild run (instead of single boards). make -j X isn't able to make use of several cores at various serialization points in our build process, so this change results in a >25% speed up for a full abuild run in my tests. Change-Id: Id484a4211c84a3a24115278e0fbe92345f346596 Signed-off-by: Patrick Georgi --- util/abuild/abuild | 68 +++++++++++++++++++++++++++++++++++++++------------ 1 files changed, 52 insertions(+), 16 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 8b81ea1..6acd793 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -583,6 +583,9 @@ test -f util/sconfig/sconfig.l && ROOT=$( pwd ) test -f ../util/sconfig/sconfig.l && ROOT=$( cd ..; pwd ) test "$ROOT" = "" && ROOT=$( cd ../..; pwd ) +# command line for xargs parallelization. Thus overwrite -c X +cmdline="$* -c 1" + # parse parameters.. try to find out whether we're running GNU getopt getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then @@ -628,8 +631,43 @@ while true ; do esac done +USE_XARGS=0 if [ "$cpus" != "1" ]; then - export MAKEFLAGS="-j $cpus" + if [ "$target" = "" ]; then + # Test if xargs supports the non-standard -P flag + echo | xargs -P 0$cpus -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1 + fi +fi + +if [ "$USE_XARGS" = "0" ]; then +export MAKEFLAGS="-j $cpus" +build_all_targets() +{ + for VENDOR in $( vendors ); do + for MAINBOARD in $( mainboards $VENDOR ); do + build_target $VENDOR $MAINBOARD + test_target $VENDOR $MAINBOARD + remove_target $VENDOR $MAINBOARD + done + done +} +else +# Limit to 32 parallel builds for now. +# Thrashing all caches because we run +# 160 abuilds in parallel is no fun. +if [ "$cpus" = "" ]; then + cpus=32 +fi +build_all_targets() +{ + # seed shared utils + MAKEFLAGS="-j $cpus" $0 $cmdline -t emulation/qemu-x86 + for VENDOR in $( vendors ); do + for MAINBOARD in $( mainboards $VENDOR ); do + echo $VENDOR/$MAINBOARD + done + done | xargs -P 0$cpus -n 1 $0 $cmdline -t +} fi # /path/to/freebios2/ @@ -650,23 +688,21 @@ if [ "$target" != "" ]; then CONFIG=`printf $target|cut -f3 -d/` if [ ! -r $ROOT/src/mainboard/$target ]; then printf "No such target: $target\n" - xml '' - junit '' - exit 1 + failed=1 + else + build_target $VENDOR $MAINBOARD $CONFIG + test_target $VENDOR $MAINBOARD + cat $TARGET/${VENDOR}_${MAINBOARD}/abuild.xml >> $REAL_XMLFILE + XMLFILE=$REAL_XMLFILE fi - build_target $VENDOR $MAINBOARD $CONFIG - test_target $VENDOR $MAINBOARD - cat $TARGET/${VENDOR}_${MAINBOARD}/abuild.xml >> $REAL_XMLFILE - XMLFILE=$REAL_XMLFILE else - # build all boards per default - for VENDOR in $( vendors ); do - for MAINBOARD in $( mainboards $VENDOR ); do - build_target $VENDOR $MAINBOARD - test_target $VENDOR $MAINBOARD - remove_target $VENDOR $MAINBOARD - done - done + build_all_targets + rm -f $REAL_XMLFILE + xml '' + xml '' + + junit '' + junit '' for xmlfile in $TARGET/*_*/abuild.xml; do cat $xmlfile >> $REAL_XMLFILE done From gerrit at coreboot.org Sat Nov 5 17:04:08 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 17:04:08 +0100 Subject: [coreboot] New patch to review for coreboot: ef31a98 Fix typo References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/410 -gerrit commit ef31a985c4c922c8c87faa907768c2c4fc3e887e Author: Patrick Georgi Date: Sat Oct 15 01:03:16 2011 +0200 Fix typo Change-Id: I195ea15ddbc725091e32191fac3b84d01b456580 Signed-off-by: Patrick Georgi --- src/mainboard/supermicro/h8qgi/mptable.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 7373cb8..5c01994 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) #if CONFIG_MAX_CPUS >= 16 apicid_sp5100 = 0x0; #else - apicid_sp5100 = CONFIG_MAX_CPUS + 1 + apicid_sp5100 = CONFIG_MAX_CPUS + 1; #endif apicid_sr5650 = apicid_sp5100 + 1; From gerrit at coreboot.org Sat Nov 5 18:01:50 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Sat, 5 Nov 2011 18:01:50 +0100 Subject: [coreboot] New patch to review for coreboot: 5322328 Add code to set the clock speed for Winbond W83627THF/THG. References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/411 -gerrit commit 53223286a4d9d9c0a87aec1d29645d8121d7b502 Author: Idwer Date: Sat Nov 5 15:31:55 2011 +0100 Add code to set the clock speed for Winbond W83627THF/THG. Change-Id: If92d96d117683cc59081061d5ac93aa23cb87327 Signed-off-by: Idwer Vollering --- src/cpu/intel/model_f2x/Kconfig | 3 + src/cpu/intel/model_f2x/Makefile.inc | 1 + src/cpu/intel/model_f2x/cache_as_ram.inc | 376 ++++++++++ src/cpu/intel/socket_mPGA478/Kconfig | 1 + src/cpu/intel/socket_mPGA478/Makefile.inc | 2 +- src/include/device/pci_ids.h | 6 +- src/mainboard/asrock/Kconfig | 5 +- src/mainboard/asrock/p4i65gv/Kconfig | 53 ++ src/mainboard/asrock/p4i65gv/Makefile.inc | 1 + src/mainboard/asrock/p4i65gv/chip.h | 22 + src/mainboard/asrock/p4i65gv/devicetree.cb | 49 ++ src/mainboard/asrock/p4i65gv/irq_tables.c | 63 ++ src/mainboard/asrock/p4i65gv/mainboard.c | 26 + src/mainboard/asrock/p4i65gv/romstage.c | 84 +++ src/mainboard/asrock/p4i65gv/rtl8139.c | 46 ++ src/mainboard/asrock/p4i65gv/watchdog.c | 36 + src/mainboard/asus/Kconfig | 4 +- src/mainboard/asus/p4p800-vm/Kconfig | 53 ++ src/mainboard/asus/p4p800-vm/Makefile.inc | 1 + src/mainboard/asus/p4p800-vm/chip.h | 22 + src/mainboard/asus/p4p800-vm/devicetree.cb | 49 ++ src/mainboard/asus/p4p800-vm/e100.c | 46 ++ src/mainboard/asus/p4p800-vm/irq_tables.c | 63 ++ src/mainboard/asus/p4p800-vm/mainboard.c | 26 + src/mainboard/asus/p4p800-vm/romstage.c | 84 +++ src/mainboard/asus/p4p800-vm/watchdog.c | 36 + src/northbridge/intel/Kconfig | 1 + src/northbridge/intel/Makefile.inc | 1 + src/northbridge/intel/i865/Kconfig | 25 + src/northbridge/intel/i865/Makefile.inc | 2 + src/northbridge/intel/i865/TODO | 16 + src/northbridge/intel/i865/chip.h | 25 + src/northbridge/intel/i865/debug.c | 139 ++++ src/northbridge/intel/i865/i865.h | 89 +++ src/northbridge/intel/i865/northbridge.c | 171 +++++ src/northbridge/intel/i865/raminit.c | 1031 ++++++++++++++++++++++++++ src/northbridge/intel/i865/raminit.h | 181 +++++ src/northbridge/intel/i865/reset_test.c | 38 + src/southbridge/intel/i82801ex/early_smbus.c | 4 +- src/southbridge/intel/i82801ex/smbus.h | 3 + src/superio/winbond/w83627thg/early_serial.c | 11 + 41 files changed, 2888 insertions(+), 7 deletions(-) diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 50cac79..ca57343 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,3 +1,6 @@ config CPU_INTEL_MODEL_F2X bool select SMP + select MMX + select SSE + select CACHE_AS_RAM diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index c393343..d4ddb7b 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1 +1,2 @@ +cpu_incs += $(src)/cpu/intel/model_f2x/cache_as_ram.inc driver-y += model_f2x_init.c diff --git a/src/cpu/intel/model_f2x/cache_as_ram.inc b/src/cpu/intel/model_f2x/cache_as_ram.inc new file mode 100644 index 0000000..7742a68 --- /dev/null +++ b/src/cpu/intel/model_f2x/cache_as_ram.inc @@ -0,0 +1,376 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000, 2007 Ronald G. Minnich + * Copyright (C) 2005 Eswar Nallusamy, LANL + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2007 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +#define CacheSize CONFIG_DCACHE_RAM_SIZE +#define CacheBase (0xd0000 - CacheSize) + + /* Save the BIST result. */ + movl %eax, %ebp + +CacheAsRam: + /* Check whether the processor has HT capability. */ + movl $01, %eax + cpuid + btl $28, %edx + jnc NotHtProcessor + bswapl %ebx + cmpb $01, %bh + jbe NotHtProcessor + + /* + * It is a HT processor. Send SIPI to the other logical processor + * within this processor so that the CAR related common system + * registers are programmed accordingly. + */ + + /* + * Use some register that is common to both logical processors + * as semaphore. Refer Appendix B, Vol.3. + */ + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRfix64K_00000_MSR, %ecx + wrmsr + + /* + * Figure out the logical AP's APIC ID; the following logic will + * work only for processors with 2 threads. + * Refer to Vol 3. Table 7-1 for details about this logic. + */ + movl $0xFEE00020, %esi + movl (%esi), %ebx + andl $0xFF000000, %ebx + bswapl %ebx + btl $0, %ebx + jnc LogicalAP0 + andb $0xFE, %bl + jmp Send_SIPI +LogicalAP0: + orb $0x01, %bl +Send_SIPI: + bswapl %ebx /* EBX - logical AP's APIC ID. */ + + /* + * Fill up the IPI command registers in the Local APIC mapped to + * default address and issue SIPI to the other logical processor + * within this processor die. + */ +Retry_SIPI: + movl %ebx, %eax + movl $0xFEE00310, %esi + movl %eax, (%esi) + + /* SIPI vector - F900:0000 */ + movl $0x000006F9, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + movl $0x30, %ecx +SIPI_Delay: + pause + decl %ecx + jnz SIPI_Delay + + movl (%esi), %eax + andl $0x00001000, %eax + jnz Retry_SIPI + + /* Wait for the Logical AP to complete initialization. */ +LogicalAP_SIPINotdone: + movl $MTRRfix64K_00000_MSR, %ecx + rdmsr + orl %eax, %eax + jz LogicalAP_SIPINotdone + +NotHtProcessor: + /* Set the default memory type and enable fixed and variable MTRRs. */ + movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax + wrmsr + + /* Clear all MTRRs. */ + xorl %edx, %edx + movl $all_mtrr_msrs, %esi + +clear_fixed_var_mtrr: + lodsl (%esi), %eax + testl %eax, %eax + jz clear_fixed_var_mtrr_out + + movl %eax, %ecx + xorl %eax, %eax + wrmsr + + jmp clear_fixed_var_mtrr + +all_mtrr_msrs: + /* fixed MTRR MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var MTRR MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) + + .long 0x000 /* NULL, end of table */ + +clear_fixed_var_mtrr_out: + +/* + * 0x06 is the WB IO type for a given 4k segment. + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* + * The xorl here is superfluous because at the point of first execution + * of this macro, %eax and %edx are cleared. Later invocations of this + * macro will have a monotonically increasing segs parameter. + */ + xorl \reg, \reg +.elseif \segs == 1 + movl $0x06000000, \reg /* WB IO type */ +.elseif \segs == 2 + movl $0x06060000, \reg /* WB IO type */ +.elseif \segs == 3 + movl $0x06060600, \reg /* WB IO type */ +.elseif \segs >= 4 + movl $0x06060606, \reg /* WB IO type */ +.endif +.endm + +/* + * carsize is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size. + */ +.macro simplemask carsize, windowoffset + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + extractmask gas_bug_workaround, %eax + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + extractmask gas_bug_workaround, %edx + /* + * Without the gas bug workaround, the entire macro would consist + * only of the two lines below: + * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + */ +.endm + +#if CacheSize > 0x10000 +#error Invalid CAR size, must be at most 64k. +#endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif + +#if CacheSize > 0x8000 + /* Enable caching for 32K-64K using fixed MTRR. */ + movl $MTRRfix4K_C0000_MSR, %ecx + simplemask CacheSize, 0x8000 + wrmsr +#endif + + /* Enable caching for 0-32K using fixed MTRR. */ + movl $MTRRfix4K_C8000_MSR, %ecx + simplemask CacheSize, 0 + wrmsr + +#if CONFIG_XIP_ROM_SIZE + + /* + * Enable write base caching so we can do execute in place (XIP) + * on the flash ROM. + */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Read the range with lodsl. */ + movl $CacheBase, %esi + cld + movl $(CacheSize >> 2), %ecx + rep lodsl + + /* Clear the range. */ + movl $CacheBase, %edi + movl $(CacheSize >> 2), %ecx + xorl %eax, %eax + rep stosl + +#if 0 + /* Check the cache as ram. */ + movl $CacheBase, %esi + movl $(CacheSize >> 2), %ecx +.xin1: + movl %esi, %eax + movl %eax, (%esi) + decl %ecx + je .xout1 + add $4, %esi + jmp .xin1 +.xout1: + + movl $CacheBase, %esi + // movl $(CacheSize >> 2), %ecx + movl $4, %ecx +.xin1x: + movl %esi, %eax + + movl $0x4000, %edx + movb %ah, %al +.testx1: + outb %al, $0x80 + decl %edx + jnz .testx1 + + movl (%esi), %eax + cmpb 0xff, %al + je .xin2 /* Don't show. */ + + movl $0x4000, %edx +.testx2: + outb %al, $0x80 + decl %edx + jnz .testx2 + +.xin2: + decl %ecx + je .xout1x + add $4, %esi + jmp .xin1x +.xout1x: +#endif + + movl $(CacheBase + CacheSize - 4), %eax + movl %eax, %esp +lout: + /* Restore the BIST result. */ + movl %ebp, %eax + + /* We need to set EBP? No need. */ + movl %esp, %ebp + pushl %eax /* BIST */ + call main + + /* We don't need CAR from now on. */ + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + /* Clear sth. */ + movl $MTRRfix4K_C8000_MSR, %ecx + xorl %edx, %edx + xorl %eax, %eax + wrmsr + +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 + movl $MTRRfix4K_C0000_MSR, %ecx + wrmsr +#endif + + /* + * Set the default memory type and disable fixed + * and enable variable MTRRs. + */ + movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */ + wrmsr + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + diff --git a/src/cpu/intel/socket_mPGA478/Kconfig b/src/cpu/intel/socket_mPGA478/Kconfig index 8c447c9..c17780f 100644 --- a/src/cpu/intel/socket_mPGA478/Kconfig +++ b/src/cpu/intel/socket_mPGA478/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_SOCKET_MPGA478 bool select CPU_INTEL_MODEL_69X select CPU_INTEL_MODEL_6DX + select CPU_INTEL_MODEL_F2X diff --git a/src/cpu/intel/socket_mPGA478/Makefile.inc b/src/cpu/intel/socket_mPGA478/Makefile.inc index ba2f13c..c3742f3 100644 --- a/src/cpu/intel/socket_mPGA478/Makefile.inc +++ b/src/cpu/intel/socket_mPGA478/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += socket_mPGA478.c subdirs-y += ../model_69x subdirs-y += ../model_6dx +subdirs-y += ../model_f2x subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic @@ -8,4 +9,3 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading - diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d16f85e..37b5848 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2142,7 +2142,8 @@ #define PCI_DEVICE_ID_INTEL_82801DBM_EHCI 0x24cd /* Intel 82801EB (ICH5) */ -#define PCI_DEVICE_ID_INTEL_82801EB_LAN 0x1051 +#define PCI_DEVICE_ID_INTEL_82801EB_LAN1 0x1050 +#define PCI_DEVICE_ID_INTEL_82801EB_LAN2 0x1051 #define PCI_DEVICE_ID_INTEL_82801EB_PCI 0x244e #define PCI_DEVICE_ID_INTEL_82801EB_LPC 0x24d0 #define PCI_DEVICE_ID_INTEL_82801EB_SATA 0x24d1 @@ -2157,7 +2158,8 @@ #define PCI_DEVICE_ID_INTEL_82801EB_USB4 0x24de /* Intel 82801ER (ICH5R) */ -#define PCI_DEVICE_ID_INTEL_82801ER_LAN 0x1051 +#define PCI_DEVICE_ID_INTEL_82801ER_LAN1 0x1050 +#define PCI_DEVICE_ID_INTEL_82801ER_LAN2 0x1051 #define PCI_DEVICE_ID_INTEL_82801ER_PCI 0x244e #define PCI_DEVICE_ID_INTEL_82801ER_LPC 0x24d0 #define PCI_DEVICE_ID_INTEL_82801ER_USB1 0x24d2 diff --git a/src/mainboard/asrock/Kconfig b/src/mainboard/asrock/Kconfig index 1e4fff9..260f048 100644 --- a/src/mainboard/asrock/Kconfig +++ b/src/mainboard/asrock/Kconfig @@ -25,11 +25,14 @@ config BOARD_ASROCK_939A785GMH bool "939A785GMH/128M" config BOARD_ASROCK_E350M1 bool "E350M1" +config BOARD_ASROCK_P4I65GV + bool "P4i65GV" endchoice -source "src/mainboard/asrock/939a785gmh/Kconfig" +source "src/mainboard/asrock/939a785gmh/Kconfig" source "src/mainboard/asrock/e350m1/Kconfig" +source "src/mainboard/asrock/p4i65gv/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/asrock/p4i65gv/Kconfig b/src/mainboard/asrock/p4i65gv/Kconfig new file mode 100644 index 0000000..21e2b3d --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/Kconfig @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify it under the terms of the GNU General +## Public License as published by the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the +## implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along with this program; if not, write to +## the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +if BOARD_ASROCK_P4I65GV + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA478 + select NORTHBRIDGE_INTEL_I865 + select SOUTHBRIDGE_INTEL_I82801EX + select SUPERIO_WINBOND_W83627HF + select HAVE_HARD_RESET +# select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + select USE_WATCHDOG_ON_BOOT +# select HAVE_ACPI_TABLES +# select CACHE_AS_RAM # inherited from the socket option + +config MAINBOARD_DIR + string + default asrock/p4i65gv + +config MAINBOARD_PART_NUMBER + string + default "P4i65GV" + +config DCACHE_RAM_BASE + hex + default 0xfff00000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 # ok? + +config IRQ_SLOT_COUNT + int + default 6 # no idea + +endif # BOARD_ASROCK_P4I65GV diff --git a/src/mainboard/asrock/p4i65gv/Makefile.inc b/src/mainboard/asrock/p4i65gv/Makefile.inc new file mode 100644 index 0000000..03e044d --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/Makefile.inc @@ -0,0 +1 @@ +driver-y += rtl8139.c diff --git a/src/mainboard/asrock/p4i65gv/chip.h b/src/mainboard/asrock/p4i65gv/chip.h new file mode 100644 index 0000000..e77b136 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asrock/p4i65gv/devicetree.cb b/src/mainboard/asrock/p4i65gv/devicetree.cb new file mode 100644 index 0000000..992463c --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/devicetree.cb @@ -0,0 +1,49 @@ +chip northbridge/intel/i865 + device lapic_cluster 0 on + chip cpu/intel/socket_mPGA478 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 0.0 on end # northbridge + device pci 0.1 off end # agp + device pci 0.2 on end # igd + device pnp 0.3 off end # csa + device pci 0.6 on end # overflow device + + chip southbridge/intel/i82801ex + device pci 1d.0 on end # uhci #1 + device pci 1d.1 on end # uhci #2 + device pci 1d.2 on end # uhci #3 + device pci 1d.3 on end # uhci #4 + device pci 1d.7 on end # ehci + device pci 1e.0 on # pci bridge + # 01:05.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10) + device pci 05.0 on end + end + + device pci 1f.0 on # lpc bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off end # floppy + device pnp 2e.1 off end # parallel + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end # com1 + device pnp 2e.3 off end # com2 + device pnp 2e.5 on end # keyboard + device pnp 2e.6 off end # ir + device pnp 2e.7 on end # game/gpio 1 + device pnp 2e.8 on end # gpio 2 + device pnp 2e.9 on end # gpio 3 + device pnp 2e.a on end # acpi + device pnp 2e.b on end # hardware monitor + end # superio + end # 1f.0 + device pci 1f.1 on end # pata + device pci 1f.2 on end # sata + device pci 1f.3 on end # smbus + device pci 1f.5 off end # ac97 + end # southbridge + end # pci_domain +end # northbridge diff --git a/src/mainboard/asrock/p4i65gv/irq_tables.c b/src/mainboard/asrock/p4i65gv/irq_tables.c new file mode 100644 index 0000000..240ab23 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/irq_tables.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 200x TODO + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef GETPIR /* TODO: Drop this when copying to coreboot. */ +#include "pirq_routing.h" /* TODO: Drop this when copying to coreboot. */ +#else /* TODO: Drop this when copying to coreboot. */ +#include +#endif /* TODO: Drop this when copying to coreboot. */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 13, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x24d0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3e, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x01, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x6b, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{0x00, 0x0000}, {0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x01, (0x03 << 3) | 0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}}, 0x1, 0x0}, + {0x01, (0x01 << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x2, 0x0}, + {0x01, (0x02 << 3) | 0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x3, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}}, 0x4, 0x0}, + {0x01, (0x04 << 3) | 0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x01, (0x0a << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x6, 0x0}, + {0x01, (0x05 << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/asrock/p4i65gv/mainboard.c b/src/mainboard/asrock/p4i65gv/mainboard.c new file mode 100644 index 0000000..78aec29 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASRock P4i65GV Mainboard") +}; diff --git a/src/mainboard/asrock/p4i65gv/romstage.c b/src/mainboard/asrock/p4i65gv/romstage.c new file mode 100644 index 0000000..7f70ca0 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/romstage.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pc80/udelay_io.c" +//#include "lib/delay.c" +#include "cpu/x86/bist.h" + +//#include "southbridge/intel/i82801ex/i82801ex.h" +#include "southbridge/intel/i82801ex/early_smbus.c" +#include "northbridge/intel/i865/debug.c" +#include "northbridge/intel/i865/raminit.c" +//#include "northbridge/intel/i865/reset_test.c" +#include "northbridge/intel/i865/i865.h" +#include "superio/winbond/w83627hf/early_serial.c" +#include "watchdog.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +//int spd_read_byte(unsigned int device, unsigned int address) +//static inline int spd_read_byte(unsigned device, unsigned address) +//{ +// return smbus_read_byte(device, address); +//} + +void main(unsigned long bist) { + + // TODO + // copied from dell/s1850/romstage.c + /* + static const struct mem_controller memctrl[] = { + { + // node id? + .channel0 = { DIMM0, DIMM1, DIMM2, DIMM3, }, + .channel1 = { DIMM4, DIMM5, DIMM6, DIMM7, }, + } + }; +*/ + if (bist == 0) + enable_lapic(); + + w83627hf_set_clksel_48(SERIAL_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + report_bist_failure(bist); + +// if (!bios_reset_detected()) /* board doesn't boot when using bios_rest_detected() */ +// { + enable_smbus(); + dump_spd_registers(); + + disable_ich5_watchdog(); + + // TODO: dual-channel, e.g.: + // sdram_initialize(ARRAY_SIZE(memctrl), memctrl); // copied from dell/s1850/romstage.c + sdram_initialize(); +// } +} diff --git a/src/mainboard/asrock/p4i65gv/rtl8139.c b/src/mainboard/asrock/p4i65gv/rtl8139.c new file mode 100644 index 0000000..d909af7 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/rtl8139.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include +#include +#include +#include + +static void nic_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Initializing RTL8139 Fast Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. +} +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver rtl8139_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_REALTEK, + .device = PCI_DEVICE_ID_REALTEK_8139, +}; diff --git a/src/mainboard/asrock/p4i65gv/watchdog.c b/src/mainboard/asrock/p4i65gv/watchdog.c new file mode 100644 index 0000000..8c7b0f6 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/watchdog.c @@ -0,0 +1,36 @@ +/* copied and adapted from src/mainboard/dell/s1850/watchdog.c */ + +#define ICH5_WDBASE 0x800 /* PMBASE */ +#define ICH5_GPIOBASE 0x480 + +static void disable_ich5_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); /* LPC bridge */ + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); /* PCICMD */ + value |= (1 << 10); /* reserved? */ + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); /* PMBASE */ + pci_write_config8(dev, 0x44, 0x10); /* ACPI_CNTL = ACPI_EN */ + base = ICH5_WDBASE + 0x60; /* TCO offset, ich5 datasheet ch9.11 */ + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; /* enable TCO_TMR_HLT */ + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); /* TCO1_STS, raise bit 3: TIMEOUT */ + outw(0x0002, base + 0x06); /* TCO2_STS, raise bit 2: SECOND_TO_STS */ + + printk(BIOS_DEBUG, "Board-specific ICH5 watchdog disabled\n"); +} diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..1369a4b 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -55,7 +55,8 @@ config BOARD_ASUS_P2B_LS bool "P2B-LS" config BOARD_ASUS_P3B_F bool "P3B-F" - +config BOARD_ASUS_P4P800_VM + bool "P4P800-VM" endchoice source "src/mainboard/asus/a8n_e/Kconfig" @@ -75,6 +76,7 @@ source "src/mainboard/asus/p2b-ds/Kconfig" source "src/mainboard/asus/p2b-f/Kconfig" source "src/mainboard/asus/p2b-ls/Kconfig" source "src/mainboard/asus/p3b-f/Kconfig" +source "src/mainboard/asus/p4p800-vm/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/asus/p4p800-vm/Kconfig b/src/mainboard/asus/p4p800-vm/Kconfig new file mode 100644 index 0000000..ef93089 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/Kconfig @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify it under the terms of the GNU General +## Public License as published by the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the +## implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along with this program; if not, write to +## the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +if BOARD_ASUS_P4P800_VM + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA478 + select NORTHBRIDGE_INTEL_I865 + select SOUTHBRIDGE_INTEL_I82801EX + select SUPERIO_WINBOND_W83627THG + select HAVE_HARD_RESET +# select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + select USE_WATCHDOG_ON_BOOT +# select HAVE_ACPI_TABLES +# select CACHE_AS_RAM # inherited from the socket option + +config MAINBOARD_DIR + string + default asus/p4p800-vm + +config MAINBOARD_PART_NUMBER + string + default "P4P800-VM" + +config DCACHE_RAM_BASE + hex + default 0xfff00000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 # ok? + +config IRQ_SLOT_COUNT + int + default 6 # no idea + +endif # BOARD_ASUS_P4P800_VM diff --git a/src/mainboard/asus/p4p800-vm/Makefile.inc b/src/mainboard/asus/p4p800-vm/Makefile.inc new file mode 100644 index 0000000..93aefe9 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/Makefile.inc @@ -0,0 +1 @@ +driver-y += e100.c diff --git a/src/mainboard/asus/p4p800-vm/chip.h b/src/mainboard/asus/p4p800-vm/chip.h new file mode 100644 index 0000000..e77b136 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/p4p800-vm/devicetree.cb b/src/mainboard/asus/p4p800-vm/devicetree.cb new file mode 100644 index 0000000..cf80f53 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/devicetree.cb @@ -0,0 +1,49 @@ +chip northbridge/intel/i865 + device lapic_cluster 0 on + chip cpu/intel/socket_mPGA478 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 0.0 on end # northbridge + device pci 0.1 off end # agp + device pci 0.2 on end # igd + device pnp 0.3 off end # csa + device pci 0.6 on end # overflow device + + chip southbridge/intel/i82801ex + device pci 1d.0 on end # uhci #1 + device pci 1d.1 on end # uhci #2 + device pci 1d.2 on end # uhci #3 + device pci 1d.3 on end # uhci #4 + device pci 1d.7 on end # ehci + device pci 1e.0 on # pci bridge + # 01:08.0 Ethernet controller: Intel Corporation 82562EZ 10/100 Ethernet Controller (rev 02) + device pci 08.0 on end + end + + device pci 1f.0 on # lpc bridge + chip superio/winbond/w83627thg + device pnp 2e.0 off end # floppy + device pnp 2e.1 off end # parallel + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end # com1 + device pnp 2e.3 off end # com2 + device pnp 2e.5 on end # keyboard + device pnp 2e.6 off end # ir + device pnp 2e.7 on end # game/gpio 1 + device pnp 2e.8 on end # gpio 2 + device pnp 2e.9 on end # gpio 3 + device pnp 2e.a on end # acpi + device pnp 2e.b on end # hardware monitor + end # superio + end # 1f.0 + device pci 1f.1 on end # pata + device pci 1f.2 on end # sata + device pci 1f.3 on end # smbus + device pci 1f.5 off end # ac97 + end # southbridge + end # pci_domain +end # northbridge diff --git a/src/mainboard/asus/p4p800-vm/e100.c b/src/mainboard/asus/p4p800-vm/e100.c new file mode 100644 index 0000000..d3c0e07 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/e100.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include +#include +#include +#include + +static void nic_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Initializing Intel 82562EZ 10/100 Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. +} +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver intel_e100_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_LAN1, /* 8086:1050 */ +}; diff --git a/src/mainboard/asus/p4p800-vm/irq_tables.c b/src/mainboard/asus/p4p800-vm/irq_tables.c new file mode 100644 index 0000000..240ab23 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/irq_tables.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 200x TODO + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef GETPIR /* TODO: Drop this when copying to coreboot. */ +#include "pirq_routing.h" /* TODO: Drop this when copying to coreboot. */ +#else /* TODO: Drop this when copying to coreboot. */ +#include +#endif /* TODO: Drop this when copying to coreboot. */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 13, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x24d0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3e, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x01, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x6b, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{0x00, 0x0000}, {0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x01, (0x03 << 3) | 0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}}, 0x1, 0x0}, + {0x01, (0x01 << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x2, 0x0}, + {0x01, (0x02 << 3) | 0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x3, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}}, 0x4, 0x0}, + {0x01, (0x04 << 3) | 0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x01, (0x0a << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x6, 0x0}, + {0x01, (0x05 << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/asus/p4p800-vm/mainboard.c b/src/mainboard/asus/p4p800-vm/mainboard.c new file mode 100644 index 0000000..5b47989 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS P4P800-VM Mainboard") +}; diff --git a/src/mainboard/asus/p4p800-vm/romstage.c b/src/mainboard/asus/p4p800-vm/romstage.c new file mode 100644 index 0000000..fad3aca --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/romstage.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pc80/udelay_io.c" +//#include "lib/delay.c" +#include "cpu/x86/bist.h" + +//#include "southbridge/intel/i82801ex/i82801ex.h" +#include "southbridge/intel/i82801ex/early_smbus.c" +#include "northbridge/intel/i865/debug.c" +#include "northbridge/intel/i865/raminit.c" +//#include "northbridge/intel/i865/reset_test.c" +#include "northbridge/intel/i865/i865.h" +#include "superio/winbond/w83627thg/early_serial.c" +#include "watchdog.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +//int spd_read_byte(unsigned int device, unsigned int address) +//static inline int spd_read_byte(unsigned device, unsigned address) +//{ +// return smbus_read_byte(device, address); +//} + +void main(unsigned long bist) { + + // TODO + // copied from dell/s1850/romstage.c + /* + static const struct mem_controller memctrl[] = { + { + // node id? + .channel0 = { DIMM0, DIMM1, DIMM2, DIMM3, }, + .channel1 = { DIMM4, DIMM5, DIMM6, DIMM7, }, + } + }; +*/ + if (bist == 0) + enable_lapic(); + + w83627thg_set_clksel_48(SERIAL_DEV); + w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + report_bist_failure(bist); + +// if (!bios_reset_detected()) /* board doesn't boot when using bios_rest_detected() */ +// { + enable_smbus(); + dump_spd_registers(); + + disable_ich5_watchdog(); + + // TODO: dual-channel, e.g.: + // sdram_initialize(ARRAY_SIZE(memctrl), memctrl); // copied from dell/s1850/romstage.c + sdram_initialize(); +// } +} diff --git a/src/mainboard/asus/p4p800-vm/watchdog.c b/src/mainboard/asus/p4p800-vm/watchdog.c new file mode 100644 index 0000000..8c7b0f6 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/watchdog.c @@ -0,0 +1,36 @@ +/* copied and adapted from src/mainboard/dell/s1850/watchdog.c */ + +#define ICH5_WDBASE 0x800 /* PMBASE */ +#define ICH5_GPIOBASE 0x480 + +static void disable_ich5_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); /* LPC bridge */ + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); /* PCICMD */ + value |= (1 << 10); /* reserved? */ + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); /* PMBASE */ + pci_write_config8(dev, 0x44, 0x10); /* ACPI_CNTL = ACPI_EN */ + base = ICH5_WDBASE + 0x60; /* TCO offset, ich5 datasheet ch9.11 */ + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; /* enable TCO_TMR_HLT */ + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); /* TCO1_STS, raise bit 3: TIMEOUT */ + outw(0x0002, base + 0x06); /* TCO2_STS, raise bit 2: SECOND_TO_STS */ + + printk(BIOS_DEBUG, "Board-specific ICH5 watchdog disabled\n"); +} diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 1809d11..e5c8ed5 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -8,5 +8,6 @@ source src/northbridge/intel/i440lx/Kconfig source src/northbridge/intel/i82810/Kconfig source src/northbridge/intel/i82830/Kconfig source src/northbridge/intel/i855/Kconfig +source src/northbridge/intel/i865/Kconfig source src/northbridge/intel/i945/Kconfig source src/northbridge/intel/sch/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 0d116d0..9d333b6 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -8,6 +8,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440LX) += i440lx subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I865) += i865 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch diff --git a/src/northbridge/intel/i865/Kconfig b/src/northbridge/intel/i865/Kconfig new file mode 100644 index 0000000..944f701 --- /dev/null +++ b/src/northbridge/intel/i865/Kconfig @@ -0,0 +1,25 @@ +config NORTHBRIDGE_INTEL_I865 + bool + select HAVE_DEBUG_RAM_SETUP +choice +prompt "Onboard graphics" + default I865_VIDEO_MB_8MB + depends on NORTHBRIDGE_INTEL_I865 + +config I865_VIDEO_MB_OFF + bool "Disabled, 0KB" +config I865_VIDEO_MB_1MB + bool "Enabled, 1MB" +config I865_VIDEO_MB_8MB + bool "Enabled, 8MB" +config I865_VIDEO_MB_16MB + bool "Enabled, 16MB" +endchoice + +config VIDEO_MB + int + default 0 if I865_VIDEO_MB_OFF + default 1 if I865_VIDEO_MB_1MB + default 8 if I865_VIDEO_MB_8MB + default 16 if I865_VIDEO_MB_16MB + depends on NORTHBRIDGE_INTEL_I865 diff --git a/src/northbridge/intel/i865/Makefile.inc b/src/northbridge/intel/i865/Makefile.inc new file mode 100644 index 0000000..8cec43f --- /dev/null +++ b/src/northbridge/intel/i865/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += northbridge.c +#romstage-y += early_init.c diff --git a/src/northbridge/intel/i865/TODO b/src/northbridge/intel/i865/TODO new file mode 100644 index 0000000..2f28af0 --- /dev/null +++ b/src/northbridge/intel/i865/TODO @@ -0,0 +1,16 @@ +TODO (probably incomplete) + +raminit.c: + * re-use the mchbar macro from i945 and read/write from/to it like its raminit code does + * GPL headers everywhere + * includes (is assert.h really needed?) + * set TOUD (from northbridge.c?) + * set SMFREQ and FSBFREQ (in GMCHCFG) (from northbridge.c?)? + * AGP (device 1) code + * VGA/IGD (device 2) code + * CSA (device 3) code? + * clean up/trim northbridge_set_registers() + * dual-channel code (and don't forget romstage.c) + +DONE +* raise bits 0 (IOAE, I/O access enable) and 1 (MAE, memory access enable) in PCICMD6 (from northbridge.c?) diff --git a/src/northbridge/intel/i865/chip.h b/src/northbridge/intel/i865/chip.h new file mode 100644 index 0000000..6e7b21e --- /dev/null +++ b/src/northbridge/intel/i865/chip.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Jon Dufresne + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_intel_i865_config +{ +}; + +extern struct chip_operations northbridge_intel_i865_ops; diff --git a/src/northbridge/intel/i865/debug.c b/src/northbridge/intel/i865/debug.c new file mode 100644 index 0000000..a7935ce --- /dev/null +++ b/src/northbridge/intel/i865/debug.c @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +static void print_debug_pci_dev(unsigned dev) { + print_debug("PCI: "); + print_debug_hex8((dev >> 20) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 15) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 12) & 0x07); +} +static inline void print_pci_devices(void) { + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\n"); + } +} +static void dump_pci_device(unsigned dev) { + int i; + print_debug_pci_dev(dev); + print_debug("\n"); + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} +static inline void dump_pci_devices(void) { + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} +static inline void dump_spd_registers(void) { + int i; + print_debug("\n"); + for(i = 0; i < 2; i++) { + unsigned device; + device = DIMM0 + i; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\n"); + } + } +} +static inline void dump_smbus_registers(void) { + int i; + print_debug("\n"); + for(i = 1; i < 0x80; i++) { + unsigned device; + device = i; + int j; + print_debug("smbus: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\n"); + } +} diff --git a/src/northbridge/intel/i865/i865.h b/src/northbridge/intel/i865/i865.h new file mode 100644 index 0000000..51cf0bc --- /dev/null +++ b/src/northbridge/intel/i865/i865.h @@ -0,0 +1,89 @@ +/* TODO: + * AGP #defines + * GPL header + */ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Travelping GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* size, default value */ +/* DRAM Controller (device 0) */ +#define APBASE 0x10 /* 32 bit, 0x8 */ +// #define AGPM 0x51 /* 8 bit, 0x0 */ +// #define ESMRAMC 0x9e /* 8 bit, 0x38 */ +// #define ACAPID 0xa0 /* 32bit, 0x300002 (RO) */ +// #define AGPSTAT 0xa4 /* 32bit, AGP 2.0: 0x1f004217 (RO) or AGP 3.0: 0x1f004a13 (RO) */ +// #define AGPCMD 0xa8 /* 32bit, AGP 2.0: 0x0 or AGP 3.0: 0xa00 */ +// #define AGPCTRL 0xb0 /* 32bit, 0x0 */ +#define AMTT 0xbc /* 8 bit, 0x10 */ +#define APSIZE 0xb4 /* 8 bit, 0x0 */ +// #define ATTBASE 0xb8 /* 32 bit, 0x0 */ +#define TOUD 0xc4 /* 16 bit, 0x400 */ +#define GMCHCFG 0xc6 /* 16 bit, 0x0 */ +#define ERRSTS 0xc8 /* 16 bit, 0x0 */ +// #define ERRCMD 0xca /* 16 bit, 0x0 */ +// #define FDHC 0x97 /* 8 bit, 0x0 */ +// #define FPLLCONT 0x60 /* 8 bit, 0x0 */ +#define GC 0x52 /* 8 bit (looks wrong), 0x1000 */ +#define LPTT 0xbd /* 8 bit, 0x10 */ +#define PCISTS 0x10 /* 16 bit, 0x90 */ +// #define SMRAM 0x9D /* 8 bit, 0x2 */ +#define SVID 0x2c /* 16 bit, 0x0 */ +#define SID 0x2e /* 16 bit, 0x0 */ +// #define CSABCONT 0x53 /* 8 bit, 0x0 */ +#define VID 0x0 /* 16 bit, 0x8086 */ +#define DID 0x2 /* 16 bit, 0x2570 */ +/* PCI-to-AGP bridge (device 1) */ +// #define PCICMD1 0x04 /* 16 bit, 0x0 */ +// #define SMLT1 0x0d /* 8 bit, 0x0 */ +// #define SBUSN1 0x19 /* 8 bit, 0x0 */ +// #define SUBUSN1 0x1a /* 8 bit, 0x0 */ +// #define PMBASE1 0x24 /* 16 bit, 0xfff0 */ +// #define PMLIMIT1 0x26 /* 16 bit, 0x0 */ +// #define BCTRL1 0x3e /* 8 bit, 0x0 */ +// #define ERRCMD1 0x40 /* 8 bit, 0x0 */ + +/* Integrated Graphics Device (device 2) */ +// #define PCICMD2 0x04 /* 16 bit, 0x0 */ +// #define GMADR 0x10 /* 32 bit, 0x8 */ +// #define MMADR 0x14 /* 32 bit, 0x0 */ +// #define IOBAR 0x18 /* 32 bit, 0x1 */ +// #define SVID2 0x2c /* 16 bit, 0x0 */ +// #define SID2 0x2e /* 16 bit, 0x0 */ +// #define INTRLINE 0x3c /* 8 bit, 0x0 */ +// #define PMCS 0xd4 /* 16 bit, 0x0 */ +// #define SWSMI 0xe0 /* 16 bit, 0x0 */ + +/* PCI-to-CSA bridge (device 3) */ +// #define PCICMD3 0x04 /* 16 bit, 0x0 */ +// #define IOBASE3 0x1c /* 8 bit, 0xf0 */ +// #define IOLIMIT3 0x1d /* 8 bit, 0x0 */ +// #define MBASE3 0x20 /* 16 bit, 0xfff0 */ +// #define MLIMIT3 0x22 /* 16 bit, 0x0 */ +// #define PMBASE3 0x24 /* 16 bit, 0xfff0 */ +// #define PMLIMIT3 0x26 /* 16 bit, 0x0 */ +// #define BCTRL3 0x3e /* 8 bit, 0x0 */ +// #define CSACNTRL 0x50 /* 32 bit, 0xe042802 */ + +/* Overflow device (device 6) */ +#define PCICMD6 0x04 /* 16 bit (looks wrong), 0x0 */ +#define BAR6 0x10 /* 32 bit, 0x0 */ +// #define SVID6 0x2c /* 16 bit, 0x0 */ +// #define SID6 0x2e /* 16 bit, 0x0 */ diff --git a/src/northbridge/intel/i865/northbridge.c b/src/northbridge/intel/i865/northbridge.c new file mode 100644 index 0000000..c249be3 --- /dev/null +++ b/src/northbridge/intel/i865/northbridge.c @@ -0,0 +1,171 @@ +/* TODO: + * CSA (device 3) code + * set all subsytem IDs (SID*, SVID*) + */ + + /* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Ronald G. Minnich + * Copyright (C) 2003-2004 Eric W. Biederman + * Copyright (C) 2006 Jon Dufresne + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "i865.h" +#include "raminit.h" + +static void northbridge_init(device_t dev) +{ + printk(BIOS_SPEW, "Northbridge init\n"); +} + +static struct device_operations northbridge_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2570, +}; + +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif +static void pci_domain_set_resources(device_t dev) +{ + device_t mc_dev; + uint32_t pci_tolm; + + printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); + printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device); + + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children->sibling; + printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor); + printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device); + + if (mc_dev) { + /* Figure out which areas are/should be occupied by RAM. + * This is all computed in kilobytes and converted to/from + * the memory controller right at the edges. + * Having different variables in different units is + * too confusing to get right. Kilobytes are good up to + * 4 Terabytes of RAM... + */ + unsigned long tomk, tolmk; + int idx; + + /* Get the value of the highest DRB. This tells the end of + * the physical memory. The units are ticks of 64 MB + * i.e. 1 means 64 MB. + */ + //tomk = (unsigned long)pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), DRB + 7); +// tomk = BAR6_8(DRB + 7); + tomk = MCHBAR8(DRB + 7); + tomk = tomk * 64 * 1024; + /* add vga_mem detection */ + tomk = tomk - 16 * 1024; // 16 MB, graphics mode select (GMS) + /* Compute the top of Low memory */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does not overlap memory + */ + tolmk = tomk; + } + /* Write the ram configuration registers, + * preserving the reserved bits. + */ + + /* Report the memory regions */ + printk(BIOS_DEBUG, "tomk = %ld\n", tomk); + printk(BIOS_DEBUG, "tolmk = %ld\n", tolmk); + + idx = 10; + /* avoid pam region */ + ram_resource(dev, idx++, 0, 640); + /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ + ram_resource(dev, idx++, 768, tolmk - 768); + +#if CONFIG_WRITE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif + } + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_i865_ops = { + CHIP_NAME("Intel 865 Northbridge") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/intel/i865/raminit.c b/src/northbridge/intel/i865/raminit.c new file mode 100644 index 0000000..91e3144 --- /dev/null +++ b/src/northbridge/intel/i865/raminit.c @@ -0,0 +1,1031 @@ +#include +#include +#include + +#include "i865.h" +#include "raminit.h" + +struct dimm_size { + unsigned int side1; + unsigned int side2; +}; + +static const uint32_t refresh_frequency[] = { + /* Relative frequency (array value) of each E7501 Refresh Mode Select + * (RMS) value (array index) + * 0 == least frequent refresh (longest interval between refreshes) + * [0] disabled -> 0 + * [1] 15.6 usec -> 2 + * [2] 7.8 usec -> 3 + * [3] 64 usec -> 1 + * [4] reserved -> 0 + * [5] reserved -> 0 + * [6] reserved -> 0 + * [7] 64 clocks -> 4 + */ + 0, 2, 3, 1, 0, 0, 0, 4 +}; + +static const uint32_t refresh_rate_map[] = { + /* Map the JEDEC spd refresh rates (array index) to i855 Refresh Mode + * Select values (array value) + * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 + * The i855 supports only 15.6 us (1), 7.8 us (2) and + * 64 clock (481 ns) (7) refresh. + * [0] == 15.625 us -> 15.6 us + * [1] == 3.9 us -> 481 ns + * [2] == 7.8 us -> 7.8 us + * [3] == 31.3 us -> 15.6 us + * [4] == 62.5 us -> 15.6 us + * [5] == 125 us -> 15.6 us + */ + 1, 7, 2, 1, 1, 1 +}; + +#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) + +static inline int spd_read_byte(unsigned device, unsigned address) +//static int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +static void set_initialization_complete(void) +{ + printk(BIOS_DEBUG, "Setting initialization complete (DRC bit 29)\n"); + MCHBAR32(DRC) |= RAM_INITIALIZATION_COMPLETE; +} + +//static void do_ram_command(u32 command) +static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) +{ + int i; + u32 reg32; +// uint8_t dimm_start_32M_multiple = 0; + uint8_t dimm_start_64M_multiple = 0; + uint16_t i855_mode_bits = jedec_mode_bits; + + /* Configure the RAM command. */ +// reg32 = pci_read_config32(NORTHBRIDGE_MMC, DRC); + reg32 = MCHBAR32(DRC); + reg32 &= ~(7 << 4); + reg32 |= (command << 4); + printk(BIOS_DEBUG, " Sending RAM command 0x%08x\n", reg32); +// pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32); + MCHBAR32(DRC) = reg32; + + // RAM_COMMAND_NORMAL is an exception. + // It affects only the memory controller and does not need to be "sent" to the DIMMs. + + if (command != RAM_COMMAND_NORMAL) { + + // Send the command to all DIMMs by accessing a memory location within each + // NOTE: for mode select commands, some of the location address bits + // are part of the command + + // Map JEDEC mode bits to i855 + if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) { + /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ + // i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9)); + /* Host address lines [13:3] map to DIMM address lines [5:1] */ + // i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (6 - 1)); + i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3f) << (6 - 1)); + } + + for (i = 0; i < (DIMM_SOCKETS * 2); ++i) { +// uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i); + /* i865 uses a granularity of 64 megabyte */ + uint8_t dimm_end_64M_multiple = MCHBAR8(DRB + i); +// if (dimm_end_32M_multiple > dimm_start_32M_multiple) { + if (dimm_end_64M_multiple > dimm_start_64M_multiple) { + +// uint32_t dimm_start_address = dimm_start_32M_multiple << 25; + uint32_t dimm_start_address = dimm_start_64M_multiple << 25; + printk(BIOS_DEBUG, " Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits); + //read32(dimm_start_address + i855_mode_bits); + printk(BIOS_DEBUG, " /* skipping read32() */\n"); + printk(BIOS_DEBUG, " Sent. dimm_start_address = 0x%x and i855_mode_bits = 0x%x\n", dimm_start_address, i855_mode_bits); + + // Set the start of the next DIMM +// dimm_start_32M_multiple = dimm_end_32M_multiple; + dimm_start_64M_multiple = dimm_end_64M_multiple; + } + } + } +} + +static void sdram_enable(void) +{ + int i; + + print_debug("Ram enable 1\n"); + delay(); + delay(); + + /* NOP command */ + printk(BIOS_DEBUG, " NOP\n"); + do_ram_command(RAM_COMMAND_NOP, 0); + delay(); + delay(); + delay(); + + /* Pre-charge all banks (at least 200 us after NOP) */ + printk(BIOS_DEBUG, " Pre-charging all banks\n"); + do_ram_command(RAM_COMMAND_PRECHARGE, 0); + delay(); + delay(); + delay(); + + printk(BIOS_DEBUG, "Ram enable 4\n"); + do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE); + delay(); + delay(); + delay(); + + print_debug("Ram enable 5\n"); + do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_DLL_RESET); + + print_debug("Ram enable 6\n"); + do_ram_command(RAM_COMMAND_PRECHARGE, 0); + delay(); + delay(); + delay(); + + /* 8 CBR refreshes (Auto Refresh) */ + printk(BIOS_DEBUG, " 8 CBR refreshes\n"); + for(i = 0; i < 8; i++) { + do_ram_command(RAM_COMMAND_CBR, 0); + delay(); + delay(); + delay(); + } + + printk(BIOS_DEBUG, "Ram enable 8\n"); + do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_NORMAL); + + /* Set GME-M Mode Select bits back to NORMAL operation mode */ + printk(BIOS_DEBUG, " Normal operation mode\n"); + do_ram_command(RAM_COMMAND_NORMAL, 0); +/* delay(); + delay(); + delay(); + + print_debug("Ram enable 9\n"); + set_initialize_complete(); + + delay(); + delay(); + delay(); + delay(); + delay(); + + print_debug("After configuration:\n"); +*/ + /* dump_pci_devices(); */ + + /* + print_debug("\n\n***** RAM TEST *****\n"); + ram_check(0, 0xa0000); + ram_check(0x100000, 0x40000000); + */ +} + +//static void ram_read32(u8 dimm_start, u32 offset) +//{ + /* not implemented */ +//} + +//static void initialize_dimm_rows(void) +//{ + /* copied from i82830/raminit.c */ + /* not implemented */ +//} + +static void die_on_spd_error(int spd_return_value) +{ + if (spd_return_value < 0) + printk(BIOS_DEBUG, "Error reading SPD info: got %d\n", spd_return_value); +/* + if (spd_return_value < 0) + die("Error reading SPD info\n"); +*/ +} + +static struct dimm_size sdram_spd_get_page_size(u8 dimm_socket_address) +{ + uint16_t module_data_width; + int value; + struct dimm_size pgsz; + + pgsz.side1 = 0; + pgsz.side2 = 0; + + // Side 1 + value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + die_on_spd_error(value); + + pgsz.side1 = value & 0xf; // # columns in bank 1 + + /* Get the module data width and convert it to a power of two */ + value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); + die_on_spd_error(value); + + module_data_width = (value & 0xff) << 8; + + value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); + die_on_spd_error(value); + + module_data_width |= (value & 0xff); + + pgsz.side1 += log2(module_data_width); + + /* side two */ + value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + die_on_spd_error(value); + + if (value > 2) + printk(BIOS_DEBUG, "Bad SPD value\n"); + + if (value == 2) { + pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently + value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + die_on_spd_error(value); + + if ((value & 0xf0) != 0) { + // Asymmetric banks + pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */ + pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */ + } + } + + return pgsz; +} + +/** + * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16). + * + * @param dimm_socket_address SMBus address of DIMM socket to interrogate. + * @return Width in bits of each DIMM side's DRAMs. + */ +static struct dimm_size sdram_spd_get_width(u8 dimm_socket_address) +{ + int value; + struct dimm_size width; + + width.side1 = 0; + width.side2 = 0; + + value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); + die_on_spd_error(value); + + width.side1 = value & 0x7f; // Mask off bank 2 flag + + if (value & 0x80) { + width.side2 = width.side1 << 1; // Bank 2 exists and is double-width + } else { + // If bank 2 exists, it's the same width as bank 1 + value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + die_on_spd_error(value); + + switch (value) { + case 2: + width.side2 = width.side1; + break; + + default: + break; + } + } + + return width; +} + +/** + * Calculate the log base 2 size in bits of both DIMM sides. + * + * log2(# bits) = (# columns) + log2(data width) + + * (# rows) + log2(banks per SDRAM) + * + * Note that it might be easier to use SPD byte 31 here, it has the DIMM size + * as a multiple of 4MB. The way we do it now we can size both sides of an + * asymmetric DIMM. + * + * @param dimm SMBus address of DIMM socket to interrogate. + * @return log2(number of bits) for each side of the DIMM. + */ +static struct dimm_size spd_get_dimm_size(unsigned dimm) +{ + int value; + + // Start with log2(page size) + struct dimm_size sz = sdram_spd_get_page_size(dimm); + + if (sz.side1 > 0) { + value = spd_read_byte(dimm, SPD_NUM_ROWS); + die_on_spd_error(value); + + sz.side1 += value & 0xf; + + if (sz.side2 > 0) { + // Double-sided DIMM + if (value & 0xF0) + sz.side2 += value >> 4; // Asymmetric + else + sz.side2 += value; // Symmetric + } + + value = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); + die_on_spd_error(value); + + value = log2(value); + sz.side1 += value; + if (sz.side2 > 0) + sz.side2 += value; + } + + return sz; +} + +// static void set_dram_row_boundaries(void) { /* TODO */ } +// static void set_dram_row_attributes(void) { /* TODO */ } +// static void set_dram_timing(void) { /* TODO */ } +// static void sdram_set_registers(void) { /* TODO */ } + +static uint8_t spd_get_supported_dimms(void) +{ + int i; + uint8_t dimm_mask = 0; + +// for (i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { + u8 dimm = DIMM0 + i; + + struct dimm_size page_size; + struct dimm_size sdram_width; + + int spd_value; + + if (dimm == 0) + continue; + + if (spd_read_byte(dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR) + // print a little warning, maybe? + continue; + + if ((spd_value = spd_read_byte(dimm, SPD_MODULE_VOLTAGE)) != SPD_VOLTAGE_SSTL2) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported voltage: %02x\n", spd_value); + continue; + } + + page_size = sdram_spd_get_page_size(dimm); + sdram_width = sdram_spd_get_width(dimm); + + // Validate DIMM page size + // The i855 only supports page sizes of 4, 8, 16 KB per channel + // NOTE: 4 KB = 32 Kb = 2^15 + // 16 KB = 128 Kb = 2^17 + + if ((page_size.side1 < 15) || (page_size.side1 > 17)) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported page size: %d\n", page_size.side1); + continue; + } + + // If DIMM is double-sided, verify side2 page size + if (page_size.side2 != 0) { + if ((page_size.side2 < 15) || (page_size.side2 > 17)) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported page size: %d\n", page_size.side2); + continue; + } + } + // Validate SDRAM width + // The i855 only supports x8 and x16 devices + if ((sdram_width.side1 != 8) && (sdram_width.side1 != 16)) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported width: %d\n", sdram_width.side2); + continue; + } + + // If DIMM is double-sided, verify side2 width + if (sdram_width.side2 != 0) { + if ((sdram_width.side2 != 8) + && (sdram_width.side2 != 16)) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported width: %d\n", sdram_width.side2); + continue; + } + } + // Made it through all the checks, this DIMM is usable + dimm_mask |= (1 << i); + } + + return dimm_mask; +} + +static void spd_set_row_attributes(uint8_t dimm_mask) +{ + int i; + uint16_t row_attributes = 0; + + for (i = 0; i < DIMM_SOCKETS; i++) { + u8 dimm = DIMM0 + i; + struct dimm_size page_size; + struct dimm_size sdram_width; + + if (!(dimm_mask & (1 << i))) { +// row_attributes |= 0x77 << (i << 3); + row_attributes |= 0x0 << (i << 3); // default value of DRA on i865 is 0x0 + continue; // This DIMM not usable + } + + // Get the relevant parameters via SPD + page_size = sdram_spd_get_page_size(dimm); + sdram_width = sdram_spd_get_width(dimm); + + // Update the DRAM Row Attributes. + // Page size is encoded as log2(page size in bits) - log2(2 KB) or 4 KB == 1, 8 KB == 3, 16KB == 3 +// i865: Page size is encoded as log2(page size in bits) - log2(2 KB) or 4 KB == 0, 8 KB == 1, 16KB == 2, 32KB == 3 + // NOTE: 2 KB = 16 Kb = 2^14 +// row_attributes |= (page_size.side1 - 14) << (i << 3); // Side 1 of each DIMM is an EVEN row + // i865: NOTE: 4 KB = 32 Kb = 2^15 + row_attributes |= (page_size.side1 - 15) << (i << 3); // Side 1 of each DIMM is an EVEN row + + if (sdram_width.side2 > 0) +// row_attributes |= (page_size.side2 - 14) << ((i << 3) + 4); // Side 2 is ODD + row_attributes |= (page_size.side2 - 15) << ((i << 3) + 4); // Side 2 is ODD +// else +// row_attributes |= 7 << ((i << 3) + 4); // "not populated", i865 doesn't have that bit + + /* on the asrock pi465gv (rev g/a 1.11), + physical ram slots "DDR2" and "DDR1" + are logically slots 2 and 1 (or 1 and 0) */ +// printk(BIOS_DEBUG, "DRA%d: 0x%x\n", i, row_attributes); +// printk(BIOS_DEBUG, "DRA: row %d,%d: 0x%x\n", i, i + 1, row_attributes); + printk(BIOS_DEBUG, "DRA: row %d,%d: 0x%x\n", i * 2, i * 2 + 1, row_attributes); + MCHBAR8(DRA + i) = row_attributes; + + /* go to the next DIMM */ + } + +// PRINTK_DEBUG("DRA: %04x\n", row_attributes); + + /* Write the new row attributes register */ +// pci_write_config16(NORTHBRIDGE_MMC, DRA, row_attributes); +} + +static void spd_set_dram_controller_mode(uint8_t dimm_mask) +{ + int i; + + // Initial settings +// u32 controller_mode = pci_read_config32(NORTHBRIDGE_MMC, DRC); + u32 controller_mode = MCHBAR32(DRC); +// u32 system_refresh_mode = (controller_mode >> 7) & 7; + u32 system_refresh_mode = (controller_mode >> 8) & 7; // i865: RMS is at bits 10:8 + +// controller_mode |= (1 << 20); // ECC +// controller_mode |= (1 << 15); // RAS lockout +// controller_mode |= (1 << 12); // Address Tri-state enable (ADRTRIEN), FIXME: how is this detected????? +// controller_mode |= (2 << 10); // FIXME: Undocumented, really needed????? + +// for (i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { + u8 dimm = DIMM0 + i; + uint32_t dimm_refresh_mode; + int value; +// u8 tRCD, tRP; + + if (!(dimm_mask & (1 << i))) { + continue; // This DIMM not usable + } + + // Disable ECC mode if any one of the DIMMs does not support ECC +// no ECC on i865, disabling +// value = spd_read_byte(dimm, SPD_DIMM_CONFIG_TYPE); +// die_on_spd_error(value); +// if (value != ERROR_SCHEME_ECC) +// controller_mode &= ~(3 << 20); + + value = spd_read_byte(dimm, SPD_REFRESH); + die_on_spd_error(value); + value &= 0x7f; // Mask off self-refresh bit + if (value > MAX_SPD_REFRESH_RATE) { + print_err("unsupported refresh rate\n"); + continue; + } + // Get the appropriate i855 refresh mode for this DIMM + dimm_refresh_mode = refresh_rate_map[value]; + if (dimm_refresh_mode > 7) { + print_err("unsupported refresh rate\n"); + continue; + } + // If this DIMM requires more frequent refresh than others, + // update the system setting + if (refresh_frequency[dimm_refresh_mode] > + refresh_frequency[system_refresh_mode]) + system_refresh_mode = dimm_refresh_mode; + + /* FIXME: is this correct? */ +// tRCD = spd_read_byte(dimm, SPD_tRCD); +// tRP = spd_read_byte(dimm, SPD_tRP); +// no RAS lockout on i865 +// if (tRCD != tRP) { +// PRINTK_DEBUG(" Disabling RAS lockouk due to tRCD (%d) != tRP (%d)\n", tRCD, tRP); +// printk(BIOS_DEBUG, " Disabling RAS lockouk due to tRCD (%d) != tRP (%d)\n", tRCD, tRP); +// controller_mode &= ~(1 << 15); +// } + + /* go to the next DIMM */ + } + +// controller_mode &= ~(7 << 7); +// controller_mode |= (system_refresh_mode << 7); + controller_mode &= ~(7 << 8); + controller_mode |= (system_refresh_mode << 8); +// PRINTK_DEBUG("DRC: %08x\n", controller_mode); + printk(BIOS_DEBUG, "DRC: %08x\n", controller_mode); + +// pci_write_config32(NORTHBRIDGE_MMC, DRC, controller_mode); + MCHBAR32(DRC) = controller_mode; +} + +static void spd_set_dram_timing(uint8_t dimm_mask) +{ + int i; + u32 dram_timing; + + // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format + // NOTE: i82822 supports only 2.0 and 2.5 +// uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; + +/* SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5 | SPD_CAS_LATENCY_3_0 == 0x1c */ + uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5 | SPD_CAS_LATENCY_3_0; +// uint32_t system_compatible_cas_latencies = DRT_CAS_2_0 | DRT_CAS_2_5 | DRT_CAS_3_0; + uint8_t slowest_row_precharge = 0; + uint8_t slowest_ras_cas_delay = 0; + uint8_t slowest_active_to_precharge_delay = 0; + +// for (i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { + u8 dimm = DIMM0 + i; + int value; + uint32_t current_cas_latency; + uint32_t dimm_compatible_cas_latencies; + if (!(dimm_mask & (1 << i))) + continue; // This DIMM not usable + + value = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); + printk(BIOS_DEBUG, "SPD_ACCEPTABLE_CAS_LATENCIES: %d\n", value); + die_on_spd_error(value); + + dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM + printk(BIOS_DEBUG, "dimm_compatible_cas_latencies #1: %d\n", dimm_compatible_cas_latencies); + + current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM + printk(BIOS_DEBUG, "current_cas_latency: %d\n", current_cas_latency); + + // Can we support the highest CAS# latency? + value = spd_read_byte(dimm, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); + die_on_spd_error(value); + printk(BIOS_DEBUG, "SPD_MIN_CYCLE_TIME_AT_CAS_MAX: %d.%d\n", value >> 4, value & 0xf); + + // NOTE: At 133 MHz, 1 clock == 7.52 ns + if (value > 0x75) { + // Our bus is too fast for this CAS# latency + // Remove it from the bitmask of those supported by the DIMM that are compatible + dimm_compatible_cas_latencies &= ~current_cas_latency; + printk(BIOS_DEBUG, "dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies); + } + // Can we support the next-highest CAS# latency (max - 0.5)? + + current_cas_latency >>= 1; + if (current_cas_latency != 0) { + value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND); + die_on_spd_error(value); + printk(BIOS_DEBUG, "SPD_SDRAM_CYCLE_TIME_2ND: %d.%d\n", value >> 4, value & 0xf); + if (value > 0x75) { + dimm_compatible_cas_latencies &= ~current_cas_latency; + printk(BIOS_DEBUG, "dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies); + } + } + // Can we support the next-highest CAS# latency (max - 1.0)? + current_cas_latency >>= 1; + if (current_cas_latency != 0) { + value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD); + printk(BIOS_DEBUG, "SPD_SDRAM_CYCLE_TIME_3RD: %d.%d\n", value >> 4, value & 0xf); + die_on_spd_error(value); + if (value > 0x75) { + dimm_compatible_cas_latencies &= ~current_cas_latency; + printk(BIOS_DEBUG, "dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies); + } + } + // Restrict the system to CAS# latencies compatible with this DIMM + system_compatible_cas_latencies &= dimm_compatible_cas_latencies; + + value = spd_read_byte(dimm, SPD_MIN_ROW_PRECHARGE_TIME); + die_on_spd_error(value); + if (value > slowest_row_precharge) + slowest_row_precharge = value; + + value = spd_read_byte(dimm, SPD_MIN_RAS_TO_CAS_DELAY); + die_on_spd_error(value); + if (value > slowest_ras_cas_delay) + slowest_ras_cas_delay = value; + + value = spd_read_byte(dimm, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); + die_on_spd_error(value); + if (value > slowest_active_to_precharge_delay) + slowest_active_to_precharge_delay = value; + + /* go to the next DIMM */ + } + printk(BIOS_DEBUG, "CAS latency: %d\n", system_compatible_cas_latencies); + +// dram_timing = pci_read_config32(NORTHBRIDGE_MMC, DRT); + dram_timing = MCHBAR32(DRT); +// dram_timing &= ~(DRT_CAS_MASK | DRT_TRP_MASK | DRT_RCD_MASK); + dram_timing &= ~(DRT_CAS_MASK | DRT_TRP_MASK | DRT_TRCD_MASK); + printk(BIOS_DEBUG, "DRT: %08x\n", dram_timing); + + if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { + dram_timing |= DRT_CAS_2_0; + } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { + dram_timing |= DRT_CAS_2_5; + } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_3_0) { + dram_timing |= DRT_CAS_3_0; + } else + die("No CAS# latencies compatible with all DIMMs!!\n"); + +// uint32_t current_cas_latency = dram_timing & DRT_CAS_MASK; + + /* tRP */ + + printk(BIOS_DEBUG, "slowest_row_precharge: %d.%d\n", slowest_row_precharge >> 2, slowest_row_precharge & 0x3); + // i855 supports only 2, 3 or 4 clocks for tRP + if (slowest_row_precharge > (30 << 2)) // 30 = 11110b = tRCD = 2 dram clocks, tCL = reserved + die("unsupported DIMM tRP"); // > 30.0 ns: 5 or more clocks + else if (slowest_row_precharge > ( (22 << 2) | (2 << 0) )) + // 22 = 10110b = tRCD = 2 dram clocks, tCL = 2 + // 2 = 10b = 2 dram clocks (tRP) + dram_timing |= DRT_TRP_4; // > 22.5 ns: 4 or more clocks + else if (slowest_row_precharge > (15 << 2)) // 15 = 1111b = tRCD = reserved, tCL = 2 + dram_timing |= DRT_TRP_3; // > 15.0 ns: 3 clocks + else + dram_timing |= DRT_TRP_2; // <= 15.0 ns: 2 clocks + + /* tRCD */ + + printk(BIOS_DEBUG, "slowest_ras_cas_delay: %d.%d\n", slowest_ras_cas_delay >> 2, slowest_ras_cas_delay & 0x3); + // i855 supports only 2, 3 or 4 clocks for tRCD + if (slowest_ras_cas_delay > ((30 << 2))) + die("unsupported DIMM tRCD"); // > 30.0 ns: 5 or more clocks + else if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) +// dram_timing |= DRT_RCD_4; // > 22.5 ns: 4 or more clocks + dram_timing |= DRT_TRCD_4; // > 22.5 ns: 4 or more clocks + else if (slowest_ras_cas_delay > (15 << 2)) +// dram_timing |= DRT_RCD_3; // > 15.0 ns: 3 clocks + dram_timing |= DRT_TRCD_3; // > 15.0 ns: 3 clocks + else +// dram_timing |= DRT_RCD_2; // <= 15.0 ns: 2 clocks + dram_timing |= DRT_TRCD_2; // <= 15.0 ns: 2 clocks + + /* tRAS, min */ + + printk(BIOS_DEBUG, "slowest_active_to_precharge_delay: %d\n", slowest_active_to_precharge_delay); + // i855 supports only 5, 6, 7 or 8 clocks for tRAS + // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns, 8 clocks ~= 60.1 ns + // TODO + if (slowest_active_to_precharge_delay > 60) + die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks + else if (slowest_active_to_precharge_delay > 52) + dram_timing |= DRT_TRAS_MIN_8; // 46-52 ns: 7 clocks + else if (slowest_active_to_precharge_delay > 45) + dram_timing |= DRT_TRAS_MIN_7; // 46-52 ns: 7 clocks + else if (slowest_active_to_precharge_delay > 37) + dram_timing |= DRT_TRAS_MIN_6; // 38-45 ns: 6 clocks + else + dram_timing |= DRT_TRAS_MIN_5; // < 38 ns: 5 clocks + + /* FIXME: guess work starts here... + * + * Intel refers to DQ turn-arround values for back to calculate the values, + * but i have no idea what this means + */ + + /* + * Back to Back Read-Write command spacing (DDR, different Rows/Bank) + */ + /* Set to a 3 clock back to back read to write turn around. + * 2 is a good delay if the CAS latency is 2.0 */ +// dram_timing &= ~(3 << 28); +// if (current_cas_latency == DRT_CAS_2_0) +// dram_timing |= (2 << 28); // 2 clocks +// else +// dram_timing |= (1 << 28); // 3 clocks + + /* + * Back to Back Read-Write command spacing (DDR, same or different Rows/Bank) + */ +// dram_timing &= ~(3 << 26); +// if (current_cas_latency == DRT_CAS_2_0) +// dram_timing |= (2 << 26); // 5 clocks +// else +// dram_timing |= (1 << 26); // 6 clocks + + /* + * Back To Back Read-Read commands spacing (DDR, different Rows): + */ +// dram_timing &= ~(1 << 25); +// dram_timing |= (1 << 25); // 3 clocks + + printk(BIOS_DEBUG, "DRT: %08x\n", dram_timing); +// pci_write_config32(NORTHBRIDGE_MMC, DRT, dram_timing); + MCHBAR32(DRT) = dram_timing; +} + +static void spd_set_dram_size(uint8_t dimm_mask) +{ + int i; + int total_dram = 0; + uint32_t drb_reg = 0; + +// for (i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { + u8 dimm = DIMM0 + i; + struct dimm_size sz; + + if (!(dimm_mask & (1 << i))) { + /* fill values even for not present DIMMs */ +// drb_reg |= (total_dram << (i * 16)); +// drb_reg |= (total_dram << ((i * 16) + 8)); + drb_reg |= (total_dram << (i * 32)); + drb_reg |= (total_dram << ((i * 32) + 8)); + + continue; // This DIMM not usable + } + sz = spd_get_dimm_size(dimm); + +// total_dram += (1 << (sz.side1 - 28)); +// drb_reg |= (total_dram << (i * 16)); + total_dram += (1 << (sz.side1 - 30)); + drb_reg |= (total_dram << (i * 32)); + +// total_dram += (1 << (sz.side2 - 28)); +// drb_reg |= (total_dram << ((i * 16) + 8)); + total_dram += (1 << (sz.side2 - 30)); + drb_reg |= (total_dram << ((i * 32) + 8)); + + printk(BIOS_DEBUG, "DRB: %08x\n", drb_reg); + MCHBAR8(DRB + i) = drb_reg; + } +// printk(BIOS_DEBUG, "DRB: %08x\n", drb_reg); +// pci_write_config32(NORTHBRIDGE_MMC, DRB, drb_reg); +} + +static void enable_refresh(void) +{ + printk(BIOS_DEBUG, "Enabling refresh (RAM_COMMAND_REFRESH)\n"); + MCHBAR32(DRC) |= RAM_COMMAND_REFRESH << 8; +} + +/* from src/northbridge/intel/i945/raminit.c and util/inteltool/memory.c */ +static void sdram_dump_mchbar_registers(void) +{ + int i; + + printk(BIOS_DEBUG, "Dumping MCHBAR registers:\n"); + for (i = 0; i < 0xffff; i += 4) { + if ( (MCHBAR32(i) == 0) || (MCHBAR32(i) == 0xffffffff) ) + continue; + switch (i) { + case (DRB + 0): + printk(BIOS_DEBUG, " DRB0: 0x%x\n", MCHBAR32(i)); + case (DRB + 1): + printk(BIOS_DEBUG, " DRB1: 0x%x\n", MCHBAR32(i)); + case (DRB + 2): + printk(BIOS_DEBUG, " DRB2: 0x%x\n", MCHBAR32(i)); + case (DRB + 3): + printk(BIOS_DEBUG, " DRB3: 0x%x\n", MCHBAR32(i)); + case (DRB + 4): + printk(BIOS_DEBUG, " DRB4: 0x%x\n", MCHBAR32(i)); + case (DRB + 5): + printk(BIOS_DEBUG, " DRB5: 0x%x\n", MCHBAR32(i)); + case (DRB + 6): + printk(BIOS_DEBUG, " DRB6: 0x%x\n", MCHBAR32(i)); + case (DRB + 7): + printk(BIOS_DEBUG, " DRB7: 0x%x\n", MCHBAR32(i)); + + case (DRA + 0): + printk(BIOS_DEBUG, " DRA0: 0x%x\n", MCHBAR32(i)); + case (DRA + 1): + printk(BIOS_DEBUG, " DRA1: 0x%x\n", MCHBAR32(i)); + case (DRA + 2): + printk(BIOS_DEBUG, " DRA2: 0x%x\n", MCHBAR32(i)); + case (DRA + 3): + printk(BIOS_DEBUG, " DRA3: 0x%x\n", MCHBAR32(i)); + case (DRA + 4): + printk(BIOS_DEBUG, " DRA4: 0x%x\n", MCHBAR32(i)); + case (DRA + 5): + printk(BIOS_DEBUG, " DRA5: 0x%x\n", MCHBAR32(i)); + case (DRA + 6): + printk(BIOS_DEBUG, " DRA6: 0x%x\n", MCHBAR32(i)); + case (DRA + 7): + printk(BIOS_DEBUG, " DRA7: 0x%x\n", MCHBAR32(i)); + + case DRT: + printk(BIOS_DEBUG, " DRT: 0x%x\n", MCHBAR32(i)); + case DRC: + printk(BIOS_DEBUG, " DRC: 0x%x\n", MCHBAR32(i)); + default: + printk(BIOS_DEBUG, "0x%x: 0x%x\n", i, MCHBAR32(i)); + } + } +} + +static void early_northbridge_set_registers(void) +{ + u8 reg8; + + /* Undocumented register */ + reg8 = pci_read_config8(NORTHBRIDGE, 0xf4); + + /* + Writing 0x2 to northbridge register 0xf4 + exposes the PCI registers of device 6. + */ + //reg8 |= 0x2; /* guesswork: the default value is 0x0 */ + reg8 = 0x2; + + printk(BIOS_DEBUG, "Enabling access to (the registers of) device 6\n"); + pci_write_config8(NORTHBRIDGE, 0xf4, reg8); + + printk(BIOS_DEBUG, "Configuring BAR6 as 0x%x\n", DEFAULT_MCHBAR); + pci_write_config32(NORTHBRIDGE_MMC, BAR6, DEFAULT_MCHBAR); + + printk(BIOS_DEBUG, "Enabling Memory Access Enable (MAE) in PCICMD6\n"); + pci_write_config16(NORTHBRIDGE_MMC, PCICMD6, 0x2); +} + +static void northbridge_set_pam(void) +{ + printk(BIOS_DEBUG, "Configuring PAM0..PAM6\n"); + pci_write_config8(NORTHBRIDGE, PAM0, 0x10); + pci_write_config8(NORTHBRIDGE, PAM1, 0x11); + pci_write_config8(NORTHBRIDGE, PAM2, 0x1); + pci_write_config8(NORTHBRIDGE, PAM3, 0x0); + pci_write_config8(NORTHBRIDGE, PAM4, 0x0); + pci_write_config8(NORTHBRIDGE, PAM5, 0x33); + pci_write_config8(NORTHBRIDGE, PAM6, 0x33); +} + +static void northbridge_set_registers(void) +{ + printk(BIOS_DEBUG, "Configuring APBASE\n"); + pci_write_config32(NORTHBRIDGE, APBASE, 0xfe800008); + + printk(BIOS_DEBUG, "Configuring APSIZE\n"); + pci_write_config8(NORTHBRIDGE, APSIZE, 0x3f); + + printk(BIOS_DEBUG, "Configuring GC\n"); /* IVD=0, IGDIS=0, GMS=8 megabyte */ + pci_write_config8(NORTHBRIDGE, GC, 0x34); + + printk(BIOS_DEBUG, "Configuring AMTT\n"); + pci_write_config8(NORTHBRIDGE, AMTT, 0x20); + + printk(BIOS_DEBUG, "Configuring LPTT\n"); + pci_write_config8(NORTHBRIDGE, LPTT, 0x10); + + printk(BIOS_DEBUG, "Configuring GMCHCFG\n"); + pci_write_config16(NORTHBRIDGE, GMCHCFG, 0x40d); + + printk(BIOS_DEBUG, "Configuring TOUD\n"); + pci_write_config16(NORTHBRIDGE, TOUD, 0x1f80); + + printk(BIOS_DEBUG, "Configuring PCISTS\n"); + pci_write_config16(NORTHBRIDGE, PCISTS, 0x2009); + + printk(BIOS_DEBUG, "Writing SVID and SID\n"); + pci_write_config16(NORTHBRIDGE, SVID, 0x1849); + pci_write_config16(NORTHBRIDGE, SID, 0x2570); + + printk(BIOS_DEBUG, "Configuring ERRSTS\n"); + pci_write_config16(NORTHBRIDGE, ERRSTS, 0x100); +} + +static void northbridge_set_undocumented_registers(void) +{ + u8 reg8; + + printk(BIOS_DEBUG, "Configuring undocumented register 0x54\n"); + /* + guesswork, the default value is 0x18 and 0x1c is the value from lspci -nnvvvxxx. + conclusion: add 0x4 */ + reg8 = pci_read_config8(NORTHBRIDGE, 0x54); + reg8 |= 0x4; + pci_write_config8(NORTHBRIDGE, 0x54, reg8); + + printk(BIOS_DEBUG, "Configuring undocumented register 0x9d\n"); + reg8 = pci_read_config8(NORTHBRIDGE, 0xc9d); + reg8 |= 0x8; + pci_write_config8(NORTHBRIDGE, 0x9d, reg8); +} + +//static void hardcoded_initialization(void) +//{ + // int i; + +// printk(BIOS_DEBUG, "Configuring DRT\n"); +// MCHBAR32(DRT) = 0x56e40d00; /* single-channel, 512MB in the first (physical) slot */ +// printk(BIOS_DEBUG, " DRT after configuring (should be 0x56e40d00): 0x%x\n", MCHBAR32(DRT)); + +// printk(BIOS_DEBUG, "Configuring DRB0..DRB7\n"); + + /* single-channel, 512MB in the first (physical) slot */ +// MCHBAR8(DRB + 0) = 0x4; +// MCHBAR8(DRB + 1) = 0x8; +// MCHBAR8(DRB + 2) = 0x8; +// MCHBAR8(DRB + 3) = 0x8; +// MCHBAR8(DRB + 4) = 0x8; +// MCHBAR8(DRB + 5) = 0x8; +// MCHBAR8(DRB + 6) = 0x8; +// MCHBAR8(DRB + 7) = 0x8; + // for (i = 0; i < 8; i++) { + // printk(BIOS_DEBUG, " DRB%i after configuring (should be 0x4 for DRB0, 0x8 for DRB1-7): 0x%x\n", i, MCHBAR8(DRB + i)); + // } + +// printk(BIOS_DEBUG, "Configuring DRA0..DRA7\n"); + + /* single-channel, 512MB in the first (physical) slot */ +// MCHBAR8(DRA + 0) = 0x0; +// MCHBAR8(DRA + 1) = 0x11; // 8 kilobyte on each row +// MCHBAR8(DRA + 2) = 0x0; +// MCHBAR8(DRA + 3) = 0x0; + // for (i = 0; i < 8; i++) { + // printk(BIOS_DEBUG, " DRA%i after configuring (should be 0x0 for DRA0, DRA2 and DRA3, 0x11 for DRA1: 0x%x\n", + // i, MCHBAR8(DRA + i)); + // } + + // BAR6_32(DRC) = 0x20104271; + + // printk(BIOS_DEBUG, "All aboard the undocumented registers train :(\n"); + +/* + MCHBAR32(0x6c) = 0xa801; + MCHBAR32(0xb0) = 0x40830; + MCHBAR32(0x100) = 0x89b; + MCHBAR32(0x104) = 0x4ad; + MCHBAR32(0x130) = 0x88d; + MCHBAR32(0x138) = 0x210843c; + MCHBAR32(0x140) = 0x1721c; + MCHBAR32(0x144) = 0xe380fff; + MCHBAR32(0x170) = 0x1a00018b; + MCHBAR32(0x1a0) = 0x3d0524fd; + MCHBAR32(0x200) = 0x1; + MCHBAR32(0x208) = 0x3937; + MCHBAR32(0x300) = 0x32; + MCHBAR32(0x800) = 0xdddddddd; +*/ + // sdram_dump_mchbar_registers(); // from i945 +//} + +static void sdram_initialize(void) +//void sdram_initialize(void) +{ + /* First things first. */ + early_northbridge_set_registers(); + + uint8_t dimm_mask; + + printk(BIOS_DEBUG, "Reading SPD data...\n"); + dimm_mask = spd_get_supported_dimms(); + + if (dimm_mask == 0) { + printk(BIOS_DEBUG, "No usable memory for this controller\n"); + } + else { + printk(BIOS_DEBUG, "DIMM mask: 0x%x\n", dimm_mask); + + spd_set_row_attributes(dimm_mask); // done? + spd_set_dram_controller_mode(dimm_mask); // TODO + spd_set_dram_timing(dimm_mask); // TODO: tRAS + spd_set_dram_size(dimm_mask); // TODO + } + + sdram_enable(); + + enable_refresh(); + + set_initialization_complete(); + + /* Setup Initial Northbridge Registers */ + northbridge_set_pam(); + northbridge_set_registers(); + northbridge_set_undocumented_registers(); + + sdram_dump_mchbar_registers(); + + printk(BIOS_DEBUG, "Northbridge following SDRAM init:\n"); + + dump_pci_device(NORTHBRIDGE); + dump_pci_device(NORTHBRIDGE_MMC); +// dump_pci_device(PCI_DEV(0, 0x1e, 0)); +// dump_pci_device(PCI_DEV(0, 0x1f, 0)); +// dump_pci_device(PCI_DEV(0, 0x1f, 3)); +} diff --git a/src/northbridge/intel/i865/raminit.h b/src/northbridge/intel/i865/raminit.h new file mode 100644 index 0000000..bf47053 --- /dev/null +++ b/src/northbridge/intel/i865/raminit.h @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Jon Dufresne + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// #ifndef NORTHBRIDGE_INTEL_I865_RAMINIT_H +// #define NORTHBRIDGE_INTEL_I865_RAMINIT_H +#ifndef RAMINIT_H +#define RAMINIT_H + +#define DIMM_SOCKETS 4 + +/* i865 Northbridge PCI devices */ +#define NORTHBRIDGE PCI_DEV(0, 0, 0) +#define NORTHBRIDGE_MMC PCI_DEV(0, 6, 0) // Overflow device + +/*----------------------------------------------------------------------------- +Macros and definitions: +-----------------------------------------------------------------------------*/ +//#define VALIDATE_DIMM_COMPATIBILITY + +#define delay() udelay(200) + +/* should dispose of this. */ +// burst length can be 4 or 8 in single-channel or 8 in dual-channel +// interleaved bursts versus sequential bursts.. no idea about the capabilities of i865, so I left it out +//#define VG86X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5) +//#define VG86X_MODE (SDRAM_BURST_4 | SDRAM_CAS_3) // SDRAM_CAS_* == tCL? +#define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5) + +/* Main Memory Control */ +#define DEFAULT_MCHBAR 0xfecf0000 /* ? KB */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +//#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) // unused +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +/* Memory mapped registers */ +#define DRB 0x0 /* DRAM Row 0-7 Boundary */ +#define DRA 0x10 /* DRAM Row 0-7 Attribute */ +#define DRT 0x60 /* DRAM Timing */ +#define DRC 0x68 /* DRAM Controller Mode */ + +/* Northbridge (device 0) */ +#define PAM0 0x90 /* Programmable Attribute Map #0 */ +#define PAM1 0x91 /* Programmable Attribute Map #1 */ +#define PAM2 0x92 /* Programmable Attribute Map #2 */ +#define PAM3 0x93 /* Programmable Attribute Map #3 */ +#define PAM4 0x94 /* Programmable Attribute Map #4 */ +#define PAM5 0x95 /* Programmable Attribute Map #5 */ +#define PAM6 0x96 /* Programmable Attribute Map #6 */ + +/* DRC[29] - Initialization Complete (IC) */ +//#define RAM_COMMAND_IC 0x1 +//#define DRC_DONE (RAM_COMMAND_IC << 29) +#define RAM_INITIALIZATION_COMPLETE (1 << 29) + +/* DRC[22:21] - Number of Channels (CHAN) */ +// TODO: rename to DRC_*_CHANNEL_* ? +#define RAM_SINGLE_CHANNEL 0x0 +#define RAM_DUAL_CHANNEL_LINEAR 0x1 +#define RAM_DUAL_CHANNEL_TILEAR 0x2 + +/* DRC[10:8] - Refresh Mode Select (RMS) + * 0x1 for Refresh interval 15.6 us + * 0x2 for Refresh interval 7.8 us + * 0x3 for Refresh interval 64 usec + * 0x7 for Refresh interval 64 Clocks. (Fast Refresh Mode) + */ +// TODO: rename to DRC_RMS_* ? +// #define RAM_RMS_15_6 0x1 /* usec */ +// #define RAM_RMS_7_8 0x2 /* usec */ +// #define RAM_RMS_64 0x3 /* usec */ +// #define RAM_RMS_FAST 0x7 /* clocks */ +#define RAM_COMMAND_REFRESH 0x1 + +/* DRC[6:4] - Mode Select (SMS) */ +// TODO: mask? +// TODO: rename to DRC_SMS_* ? +#define RAM_COMMAND_POST_RESET 0x0 +#define RAM_COMMAND_NOP 0x1 +#define RAM_COMMAND_PRECHARGE 0x2 +#define RAM_COMMAND_MRS 0x3 +#define RAM_COMMAND_EMRS 0x4 +#define RAM_COMMAND_CBR 0x6 +#define RAM_COMMAND_NORMAL 0x7 + +/* Activate to Precharge delay (tRAS) */ +#define DRT_TRAS_MAX_70 (1 << 10) +#define DRT_TRAS_MAX_120 (0 << 10) +#define DRT_TRAS_MIN_MASK (5 << 7) // conflicts with DRT_TRAS_MIN_5 +#define DRT_TRAS_MIN_10 (0 << 7) +#define DRT_TRAS_MIN_9 (1 << 7) +#define DRT_TRAS_MIN_8 (2 << 7) +#define DRT_TRAS_MIN_7 (3 << 7) +#define DRT_TRAS_MIN_6 (4 << 7) +#define DRT_TRAS_MIN_5 (5 << 7) + +/* CAS# latency (tCL) */ +#define DRT_TCL_MASK (3 << 5) +#define DRT_TCL_2_0 (1 << 5) +#define DRT_TCL_2_5 (0 << 5) +#define DRT_TCL_3_0 (2 << 5) + +/* DRAM RAS# to CAS delay (tRCD) */ +#define DRT_TRCD_MASK (3 << 2) +#define DRT_TRCD_4 (0 << 2) +#define DRT_TRCD_3 (1 << 2) +#define DRT_TRCD_2 (2 << 2) + +/* DRAM RAS# precharge (tRP) */ +#define DRT_TRP_MASK 3 +#define DRT_TRP_4 0 +#define DRT_TRP_3 1 +#define DRT_TRP_2 2 + +// moved from i855.h +#define DRT_CAS_MASK (3 << 5) +#define DRT_CAS_2_0 (1 << 5) +#define DRT_CAS_2_5 (0 << 5) +#define DRT_CAS_3_0 (2 << 5) + +struct sys_info { // copied from i945, not yet used + u16 memory_frequency; /* 400, 533 or 667 */ + u16 fsb_frequency; /* 400, 533 or 667 */ + + u8 trp; /* calculated by sdram_detect_smallest_tRP() */ + u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */ + u8 tras; /* calculated by sdram_detect_smallest_tRAS() */ + // u8 trfc; /* calculated by sdram_detect_smallest_tRFC() */ + // u8 twr; /* calculated by sdram_detect_smallest_tWR() */ + + u8 cas; /* 3, 4 or 5 */ + u8 refresh; /* 0 = 15.6us, 1 = 7.8us */ + + u8 dual_channel; /* 0 or 1 */ + u8 interleaved; + + // u8 mvco4x; /* 0 (8x) or 1 (4x) */ + // u8 clkcfg_bit7; + // u8 boot_path; +// #define BOOT_PATH_NORMAL 0 +// #define BOOT_PATH_RESET 1 +// #define BOOT_PATH_RESUME 2 + + // u8 package; /* 0 = planar, 1 = stacked */ +// #define SYSINFO_PACKAGE_PLANAR 0x00 +// #define SYSINFO_PACKAGE_STACKED 0x01 + u8 dimm[2 * DIMM_SOCKETS]; +#define SYSINFO_DIMM_X16DS 0x00 +#define SYSINFO_DIMM_X8DS 0x01 +#define SYSINFO_DIMM_X16SS 0x02 +#define SYSINFO_DIMM_X8DDS 0x03 +#define SYSINFO_DIMM_NOT_POPULATED 0x04 + + u8 banks[2 * DIMM_SOCKETS]; + + u8 banksize[2 * 2 * DIMM_SOCKETS]; + const u8 *spd_addresses; + +} __attribute__ ((packed)); + + +//void sdram_initialize(void); + +#endif /* NORTHBRIDGE_INTEL_I865_RAMINIT_H */ diff --git a/src/northbridge/intel/i865/reset_test.c b/src/northbridge/intel/i865/reset_test.c new file mode 100644 index 0000000..c465c53 --- /dev/null +++ b/src/northbridge/intel/i865/reset_test.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Jon Dufresne + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "raminit.h" + + /* If I have already booted once skip a bunch of initialization */ + /* To see if I have already booted I check to see if memory + * has been enabled. + */ +static int bios_reset_detected(void) +{ + uint32_t dword; + + dword = BAR6_32(DRC); + + if( (dword & DRC_DONE) != 0 ) { + return 1; + } + + return 0; +} diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index cdf1f62..1c67c51 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -1,6 +1,6 @@ #include "smbus.h" -#define SMBUS_IO_BASE 0x0f00 +//#define SMBUS_IO_BASE 0x0f00 static void enable_smbus(void) { @@ -9,7 +9,7 @@ static void enable_smbus(void) print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - print_debug_hex32(pci_read_config32(dev, 0x20)); + printk(BIOS_DEBUG, "SMB_BASE = 0x%x\n", pci_read_config32(dev, SMB_BASE)); /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); /* Set smbus iospace enable */ diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h index f330c0a..0fa6b84 100644 --- a/src/southbridge/intel/i82801ex/smbus.h +++ b/src/southbridge/intel/i82801ex/smbus.h @@ -1,5 +1,8 @@ #include +#define SMBUS_IO_BASE 0x400 +#define SMB_BASE 0x20 + #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3 diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 559e982..a54139f 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -45,3 +45,14 @@ static void inline w83627thg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +static void w83627thg_set_clksel_48(device_t dev) +{ + u8 reg8; + + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} From gerrit at coreboot.org Sat Nov 5 18:09:17 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Sat, 5 Nov 2011 18:09:17 +0100 Subject: [coreboot] Patch set updated for coreboot: f9cf7e3 Add code to set the clock speed for Winbond W83627THF/THG. References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/411 -gerrit commit f9cf7e33e64fe399a77aff25b105132cf90990ab Author: Idwer Vollering Date: Sat Nov 5 18:08:08 2011 +0100 Add code to set the clock speed for Winbond W83627THF/THG. Change-Id: If92d96d117683cc59081061d5ac93aa23cb87327 Signed-off-by: Idwer Vollering --- src/cpu/intel/model_f2x/Kconfig | 3 + src/cpu/intel/model_f2x/Makefile.inc | 1 + src/cpu/intel/model_f2x/cache_as_ram.inc | 376 ++++++++++ src/cpu/intel/socket_mPGA478/Kconfig | 1 + src/cpu/intel/socket_mPGA478/Makefile.inc | 2 +- src/include/device/pci_ids.h | 6 +- src/mainboard/asrock/Kconfig | 5 +- src/mainboard/asrock/p4i65gv/Kconfig | 53 ++ src/mainboard/asrock/p4i65gv/Makefile.inc | 1 + src/mainboard/asrock/p4i65gv/chip.h | 22 + src/mainboard/asrock/p4i65gv/devicetree.cb | 49 ++ src/mainboard/asrock/p4i65gv/irq_tables.c | 63 ++ src/mainboard/asrock/p4i65gv/mainboard.c | 26 + src/mainboard/asrock/p4i65gv/romstage.c | 84 +++ src/mainboard/asrock/p4i65gv/rtl8139.c | 46 ++ src/mainboard/asrock/p4i65gv/watchdog.c | 36 + src/mainboard/asus/Kconfig | 4 +- src/mainboard/asus/p4p800-vm/Kconfig | 53 ++ src/mainboard/asus/p4p800-vm/Makefile.inc | 1 + src/mainboard/asus/p4p800-vm/chip.h | 22 + src/mainboard/asus/p4p800-vm/devicetree.cb | 49 ++ src/mainboard/asus/p4p800-vm/e100.c | 46 ++ src/mainboard/asus/p4p800-vm/irq_tables.c | 63 ++ src/mainboard/asus/p4p800-vm/mainboard.c | 26 + src/mainboard/asus/p4p800-vm/romstage.c | 84 +++ src/mainboard/asus/p4p800-vm/watchdog.c | 36 + src/northbridge/intel/Kconfig | 1 + src/northbridge/intel/Makefile.inc | 1 + src/northbridge/intel/i865/Kconfig | 25 + src/northbridge/intel/i865/Makefile.inc | 2 + src/northbridge/intel/i865/TODO | 16 + src/northbridge/intel/i865/chip.h | 25 + src/northbridge/intel/i865/debug.c | 139 ++++ src/northbridge/intel/i865/i865.h | 89 +++ src/northbridge/intel/i865/northbridge.c | 171 +++++ src/northbridge/intel/i865/raminit.c | 1031 ++++++++++++++++++++++++++ src/northbridge/intel/i865/raminit.h | 181 +++++ src/northbridge/intel/i865/reset_test.c | 38 + src/southbridge/intel/i82801ex/early_smbus.c | 4 +- src/southbridge/intel/i82801ex/smbus.h | 3 + src/superio/winbond/w83627thg/early_serial.c | 11 + 41 files changed, 2888 insertions(+), 7 deletions(-) diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 50cac79..ca57343 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,3 +1,6 @@ config CPU_INTEL_MODEL_F2X bool select SMP + select MMX + select SSE + select CACHE_AS_RAM diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index c393343..d4ddb7b 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1 +1,2 @@ +cpu_incs += $(src)/cpu/intel/model_f2x/cache_as_ram.inc driver-y += model_f2x_init.c diff --git a/src/cpu/intel/model_f2x/cache_as_ram.inc b/src/cpu/intel/model_f2x/cache_as_ram.inc new file mode 100644 index 0000000..7742a68 --- /dev/null +++ b/src/cpu/intel/model_f2x/cache_as_ram.inc @@ -0,0 +1,376 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000, 2007 Ronald G. Minnich + * Copyright (C) 2005 Eswar Nallusamy, LANL + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2007 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +#define CacheSize CONFIG_DCACHE_RAM_SIZE +#define CacheBase (0xd0000 - CacheSize) + + /* Save the BIST result. */ + movl %eax, %ebp + +CacheAsRam: + /* Check whether the processor has HT capability. */ + movl $01, %eax + cpuid + btl $28, %edx + jnc NotHtProcessor + bswapl %ebx + cmpb $01, %bh + jbe NotHtProcessor + + /* + * It is a HT processor. Send SIPI to the other logical processor + * within this processor so that the CAR related common system + * registers are programmed accordingly. + */ + + /* + * Use some register that is common to both logical processors + * as semaphore. Refer Appendix B, Vol.3. + */ + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRfix64K_00000_MSR, %ecx + wrmsr + + /* + * Figure out the logical AP's APIC ID; the following logic will + * work only for processors with 2 threads. + * Refer to Vol 3. Table 7-1 for details about this logic. + */ + movl $0xFEE00020, %esi + movl (%esi), %ebx + andl $0xFF000000, %ebx + bswapl %ebx + btl $0, %ebx + jnc LogicalAP0 + andb $0xFE, %bl + jmp Send_SIPI +LogicalAP0: + orb $0x01, %bl +Send_SIPI: + bswapl %ebx /* EBX - logical AP's APIC ID. */ + + /* + * Fill up the IPI command registers in the Local APIC mapped to + * default address and issue SIPI to the other logical processor + * within this processor die. + */ +Retry_SIPI: + movl %ebx, %eax + movl $0xFEE00310, %esi + movl %eax, (%esi) + + /* SIPI vector - F900:0000 */ + movl $0x000006F9, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + movl $0x30, %ecx +SIPI_Delay: + pause + decl %ecx + jnz SIPI_Delay + + movl (%esi), %eax + andl $0x00001000, %eax + jnz Retry_SIPI + + /* Wait for the Logical AP to complete initialization. */ +LogicalAP_SIPINotdone: + movl $MTRRfix64K_00000_MSR, %ecx + rdmsr + orl %eax, %eax + jz LogicalAP_SIPINotdone + +NotHtProcessor: + /* Set the default memory type and enable fixed and variable MTRRs. */ + movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax + wrmsr + + /* Clear all MTRRs. */ + xorl %edx, %edx + movl $all_mtrr_msrs, %esi + +clear_fixed_var_mtrr: + lodsl (%esi), %eax + testl %eax, %eax + jz clear_fixed_var_mtrr_out + + movl %eax, %ecx + xorl %eax, %eax + wrmsr + + jmp clear_fixed_var_mtrr + +all_mtrr_msrs: + /* fixed MTRR MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var MTRR MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) + + .long 0x000 /* NULL, end of table */ + +clear_fixed_var_mtrr_out: + +/* + * 0x06 is the WB IO type for a given 4k segment. + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* + * The xorl here is superfluous because at the point of first execution + * of this macro, %eax and %edx are cleared. Later invocations of this + * macro will have a monotonically increasing segs parameter. + */ + xorl \reg, \reg +.elseif \segs == 1 + movl $0x06000000, \reg /* WB IO type */ +.elseif \segs == 2 + movl $0x06060000, \reg /* WB IO type */ +.elseif \segs == 3 + movl $0x06060600, \reg /* WB IO type */ +.elseif \segs >= 4 + movl $0x06060606, \reg /* WB IO type */ +.endif +.endm + +/* + * carsize is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size. + */ +.macro simplemask carsize, windowoffset + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + extractmask gas_bug_workaround, %eax + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + extractmask gas_bug_workaround, %edx + /* + * Without the gas bug workaround, the entire macro would consist + * only of the two lines below: + * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + */ +.endm + +#if CacheSize > 0x10000 +#error Invalid CAR size, must be at most 64k. +#endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif + +#if CacheSize > 0x8000 + /* Enable caching for 32K-64K using fixed MTRR. */ + movl $MTRRfix4K_C0000_MSR, %ecx + simplemask CacheSize, 0x8000 + wrmsr +#endif + + /* Enable caching for 0-32K using fixed MTRR. */ + movl $MTRRfix4K_C8000_MSR, %ecx + simplemask CacheSize, 0 + wrmsr + +#if CONFIG_XIP_ROM_SIZE + + /* + * Enable write base caching so we can do execute in place (XIP) + * on the flash ROM. + */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Read the range with lodsl. */ + movl $CacheBase, %esi + cld + movl $(CacheSize >> 2), %ecx + rep lodsl + + /* Clear the range. */ + movl $CacheBase, %edi + movl $(CacheSize >> 2), %ecx + xorl %eax, %eax + rep stosl + +#if 0 + /* Check the cache as ram. */ + movl $CacheBase, %esi + movl $(CacheSize >> 2), %ecx +.xin1: + movl %esi, %eax + movl %eax, (%esi) + decl %ecx + je .xout1 + add $4, %esi + jmp .xin1 +.xout1: + + movl $CacheBase, %esi + // movl $(CacheSize >> 2), %ecx + movl $4, %ecx +.xin1x: + movl %esi, %eax + + movl $0x4000, %edx + movb %ah, %al +.testx1: + outb %al, $0x80 + decl %edx + jnz .testx1 + + movl (%esi), %eax + cmpb 0xff, %al + je .xin2 /* Don't show. */ + + movl $0x4000, %edx +.testx2: + outb %al, $0x80 + decl %edx + jnz .testx2 + +.xin2: + decl %ecx + je .xout1x + add $4, %esi + jmp .xin1x +.xout1x: +#endif + + movl $(CacheBase + CacheSize - 4), %eax + movl %eax, %esp +lout: + /* Restore the BIST result. */ + movl %ebp, %eax + + /* We need to set EBP? No need. */ + movl %esp, %ebp + pushl %eax /* BIST */ + call main + + /* We don't need CAR from now on. */ + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + /* Clear sth. */ + movl $MTRRfix4K_C8000_MSR, %ecx + xorl %edx, %edx + xorl %eax, %eax + wrmsr + +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 + movl $MTRRfix4K_C0000_MSR, %ecx + wrmsr +#endif + + /* + * Set the default memory type and disable fixed + * and enable variable MTRRs. + */ + movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */ + wrmsr + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + diff --git a/src/cpu/intel/socket_mPGA478/Kconfig b/src/cpu/intel/socket_mPGA478/Kconfig index 8c447c9..c17780f 100644 --- a/src/cpu/intel/socket_mPGA478/Kconfig +++ b/src/cpu/intel/socket_mPGA478/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_SOCKET_MPGA478 bool select CPU_INTEL_MODEL_69X select CPU_INTEL_MODEL_6DX + select CPU_INTEL_MODEL_F2X diff --git a/src/cpu/intel/socket_mPGA478/Makefile.inc b/src/cpu/intel/socket_mPGA478/Makefile.inc index ba2f13c..c3742f3 100644 --- a/src/cpu/intel/socket_mPGA478/Makefile.inc +++ b/src/cpu/intel/socket_mPGA478/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += socket_mPGA478.c subdirs-y += ../model_69x subdirs-y += ../model_6dx +subdirs-y += ../model_f2x subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic @@ -8,4 +9,3 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading - diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d16f85e..37b5848 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2142,7 +2142,8 @@ #define PCI_DEVICE_ID_INTEL_82801DBM_EHCI 0x24cd /* Intel 82801EB (ICH5) */ -#define PCI_DEVICE_ID_INTEL_82801EB_LAN 0x1051 +#define PCI_DEVICE_ID_INTEL_82801EB_LAN1 0x1050 +#define PCI_DEVICE_ID_INTEL_82801EB_LAN2 0x1051 #define PCI_DEVICE_ID_INTEL_82801EB_PCI 0x244e #define PCI_DEVICE_ID_INTEL_82801EB_LPC 0x24d0 #define PCI_DEVICE_ID_INTEL_82801EB_SATA 0x24d1 @@ -2157,7 +2158,8 @@ #define PCI_DEVICE_ID_INTEL_82801EB_USB4 0x24de /* Intel 82801ER (ICH5R) */ -#define PCI_DEVICE_ID_INTEL_82801ER_LAN 0x1051 +#define PCI_DEVICE_ID_INTEL_82801ER_LAN1 0x1050 +#define PCI_DEVICE_ID_INTEL_82801ER_LAN2 0x1051 #define PCI_DEVICE_ID_INTEL_82801ER_PCI 0x244e #define PCI_DEVICE_ID_INTEL_82801ER_LPC 0x24d0 #define PCI_DEVICE_ID_INTEL_82801ER_USB1 0x24d2 diff --git a/src/mainboard/asrock/Kconfig b/src/mainboard/asrock/Kconfig index 1e4fff9..260f048 100644 --- a/src/mainboard/asrock/Kconfig +++ b/src/mainboard/asrock/Kconfig @@ -25,11 +25,14 @@ config BOARD_ASROCK_939A785GMH bool "939A785GMH/128M" config BOARD_ASROCK_E350M1 bool "E350M1" +config BOARD_ASROCK_P4I65GV + bool "P4i65GV" endchoice -source "src/mainboard/asrock/939a785gmh/Kconfig" +source "src/mainboard/asrock/939a785gmh/Kconfig" source "src/mainboard/asrock/e350m1/Kconfig" +source "src/mainboard/asrock/p4i65gv/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/asrock/p4i65gv/Kconfig b/src/mainboard/asrock/p4i65gv/Kconfig new file mode 100644 index 0000000..21e2b3d --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/Kconfig @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify it under the terms of the GNU General +## Public License as published by the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the +## implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along with this program; if not, write to +## the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +if BOARD_ASROCK_P4I65GV + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA478 + select NORTHBRIDGE_INTEL_I865 + select SOUTHBRIDGE_INTEL_I82801EX + select SUPERIO_WINBOND_W83627HF + select HAVE_HARD_RESET +# select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + select USE_WATCHDOG_ON_BOOT +# select HAVE_ACPI_TABLES +# select CACHE_AS_RAM # inherited from the socket option + +config MAINBOARD_DIR + string + default asrock/p4i65gv + +config MAINBOARD_PART_NUMBER + string + default "P4i65GV" + +config DCACHE_RAM_BASE + hex + default 0xfff00000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 # ok? + +config IRQ_SLOT_COUNT + int + default 6 # no idea + +endif # BOARD_ASROCK_P4I65GV diff --git a/src/mainboard/asrock/p4i65gv/Makefile.inc b/src/mainboard/asrock/p4i65gv/Makefile.inc new file mode 100644 index 0000000..03e044d --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/Makefile.inc @@ -0,0 +1 @@ +driver-y += rtl8139.c diff --git a/src/mainboard/asrock/p4i65gv/chip.h b/src/mainboard/asrock/p4i65gv/chip.h new file mode 100644 index 0000000..e77b136 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asrock/p4i65gv/devicetree.cb b/src/mainboard/asrock/p4i65gv/devicetree.cb new file mode 100644 index 0000000..992463c --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/devicetree.cb @@ -0,0 +1,49 @@ +chip northbridge/intel/i865 + device lapic_cluster 0 on + chip cpu/intel/socket_mPGA478 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 0.0 on end # northbridge + device pci 0.1 off end # agp + device pci 0.2 on end # igd + device pnp 0.3 off end # csa + device pci 0.6 on end # overflow device + + chip southbridge/intel/i82801ex + device pci 1d.0 on end # uhci #1 + device pci 1d.1 on end # uhci #2 + device pci 1d.2 on end # uhci #3 + device pci 1d.3 on end # uhci #4 + device pci 1d.7 on end # ehci + device pci 1e.0 on # pci bridge + # 01:05.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10) + device pci 05.0 on end + end + + device pci 1f.0 on # lpc bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off end # floppy + device pnp 2e.1 off end # parallel + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end # com1 + device pnp 2e.3 off end # com2 + device pnp 2e.5 on end # keyboard + device pnp 2e.6 off end # ir + device pnp 2e.7 on end # game/gpio 1 + device pnp 2e.8 on end # gpio 2 + device pnp 2e.9 on end # gpio 3 + device pnp 2e.a on end # acpi + device pnp 2e.b on end # hardware monitor + end # superio + end # 1f.0 + device pci 1f.1 on end # pata + device pci 1f.2 on end # sata + device pci 1f.3 on end # smbus + device pci 1f.5 off end # ac97 + end # southbridge + end # pci_domain +end # northbridge diff --git a/src/mainboard/asrock/p4i65gv/irq_tables.c b/src/mainboard/asrock/p4i65gv/irq_tables.c new file mode 100644 index 0000000..240ab23 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/irq_tables.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 200x TODO + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef GETPIR /* TODO: Drop this when copying to coreboot. */ +#include "pirq_routing.h" /* TODO: Drop this when copying to coreboot. */ +#else /* TODO: Drop this when copying to coreboot. */ +#include +#endif /* TODO: Drop this when copying to coreboot. */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 13, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x24d0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3e, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x01, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x6b, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{0x00, 0x0000}, {0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x01, (0x03 << 3) | 0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}}, 0x1, 0x0}, + {0x01, (0x01 << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x2, 0x0}, + {0x01, (0x02 << 3) | 0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x3, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}}, 0x4, 0x0}, + {0x01, (0x04 << 3) | 0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x01, (0x0a << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x6, 0x0}, + {0x01, (0x05 << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/asrock/p4i65gv/mainboard.c b/src/mainboard/asrock/p4i65gv/mainboard.c new file mode 100644 index 0000000..78aec29 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASRock P4i65GV Mainboard") +}; diff --git a/src/mainboard/asrock/p4i65gv/romstage.c b/src/mainboard/asrock/p4i65gv/romstage.c new file mode 100644 index 0000000..7f70ca0 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/romstage.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pc80/udelay_io.c" +//#include "lib/delay.c" +#include "cpu/x86/bist.h" + +//#include "southbridge/intel/i82801ex/i82801ex.h" +#include "southbridge/intel/i82801ex/early_smbus.c" +#include "northbridge/intel/i865/debug.c" +#include "northbridge/intel/i865/raminit.c" +//#include "northbridge/intel/i865/reset_test.c" +#include "northbridge/intel/i865/i865.h" +#include "superio/winbond/w83627hf/early_serial.c" +#include "watchdog.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +//int spd_read_byte(unsigned int device, unsigned int address) +//static inline int spd_read_byte(unsigned device, unsigned address) +//{ +// return smbus_read_byte(device, address); +//} + +void main(unsigned long bist) { + + // TODO + // copied from dell/s1850/romstage.c + /* + static const struct mem_controller memctrl[] = { + { + // node id? + .channel0 = { DIMM0, DIMM1, DIMM2, DIMM3, }, + .channel1 = { DIMM4, DIMM5, DIMM6, DIMM7, }, + } + }; +*/ + if (bist == 0) + enable_lapic(); + + w83627hf_set_clksel_48(SERIAL_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + report_bist_failure(bist); + +// if (!bios_reset_detected()) /* board doesn't boot when using bios_rest_detected() */ +// { + enable_smbus(); + dump_spd_registers(); + + disable_ich5_watchdog(); + + // TODO: dual-channel, e.g.: + // sdram_initialize(ARRAY_SIZE(memctrl), memctrl); // copied from dell/s1850/romstage.c + sdram_initialize(); +// } +} diff --git a/src/mainboard/asrock/p4i65gv/rtl8139.c b/src/mainboard/asrock/p4i65gv/rtl8139.c new file mode 100644 index 0000000..d909af7 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/rtl8139.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include +#include +#include +#include + +static void nic_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Initializing RTL8139 Fast Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. +} +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver rtl8139_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_REALTEK, + .device = PCI_DEVICE_ID_REALTEK_8139, +}; diff --git a/src/mainboard/asrock/p4i65gv/watchdog.c b/src/mainboard/asrock/p4i65gv/watchdog.c new file mode 100644 index 0000000..8c7b0f6 --- /dev/null +++ b/src/mainboard/asrock/p4i65gv/watchdog.c @@ -0,0 +1,36 @@ +/* copied and adapted from src/mainboard/dell/s1850/watchdog.c */ + +#define ICH5_WDBASE 0x800 /* PMBASE */ +#define ICH5_GPIOBASE 0x480 + +static void disable_ich5_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); /* LPC bridge */ + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); /* PCICMD */ + value |= (1 << 10); /* reserved? */ + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); /* PMBASE */ + pci_write_config8(dev, 0x44, 0x10); /* ACPI_CNTL = ACPI_EN */ + base = ICH5_WDBASE + 0x60; /* TCO offset, ich5 datasheet ch9.11 */ + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; /* enable TCO_TMR_HLT */ + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); /* TCO1_STS, raise bit 3: TIMEOUT */ + outw(0x0002, base + 0x06); /* TCO2_STS, raise bit 2: SECOND_TO_STS */ + + printk(BIOS_DEBUG, "Board-specific ICH5 watchdog disabled\n"); +} diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..1369a4b 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -55,7 +55,8 @@ config BOARD_ASUS_P2B_LS bool "P2B-LS" config BOARD_ASUS_P3B_F bool "P3B-F" - +config BOARD_ASUS_P4P800_VM + bool "P4P800-VM" endchoice source "src/mainboard/asus/a8n_e/Kconfig" @@ -75,6 +76,7 @@ source "src/mainboard/asus/p2b-ds/Kconfig" source "src/mainboard/asus/p2b-f/Kconfig" source "src/mainboard/asus/p2b-ls/Kconfig" source "src/mainboard/asus/p3b-f/Kconfig" +source "src/mainboard/asus/p4p800-vm/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/asus/p4p800-vm/Kconfig b/src/mainboard/asus/p4p800-vm/Kconfig new file mode 100644 index 0000000..ef93089 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/Kconfig @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify it under the terms of the GNU General +## Public License as published by the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the +## implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along with this program; if not, write to +## the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +if BOARD_ASUS_P4P800_VM + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA478 + select NORTHBRIDGE_INTEL_I865 + select SOUTHBRIDGE_INTEL_I82801EX + select SUPERIO_WINBOND_W83627THG + select HAVE_HARD_RESET +# select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + select USE_WATCHDOG_ON_BOOT +# select HAVE_ACPI_TABLES +# select CACHE_AS_RAM # inherited from the socket option + +config MAINBOARD_DIR + string + default asus/p4p800-vm + +config MAINBOARD_PART_NUMBER + string + default "P4P800-VM" + +config DCACHE_RAM_BASE + hex + default 0xfff00000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 # ok? + +config IRQ_SLOT_COUNT + int + default 6 # no idea + +endif # BOARD_ASUS_P4P800_VM diff --git a/src/mainboard/asus/p4p800-vm/Makefile.inc b/src/mainboard/asus/p4p800-vm/Makefile.inc new file mode 100644 index 0000000..93aefe9 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/Makefile.inc @@ -0,0 +1 @@ +driver-y += e100.c diff --git a/src/mainboard/asus/p4p800-vm/chip.h b/src/mainboard/asus/p4p800-vm/chip.h new file mode 100644 index 0000000..e77b136 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/p4p800-vm/devicetree.cb b/src/mainboard/asus/p4p800-vm/devicetree.cb new file mode 100644 index 0000000..cf80f53 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/devicetree.cb @@ -0,0 +1,49 @@ +chip northbridge/intel/i865 + device lapic_cluster 0 on + chip cpu/intel/socket_mPGA478 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 0.0 on end # northbridge + device pci 0.1 off end # agp + device pci 0.2 on end # igd + device pnp 0.3 off end # csa + device pci 0.6 on end # overflow device + + chip southbridge/intel/i82801ex + device pci 1d.0 on end # uhci #1 + device pci 1d.1 on end # uhci #2 + device pci 1d.2 on end # uhci #3 + device pci 1d.3 on end # uhci #4 + device pci 1d.7 on end # ehci + device pci 1e.0 on # pci bridge + # 01:08.0 Ethernet controller: Intel Corporation 82562EZ 10/100 Ethernet Controller (rev 02) + device pci 08.0 on end + end + + device pci 1f.0 on # lpc bridge + chip superio/winbond/w83627thg + device pnp 2e.0 off end # floppy + device pnp 2e.1 off end # parallel + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end # com1 + device pnp 2e.3 off end # com2 + device pnp 2e.5 on end # keyboard + device pnp 2e.6 off end # ir + device pnp 2e.7 on end # game/gpio 1 + device pnp 2e.8 on end # gpio 2 + device pnp 2e.9 on end # gpio 3 + device pnp 2e.a on end # acpi + device pnp 2e.b on end # hardware monitor + end # superio + end # 1f.0 + device pci 1f.1 on end # pata + device pci 1f.2 on end # sata + device pci 1f.3 on end # smbus + device pci 1f.5 off end # ac97 + end # southbridge + end # pci_domain +end # northbridge diff --git a/src/mainboard/asus/p4p800-vm/e100.c b/src/mainboard/asus/p4p800-vm/e100.c new file mode 100644 index 0000000..d3c0e07 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/e100.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include +#include +#include +#include + +static void nic_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Initializing Intel 82562EZ 10/100 Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. +} +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver intel_e100_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_LAN1, /* 8086:1050 */ +}; diff --git a/src/mainboard/asus/p4p800-vm/irq_tables.c b/src/mainboard/asus/p4p800-vm/irq_tables.c new file mode 100644 index 0000000..240ab23 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/irq_tables.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 200x TODO + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef GETPIR /* TODO: Drop this when copying to coreboot. */ +#include "pirq_routing.h" /* TODO: Drop this when copying to coreboot. */ +#else /* TODO: Drop this when copying to coreboot. */ +#include +#endif /* TODO: Drop this when copying to coreboot. */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 13, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x24d0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3e, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x01, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x6b, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{0x00, 0x0000}, {0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x01, (0x03 << 3) | 0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}}, 0x1, 0x0}, + {0x01, (0x01 << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x2, 0x0}, + {0x01, (0x02 << 3) | 0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x3, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}}, 0x4, 0x0}, + {0x01, (0x04 << 3) | 0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x01, (0x0a << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x6, 0x0}, + {0x01, (0x05 << 3) | 0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/asus/p4p800-vm/mainboard.c b/src/mainboard/asus/p4p800-vm/mainboard.c new file mode 100644 index 0000000..5b47989 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS P4P800-VM Mainboard") +}; diff --git a/src/mainboard/asus/p4p800-vm/romstage.c b/src/mainboard/asus/p4p800-vm/romstage.c new file mode 100644 index 0000000..fad3aca --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/romstage.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pc80/udelay_io.c" +//#include "lib/delay.c" +#include "cpu/x86/bist.h" + +//#include "southbridge/intel/i82801ex/i82801ex.h" +#include "southbridge/intel/i82801ex/early_smbus.c" +#include "northbridge/intel/i865/debug.c" +#include "northbridge/intel/i865/raminit.c" +//#include "northbridge/intel/i865/reset_test.c" +#include "northbridge/intel/i865/i865.h" +#include "superio/winbond/w83627thg/early_serial.c" +#include "watchdog.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +//int spd_read_byte(unsigned int device, unsigned int address) +//static inline int spd_read_byte(unsigned device, unsigned address) +//{ +// return smbus_read_byte(device, address); +//} + +void main(unsigned long bist) { + + // TODO + // copied from dell/s1850/romstage.c + /* + static const struct mem_controller memctrl[] = { + { + // node id? + .channel0 = { DIMM0, DIMM1, DIMM2, DIMM3, }, + .channel1 = { DIMM4, DIMM5, DIMM6, DIMM7, }, + } + }; +*/ + if (bist == 0) + enable_lapic(); + + w83627thg_set_clksel_48(SERIAL_DEV); + w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + report_bist_failure(bist); + +// if (!bios_reset_detected()) /* board doesn't boot when using bios_rest_detected() */ +// { + enable_smbus(); + dump_spd_registers(); + + disable_ich5_watchdog(); + + // TODO: dual-channel, e.g.: + // sdram_initialize(ARRAY_SIZE(memctrl), memctrl); // copied from dell/s1850/romstage.c + sdram_initialize(); +// } +} diff --git a/src/mainboard/asus/p4p800-vm/watchdog.c b/src/mainboard/asus/p4p800-vm/watchdog.c new file mode 100644 index 0000000..8c7b0f6 --- /dev/null +++ b/src/mainboard/asus/p4p800-vm/watchdog.c @@ -0,0 +1,36 @@ +/* copied and adapted from src/mainboard/dell/s1850/watchdog.c */ + +#define ICH5_WDBASE 0x800 /* PMBASE */ +#define ICH5_GPIOBASE 0x480 + +static void disable_ich5_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); /* LPC bridge */ + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); /* PCICMD */ + value |= (1 << 10); /* reserved? */ + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); /* PMBASE */ + pci_write_config8(dev, 0x44, 0x10); /* ACPI_CNTL = ACPI_EN */ + base = ICH5_WDBASE + 0x60; /* TCO offset, ich5 datasheet ch9.11 */ + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; /* enable TCO_TMR_HLT */ + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); /* TCO1_STS, raise bit 3: TIMEOUT */ + outw(0x0002, base + 0x06); /* TCO2_STS, raise bit 2: SECOND_TO_STS */ + + printk(BIOS_DEBUG, "Board-specific ICH5 watchdog disabled\n"); +} diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 1809d11..e5c8ed5 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -8,5 +8,6 @@ source src/northbridge/intel/i440lx/Kconfig source src/northbridge/intel/i82810/Kconfig source src/northbridge/intel/i82830/Kconfig source src/northbridge/intel/i855/Kconfig +source src/northbridge/intel/i865/Kconfig source src/northbridge/intel/i945/Kconfig source src/northbridge/intel/sch/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 0d116d0..9d333b6 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -8,6 +8,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440LX) += i440lx subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I865) += i865 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch diff --git a/src/northbridge/intel/i865/Kconfig b/src/northbridge/intel/i865/Kconfig new file mode 100644 index 0000000..944f701 --- /dev/null +++ b/src/northbridge/intel/i865/Kconfig @@ -0,0 +1,25 @@ +config NORTHBRIDGE_INTEL_I865 + bool + select HAVE_DEBUG_RAM_SETUP +choice +prompt "Onboard graphics" + default I865_VIDEO_MB_8MB + depends on NORTHBRIDGE_INTEL_I865 + +config I865_VIDEO_MB_OFF + bool "Disabled, 0KB" +config I865_VIDEO_MB_1MB + bool "Enabled, 1MB" +config I865_VIDEO_MB_8MB + bool "Enabled, 8MB" +config I865_VIDEO_MB_16MB + bool "Enabled, 16MB" +endchoice + +config VIDEO_MB + int + default 0 if I865_VIDEO_MB_OFF + default 1 if I865_VIDEO_MB_1MB + default 8 if I865_VIDEO_MB_8MB + default 16 if I865_VIDEO_MB_16MB + depends on NORTHBRIDGE_INTEL_I865 diff --git a/src/northbridge/intel/i865/Makefile.inc b/src/northbridge/intel/i865/Makefile.inc new file mode 100644 index 0000000..8cec43f --- /dev/null +++ b/src/northbridge/intel/i865/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += northbridge.c +#romstage-y += early_init.c diff --git a/src/northbridge/intel/i865/TODO b/src/northbridge/intel/i865/TODO new file mode 100644 index 0000000..2f28af0 --- /dev/null +++ b/src/northbridge/intel/i865/TODO @@ -0,0 +1,16 @@ +TODO (probably incomplete) + +raminit.c: + * re-use the mchbar macro from i945 and read/write from/to it like its raminit code does + * GPL headers everywhere + * includes (is assert.h really needed?) + * set TOUD (from northbridge.c?) + * set SMFREQ and FSBFREQ (in GMCHCFG) (from northbridge.c?)? + * AGP (device 1) code + * VGA/IGD (device 2) code + * CSA (device 3) code? + * clean up/trim northbridge_set_registers() + * dual-channel code (and don't forget romstage.c) + +DONE +* raise bits 0 (IOAE, I/O access enable) and 1 (MAE, memory access enable) in PCICMD6 (from northbridge.c?) diff --git a/src/northbridge/intel/i865/chip.h b/src/northbridge/intel/i865/chip.h new file mode 100644 index 0000000..6e7b21e --- /dev/null +++ b/src/northbridge/intel/i865/chip.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Jon Dufresne + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_intel_i865_config +{ +}; + +extern struct chip_operations northbridge_intel_i865_ops; diff --git a/src/northbridge/intel/i865/debug.c b/src/northbridge/intel/i865/debug.c new file mode 100644 index 0000000..a7935ce --- /dev/null +++ b/src/northbridge/intel/i865/debug.c @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +static void print_debug_pci_dev(unsigned dev) { + print_debug("PCI: "); + print_debug_hex8((dev >> 20) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 15) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 12) & 0x07); +} +static inline void print_pci_devices(void) { + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\n"); + } +} +static void dump_pci_device(unsigned dev) { + int i; + print_debug_pci_dev(dev); + print_debug("\n"); + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} +static inline void dump_pci_devices(void) { + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} +static inline void dump_spd_registers(void) { + int i; + print_debug("\n"); + for(i = 0; i < 2; i++) { + unsigned device; + device = DIMM0 + i; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\n"); + } + } +} +static inline void dump_smbus_registers(void) { + int i; + print_debug("\n"); + for(i = 1; i < 0x80; i++) { + unsigned device; + device = i; + int j; + print_debug("smbus: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\n"); + } +} diff --git a/src/northbridge/intel/i865/i865.h b/src/northbridge/intel/i865/i865.h new file mode 100644 index 0000000..51cf0bc --- /dev/null +++ b/src/northbridge/intel/i865/i865.h @@ -0,0 +1,89 @@ +/* TODO: + * AGP #defines + * GPL header + */ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Travelping GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* size, default value */ +/* DRAM Controller (device 0) */ +#define APBASE 0x10 /* 32 bit, 0x8 */ +// #define AGPM 0x51 /* 8 bit, 0x0 */ +// #define ESMRAMC 0x9e /* 8 bit, 0x38 */ +// #define ACAPID 0xa0 /* 32bit, 0x300002 (RO) */ +// #define AGPSTAT 0xa4 /* 32bit, AGP 2.0: 0x1f004217 (RO) or AGP 3.0: 0x1f004a13 (RO) */ +// #define AGPCMD 0xa8 /* 32bit, AGP 2.0: 0x0 or AGP 3.0: 0xa00 */ +// #define AGPCTRL 0xb0 /* 32bit, 0x0 */ +#define AMTT 0xbc /* 8 bit, 0x10 */ +#define APSIZE 0xb4 /* 8 bit, 0x0 */ +// #define ATTBASE 0xb8 /* 32 bit, 0x0 */ +#define TOUD 0xc4 /* 16 bit, 0x400 */ +#define GMCHCFG 0xc6 /* 16 bit, 0x0 */ +#define ERRSTS 0xc8 /* 16 bit, 0x0 */ +// #define ERRCMD 0xca /* 16 bit, 0x0 */ +// #define FDHC 0x97 /* 8 bit, 0x0 */ +// #define FPLLCONT 0x60 /* 8 bit, 0x0 */ +#define GC 0x52 /* 8 bit (looks wrong), 0x1000 */ +#define LPTT 0xbd /* 8 bit, 0x10 */ +#define PCISTS 0x10 /* 16 bit, 0x90 */ +// #define SMRAM 0x9D /* 8 bit, 0x2 */ +#define SVID 0x2c /* 16 bit, 0x0 */ +#define SID 0x2e /* 16 bit, 0x0 */ +// #define CSABCONT 0x53 /* 8 bit, 0x0 */ +#define VID 0x0 /* 16 bit, 0x8086 */ +#define DID 0x2 /* 16 bit, 0x2570 */ +/* PCI-to-AGP bridge (device 1) */ +// #define PCICMD1 0x04 /* 16 bit, 0x0 */ +// #define SMLT1 0x0d /* 8 bit, 0x0 */ +// #define SBUSN1 0x19 /* 8 bit, 0x0 */ +// #define SUBUSN1 0x1a /* 8 bit, 0x0 */ +// #define PMBASE1 0x24 /* 16 bit, 0xfff0 */ +// #define PMLIMIT1 0x26 /* 16 bit, 0x0 */ +// #define BCTRL1 0x3e /* 8 bit, 0x0 */ +// #define ERRCMD1 0x40 /* 8 bit, 0x0 */ + +/* Integrated Graphics Device (device 2) */ +// #define PCICMD2 0x04 /* 16 bit, 0x0 */ +// #define GMADR 0x10 /* 32 bit, 0x8 */ +// #define MMADR 0x14 /* 32 bit, 0x0 */ +// #define IOBAR 0x18 /* 32 bit, 0x1 */ +// #define SVID2 0x2c /* 16 bit, 0x0 */ +// #define SID2 0x2e /* 16 bit, 0x0 */ +// #define INTRLINE 0x3c /* 8 bit, 0x0 */ +// #define PMCS 0xd4 /* 16 bit, 0x0 */ +// #define SWSMI 0xe0 /* 16 bit, 0x0 */ + +/* PCI-to-CSA bridge (device 3) */ +// #define PCICMD3 0x04 /* 16 bit, 0x0 */ +// #define IOBASE3 0x1c /* 8 bit, 0xf0 */ +// #define IOLIMIT3 0x1d /* 8 bit, 0x0 */ +// #define MBASE3 0x20 /* 16 bit, 0xfff0 */ +// #define MLIMIT3 0x22 /* 16 bit, 0x0 */ +// #define PMBASE3 0x24 /* 16 bit, 0xfff0 */ +// #define PMLIMIT3 0x26 /* 16 bit, 0x0 */ +// #define BCTRL3 0x3e /* 8 bit, 0x0 */ +// #define CSACNTRL 0x50 /* 32 bit, 0xe042802 */ + +/* Overflow device (device 6) */ +#define PCICMD6 0x04 /* 16 bit (looks wrong), 0x0 */ +#define BAR6 0x10 /* 32 bit, 0x0 */ +// #define SVID6 0x2c /* 16 bit, 0x0 */ +// #define SID6 0x2e /* 16 bit, 0x0 */ diff --git a/src/northbridge/intel/i865/northbridge.c b/src/northbridge/intel/i865/northbridge.c new file mode 100644 index 0000000..c249be3 --- /dev/null +++ b/src/northbridge/intel/i865/northbridge.c @@ -0,0 +1,171 @@ +/* TODO: + * CSA (device 3) code + * set all subsytem IDs (SID*, SVID*) + */ + + /* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Ronald G. Minnich + * Copyright (C) 2003-2004 Eric W. Biederman + * Copyright (C) 2006 Jon Dufresne + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "i865.h" +#include "raminit.h" + +static void northbridge_init(device_t dev) +{ + printk(BIOS_SPEW, "Northbridge init\n"); +} + +static struct device_operations northbridge_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2570, +}; + +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif +static void pci_domain_set_resources(device_t dev) +{ + device_t mc_dev; + uint32_t pci_tolm; + + printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); + printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device); + + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children->sibling; + printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor); + printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device); + + if (mc_dev) { + /* Figure out which areas are/should be occupied by RAM. + * This is all computed in kilobytes and converted to/from + * the memory controller right at the edges. + * Having different variables in different units is + * too confusing to get right. Kilobytes are good up to + * 4 Terabytes of RAM... + */ + unsigned long tomk, tolmk; + int idx; + + /* Get the value of the highest DRB. This tells the end of + * the physical memory. The units are ticks of 64 MB + * i.e. 1 means 64 MB. + */ + //tomk = (unsigned long)pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), DRB + 7); +// tomk = BAR6_8(DRB + 7); + tomk = MCHBAR8(DRB + 7); + tomk = tomk * 64 * 1024; + /* add vga_mem detection */ + tomk = tomk - 16 * 1024; // 16 MB, graphics mode select (GMS) + /* Compute the top of Low memory */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does not overlap memory + */ + tolmk = tomk; + } + /* Write the ram configuration registers, + * preserving the reserved bits. + */ + + /* Report the memory regions */ + printk(BIOS_DEBUG, "tomk = %ld\n", tomk); + printk(BIOS_DEBUG, "tolmk = %ld\n", tolmk); + + idx = 10; + /* avoid pam region */ + ram_resource(dev, idx++, 0, 640); + /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ + ram_resource(dev, idx++, 768, tolmk - 768); + +#if CONFIG_WRITE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif + } + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_i865_ops = { + CHIP_NAME("Intel 865 Northbridge") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/intel/i865/raminit.c b/src/northbridge/intel/i865/raminit.c new file mode 100644 index 0000000..91e3144 --- /dev/null +++ b/src/northbridge/intel/i865/raminit.c @@ -0,0 +1,1031 @@ +#include +#include +#include + +#include "i865.h" +#include "raminit.h" + +struct dimm_size { + unsigned int side1; + unsigned int side2; +}; + +static const uint32_t refresh_frequency[] = { + /* Relative frequency (array value) of each E7501 Refresh Mode Select + * (RMS) value (array index) + * 0 == least frequent refresh (longest interval between refreshes) + * [0] disabled -> 0 + * [1] 15.6 usec -> 2 + * [2] 7.8 usec -> 3 + * [3] 64 usec -> 1 + * [4] reserved -> 0 + * [5] reserved -> 0 + * [6] reserved -> 0 + * [7] 64 clocks -> 4 + */ + 0, 2, 3, 1, 0, 0, 0, 4 +}; + +static const uint32_t refresh_rate_map[] = { + /* Map the JEDEC spd refresh rates (array index) to i855 Refresh Mode + * Select values (array value) + * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 + * The i855 supports only 15.6 us (1), 7.8 us (2) and + * 64 clock (481 ns) (7) refresh. + * [0] == 15.625 us -> 15.6 us + * [1] == 3.9 us -> 481 ns + * [2] == 7.8 us -> 7.8 us + * [3] == 31.3 us -> 15.6 us + * [4] == 62.5 us -> 15.6 us + * [5] == 125 us -> 15.6 us + */ + 1, 7, 2, 1, 1, 1 +}; + +#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) + +static inline int spd_read_byte(unsigned device, unsigned address) +//static int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +static void set_initialization_complete(void) +{ + printk(BIOS_DEBUG, "Setting initialization complete (DRC bit 29)\n"); + MCHBAR32(DRC) |= RAM_INITIALIZATION_COMPLETE; +} + +//static void do_ram_command(u32 command) +static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) +{ + int i; + u32 reg32; +// uint8_t dimm_start_32M_multiple = 0; + uint8_t dimm_start_64M_multiple = 0; + uint16_t i855_mode_bits = jedec_mode_bits; + + /* Configure the RAM command. */ +// reg32 = pci_read_config32(NORTHBRIDGE_MMC, DRC); + reg32 = MCHBAR32(DRC); + reg32 &= ~(7 << 4); + reg32 |= (command << 4); + printk(BIOS_DEBUG, " Sending RAM command 0x%08x\n", reg32); +// pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32); + MCHBAR32(DRC) = reg32; + + // RAM_COMMAND_NORMAL is an exception. + // It affects only the memory controller and does not need to be "sent" to the DIMMs. + + if (command != RAM_COMMAND_NORMAL) { + + // Send the command to all DIMMs by accessing a memory location within each + // NOTE: for mode select commands, some of the location address bits + // are part of the command + + // Map JEDEC mode bits to i855 + if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) { + /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ + // i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9)); + /* Host address lines [13:3] map to DIMM address lines [5:1] */ + // i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (6 - 1)); + i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3f) << (6 - 1)); + } + + for (i = 0; i < (DIMM_SOCKETS * 2); ++i) { +// uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i); + /* i865 uses a granularity of 64 megabyte */ + uint8_t dimm_end_64M_multiple = MCHBAR8(DRB + i); +// if (dimm_end_32M_multiple > dimm_start_32M_multiple) { + if (dimm_end_64M_multiple > dimm_start_64M_multiple) { + +// uint32_t dimm_start_address = dimm_start_32M_multiple << 25; + uint32_t dimm_start_address = dimm_start_64M_multiple << 25; + printk(BIOS_DEBUG, " Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits); + //read32(dimm_start_address + i855_mode_bits); + printk(BIOS_DEBUG, " /* skipping read32() */\n"); + printk(BIOS_DEBUG, " Sent. dimm_start_address = 0x%x and i855_mode_bits = 0x%x\n", dimm_start_address, i855_mode_bits); + + // Set the start of the next DIMM +// dimm_start_32M_multiple = dimm_end_32M_multiple; + dimm_start_64M_multiple = dimm_end_64M_multiple; + } + } + } +} + +static void sdram_enable(void) +{ + int i; + + print_debug("Ram enable 1\n"); + delay(); + delay(); + + /* NOP command */ + printk(BIOS_DEBUG, " NOP\n"); + do_ram_command(RAM_COMMAND_NOP, 0); + delay(); + delay(); + delay(); + + /* Pre-charge all banks (at least 200 us after NOP) */ + printk(BIOS_DEBUG, " Pre-charging all banks\n"); + do_ram_command(RAM_COMMAND_PRECHARGE, 0); + delay(); + delay(); + delay(); + + printk(BIOS_DEBUG, "Ram enable 4\n"); + do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE); + delay(); + delay(); + delay(); + + print_debug("Ram enable 5\n"); + do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_DLL_RESET); + + print_debug("Ram enable 6\n"); + do_ram_command(RAM_COMMAND_PRECHARGE, 0); + delay(); + delay(); + delay(); + + /* 8 CBR refreshes (Auto Refresh) */ + printk(BIOS_DEBUG, " 8 CBR refreshes\n"); + for(i = 0; i < 8; i++) { + do_ram_command(RAM_COMMAND_CBR, 0); + delay(); + delay(); + delay(); + } + + printk(BIOS_DEBUG, "Ram enable 8\n"); + do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_NORMAL); + + /* Set GME-M Mode Select bits back to NORMAL operation mode */ + printk(BIOS_DEBUG, " Normal operation mode\n"); + do_ram_command(RAM_COMMAND_NORMAL, 0); +/* delay(); + delay(); + delay(); + + print_debug("Ram enable 9\n"); + set_initialize_complete(); + + delay(); + delay(); + delay(); + delay(); + delay(); + + print_debug("After configuration:\n"); +*/ + /* dump_pci_devices(); */ + + /* + print_debug("\n\n***** RAM TEST *****\n"); + ram_check(0, 0xa0000); + ram_check(0x100000, 0x40000000); + */ +} + +//static void ram_read32(u8 dimm_start, u32 offset) +//{ + /* not implemented */ +//} + +//static void initialize_dimm_rows(void) +//{ + /* copied from i82830/raminit.c */ + /* not implemented */ +//} + +static void die_on_spd_error(int spd_return_value) +{ + if (spd_return_value < 0) + printk(BIOS_DEBUG, "Error reading SPD info: got %d\n", spd_return_value); +/* + if (spd_return_value < 0) + die("Error reading SPD info\n"); +*/ +} + +static struct dimm_size sdram_spd_get_page_size(u8 dimm_socket_address) +{ + uint16_t module_data_width; + int value; + struct dimm_size pgsz; + + pgsz.side1 = 0; + pgsz.side2 = 0; + + // Side 1 + value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + die_on_spd_error(value); + + pgsz.side1 = value & 0xf; // # columns in bank 1 + + /* Get the module data width and convert it to a power of two */ + value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); + die_on_spd_error(value); + + module_data_width = (value & 0xff) << 8; + + value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); + die_on_spd_error(value); + + module_data_width |= (value & 0xff); + + pgsz.side1 += log2(module_data_width); + + /* side two */ + value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + die_on_spd_error(value); + + if (value > 2) + printk(BIOS_DEBUG, "Bad SPD value\n"); + + if (value == 2) { + pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently + value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + die_on_spd_error(value); + + if ((value & 0xf0) != 0) { + // Asymmetric banks + pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */ + pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */ + } + } + + return pgsz; +} + +/** + * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16). + * + * @param dimm_socket_address SMBus address of DIMM socket to interrogate. + * @return Width in bits of each DIMM side's DRAMs. + */ +static struct dimm_size sdram_spd_get_width(u8 dimm_socket_address) +{ + int value; + struct dimm_size width; + + width.side1 = 0; + width.side2 = 0; + + value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); + die_on_spd_error(value); + + width.side1 = value & 0x7f; // Mask off bank 2 flag + + if (value & 0x80) { + width.side2 = width.side1 << 1; // Bank 2 exists and is double-width + } else { + // If bank 2 exists, it's the same width as bank 1 + value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + die_on_spd_error(value); + + switch (value) { + case 2: + width.side2 = width.side1; + break; + + default: + break; + } + } + + return width; +} + +/** + * Calculate the log base 2 size in bits of both DIMM sides. + * + * log2(# bits) = (# columns) + log2(data width) + + * (# rows) + log2(banks per SDRAM) + * + * Note that it might be easier to use SPD byte 31 here, it has the DIMM size + * as a multiple of 4MB. The way we do it now we can size both sides of an + * asymmetric DIMM. + * + * @param dimm SMBus address of DIMM socket to interrogate. + * @return log2(number of bits) for each side of the DIMM. + */ +static struct dimm_size spd_get_dimm_size(unsigned dimm) +{ + int value; + + // Start with log2(page size) + struct dimm_size sz = sdram_spd_get_page_size(dimm); + + if (sz.side1 > 0) { + value = spd_read_byte(dimm, SPD_NUM_ROWS); + die_on_spd_error(value); + + sz.side1 += value & 0xf; + + if (sz.side2 > 0) { + // Double-sided DIMM + if (value & 0xF0) + sz.side2 += value >> 4; // Asymmetric + else + sz.side2 += value; // Symmetric + } + + value = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); + die_on_spd_error(value); + + value = log2(value); + sz.side1 += value; + if (sz.side2 > 0) + sz.side2 += value; + } + + return sz; +} + +// static void set_dram_row_boundaries(void) { /* TODO */ } +// static void set_dram_row_attributes(void) { /* TODO */ } +// static void set_dram_timing(void) { /* TODO */ } +// static void sdram_set_registers(void) { /* TODO */ } + +static uint8_t spd_get_supported_dimms(void) +{ + int i; + uint8_t dimm_mask = 0; + +// for (i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { + u8 dimm = DIMM0 + i; + + struct dimm_size page_size; + struct dimm_size sdram_width; + + int spd_value; + + if (dimm == 0) + continue; + + if (spd_read_byte(dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR) + // print a little warning, maybe? + continue; + + if ((spd_value = spd_read_byte(dimm, SPD_MODULE_VOLTAGE)) != SPD_VOLTAGE_SSTL2) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported voltage: %02x\n", spd_value); + continue; + } + + page_size = sdram_spd_get_page_size(dimm); + sdram_width = sdram_spd_get_width(dimm); + + // Validate DIMM page size + // The i855 only supports page sizes of 4, 8, 16 KB per channel + // NOTE: 4 KB = 32 Kb = 2^15 + // 16 KB = 128 Kb = 2^17 + + if ((page_size.side1 < 15) || (page_size.side1 > 17)) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported page size: %d\n", page_size.side1); + continue; + } + + // If DIMM is double-sided, verify side2 page size + if (page_size.side2 != 0) { + if ((page_size.side2 < 15) || (page_size.side2 > 17)) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported page size: %d\n", page_size.side2); + continue; + } + } + // Validate SDRAM width + // The i855 only supports x8 and x16 devices + if ((sdram_width.side1 != 8) && (sdram_width.side1 != 16)) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported width: %d\n", sdram_width.side2); + continue; + } + + // If DIMM is double-sided, verify side2 width + if (sdram_width.side2 != 0) { + if ((sdram_width.side2 != 8) + && (sdram_width.side2 != 16)) { + printk(BIOS_DEBUG, "Skipping DIMM with unsupported width: %d\n", sdram_width.side2); + continue; + } + } + // Made it through all the checks, this DIMM is usable + dimm_mask |= (1 << i); + } + + return dimm_mask; +} + +static void spd_set_row_attributes(uint8_t dimm_mask) +{ + int i; + uint16_t row_attributes = 0; + + for (i = 0; i < DIMM_SOCKETS; i++) { + u8 dimm = DIMM0 + i; + struct dimm_size page_size; + struct dimm_size sdram_width; + + if (!(dimm_mask & (1 << i))) { +// row_attributes |= 0x77 << (i << 3); + row_attributes |= 0x0 << (i << 3); // default value of DRA on i865 is 0x0 + continue; // This DIMM not usable + } + + // Get the relevant parameters via SPD + page_size = sdram_spd_get_page_size(dimm); + sdram_width = sdram_spd_get_width(dimm); + + // Update the DRAM Row Attributes. + // Page size is encoded as log2(page size in bits) - log2(2 KB) or 4 KB == 1, 8 KB == 3, 16KB == 3 +// i865: Page size is encoded as log2(page size in bits) - log2(2 KB) or 4 KB == 0, 8 KB == 1, 16KB == 2, 32KB == 3 + // NOTE: 2 KB = 16 Kb = 2^14 +// row_attributes |= (page_size.side1 - 14) << (i << 3); // Side 1 of each DIMM is an EVEN row + // i865: NOTE: 4 KB = 32 Kb = 2^15 + row_attributes |= (page_size.side1 - 15) << (i << 3); // Side 1 of each DIMM is an EVEN row + + if (sdram_width.side2 > 0) +// row_attributes |= (page_size.side2 - 14) << ((i << 3) + 4); // Side 2 is ODD + row_attributes |= (page_size.side2 - 15) << ((i << 3) + 4); // Side 2 is ODD +// else +// row_attributes |= 7 << ((i << 3) + 4); // "not populated", i865 doesn't have that bit + + /* on the asrock pi465gv (rev g/a 1.11), + physical ram slots "DDR2" and "DDR1" + are logically slots 2 and 1 (or 1 and 0) */ +// printk(BIOS_DEBUG, "DRA%d: 0x%x\n", i, row_attributes); +// printk(BIOS_DEBUG, "DRA: row %d,%d: 0x%x\n", i, i + 1, row_attributes); + printk(BIOS_DEBUG, "DRA: row %d,%d: 0x%x\n", i * 2, i * 2 + 1, row_attributes); + MCHBAR8(DRA + i) = row_attributes; + + /* go to the next DIMM */ + } + +// PRINTK_DEBUG("DRA: %04x\n", row_attributes); + + /* Write the new row attributes register */ +// pci_write_config16(NORTHBRIDGE_MMC, DRA, row_attributes); +} + +static void spd_set_dram_controller_mode(uint8_t dimm_mask) +{ + int i; + + // Initial settings +// u32 controller_mode = pci_read_config32(NORTHBRIDGE_MMC, DRC); + u32 controller_mode = MCHBAR32(DRC); +// u32 system_refresh_mode = (controller_mode >> 7) & 7; + u32 system_refresh_mode = (controller_mode >> 8) & 7; // i865: RMS is at bits 10:8 + +// controller_mode |= (1 << 20); // ECC +// controller_mode |= (1 << 15); // RAS lockout +// controller_mode |= (1 << 12); // Address Tri-state enable (ADRTRIEN), FIXME: how is this detected????? +// controller_mode |= (2 << 10); // FIXME: Undocumented, really needed????? + +// for (i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { + u8 dimm = DIMM0 + i; + uint32_t dimm_refresh_mode; + int value; +// u8 tRCD, tRP; + + if (!(dimm_mask & (1 << i))) { + continue; // This DIMM not usable + } + + // Disable ECC mode if any one of the DIMMs does not support ECC +// no ECC on i865, disabling +// value = spd_read_byte(dimm, SPD_DIMM_CONFIG_TYPE); +// die_on_spd_error(value); +// if (value != ERROR_SCHEME_ECC) +// controller_mode &= ~(3 << 20); + + value = spd_read_byte(dimm, SPD_REFRESH); + die_on_spd_error(value); + value &= 0x7f; // Mask off self-refresh bit + if (value > MAX_SPD_REFRESH_RATE) { + print_err("unsupported refresh rate\n"); + continue; + } + // Get the appropriate i855 refresh mode for this DIMM + dimm_refresh_mode = refresh_rate_map[value]; + if (dimm_refresh_mode > 7) { + print_err("unsupported refresh rate\n"); + continue; + } + // If this DIMM requires more frequent refresh than others, + // update the system setting + if (refresh_frequency[dimm_refresh_mode] > + refresh_frequency[system_refresh_mode]) + system_refresh_mode = dimm_refresh_mode; + + /* FIXME: is this correct? */ +// tRCD = spd_read_byte(dimm, SPD_tRCD); +// tRP = spd_read_byte(dimm, SPD_tRP); +// no RAS lockout on i865 +// if (tRCD != tRP) { +// PRINTK_DEBUG(" Disabling RAS lockouk due to tRCD (%d) != tRP (%d)\n", tRCD, tRP); +// printk(BIOS_DEBUG, " Disabling RAS lockouk due to tRCD (%d) != tRP (%d)\n", tRCD, tRP); +// controller_mode &= ~(1 << 15); +// } + + /* go to the next DIMM */ + } + +// controller_mode &= ~(7 << 7); +// controller_mode |= (system_refresh_mode << 7); + controller_mode &= ~(7 << 8); + controller_mode |= (system_refresh_mode << 8); +// PRINTK_DEBUG("DRC: %08x\n", controller_mode); + printk(BIOS_DEBUG, "DRC: %08x\n", controller_mode); + +// pci_write_config32(NORTHBRIDGE_MMC, DRC, controller_mode); + MCHBAR32(DRC) = controller_mode; +} + +static void spd_set_dram_timing(uint8_t dimm_mask) +{ + int i; + u32 dram_timing; + + // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format + // NOTE: i82822 supports only 2.0 and 2.5 +// uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; + +/* SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5 | SPD_CAS_LATENCY_3_0 == 0x1c */ + uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5 | SPD_CAS_LATENCY_3_0; +// uint32_t system_compatible_cas_latencies = DRT_CAS_2_0 | DRT_CAS_2_5 | DRT_CAS_3_0; + uint8_t slowest_row_precharge = 0; + uint8_t slowest_ras_cas_delay = 0; + uint8_t slowest_active_to_precharge_delay = 0; + +// for (i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { + u8 dimm = DIMM0 + i; + int value; + uint32_t current_cas_latency; + uint32_t dimm_compatible_cas_latencies; + if (!(dimm_mask & (1 << i))) + continue; // This DIMM not usable + + value = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); + printk(BIOS_DEBUG, "SPD_ACCEPTABLE_CAS_LATENCIES: %d\n", value); + die_on_spd_error(value); + + dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM + printk(BIOS_DEBUG, "dimm_compatible_cas_latencies #1: %d\n", dimm_compatible_cas_latencies); + + current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM + printk(BIOS_DEBUG, "current_cas_latency: %d\n", current_cas_latency); + + // Can we support the highest CAS# latency? + value = spd_read_byte(dimm, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); + die_on_spd_error(value); + printk(BIOS_DEBUG, "SPD_MIN_CYCLE_TIME_AT_CAS_MAX: %d.%d\n", value >> 4, value & 0xf); + + // NOTE: At 133 MHz, 1 clock == 7.52 ns + if (value > 0x75) { + // Our bus is too fast for this CAS# latency + // Remove it from the bitmask of those supported by the DIMM that are compatible + dimm_compatible_cas_latencies &= ~current_cas_latency; + printk(BIOS_DEBUG, "dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies); + } + // Can we support the next-highest CAS# latency (max - 0.5)? + + current_cas_latency >>= 1; + if (current_cas_latency != 0) { + value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND); + die_on_spd_error(value); + printk(BIOS_DEBUG, "SPD_SDRAM_CYCLE_TIME_2ND: %d.%d\n", value >> 4, value & 0xf); + if (value > 0x75) { + dimm_compatible_cas_latencies &= ~current_cas_latency; + printk(BIOS_DEBUG, "dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies); + } + } + // Can we support the next-highest CAS# latency (max - 1.0)? + current_cas_latency >>= 1; + if (current_cas_latency != 0) { + value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD); + printk(BIOS_DEBUG, "SPD_SDRAM_CYCLE_TIME_3RD: %d.%d\n", value >> 4, value & 0xf); + die_on_spd_error(value); + if (value > 0x75) { + dimm_compatible_cas_latencies &= ~current_cas_latency; + printk(BIOS_DEBUG, "dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies); + } + } + // Restrict the system to CAS# latencies compatible with this DIMM + system_compatible_cas_latencies &= dimm_compatible_cas_latencies; + + value = spd_read_byte(dimm, SPD_MIN_ROW_PRECHARGE_TIME); + die_on_spd_error(value); + if (value > slowest_row_precharge) + slowest_row_precharge = value; + + value = spd_read_byte(dimm, SPD_MIN_RAS_TO_CAS_DELAY); + die_on_spd_error(value); + if (value > slowest_ras_cas_delay) + slowest_ras_cas_delay = value; + + value = spd_read_byte(dimm, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); + die_on_spd_error(value); + if (value > slowest_active_to_precharge_delay) + slowest_active_to_precharge_delay = value; + + /* go to the next DIMM */ + } + printk(BIOS_DEBUG, "CAS latency: %d\n", system_compatible_cas_latencies); + +// dram_timing = pci_read_config32(NORTHBRIDGE_MMC, DRT); + dram_timing = MCHBAR32(DRT); +// dram_timing &= ~(DRT_CAS_MASK | DRT_TRP_MASK | DRT_RCD_MASK); + dram_timing &= ~(DRT_CAS_MASK | DRT_TRP_MASK | DRT_TRCD_MASK); + printk(BIOS_DEBUG, "DRT: %08x\n", dram_timing); + + if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { + dram_timing |= DRT_CAS_2_0; + } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { + dram_timing |= DRT_CAS_2_5; + } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_3_0) { + dram_timing |= DRT_CAS_3_0; + } else + die("No CAS# latencies compatible with all DIMMs!!\n"); + +// uint32_t current_cas_latency = dram_timing & DRT_CAS_MASK; + + /* tRP */ + + printk(BIOS_DEBUG, "slowest_row_precharge: %d.%d\n", slowest_row_precharge >> 2, slowest_row_precharge & 0x3); + // i855 supports only 2, 3 or 4 clocks for tRP + if (slowest_row_precharge > (30 << 2)) // 30 = 11110b = tRCD = 2 dram clocks, tCL = reserved + die("unsupported DIMM tRP"); // > 30.0 ns: 5 or more clocks + else if (slowest_row_precharge > ( (22 << 2) | (2 << 0) )) + // 22 = 10110b = tRCD = 2 dram clocks, tCL = 2 + // 2 = 10b = 2 dram clocks (tRP) + dram_timing |= DRT_TRP_4; // > 22.5 ns: 4 or more clocks + else if (slowest_row_precharge > (15 << 2)) // 15 = 1111b = tRCD = reserved, tCL = 2 + dram_timing |= DRT_TRP_3; // > 15.0 ns: 3 clocks + else + dram_timing |= DRT_TRP_2; // <= 15.0 ns: 2 clocks + + /* tRCD */ + + printk(BIOS_DEBUG, "slowest_ras_cas_delay: %d.%d\n", slowest_ras_cas_delay >> 2, slowest_ras_cas_delay & 0x3); + // i855 supports only 2, 3 or 4 clocks for tRCD + if (slowest_ras_cas_delay > ((30 << 2))) + die("unsupported DIMM tRCD"); // > 30.0 ns: 5 or more clocks + else if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) +// dram_timing |= DRT_RCD_4; // > 22.5 ns: 4 or more clocks + dram_timing |= DRT_TRCD_4; // > 22.5 ns: 4 or more clocks + else if (slowest_ras_cas_delay > (15 << 2)) +// dram_timing |= DRT_RCD_3; // > 15.0 ns: 3 clocks + dram_timing |= DRT_TRCD_3; // > 15.0 ns: 3 clocks + else +// dram_timing |= DRT_RCD_2; // <= 15.0 ns: 2 clocks + dram_timing |= DRT_TRCD_2; // <= 15.0 ns: 2 clocks + + /* tRAS, min */ + + printk(BIOS_DEBUG, "slowest_active_to_precharge_delay: %d\n", slowest_active_to_precharge_delay); + // i855 supports only 5, 6, 7 or 8 clocks for tRAS + // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns, 8 clocks ~= 60.1 ns + // TODO + if (slowest_active_to_precharge_delay > 60) + die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks + else if (slowest_active_to_precharge_delay > 52) + dram_timing |= DRT_TRAS_MIN_8; // 46-52 ns: 7 clocks + else if (slowest_active_to_precharge_delay > 45) + dram_timing |= DRT_TRAS_MIN_7; // 46-52 ns: 7 clocks + else if (slowest_active_to_precharge_delay > 37) + dram_timing |= DRT_TRAS_MIN_6; // 38-45 ns: 6 clocks + else + dram_timing |= DRT_TRAS_MIN_5; // < 38 ns: 5 clocks + + /* FIXME: guess work starts here... + * + * Intel refers to DQ turn-arround values for back to calculate the values, + * but i have no idea what this means + */ + + /* + * Back to Back Read-Write command spacing (DDR, different Rows/Bank) + */ + /* Set to a 3 clock back to back read to write turn around. + * 2 is a good delay if the CAS latency is 2.0 */ +// dram_timing &= ~(3 << 28); +// if (current_cas_latency == DRT_CAS_2_0) +// dram_timing |= (2 << 28); // 2 clocks +// else +// dram_timing |= (1 << 28); // 3 clocks + + /* + * Back to Back Read-Write command spacing (DDR, same or different Rows/Bank) + */ +// dram_timing &= ~(3 << 26); +// if (current_cas_latency == DRT_CAS_2_0) +// dram_timing |= (2 << 26); // 5 clocks +// else +// dram_timing |= (1 << 26); // 6 clocks + + /* + * Back To Back Read-Read commands spacing (DDR, different Rows): + */ +// dram_timing &= ~(1 << 25); +// dram_timing |= (1 << 25); // 3 clocks + + printk(BIOS_DEBUG, "DRT: %08x\n", dram_timing); +// pci_write_config32(NORTHBRIDGE_MMC, DRT, dram_timing); + MCHBAR32(DRT) = dram_timing; +} + +static void spd_set_dram_size(uint8_t dimm_mask) +{ + int i; + int total_dram = 0; + uint32_t drb_reg = 0; + +// for (i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { + u8 dimm = DIMM0 + i; + struct dimm_size sz; + + if (!(dimm_mask & (1 << i))) { + /* fill values even for not present DIMMs */ +// drb_reg |= (total_dram << (i * 16)); +// drb_reg |= (total_dram << ((i * 16) + 8)); + drb_reg |= (total_dram << (i * 32)); + drb_reg |= (total_dram << ((i * 32) + 8)); + + continue; // This DIMM not usable + } + sz = spd_get_dimm_size(dimm); + +// total_dram += (1 << (sz.side1 - 28)); +// drb_reg |= (total_dram << (i * 16)); + total_dram += (1 << (sz.side1 - 30)); + drb_reg |= (total_dram << (i * 32)); + +// total_dram += (1 << (sz.side2 - 28)); +// drb_reg |= (total_dram << ((i * 16) + 8)); + total_dram += (1 << (sz.side2 - 30)); + drb_reg |= (total_dram << ((i * 32) + 8)); + + printk(BIOS_DEBUG, "DRB: %08x\n", drb_reg); + MCHBAR8(DRB + i) = drb_reg; + } +// printk(BIOS_DEBUG, "DRB: %08x\n", drb_reg); +// pci_write_config32(NORTHBRIDGE_MMC, DRB, drb_reg); +} + +static void enable_refresh(void) +{ + printk(BIOS_DEBUG, "Enabling refresh (RAM_COMMAND_REFRESH)\n"); + MCHBAR32(DRC) |= RAM_COMMAND_REFRESH << 8; +} + +/* from src/northbridge/intel/i945/raminit.c and util/inteltool/memory.c */ +static void sdram_dump_mchbar_registers(void) +{ + int i; + + printk(BIOS_DEBUG, "Dumping MCHBAR registers:\n"); + for (i = 0; i < 0xffff; i += 4) { + if ( (MCHBAR32(i) == 0) || (MCHBAR32(i) == 0xffffffff) ) + continue; + switch (i) { + case (DRB + 0): + printk(BIOS_DEBUG, " DRB0: 0x%x\n", MCHBAR32(i)); + case (DRB + 1): + printk(BIOS_DEBUG, " DRB1: 0x%x\n", MCHBAR32(i)); + case (DRB + 2): + printk(BIOS_DEBUG, " DRB2: 0x%x\n", MCHBAR32(i)); + case (DRB + 3): + printk(BIOS_DEBUG, " DRB3: 0x%x\n", MCHBAR32(i)); + case (DRB + 4): + printk(BIOS_DEBUG, " DRB4: 0x%x\n", MCHBAR32(i)); + case (DRB + 5): + printk(BIOS_DEBUG, " DRB5: 0x%x\n", MCHBAR32(i)); + case (DRB + 6): + printk(BIOS_DEBUG, " DRB6: 0x%x\n", MCHBAR32(i)); + case (DRB + 7): + printk(BIOS_DEBUG, " DRB7: 0x%x\n", MCHBAR32(i)); + + case (DRA + 0): + printk(BIOS_DEBUG, " DRA0: 0x%x\n", MCHBAR32(i)); + case (DRA + 1): + printk(BIOS_DEBUG, " DRA1: 0x%x\n", MCHBAR32(i)); + case (DRA + 2): + printk(BIOS_DEBUG, " DRA2: 0x%x\n", MCHBAR32(i)); + case (DRA + 3): + printk(BIOS_DEBUG, " DRA3: 0x%x\n", MCHBAR32(i)); + case (DRA + 4): + printk(BIOS_DEBUG, " DRA4: 0x%x\n", MCHBAR32(i)); + case (DRA + 5): + printk(BIOS_DEBUG, " DRA5: 0x%x\n", MCHBAR32(i)); + case (DRA + 6): + printk(BIOS_DEBUG, " DRA6: 0x%x\n", MCHBAR32(i)); + case (DRA + 7): + printk(BIOS_DEBUG, " DRA7: 0x%x\n", MCHBAR32(i)); + + case DRT: + printk(BIOS_DEBUG, " DRT: 0x%x\n", MCHBAR32(i)); + case DRC: + printk(BIOS_DEBUG, " DRC: 0x%x\n", MCHBAR32(i)); + default: + printk(BIOS_DEBUG, "0x%x: 0x%x\n", i, MCHBAR32(i)); + } + } +} + +static void early_northbridge_set_registers(void) +{ + u8 reg8; + + /* Undocumented register */ + reg8 = pci_read_config8(NORTHBRIDGE, 0xf4); + + /* + Writing 0x2 to northbridge register 0xf4 + exposes the PCI registers of device 6. + */ + //reg8 |= 0x2; /* guesswork: the default value is 0x0 */ + reg8 = 0x2; + + printk(BIOS_DEBUG, "Enabling access to (the registers of) device 6\n"); + pci_write_config8(NORTHBRIDGE, 0xf4, reg8); + + printk(BIOS_DEBUG, "Configuring BAR6 as 0x%x\n", DEFAULT_MCHBAR); + pci_write_config32(NORTHBRIDGE_MMC, BAR6, DEFAULT_MCHBAR); + + printk(BIOS_DEBUG, "Enabling Memory Access Enable (MAE) in PCICMD6\n"); + pci_write_config16(NORTHBRIDGE_MMC, PCICMD6, 0x2); +} + +static void northbridge_set_pam(void) +{ + printk(BIOS_DEBUG, "Configuring PAM0..PAM6\n"); + pci_write_config8(NORTHBRIDGE, PAM0, 0x10); + pci_write_config8(NORTHBRIDGE, PAM1, 0x11); + pci_write_config8(NORTHBRIDGE, PAM2, 0x1); + pci_write_config8(NORTHBRIDGE, PAM3, 0x0); + pci_write_config8(NORTHBRIDGE, PAM4, 0x0); + pci_write_config8(NORTHBRIDGE, PAM5, 0x33); + pci_write_config8(NORTHBRIDGE, PAM6, 0x33); +} + +static void northbridge_set_registers(void) +{ + printk(BIOS_DEBUG, "Configuring APBASE\n"); + pci_write_config32(NORTHBRIDGE, APBASE, 0xfe800008); + + printk(BIOS_DEBUG, "Configuring APSIZE\n"); + pci_write_config8(NORTHBRIDGE, APSIZE, 0x3f); + + printk(BIOS_DEBUG, "Configuring GC\n"); /* IVD=0, IGDIS=0, GMS=8 megabyte */ + pci_write_config8(NORTHBRIDGE, GC, 0x34); + + printk(BIOS_DEBUG, "Configuring AMTT\n"); + pci_write_config8(NORTHBRIDGE, AMTT, 0x20); + + printk(BIOS_DEBUG, "Configuring LPTT\n"); + pci_write_config8(NORTHBRIDGE, LPTT, 0x10); + + printk(BIOS_DEBUG, "Configuring GMCHCFG\n"); + pci_write_config16(NORTHBRIDGE, GMCHCFG, 0x40d); + + printk(BIOS_DEBUG, "Configuring TOUD\n"); + pci_write_config16(NORTHBRIDGE, TOUD, 0x1f80); + + printk(BIOS_DEBUG, "Configuring PCISTS\n"); + pci_write_config16(NORTHBRIDGE, PCISTS, 0x2009); + + printk(BIOS_DEBUG, "Writing SVID and SID\n"); + pci_write_config16(NORTHBRIDGE, SVID, 0x1849); + pci_write_config16(NORTHBRIDGE, SID, 0x2570); + + printk(BIOS_DEBUG, "Configuring ERRSTS\n"); + pci_write_config16(NORTHBRIDGE, ERRSTS, 0x100); +} + +static void northbridge_set_undocumented_registers(void) +{ + u8 reg8; + + printk(BIOS_DEBUG, "Configuring undocumented register 0x54\n"); + /* + guesswork, the default value is 0x18 and 0x1c is the value from lspci -nnvvvxxx. + conclusion: add 0x4 */ + reg8 = pci_read_config8(NORTHBRIDGE, 0x54); + reg8 |= 0x4; + pci_write_config8(NORTHBRIDGE, 0x54, reg8); + + printk(BIOS_DEBUG, "Configuring undocumented register 0x9d\n"); + reg8 = pci_read_config8(NORTHBRIDGE, 0xc9d); + reg8 |= 0x8; + pci_write_config8(NORTHBRIDGE, 0x9d, reg8); +} + +//static void hardcoded_initialization(void) +//{ + // int i; + +// printk(BIOS_DEBUG, "Configuring DRT\n"); +// MCHBAR32(DRT) = 0x56e40d00; /* single-channel, 512MB in the first (physical) slot */ +// printk(BIOS_DEBUG, " DRT after configuring (should be 0x56e40d00): 0x%x\n", MCHBAR32(DRT)); + +// printk(BIOS_DEBUG, "Configuring DRB0..DRB7\n"); + + /* single-channel, 512MB in the first (physical) slot */ +// MCHBAR8(DRB + 0) = 0x4; +// MCHBAR8(DRB + 1) = 0x8; +// MCHBAR8(DRB + 2) = 0x8; +// MCHBAR8(DRB + 3) = 0x8; +// MCHBAR8(DRB + 4) = 0x8; +// MCHBAR8(DRB + 5) = 0x8; +// MCHBAR8(DRB + 6) = 0x8; +// MCHBAR8(DRB + 7) = 0x8; + // for (i = 0; i < 8; i++) { + // printk(BIOS_DEBUG, " DRB%i after configuring (should be 0x4 for DRB0, 0x8 for DRB1-7): 0x%x\n", i, MCHBAR8(DRB + i)); + // } + +// printk(BIOS_DEBUG, "Configuring DRA0..DRA7\n"); + + /* single-channel, 512MB in the first (physical) slot */ +// MCHBAR8(DRA + 0) = 0x0; +// MCHBAR8(DRA + 1) = 0x11; // 8 kilobyte on each row +// MCHBAR8(DRA + 2) = 0x0; +// MCHBAR8(DRA + 3) = 0x0; + // for (i = 0; i < 8; i++) { + // printk(BIOS_DEBUG, " DRA%i after configuring (should be 0x0 for DRA0, DRA2 and DRA3, 0x11 for DRA1: 0x%x\n", + // i, MCHBAR8(DRA + i)); + // } + + // BAR6_32(DRC) = 0x20104271; + + // printk(BIOS_DEBUG, "All aboard the undocumented registers train :(\n"); + +/* + MCHBAR32(0x6c) = 0xa801; + MCHBAR32(0xb0) = 0x40830; + MCHBAR32(0x100) = 0x89b; + MCHBAR32(0x104) = 0x4ad; + MCHBAR32(0x130) = 0x88d; + MCHBAR32(0x138) = 0x210843c; + MCHBAR32(0x140) = 0x1721c; + MCHBAR32(0x144) = 0xe380fff; + MCHBAR32(0x170) = 0x1a00018b; + MCHBAR32(0x1a0) = 0x3d0524fd; + MCHBAR32(0x200) = 0x1; + MCHBAR32(0x208) = 0x3937; + MCHBAR32(0x300) = 0x32; + MCHBAR32(0x800) = 0xdddddddd; +*/ + // sdram_dump_mchbar_registers(); // from i945 +//} + +static void sdram_initialize(void) +//void sdram_initialize(void) +{ + /* First things first. */ + early_northbridge_set_registers(); + + uint8_t dimm_mask; + + printk(BIOS_DEBUG, "Reading SPD data...\n"); + dimm_mask = spd_get_supported_dimms(); + + if (dimm_mask == 0) { + printk(BIOS_DEBUG, "No usable memory for this controller\n"); + } + else { + printk(BIOS_DEBUG, "DIMM mask: 0x%x\n", dimm_mask); + + spd_set_row_attributes(dimm_mask); // done? + spd_set_dram_controller_mode(dimm_mask); // TODO + spd_set_dram_timing(dimm_mask); // TODO: tRAS + spd_set_dram_size(dimm_mask); // TODO + } + + sdram_enable(); + + enable_refresh(); + + set_initialization_complete(); + + /* Setup Initial Northbridge Registers */ + northbridge_set_pam(); + northbridge_set_registers(); + northbridge_set_undocumented_registers(); + + sdram_dump_mchbar_registers(); + + printk(BIOS_DEBUG, "Northbridge following SDRAM init:\n"); + + dump_pci_device(NORTHBRIDGE); + dump_pci_device(NORTHBRIDGE_MMC); +// dump_pci_device(PCI_DEV(0, 0x1e, 0)); +// dump_pci_device(PCI_DEV(0, 0x1f, 0)); +// dump_pci_device(PCI_DEV(0, 0x1f, 3)); +} diff --git a/src/northbridge/intel/i865/raminit.h b/src/northbridge/intel/i865/raminit.h new file mode 100644 index 0000000..bf47053 --- /dev/null +++ b/src/northbridge/intel/i865/raminit.h @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Jon Dufresne + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// #ifndef NORTHBRIDGE_INTEL_I865_RAMINIT_H +// #define NORTHBRIDGE_INTEL_I865_RAMINIT_H +#ifndef RAMINIT_H +#define RAMINIT_H + +#define DIMM_SOCKETS 4 + +/* i865 Northbridge PCI devices */ +#define NORTHBRIDGE PCI_DEV(0, 0, 0) +#define NORTHBRIDGE_MMC PCI_DEV(0, 6, 0) // Overflow device + +/*----------------------------------------------------------------------------- +Macros and definitions: +-----------------------------------------------------------------------------*/ +//#define VALIDATE_DIMM_COMPATIBILITY + +#define delay() udelay(200) + +/* should dispose of this. */ +// burst length can be 4 or 8 in single-channel or 8 in dual-channel +// interleaved bursts versus sequential bursts.. no idea about the capabilities of i865, so I left it out +//#define VG86X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5) +//#define VG86X_MODE (SDRAM_BURST_4 | SDRAM_CAS_3) // SDRAM_CAS_* == tCL? +#define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5) + +/* Main Memory Control */ +#define DEFAULT_MCHBAR 0xfecf0000 /* ? KB */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +//#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) // unused +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +/* Memory mapped registers */ +#define DRB 0x0 /* DRAM Row 0-7 Boundary */ +#define DRA 0x10 /* DRAM Row 0-7 Attribute */ +#define DRT 0x60 /* DRAM Timing */ +#define DRC 0x68 /* DRAM Controller Mode */ + +/* Northbridge (device 0) */ +#define PAM0 0x90 /* Programmable Attribute Map #0 */ +#define PAM1 0x91 /* Programmable Attribute Map #1 */ +#define PAM2 0x92 /* Programmable Attribute Map #2 */ +#define PAM3 0x93 /* Programmable Attribute Map #3 */ +#define PAM4 0x94 /* Programmable Attribute Map #4 */ +#define PAM5 0x95 /* Programmable Attribute Map #5 */ +#define PAM6 0x96 /* Programmable Attribute Map #6 */ + +/* DRC[29] - Initialization Complete (IC) */ +//#define RAM_COMMAND_IC 0x1 +//#define DRC_DONE (RAM_COMMAND_IC << 29) +#define RAM_INITIALIZATION_COMPLETE (1 << 29) + +/* DRC[22:21] - Number of Channels (CHAN) */ +// TODO: rename to DRC_*_CHANNEL_* ? +#define RAM_SINGLE_CHANNEL 0x0 +#define RAM_DUAL_CHANNEL_LINEAR 0x1 +#define RAM_DUAL_CHANNEL_TILEAR 0x2 + +/* DRC[10:8] - Refresh Mode Select (RMS) + * 0x1 for Refresh interval 15.6 us + * 0x2 for Refresh interval 7.8 us + * 0x3 for Refresh interval 64 usec + * 0x7 for Refresh interval 64 Clocks. (Fast Refresh Mode) + */ +// TODO: rename to DRC_RMS_* ? +// #define RAM_RMS_15_6 0x1 /* usec */ +// #define RAM_RMS_7_8 0x2 /* usec */ +// #define RAM_RMS_64 0x3 /* usec */ +// #define RAM_RMS_FAST 0x7 /* clocks */ +#define RAM_COMMAND_REFRESH 0x1 + +/* DRC[6:4] - Mode Select (SMS) */ +// TODO: mask? +// TODO: rename to DRC_SMS_* ? +#define RAM_COMMAND_POST_RESET 0x0 +#define RAM_COMMAND_NOP 0x1 +#define RAM_COMMAND_PRECHARGE 0x2 +#define RAM_COMMAND_MRS 0x3 +#define RAM_COMMAND_EMRS 0x4 +#define RAM_COMMAND_CBR 0x6 +#define RAM_COMMAND_NORMAL 0x7 + +/* Activate to Precharge delay (tRAS) */ +#define DRT_TRAS_MAX_70 (1 << 10) +#define DRT_TRAS_MAX_120 (0 << 10) +#define DRT_TRAS_MIN_MASK (5 << 7) // conflicts with DRT_TRAS_MIN_5 +#define DRT_TRAS_MIN_10 (0 << 7) +#define DRT_TRAS_MIN_9 (1 << 7) +#define DRT_TRAS_MIN_8 (2 << 7) +#define DRT_TRAS_MIN_7 (3 << 7) +#define DRT_TRAS_MIN_6 (4 << 7) +#define DRT_TRAS_MIN_5 (5 << 7) + +/* CAS# latency (tCL) */ +#define DRT_TCL_MASK (3 << 5) +#define DRT_TCL_2_0 (1 << 5) +#define DRT_TCL_2_5 (0 << 5) +#define DRT_TCL_3_0 (2 << 5) + +/* DRAM RAS# to CAS delay (tRCD) */ +#define DRT_TRCD_MASK (3 << 2) +#define DRT_TRCD_4 (0 << 2) +#define DRT_TRCD_3 (1 << 2) +#define DRT_TRCD_2 (2 << 2) + +/* DRAM RAS# precharge (tRP) */ +#define DRT_TRP_MASK 3 +#define DRT_TRP_4 0 +#define DRT_TRP_3 1 +#define DRT_TRP_2 2 + +// moved from i855.h +#define DRT_CAS_MASK (3 << 5) +#define DRT_CAS_2_0 (1 << 5) +#define DRT_CAS_2_5 (0 << 5) +#define DRT_CAS_3_0 (2 << 5) + +struct sys_info { // copied from i945, not yet used + u16 memory_frequency; /* 400, 533 or 667 */ + u16 fsb_frequency; /* 400, 533 or 667 */ + + u8 trp; /* calculated by sdram_detect_smallest_tRP() */ + u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */ + u8 tras; /* calculated by sdram_detect_smallest_tRAS() */ + // u8 trfc; /* calculated by sdram_detect_smallest_tRFC() */ + // u8 twr; /* calculated by sdram_detect_smallest_tWR() */ + + u8 cas; /* 3, 4 or 5 */ + u8 refresh; /* 0 = 15.6us, 1 = 7.8us */ + + u8 dual_channel; /* 0 or 1 */ + u8 interleaved; + + // u8 mvco4x; /* 0 (8x) or 1 (4x) */ + // u8 clkcfg_bit7; + // u8 boot_path; +// #define BOOT_PATH_NORMAL 0 +// #define BOOT_PATH_RESET 1 +// #define BOOT_PATH_RESUME 2 + + // u8 package; /* 0 = planar, 1 = stacked */ +// #define SYSINFO_PACKAGE_PLANAR 0x00 +// #define SYSINFO_PACKAGE_STACKED 0x01 + u8 dimm[2 * DIMM_SOCKETS]; +#define SYSINFO_DIMM_X16DS 0x00 +#define SYSINFO_DIMM_X8DS 0x01 +#define SYSINFO_DIMM_X16SS 0x02 +#define SYSINFO_DIMM_X8DDS 0x03 +#define SYSINFO_DIMM_NOT_POPULATED 0x04 + + u8 banks[2 * DIMM_SOCKETS]; + + u8 banksize[2 * 2 * DIMM_SOCKETS]; + const u8 *spd_addresses; + +} __attribute__ ((packed)); + + +//void sdram_initialize(void); + +#endif /* NORTHBRIDGE_INTEL_I865_RAMINIT_H */ diff --git a/src/northbridge/intel/i865/reset_test.c b/src/northbridge/intel/i865/reset_test.c new file mode 100644 index 0000000..c465c53 --- /dev/null +++ b/src/northbridge/intel/i865/reset_test.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Jon Dufresne + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "raminit.h" + + /* If I have already booted once skip a bunch of initialization */ + /* To see if I have already booted I check to see if memory + * has been enabled. + */ +static int bios_reset_detected(void) +{ + uint32_t dword; + + dword = BAR6_32(DRC); + + if( (dword & DRC_DONE) != 0 ) { + return 1; + } + + return 0; +} diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index cdf1f62..1c67c51 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -1,6 +1,6 @@ #include "smbus.h" -#define SMBUS_IO_BASE 0x0f00 +//#define SMBUS_IO_BASE 0x0f00 static void enable_smbus(void) { @@ -9,7 +9,7 @@ static void enable_smbus(void) print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - print_debug_hex32(pci_read_config32(dev, 0x20)); + printk(BIOS_DEBUG, "SMB_BASE = 0x%x\n", pci_read_config32(dev, SMB_BASE)); /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); /* Set smbus iospace enable */ diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h index f330c0a..0fa6b84 100644 --- a/src/southbridge/intel/i82801ex/smbus.h +++ b/src/southbridge/intel/i82801ex/smbus.h @@ -1,5 +1,8 @@ #include +#define SMBUS_IO_BASE 0x400 +#define SMB_BASE 0x20 + #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3 diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 559e982..a54139f 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -45,3 +45,14 @@ static void inline w83627thg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +static void w83627thg_set_clksel_48(device_t dev) +{ + u8 reg8; + + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} From gerrit at coreboot.org Sat Nov 5 19:25:12 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Sat, 5 Nov 2011 19:25:12 +0100 Subject: [coreboot] New patch to review for coreboot: bf75f52 Add code to set the clock speed for Winbond W83627THF/THG. References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/412 -gerrit commit bf75f52a17bb63332f115dd1abd2db8925535975 Author: Idwer Vollering Date: Sat Nov 5 19:24:09 2011 +0100 Add code to set the clock speed for Winbond W83627THF/THG. Change-Id: I984404dd1df50b3ba423ac610283b9bf8bca5a31 Signed-off-by: Idwer Vollering --- src/superio/winbond/w83627thg/early_serial.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 559e982..95d362e 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -45,3 +45,13 @@ static void inline w83627thg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +static void w83627thg_set_clksel_48(device_t dev) +{ + u8 reg8; + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} From gerrit at coreboot.org Sat Nov 5 19:34:42 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Sat, 5 Nov 2011 19:34:42 +0100 Subject: [coreboot] New patch to review for coreboot: e544fdc Refactor src/southbridge/intel/i82801ex/smbus.h References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/413 -gerrit commit e544fdc1961b886af95a06a8d17396057671df4b Author: Idwer Vollering Date: Sat Nov 5 19:34:11 2011 +0100 Refactor src/southbridge/intel/i82801ex/smbus.h Change-Id: I72f6bf68f1577f41565c96cb4c389609cde55b01 Signed-off-by: Idwer Vollering --- src/southbridge/intel/i82801ex/early_smbus.c | 4 +--- src/southbridge/intel/i82801ex/smbus.h | 4 ++++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index cdf1f62..618bec7 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -1,7 +1,5 @@ #include "smbus.h" -#define SMBUS_IO_BASE 0x0f00 - static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); @@ -9,7 +7,7 @@ static void enable_smbus(void) print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - print_debug_hex32(pci_read_config32(dev, 0x20)); + printk(BIOS_DEBUG, "SMB_BASE = 0x%x\n", pci_read_config32(dev, SMB_BASE)); /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); /* Set smbus iospace enable */ diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h index f330c0a..e257e25 100644 --- a/src/southbridge/intel/i82801ex/smbus.h +++ b/src/southbridge/intel/i82801ex/smbus.h @@ -1,5 +1,9 @@ #include +//#define SMBUS_IO_BASE 0x0f00 +#define SMBUS_IO_BASE 0x400 +#define SMB_BASE 0x20 + #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3 From gerrit at coreboot.org Sat Nov 5 19:42:29 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Sat, 5 Nov 2011 19:42:29 +0100 Subject: [coreboot] New patch to review for coreboot: f803b6e Refactor src/southbridge/intel/i82801ex/smbus.h References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/414 -gerrit commit f803b6e3c01a9dffd11ed72b95026e26d4822a92 Author: Idwer Vollering Date: Sat Nov 5 19:41:53 2011 +0100 Refactor src/southbridge/intel/i82801ex/smbus.h Change-Id: I67a43222e9d8f2c859c7351fc4c13557462c1fec Signed-off-by: Idwer Vollering --- src/southbridge/intel/i82801ex/early_smbus.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index 618bec7..37799a8 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -6,7 +6,7 @@ static void enable_smbus(void) print_spew("SMBus controller enabled\n"); - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | 1); printk(BIOS_DEBUG, "SMB_BASE = 0x%x\n", pci_read_config32(dev, SMB_BASE)); /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); From gerrit at coreboot.org Sat Nov 5 20:05:16 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Sat, 5 Nov 2011 20:05:16 +0100 Subject: [coreboot] New patch to review for coreboot: e973da4 Refactor src/southbridge/intel/i82801ex/smbus.h References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/415 -gerrit commit e973da4cfb41d2f6ed13f2b6b8cfc2ccd8cfdb3d Author: Idwer Vollering Date: Sat Nov 5 20:02:29 2011 +0100 Refactor src/southbridge/intel/i82801ex/smbus.h Change-Id: I8be22f0292e322562b117f1e8bf493ed25eb4bec Signed-off-by: Idwer Vollering --- src/southbridge/intel/i82801ex/early_smbus.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index 37799a8..400ac50 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -7,7 +7,11 @@ static void enable_smbus(void) print_spew("SMBus controller enabled\n"); pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | 1); - printk(BIOS_DEBUG, "SMB_BASE = 0x%x\n", pci_read_config32(dev, SMB_BASE)); + + print_debug("SMB_BASE = 0x") + print_debug_hex32(pci_read_config32(dev, SMB_BASE)); + print_debug("\n"); + /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); /* Set smbus iospace enable */ From gerrit at coreboot.org Sat Nov 5 20:08:06 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Sat, 5 Nov 2011 20:08:06 +0100 Subject: [coreboot] Patch set updated for coreboot: fb4e8e6 Refactor src/southbridge/intel/i82801ex/smbus.h References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/415 -gerrit commit fb4e8e6babbe995dd7f82d7e3f9c056a26df86c9 Author: Idwer Vollering Date: Sat Nov 5 20:02:29 2011 +0100 Refactor src/southbridge/intel/i82801ex/smbus.h Change-Id: I8be22f0292e322562b117f1e8bf493ed25eb4bec Signed-off-by: Idwer Vollering --- src/southbridge/intel/i82801ex/early_smbus.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index 37799a8..16b5e2a 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -7,7 +7,11 @@ static void enable_smbus(void) print_spew("SMBus controller enabled\n"); pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | 1); - printk(BIOS_DEBUG, "SMB_BASE = 0x%x\n", pci_read_config32(dev, SMB_BASE)); + + print_debug("SMB_BASE = 0x"); + print_debug_hex32(pci_read_config32(dev, SMB_BASE)); + print_debug("\n"); + /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); /* Set smbus iospace enable */ From gerrit at coreboot.org Sat Nov 5 20:34:50 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Sat, 5 Nov 2011 20:34:50 +0100 Subject: [coreboot] New patch to review for coreboot: 3a6e78d Make the Makefile of inteltool and superiotool more flexible. References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/416 -gerrit commit 3a6e78ddb8b21625f4150a24cd1e124f36e77682 Author: Idwer Vollering Date: Sat Nov 5 20:34:03 2011 +0100 Make the Makefile of inteltool and superiotool more flexible. Change-Id: I0a85cb469bd1188fcd4e88df59380ffa5828496f Signed-off-by: Idwer Vollering --- util/inteltool/Makefile | 2 +- util/superiotool/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index db7fca0..e347931 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -22,7 +22,7 @@ PROGRAM = inteltool CC = gcc -INSTALL = /usr/bin/install +INSTALL = $(shell which install) PREFIX = /usr/local CFLAGS = -O2 -g -Wall -W LDFLAGS = -lpci -lz diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 5cc7650..45af168 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -21,7 +21,7 @@ PROGRAM = superiotool CC = gcc -INSTALL = /usr/bin/install +INSTALL = $(shell which install) PREFIX = /usr/local # Set the superiotool version string from the highest revision number From gerrit at coreboot.org Sat Nov 5 22:32:07 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 5 Nov 2011 22:32:07 +0100 Subject: [coreboot] New patch to review for coreboot: 1b5519c buildgcc: Fix wrapper Makefile References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/417 -gerrit commit 1b5519c088120550324b21ab5d15fee2cf6a3308 Author: Patrick Georgi Date: Sat Nov 5 22:30:56 2011 +0100 buildgcc: Fix wrapper Makefile buildgcc moved from building gdb by default (with opt-out) to gdb being optional. Adapt Makefile so it works again Change-Id: I663a8c70db4f7b5d07456fb67a223dbb2de2c133 Signed-off-by: Patrick Georgi --- util/crossgcc/Makefile | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 8fe9c54..b63cc06 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,11 +1,11 @@ all: build build: - bash ./buildgcc + bash ./buildgcc -G .PHONY: build-without-gdb build-without-gdb: - bash ./buildgcc --skip-gdb + bash ./buildgcc clean: rm -rf xgcc From gerrit at coreboot.org Sat Nov 5 22:34:11 2011 From: gerrit at coreboot.org (Christoph Grenz (christophg+cb@grenz-bonn.de)) Date: Sat, 5 Nov 2011 22:34:11 +0100 Subject: [coreboot] Patch set updated for coreboot: e3328fc w83627hf: drop Scope(\_SB) from ASL include References: Message-ID: Christoph Grenz (christophg+cb at grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/298 -gerrit commit e3328fc1773c0c943d1ad78b02fd1c2d36d2c13e Author: Christoph Grenz Date: Sat Nov 5 22:14:41 2011 +0100 w83627hf: drop Scope(\_SB) from ASL include Drop explicit Scope(\_SB) from devtree.asl as it forces the SuperIO to appear as child of the root device. devtree.asl then needs to be included at a reasonable position inside the \_SB device tree. Change-Id: I72a57eddc5ec5f9763fdf789094a7be042758256 Signed-off-by: Christoph Grenz --- src/superio/winbond/w83627hf/devtree.asl | 2496 +++++++++++++++--------------- 1 files changed, 1246 insertions(+), 1250 deletions(-) diff --git a/src/superio/winbond/w83627hf/devtree.asl b/src/superio/winbond/w83627hf/devtree.asl index aa18841..ddac22e 100644 --- a/src/superio/winbond/w83627hf/devtree.asl +++ b/src/superio/winbond/w83627hf/devtree.asl @@ -18,8 +18,8 @@ */ /* - * include this file into a mainboard's DSDT and it will expose the W83627HF - * SuperIO and its functionality in the _SB device tree. + * include this file into a mainboard's DSDT _SB device tree and it will expose the + * W83627HF SuperIO and its functionality. * * Devices are marked as nonexistant if they got 0x00000000 as I/O base address * (compatibility with legacy bios, which disables logical devices that way) @@ -56,960 +56,827 @@ * http://www.itox.com/pages/support/wdt/W83627HF.pdf */ -Scope (\_SB) -{ +Device(SIO) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Winbond W83627HF SuperIO")) + Name (_UID, "w83627hf") - Device(SIO) { - Name (_HID, EisaId("PNP0A05")) - Name (_STR, Unicode("Winbond W83627HF SuperIO")) - Name (_UID, "w83627hf") + /* Mutex for accesses to the configuration ports (prolog and epilog commands are used, so synchronization is useful) */ + Mutex(CRMX, 1) - /* Mutex for accesses to the configuration ports (prolog and epilog commands are used, so synchronization is useful) */ - Mutex(CRMX, 1) + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, 0x2E, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + ADDR, 8, + DATA, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + RST, 1, /* Soft reset */ + , 7, + Offset (0x07), + LDN, 8, /* Logical device selector */ + Offset (0x20), + DID, 8, /* Device ID */ + DREV, 8, /* Device Revision */ + FDPW, 1, /* FDC Power Down */ + , 2, + PRPW, 1, /* PRT Power Down */ + UAPW, 1, /* UART A Power Down */ + UBPW, 1, /* UART B Power Down */ + HWPW, 1, /* HWM Power Down */ + , 1, + IPD, 1, /* Immediate Chip Power Down */ + , 7, + PNPS, 1, /* PnP Address Select Register Default Value Mode */ + , 1, + KBCR, 1, /* KBC enabled after system reset (read-only) */ + , 3, + CLKS, 1, /* Clock select */ + AQ16, 1, /* 16bit Address Qualification */ + FDCT, 1, /* Tristate FDC (?) */ + , 2, + PRTT, 1, /* Tristate parallel port (?) */ + URAT, 1, /* Tristate UART A (?) */ + URBT, 1, /* Tristate UART B (?) */ + , 2, + URAI, 1, /* UART A Legacy IRQ Select Disable */ + URBI, 1, /* UART B Legacy IRQ Select Disable */ + PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ + FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ + , 1, + LCKC, 1, /* Lock Configuration Registers */ + Offset (0x29), + IO3S, 8, /* GPIO3 pin selection register */ + ACTR, 1, /* Logical device activation */ + ACT1, 1, /* Logical part activation 1 (mostly unused) */ + ACT2, 1, /* Logical part activation 2 (mostly unused) */ + , 5, + Offset (0x60), + IO1H, 8, /* First I/O port base - high byte */ + IO1L, 8, /* First I/O port base - low byte */ + IO2H, 8, /* Second I/O port base - high byte */ + IO2L, 8, /* Second I/O port base - low byte */ + Offset (0x70), + IRQ0, 8, /* First IRQ */ + Offset (0x72), + IRQ1, 8, /* First IRQ */ + Offset (0x74), + DMA0, 8, /* DMA */ + Offset (0xE0), + /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ + CRE0, 8, + CRE1, 8, + CRE2, 8, + CRE3, 8, + CRE4, 8, + Offset (0xF0), + /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ + OPT1, 8, + OPT2, 8, + OPT3, 8, + OPT4, 8, + OPT5, 8, + OPT6, 8, + OPT7, 8, + OPT8, 8, + OPT9, 8, + OPTA, 8 + } - /* SuperIO configuration ports */ - OperationRegion (CREG, SystemIO, 0x2E, 0x02) - Field (CREG, ByteAcc, NoLock, Preserve) - { - ADDR, 8, - DATA, 8 - } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) - { - Offset (0x02), - RST, 1, /* Soft reset */ - , 7, - Offset (0x07), - LDN, 8, /* Logical device selector */ - Offset (0x20), - DID, 8, /* Device ID */ - DREV, 8, /* Device Revision */ - FDPW, 1, /* FDC Power Down */ - , 2, - PRPW, 1, /* PRT Power Down */ - UAPW, 1, /* UART A Power Down */ - UBPW, 1, /* UART B Power Down */ - HWPW, 1, /* HWM Power Down */ - , 1, - IPD, 1, /* Immediate Chip Power Down */ - , 7, - PNPS, 1, /* PnP Address Select Register Default Value Mode */ - , 1, - KBCR, 1, /* KBC enabled after system reset (read-only) */ - , 3, - CLKS, 1, /* Clock select */ - AQ16, 1, /* 16bit Address Qualification */ - FDCT, 1, /* Tristate FDC (?) */ - , 2, - PRTT, 1, /* Tristate parallel port (?) */ - URAT, 1, /* Tristate UART A (?) */ - URBT, 1, /* Tristate UART B (?) */ - , 2, - URAI, 1, /* UART A Legacy IRQ Select Disable */ - URBI, 1, /* UART B Legacy IRQ Select Disable */ - PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ - FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ - , 1, - LCKC, 1, /* Lock Configuration Registers */ - Offset (0x29), - IO3S, 8, /* GPIO3 pin selection register */ - ACTR, 1, /* Logical device activation */ - ACT1, 1, /* Logical part activation 1 (mostly unused) */ - ACT2, 1, /* Logical part activation 2 (mostly unused) */ - , 5, - Offset (0x60), - IO1H, 8, /* First I/O port base - high byte */ - IO1L, 8, /* First I/O port base - low byte */ - IO2H, 8, /* Second I/O port base - high byte */ - IO2L, 8, /* Second I/O port base - low byte */ - Offset (0x70), - IRQ0, 8, /* First IRQ */ - Offset (0x72), - IRQ1, 8, /* First IRQ */ - Offset (0x74), - DMA0, 8, /* DMA */ - Offset (0xE0), - /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ - CRE0, 8, - CRE1, 8, - CRE2, 8, - CRE3, 8, - CRE4, 8, - Offset (0xF0), - /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ - OPT1, 8, - OPT2, 8, - OPT3, 8, - OPT4, 8, - OPT5, 8, - OPT6, 8, - OPT7, 8, - OPT8, 8, - OPT9, 8, - OPTA, 8 - } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) /* Announce the used I/O ports to the OS */ + IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) /* this port is used in some configurations, so announce it to be sure */ + }) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) /* Announce the used I/O ports to the OS */ - IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) /* this port is used in some configurations, so announce it to be sure */ - }) + /* Enter configuration mode (and aquire mutex) + Method must be run before accesssing the configuration region. + */ + Method (ENCM) + { + Acquire (CRMX, 0xFFFF) + Store (0x87, ADDR) + Store (0x87, ADDR) + } - /* Enter configuration mode (and aquire mutex) - Method must be run before accesssing the configuration region. - */ - Method (ENCM) - { - Acquire (CRMX, 0xFFFF) - Store (0x87, ADDR) - Store (0x87, ADDR) + /* Exit configuration mode (and release mutex) + Method must be run after accessing the configuration region. + */ + Method (EXCM) + { + Release (CRMX) + Store (0xAA, ADDR) + } + + /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ + Method (_PSC) { + ENCM () + Store (IPD, Local0) + EXCM () + If (Local0) { Return (2) } + Else { Return (0) } + } + + /* PM: Switch to D0 by setting IPD low */ + Method (_PS0) { + ENCM () + Store (Zero, IPD) + EXCM () + } + + /* PM: Switch to D2 by setting IPD high */ + Method (_PS2) { + ENCM () + Store (One, IPD) + EXCM () + } + + #ifndef NO_W83627HF_FDC + /* =================== Floppy Disk Controller ================ */ + Device (FDC0) { + Name (_HID, EisaId ("PNP0700")) + Name (_STR, Unicode ("W83627HF Floppy Disk Controller")) + Name (_UID, "w83627hf-fdc") + + #ifndef NO_W83627HF_FDC_ENUM + /* Initialization method: Should be run once on boot + If FDC is active, enumerate all connected devices */ + Method (_INI) { + ENCM () + Store (0x00, LDN) + Store (ACTR, Local0) + Store (IO1H, Local1) + Store (IO1L, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or(Local1, Local2, Local1) + If (Local0) { + /* Try probing drives and save result in _FDE */ + PROB(Local1) + } } + #endif - /* Exit configuration mode (and release mutex) - Method must be run after accessing the configuration region. - */ - Method (EXCM) + Method (_STA) { - Release (CRMX) - Store (0xAA, ADDR) + Store (0x00, Local0) + ENCM () + Store (0x00, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) } - /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } ENCM () - Store (IPD, Local0) + Store (FDPW, Local0) EXCM () - If (Local0) { Return (2) } + If (Local0) { Return (1) } Else { Return (0) } } - - /* PM: Switch to D0 by setting IPD low */ Method (_PS0) { ENCM () - Store (Zero, IPD) + Store (Zero, FDPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, FDPW) EXCM () } - /* PM: Switch to D2 by setting IPD high */ - Method (_PS2) { + Method (_DIS) + { ENCM () - Store (One, IPD) + Store (0x00, LDN) + Store (Zero, ACTR) EXCM () } - #ifndef NO_W83627HF_FDC - /* =================== Floppy Disk Controller ================ */ - Device (FDC0) { - Name (_HID, EisaId ("PNP0700")) - Name (_STR, Unicode ("W83627HF Floppy Disk Controller")) - Name (_UID, "w83627hf-fdc") + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x06, IO0) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + ENCM () + Store (0x00, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - #ifndef NO_W83627HF_FDC_ENUM - /* Initialization method: Should be run once on boot - If FDC is active, enumerate all connected devices */ - Method (_INI) { - ENCM () - Store (0x00, LDN) - Store (ACTR, Local0) - Store (IO1H, Local1) - Store (IO1L, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or(Local1, Local2, Local1) - If (Local0) { - /* Try probing drives and save result in _FDE */ - PROB(Local1) - } - } - #endif + Return (CRS) + } - Method (_STA) + Name (_PRS, ResourceTemplate () + { + StartDependentFnNoPri () { - Store (0x00, Local0) - ENCM () - Store (0x00, LDN) - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} } + EndDependentFn () + }) - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (FDPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, FDPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, FDPW) - EXCM () - } + #ifndef NO_W83627HF_FDC_ENUM + Name(_FDE, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + #endif - Method (_DIS) + Method (PROB, 1) { + #ifndef NO_W83627HF_FDC_ENUM + /* Try probing drives and save result in _FDE + Probing is done through selecting and activating a drive + and reading 0x03F7 aka the "shared IDE and floppy register" + as any value there besides zero seems to indicate a + connected drive. + */ + OperationRegion (FIO1, SystemIO, Arg0, 0x06) + Field (FIO1, ByteAcc, NoLock, Preserve) { - ENCM () - Store (0x00, LDN) - Store (Zero, ACTR) - EXCM () + Offset(0x02), + SELE, 2, + RSTL, 1, + IDMA, 1, + ACT1, 1, + ACT2, 1, + ACT3, 1, + ACT4, 1, + Offset(0x04), + BSY1, 1, + BSY2, 1, + BSY3, 1, + BSY4, 1, + BUSY, 1, + NDMA, 1, + IODI, 1, + RDY, 1, + DATA, 8, } + OperationRegion (FIO2, SystemIO, 0x3F7, 0x01) - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x06, IO0) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - ENCM () - Store (0x00, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + CreateByteField (_FDE, 3, FD1) + CreateByteField (_FDE, 7, FD2) + CreateByteField (_FDE, 11, FD3) + CreateByteField (_FDE, 15, FD4) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + Store(One, ACT1) + Store(0, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD1) } - Return (CRS) - } + Store(Zero, ACT1) + Store(One, ACT2) + Store(1, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD2) } - Name (_PRS, ResourceTemplate () - { - StartDependentFnNoPri () - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - } - EndDependentFn () - }) + Store(Zero, ACT2) + Store(One, ACT3) + Store(2, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD3) } - #ifndef NO_W83627HF_FDC_ENUM - Name(_FDE, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + Store(Zero, ACT3) + Store(One, ACT4) + Store(3, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD4) } + Store(Zero, ACT4) + Store(Zero, SELE) #endif - - Method (PROB, 1) { - #ifndef NO_W83627HF_FDC_ENUM - /* Try probing drives and save result in _FDE - Probing is done through selecting and activating a drive - and reading 0x03F7 aka the "shared IDE and floppy register" - as any value there besides zero seems to indicate a - connected drive. - */ - OperationRegion (FIO1, SystemIO, Arg0, 0x06) - Field (FIO1, ByteAcc, NoLock, Preserve) - { - Offset(0x02), - SELE, 2, - RSTL, 1, - IDMA, 1, - ACT1, 1, - ACT2, 1, - ACT3, 1, - ACT4, 1, - Offset(0x04), - BSY1, 1, - BSY2, 1, - BSY3, 1, - BSY4, 1, - BUSY, 1, - NDMA, 1, - IODI, 1, - RDY, 1, - DATA, 8, - } - OperationRegion (FIO2, SystemIO, 0x3F7, 0x01) - - CreateByteField (_FDE, 3, FD1) - CreateByteField (_FDE, 7, FD2) - CreateByteField (_FDE, 11, FD3) - CreateByteField (_FDE, 15, FD4) - - Store(One, ACT1) - Store(0, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD1) } - - Store(Zero, ACT1) - Store(One, ACT2) - Store(1, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD2) } - - Store(Zero, ACT2) - Store(One, ACT3) - Store(2, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD3) } - - Store(Zero, ACT3) - Store(One, ACT4) - Store(3, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD4) } - Store(Zero, ACT4) - Store(Zero, SELE) - #endif - } + } - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 6, IO0) - IO (Decode16, 0, 0, 1, 1, IO1) - IRQNoFlags (IRQ0) {} - DMA (Compatibility, NotBusMaster, Transfer8, DMA0) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO1._MIN, IOA1) - CreateByteField (Arg0, IRQ0._INT, IRQL) - CreateByteField (Arg0, DMA0._DMA, DMCH) + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 6, IO0) + IO (Decode16, 0, 0, 1, 1, IO1) + IRQNoFlags (IRQ0) {} + DMA (Compatibility, NotBusMaster, Transfer8, DMA0) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO1._MIN, IOA1) + CreateByteField (Arg0, IRQ0._INT, IRQL) + CreateByteField (Arg0, DMA0._DMA, DMCH) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - ENCM () - Store (0, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (One, ACTR) - EXCM () + ENCM () + Store (0, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (One, ACTR) + EXCM () - /* Try probing drives and save result in _FDE */ - PROB(IOA0) - } + /* Try probing drives and save result in _FDE */ + PROB(IOA0) } - #endif + } + #endif - #ifndef NO_W83627HF_PPORT - /* ======================== Parallel Port ======================== */ - /* Currently no ECP support */ - Device (PAR0) { - Name (_HID, EisaId ("PNP0400")) - Name (_DDN, "LPT1") - Name (_UID, "w83627hf-pport") + #ifndef NO_W83627HF_PPORT + /* ======================== Parallel Port ======================== */ + /* Currently no ECP support */ + Device (PAR0) { + Name (_HID, EisaId ("PNP0400")) + Name (_DDN, "LPT1") + Name (_UID, "w83627hf-pport") - Method (MODE, 1) { - And(Arg0, 0x07, Local0) - ENCM () - Store (0x01, LDN) - And(OPT1, 0x3, Local1) - Or(Local1, Local0, OPT1) - EXCM() - } + Method (MODE, 1) { + And(Arg0, 0x07, Local0) + ENCM () + Store (0x01, LDN) + And(OPT1, 0x3, Local1) + Or(Local1, Local0, OPT1) + EXCM() + } - Method (_INI) - { - /* Deactivate DMA, even if set by BIOS. We don't announce it - through _CRS and it's only useful in ECP mode which we - don't support at the moment. */ - ENCM () - Store (0x01, LDN) - Store (0x04, DMA0) - EXCM () - } + Method (_INI) + { + /* Deactivate DMA, even if set by BIOS. We don't announce it + through _CRS and it's only useful in ECP mode which we + don't support at the moment. */ + ENCM () + Store (0x01, LDN) + Store (0x04, DMA0) + EXCM () + } - Method (_STA) - { - Store (0x00, Local0) - ENCM () - Store (0x01, LDN) - And(OPT1, 0x3, Local1) - If (ACTR) { - If (LNotEqual(Local1, 2)) { - Store (0x0D, Local0) - } Else { - Store (0x0D, Local0) - } - } - ElseIf (LOr (IO1H, IO1L)) - { + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x01, LDN) + And(OPT1, 0x3, Local1) + If (ACTR) { + If (LNotEqual(Local1, 2)) { + Store (0x0D, Local0) + } Else { Store (0x0D, Local0) } - EXCM () - Return (Local0) - } - - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (PRPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, PRPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, PRPW) - EXCM () } - - Method (_DIS) { - ENCM () - Store (0x01, LDN) - Store (Zero, ACTR) - EXCM () - } - - Method (_CRS) + ElseIf (LOr (IO1H, IO1L)) { - Name (CRS, ResourceTemplate () - { - IO (Decode16, 0x0000, 0x0000, 0x04, 0x08, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (CRS, IO0._MIN, IOP0) - CreateWordField (CRS, IO0._MAX, IOR0) - CreateByteField (CRS, IO0._ALN, IOAL) - CreateByteField (CRS, IO0._LEN, IOLE) - CreateWordField (CRS, IRQX._INT, IRQW) - - ENCM () - Store (0x01, LDN) - Store (IO1L, Local0) - Store (IO1H, Local1) - Store (OPT1, Local2) - Store (IRQ0, Local5) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local1) + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } - And(Local2, 0x3, Local3) - And(Local2, 0x4, Local4) - If (Local4) { - Store(0x04, IOAL) - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (PRPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, PRPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, PRPW) + EXCM () + } - Store(Local1, IOP0) - Store(Local1, IOR0) + Method (_DIS) { + ENCM () + Store (0x01, LDN) + Store (Zero, ACTR) + EXCM () + } - If (LEqual (Local0, 0xBC)) - { - Store (0x04, IOLE) - } - Else - { - Store (0x08, IOLE) - } + Method (_CRS) + { + Name (CRS, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x04, 0x08, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (CRS, IO0._MIN, IOP0) + CreateWordField (CRS, IO0._MAX, IOR0) + CreateByteField (CRS, IO0._ALN, IOAL) + CreateByteField (CRS, IO0._LEN, IOLE) + CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local0) - ShiftLeft (Local0, Local5, IRQW) + ENCM () + Store (0x01, LDN) + Store (IO1L, Local0) + Store (IO1H, Local1) + Store (OPT1, Local2) + Store (IRQ0, Local5) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local1) - Return (CRS) + And(Local2, 0x3, Local3) + And(Local2, 0x4, Local4) + If (Local4) { + Store(0x04, IOAL) } - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,1) - { - IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,1) - { - IO (Decode16, 0x0278, 0x0278, 0x04, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,1) - { - IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) - { - IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) - { - IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) - { - IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,1) - { - IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn () - }) + Store(Local1, IOP0) + Store(Local1, IOR0) - Method (_SRS, 1, Serialized) + If (LEqual (Local0, 0xBC)) { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 4, 4, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO0._MIN, IOA1) - CreateByteField (Arg0, IO0._ALN, IOAL) - CreateByteField (Arg0, IO0._LEN, IOLE) - CreateWordField (Arg0, IRQX._INT, IRQL) - - If (LEqual(IOAL, 4)) { - Store(0x0, Local2) - } else { - Store(0x1, Local2) - } + Store (0x04, IOLE) + } + Else + { + Store (0x08, IOLE) + } - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Store (One, Local0) + ShiftLeft (Local0, Local5, IRQW) - ENCM () - Store (0x01, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - /*Mode*/ - Store (OPT1, Local3) - And (Local3, 0xF8, Local3) - Or (Local2, Local3, OPT1) - /*DMA off*/ - Store (0x04, DMA0) - /*IRQ*/ - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) - Store (Local3, IRQ0) - /*Activate*/ - Store (One, ACTR) - EXCM () - } + Return (CRS) } - #endif - - #ifndef NO_W83627HF_UARTA - /* =========================== UART A ============================ */ - Device (SER0) { - Name (_HID, EisaId ("PNP0501")) - Name (_UID, "w83627hf-uarta") - Name (_DDN, "COM1") - Method (_STA) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,1) { - Store (0x00, Local0) - ENCM () - Store (0x02, LDN) - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (UAPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } + StartDependentFn (0,1) + { + IO (Decode16, 0x0278, 0x0278, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - Method (_PS0) { - ENCM () - Store (Zero, UAPW) - EXCM () + StartDependentFn (0,1) + { + IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - Method (_PS1) { - ENCM () - Store (One, UAPW) - EXCM () + StartDependentFn (0,0) + { + IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Method (_DIS) + StartDependentFn (0,0) { - ENCM () - Store (0x02, LDN) - Store (Zero, ACTR) - EXCM () + IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Method (_CRS) + StartDependentFn (2,0) { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x02, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) - - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) - - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - - Return (CRS) + IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Name (_PRS, ResourceTemplate () + StartDependentFn (2,1) { - StartDependentFn (0,0) { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() - }) + IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn () + }) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 6, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 4, 4, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO0._MIN, IOA1) + CreateByteField (Arg0, IO0._ALN, IOAL) + CreateByteField (Arg0, IO0._LEN, IOLE) + CreateWordField (Arg0, IRQX._INT, IRQL) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + If (LEqual(IOAL, 4)) { + Store(0x0, Local2) + } else { + Store(0x1, Local2) + } - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - ENCM () - Store (2, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (0x01, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + /*Mode*/ + Store (OPT1, Local3) + And (Local3, 0xF8, Local3) + Or (Local2, Local3, OPT1) + /*DMA off*/ + Store (0x04, DMA0) + /*IRQ*/ + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) + Store (Local3, IRQ0) + /*Activate*/ + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_UARTB - /* =========================== UART B ============================ */ - Device (SER1) { - Name (_HID, EisaId ("PNP0501")) - Name (_UID, "w83627hf-uartb") - Name (_DDN, "COM2") + #ifndef NO_W83627HF_UARTA + /* =========================== UART A ============================ */ + Device (SER0) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, "w83627hf-uarta") + Name (_DDN, "COM1") - Method (_STA) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x02, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) { - Store (0x00, Local0) - ENCM () - Store (0x03, LDN) - If (LNot(And(OPT2, 0x30))) - { - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } - } - EXCM () - Return (Local0) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (UBPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, UBPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, UBPW) - EXCM () - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UAPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UAPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UAPW) + EXCM () + } - Method (_DIS) - { - ENCM () - Store (0x03, LDN) - Store (Zero, ACTR) - EXCM () - } + Method (_DIS) + { + ENCM () + Store (0x02, LDN) + Store (Zero, ACTR) + EXCM () + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x02, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + StartDependentFn (1,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 6, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 8, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) - - ENCM () - Store (3, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (2, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_IRDA - /* ======================== UART B (IRDA) ======================== */ - Device (IRDA) { - Name (_HID, EisaId ("PNP0510")) - Name (_UID, "w83627hf-irda") - Name (_STR, Unicode("IrDA Port")) + #ifndef NO_W83627HF_UARTB + /* =========================== UART B ============================ */ + Device (SER1) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, "w83627hf-uartb") + Name (_DDN, "COM2") - Method (_STA) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x03, LDN) + If (LNot(And(OPT2, 0x30))) { - Store (0x00, Local0) - ENCM () - Store (0x03, LDN) - If (And(OPT2, 0x30)) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) { - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } + Store (0x0D, Local0) } - EXCM () - Return (Local0) } + EXCM () + Return (Local0) + } - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (UBPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, UBPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, UBPW) - EXCM () - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UBPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UBPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UBPW) + EXCM () + } - Method (_DIS) - { - ENCM () - Store (0x03, LDN) - Store (Zero, ACTR) - EXCM () - } + Method (_DIS) + { + ENCM () + Store (0x03, LDN) + Store (Zero, ACTR) + EXCM () + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) - Return (CRS) + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + StartDependentFn (1,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 8, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) - - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - ENCM () - Store (3, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (3, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_CIR - /* ========================= Consumer IR ========================= */ - Device (CIR0) { - Name (_HID, EisaId ("WEC1022")) /* Should be the correct one */ - Name (_UID, "w83627hf-cir") - Name (_STR, Unicode("Winbond Consumer Infrared Transceiver")) + #ifndef NO_W83627HF_IRDA + /* ======================== UART B (IRDA) ======================== */ + Device (IRDA) { + Name (_HID, EisaId ("PNP0510")) + Name (_UID, "w83627hf-irda") + Name (_STR, Unicode("IrDA Port")) - Method (_STA) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x03, LDN) + If (And(OPT2, 0x30)) { - Store (0x00, Local0) - ENCM () - Store (0x06, LDN) If (ACTR) { Store (0x0F, Local0) } @@ -1017,508 +884,637 @@ Scope (\_SB) { Store (0x0D, Local0) } - EXCM () - Return (Local0) } + EXCM () + Return (Local0) + } - Method (_DIS) - { - ENCM () - Store (0x06, LDN) - Store (Zero, ACTR) - EXCM () - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UBPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UBPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UBPW) + EXCM () + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Method (_DIS) + { + ENCM () + Store (0x03, LDN) + Store (Zero, ACTR) + EXCM () + } - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 8, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) - - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - ENCM () - Store (6, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (3, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_KBC - /* ===================== Keyboard Controller ===================== */ - Device (KBD0) { - Name (_HID, EisaId ("PNP0303")) - Name (_CID, 0x0B03D041) - Name (_UID, "w83627hf-kbc") + #ifndef NO_W83627HF_CIR + /* ========================= Consumer IR ========================= */ + Device (CIR0) { + Name (_HID, EisaId ("WEC1022")) /* Should be the correct one */ + Name (_UID, "w83627hf-cir") + Name (_STR, Unicode("Winbond Consumer Infrared Transceiver")) - Method (_STA) - { - Store (0x00, Local0) - ENCM () - Store (0x05, LDN) - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x06, LDN) + If (ACTR) { + Store (0x0F, Local0) } - - Method (_DIS) + ElseIf (LOr (IO1H, IO1L)) { - ENCM () - Store (0x05, LDN) - Store (Zero, ACTR) - EXCM () - Notify(PS2M, 1) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x05, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IO2H, Local2) - Store(IO2L, Local3) - Store(IRQ0, Local4) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + Method (_DIS) + { + ENCM () + Store (0x06, LDN) + Store (Zero, ACTR) + EXCM () + } - ShiftLeft(Local2, 8, Local2) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IO1._MIN, I1MI) - Store (Local2, I1MI) - CreateWordField (CRS, IO1._MAX, I1MA) - Store (Local2, I1MA) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local5) - ShiftLeft (Local5, Local4, IRQW) + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 1, IO0) - IO (Decode16, 0, 0, 1, 1, IO1) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO1._MIN, IOA1) - CreateByteField (Arg0, IRQX._INT, IRQL) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - Divide(IOA1, 256, Local2, Local3) - ShiftRight(Local1, 8, Local1) + ENCM () + Store (6, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #endif - FindSetLeftBit (IRQL, Local4) - Subtract (Local4, 0x01, Local4) + #ifndef NO_W83627HF_KBC + /* ===================== Keyboard Controller ===================== */ + Device (KBD0) { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, 0x0B03D041) + Name (_UID, "w83627hf-kbc") - ENCM () - Store (5, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IO2H) - Store (Local2, IO2L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x05, LDN) + If (ACTR) { + Store (0x0F, Local0) } - } - #ifndef NO_W83627HF_PS2M - Device (PS2M) { - Name (_HID, EisaId ("PNP0F13")) - Name (_UID, "w83627hf-ps2m") - - Method (_STA) + ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) { - Store (0x00, Local0) - ENCM () - Store (0x05, LDN) - If (LAnd(ACTR, IRQ1) ) { - Store (0x0F, Local0) - } - ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } - Method (_DIS) - { - ENCM () - Store (0x05, LDN) - Store (Zero, IRQ1) - EXCM () - } + Method (_DIS) + { + ENCM () + Store (0x05, LDN) + Store (Zero, ACTR) + EXCM () + Notify(PS2M, 1) + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IRQNoFlags (IRQX) {} - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) - }) - ENCM () - Store (0x05, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IO2H, Local2) - Store(IO2L, Local3) - Store(IRQ1, Local4) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x05, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IO2H, Local2) + Store(IO2L, Local3) + Store(IRQ0, Local4) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) - ShiftLeft(Local2, 8, Local2) - Or (Local1, Local0, Local0) + ShiftLeft(Local2, 8, Local2) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IO1._MIN, I1MI) - Store (Local2, I1MI) - CreateWordField (CRS, IO1._MAX, I1MA) - Store (Local2, I1MA) + CreateWordField (CRS, IO1._MIN, I1MI) + Store (Local2, I1MI) + CreateWordField (CRS, IO1._MAX, I1MA) + Store (Local2, I1MA) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local5) - ShiftLeft (Local5, Local4, IRQW) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local5) + ShiftLeft (Local5, Local4, IRQW) + + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IRQNoFlags () {12} - } - StartDependentFn (2,0) { - IRQNoFlags () {1,3,4,5,6,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 1, IO0) + IO (Decode16, 0, 0, 1, 1, IO1) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO1._MIN, IOA1) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IRQNoFlags (IRQX) {} - }) - CreateByteField (Arg0, IRQX._INT, IRQL) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local0) - Subtract (Local0, 0x01, Local0) + Divide(IOA1, 256, Local2, Local3) + ShiftRight(Local1, 8, Local1) - ENCM () - Store (5, LDN) - Store (Local0, IRQ1) - /* Only activates if KBD is active */ - Store (One, ACTR) - EXCM () - } - } - #endif - #endif + FindSetLeftBit (IRQL, Local4) + Subtract (Local4, 0x01, Local4) - #ifndef NO_W83627HF_GAME - /* ========================== Game Port ========================== */ - Device (GAME) { - Name (_HID, EisaId ("PNPB02F")) - Name (_STR, Unicode ("Joystick/Game Port")) - Name (_UID, "w83627hf-game") + ENCM () + Store (5, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IO2H) + Store (Local2, IO2L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #ifndef NO_W83627HF_PS2M + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_UID, "w83627hf-ps2m") - Method (_STA) { - ENCM () - Store(0, Local0) - Store (0x07, LDN) - If (LOr(IO1L, IO1H)) { - If (LOr(ACTR, ACT1)) { - Store (0x0F, Local0) - } - Else { - Store (0x0D, Local0) - } - } - EXCM () - Return (Local0) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x05, LDN) + If (LAnd(ACTR, IRQ1) ) { + Store (0x0F, Local0) } - - Method (_CRS) + ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x07, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) - - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) - - If (Local2) { - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - } - - Return (CRS) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } + Method (_DIS) + { + ENCM () + Store (0x05, LDN) + Store (Zero, IRQ1) + EXCM () } - #endif - #ifndef NO_W83627HF_MIDI - /* ========================== MIDI Port ========================== */ - Device (MIDI) { - Name (_HID, EisaId ("PNPB006")) - Name (_STR, Unicode ("MPU-401 Compatible MIDI Port")) - Name (_UID, "w83627hf-midi") + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IRQNoFlags (IRQX) {} + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + }) + ENCM () + Store (0x05, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IO2H, Local2) + Store(IO2L, Local3) + Store(IRQ1, Local4) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + ShiftLeft(Local2, 8, Local2) + Or (Local1, Local0, Local0) - Method (_STA) { - ENCM () - Store(0, Local0) - Store (0x07, LDN) - If (LOr(IO2L, IO2H)) { - If (LOr(ACTR, ACT2)) { - Store (0x0F, Local0) - } - Else { - Store (0x0D, Local0) - } - } - EXCM () - Return (Local0) - } + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x02, 0x02, IO0) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x07, LDN) - Store(IO2H, Local0) - Store(IO2L, Local1) - Store(IRQ1, Local2) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + CreateWordField (CRS, IO1._MIN, I1MI) + Store (Local2, I1MI) + CreateWordField (CRS, IO1._MAX, I1MA) + Store (Local2, I1MA) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local5) + ShiftLeft (Local5, Local4, IRQW) - If (Local2) { - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - } + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IRQNoFlags () {12} + } + StartDependentFn (2,0) { + IRQNoFlags () {1,3,4,5,6,7,9,10,11,12} } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IRQNoFlags (IRQX) {} + }) + CreateByteField (Arg0, IRQX._INT, IRQL) + FindSetLeftBit (IRQL, Local0) + Subtract (Local0, 0x01, Local0) + + ENCM () + Store (5, LDN) + Store (Local0, IRQ1) + /* Only activates if KBD is active */ + Store (One, ACTR) + EXCM () } - #endif + } + #endif + #endif + + #ifndef NO_W83627HF_GAME + /* ========================== Game Port ========================== */ + Device (GAME) { + Name (_HID, EisaId ("PNPB02F")) + Name (_STR, Unicode ("Joystick/Game Port")) + Name (_UID, "w83627hf-game") - /* ==== Suspend LED control if it is connected to the SuperIO ==== */ - Method (SLED, 1) { + Method (_STA) { ENCM () - Store (9, LDN) - Store(OPT4, Local0) - And(Local0, 63, Local0) - Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + Store(0, Local0) + Store (0x07, LDN) + If (LOr(IO1L, IO1H)) { + If (LOr(ACTR, ACT1)) { + Store (0x0F, Local0) + } + Else { + Store (0x0D, Local0) + } + } EXCM () + Return (Local0) } - /* ===== Power LED control if it is connected to the SuperIO ===== */ - Method (PLED, 1) { + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IRQNoFlags (IRQX) {} + }) ENCM () - Store (8, LDN) - Store(OPT4, Local0) - And(Local0, 63, Local0) - Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + Store (0x07, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IRQ0, Local2) EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + } + + Return (CRS) } - #ifndef NO_W83627HF_HWMON - /* ====================== Hardware Monitor ======================= */ - Device (HMON) { - Name (_HID, EisaId ("PNP0C02")) // TODO: find better matching ID - Name (_STR, Unicode("W83627 Hardware Monitor")) - Name (_UID, "w83627hf-hwmon") + } + #endif + + #ifndef NO_W83627HF_MIDI + /* ========================== MIDI Port ========================== */ + Device (MIDI) { + Name (_HID, EisaId ("PNPB006")) + Name (_STR, Unicode ("MPU-401 Compatible MIDI Port")) + Name (_UID, "w83627hf-midi") - Method (_STA) - { - Store (0x00, Local0) - ENCM () - Store (0x0B, LDN) - If (ACTR) { + Method (_STA) { + ENCM () + Store(0, Local0) + Store (0x07, LDN) + If (LOr(IO2L, IO2H)) { + If (LOr(ACTR, ACT2)) { Store (0x0F, Local0) } - ElseIf (LOr (IO1H, IO1L)) - { + Else { Store (0x0D, Local0) } - EXCM () - Return (Local0) } + EXCM () + Return (Local0) + } - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (HWPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, HWPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, HWPW) - EXCM () + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x02, 0x02, IO0) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x07, LDN) + Store(IO2H, Local0) + Store(IO2L, Local1) + Store(IRQ1, Local2) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x0B, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IRQ1, Local2) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + Return (CRS) + } - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + } + #endif - If (Local2) { - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - } - Return (CRS) + /* ==== Suspend LED control if it is connected to the SuperIO ==== */ + Method (SLED, 1) { + ENCM () + Store (9, LDN) + Store(OPT4, Local0) + And(Local0, 63, Local0) + Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + EXCM () + } + + /* ===== Power LED control if it is connected to the SuperIO ===== */ + Method (PLED, 1) { + ENCM () + Store (8, LDN) + Store(OPT4, Local0) + And(Local0, 63, Local0) + Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + EXCM () + } + + #ifndef NO_W83627HF_HWMON + /* ====================== Hardware Monitor ======================= */ + Device (HMON) { + Name (_HID, EisaId ("PNP0C02")) // TODO: find better matching ID + Name (_STR, Unicode("W83627 Hardware Monitor")) + Name (_UID, "w83627hf-hwmon") + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x0B, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) } + EXCM () + Return (Local0) } - #endif - /* Returns the wake source register. - It is cleared after reading. - Bit 0: Keyboard wake-up event - Bit 1: Mouse wake-up event - Bit 2: Power button event - Bit 3: CIR wake-up event - Bit 4: Power loss event - Bit 5: VSB power loss status - */ - Method (WAKS) { + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } ENCM () - Store (0x0A, LDN) - Store (CRE3, Local0) + Store (HWPW, Local0) EXCM () - Return (Local0) + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, HWPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, HWPW) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x0B, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IRQ1, Local2) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + } + Return (CRS) } } + #endif + + /* Returns the wake source register. + It is cleared after reading. + Bit 0: Keyboard wake-up event + Bit 1: Mouse wake-up event + Bit 2: Power button event + Bit 3: CIR wake-up event + Bit 4: Power loss event + Bit 5: VSB power loss status + */ + Method (WAKS) { + ENCM () + Store (0x0A, LDN) + Store (CRE3, Local0) + EXCM () + Return (Local0) + } } From gerrit at coreboot.org Sat Nov 5 23:43:10 2011 From: gerrit at coreboot.org (Christoph Grenz (christophg+cb@grenz-bonn.de)) Date: Sat, 5 Nov 2011 23:43:10 +0100 Subject: [coreboot] Patch set updated for coreboot: 4855348 w83627hf: multiple fixes and enhancements in ASL include References: Message-ID: Christoph Grenz (christophg+cb at grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/357 -gerrit commit 4855348c4090ff1709e412432ad0846c0343306e Author: Christoph Grenz Date: Sat Nov 5 23:39:20 2011 +0100 w83627hf: multiple fixes and enhancements in ASL include Fix multiple copy&paste errors and some other bugs in devtree.asl. Redesign ENCM method to enter configuration mode and set LDN by parameter. Reordered and commented some statements to make the code a bit more readable. Add an ifdef to enable never showing the keyboard controller as disabled, which seems to cause bugs at least with some Linux kernels. Remove keyboard controller IO regions from PS/2 mouse device as e.g. Linux infers them from the keyboard controller device. Change-Id: I44611339fabe31a8a584a3e6bd225082bfdd0b8e Signed-off-by: Christoph Grenz --- src/superio/winbond/w83627hf/devtree.asl | 457 +++++++++++++---------------- 1 files changed, 205 insertions(+), 252 deletions(-) diff --git a/src/superio/winbond/w83627hf/devtree.asl b/src/superio/winbond/w83627hf/devtree.asl index ddac22e..4fe6958 100644 --- a/src/superio/winbond/w83627hf/devtree.asl +++ b/src/superio/winbond/w83627hf/devtree.asl @@ -51,6 +51,9 @@ * NO_W83627HF_MIDI: don't expose the MIDI port * NO_W83627HF_HWMON: don't expose the hardware monitor as * PnP "Motherboard Ressource" + * W83627HF_KBC_COMPAT: show the keyboard controller and the PS/2 mouse as + * enabled if it is disabled but an address is assigned + * to it. This may be neccessary in some cases. * * Datasheet: "W83627HF/F WINBOND I/O" rev. 6.0 * http://www.itox.com/pages/support/wdt/W83627HF.pdf @@ -146,19 +149,27 @@ Device(SIO) { OPTA, 8 } - Name (_CRS, ResourceTemplate () { + Method (_CRS) + { + Return (ResourceTemplate () { IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) /* Announce the used I/O ports to the OS */ IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) /* this port is used in some configurations, so announce it to be sure */ - }) + }) + } /* Enter configuration mode (and aquire mutex) Method must be run before accesssing the configuration region. + Parameter is the LDN which should be accessed. Values >= 0xFF mean + no LDN switch should be done. */ - Method (ENCM) + Method (ENCM, 1) { Acquire (CRMX, 0xFFFF) Store (0x87, ADDR) Store (0x87, ADDR) + If (LLess(Arg0, 0xFF)) { + Store(Arg0, LDN) + } } /* Exit configuration mode (and release mutex) @@ -166,13 +177,13 @@ Device(SIO) { */ Method (EXCM) { - Release (CRMX) Store (0xAA, ADDR) + Release (CRMX) } /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ Method (_PSC) { - ENCM () + ENCM (0xFF) Store (IPD, Local0) EXCM () If (Local0) { Return (2) } @@ -181,14 +192,14 @@ Device(SIO) { /* PM: Switch to D0 by setting IPD low */ Method (_PS0) { - ENCM () + ENCM (0xFF) Store (Zero, IPD) EXCM () } /* PM: Switch to D2 by setting IPD high */ Method (_PS2) { - ENCM () + ENCM (0xFF) Store (One, IPD) EXCM () } @@ -204,8 +215,7 @@ Device(SIO) { /* Initialization method: Should be run once on boot If FDC is active, enumerate all connected devices */ Method (_INI) { - ENCM () - Store (0x00, LDN) + ENCM (0) Store (ACTR, Local0) Store (IO1H, Local1) Store (IO1L, Local2) @@ -222,8 +232,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM () - Store (0x00, LDN) + ENCM (0) If (ACTR) { Store (0x0F, Local0) } @@ -235,30 +244,34 @@ Device(SIO) { Return (Local0) } + /* Current power state (Returns 1 if LDN in power saving mode, + * 2 if whole chip is powered down), 0 else + */ Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM () + ENCM (0xFF) Store (FDPW, Local0) EXCM () If (Local0) { Return (1) } Else { Return (0) } } + /* Disable power saving mode */ Method (_PS0) { - ENCM () + ENCM (0xFF) Store (Zero, FDPW) EXCM () } + /* Enable power saving mode */ Method (_PS1) { - ENCM () + ENCM (0xFF) Store (One, FDPW) EXCM () } Method (_DIS) { - ENCM () - Store (0x00, LDN) + ENCM (0) Store (Zero, ACTR) EXCM () } @@ -266,38 +279,41 @@ Device(SIO) { Method (_CRS) { Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x06, IO0) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x07, IO0) IRQNoFlags () {6} DMA (Compatibility, NotBusMaster, Transfer8) {2} }) - ENCM () - Store (0x00, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) + + /* Get IO port info */ + ENCM (0) + Store(IO1L, Local0) + Store(IO1H, Local1) EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + /* Calculate full IO port address */ + Or(ShiftLeft(Local1, 8), Local0, Local0) + + /* Modify the resource template and return it */ CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMIN) Store (Local0, IMAX) - Return (CRS) } - Name (_PRS, ResourceTemplate () + Method (_PRS) { - StartDependentFnNoPri () + Return (ResourceTemplate () { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - } - EndDependentFn () - }) + StartDependentFnNoPri () + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x07) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + } + EndDependentFn () + }) + } #ifndef NO_W83627HF_FDC_ENUM Name(_FDE, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) @@ -371,23 +387,19 @@ Device(SIO) { Method (_SRS, 1, Serialized) { Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 6, IO0) - IO (Decode16, 0, 0, 1, 1, IO1) + IO (Decode16, 0, 0, 1, 7, IO0) IRQNoFlags (IRQ0) {} DMA (Compatibility, NotBusMaster, Transfer8, DMA0) {} }) CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO1._MIN, IOA1) CreateByteField (Arg0, IRQ0._INT, IRQL) CreateByteField (Arg0, DMA0._DMA, DMCH) Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) - ENCM () - Store (0, LDN) - Store (Local1, IO1H) + ENCM (0) Store (Local0, IO1L) + Store (Local1, IO1H) Store (One, ACTR) EXCM () @@ -407,8 +419,7 @@ Device(SIO) { Method (MODE, 1) { And(Arg0, 0x07, Local0) - ENCM () - Store (0x01, LDN) + ENCM (1) And(OPT1, 0x3, Local1) Or(Local1, Local0, OPT1) EXCM() @@ -419,8 +430,7 @@ Device(SIO) { /* Deactivate DMA, even if set by BIOS. We don't announce it through _CRS and it's only useful in ECP mode which we don't support at the moment. */ - ENCM () - Store (0x01, LDN) + ENCM (1) Store (0x04, DMA0) EXCM () } @@ -428,8 +438,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM () - Store (0x01, LDN) + ENCM (1) And(OPT1, 0x3, Local1) If (ACTR) { If (LNotEqual(Local1, 2)) { @@ -449,26 +458,25 @@ Device(SIO) { Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM () + ENCM (0xFF) Store (PRPW, Local0) EXCM () If (Local0) { Return (1) } Else { Return (0) } } Method (_PS0) { - ENCM () + ENCM (0xFF) Store (Zero, PRPW) EXCM () } Method (_PS1) { - ENCM () + ENCM (0xFF) Store (One, PRPW) EXCM () } Method (_DIS) { - ENCM () - Store (0x01, LDN) + ENCM (1) Store (Zero, ACTR) EXCM () } @@ -486,25 +494,24 @@ Device(SIO) { CreateByteField (CRS, IO0._LEN, IOLE) CreateWordField (CRS, IRQX._INT, IRQW) - ENCM () - Store (0x01, LDN) + /* Get device settings */ + ENCM (1) Store (IO1L, Local0) Store (IO1H, Local1) Store (OPT1, Local2) Store (IRQ0, Local5) EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local1) + /* Calculate IO port and modify template */ + Or(ShiftLeft(Local1, 8), Local0, Local0) + Store(Local1, IOP0) + Store(Local1, IOR0) + /* Set align and length based on active parallel port mode */ And(Local2, 0x3, Local3) And(Local2, 0x4, Local4) If (Local4) { Store(0x04, IOAL) } - - Store(Local1, IOP0) - Store(Local1, IOR0) - If (LEqual (Local0, 0xBC)) { Store (0x04, IOLE) @@ -513,10 +520,10 @@ Device(SIO) { { Store (0x08, IOLE) } - + /* Calculate IRQ bitmap */ Store (One, Local0) ShiftLeft (Local0, Local5, IRQW) - + /* Return resource template */ Return (CRS) } @@ -579,23 +586,20 @@ Device(SIO) { } Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) - ENCM () - Store (0x01, LDN) - Store (Local1, IO1H) + ENCM (1) + /* IO port */ Store (Local0, IO1L) - /*Mode*/ + Store (Local1, IO1H) + /* Mode */ Store (OPT1, Local3) And (Local3, 0xF8, Local3) Or (Local2, Local3, OPT1) - /*DMA off*/ + /* DMA off */ Store (0x04, DMA0) - /*IRQ*/ - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) - Store (Local3, IRQ0) - /*Activate*/ + /* IRQ */ + Subtract(FindSetLeftBit (IRQL), 1, IRQ0) + /* Activate */ Store (One, ACTR) EXCM () } @@ -612,8 +616,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM () - Store (0x02, LDN) + ENCM (2) If (ACTR) { Store (0x0F, Local0) } @@ -628,27 +631,26 @@ Device(SIO) { Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM () + ENCM (0xFF) Store (UAPW, Local0) EXCM () If (Local0) { Return (1) } Else { Return (0) } } Method (_PS0) { - ENCM () + ENCM (0xFF) Store (Zero, UAPW) EXCM () } Method (_PS1) { - ENCM () + ENCM (0xFF) Store (One, UAPW) EXCM () } Method (_DIS) { - ENCM () - Store (0x02, LDN) + ENCM (2) Store (Zero, ACTR) EXCM () } @@ -659,14 +661,12 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) IRQNoFlags (IRQX) {6} }) - ENCM () - Store (0x02, LDN) - Store(IO1H, Local1) + ENCM (2) Store(IO1L, Local0) + Store(IO1H, Local1) Store(IRQ0, Local2) EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) Store (Local0, IMIN) @@ -715,15 +715,12 @@ Device(SIO) { CreateByteField (Arg0, IRQX._INT, IRQL) Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + Subtract(FindSetLeftBit (IRQL), 1, Local3) - ENCM () - Store (2, LDN) - Store (Local1, IO1H) + ENCM (2) Store (Local0, IO1L) + Store (Local1, IO1H) Store (Local3, IRQ0) Store (One, ACTR) EXCM () @@ -741,8 +738,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM () - Store (0x03, LDN) + ENCM (3) If (LNot(And(OPT2, 0x30))) { If (ACTR) { @@ -760,27 +756,26 @@ Device(SIO) { Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM () + ENCM (0xFF) Store (UBPW, Local0) EXCM () If (Local0) { Return (1) } Else { Return (0) } } Method (_PS0) { - ENCM () + ENCM (0xFF) Store (Zero, UBPW) EXCM () } Method (_PS1) { - ENCM () + ENCM (0xFF) Store (One, UBPW) EXCM () } Method (_DIS) { - ENCM () - Store (0x03, LDN) + ENCM (3) Store (Zero, ACTR) EXCM () } @@ -791,14 +786,12 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) IRQNoFlags (IRQX) {6} }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) + ENCM (3) Store(IO1L, Local0) + Store(IO1H, Local1) Store(IRQ0, Local2) EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) Store (Local0, IMIN) @@ -847,15 +840,12 @@ Device(SIO) { CreateByteField (Arg0, IRQX._INT, IRQL) Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + Subtract(FindSetLeftBit (IRQL), 1, Local3) - ENCM () - Store (3, LDN) - Store (Local1, IO1H) + ENCM (3) Store (Local0, IO1L) + Store (Local1, IO1H) Store (Local3, IRQ0) Store (One, ACTR) EXCM () @@ -873,8 +863,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM () - Store (0x03, LDN) + ENCM (3) If (And(OPT2, 0x30)) { If (ACTR) { @@ -892,27 +881,26 @@ Device(SIO) { Method (_PSC) { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM () + ENCM (0xFF) Store (UBPW, Local0) EXCM () If (Local0) { Return (1) } Else { Return (0) } } Method (_PS0) { - ENCM () + ENCM (0xFF) Store (Zero, UBPW) EXCM () } Method (_PS1) { - ENCM () + ENCM (0xFF) Store (One, UBPW) EXCM () } Method (_DIS) { - ENCM () - Store (0x03, LDN) + ENCM (3) Store (Zero, ACTR) EXCM () } @@ -923,14 +911,12 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) IRQNoFlags (IRQX) {6} }) - ENCM () - Store (0x03, LDN) + ENCM (3) Store(IO1H, Local1) Store(IO1L, Local0) Store(IRQ0, Local2) EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) Store (Local0, IMIN) @@ -979,15 +965,12 @@ Device(SIO) { CreateByteField (Arg0, IRQX._INT, IRQL) Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + Subtract(FindSetLeftBit (IRQL), 1, Local3) - ENCM () - Store (3, LDN) - Store (Local1, IO1H) + ENCM (3) Store (Local0, IO1L) + Store (Local1, IO1H) Store (Local3, IRQ0) Store (One, ACTR) EXCM () @@ -997,7 +980,8 @@ Device(SIO) { #ifndef NO_W83627HF_CIR /* ========================= Consumer IR ========================= */ - Device (CIR0) { + Device (CIR0) + { Name (_HID, EisaId ("WEC1022")) /* Should be the correct one */ Name (_UID, "w83627hf-cir") Name (_STR, Unicode("Winbond Consumer Infrared Transceiver")) @@ -1005,8 +989,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM () - Store (0x06, LDN) + ENCM (6) If (ACTR) { Store (0x0F, Local0) } @@ -1020,8 +1003,7 @@ Device(SIO) { Method (_DIS) { - ENCM () - Store (0x06, LDN) + ENCM (6) Store (Zero, ACTR) EXCM () } @@ -1032,14 +1014,12 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) IRQNoFlags (IRQX) {6} }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) + ENCM (6) Store(IO1L, Local0) + Store(IO1H, Local1) Store(IRQ0, Local2) EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) Store (Local0, IMIN) @@ -1072,15 +1052,12 @@ Device(SIO) { CreateByteField (Arg0, IRQX._INT, IRQL) Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + Subtract(FindSetLeftBit (IRQL), 1, Local3) - ENCM () - Store (6, LDN) - Store (Local1, IO1H) + ENCM (6) Store (Local0, IO1L) + Store (Local1, IO1H) Store (Local3, IRQ0) Store (One, ACTR) EXCM () @@ -1090,22 +1067,25 @@ Device(SIO) { #ifndef NO_W83627HF_KBC /* ===================== Keyboard Controller ===================== */ - Device (KBD0) { + Device (KBD0) + { Name (_HID, EisaId ("PNP0303")) - Name (_CID, 0x0B03D041) Name (_UID, "w83627hf-kbc") Method (_STA) { Store (0x00, Local0) - ENCM () - Store (0x05, LDN) + ENCM (5) If (ACTR) { Store (0x0F, Local0) } ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) { + #ifdef W83627HF_KBC_COMPAT + Store (0x0F, Local0) + #else Store (0x0D, Local0) + #endif } EXCM () Return (Local0) @@ -1113,8 +1093,7 @@ Device(SIO) { Method (_DIS) { - ENCM () - Store (0x05, LDN) + ENCM (5) Store (Zero, ACTR) EXCM () Notify(PS2M, 1) @@ -1123,23 +1102,20 @@ Device(SIO) { Method (_CRS) { Name (CRS, ResourceTemplate () { + IRQNoFlags (IRQX) {} IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) - IRQNoFlags (IRQX) {} }) - ENCM () - Store (0x05, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IO2H, Local2) - Store(IO2L, Local3) + ENCM (5) + Store(IO1L, Local0) + Store(IO1H, Local1) + Store(IO2L, Local2) + Store(IO2H, Local3) Store(IRQ0, Local4) EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) - ShiftLeft(Local2, 8, Local2) - Or (Local1, Local0, Local0) + Or(ShiftLeft(Local1, 8), Local0, Local0) + Or(ShiftLeft(Local3, 8), Local2, Local2) CreateWordField (CRS, IO0._MIN, IMIN) Store (Local0, IMIN) @@ -1161,9 +1137,9 @@ Device(SIO) { Name (_PRS, ResourceTemplate () { StartDependentFn (0,0) { + IRQNoFlags () {1} IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} } EndDependentFn() }) @@ -1171,50 +1147,50 @@ Device(SIO) { Method (_SRS, 1, Serialized) { Name (TMPL, ResourceTemplate () { + IRQNoFlags (IRQX) {} IO (Decode16, 0, 0, 1, 1, IO0) IO (Decode16, 0, 0, 1, 1, IO1) - IRQNoFlags (IRQX) {} }) CreateWordField (Arg0, IO0._MIN, IOA0) CreateWordField (Arg0, IO1._MIN, IOA1) CreateByteField (Arg0, IRQX._INT, IRQL) Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) - Divide(IOA1, 256, Local2, Local3) - ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local4) - Subtract (Local4, 0x01, Local4) + Subtract(FindSetLeftBit (IRQL), 1, Local4) - ENCM () - Store (5, LDN) - Store (Local1, IO1H) + ENCM (5) Store (Local0, IO1L) - Store (Local3, IO2H) + Store (Local1, IO1H) Store (Local2, IO2L) - Store (Local3, IRQ0) + Store (Local3, IO2H) + Store (Local4, IRQ0) Store (One, ACTR) EXCM () + Notify(PS2M, 1) } } #ifndef NO_W83627HF_PS2M - Device (PS2M) { + Device (PS2M) + { Name (_HID, EisaId ("PNP0F13")) Name (_UID, "w83627hf-ps2m") Method (_STA) { Store (0x00, Local0) - ENCM () - Store (0x05, LDN) + ENCM (5) If (LAnd(ACTR, IRQ1) ) { Store (0x0F, Local0) } ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) { + #ifdef W83627HF_KBC_COMPAT + Store (0x0F, Local0) + #else Store (0x0D, Local0) + #endif } EXCM () Return (Local0) @@ -1222,8 +1198,7 @@ Device(SIO) { Method (_DIS) { - ENCM () - Store (0x05, LDN) + ENCM (5) Store (Zero, IRQ1) EXCM () } @@ -1232,32 +1207,10 @@ Device(SIO) { { Name (CRS, ResourceTemplate () { IRQNoFlags (IRQX) {} - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) }) - ENCM () - Store (0x05, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IO2H, Local2) - Store(IO2L, Local3) + ENCM (5) Store(IRQ1, Local4) EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) - - ShiftLeft(Local2, 8, Local2) - Or (Local1, Local0, Local0) - - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) - - CreateWordField (CRS, IO1._MIN, I1MI) - Store (Local2, I1MI) - CreateWordField (CRS, IO1._MAX, I1MA) - Store (Local2, I1MA) CreateWordField (CRS, IRQX._INT, IRQW) Store (One, Local5) @@ -1272,7 +1225,7 @@ Device(SIO) { IRQNoFlags () {12} } StartDependentFn (2,0) { - IRQNoFlags () {1,3,4,5,6,7,9,10,11,12} + IRQNoFlags () {1,3,4,5,6,7,9,10,11} } EndDependentFn() }) @@ -1284,14 +1237,11 @@ Device(SIO) { }) CreateByteField (Arg0, IRQX._INT, IRQL) - FindSetLeftBit (IRQL, Local0) - Subtract (Local0, 0x01, Local0) + Subtract(FindSetLeftBit (IRQL), 1, Local0) - ENCM () - Store (5, LDN) + ENCM (5) Store (Local0, IRQ1) /* Only activates if KBD is active */ - Store (One, ACTR) EXCM () } } @@ -1300,15 +1250,15 @@ Device(SIO) { #ifndef NO_W83627HF_GAME /* ========================== Game Port ========================== */ - Device (GAME) { + Device (GAME) + { Name (_HID, EisaId ("PNPB02F")) Name (_STR, Unicode ("Joystick/Game Port")) Name (_UID, "w83627hf-game") Method (_STA) { - ENCM () Store(0, Local0) - Store (0x07, LDN) + ENCM (7) If (LOr(IO1L, IO1H)) { If (LOr(ACTR, ACT1)) { Store (0x0F, Local0) @@ -1327,18 +1277,17 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) IRQNoFlags (IRQX) {} }) - ENCM () - Store (0x07, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) + ENCM (7) + Store(IO1L, Local0) + Store(IO1H, Local1) Store(IRQ0, Local2) EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + + Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMIN) Store (Local0, IMAX) If (Local2) { @@ -1355,15 +1304,16 @@ Device(SIO) { #ifndef NO_W83627HF_MIDI /* ========================== MIDI Port ========================== */ - Device (MIDI) { + Device (MIDI) + { Name (_HID, EisaId ("PNPB006")) Name (_STR, Unicode ("MPU-401 Compatible MIDI Port")) Name (_UID, "w83627hf-midi") - Method (_STA) { - ENCM () + Method (_STA) + { Store(0, Local0) - Store (0x07, LDN) + ENCM (7) If (LOr(IO2L, IO2H)) { If (LOr(ACTR, ACT2)) { Store (0x0F, Local0) @@ -1382,18 +1332,17 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x02, 0x02, IO0) IRQNoFlags (IRQX) {} }) - ENCM () - Store (0x07, LDN) - Store(IO2H, Local0) - Store(IO2L, Local1) + ENCM (7) + Store(IO2L, Local0) + Store(IO2H, Local1) Store(IRQ1, Local2) EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + + Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMIN) Store (Local0, IMAX) If (Local2) { @@ -1409,9 +1358,9 @@ Device(SIO) { #endif /* ==== Suspend LED control if it is connected to the SuperIO ==== */ - Method (SLED, 1) { - ENCM () - Store (9, LDN) + Method (SLED, 1) + { + ENCM (9) Store(OPT4, Local0) And(Local0, 63, Local0) Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) @@ -1419,9 +1368,9 @@ Device(SIO) { } /* ===== Power LED control if it is connected to the SuperIO ===== */ - Method (PLED, 1) { - ENCM () - Store (8, LDN) + Method (PLED, 1) + { + ENCM (8) Store(OPT4, Local0) And(Local0, 63, Local0) Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) @@ -1430,7 +1379,8 @@ Device(SIO) { #ifndef NO_W83627HF_HWMON /* ====================== Hardware Monitor ======================= */ - Device (HMON) { + Device (HMON) + { Name (_HID, EisaId ("PNP0C02")) // TODO: find better matching ID Name (_STR, Unicode("W83627 Hardware Monitor")) Name (_UID, "w83627hf-hwmon") @@ -1438,8 +1388,7 @@ Device(SIO) { Method (_STA) { Store (0x00, Local0) - ENCM () - Store (0x0B, LDN) + ENCM (11) If (ACTR) { Store (0x0F, Local0) } @@ -1451,22 +1400,27 @@ Device(SIO) { Return (Local0) } - Method (_PSC) { + Method (_PSC) + { Store(^^_PSC (), Local0) If (Local0) { Return (Local0) } - ENCM () + ENCM (0xFF) Store (HWPW, Local0) EXCM () If (Local0) { Return (1) } Else { Return (0) } } - Method (_PS0) { - ENCM () + + Method (_PS0) + { + ENCM (0xFF) Store (Zero, HWPW) EXCM () } - Method (_PS1) { - ENCM () + + Method (_PS1) + { + ENCM (0xFF) Store (One, HWPW) EXCM () } @@ -1477,18 +1431,17 @@ Device(SIO) { IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0) IRQNoFlags (IRQX) {} }) - ENCM () - Store (0x0B, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) + ENCM (11) + Store(IO1L, Local0) + Store(IO1H, Local1) Store(IRQ1, Local2) EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + + Or(ShiftLeft(Local1, 8), Local0, Local0) CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMIN) Store (Local0, IMAX) If (Local2) { @@ -1510,9 +1463,9 @@ Device(SIO) { Bit 4: Power loss event Bit 5: VSB power loss status */ - Method (WAKS) { - ENCM () - Store (0x0A, LDN) + Method (WAKS) + { + ENCM (10) Store (CRE3, Local0) EXCM () Return (Local0) From patrick at georgi-clan.de Sun Nov 6 11:31:29 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sun, 06 Nov 2011 11:31:29 +0100 Subject: [coreboot] buildgcc broken In-Reply-To: <1320520561.3771.12.camel@Debian.lan> References: <1320520561.3771.12.camel@Debian.lan> Message-ID: <4EB66201.1020603@georgi-clan.de> Am Sa 05 Nov 2011 20:16:01 CET schrieb Nils: > I tried to test Patricks new patch "Change Id9e6b204: buildgcc: > Explicitely state CC everywhere" but crossgcc doesn't compile at al. > > The problem started after commit: "Change I1b7d5b89: buildgcc: Update > coreboot reference toolchain to gcc 4.6.2" > > The messages are: > nils at Debian:~/coreboot$ make crossgcc > Welcome to the coreboot cross toolchain builder v1.07 (November 1st, > 2011) > > Invalid option Does http://review.coreboot.org/#change,417 fix it for you? Patrick From gerrit at coreboot.org Sun Nov 6 18:06:29 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:06:29 +0100 Subject: [coreboot] Patch merged into coreboot/master: 1b5519c buildgcc: Fix wrapper Makefile References: Message-ID: the following patch was just integrated into master: commit 1b5519c088120550324b21ab5d15fee2cf6a3308 Author: Patrick Georgi Date: Sat Nov 5 22:30:56 2011 +0100 buildgcc: Fix wrapper Makefile buildgcc moved from building gdb by default (with opt-out) to gdb being optional. Adapt Makefile so it works again Change-Id: I663a8c70db4f7b5d07456fb67a223dbb2de2c133 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Sat Nov 5 22:43:19 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:06:27 2011, giving +2 See http://review.coreboot.org/417 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:12:27 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:12:27 +0100 Subject: [coreboot] Patch merged into coreboot/master: e3328fc w83627hf: drop Scope(\_SB) from ASL include References: Message-ID: the following patch was just integrated into master: commit e3328fc1773c0c943d1ad78b02fd1c2d36d2c13e Author: Christoph Grenz Date: Sat Nov 5 22:14:41 2011 +0100 w83627hf: drop Scope(\_SB) from ASL include Drop explicit Scope(\_SB) from devtree.asl as it forces the SuperIO to appear as child of the root device. devtree.asl then needs to be included at a reasonable position inside the \_SB device tree. Change-Id: I72a57eddc5ec5f9763fdf789094a7be042758256 Signed-off-by: Christoph Grenz Build-Tested: build bot (Jenkins) at Sat Nov 5 22:53:49 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:10:19 2011, giving +2 See http://review.coreboot.org/298 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:17:14 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:17:14 +0100 Subject: [coreboot] Patch merged into coreboot/master: 4855348 w83627hf: multiple fixes and enhancements in ASL include References: Message-ID: the following patch was just integrated into master: commit 4855348c4090ff1709e412432ad0846c0343306e Author: Christoph Grenz Date: Sat Nov 5 23:39:20 2011 +0100 w83627hf: multiple fixes and enhancements in ASL include Fix multiple copy&paste errors and some other bugs in devtree.asl. Redesign ENCM method to enter configuration mode and set LDN by parameter. Reordered and commented some statements to make the code a bit more readable. Add an ifdef to enable never showing the keyboard controller as disabled, which seems to cause bugs at least with some Linux kernels. Remove keyboard controller IO regions from PS/2 mouse device as e.g. Linux infers them from the keyboard controller device. Change-Id: I44611339fabe31a8a584a3e6bd225082bfdd0b8e Signed-off-by: Christoph Grenz Build-Tested: build bot (Jenkins) at Sat Nov 5 23:53:42 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:17:10 2011, giving +2 See http://review.coreboot.org/357 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:20:14 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:20:14 +0100 Subject: [coreboot] Patch merged into coreboot/master: ef31a98 Fix typo References: Message-ID: the following patch was just integrated into master: commit ef31a985c4c922c8c87faa907768c2c4fc3e887e Author: Patrick Georgi Date: Sat Oct 15 01:03:16 2011 +0200 Fix typo Change-Id: I195ea15ddbc725091e32191fac3b84d01b456580 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Sat Nov 5 17:16:09 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:20:07 2011, giving +2 See http://review.coreboot.org/410 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:20:58 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:20:58 +0100 Subject: [coreboot] Patch merged into coreboot/master: bfbba64 Inline Makefile.bootblock.inc References: Message-ID: the following patch was just integrated into master: commit bfbba6462f66aaf91af3c59fdb89ee91676351b4 Author: Patrick Georgi Date: Tue Nov 1 18:55:59 2011 +0100 Inline Makefile.bootblock.inc This was split out when we had separate rules for big bootblock. Change-Id: Id0a117f6996fb6bdef7bf97e7d80c36f5dec0ad7 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Sat Nov 5 12:44:42 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:20:48 2011, giving +2 See http://review.coreboot.org/404 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:21:42 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:21:42 +0100 Subject: [coreboot] Patch merged into coreboot/master: 4e95b5a abuild: Avoid race condition when running abuild parallely References: Message-ID: the following patch was just integrated into master: commit 4e95b5a8d0a0c82705ff8cadf1f316278dc02dd1 Author: Patrick Georgi Date: Sat Nov 5 12:47:13 2011 +0100 abuild: Avoid race condition when running abuild parallely By moving the just-created file away, parallel runs of abuild might break. Change-Id: I03368f00e9b11dad4c80d41279970e28debc7ed5 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Sat Nov 5 15:00:05 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:21:40 2011, giving +2 See http://review.coreboot.org/405 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:22:32 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:22:32 +0100 Subject: [coreboot] Patch merged into filo/master: 4162c3b Allow using binary libpayload References: Message-ID: the following patch was just integrated into master: commit 4162c3bbf3d0be1cf2cf71ab408d3b65de75a0bc Author: Patrick Georgi Date: Sat Nov 5 01:18:53 2011 +0100 Allow using binary libpayload We already test for LIBPAYLOAD_PREFIX in the Makefile's build codepath. Also test for it in the configuration codepath, so a prebuilt libpayload can be used for FILO. Change-Id: I8f2aa102f1e41f698bfd4061c5e7e7b8082c885e Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Sat Nov 5 15:01:34 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:22:26 2011, giving +2 See http://review.coreboot.org/403 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:23:35 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:23:35 +0100 Subject: [coreboot] Patch merged into coreboot/master: ee5a22c abuild: Refactor parallelization support References: Message-ID: the following patch was just integrated into master: commit ee5a22cce013e20eda3fb39152584382327c1065 Author: Patrick Georgi Date: Sat Nov 5 12:55:18 2011 +0100 abuild: Refactor parallelization support Use MAKEFLAGS to propagate the parallelization configuration to the build Change-Id: If90ed446edd8e6dc679d284ee9db7a24269edd36 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Sat Nov 5 15:10:46 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:23:30 2011, giving +2 See http://review.coreboot.org/406 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:24:28 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:24:28 +0100 Subject: [coreboot] Patch merged into coreboot/master: 6e67db0 abuild: Write XML/JUnit files per board References: Message-ID: the following patch was just integrated into master: commit 6e67db0f0212f219c0eca3cae45ceff0a1abd79a Author: Patrick Georgi Date: Sat Nov 5 13:21:14 2011 +0100 abuild: Write XML/JUnit files per board Write them per-board and merge them after everything is done. This prepares for build parallelization. Change-Id: Ia4e7ce03473bcf8861fb9ae06e9c1270292401ac Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Sat Nov 5 15:20:05 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:24:25 2011, giving +2 See http://review.coreboot.org/407 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:25:30 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:25:30 +0100 Subject: [coreboot] Patch merged into coreboot/master: 8258504 kconfig: Use more collision resistant temporary filenames References: Message-ID: the following patch was just integrated into master: commit 82585042cc979c553aee4d9e88665b4b401d342f Author: Patrick Georgi Date: Sat Nov 5 14:39:56 2011 +0100 kconfig: Use more collision resistant temporary filenames kconfig creates reasonably safe filenames for its temporary files except for two of them. Change-Id: I6861f55ae2a5311e3fb7919333ce9af1e39ce78b Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Sat Nov 5 15:30:43 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:25:20 2011, giving +2 See http://review.coreboot.org/408 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:26:29 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:26:29 +0100 Subject: [coreboot] Patch merged into filo/master: 2d71835 Shut down USB before starting Linux References: Message-ID: the following patch was just integrated into master: commit 2d718354199266b4f919b38e68386f0c92dc8d01 Author: Patrick Georgi Date: Sat Nov 5 01:09:47 2011 +0100 Shut down USB before starting Linux Otherwise, if FILO knows EHCI and Linux only knows USB1 controllers, Linux won't find any devices as they're routed to EHCI. Change-Id: I06d046056b9807d660127c28c364abf3852b32a5 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Sat Nov 5 01:13:08 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:26:28 2011, giving +2 See http://review.coreboot.org/402 for details. -gerrit From gerrit at coreboot.org Sun Nov 6 18:44:54 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 6 Nov 2011 18:44:54 +0100 Subject: [coreboot] Patch merged into coreboot/master: fbbbb4a buildgcc: Explicitely state CC everywhere References: Message-ID: the following patch was just integrated into master: commit fbbbb4a66ab9b1c2c22f75b673a7aa233de6e5e0 Author: Patrick Georgi Date: Fri Nov 4 21:30:49 2011 +0100 buildgcc: Explicitely state CC everywhere This should fix issues with the iasl Makefile on Debian and prepares ccache support for buildgcc. Change-Id: Id9e6b2044b159b19bf013ec5c47b60ca1c2f2991 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Nov 4 22:35:18 2011, giving +1 Reviewed-By: Stefan Reinauer at Sun Nov 6 18:44:53 2011, giving +2 See http://review.coreboot.org/399 for details. -gerrit From renework at xs4all.nl Mon Nov 7 00:37:11 2011 From: renework at xs4all.nl (Rene) Date: Mon, 07 Nov 2011 00:37:11 +0100 Subject: [coreboot] ASUS P5B-vm mainboard Message-ID: I want to add this board to coreboot. why? It is probably a case of because its there. I also understand that I'm not going to do this in a couple of days or weeks. ( I wonder if I will be able to get it done at all. There is a lot of low-level stuff which is overwhelming) Of this board The cpu is ????? The socket LGA 775 i haven't seen it yet in the coreboot tree. The super io Winbond W83627DHG (id=0xa0, rev=0x23) at 0x2e is supported. The North-(G965) and Southbridge(i82801H ICH8) not. :-( proc/cpuinfo processor : 1 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Core(TM)2 CPU 6320 @ 1.86GHz stepping : 6 cpu MHz : 1862.000 it is a LGA775 socket. I thought of adding the mainboard/asus/p5b-vm/devicetree.cb first. I use the mainboard/intel/d945clgf as a starting point. Which brings me to a first question. What is de entry for this socket/cpu in devicetree.cb? device lapic_cluster 0 on chip cpu/intel/socket_441 device lapic 0 on end end end Is there a way to generate devicetree.cb from superio and lspci output and other info ? secondly I'm a bit unsure how the keyboard pci info is derived my lspci looks like 00:00.0 Host bridge: Intel Corporation 82P965/G965 Memory Controller Hub (rev 02) 00:01.0 PCI bridge: Intel Corporation 82P965/G965 PCI Express Root Port (rev 02) 00:02.0 VGA compatible controller: Intel Corporation 82G965 Integrated Graphics Controller (rev 02) 00:1a.0 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 (rev 02) 00:1a.1 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 (rev 02) 00:1a.7 USB controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 (rev 02) 00:1b.0 Audio device: Intel Corporation 82801H (ICH8 Family) HD Audio Controller (rev 02) 00:1c.0 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 1 (rev 02) 00:1c.4 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 5 (rev 02) 00:1c.5 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 6 (rev 02) 00:1d.0 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 (rev 02) 00:1d.1 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 (rev 02) 00:1d.2 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 (rev 02) 00:1d.7 USB controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 02) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev f2) 00:1f.0 ISA bridge: Intel Corporation 82801HB/HR (ICH8/R) LPC Interface Controller (rev 02) 00:1f.2 IDE interface: Intel Corporation 82801H (ICH8 Family) 4 port SATA IDE Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801H (ICH8 Family) SMBus Controller (rev 02) 00:1f.5 IDE interface: Intel Corporation 82801H (ICH8 Family) 2 port SATA IDE Controller (rev 02) 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01) 03:00.0 SATA controller: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) 03:00.1 IDE interface: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) 05:01.0 FireWire (IEEE 1394): Texas Instruments TSB43AB22A IEEE-1394a-2000 Controller (PHY/Link) [iOHCI-Lynx] the mainboard/intel/d945clgf/devicetree.cb has device pci 1f.0 on # LPC bridge chip superio/winbond/w83627dhg #######should be for my board device pnp 2e.0 off # Floppy end device pnp 2e.3 off # Parport end What I fail to understand is why these devices(floppy, keyboard, mouse, com and Parport) are not on the 1f.[0-9a-f] in d945clgf/devicetree.cb. But that might be specific for that board. How can I find these for my board? -- Rene From njacobs8 at adsltotaal.nl Wed Nov 2 20:48:54 2011 From: njacobs8 at adsltotaal.nl (Nils) Date: Wed, 02 Nov 2011 20:48:54 +0100 Subject: [coreboot] Patch set updated for coreboot: 7849219 Update coreboot cross toolchain to gcc 4.6.1 In-Reply-To: <4EB044DB.3050200@georgi-clan.de> References: <1319920444.32412.19.camel@Debian.lan> <4EB044DB.3050200@georgi-clan.de> Message-ID: <1320263334.2245.17.camel@Debian.lan> Op dinsdag 01-11-2011 om 20:13 uur [tijdzone +0100], schreef Patrick Georgi: > Am 29.10.2011 22:34, schrieb Nils: > > CC wasn't set and bison and flex were not instaled. > > > > The acpica-unix-20110922/README states that the Makefiles contain > > CC = gcc but only the main acpica-unix-20110922/generate/ > > unix/Makefile.config contains it and it is not used by coreboot. > We better pass CC in from the outside - I want to add ccache support to > buildgcc. > > Also the bison/flex tests: I regularily have the build fail on m4 and > gawk (iirc), too. Maybe all these should be tested for in the buildgcc > script instead. > > > Patrick I'm fine with that. I would be happy to test any patches. Thanks,Nils. From njacobs8 at adsltotaal.nl Sat Nov 5 20:16:01 2011 From: njacobs8 at adsltotaal.nl (Nils) Date: Sat, 05 Nov 2011 20:16:01 +0100 Subject: [coreboot] buildgcc broken Message-ID: <1320520561.3771.12.camel@Debian.lan> Hi Patrick and Stefan, I tried to test Patricks new patch "Change Id9e6b204: buildgcc: Explicitely state CC everywhere" but crossgcc doesn't compile at al. The problem started after commit: "Change I1b7d5b89: buildgcc: Update coreboot reference toolchain to gcc 4.6.2" The messages are: nils at Debian:~/coreboot$ make crossgcc Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011) Invalid option Usage: ./buildgcc [-V] [-c] [-p ] [-d ] [-D ] [-G] [-S] ./buildgcc [-V|--version] ./buildgcc [-h|--help] Options: [-V|--version] print version number and exit [-h|--help] print this help and exit [-c|--clean] remove temporary files before build [-t|--savetemps] don't remove temporary files after build [-j|--jobs ] run jobs in parallel in make [-p|--platform ] target platform to build cross compiler for (defaults to i386-elf) [-d|--directory ] target directory to install cross compiler to (defaults to /home/nils/coreboot/util/crossgcc/xgcc) [-D|--destdir ] destination directory to install cross compiler to (for RPM builds, default unset) [-G|--gdb] build GNU debugger [-S|--scripting] build scripting support for GDB make[1]: *** [build-without-gdb] Error 1 make: *** [crossgcc] Error 2 nils at Debian:~/coreboot$ Thanks, Nils. From njacobs8 at adsltotaal.nl Sun Nov 6 20:21:29 2011 From: njacobs8 at adsltotaal.nl (Nils) Date: Sun, 06 Nov 2011 20:21:29 +0100 Subject: [coreboot] buildgcc broken In-Reply-To: <4EB66201.1020603@georgi-clan.de> References: <1320520561.3771.12.camel@Debian.lan> <4EB66201.1020603@georgi-clan.de> Message-ID: <1320607289.17452.2.camel@Debian.lan> Op zondag 06-11-2011 om 11:31 uur [tijdzone +0100], schreef Patrick Georgi: > Am Sa 05 Nov 2011 20:16:01 CET schrieb Nils: > > I tried to test Patricks new patch "Change Id9e6b204: buildgcc: > > Explicitely state CC everywhere" but crossgcc doesn't compile at al. > > > > The problem started after commit: "Change I1b7d5b89: buildgcc: Update > > coreboot reference toolchain to gcc 4.6.2" > > > > The messages are: > > nils at Debian:~/coreboot$ make crossgcc > > Welcome to the coreboot cross toolchain builder v1.07 (November 1st, > > 2011) > > > > Invalid option > Does http://review.coreboot.org/#change,417 fix it for you? > > > Patrick I tested trunk 643c9e892fab5f73dde566b9ffb73f2f0463d9a7 and that works fine now. Thanks for your efforts. Nils. From peter at stuge.se Mon Nov 7 03:31:53 2011 From: peter at stuge.se (Peter Stuge) Date: Mon, 7 Nov 2011 03:31:53 +0100 Subject: [coreboot] Lenovo T60p 8742 Y19 - Black screen In-Reply-To: References: Message-ID: <20111107023153.25408.qmail@stuge.se> Matias Jose Seco wrote: > builded on the native laptop through Gentoo installed on USB, from an > amd64 (march=native) version: Was your gcc and binutils built with USE=vanilla? If not, it is completely possible that your toolchain produced a broken image. I've had this happen with some gcc versions. > Options chosen other than default: > - Lenovo T60 (p) > - Dont save config options CMOS/NVRAM? That may need to be enabled for image to work. > - mmx,smp,sse,sse2 How did you set this exactly? > Could i do any further check to get the problem? Get a docking station, port replicator or ultrabay superio module, so that you get a serial port, and connect that to another computer. coreboot should output debug information there when starting, and it may be clear what the problem is. Also, does it seem like the system boots? Is there some hard drive access after you power on? And, does caps lock work after you power on? Finally, did you include a VGA BIOS into your coreboot.rom? This is easiest done by configuring the filename in menuconfig. Note that coreboot should not execute the VGA BIOS, the file should only be added. You may need to change the defaults for this. //Peter From gerrit at coreboot.org Mon Nov 7 11:40:56 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 11:40:56 +0100 Subject: [coreboot] Patch merged into coreboot/master: c593fc8 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 References: Message-ID: the following patch was just integrated into master: commit c593fc823a5a2bc3de327fea5f1d44cfec8aec15 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:12 2011 +0100 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl Reviewed-By: Patrick Georgi at Mon Nov 7 11:40:55 2011, giving +2 See http://review.coreboot.org/370 for details. -gerrit From gerrit at coreboot.org Mon Nov 7 13:04:37 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 13:04:37 +0100 Subject: [coreboot] Patch merged into coreboot/master: 16f7f24 in vt8237r_enable(), write function enables only to ISA bridge config space References: Message-ID: the following patch was just integrated into master: commit 16f7f242b6f4c7d3bdd8d4f41a1f2366a861d06f Author: Florian Zumbiehl Date: Tue Nov 1 20:16:16 2011 +0100 in vt8237r_enable(), write function enables only to ISA bridge config space vt8237r_enable() so far wrote the function enable values to the same offset in the config space of every one of the vt8237's functions, even though the register is located in the ISA bridge only. Change-Id: I639586dc238132f5b8d2f320b794948718281b9c Signed-off-by: Florian Zumbiehl Reviewed-By: Patrick Georgi at Mon Nov 7 13:04:36 2011, giving +2 See http://review.coreboot.org/368 for details. -gerrit From svn at coreboot.org Mon Nov 7 16:00:02 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 07 Nov 2011 16:00:02 +0100 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Mon Nov 7 17:47:30 2011 From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net)) Date: Mon, 7 Nov 2011 17:47:30 +0100 Subject: [coreboot] New patch to review for coreboot: 1e93c67 Avoid false detection of SMSC FDC37N972 when Infineon TPM is present References: Message-ID: Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/420 -gerrit commit 1e93c672d9a0464eb3b0b860e82d9c5f7f672872 Author: Jonathan A. Kollasch Date: Mon Nov 7 10:43:05 2011 -0600 Avoid false detection of SMSC FDC37N972 when Infineon TPM is present Change-Id: Ibfb3af4c5d7675a5d4e27021cbb988c2ce00fd9f Signed-off-by: Jonathan A. Kollasch --- util/superiotool/smsc.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index 17925ae..012ffbd 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -844,6 +844,19 @@ static void probe_idregs_smsc_helper(uint16_t port, uint8_t idreg, return; } + /* Infineon TPM causes false match of FDC37N972 */ + if (idreg == DEVICE_ID_REG && revreg == DEVICE_REV_REG && + id == 0x0b && rev == 0x00) { + /* Infineon sets config port in 0x27:0x26, but SMSC does not */ + if (((regval(port, 0x27)<<8)|regval(port, 0x26)) == port) { + if (verbose) + printf(NOTFOUND "id=0x%02x, rev=0x%02x\n", + id, rev); + exit_conf_mode_smsc(port); + return; + } + } + printf("Found %s %s (id=0x%02x, rev=0x%02x) at 0x%x\n", (id == 0x77 ? "ASUS" : "SMSC"), get_superio_name(reg_table, id), id, rev, port); From gerrit at coreboot.org Mon Nov 7 17:49:27 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Mon, 7 Nov 2011 17:49:27 +0100 Subject: [coreboot] Patch set updated for coreboot: 0776ce9 Add code to set the clock speed for Winbond W83627THF/THG. References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/412 -gerrit commit 0776ce9e109aa7decf366022f786d0d8c4699de2 Author: Idwer Vollering Date: Mon Nov 7 17:48:33 2011 +0100 Add code to set the clock speed for Winbond W83627THF/THG. Change-Id: I984404dd1df50b3ba423ac610283b9bf8bca5a31 Signed-off-by: Idwer Vollering --- src/superio/winbond/w83627thg/early_serial.c | 9 +++++++++ src/superio/winbond/w83627thg/w83627thg.h | 2 ++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 559e982..bdb3e07 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -45,3 +45,12 @@ static void inline w83627thg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +void w83627thg_set_clksel_48(device_t dev) { + u8 reg8; + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index 73be544..99ff565 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -34,4 +34,6 @@ #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware monitor */ +void w83627thg_set_clksel_48(device_t dev); + #endif From gerrit at coreboot.org Mon Nov 7 17:58:05 2011 From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net)) Date: Mon, 7 Nov 2011 17:58:05 +0100 Subject: [coreboot] New patch to review for coreboot: 2af661a superiotool: add detection and dump of Infineon SLB9635 TPM References: Message-ID: Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/421 -gerrit commit 2af661acd3e793e6acd5448e34c85da3660eee5b Author: Jonathan A. Kollasch Date: Mon Nov 7 10:56:42 2011 -0600 superiotool: add detection and dump of Infineon SLB9635 TPM Change-Id: If94ea5f45135a4b65bdd37532851fa0ba864bb73 Signed-off-by: Jonathan A. Kollasch --- util/superiotool/Makefile | 2 +- util/superiotool/infineon.c | 79 ++++++++++++++++++++++++++++++++++++++++ util/superiotool/superiotool.h | 6 +++ 3 files changed, 86 insertions(+), 1 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 5cc7650..e7d2f63 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -34,7 +34,7 @@ CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ LDFLAGS += -lz OBJS = superiotool.o serverengines.o ali.o fintek.o ite.o nsc.o nuvoton.o \ - smsc.o winbond.o + smsc.o winbond.o infineon.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/superiotool/infineon.c b/util/superiotool/infineon.c new file mode 100644 index 0000000..da25383 --- /dev/null +++ b/util/superiotool/infineon.c @@ -0,0 +1,79 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2011 Jonathan A. Kollasch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "superiotool.h" + +#define DEVICE_ID_REG 0x20 +#define DEVICE_REV_REG 0x21 + +static const struct superio_registers reg_table[] = { + {0x0b, "SLB9635TT12", { + {NOLDN, NULL, + {0x20,0x21,0x26,0x27,EOT}, + {0x0b,0x00,NANA,NANA,EOT}}, + {0, NULL, + {0x30,0x38,0x60,0x61,0x70,0x71,0xf1,0xf2,0xf3,0xf4,0xf5,EOT}, + {0x00,0x00,NANA,NANA,0x00,0x02,0xd1,0x15,0x0b,0x00,NANA,EOT}}, + {EOT}}}, + {EOT} +}; + +/* same as some SMSC */ +static void enter_conf_mode_infineon(uint16_t port) +{ + OUTB(0x55, port); +} + +static void exit_conf_mode_infineon(uint16_t port) +{ + OUTB(0xaa, port); +} + +void probe_idregs_infineon(uint16_t port) +{ + uint8_t rev, devid; + + probing_for("Infinieon", "", port); + + enter_conf_mode_infineon(port); + + devid = regval(port, DEVICE_ID_REG); + rev = regval(port, DEVICE_REV_REG); + + if (superio_unknown(reg_table, devid)) { + if (verbose) + printf(NOTFOUND "id=0x%02x, rev=0x%02x\n", devid, rev); + exit_conf_mode_infineon(port); + return; + } + + printf("Found Infineon %s (id=0x%02x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, devid), devid, rev, port); + chip_found = 1; + + dump_superio("Infineon", reg_table, port, devid, LDN_SEL); + + exit_conf_mode_infineon(port); +} + +void print_infineon_chips(void) +{ + print_vendor_chips("Infineon", reg_table); +} diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index f705a58..5583ec5 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -195,6 +195,10 @@ void probe_idregs_fintek(uint16_t port); void probe_idregs_fintek_alternative(uint16_t port); void print_fintek_chips(void); +/* infineon.c */ +void probe_idregs_infineon(uint16_t port); +void print_infineon_chips(void); + /* ite.c */ void probe_idregs_ite(uint16_t port); void print_ite_chips(void); @@ -243,6 +247,7 @@ static const struct { {probe_idregs_amd, {0xaa, EOT}}, #endif {probe_idregs_serverengines, {0x2e, EOT}}, + {probe_idregs_infineon, {0x2e, 0x4e}}, }; /** Table of functions to print out supported Super I/O chips. */ @@ -261,6 +266,7 @@ static const struct { {print_amd_chips}, #endif {print_serverengines_chips}, + {print_infineon_chips}, }; #endif From gerrit at coreboot.org Mon Nov 7 18:15:49 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 18:15:49 +0100 Subject: [coreboot] Patch merged into coreboot/master: 1e93c67 Avoid false detection of SMSC FDC37N972 when Infineon TPM is present References: Message-ID: the following patch was just integrated into master: commit 1e93c672d9a0464eb3b0b860e82d9c5f7f672872 Author: Jonathan A. Kollasch Date: Mon Nov 7 10:43:05 2011 -0600 Avoid false detection of SMSC FDC37N972 when Infineon TPM is present Change-Id: Ibfb3af4c5d7675a5d4e27021cbb988c2ce00fd9f Signed-off-by: Jonathan A. Kollasch Build-Tested: build bot (Jenkins) at Mon Nov 7 18:11:21 2011, giving +1 Reviewed-By: Stefan Reinauer at Mon Nov 7 18:13:14 2011, giving +2 See http://review.coreboot.org/420 for details. -gerrit From gerrit at coreboot.org Mon Nov 7 18:37:07 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 18:37:07 +0100 Subject: [coreboot] Patch merged into coreboot/master: 57f3190 add support for 1106:3188 (host controller of the old version of k8t800) References: Message-ID: the following patch was just integrated into master: commit 57f31907876dc6ea941ca53547e22b655ac22179 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: Id61678f03e1f7d964f7180a062dd6a689852d4ac Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Fri Nov 4 23:25:53 2011, giving +1 Reviewed-By: Stefan Reinauer at Mon Nov 7 18:37:02 2011, giving +2 See http://review.coreboot.org/401 for details. -gerrit From gerrit at coreboot.org Mon Nov 7 19:03:03 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Mon, 7 Nov 2011 19:03:03 +0100 Subject: [coreboot] New patch to review for coreboot: 2562633 abuild: Don't try to use files that don't exist References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/422 -gerrit commit 2562633abcc66b2fc908e00f7b6f5eb2a22f0473 Author: Patrick Georgi Date: Mon Nov 7 19:01:54 2011 +0100 abuild: Don't try to use files that don't exist Collecting per-board abuild.xml is bound to fail if there are no such files. Change-Id: I6bd6b4389beda51654005e0380f0e52f006642db Signed-off-by: Patrick Georgi --- util/abuild/abuild | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 8b81ea1..78a4718 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -656,7 +656,7 @@ if [ "$target" != "" ]; then fi build_target $VENDOR $MAINBOARD $CONFIG test_target $VENDOR $MAINBOARD - cat $TARGET/${VENDOR}_${MAINBOARD}/abuild.xml >> $REAL_XMLFILE + test "$mode" != "text" && cat $TARGET/${VENDOR}_${MAINBOARD}/abuild.xml >> $REAL_XMLFILE XMLFILE=$REAL_XMLFILE else # build all boards per default @@ -667,9 +667,11 @@ else remove_target $VENDOR $MAINBOARD done done - for xmlfile in $TARGET/*_*/abuild.xml; do - cat $xmlfile >> $REAL_XMLFILE - done + if [ "$mode" != "text" ]; then + for xmlfile in $TARGET/*_*/abuild.xml; do + cat $xmlfile >> $REAL_XMLFILE + done + fi XMLFILE=$REAL_XMLFILE fi xml '' From gerrit at coreboot.org Mon Nov 7 19:17:25 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 19:17:25 +0100 Subject: [coreboot] Patch merged into coreboot/master: 28be6c6 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() References: Message-ID: the following patch was just integrated into master: commit 28be6c68a96a99a6e85cc3fc878a2ce748ea7637 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl Reviewed-By: Patrick Georgi at Mon Nov 7 19:17:12 2011, giving +2 See http://review.coreboot.org/378 for details. -gerrit From gerrit at coreboot.org Mon Nov 7 19:17:33 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 19:17:33 +0100 Subject: [coreboot] Patch merged into coreboot/master: a3f5358 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible References: Message-ID: the following patch was just integrated into master: commit a3f5358e99e8b04932137a79ba1448e0cca16259 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl Reviewed-By: Patrick Georgi at Mon Nov 7 19:12:45 2011, giving +2 See http://review.coreboot.org/379 for details. -gerrit From gerrit at coreboot.org Mon Nov 7 19:19:57 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Mon, 7 Nov 2011 19:19:57 +0100 Subject: [coreboot] Patch set updated for coreboot: 924df9b abuild: Don't try to use files that don't exist References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/422 -gerrit commit 924df9b71a38bf7d7a16faea3d84a49d5d9d015d Author: Patrick Georgi Date: Mon Nov 7 19:01:54 2011 +0100 abuild: Don't try to use files that don't exist Collecting per-board abuild.xml is bound to fail if there are no such files. Change-Id: I6bd6b4389beda51654005e0380f0e52f006642db Signed-off-by: Patrick Georgi --- util/abuild/abuild | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 8b81ea1..78a4718 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -656,7 +656,7 @@ if [ "$target" != "" ]; then fi build_target $VENDOR $MAINBOARD $CONFIG test_target $VENDOR $MAINBOARD - cat $TARGET/${VENDOR}_${MAINBOARD}/abuild.xml >> $REAL_XMLFILE + test "$mode" != "text" && cat $TARGET/${VENDOR}_${MAINBOARD}/abuild.xml >> $REAL_XMLFILE XMLFILE=$REAL_XMLFILE else # build all boards per default @@ -667,9 +667,11 @@ else remove_target $VENDOR $MAINBOARD done done - for xmlfile in $TARGET/*_*/abuild.xml; do - cat $xmlfile >> $REAL_XMLFILE - done + if [ "$mode" != "text" ]; then + for xmlfile in $TARGET/*_*/abuild.xml; do + cat $xmlfile >> $REAL_XMLFILE + done + fi XMLFILE=$REAL_XMLFILE fi xml '' From gerrit at coreboot.org Mon Nov 7 19:45:17 2011 From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net)) Date: Mon, 7 Nov 2011 19:45:17 +0100 Subject: [coreboot] Patch set updated for coreboot: 742a11b superiotool: add detection and dump of Infineon SLB9635 TPM References: Message-ID: Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/421 -gerrit commit 742a11bc8deb5ed4701d0baf721830fe8ee96570 Author: Jonathan A. Kollasch Date: Mon Nov 7 10:56:42 2011 -0600 superiotool: add detection and dump of Infineon SLB9635 TPM Change-Id: If94ea5f45135a4b65bdd37532851fa0ba864bb73 Signed-off-by: Jonathan A. Kollasch --- util/superiotool/Makefile | 2 +- util/superiotool/infineon.c | 87 ++++++++++++++++++++++++++++++++++++++++ util/superiotool/superiotool.h | 6 +++ 3 files changed, 94 insertions(+), 1 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 5cc7650..e7d2f63 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -34,7 +34,7 @@ CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ LDFLAGS += -lz OBJS = superiotool.o serverengines.o ali.o fintek.o ite.o nsc.o nuvoton.o \ - smsc.o winbond.o + smsc.o winbond.o infineon.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/superiotool/infineon.c b/util/superiotool/infineon.c new file mode 100644 index 0000000..56bc062 --- /dev/null +++ b/util/superiotool/infineon.c @@ -0,0 +1,87 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2011 Jonathan A. Kollasch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "superiotool.h" + +#define DEVICE_ID_REG 0x20 +#define DEVICE_REV_REG 0x21 + +static const struct superio_registers reg_table[] = { + {0x0b, "SLB9635TT12", { + {NOLDN, NULL, + {0x20,0x21,0x26,0x27,EOT}, + {0x0b,0x00,NANA,NANA,EOT}}, + {0, NULL, + {0x30,0x38,0x60,0x61,0x70,0x71,0xf1,0xf2,0xf3,0xf4,0xf5,EOT}, + {0x00,0x00,NANA,NANA,0x00,0x02,0xd1,0x15,0x0b,0x00,NANA,EOT}}, + {EOT}}}, + {EOT} +}; + +/* same as some SMSC */ +static void enter_conf_mode_infineon(uint16_t port) +{ + OUTB(0x55, port); +} + +static void exit_conf_mode_infineon(uint16_t port) +{ + OUTB(0xaa, port); +} + +void probe_idregs_infineon(uint16_t port) +{ + uint8_t rev, devid; + + probing_for("Infineon", "", port); + + enter_conf_mode_infineon(port); + + devid = regval(port, DEVICE_ID_REG); + rev = regval(port, DEVICE_REV_REG); + + if (superio_unknown(reg_table, devid)) { + if (verbose) + printf(NOTFOUND "id=0x%02x, rev=0x%02x\n", devid, rev); + exit_conf_mode_infineon(port); + return; + } + + /* Attempt to prevent false matches on SMSC FDC37N972, see smsc.c */ + if (((regval(port, 0x27)<<8)|regval(port, 0x26)) != port) { + if (verbose) + printf(NOTFOUND "id=0x%02x, rev=0x%02x\n", devid, rev); + exit_conf_mode_infineon(port); + return; + } + + printf("Found Infineon %s (id=0x%02x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, devid), devid, rev, port); + chip_found = 1; + + dump_superio("Infineon", reg_table, port, devid, LDN_SEL); + + exit_conf_mode_infineon(port); +} + +void print_infineon_chips(void) +{ + print_vendor_chips("Infineon", reg_table); +} diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index f705a58..5583ec5 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -195,6 +195,10 @@ void probe_idregs_fintek(uint16_t port); void probe_idregs_fintek_alternative(uint16_t port); void print_fintek_chips(void); +/* infineon.c */ +void probe_idregs_infineon(uint16_t port); +void print_infineon_chips(void); + /* ite.c */ void probe_idregs_ite(uint16_t port); void print_ite_chips(void); @@ -243,6 +247,7 @@ static const struct { {probe_idregs_amd, {0xaa, EOT}}, #endif {probe_idregs_serverengines, {0x2e, EOT}}, + {probe_idregs_infineon, {0x2e, 0x4e}}, }; /** Table of functions to print out supported Super I/O chips. */ @@ -261,6 +266,7 @@ static const struct { {print_amd_chips}, #endif {print_serverengines_chips}, + {print_infineon_chips}, }; #endif From gerrit at coreboot.org Mon Nov 7 19:59:03 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Mon, 7 Nov 2011 19:59:03 +0100 Subject: [coreboot] Patch set updated for coreboot: 67f17df Add code to set the clock speed for Winbond W83627THF/THG. References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/412 -gerrit commit 67f17df800f9f27b4854d432dee09fd9420233ca Author: Idwer Vollering Date: Mon Nov 7 17:48:33 2011 +0100 Add code to set the clock speed for Winbond W83627THF/THG. Change-Id: I984404dd1df50b3ba423ac610283b9bf8bca5a31 Signed-off-by: Idwer Vollering --- src/superio/winbond/w83627thg/early_serial.c | 11 +++++++++++ src/superio/winbond/w83627thg/w83627thg.h | 2 ++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 559e982..b80e514 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -45,3 +45,14 @@ static void inline w83627thg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +#ifndef __ROMCC__ +void w83627thg_set_clksel_48(device_t dev) { + u8 reg8; + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} +#endif diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index 73be544..99ff565 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -34,4 +34,6 @@ #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware monitor */ +void w83627thg_set_clksel_48(device_t dev); + #endif From gerrit at coreboot.org Mon Nov 7 20:09:18 2011 From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net)) Date: Mon, 7 Nov 2011 20:09:18 +0100 Subject: [coreboot] New patch to review for coreboot: 02b1ce4 buildgcc: don't download python and expat if disabled References: Message-ID: Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/423 -gerrit commit 02b1ce47657abe3db2cab7e0c2a6b114f0423086 Author: Jonathan A. Kollasch Date: Mon Nov 7 13:05:18 2011 -0600 buildgcc: don't download python and expat if disabled Change-Id: I18cb1426e935c46ead30c72685829c20d186f9d8 Signed-off-by: Jonathan A. Kollasch --- util/crossgcc/buildgcc | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 748b944..f86332d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -211,7 +211,9 @@ if [ $SKIPGDB -eq 1 ]; then fi fi if [ $SKIPPYTHON -eq 1 ]; then + PYTHON_ARCHIVE="" PYTHON_PACKAGE="" + EXPAT_ARCHIVE="" EXPAT_PACKAGE="" fi From kyosti.malkki at gmail.com Mon Nov 7 20:01:31 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Mon, 07 Nov 2011 21:01:31 +0200 Subject: [coreboot] Cache-line trouble on Xeon Message-ID: <1320692491.9998.144.camel@obelix> I keep trying to get Cache-As-Ram working with a dual Xeon P4/HT board, and have a few simple(?) questions about cache behaviour. I may have misunderstood some aspects of the cache logic here. As a test setup, my coreboot.rom image now includes the cache_as_ram.inc from intel/model_6ex and I link it with a ROMCC compiled romstage for easier debugging. Except for the cache-based stack, I got this to work nicely. The Xeon P4/HT CPUs installed on the mainboard have 8 kB L1, 512 kB L2 and 1024 kB L3. All levels share code and data, cache-line is 64 bytes. Below I have ignored the existence of L3. Problem 1: L2 does not store cache-line. I may have a case that L2 cache is currently not enabled at all. The reference code uses MSR 0x11e to explicitly enable L2, but this MSR does not exist for Xeon P4 and actually halts CPU. I did not find controls besides CR0 and L3 disable MSR that effect cache. As a test procedure, I have defined a 16 kB cache region over non-existing MMIO on the system bus, just below the FWH decode range. DCACHE_RAM_SIZE=0x4000 and DCACHE_RAM_BASE=0xffafc000. All reads there return 0xFF's and any writes are ignored. MTRR is setup for write-back. State of CR0.CD (cache disable bit) seems to have no effect on this test. For every dword in the range, starting from BASE, I first read them from system bus, hoping to get valid cache-lines in L2 to hit later on. Then I write each dword in the range with its address. When reading back, again starting from BASE, the last 8kB (except for one cache line) return the contents I wrote. My conclusion of this is, that when a modified cache-line is de-allocated from L1, there is a write miss on L2 and the write is lost on the system bus. Is this allowed or typical behaviour, as under normal operation the cache-line would be stored in DRAM? Is the minimum amount of RAM required for romstage 32 kB? (STACK_SIZE = 0x8000)? So L1 alone cannot handle it? Problem 2: Can I skip cache-fill from L2? This question is only relevant, if I cannot enable L2 and the 8kB L1 would be enough for Cache-As-Ram (which I doubt). I have dirty (exclusive?) cache-lines stored in L1 and code reaches execution of an instruction that requires writing dirty lines to system bus. Examples of such opcodes : inb, outb, mov ->cr0, wrmsr->MTRR. I assume that with one of these opcodes, any modified cache-lines are written on the system bus. The cache-line data remains valid in L1, but the state is probably changed (exclusive -> shared ?). The first write access on such a line will cause a fill from next level cache (L2) or system bus. In my case L2 might be disabled, so cache-line then contains all 0xFF's except for the data from our store instruction. Further writes on the same line do not cause new fill. Is there a way to avoid the fill from L2 on the first write, and re-use the valid data on the (shared?) line? I thought the no-fill mode (CR0.NW) would do this for me. Problem 3: Cache re-allocation policy? Cache-lines for the stack must remain in L1 while the XIP ROM lines can be thrown out whenever necessary. Generally, do dirty cache-lines remain in L1 as long as there are non-dirty cache-lines that require less effort to re-allocate? Ky?sti From gerrit at coreboot.org Mon Nov 7 21:59:39 2011 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Mon, 7 Nov 2011 21:59:39 +0100 Subject: [coreboot] New patch to review for coreboot: 8a703fb selfboot: cleanup References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/424 -gerrit commit 8a703fb508b048380007cccc0d24fd2ae629bae7 Author: Stefan Reinauer Date: Mon Nov 7 12:43:03 2011 -0800 selfboot: cleanup - move cbfs_load_payload to the end so we can drop the prototype - move lb_start and lb_end to the beginning so they can be used in other functions. - drop two unused function declarations - break a 80+ characters line - fix a comment Change-Id: I460aa1e2ccf9d95ac12233af001076f73ab0268e Signed-off-by: Stefan Reinauer --- src/boot/selfboot.c | 69 +++++++++++++++++++++----------------------------- 1 files changed, 29 insertions(+), 40 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index cdb1fa1..573dd5e 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -31,15 +31,18 @@ #include #include -/* Maximum physical address we can use for the coreboot bounce buffer. - */ +/* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR #define MAX_ADDR -1UL #endif +/* from coreboot_ram.ld: */ extern unsigned char _ram_seg; extern unsigned char _eram_seg; +static const unsigned long lb_start = (unsigned long)&_ram_seg; +static const unsigned long lb_end = (unsigned long)&_eram_seg; + struct segment { struct segment *next; struct segment *prev; @@ -52,36 +55,6 @@ struct segment { int compression; }; -struct verify_callback { - struct verify_callback *next; - int (*callback)(struct verify_callback *vcb, - Elf_ehdr *ehdr, Elf_phdr *phdr, struct segment *head); - unsigned long desc_offset; - unsigned long desc_addr; -}; - -struct ip_checksum_vcb { - struct verify_callback data; - unsigned short ip_checksum; -}; - -static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload); - -void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name) -{ - struct cbfs_payload *payload; - - payload = (struct cbfs_payload *)cbfs_find_file(name, CBFS_TYPE_PAYLOAD); - if (payload == NULL) - return (void *) -1; - printk(BIOS_DEBUG, "Got a payload\n"); - - selfboot(lb_mem, payload); - printk(BIOS_EMERG, "SELFBOOT RETURNED!\n"); - - return (void *) -1; -} - /* The problem: * Static executables all want to share the same addresses * in memory because only a few addresses are reliably present on @@ -100,7 +73,6 @@ void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name) * - Coreboot is preserved, so it can be returned to. * - The implementation is still relatively simple, * and much simpler than the general case implemented in kexec. - * */ static unsigned long bounce_size, bounce_buffer; @@ -111,10 +83,12 @@ static void get_bounce_buffer(struct lb_memory *mem, unsigned long req_size) unsigned long mem_entries; unsigned long buffer; int i; - lb_size = (unsigned long)(&_eram_seg - &_ram_seg); - /* Double coreboot size so I have somewhere to place a copy to return to */ + lb_size = lb_end - lb_start; + /* Plus coreboot size so I have somewhere + * to place a copy to return to. + */ lb_size = req_size + lb_size; - mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + mem_entries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]); buffer = 0; for(i = 0; i < mem_entries; i++) { unsigned long mstart, mend; @@ -149,7 +123,8 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer, */ int i; unsigned long end = start + len; - unsigned long mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + unsigned long mem_entries = (mem->size - sizeof(*mem)) / + sizeof(mem->map[0]); /* See if I conflict with the bounce buffer */ if (end >= buffer) { @@ -194,8 +169,6 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer, return 1; } -static const unsigned long lb_start = (unsigned long)&_ram_seg; -static const unsigned long lb_end = (unsigned long)&_eram_seg; static int overlaps_coreboot(struct segment *seg) { @@ -211,7 +184,8 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) * to load onto the bounce buffer instead. */ /* ret: 1 : A new segment is inserted before the seg. - * 0 : A new segment is inserted after the seg, or no new one. */ + * 0 : A new segment is inserted after the seg, or no new one. + */ unsigned long start, middle, end, ret = 0; printk(BIOS_SPEW, "lb: [0x%016lx, 0x%016lx)\n", @@ -559,3 +533,18 @@ static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) return 0; } +void *cbfs_load_payload(struct lb_memory *lb_mem, const char *name) +{ + struct cbfs_payload *payload; + + payload = (struct cbfs_payload *)cbfs_find_file(name, CBFS_TYPE_PAYLOAD); + if (payload == NULL) + return (void *) -1; + printk(BIOS_DEBUG, "Got a payload\n"); + + selfboot(lb_mem, payload); + printk(BIOS_EMERG, "SELFBOOT RETURNED!\n"); + + return (void *) -1; +} + From gerrit at coreboot.org Mon Nov 7 21:59:40 2011 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Mon, 7 Nov 2011 21:59:40 +0100 Subject: [coreboot] New patch to review for coreboot: e13a5ed selfboot: fix bug in valid_area() References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/425 -gerrit commit e13a5edca121b2781a3fa05f7b4b23476d60ee65 Author: Stefan Reinauer Date: Mon Nov 7 12:56:12 2011 -0800 selfboot: fix bug in valid_area() valid_area will accept a region as valid for the payload if only a part of coreboot fits in that region. This means if a payload reaches into a neighboring RESERVED region, coreboot would not care and happily overwrite that region, as long as the payload also writes to some RAM. Change-Id: Ie263f83be18009b01a31c71e7285c998747d097f Signed-off-by: Stefan Reinauer --- src/boot/selfboot.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index 573dd5e..ab0bf21 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -140,10 +140,10 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer, mtype = mem->map[i].type; mstart = unpack_lb64(mem->map[i].start); mend = mstart + unpack_lb64(mem->map[i].size); - if ((mtype == LB_MEM_RAM) && (start < mend) && (end > mstart)) { + if ((mtype == LB_MEM_RAM) && (start >= mstart) && (end < mend)) { break; } - if ((mtype == LB_MEM_TABLE) && (start < mend) && (end > mstart)) { + if ((mtype == LB_MEM_TABLE) && (start >= mstart) && (end < mend)) { printk(BIOS_ERR, "Payload is overwriting coreboot tables.\n"); break; } From gerrit at coreboot.org Mon Nov 7 22:05:21 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 22:05:21 +0100 Subject: [coreboot] Patch merged into coreboot/master: 924df9b abuild: Don't try to use files that don't exist References: Message-ID: the following patch was just integrated into master: commit 924df9b71a38bf7d7a16faea3d84a49d5d9d015d Author: Patrick Georgi Date: Mon Nov 7 19:01:54 2011 +0100 abuild: Don't try to use files that don't exist Collecting per-board abuild.xml is bound to fail if there are no such files. Change-Id: I6bd6b4389beda51654005e0380f0e52f006642db Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Mon Nov 7 19:44:28 2011, giving +1 Reviewed-By: Stefan Reinauer at Mon Nov 7 22:02:03 2011, giving +2 See http://review.coreboot.org/422 for details. -gerrit From gerrit at coreboot.org Mon Nov 7 22:05:24 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 22:05:24 +0100 Subject: [coreboot] Patch merged into coreboot/master: 02b1ce4 buildgcc: don't download python and expat if disabled References: Message-ID: the following patch was just integrated into master: commit 02b1ce47657abe3db2cab7e0c2a6b114f0423086 Author: Jonathan A. Kollasch Date: Mon Nov 7 13:05:18 2011 -0600 buildgcc: don't download python and expat if disabled Change-Id: I18cb1426e935c46ead30c72685829c20d186f9d8 Signed-off-by: Jonathan A. Kollasch Build-Tested: build bot (Jenkins) at Mon Nov 7 20:24:46 2011, giving +1 Reviewed-By: Stefan Reinauer at Mon Nov 7 22:02:58 2011, giving +2 See http://review.coreboot.org/423 for details. -gerrit From gerrit at coreboot.org Mon Nov 7 22:05:25 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 22:05:25 +0100 Subject: [coreboot] Patch merged into coreboot/master: 742a11b superiotool: add detection and dump of Infineon SLB9635 TPM References: Message-ID: the following patch was just integrated into master: commit 742a11bc8deb5ed4701d0baf721830fe8ee96570 Author: Jonathan A. Kollasch Date: Mon Nov 7 10:56:42 2011 -0600 superiotool: add detection and dump of Infineon SLB9635 TPM Change-Id: If94ea5f45135a4b65bdd37532851fa0ba864bb73 Signed-off-by: Jonathan A. Kollasch Build-Tested: build bot (Jenkins) at Mon Nov 7 19:58:46 2011, giving +1 Reviewed-By: Stefan Reinauer at Mon Nov 7 22:03:36 2011, giving +2 See http://review.coreboot.org/421 for details. -gerrit From gerrit at coreboot.org Mon Nov 7 22:12:13 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 22:12:13 +0100 Subject: [coreboot] Patch merged into coreboot/master: 67f17df Add code to set the clock speed for Winbond W83627THF/THG. References: Message-ID: the following patch was just integrated into master: commit 67f17df800f9f27b4854d432dee09fd9420233ca Author: Idwer Vollering Date: Mon Nov 7 17:48:33 2011 +0100 Add code to set the clock speed for Winbond W83627THF/THG. Change-Id: I984404dd1df50b3ba423ac610283b9bf8bca5a31 Signed-off-by: Idwer Vollering Build-Tested: build bot (Jenkins) at Mon Nov 7 20:11:29 2011, giving +1 Reviewed-By: Stefan Reinauer at Mon Nov 7 22:12:11 2011, giving +2 See http://review.coreboot.org/412 for details. -gerrit From gerrit at coreboot.org Mon Nov 7 22:17:24 2011 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Mon, 7 Nov 2011 22:17:24 +0100 Subject: [coreboot] New patch to review for coreboot: c0ce7d7 selfboot: Don't include unneeded ip_checksum.h References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/426 -gerrit commit c0ce7d7b25f94be2e1ff3fe26253debead9dcf60 Author: Stefan Reinauer Date: Mon Nov 7 13:16:38 2011 -0800 selfboot: Don't include unneeded ip_checksum.h Change-Id: I09b888e70f7432f7025b0b851acfb0279553400f Signed-off-by: Stefan Reinauer --- src/boot/selfboot.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index ab0bf21..fe56653 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include From gerrit at coreboot.org Mon Nov 7 22:15:24 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 7 Nov 2011 22:15:24 +0100 Subject: [coreboot] Patch merged into coreboot/master: 1415c32 Added RAMINIT_SYSINFO and declared the necessary structs References: Message-ID: the following patch was just integrated into master: commit 1415c32a1a36d9646c43816113e14bc115ba0dea Author: Oskar Enoksson Date: Tue Oct 4 22:15:51 2011 +0200 Added RAMINIT_SYSINFO and declared the necessary structs Using RAMINIT_SYSINFO should be beneficial for this platform. It is also more clean/safe to put data in struct mb_sysconf_t. It's more consistent with other MB's and I've tested it thoroughly on my DL145. Signed-off-by: Oskar Enoksson Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be Build-Tested: build bot (Jenkins) at Tue Oct 18 15:41:32 2011, giving +1 Reviewed-By: Stefan Reinauer at Mon Nov 7 22:13:36 2011, giving +2 See http://review.coreboot.org/236 for details. -gerrit From gerrit at coreboot.org Tue Nov 8 03:23:31 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Tue, 8 Nov 2011 03:23:31 +0100 Subject: [coreboot] Patch set updated for coreboot: 897a07d Refactor src/southbridge/intel/i82801ex/ References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/415 -gerrit commit 897a07d55541bec5336b67789cfc155c31053d41 Author: Idwer Vollering Date: Mon Nov 7 17:48:33 2011 +0100 Refactor src/southbridge/intel/i82801ex/ Change-Id: I8be22f0292e322562b117f1e8bf493ed25eb4bec Signed-off-by: Idwer Vollering --- src/southbridge/intel/i82801ex/chip.h | 1 - src/southbridge/intel/i82801ex/early_smbus.c | 32 ++++++++------ src/southbridge/intel/i82801ex/ehci.c | 8 ++- src/southbridge/intel/i82801ex/i82801ex.c | 12 +++--- src/southbridge/intel/i82801ex/i82801ex.h | 26 +++++++++--- src/southbridge/intel/i82801ex/ide.c | 15 +++---- src/southbridge/intel/i82801ex/lpc.c | 59 +++++++++++++------------- src/southbridge/intel/i82801ex/pci.c | 20 +++++---- src/southbridge/intel/i82801ex/sata.c | 35 +++++++++------- src/southbridge/intel/i82801ex/smbus.c | 3 +- src/southbridge/intel/i82801ex/smbus.h | 6 ++- src/southbridge/intel/i82801ex/uhci.c | 1 - src/southbridge/intel/i82801ex/watchdog.c | 10 +++-- src/superio/winbond/w83627thg/early_serial.c | 11 +++++ src/superio/winbond/w83627thg/w83627thg.h | 2 + 15 files changed, 141 insertions(+), 100 deletions(-) diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h index f04fc3f..544b6f7 100644 --- a/src/southbridge/intel/i82801ex/chip.h +++ b/src/southbridge/intel/i82801ex/chip.h @@ -33,4 +33,3 @@ struct southbridge_intel_i82801ex_config extern struct chip_operations southbridge_intel_i82801ex_ops; #endif /* I82801EX_CHIP_H */ - diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index cdf1f62..b9c3849 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -1,21 +1,25 @@ +#include "i82801ex.h" #include "smbus.h" -#define SMBUS_IO_BASE 0x0f00 - static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); print_spew("SMBus controller enabled\n"); - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - print_debug_hex32(pci_read_config32(dev, 0x20)); + /* bit 0 is read only and hardwired to 1 */ + pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE); + print_debug("SMB_BASE = 0x"); + /* don't show bit 0 */ + print_debug_hex32(pci_read_config32(dev, SMB_BASE) & 0xfffffffe); + print_debug("\n"); + /* Set smbus enable */ - pci_write_config8(dev, 0x40, 1); + pci_write_config8(dev, HOSTC, 1); /* Set smbus iospace enable */ - pci_write_config8(dev, 0x4, 1); + pci_write_config8(dev, PCICMD, 1); /* SMBALERT_DIS */ - pci_write_config8(dev, 0x11, 4); + pci_write_config8(dev, SLV_CMD, 4); /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); @@ -81,7 +85,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, /* setup transaction */ /* Obtain ownership */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for(stat=0;(stat&0x40)==0;) { + for (stat = 0; (stat & 0x40) == 0;) { stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); } /* clear the done bit */ @@ -99,13 +103,13 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0); /* try sending out the first byte of data here */ - byte=(data1>>(0))&0x0ff; - outb(byte,SMBUS_IO_BASE + SMBBLKDAT); + byte = (data1 >> (0) ) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); /* issue a block write command */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, SMBUS_IO_BASE + SMBHSTCTL); - for(i=0;i3) - byte=(data2>>(i%4))&0x0ff; + if(i > 3) + byte= (data2 >> (i % 4)) & 0x0ff; else - byte=(data1>>(i))&0x0ff; + byte=(data1 >> (i)) & 0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); /* clear the done bit */ diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c index 8ae921d..4117c4e 100644 --- a/src/southbridge/intel/i82801ex/ehci.c +++ b/src/southbridge/intel/i82801ex/ehci.c @@ -5,6 +5,8 @@ #include #include "i82801ex.h" +#define ACCESS_CNTL 0x80 + static void ehci_init(struct device *dev) { uint32_t cmd; @@ -20,14 +22,14 @@ static void ehci_init(struct device *dev) static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { uint8_t access_cntl; - access_cntl = pci_read_config8(dev, 0x80); + access_cntl = pci_read_config8(dev, ACCESS_CNTL); /* Enable writes to protected registers */ - pci_write_config8(dev, 0x80, access_cntl | 1); + pci_write_config8(dev, ACCESS_CNTL, access_cntl | 1); /* Write the subsystem vendor and device id */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection */ - pci_write_config8(dev, 0x80, access_cntl); + pci_write_config8(dev, ACCESS_CNTL, access_cntl); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c index fc41645..a30e887 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -12,13 +12,13 @@ void i82801ex_enable(device_t dev) /* See if we are behind the i82801ex pci bridge */ lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); - if((dev->path.pci.devfn &0xf8)== 0xf8) { + if((dev->path.pci.devfn & 0xf8) == 0xf8) { index = dev->path.pci.devfn & 7; } - else if((dev->path.pci.devfn &0xf8)== 0xe8) { - index = (dev->path.pci.devfn & 7) +8; + else if((dev->path.pci.devfn & 0xf8) == 0xe8) { + index = (dev->path.pci.devfn & 7) + 8; } - if ((!lpc_dev) || (index >= 16) || ((1<= 16) || ((1 << index) & 0x3091)) { return; } if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || @@ -31,13 +31,13 @@ void i82801ex_enable(device_t dev) } } - reg = reg_old = pci_read_config16(lpc_dev, 0xf2); + reg = reg_old = pci_read_config16(lpc_dev, FUNC_DIS); reg &= ~(1 << index); if (!dev->enabled) { reg |= (1 << index); } if (reg != reg_old) { - pci_write_config16(lpc_dev, 0xf2, reg); + pci_write_config16(lpc_dev, FUNC_DIS, reg); } } diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 67fecdd..137b346 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -5,11 +5,25 @@ extern void i82801ex_enable(device_t dev); -#define PCI_DMA_CFG 0x90 -#define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 -#define GEN_PMCON_3 0xa4 +#define PCICMD 0x4 + +#define ACPI_CNTL 0x44 +#define SERIRQ_CNTL 0x64 +#define PCI_DMA_CFG 0x90 +#define GEN_PMCON_3 0xa4 +#define SATA_RD_CFG 0xae +#define GEN_CNTL 0xd0 +#define GEN_STA 0xd4 +#define RTC_CONF 0xd8 +#define GPIO_CNTL 0x5c +#define LPC_EN 0xe6 +#define FUNC_DIS 0xf2 + +/* IDE, SATA */ +#define IDE_TIMP 0x40 +#define IDE_TIMS 0x42 +#define SDMA_CNT 0x48 +#define SDMA_TIM 0x4a +#define IDE_CONFIG 0x54 #endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/ide.c b/src/southbridge/intel/i82801ex/ide.c index bbab6f1..b67ae7a 100644 --- a/src/southbridge/intel/i82801ex/ide.c +++ b/src/southbridge/intel/i82801ex/ide.c @@ -7,18 +7,18 @@ static void ide_init(struct device *dev) { - /* Enable IDE devices and timmings */ - pci_write_config16(dev, 0x40, 0x0a307); // IDE0 - pci_write_config16(dev, 0x42, 0x0a307); // IDE1 - pci_write_config8(dev, 0x48, 0x05); - pci_write_config16(dev, 0x4a, 0x0101); - pci_write_config16(dev, 0x54, 0x5055); + /* Enable IDE devices and timings */ + pci_write_config16(dev, IDE_TIMP, 0x0a307); + pci_write_config16(dev, IDE_TIMS, 0x0a307); + pci_write_config8(dev, SDMA_CNT, 0x05); + pci_write_config16(dev, SDMA_TIM, 0x0101); + pci_write_config16(dev, IDE_CONFIG, 0x5055); printk(BIOS_DEBUG, "IDE Enabled\n"); } static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - /* This value is also visible in uchi[0-2] and smbus functions */ + /* This value is also visible in uhci[0-2] and smbus functions */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -40,4 +40,3 @@ static const struct pci_driver ide_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_IDE, }; - diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 998360c..d57517f 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -12,33 +12,32 @@ #include #include "i82801ex.h" -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x58 +#define ACPI_BAR 0x40 +#define GPIO_BAR 0x58 +#define PIRQ_ABCD_OUT 0x60 +#define PIRQ_EFGH_OUT 0x68 -#define NMI_OFF 0 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 +#define NMI_OFF 0 +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -#define SERIRQ_CNTL 0x64 static void i82801ex_enable_serial_irqs(device_t dev) { /* set packet length and toggle silent mode bit */ - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); } -#define PCI_DMA_CFG 0x90 static void i82801ex_pci_dma_cfg(device_t dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); } -#define LPC_EN 0xe6 static void i82801ex_enable_lpc(device_t dev) { /* lpc i/f enable */ @@ -169,10 +168,10 @@ static void i82801ex_pirq_init(device_t dev) config = dev->chip_info; if(config->pirq_a_d) { - pci_write_config32(dev, 0x60, config->pirq_a_d); + pci_write_config32(dev, PIRQ_ABCD_OUT, config->pirq_a_d); } if(config->pirq_e_h) { - pci_write_config32(dev, 0x68, config->pirq_e_h); + pci_write_config32(dev, PIRQ_EFGH_OUT, config->pirq_e_h); } } @@ -230,25 +229,25 @@ static void enable_hpet(struct device *dev) */ dword &= ~(3 << 15); /* clear it */ - dword |= (code<<15); + dword |= (code << 15); pci_write_config32(dev, GEN_CNTL, dword); - printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) ); + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code << 12) ); } static void lpc_init(struct device *dev) { uint8_t byte; uint32_t value; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* IO APIC initialization */ - value = pci_read_config32(dev, 0xd0); - value |= (1 << 8)|(1<<7)|(1<<1); - pci_write_config32(dev, 0xd0, value); - value = pci_read_config32(dev, 0xd4); - value |= (1<<1); - pci_write_config32(dev, 0xd4, value); + value = pci_read_config32(dev, GEN_CNTL); + value |= (1 << 8) | (1 << 7) | (1 << 1); + pci_write_config32(dev, GEN_CNTL, value); + value = pci_read_config32(dev, GEN_STA); + value |= (1 << 1); + pci_write_config32(dev, GEN_STA, value); setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. i82801ex_enable_serial_irqs(dev); @@ -258,16 +257,16 @@ static void lpc_init(struct device *dev) i82801ex_enable_lpc(dev); /* Clear SATA to non raid */ - pci_write_config8(dev, 0xae, 0x00); + pci_write_config8(dev, SATA_RD_CFG, 0x00); get_option(&pwr_on, "power_on_after_fail"); - byte = pci_read_config8(dev, 0xa4); + byte = pci_read_config8(dev, GEN_PMCON_3); byte &= 0xfe; if (!pwr_on) { byte |= 1; } - pci_write_config8(dev, 0xa4, byte); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off"); + pci_write_config8(dev, GEN_PMCON_3, byte); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); /* Set up the PIRQ */ i82801ex_pirq_init(dev); @@ -282,7 +281,7 @@ static void lpc_init(struct device *dev) isa_dma_init(); /* Disable IDE (needed when sata is enabled) */ - pci_write_config8(dev, 0xf2, 0x60); + pci_write_config8(dev, FUNC_DIS, 0x60); enable_hpet(dev); } @@ -327,14 +326,14 @@ static void i82801ex_lpc_enable_resources(device_t dev) pci_dev_enable_resources(dev); /* Enable the ACPI bar */ - acpi_cntl = pci_read_config8(dev, 0x44); + acpi_cntl = pci_read_config8(dev, ACPI_CNTL); acpi_cntl |= (1 << 4); - pci_write_config8(dev, 0x44, acpi_cntl); + pci_write_config8(dev, ACPI_CNTL, acpi_cntl); /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, 0x5c); + gpio_cntl = pci_read_config8(dev, GPIO_CNTL); gpio_cntl |= (1 << 4); - pci_write_config8(dev, 0x5c, gpio_cntl); + pci_write_config8(dev, GPIO_CNTL, gpio_cntl); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/i82801ex/pci.c b/src/southbridge/intel/i82801ex/pci.c index 80c6e49..4c8254e 100644 --- a/src/southbridge/intel/i82801ex/pci.c +++ b/src/southbridge/intel/i82801ex/pci.c @@ -5,27 +5,30 @@ #include #include "i82801ex.h" +#define PCISTS 0x6 +#define SECSTS 0x1e + static void pci_init(struct device *dev) { uint16_t word; /* Clear system errors */ - word = pci_read_config16(dev, 0x06); + word = pci_read_config16(dev, PCISTS); word |= 0xf900; /* Clear possible errors */ - pci_write_config16(dev, 0x06, word); + pci_write_config16(dev, PCISTS, word); #if 0 /* System error enable */ uint32_t dword; - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* SERR# Enable */ - dword |= (1<<6); /* Parity Error Response */ - pci_write_config32(dev, 0x04, dword); + dword = pci_read_config32(dev, PCICMD); + dword |= (1 << 8); /* SERR# Enable */ + dword |= (1 << 6); /* Parity Error Response */ + pci_write_config32(dev, PCICMD, dword); #endif - word = pci_read_config16(dev, 0x1e); + word = pci_read_config16(dev, SECSTS); word |= 0xf800; /* Clear possible errors */ - pci_write_config16(dev, 0x1e, word); + pci_write_config16(dev, SECSTS, word); } static struct device_operations pci_ops = { @@ -42,4 +45,3 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_PCI, }; - diff --git a/src/southbridge/intel/i82801ex/sata.c b/src/southbridge/intel/i82801ex/sata.c index 9b340e9..0ac709f 100644 --- a/src/southbridge/intel/i82801ex/sata.c +++ b/src/southbridge/intel/i82801ex/sata.c @@ -5,35 +5,41 @@ #include #include "i82801ex.h" +#define SATA_PI 0x9 +#define SATA_MAP 0x90 +#define SATA_PCS 0x92 +#define SATA_SRI 0xa0 +#define SATA_SRD 0xa4 + static void sata_init(struct device *dev) { printk(BIOS_DEBUG, "SATA init\n"); /* SATA configuration */ - pci_write_config8(dev, 0x04, 0x07); - pci_write_config8(dev, 0x09, 0x8f); + pci_write_config8(dev, PCICMD, 0x07); + pci_write_config8(dev, SATA_PI, 0x8f); - /* Set timmings */ - pci_write_config16(dev, 0x40, 0x0a307); - pci_write_config16(dev, 0x42, 0x0a307); + /* Set timings */ + pci_write_config16(dev, IDE_TIMP, 0x0a307); + pci_write_config16(dev, IDE_TIMS, 0x0a307); /* Sync DMA */ - pci_write_config16(dev, 0x48, 0x000f); - pci_write_config16(dev, 0x4a, 0x1111); + pci_write_config16(dev, SDMA_CNT, 0x000f); + pci_write_config16(dev, SDMA_TIM, 0x1111); /* 66 mhz */ - pci_write_config16(dev, 0x54, 0xf00f); + pci_write_config16(dev, IDE_CONFIG, 0xf00f); /* Combine ide - sata configuration */ - pci_write_config8(dev, 0x90, 0x0); + pci_write_config8(dev, SATA_MAP, 0x0); /* port 0 & 1 enable */ - pci_write_config8(dev, 0x92, 0x33); + pci_write_config8(dev, SATA_PCS, 0x33); /* initialize SATA */ - pci_write_config16(dev, 0xa0, 0x0018); - pci_write_config32(dev, 0xa4, 0x00000264); - pci_write_config16(dev, 0xa0, 0x0040); - pci_write_config32(dev, 0xa4, 0x00220043); + pci_write_config16(dev, SATA_SRI, 0x0018); + pci_write_config32(dev, SATA_SRD, 0x00000264); + pci_write_config16(dev, SATA_SRI, 0x0040); + pci_write_config32(dev, SATA_SRD, 0x00220043); } @@ -57,4 +63,3 @@ static const struct pci_driver sata_driver_nr __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801EB_SATA, }; - diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c index 6bb4899..eb2794c 100644 --- a/src/southbridge/intel/i82801ex/smbus.c +++ b/src/southbridge/intel/i82801ex/smbus.c @@ -16,7 +16,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, SMB_BASE); return do_smbus_read_byte(res->base, device, address); } @@ -46,4 +46,3 @@ static const struct pci_driver smbus_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_SMB, }; - diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h index f330c0a..a9167d2 100644 --- a/src/southbridge/intel/i82801ex/smbus.h +++ b/src/southbridge/intel/i82801ex/smbus.h @@ -1,5 +1,10 @@ #include +#define SMBUS_IO_BASE 0xf00 +#define SMB_BASE 0x20 +#define SLV_CMD 0x11 +#define HOSTC 0x40 + #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3 @@ -102,4 +107,3 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned } return byte; } - diff --git a/src/southbridge/intel/i82801ex/uhci.c b/src/southbridge/intel/i82801ex/uhci.c index 56536b7..c9cf82e 100644 --- a/src/southbridge/intel/i82801ex/uhci.c +++ b/src/southbridge/intel/i82801ex/uhci.c @@ -53,4 +53,3 @@ static const struct pci_driver usb3_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_USB3, }; - diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c index 26f6644..3f02f61 100644 --- a/src/southbridge/intel/i82801ex/watchdog.c +++ b/src/southbridge/intel/i82801ex/watchdog.c @@ -3,6 +3,9 @@ #include #include #include +#include "i82801ex.h" + +#define PMBASE 0x40 void watchdog_off(void) { @@ -12,11 +15,11 @@ void watchdog_off(void) /* turn off the ICH5 watchdog */ dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); + value = pci_read_config16(dev, PCICMD); value |= (1 << 10); - pci_write_config16(dev, 0x04, value); + pci_write_config16(dev, PCICMD, value); /* Get TCO base */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + base = (pci_read_config32(dev, PMBASE) & 0x0fffe) + 0x60; /* Disable the watchdog timer */ value = inw(base + 0x08); value |= 1 << 11; @@ -26,4 +29,3 @@ void watchdog_off(void) outw(0x0002, base + 0x06); printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); } - diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 559e982..b80e514 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -45,3 +45,14 @@ static void inline w83627thg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +#ifndef __ROMCC__ +void w83627thg_set_clksel_48(device_t dev) { + u8 reg8; + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} +#endif diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index 73be544..99ff565 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -34,4 +34,6 @@ #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware monitor */ +void w83627thg_set_clksel_48(device_t dev); + #endif From gerrit at coreboot.org Tue Nov 8 03:26:11 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Tue, 8 Nov 2011 03:26:11 +0100 Subject: [coreboot] Patch set updated for coreboot: 8c63d8f Make the installation section Makefile of inteltool and superiotool more flexible. References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/416 -gerrit commit 8c63d8f92ae4e63b2e8f8dcc2623e574d18acbab Author: Idwer Vollering Date: Mon Nov 7 17:48:33 2011 +0100 Make the installation section Makefile of inteltool and superiotool more flexible. Change-Id: I0a85cb469bd1188fcd4e88df59380ffa5828496f Signed-off-by: Idwer Vollering --- src/southbridge/intel/i82801ex/chip.h | 1 - src/southbridge/intel/i82801ex/early_smbus.c | 32 ++++++++------ src/southbridge/intel/i82801ex/ehci.c | 8 ++- src/southbridge/intel/i82801ex/i82801ex.c | 12 +++--- src/southbridge/intel/i82801ex/i82801ex.h | 26 +++++++++--- src/southbridge/intel/i82801ex/ide.c | 15 +++---- src/southbridge/intel/i82801ex/lpc.c | 59 +++++++++++++------------- src/southbridge/intel/i82801ex/pci.c | 20 +++++---- src/southbridge/intel/i82801ex/sata.c | 35 +++++++++------- src/southbridge/intel/i82801ex/smbus.c | 3 +- src/southbridge/intel/i82801ex/smbus.h | 6 ++- src/southbridge/intel/i82801ex/uhci.c | 1 - src/southbridge/intel/i82801ex/watchdog.c | 10 +++-- src/superio/winbond/w83627thg/early_serial.c | 11 +++++ src/superio/winbond/w83627thg/w83627thg.h | 2 + util/inteltool/Makefile | 2 +- util/superiotool/Makefile | 2 +- 17 files changed, 143 insertions(+), 102 deletions(-) diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h index f04fc3f..544b6f7 100644 --- a/src/southbridge/intel/i82801ex/chip.h +++ b/src/southbridge/intel/i82801ex/chip.h @@ -33,4 +33,3 @@ struct southbridge_intel_i82801ex_config extern struct chip_operations southbridge_intel_i82801ex_ops; #endif /* I82801EX_CHIP_H */ - diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index cdf1f62..b9c3849 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -1,21 +1,25 @@ +#include "i82801ex.h" #include "smbus.h" -#define SMBUS_IO_BASE 0x0f00 - static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); print_spew("SMBus controller enabled\n"); - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - print_debug_hex32(pci_read_config32(dev, 0x20)); + /* bit 0 is read only and hardwired to 1 */ + pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE); + print_debug("SMB_BASE = 0x"); + /* don't show bit 0 */ + print_debug_hex32(pci_read_config32(dev, SMB_BASE) & 0xfffffffe); + print_debug("\n"); + /* Set smbus enable */ - pci_write_config8(dev, 0x40, 1); + pci_write_config8(dev, HOSTC, 1); /* Set smbus iospace enable */ - pci_write_config8(dev, 0x4, 1); + pci_write_config8(dev, PCICMD, 1); /* SMBALERT_DIS */ - pci_write_config8(dev, 0x11, 4); + pci_write_config8(dev, SLV_CMD, 4); /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); @@ -81,7 +85,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, /* setup transaction */ /* Obtain ownership */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for(stat=0;(stat&0x40)==0;) { + for (stat = 0; (stat & 0x40) == 0;) { stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); } /* clear the done bit */ @@ -99,13 +103,13 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0); /* try sending out the first byte of data here */ - byte=(data1>>(0))&0x0ff; - outb(byte,SMBUS_IO_BASE + SMBBLKDAT); + byte = (data1 >> (0) ) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); /* issue a block write command */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, SMBUS_IO_BASE + SMBHSTCTL); - for(i=0;i3) - byte=(data2>>(i%4))&0x0ff; + if(i > 3) + byte= (data2 >> (i % 4)) & 0x0ff; else - byte=(data1>>(i))&0x0ff; + byte=(data1 >> (i)) & 0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); /* clear the done bit */ diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c index 8ae921d..4117c4e 100644 --- a/src/southbridge/intel/i82801ex/ehci.c +++ b/src/southbridge/intel/i82801ex/ehci.c @@ -5,6 +5,8 @@ #include #include "i82801ex.h" +#define ACCESS_CNTL 0x80 + static void ehci_init(struct device *dev) { uint32_t cmd; @@ -20,14 +22,14 @@ static void ehci_init(struct device *dev) static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { uint8_t access_cntl; - access_cntl = pci_read_config8(dev, 0x80); + access_cntl = pci_read_config8(dev, ACCESS_CNTL); /* Enable writes to protected registers */ - pci_write_config8(dev, 0x80, access_cntl | 1); + pci_write_config8(dev, ACCESS_CNTL, access_cntl | 1); /* Write the subsystem vendor and device id */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection */ - pci_write_config8(dev, 0x80, access_cntl); + pci_write_config8(dev, ACCESS_CNTL, access_cntl); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c index fc41645..a30e887 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -12,13 +12,13 @@ void i82801ex_enable(device_t dev) /* See if we are behind the i82801ex pci bridge */ lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); - if((dev->path.pci.devfn &0xf8)== 0xf8) { + if((dev->path.pci.devfn & 0xf8) == 0xf8) { index = dev->path.pci.devfn & 7; } - else if((dev->path.pci.devfn &0xf8)== 0xe8) { - index = (dev->path.pci.devfn & 7) +8; + else if((dev->path.pci.devfn & 0xf8) == 0xe8) { + index = (dev->path.pci.devfn & 7) + 8; } - if ((!lpc_dev) || (index >= 16) || ((1<= 16) || ((1 << index) & 0x3091)) { return; } if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || @@ -31,13 +31,13 @@ void i82801ex_enable(device_t dev) } } - reg = reg_old = pci_read_config16(lpc_dev, 0xf2); + reg = reg_old = pci_read_config16(lpc_dev, FUNC_DIS); reg &= ~(1 << index); if (!dev->enabled) { reg |= (1 << index); } if (reg != reg_old) { - pci_write_config16(lpc_dev, 0xf2, reg); + pci_write_config16(lpc_dev, FUNC_DIS, reg); } } diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 67fecdd..137b346 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -5,11 +5,25 @@ extern void i82801ex_enable(device_t dev); -#define PCI_DMA_CFG 0x90 -#define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 -#define GEN_PMCON_3 0xa4 +#define PCICMD 0x4 + +#define ACPI_CNTL 0x44 +#define SERIRQ_CNTL 0x64 +#define PCI_DMA_CFG 0x90 +#define GEN_PMCON_3 0xa4 +#define SATA_RD_CFG 0xae +#define GEN_CNTL 0xd0 +#define GEN_STA 0xd4 +#define RTC_CONF 0xd8 +#define GPIO_CNTL 0x5c +#define LPC_EN 0xe6 +#define FUNC_DIS 0xf2 + +/* IDE, SATA */ +#define IDE_TIMP 0x40 +#define IDE_TIMS 0x42 +#define SDMA_CNT 0x48 +#define SDMA_TIM 0x4a +#define IDE_CONFIG 0x54 #endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/ide.c b/src/southbridge/intel/i82801ex/ide.c index bbab6f1..b67ae7a 100644 --- a/src/southbridge/intel/i82801ex/ide.c +++ b/src/southbridge/intel/i82801ex/ide.c @@ -7,18 +7,18 @@ static void ide_init(struct device *dev) { - /* Enable IDE devices and timmings */ - pci_write_config16(dev, 0x40, 0x0a307); // IDE0 - pci_write_config16(dev, 0x42, 0x0a307); // IDE1 - pci_write_config8(dev, 0x48, 0x05); - pci_write_config16(dev, 0x4a, 0x0101); - pci_write_config16(dev, 0x54, 0x5055); + /* Enable IDE devices and timings */ + pci_write_config16(dev, IDE_TIMP, 0x0a307); + pci_write_config16(dev, IDE_TIMS, 0x0a307); + pci_write_config8(dev, SDMA_CNT, 0x05); + pci_write_config16(dev, SDMA_TIM, 0x0101); + pci_write_config16(dev, IDE_CONFIG, 0x5055); printk(BIOS_DEBUG, "IDE Enabled\n"); } static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - /* This value is also visible in uchi[0-2] and smbus functions */ + /* This value is also visible in uhci[0-2] and smbus functions */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -40,4 +40,3 @@ static const struct pci_driver ide_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_IDE, }; - diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 998360c..d57517f 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -12,33 +12,32 @@ #include #include "i82801ex.h" -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x58 +#define ACPI_BAR 0x40 +#define GPIO_BAR 0x58 +#define PIRQ_ABCD_OUT 0x60 +#define PIRQ_EFGH_OUT 0x68 -#define NMI_OFF 0 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 +#define NMI_OFF 0 +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -#define SERIRQ_CNTL 0x64 static void i82801ex_enable_serial_irqs(device_t dev) { /* set packet length and toggle silent mode bit */ - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); } -#define PCI_DMA_CFG 0x90 static void i82801ex_pci_dma_cfg(device_t dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); } -#define LPC_EN 0xe6 static void i82801ex_enable_lpc(device_t dev) { /* lpc i/f enable */ @@ -169,10 +168,10 @@ static void i82801ex_pirq_init(device_t dev) config = dev->chip_info; if(config->pirq_a_d) { - pci_write_config32(dev, 0x60, config->pirq_a_d); + pci_write_config32(dev, PIRQ_ABCD_OUT, config->pirq_a_d); } if(config->pirq_e_h) { - pci_write_config32(dev, 0x68, config->pirq_e_h); + pci_write_config32(dev, PIRQ_EFGH_OUT, config->pirq_e_h); } } @@ -230,25 +229,25 @@ static void enable_hpet(struct device *dev) */ dword &= ~(3 << 15); /* clear it */ - dword |= (code<<15); + dword |= (code << 15); pci_write_config32(dev, GEN_CNTL, dword); - printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) ); + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code << 12) ); } static void lpc_init(struct device *dev) { uint8_t byte; uint32_t value; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* IO APIC initialization */ - value = pci_read_config32(dev, 0xd0); - value |= (1 << 8)|(1<<7)|(1<<1); - pci_write_config32(dev, 0xd0, value); - value = pci_read_config32(dev, 0xd4); - value |= (1<<1); - pci_write_config32(dev, 0xd4, value); + value = pci_read_config32(dev, GEN_CNTL); + value |= (1 << 8) | (1 << 7) | (1 << 1); + pci_write_config32(dev, GEN_CNTL, value); + value = pci_read_config32(dev, GEN_STA); + value |= (1 << 1); + pci_write_config32(dev, GEN_STA, value); setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. i82801ex_enable_serial_irqs(dev); @@ -258,16 +257,16 @@ static void lpc_init(struct device *dev) i82801ex_enable_lpc(dev); /* Clear SATA to non raid */ - pci_write_config8(dev, 0xae, 0x00); + pci_write_config8(dev, SATA_RD_CFG, 0x00); get_option(&pwr_on, "power_on_after_fail"); - byte = pci_read_config8(dev, 0xa4); + byte = pci_read_config8(dev, GEN_PMCON_3); byte &= 0xfe; if (!pwr_on) { byte |= 1; } - pci_write_config8(dev, 0xa4, byte); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off"); + pci_write_config8(dev, GEN_PMCON_3, byte); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); /* Set up the PIRQ */ i82801ex_pirq_init(dev); @@ -282,7 +281,7 @@ static void lpc_init(struct device *dev) isa_dma_init(); /* Disable IDE (needed when sata is enabled) */ - pci_write_config8(dev, 0xf2, 0x60); + pci_write_config8(dev, FUNC_DIS, 0x60); enable_hpet(dev); } @@ -327,14 +326,14 @@ static void i82801ex_lpc_enable_resources(device_t dev) pci_dev_enable_resources(dev); /* Enable the ACPI bar */ - acpi_cntl = pci_read_config8(dev, 0x44); + acpi_cntl = pci_read_config8(dev, ACPI_CNTL); acpi_cntl |= (1 << 4); - pci_write_config8(dev, 0x44, acpi_cntl); + pci_write_config8(dev, ACPI_CNTL, acpi_cntl); /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, 0x5c); + gpio_cntl = pci_read_config8(dev, GPIO_CNTL); gpio_cntl |= (1 << 4); - pci_write_config8(dev, 0x5c, gpio_cntl); + pci_write_config8(dev, GPIO_CNTL, gpio_cntl); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/i82801ex/pci.c b/src/southbridge/intel/i82801ex/pci.c index 80c6e49..4c8254e 100644 --- a/src/southbridge/intel/i82801ex/pci.c +++ b/src/southbridge/intel/i82801ex/pci.c @@ -5,27 +5,30 @@ #include #include "i82801ex.h" +#define PCISTS 0x6 +#define SECSTS 0x1e + static void pci_init(struct device *dev) { uint16_t word; /* Clear system errors */ - word = pci_read_config16(dev, 0x06); + word = pci_read_config16(dev, PCISTS); word |= 0xf900; /* Clear possible errors */ - pci_write_config16(dev, 0x06, word); + pci_write_config16(dev, PCISTS, word); #if 0 /* System error enable */ uint32_t dword; - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* SERR# Enable */ - dword |= (1<<6); /* Parity Error Response */ - pci_write_config32(dev, 0x04, dword); + dword = pci_read_config32(dev, PCICMD); + dword |= (1 << 8); /* SERR# Enable */ + dword |= (1 << 6); /* Parity Error Response */ + pci_write_config32(dev, PCICMD, dword); #endif - word = pci_read_config16(dev, 0x1e); + word = pci_read_config16(dev, SECSTS); word |= 0xf800; /* Clear possible errors */ - pci_write_config16(dev, 0x1e, word); + pci_write_config16(dev, SECSTS, word); } static struct device_operations pci_ops = { @@ -42,4 +45,3 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_PCI, }; - diff --git a/src/southbridge/intel/i82801ex/sata.c b/src/southbridge/intel/i82801ex/sata.c index 9b340e9..0ac709f 100644 --- a/src/southbridge/intel/i82801ex/sata.c +++ b/src/southbridge/intel/i82801ex/sata.c @@ -5,35 +5,41 @@ #include #include "i82801ex.h" +#define SATA_PI 0x9 +#define SATA_MAP 0x90 +#define SATA_PCS 0x92 +#define SATA_SRI 0xa0 +#define SATA_SRD 0xa4 + static void sata_init(struct device *dev) { printk(BIOS_DEBUG, "SATA init\n"); /* SATA configuration */ - pci_write_config8(dev, 0x04, 0x07); - pci_write_config8(dev, 0x09, 0x8f); + pci_write_config8(dev, PCICMD, 0x07); + pci_write_config8(dev, SATA_PI, 0x8f); - /* Set timmings */ - pci_write_config16(dev, 0x40, 0x0a307); - pci_write_config16(dev, 0x42, 0x0a307); + /* Set timings */ + pci_write_config16(dev, IDE_TIMP, 0x0a307); + pci_write_config16(dev, IDE_TIMS, 0x0a307); /* Sync DMA */ - pci_write_config16(dev, 0x48, 0x000f); - pci_write_config16(dev, 0x4a, 0x1111); + pci_write_config16(dev, SDMA_CNT, 0x000f); + pci_write_config16(dev, SDMA_TIM, 0x1111); /* 66 mhz */ - pci_write_config16(dev, 0x54, 0xf00f); + pci_write_config16(dev, IDE_CONFIG, 0xf00f); /* Combine ide - sata configuration */ - pci_write_config8(dev, 0x90, 0x0); + pci_write_config8(dev, SATA_MAP, 0x0); /* port 0 & 1 enable */ - pci_write_config8(dev, 0x92, 0x33); + pci_write_config8(dev, SATA_PCS, 0x33); /* initialize SATA */ - pci_write_config16(dev, 0xa0, 0x0018); - pci_write_config32(dev, 0xa4, 0x00000264); - pci_write_config16(dev, 0xa0, 0x0040); - pci_write_config32(dev, 0xa4, 0x00220043); + pci_write_config16(dev, SATA_SRI, 0x0018); + pci_write_config32(dev, SATA_SRD, 0x00000264); + pci_write_config16(dev, SATA_SRI, 0x0040); + pci_write_config32(dev, SATA_SRD, 0x00220043); } @@ -57,4 +63,3 @@ static const struct pci_driver sata_driver_nr __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801EB_SATA, }; - diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c index 6bb4899..eb2794c 100644 --- a/src/southbridge/intel/i82801ex/smbus.c +++ b/src/southbridge/intel/i82801ex/smbus.c @@ -16,7 +16,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, SMB_BASE); return do_smbus_read_byte(res->base, device, address); } @@ -46,4 +46,3 @@ static const struct pci_driver smbus_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_SMB, }; - diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h index f330c0a..a9167d2 100644 --- a/src/southbridge/intel/i82801ex/smbus.h +++ b/src/southbridge/intel/i82801ex/smbus.h @@ -1,5 +1,10 @@ #include +#define SMBUS_IO_BASE 0xf00 +#define SMB_BASE 0x20 +#define SLV_CMD 0x11 +#define HOSTC 0x40 + #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3 @@ -102,4 +107,3 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned } return byte; } - diff --git a/src/southbridge/intel/i82801ex/uhci.c b/src/southbridge/intel/i82801ex/uhci.c index 56536b7..c9cf82e 100644 --- a/src/southbridge/intel/i82801ex/uhci.c +++ b/src/southbridge/intel/i82801ex/uhci.c @@ -53,4 +53,3 @@ static const struct pci_driver usb3_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_USB3, }; - diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c index 26f6644..3f02f61 100644 --- a/src/southbridge/intel/i82801ex/watchdog.c +++ b/src/southbridge/intel/i82801ex/watchdog.c @@ -3,6 +3,9 @@ #include #include #include +#include "i82801ex.h" + +#define PMBASE 0x40 void watchdog_off(void) { @@ -12,11 +15,11 @@ void watchdog_off(void) /* turn off the ICH5 watchdog */ dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); + value = pci_read_config16(dev, PCICMD); value |= (1 << 10); - pci_write_config16(dev, 0x04, value); + pci_write_config16(dev, PCICMD, value); /* Get TCO base */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + base = (pci_read_config32(dev, PMBASE) & 0x0fffe) + 0x60; /* Disable the watchdog timer */ value = inw(base + 0x08); value |= 1 << 11; @@ -26,4 +29,3 @@ void watchdog_off(void) outw(0x0002, base + 0x06); printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); } - diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 559e982..b80e514 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -45,3 +45,14 @@ static void inline w83627thg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +#ifndef __ROMCC__ +void w83627thg_set_clksel_48(device_t dev) { + u8 reg8; + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} +#endif diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index 73be544..99ff565 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -34,4 +34,6 @@ #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware monitor */ +void w83627thg_set_clksel_48(device_t dev); + #endif diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index db7fca0..0ba11d6 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -22,7 +22,7 @@ PROGRAM = inteltool CC = gcc -INSTALL = /usr/bin/install +INSTALL = install PREFIX = /usr/local CFLAGS = -O2 -g -Wall -W LDFLAGS = -lpci -lz diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 5cc7650..f485a50 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -21,7 +21,7 @@ PROGRAM = superiotool CC = gcc -INSTALL = /usr/bin/install +INSTALL = install PREFIX = /usr/local # Set the superiotool version string from the highest revision number From gerrit at coreboot.org Tue Nov 8 04:11:15 2011 From: gerrit at coreboot.org (Idwer Vollering (vidwer@gmail.com)) Date: Tue, 8 Nov 2011 04:11:15 +0100 Subject: [coreboot] Patch set updated for coreboot: 3061010 Make the installation section Makefile of inteltool and superiotool more flexible. References: Message-ID: Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/416 -gerrit commit 306101099771a3d4c9772e668ebfb622699c9b27 Author: Oskar Enoksson Date: Tue Oct 4 22:15:51 2011 +0200 Make the installation section Makefile of inteltool and superiotool more flexible. Change-Id: I0a85cb469bd1188fcd4e88df59380ffa5828496f Signed-off-by: Idwer Vollering --- src/mainboard/hp/dl145_g1/Kconfig | 1 + src/mainboard/hp/dl145_g1/get_bus_conf.c | 52 ++++++++++++---------------- src/mainboard/hp/dl145_g1/irq_tables.c | 19 +++------- src/mainboard/hp/dl145_g1/mb_sysconf.h | 20 +++++++++++ src/mainboard/hp/dl145_g1/mptable.c | 36 +++++++------------ src/mainboard/hp/dl145_g1/romstage.c | 55 +++++++++++++++++------------- util/inteltool/Makefile | 2 +- util/superiotool/Makefile | 2 +- 8 files changed, 96 insertions(+), 91 deletions(-) diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index eb90b07..ebd7ffd 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO # select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index e4721ce..6ea751d 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -10,19 +10,12 @@ #include #include +#include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -//busnum is default -unsigned char bus_8131_0 = 1; -unsigned char bus_8131_1 = 2; -unsigned char bus_8131_2 = 3; -unsigned char bus_8111_0 = 1; -unsigned char bus_8111_1 = 4; -unsigned apicid_8111 ; -unsigned apicid_8131_1; -unsigned apicid_8131_2; +struct mb_sysconf_t mb_sysconf; -unsigned pci1234x[] = +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -34,7 +27,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -45,8 +38,6 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned sbdn3; - static unsigned get_bus_conf_done = 0; @@ -63,6 +54,9 @@ void get_bus_conf(void) get_bus_conf_done = 1; + sysconf.mb = &mb_sysconf; + struct mb_sysconf_t *m = sysconf.mb; + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i> 8) & 0xff; - sbdn3 = sysconf.hcdn[0] & 0xff; + m->sbdn3 = sysconf.hcdn[0] & 0xff; - bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; - bus_8111_0 = bus_8131_0; + m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; + m->bus_8111_0 = m->bus_8131_0; /* 8111 */ - dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0); } /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0)); if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0); } - /* 8132-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); + /* 8131-2 */ + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0)); if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0); } @@ -111,7 +105,7 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + m->apicid_8111 = apicid_base+0; + m->apicid_8131_1 = apicid_base+1; + m->apicid_8131_2 = apicid_base+2; } diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c index b53a992..9d70a89 100644 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ b/src/mainboard/hp/dl145_g1/irq_tables.c @@ -11,6 +11,7 @@ #include #include +#include "mb_sysconf.h" static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, @@ -30,23 +31,13 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev pirq_info->rfu = rfu; } -extern unsigned char bus_8131_0; -extern unsigned char bus_8131_1; -extern unsigned char bus_8131_2; -extern unsigned char bus_8111_0; -extern unsigned char bus_8111_1; - -extern unsigned sbdn3; - - - unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; uint8_t *v; + struct mb_sysconf_t *m = sysconf.mb; uint8_t sum=0; int i; @@ -66,7 +57,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_8111_0; + pirq->rtr_bus = m->bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; @@ -81,10 +72,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge -// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; pirq_info++; slot_num++; diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h new file mode 100644 index 0000000..0bceab4 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h @@ -0,0 +1,20 @@ +#ifndef MB_SYSCONF_H + +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_8131_0; + unsigned char bus_8131_1; + unsigned char bus_8131_2; + unsigned char bus_8111_0; + unsigned char bus_8111_1; + + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2; + + unsigned sbdn3; +}; + +#endif + diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index 010f986..c15dff6 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -5,17 +5,7 @@ #include #include #include - -extern unsigned char bus_8131_0; -extern unsigned char bus_8131_1; -extern unsigned char bus_8131_2; -extern unsigned char bus_8111_0; -extern unsigned char bus_8111_1; -extern unsigned apicid_8111; -extern unsigned apicid_8131_1; -extern unsigned apicid_8131_2; - -extern unsigned sbdn3; +#include "mb_sysconf.h" static void *smp_write_config_table(void *v) { @@ -30,31 +20,33 @@ static void *smp_write_config_table(void *v) get_bus_conf(); + struct mb_sysconf_t *m = sysconf.mb; + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base); + smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base); } } - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base); + smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base); } } } - mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0); + mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); // // The commented-out lines are auto-detected on my servers. @@ -66,18 +58,18 @@ static void *smp_write_config_table(void *v) //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); // Integrated AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13); // On board ATI Rage XL //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); // On board Broadcom nics - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00); // On board LSI SCSI //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); // PCIX-133 Slot - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index f51b4c4..c0a12d9 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -1,17 +1,17 @@ #include #include #include +#include #include #include #include #include #include #include -#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/amdk8.h" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/early_serial.c" @@ -55,7 +55,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); } while ((ret!=0) && (i-->0)); - smbus_write_byte(SMBUS_HUB, 0x03, 0); } @@ -77,6 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -86,8 +86,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#define RC0 ((1<<1)<<8) // Not sure about these values -#define RC1 ((1<<2)<<8) // Not sure about these values +#define RC0 ((1<<1)<<8) +#define RC1 ((1<<2)<<8) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -101,13 +101,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) RC1|DIMM1, RC1|DIMM3, 0, 0, #endif }; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; - unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + int needs_reset = 0; + unsigned bsp_apicid = 0; if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx); + bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -115,47 +116,53 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + setup_dl145g1_resource_map(); //setup_default_resource_map(); - needs_reset = setup_coherent_ht_domain(); - - wait_all_core0_started(); +#if CONFIG_MEM_TRAIN_SEQ == 1 + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram +#endif + setup_coherent_ht_domain(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - needs_reset |= ht_setup_chains_x(); + ht_setup_chains_x(sysinfo); - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } enable_smbus(); int i; for(i=0;i<2;i++) { - activate_spd_rom(&ctrl[i]); + activate_spd_rom(&sysinfo->ctrl[i]); } - for(i=2;i<8;i<<=1) { + for(i=RC0;i<=RC1;i<<=1) { change_i2c_mux(i); } - //dump_spd_registers(&ctrl[0]); - //dump_spd_registers(&ctrl[1]); + //dump_spd_registers(&sysinfo->ctrl[0]); + //dump_spd_registers(&sysinfo->ctrl[1]); //dump_smbus_registers(); allow_all_aps_stop(bsp_apicid); - nodes = get_nodes(); //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); - sdram_initialize(nodes, ctrl); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); //dump_pci_devices(); diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index db7fca0..0ba11d6 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -22,7 +22,7 @@ PROGRAM = inteltool CC = gcc -INSTALL = /usr/bin/install +INSTALL = install PREFIX = /usr/local CFLAGS = -O2 -g -Wall -W LDFLAGS = -lpci -lz diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index e7d2f63..598c01e 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -21,7 +21,7 @@ PROGRAM = superiotool CC = gcc -INSTALL = /usr/bin/install +INSTALL = install PREFIX = /usr/local # Set the superiotool version string from the highest revision number From gerrit at coreboot.org Tue Nov 8 07:28:00 2011 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 8 Nov 2011 07:28:00 +0100 Subject: [coreboot] New patch to review for coreboot: 87407f2 Cleanup Persimmon mainboard whitespace. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/427 -gerrit commit 87407f2e27b9dd3f2ba72c4e0f538843a436b2bc Author: Marc Jones Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Change-Id: I389bde86c5583a4fb37a699162b65b475ed94ddc Signed-off-by: Marc Jones --- src/mainboard/amd/persimmon/BiosCallOuts.c | 938 ++++++++++---------- src/mainboard/amd/persimmon/BiosCallOuts.h | 48 +- src/mainboard/amd/persimmon/Kconfig | 140 ++-- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 208 +++--- .../amd/persimmon/PlatformGnbPcieComplex.h | 68 +- src/mainboard/amd/persimmon/acpi_tables.c | 309 ++++---- src/mainboard/amd/persimmon/agesawrapper.c | 729 ++++++++-------- src/mainboard/amd/persimmon/agesawrapper.h | 40 +- src/mainboard/amd/persimmon/buildOpts.c | 568 ++++++------ src/mainboard/amd/persimmon/cmos.layout | 10 +- src/mainboard/amd/persimmon/devicetree.cb | 171 ++-- src/mainboard/amd/persimmon/dimmSpd.c | 191 ++-- src/mainboard/amd/persimmon/dimmSpd.h | 8 +- src/mainboard/amd/persimmon/get_bus_conf.c | 109 ++-- src/mainboard/amd/persimmon/mainboard.c | 25 +- src/mainboard/amd/persimmon/mptable.c | 168 ++-- src/mainboard/amd/persimmon/romstage.c | 119 ++-- 17 files changed, 1915 insertions(+), 1934 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 3cfd741..c8379ff 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "agesawrapper.h" @@ -26,589 +26,581 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, - BiosAllocateBuffer - }, + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, - {AGESA_DEALLOCATE_BUFFER, - BiosDeallocateBuffer - }, + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, - {AGESA_DO_RESET, - BiosReset - }, + {AGESA_DO_RESET, + BiosReset + }, - {AGESA_LOCATE_BUFFER, - BiosLocateBuffer - }, + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, - {AGESA_READ_SPD, - BiosReadSpd - }, + {AGESA_READ_SPD, + BiosReadSpd + }, - {AGESA_READ_SPD_RECOVERY, - BiosDefaultRet - }, + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, - {AGESA_RUNFUNC_ONAP, - BiosRunFuncOnAp - }, + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, - {AGESA_GNB_PCIE_SLOT_RESET, - BiosGnbPcieSlotReset - }, + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset + }, - {AGESA_HOOKBEFORE_DRAM_INIT, - BiosHookBeforeDramInit - }, + {AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, - BiosHookBeforeDramInitRecovery - }, + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, - {AGESA_HOOKBEFORE_DQS_TRAINING, - BiosHookBeforeDQSTraining - }, + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, - BiosHookBeforeExitSelfRefresh - }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINTN i; - AGESA_STATUS CalloutStatus; - UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); - CalloutStatus = AGESA_UNSUPPORTED; + CalloutStatus = AGESA_UNSUPPORTED; - for (i = 0; i < CallOutCount; i++) - { - if (BiosCallouts[i].CalloutName == Func) - { - CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); - return CalloutStatus; - } - } + for (i = 0; i < CallOutCount; i++) { + if (BiosCallouts[i].CalloutName == Func) { + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + return CalloutStatus; + } + } - return CalloutStatus; + return CalloutStatus; } AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - BIOS_BUFFER_NODE *CurrNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *BestFitNodePtr; - BIOS_BUFFER_NODE *BestFitPrevNodePtr; - BIOS_BUFFER_NODE *NextFreePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; - AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); - AllocParams->BufferPointer = NULL; + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; - AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { - /* First allocation */ - CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - CurrNodePtr->BufferHandle = AllocParams->BufferHandle; - CurrNodePtr->BufferSize = AllocParams->BufferLength; - CurrNodePtr->NextNodeOffset = 0; - AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); - /* Update the remaining free space */ - FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; - FreedNodePtr->NextNodeOffset = 0; + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; - /* Update the offsets for Allocated and Freed nodes */ - BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; - BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; - } else { - /* Find out whether BufferHandle has been allocated on the heap. */ - /* If it has, return AGESA_BOUNDS_CHK */ - CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - while (CurrNodeOffset != 0) { - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { - return AGESA_BOUNDS_CHK; - } - CurrNodeOffset = CurrNodePtr->NextNodeOffset; - /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - to the end of the allocated nodes list. - */ + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ - } - /* Find the node that best fits the requested buffer size */ - FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; - PrevNodeOffset = FreedNodeOffset; - BestFitNodeOffset = 0; - BestFitPrevNodeOffset = 0; - while (FreedNodeOffset != 0) { - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - if (BestFitNodeOffset == 0) { - /* First node that fits the requested buffer size */ - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } else { - /* Find out whether current node is a better fit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } - } - } - PrevNodeOffset = FreedNodeOffset; - FreedNodeOffset = FreedNodePtr->NextNodeOffset; - } /* end of while loop */ + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); - if (BestFitNodeOffset == 0) { - /* If we could not find a node that fits the requested buffer */ - /* size, return AGESA_BOUNDS_CHK */ - return AGESA_BOUNDS_CHK; - } else { - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); - /* If BestFitNode is larger than the requested buffer, fragment the node further */ - if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } - NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); - NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; - } else { - /* Otherwise, next free node is NextNodeOffset of BestFitNode */ - NextFreeOffset = BestFitNodePtr->NextNodeOffset; - } + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } - /* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node - */ - if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { - BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; - } else { - BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; - } + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; - /* Add BestFitNode to the list of Allocated nodes */ - CurrNodePtr->NextNodeOffset = BestFitNodeOffset; - BestFitNodePtr->BufferSize = AllocParams->BufferLength; - BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; - BestFitNodePtr->NextNodeOffset = 0; + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } - /* Remove BestFitNode from list of Freed nodes */ - AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); - } - } - - return AGESA_SUCCESS; + return AGESA_SUCCESS; } AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; - /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found - */ - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - PrevNodeOffset = AllocNodeOffset; + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { - return AGESA_BOUNDS_CHK; - } - PrevNodeOffset = AllocNodeOffset; - AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - } + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - /* Remove target node from list of allocated nodes */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); - PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; - /* Zero out the buffer, and clear the BufferHandle */ - LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); - AllocNodePtr->BufferHandle = 0; - AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } - /* Add deallocated node in order to the list of freed nodes */ - FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; - EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); - if (AllocNodeOffset < FreedNodeOffset) { - /* Add to the start of the freed list */ - if (EndNodeOffset == FreedNodeOffset) { - /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ - AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - /* Clear the BufferSize and NextNodeOffset of the previous first node */ - FreedNodePtr->BufferSize = 0; - FreedNodePtr->NextNodeOffset = 0; + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; - } else { - /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE - */ - AllocNodePtr->NextNodeOffset = FreedNodeOffset; - } - /* Update StartOfFreedNodes to the new first node */ - BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; - } else { - /* Traverse list of freed nodes to find where the deallocated node - should be place - */ - NextNodeOffset = FreedNodeOffset; - NextNodePtr = FreedNodePtr; - while (AllocNodeOffset > NextNodeOffset) { - PrevNodeOffset = NextNodeOffset; - if (NextNodePtr->NextNodeOffset == 0) { - break; - } - NextNodeOffset = NextNodePtr->NextNodeOffset; - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); - } + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; - /* If deallocated node is adjacent to the next node, - concatenate both nodes - */ - if (NextNodeOffset == EndNodeOffset) { - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); - AllocNodePtr->BufferSize += NextNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } - NextNodePtr->BufferSize = 0; - NextNodePtr->NextNodeOffset = 0; - } else { - /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ - AllocNodePtr->NextNodeOffset = NextNodeOffset; - } - /* If deallocated node is adjacent to the previous node, - concatenate both nodes - */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); - EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; - if (AllocNodeOffset == EndNodeOffset) { - PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; - PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; - AllocNodePtr->BufferSize = 0; - AllocNodePtr->NextNodeOffset = 0; - } else { - PrevNodePtr->NextNodeOffset = AllocNodeOffset; - } - } - return AGESA_SUCCESS; + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; } AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { - AllocParams->BufferPointer = NULL; - AllocParams->BufferLength = 0; - return AGESA_BOUNDS_CHK; - } else { - AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - } - } + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } - AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); - AllocParams->BufferLength = AllocNodePtr->BufferSize; + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; - return AGESA_SUCCESS; + return AGESA_SUCCESS; } AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status; - Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); - return Status; + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + return Status; } AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; - AMD_CONFIG_PARAMS *StdHeader; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; - ResetType = Data; - StdHeader = ConfigPtr; + ResetType = Data; + StdHeader = ConfigPtr; - // - // Perform the RESET based upon the ResetType. In case of - // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to - // AmdResetManager. During the critical condition, where reset is required - // immediately, the reset will be invoked directly by writing 0x04 to port - // 0xCF9 (Reset Port). - // - switch (ResetType) { - case WARM_RESET_WHENEVER: - case COLD_RESET_WHENEVER: - break; + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; - case WARM_RESET_IMMEDIATELY: - case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); - break; + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; - default: - break; - } + default: + break; + } - Status = 0; - return Status; + Status = 0; + return Status; } AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); - return Status; + return Status; } AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - return AGESA_UNSUPPORTED; + return AGESA_UNSUPPORTED; } -/* Call the host environment interface to provide a user hook opportunity. */ +/* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - return AGESA_SUCCESS; + return AGESA_SUCCESS; } -/* Call the host environment interface to provide a user hook opportunity. */ +/* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; - FcnData = Data; - MemData = ConfigPtr; + FcnData = Data; + MemData = ConfigPtr; - Status = AGESA_SUCCESS; - /* Get SB MMIO Base (AcpiMmioAddr) */ - WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8<<8; - WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - switch(MemData->ParameterListPtr->DDR3Voltage){ - case VOLT1_35: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_25: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_5: - default: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - } - return Status; + switch(MemData->ParameterListPtr->DDR3Voltage){ + case VOLT1_35: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_25: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_5: + default: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + } + return Status; } -/* Call the host environment interface to provide a user hook opportunity. */ +/* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - return AGESA_SUCCESS; + return AGESA_SUCCESS; } -/* Call the host environment interface to provide a user hook opportunity. */ +/* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - return AGESA_SUCCESS; + return AGESA_SUCCESS; } /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; - FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16|=Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 4: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - } - break; - case 6: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - } - break; - case 7: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - } - break; - } - return Status; + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 4: + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + } + break; + case 6: + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + } + break; + case 7: + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; } diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index b7c7883..e023e38 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef _BIOS_CALLOUT_H_ @@ -23,20 +23,20 @@ #include "Porting.h" #include "AGESA.h" -#define REQUIRED_CALLOUTS 12 -#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define REQUIRED_CALLOUTS 12 +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ typedef struct _BIOS_HEAP_MANAGER { - //UINT32 AvailableSize; - UINT32 StartOfAllocatedNodes; - UINT32 StartOfFreedNodes; + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; } BIOS_HEAP_MANAGER; typedef struct _BIOS_BUFFER_NODE { - UINT32 BufferHandle; - UINT32 BufferSize; - UINT32 NextNodeOffset; + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; } BIOS_BUFFER_NODE; /* * CALLOUTS @@ -54,27 +54,27 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* AGESA ADVANCED CALLOUTS - MEMORY */ -AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); /* BIOS DEFAULT RET */ AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ +/* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ +/* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ +/* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ +/* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 93b4554..e01e101 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -9,132 +9,130 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_X86 - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_FINTEK_F81865F - select BOARD_HAS_FADT - select HAVE_BUS_CONFIG - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select SERIAL_CPU_INIT - select AMDMCT - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA config AMD_AGESA - bool - default y + bool + default y config MAINBOARD_DIR - string - default amd/persimmon + string + default amd/persimmon config APIC_ID_OFFSET - hex - default 0x0 + hex + default 0x0 config MAINBOARD_PART_NUMBER - string - default "Persimmon" + string + default "Persimmon" config HW_MEM_HOLE_SIZEK - hex - default 0x200000 + hex + default 0x200000 config MAX_CPUS - int - default 2 + int + default 2 config MAX_PHYSICAL_CPUS - int - default 1 + int + default 1 config HW_MEM_HOLE_SIZE_AUTO_INC - bool - default n + bool + default n config MEM_TRAIN_SEQ - int - default 2 + int + default 2 config IRQ_SLOT_COUNT - int - default 11 + int + default 11 config RAMTOP - hex - default 0x1000000 + hex + default 0x1000000 config HEAP_SIZE - hex - default 0xc0000 + hex + default 0xc0000 config STACK_SIZE - hex - default 0x10000 + hex + default 0x10000 config ACPI_SSDTX_NUM - int - default 0 + int + default 0 config RAMBASE - hex - default 0x200000 + hex + default 0x200000 config SIO_PORT - hex - default 0x4e + hex + default 0x4e config ONBOARD_VGA_IS_PRIMARY - bool - default y + bool + default y config VGA_BIOS - bool - default n + bool + default n #config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVbios.bin" config VGA_BIOS_ID - string - default "1002,9802" - + string + default "1002,9802" config SB800_AHCI_ROM - bool - default n + bool + default n config DRIVERS_PS2_KEYBOARD - bool - default n + bool + default n config WARNINGS_ARE_ERRORS - bool - default n + bool + default n endif # BOARD_AMD_PERSIMMON - diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index b0389b8..5e37f51 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "AGESA.h" @@ -28,141 +28,141 @@ /*---------------------------------------------------------------------------------------*/ /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This is the stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ VOID OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) + IN OUT AMD_EARLY_PARAMS *InitEarly + ) { - AGESA_STATUS Status; - VOID *BrazosPcieComplexListPtr; - VOID *BrazosPciePortPtr; - VOID *BrazosPcieDdiPtr; + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; + ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) - }, + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) - }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) - { - 0, //Descriptor flags - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeDP, Aux1, Hdp1} - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} - } + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeDP, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } }; PCIe_COMPLEX_DESCRIPTOR Brazos = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] }; - // GNB PCIe topology Porting + // GNB PCIe topology Porting - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; - AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); - if ( Status!= AGESA_SUCCESS) { - // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); - return; - } + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - LibAmdMemFill (BrazosPcieComplexListPtr, - 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), - &InitEarly->StdHeader); + LibAmdMemFill (BrazosPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); - LibAmdMemFill (BrazosPciePortPtr, - 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, - &InitEarly->StdHeader); + LibAmdMemFill (BrazosPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 5, + &InitEarly->StdHeader); - LibAmdMemFill (BrazosPcieDdiPtr, - 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, - &InitEarly->StdHeader); + LibAmdMemFill (BrazosPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 2, + &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index b51089f..b50cb1a 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H @@ -25,48 +25,48 @@ #include "amdlib.h" //GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced VOID OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); + IN OUT AMD_EARLY_PARAMS *InitEarly + ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 7c5aa39..637a304 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include @@ -35,15 +35,15 @@ static void dump_mem(u32 start, u32 end) { - u32 i; - print_debug("dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); - } - print_debug("\n"); + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); } #endif @@ -52,193 +52,194 @@ extern const unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) { - /* Just a dummy */ - return current; + /* Just a dummy */ + return current; } unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edige-triggered, Active high */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ - return current; + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; } unsigned long acpi_fill_slit(unsigned long current) { - // Not implemented - return current; + // Not implemented + return current; } unsigned long acpi_fill_srat(unsigned long current) { - /* No NUMA, no SRAT */ - return current; + /* No NUMA, no SRAT */ + return current; } unsigned long write_acpi_tables(unsigned long start) { - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; - current = start; + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); - /* clear all table memory */ - memset((void *)start, 0, current - start); + /* clear all table memory */ + memset((void *)start, 0, current - start); - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); - /* FDAT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); + /* FDAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); - /* - * We explicitly add these tables later on: - */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); + /* + * We explicitly add these tables later on: + */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); - /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); - /* SRAT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); - if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - //acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - } + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } - /* SLIT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); - if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - //acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - } + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } - /* SSDT */ - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; - current += ssdt->length; - } - else { - ssdt = (acpi_header_t *) current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - } - acpi_add_table(rsdp,ssdt); + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + ssdt = (acpi_header_t *) current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } + acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); #if DUMP_ACPI_TABLES == 1 - printk(BIOS_DEBUG, "rsdp\n"); - dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); - printk(BIOS_DEBUG, "rsdt\n"); - dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); - printk(BIOS_DEBUG, "madt\n"); - dump_mem(madt, ((void *)madt) + madt->header.length); + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); - printk(BIOS_DEBUG, "srat\n"); - dump_mem(srat, ((void *)srat) + srat->header.length); + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); - printk(BIOS_DEBUG, "slit\n"); - dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); - printk(BIOS_DEBUG, "ssdt\n"); - dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); - printk(BIOS_DEBUG, "fadt\n"); - dump_mem(fadt, ((void *)fadt) + fadt->header.length); + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); #endif - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + printk(BIOS_INFO, "ACPI: done.\n"); + return current; } diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 9d9f864..89f171b 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -9,16 +9,16 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ @@ -41,501 +41,500 @@ #define FILECODE UNASSIGNED_FILE_FILECODE /*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ #define MMCONF_ENABLE 1 /* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL; /*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ /*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ UINT32 agesawrapper_amdinitcpuio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; // last address before non-posted range - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; // last address before non-posted range + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitmmio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; - UINT8 BusRangeVal = 0; - UINT8 BusNum; - UINT8 Index; + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ - for (Index = 0; Index < 8; Index++) { - BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; - if (BusNum == 1) { - BusRangeVal = Index; - break; - } - } + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } - MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000ull; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000ull; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* Set Ontario Link Data */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); - PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitreset ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = NULL; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; } UINT32 agesawrapper_amdinitearly ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return (UINT32)status; } UINT32 agesawrapper_amdinitpost ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; - AMD_INTERFACE_PARAMS AmdParamStruct; - BIOS_HEAP_MANAGER *BiosManagerPtr; + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); + AmdCreateStruct (&AmdParamStruct); + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; - HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { - *HeadPtr = 0x00000000; - HeadPtr++; - } - BiosManagerPtr->StartOfAllocatedNodes = 0; - BiosManagerPtr->StartOfFreedNodes = 0; + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; - return (UINT32)status; + return (UINT32)status; } UINT32 agesawrapper_amdinitenv ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - PCI_ADDR PciAddress; - UINT32 PciValue; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - /* Write to D1F0x18 */ - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x00010100; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + /* Write to D1F0x18 */ + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x00010100; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize GMM Base Address for Legacy Bridge Mode - * Modify B1D5F0x18 - */ - PciAddress.Address.Bus = 1; - PciAddress.Address.Device = 5; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; + /* Initialize GMM Base Address for Legacy Bridge Mode + * Modify B1D5F0x18 + */ + PciAddress.Address.Bus = 1; + PciAddress.Address.Device = 5; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize FB Base Address for Legacy Bridge Mode - * Modify B1D5F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + /* Initialize FB Base Address for Legacy Bridge Mode + * Modify B1D5F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize GMM Base Address for Pcie Mode - * Modify B0D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; + /* Initialize GMM Base Address for Pcie Mode + * Modify B0D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize FB Base Address for Pcie Mode - * Modify B0D1F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + /* Initialize FB Base Address for Pcie Mode + * Modify B0D1F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize MMIO Base and Limit Address - * Modify B0D1F0x20 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x20; + /* Initialize MMIO Base and Limit Address + * Modify B0D1F0x20 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x20; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96009600; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96009600; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize MMIO Prefetchable Memory Limit and Base - * Modify B0D1F0x24 - */ - PciAddress.Address.Register = 0x24; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x8FF18001; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - AmdReleaseStruct (&AmdParamStruct); + /* Initialize MMIO Prefetchable Memory Limit and Base + * Modify B0D1F0x24 + */ + PciAddress.Address.Register = 0x24; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x8FF18001; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return (UINT32)status; } VOID * agesawrapper_getlateinitptr ( - int pick - ) + int pick + ) { - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - default: - return NULL; - } + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } } UINT32 agesawrapper_amdinitmid ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); + AmdCreateStruct (&AmdParamStruct); - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return (UINT32)status; } UINT32 agesawrapper_amdinitlate ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; - Status = AmdInitLate (&AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + Status = AmdInitLate (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; - return (UINT32)Status; + return (UINT32)Status; } UINT32 agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) { - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; - Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } - return (UINT32)Status; + return (UINT32)Status; } UINT32 agesawrapper_amdreadeventlog ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } - return (UINT32)Status; + return (UINT32)Status; } diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index f8d924e..7bed570 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -9,16 +9,16 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ @@ -30,46 +30,46 @@ #include "AGESA.h" /*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ }; /*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */ typedef struct { - UINT32 CalloutName; - AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); } BIOS_CALLOUT_STRUCT; /*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ /*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 8025f4f..368eed2 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /** @@ -28,32 +28,32 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE -/* Select the cpu family. */ +/* Select the cpu family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the cpu socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE #define INSTALL_S1G4_SOCKET_SUPPORT FALSE #define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -61,163 +61,163 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE /* * Agesa entry points used in this implementation. */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 /* * Agesa configuration values selection. @@ -230,21 +230,21 @@ /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -259,7 +259,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "GnbInterface.h" /***************************************************************************** - * Define the RELEASE VERSION string + * Define the RELEASE VERSION string * * The Release Version string should identify the next planned release. * When a branch is made in preparation for a release, the release manager @@ -271,123 +271,123 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} +// This is the delivery package title, "BrazosPI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode // The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product +// no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) // Instantiate all solution relevant data. #include "PlatformInstall.h" /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), - PSO_END + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END }; /* @@ -405,13 +405,13 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), // - // NOTE: - // The following training hardcode values are example values that were taken from a tilapia motherboard - // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in - // the table and replace the byte lane values with your own. + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -437,22 +437,22 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); /* *************************************************************************** - * Optional User code to be included into the AGESA build - * These may be 32-bit call-out routines... + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, -// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd -// ) +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) //{ -// /* platform code to read an SPD... */ -// return Status; +// /* platform code to read an SPD... */ +// return Status; //} diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout index 8315401..3b98cbb 100644 --- a/src/mainboard/amd/persimmon/cmos.layout +++ b/src/mainboard/amd/persimmon/cmos.layout @@ -1,18 +1,18 @@ #***************************************************************************** -# +# # This file is part of the coreboot project. -# +# # Copyright (C) 2011 Advanced Micro Devices, Inc. -# +# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index b47e6b9..e5bbca2 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -17,92 +17,91 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # chip northbridge/amd/agesa/family14/root_complex - device lapic_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device pci_domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + device lapic_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #pci_domain + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #pci_domain end #northbridge/amd/agesa/family14/root_complex - diff --git a/src/mainboard/amd/persimmon/dimmSpd.c b/src/mainboard/amd/persimmon/dimmSpd.c index 2bd27d6..1343ae9 100644 --- a/src/mainboard/amd/persimmon/dimmSpd.c +++ b/src/mainboard/amd/persimmon/dimmSpd.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "Porting.h" @@ -30,19 +30,19 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA * SPD address table - porting required */ -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm - { - // socket 0 - { - {0xA0, 0xA2}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - }; +static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm +{ +// socket 0 + { + {0xA0, 0xA2}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + // socket 1 + { + {0x00, 0x00}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, +}; /*----------------------------------------------------------------------------- * @@ -50,117 +50,114 @@ static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm */ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) - { - unsigned int status; - UINT64 limit; +{ + unsigned int status; + UINT64 limit; - address |= 1; // set read bit + address |= 1; // set read bit - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} /*----------------------------------------------------------------------------- * * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData + * this function is faster function readSmbusByteData */ static int readSmbusByte (int iobase, int address, char *buffer) - { - unsigned int status; - UINT64 limit; +{ + unsigned int status; + UINT64 limit; - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} /*--------------------------------------------------------------------------- * * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. */ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) - { - int index, error; +{ + int index, error; - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) { + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } - return 0; - } + return 0; +} static void writePmReg (int reg, int data) - { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); - } + { + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); + } static void setupFch (int ioBase) - { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz - } +{ + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + writePmReg (0x29, 0x80); + writePmReg (0x28, 0x61); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz +} AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) - { - int spdAddress, ioBase; +{ + int spdAddress, ioBase; - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = 0xB00; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); - } + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + ioBase = 0xB00; + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); +} diff --git a/src/mainboard/amd/persimmon/dimmSpd.h b/src/mainboard/amd/persimmon/dimmSpd.h index 069c34a..caaefbe 100644 --- a/src/mainboard/amd/persimmon/dimmSpd.h +++ b/src/mainboard/amd/persimmon/dimmSpd.h @@ -50,10 +50,10 @@ AGESA_STATUS AmdMemoryReadSPD ( - IN UINT32 Func, - IN UINT32 Data, - IN OUT AGESA_READ_SPD_PARAMS *SpdData - ); + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); /*--------------------------------------------------------------------------------------- * L O C A L F U N C T I O N S diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 2d28023..0142762 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include @@ -43,7 +43,7 @@ u32 apicid_sb800; * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ u32 pci1234x[] = { - 0x0000ff0, + 0x0000ff0, }; u32 bus_type[256]; @@ -54,83 +54,80 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { - u32 apicid_base; - u32 status; + u32 apicid_base; + u32 status; - device_t dev; - int i, j; + device_t dev; + int i, j; - if (get_bus_conf_done == 1) - return; /* do it only once */ + if (get_bus_conf_done == 1) + return; /* do it only once */ - get_bus_conf_done = 1; + get_bus_conf_done = 1; /* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * call. The logically correct place to call AmdInitLate is after PCI scan is done, * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform * specific entry point between the S3 resume decision point and the call to * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right + * the ACPI table write functions. The first of ose would seem to be the right * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning + * called before the ACPI tables are written. This routine is called at the beginning * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } - sbdn_sb800 = 0; + sbdn_sb800 = 0; - for (i = 0; i < 3; i++) { - bus_sb800[i] = 0; - } + for (i = 0; i < 3; i++) { + bus_sb800[i] = 0; + } - for (i = 0; i < 256; i++) { - bus_type[i] = 0; /* default ISA bus. */ - } + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + bus_type[0] = 1; /* pci */ - bus_type[0] = 1; /* pci */ +// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + /* sb800 */ + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); - /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + if (dev) { + bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb800[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + if (dev) { + bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } - if (dev) { - bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + for (j = bus_sb800[2]; j < bus_isa; j++) + bus_type[j] = 1; - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - for (j = bus_sb800[1]; j < bus_isa; j++) - bus_type[j] = 1; - } - - for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); - if (dev) { - bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } - } - for (j = bus_sb800[2]; j < bus_isa; j++) - bus_type[j] = 1; - - - /* I/O APICs: APIC ID Version State Address */ - bus_isa = 10; - apicid_base = CONFIG_MAX_CPUS; - apicid_sb800 = apicid_base; + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_sb800 = apicid_base; #if CONFIG_AMD_SB_CIMX sb_Late_Post(); diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 135f8f4..3b181a1 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -63,14 +63,14 @@ static void persimmon_enable(device_t dev) /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); /* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); /* refer to UMA Size Consideration in Family14h BKDG. */ sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() @@ -78,17 +78,16 @@ static void persimmon_enable(device_t dev) uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ } else { - if (sys_mem >= 0x40000000) { - uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ - } - else { - uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ - } + if (sys_mem >= 0x40000000) { + uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } else { + uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); + __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ #else @@ -105,9 +104,9 @@ int add_mainboard_resources(struct lb_memory *mem) */ #if (CONFIG_GFXUMA == 1) printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", - uma_memory_base, uma_memory_size); + uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, - uma_memory_size); + uma_memory_size); #endif return 0; } diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 546d9bd..92c842f 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ @@ -35,124 +35,124 @@ extern u32 bus_type[256]; extern u32 sbdn_sb800; u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 }; static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int bus_isa; + struct mp_config_table *mc; + int bus_isa; - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); + mptable_init(mc, LAPIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); - smp_write_processors(mc); + smp_write_processors(mc); - get_bus_conf(); + get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); + mptable_write_buses(mc, NULL, &bus_isa); - /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ - u32 dword; - u8 byte; + u32 dword; + u8 byte; - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); - dword &= 0xFFFFFFF0; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + dword &= 0xFFFFFFF0; + smp_write_ioapic(mc, apicid_sb800, 0x21, dword); - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ #if CONFIG_GENERATE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + /* HD Audio: */ + PCI_INT(0x0, 0x14, 0x2, 0x12); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ + /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ - /* on board NIC & Slot PCIE. */ + /* on board NIC & Slot PCIE. */ - /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); - /* PCI_SLOT 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + /* PCI_SLOT 1. */ + PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); - /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); + /* PCI_SLOT 2. */ + PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); + PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); + PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ - /* Compute the checksums */ - return mptable_finalize(mc); + /* Compute the checksums */ + return mptable_finalize(mc); } unsigned long write_smp_table(unsigned long addr) { - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 0eb7490..bf8535f 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include @@ -44,78 +44,77 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - u32 val; + u32 val; - // all cores: allow caching of flash chip code and data - // (there are no cache-as-ram reliability concerns with family 14h) - __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); - // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time - __writemsr (0xc0010062, 0); + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + __writemsr (0xc0010062, 0); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); - post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } + post_code(0x31); + f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); - post_code(0x35); - val = agesawrapper_amdinitmmio(); + post_code(0x35); + val = agesawrapper_amdinitmmio(); - post_code(0x37); - val = agesawrapper_amdinitreset(); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); - } + post_code(0x37); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } - post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + post_code(0x38); + printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); - post_code(0x39); - val = agesawrapper_amdinitearly (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + post_code(0x39); + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); - post_code(0x40); - val = agesawrapper_amdinitpost (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); - post_code(0x41); - val = agesawrapper_amdinitenv (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); - post_code(0x50); - copy_and_run(0); + post_code(0x50); + copy_and_run(0); - post_code(0x54); // Should never see this post code. + post_code(0x54); // Should never see this post code. } - From r.marek at assembler.cz Tue Nov 8 09:33:02 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 08 Nov 2011 09:33:02 +0100 Subject: [coreboot] Cache-line trouble on Xeon In-Reply-To: <1320692491.9998.144.camel@obelix> References: <1320692491.9998.144.camel@obelix> Message-ID: <4EB8E93E.4000008@assembler.cz> Hi, Just a quick notes. There a peformance MSRs which have L2 fills counters. I did want to know on AMD how the fills/misses/etc works so I used that counters to see what is actually going on. http://oprofile.sourceforge.net/docs Has a list of events. > Problem 3: Cache re-allocation policy? > > Cache-lines for the stack must remain in L1 while the XIP ROM lines can > be thrown out whenever necessary. Generally, do dirty cache-lines remain > in L1 as long as there are non-dirty cache-lines that require less > effort to re-allocate? I think non-dirty stuff which is not modified is just discarded (XIP ROM)or moved to L2. The CR.NW mode differs accross Intel CPUs just check documentation what is it doing in your case (The architecture manuals). To get CAR working I would simply follow the BIOS with serialICE. Thanks Rudolf From paulepanter at users.sourceforge.net Tue Nov 8 11:05:39 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Tue, 08 Nov 2011 11:05:39 +0100 Subject: [coreboot] Patch set updated for coreboot: 897a07d Refactor src/southbridge/intel/i82801ex/ In-Reply-To: References: Message-ID: <1320746739.3915.5.camel@mattotaupa> Dear Idwer, Am Dienstag, den 08.11.2011, 03:23 +0100 schrieb Idwer Vollering: > Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/415 > > -gerrit > > commit 897a07d55541bec5336b67789cfc155c31053d41 > Author: Idwer Vollering > Date: Mon Nov 7 17:48:33 2011 +0100 > > Refactor src/southbridge/intel/i82801ex/ > > Change-Id: I8be22f0292e322562b117f1e8bf493ed25eb4bec > Signed-off-by: Idwer Vollering > --- > src/southbridge/intel/i82801ex/chip.h | 1 - > src/southbridge/intel/i82801ex/early_smbus.c | 32 ++++++++------ > src/southbridge/intel/i82801ex/ehci.c | 8 ++- > src/southbridge/intel/i82801ex/i82801ex.c | 12 +++--- > src/southbridge/intel/i82801ex/i82801ex.h | 26 +++++++++--- > src/southbridge/intel/i82801ex/ide.c | 15 +++---- > src/southbridge/intel/i82801ex/lpc.c | 59 +++++++++++++------------- > src/southbridge/intel/i82801ex/pci.c | 20 +++++---- > src/southbridge/intel/i82801ex/sata.c | 35 +++++++++------- > src/southbridge/intel/i82801ex/smbus.c | 3 +- > src/southbridge/intel/i82801ex/smbus.h | 6 ++- > src/southbridge/intel/i82801ex/uhci.c | 1 - > src/southbridge/intel/i82801ex/watchdog.c | 10 +++-- > src/superio/winbond/w83627thg/early_serial.c | 11 +++++ > src/superio/winbond/w83627thg/w83627thg.h | 2 + > 15 files changed, 141 insertions(+), 100 deletions(-) that new diff looks rather large. Especially in comparison with the former patch iteration. The w83627thg changes could also go in as a separate patch? What is the objective of the refactoring? To more conform with other targets? [?] Thanks, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From gerrit at coreboot.org Tue Nov 8 12:25:27 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 8 Nov 2011 12:25:27 +0100 Subject: [coreboot] Patch merged into coreboot/master: 8a703fb selfboot: cleanup References: Message-ID: the following patch was just integrated into master: commit 8a703fb508b048380007cccc0d24fd2ae629bae7 Author: Stefan Reinauer Date: Mon Nov 7 12:43:03 2011 -0800 selfboot: cleanup - move cbfs_load_payload to the end so we can drop the prototype - move lb_start and lb_end to the beginning so they can be used in other functions. - drop two unused function declarations - break a 80+ characters line - fix a comment Change-Id: I460aa1e2ccf9d95ac12233af001076f73ab0268e Signed-off-by: Stefan Reinauer Reviewed-By: Patrick Georgi at Tue Nov 8 12:25:25 2011, giving +2 See http://review.coreboot.org/424 for details. -gerrit From kyosti.malkki at gmail.com Tue Nov 8 12:55:12 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Tue, 08 Nov 2011 13:55:12 +0200 Subject: [coreboot] Cache-line trouble on Xeon In-Reply-To: <4EB8E93E.4000008@assembler.cz> References: <1320692491.9998.144.camel@obelix> <4EB8E93E.4000008@assembler.cz> Message-ID: <1320753312.9998.197.camel@obelix> On Tue, 2011-11-08 at 09:33 +0100, Rudolf Marek wrote: > Hi, > > Just a quick notes. There a peformance MSRs which have L2 fills counters. I did > want to know on AMD how the fills/misses/etc works so I used that counters to > see what is actually going on. > > http://oprofile.sourceforge.net/docs > > Has a list of events. Good tip! I should be able to use events BSQ_cache_reference and BSQ_allocation to count cache hits and misses. > The CR.NW mode differs accross Intel CPUs just check documentation what is it > doing in your case (The architecture manuals). To get CAR working I would simply > follow the BIOS with serialICE. Well, for Xeon CR0.NW is a don't care bit and it's always in no-fill mode. A part of my Problem 2 was that also inb()/outb() flushes modified cache-lines from L1 to (disabled?) L2 and system bus. I think with SerialICE I could not store a single valid cache-line in L1, as this would involve serial-io between any two store dword instructions. I just realised that attempts to use compressed ramstage on this mainboard have always halted on un-LZMA, while for payload un-LZMA is OK. Until now I thought it was a compiler issue with ROMCC and GCC creating slighty different machine code, but maybe I should push microcode update before any cache use. While there are quite a few errata for these CPUs, I did not identify any of those with the symptoms I saw. Thanks, Ky?sti From gerrit at coreboot.org Tue Nov 8 14:47:21 2011 From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se)) Date: Tue, 8 Nov 2011 14:47:21 +0100 Subject: [coreboot] New patch to review for coreboot: 3575fdf Fixed whitespace and indentation References: Message-ID: Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/428 -gerrit commit 3575fdffeab51f4a8140067b82605beaca81e502 Author: Oskar Enoksson Date: Mon Nov 7 18:31:33 2011 +0100 Fixed whitespace and indentation Code style fixes for the hp/dl145_g1 system board code. Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e Signed-off-by: Oskar Enoksson --- src/mainboard/hp/dl145_g1/devicetree.cb | 278 +++++++++++++++--------------- src/mainboard/hp/dl145_g1/get_bus_conf.c | 96 +++++----- src/mainboard/hp/dl145_g1/irq_tables.c | 54 +++--- src/mainboard/hp/dl145_g1/mb_sysconf.h | 8 +- src/mainboard/hp/dl145_g1/mptable.c | 40 ++-- src/mainboard/hp/dl145_g1/romstage.c | 92 +++++----- 6 files changed, 284 insertions(+), 284 deletions(-) diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb index bd67f23..0f4a34f 100644 --- a/src/mainboard/hp/dl145_g1/devicetree.cb +++ b/src/mainboard/hp/dl145_g1/devicetree.cb @@ -1,142 +1,142 @@ chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end - device pci_domain 0 on - subsystemid 0x1022 0x7460 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on # link 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on # PCIX Bridge A - # PCI-X expansion slot cards auto-detected here - end - device pci 0.1 on end # IOAPIC A - device pci 1.0 on # PCIX Bridge B - # On-board BCM5704 dual port ethernet chip auto-detected here - # Optional SCSI board also (?) - end - device pci 1.1 on end # IOAPIC B - device pci 2.0 off end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent of the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end # OHCI-based USB controller 0 - device pci 0.1 on end # OCHI-based USB controller 1 - device pci 0.2 on end # EHCI-based USB2 controller - device pci 1.0 off end # LAN Ethernet controller - #device pci 4.0 on end # VGA PCI-card (auto detected) - end - device pci 1.0 on # LPC Bridge - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - #io 0x60 = 0x3f0 - #irq 0x70 = 6 - #drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - #io 0x60 = 0x378 - #irq 0x70 = 7 - #drq 0x74 = 1 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - #io 0x60 = 0x2f8 - #irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - end - device pnp 2e.7 off # GAM_MIDI_GPIO1 - #io 0x60 = 0x201 - #io 0x62 = 0x330 - #irq 0x70 = 9 - end - device pnp 2e.8 on # GPIO2 (watchdog timer) - end - device pnp 2e.9 on # GPIO3 - end - device pnp 2e.a on # ACPI - end - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end # EIDE controller - device pci 1.2 on - chip drivers/generic/generic - device i2c 8 on end # Some HW-monitor/sensor? - end - end - device pci 1.2 on - chip drivers/i2c/i2cmux # Multplexed DIMM spd eeproms. - device i2c 18 on #0 pca9516 (?) - # Some dimms also listen to address 30-33 - # It's some kind of write-protect function - # The 50-53 addresses are the interesting ones. - chip drivers/generic/generic #dimm H0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm H0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm H0-2 - device i2c 52 on end - end - chip drivers/generic/generic #dimm H0-3 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 (?) - chip drivers/generic/generic #dimm H1-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm H1-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm H1-2 - device i2c 52 on end - end - chip drivers/generic/generic #dimm H1-3 - device i2c 53 on end - end - end - end - end - device pci 1.2 on - chip drivers/generic/generic - device i2c 69 on end # Texas Instruments cdc960 clock synthesizer - end - end # SMBus 2.0 controller - device pci 1.3 on # System management registers (ACPI) - end # System management - #device pci 1.4 off end - device pci 1.5 off end # AC97 Audio - device pci 1.6 off end # AC97 Modem - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end + device lapic_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x7460 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on end # link 0 + device pci 18.0 on end # link 1 + device pci 18.0 on # link 2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on # PCIX Bridge A + # PCI-X expansion slot cards auto-detected here + end + device pci 0.1 on end # IOAPIC A + device pci 1.0 on # PCIX Bridge B + # On-board BCM5704 dual port ethernet chip auto-detected here + # Optional SCSI board also (?) + end + device pci 1.1 on end # IOAPIC B + device pci 2.0 off end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent of the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end # OHCI-based USB controller 0 + device pci 0.1 on end # OCHI-based USB controller 1 + device pci 0.2 on end # EHCI-based USB2 controller + device pci 1.0 off end # LAN Ethernet controller + #device pci 4.0 on end # VGA PCI-card (auto detected) + end + device pci 1.0 on # LPC Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + #io 0x60 = 0x3f0 + #irq 0x70 = 6 + #drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + #io 0x60 = 0x378 + #irq 0x70 = 7 + #drq 0x74 = 1 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + #io 0x60 = 0x2f8 + #irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + end + device pnp 2e.7 off # GAM_MIDI_GPIO1 + #io 0x60 = 0x201 + #io 0x62 = 0x330 + #irq 0x70 = 9 + end + device pnp 2e.8 on # GPIO2 (watchdog timer) + end + device pnp 2e.9 on # GPIO3 + end + device pnp 2e.a on # ACPI + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end # EIDE controller + device pci 1.2 on + chip drivers/generic/generic + device i2c 8 on end # Some HW-monitor/sensor? + end + end + device pci 1.2 on + chip drivers/i2c/i2cmux # Multplexed DIMM spd eeproms. + device i2c 18 on #0 pca9516 (?) + # Some dimms also listen to address 30-33 + # It's some kind of write-protect function + # The 50-53 addresses are the interesting ones. + chip drivers/generic/generic #dimm H0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm H0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm H0-2 + device i2c 52 on end + end + chip drivers/generic/generic #dimm H0-3 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 (?) + chip drivers/generic/generic #dimm H1-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm H1-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm H1-2 + device i2c 52 on end + end + chip drivers/generic/generic #dimm H1-3 + device i2c 53 on end + end + end + end + end + device pci 1.2 on + chip drivers/generic/generic + device i2c 69 on end # Texas Instruments cdc960 clock synthesizer + end + end # SMBus 2.0 controller + device pci 1.3 on # System management registers (ACPI) + end # System management + #device pci 1.4 off end + device pci 1.5 off end # AC97 Audio + device pci 1.6 off end # AC97 Modem + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end end diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index 6ea751d..b7bbaad 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -16,27 +16,27 @@ struct mb_sysconf_t mb_sysconf; static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not +{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 + 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 }; static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, }; @@ -47,23 +47,23 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done==1) return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; sysconf.mb = &mb_sysconf; struct mb_sysconf_t *m = sysconf.mb; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i> 8) & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff; @@ -71,32 +71,32 @@ void get_bus_conf(void) m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; m->bus_8111_0 = m->bus_8131_0; - /* 8111 */ - dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } + /* 8111 */ + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); + if (dev) { + m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0); - } + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0); + } - /* 8131-1 */ - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0)); - if (dev) { - m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0); - } + /* 8131-1 */ + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0)); + if (dev) { + m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0); + } - /* 8131-2 */ - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0)); - if (dev) { - m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0); - } + /* 8131-2 */ + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0)); + if (dev) { + m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0); + } /*I/O APICs: APIC ID Version State Address*/ diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c index 9d70a89..71288dd 100644 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ b/src/mainboard/hp/dl145_g1/irq_tables.c @@ -17,18 +17,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; } unsigned long write_pirq_routing_table(unsigned long addr) @@ -39,17 +39,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t *v; struct mb_sysconf_t *m = sysconf.mb; - uint8_t sum=0; - int i; + uint8_t sum=0; + int i; get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; - /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -75,21 +75,21 @@ unsigned long write_pirq_routing_table(unsigned long addr) write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge -// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; +// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// pirq_info++; slot_num++; - pirq_info++; slot_num++; + pirq_info++; slot_num++; pirq->size = 32 + 16 * slot_num; - for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i]; sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + } printk(BIOS_INFO, "done.\n"); diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h index 0bceab4..2b16791 100644 --- a/src/mainboard/hp/dl145_g1/mb_sysconf.h +++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h @@ -9,11 +9,11 @@ struct mb_sysconf_t { unsigned char bus_8111_0; unsigned char bus_8111_1; - unsigned apicid_8111; - unsigned apicid_8131_1; - unsigned apicid_8131_2; + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2; - unsigned sbdn3; + unsigned sbdn3; }; #endif diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index c15dff6..e33f681 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -9,14 +9,14 @@ static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int bus_isa; - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); - smp_write_processors(mc); + smp_write_processors(mc); get_bus_conf(); @@ -26,23 +26,23 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base); - } - } - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base); - } - } + { + device_t dev; + struct resource *res; + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base); + } + } + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base); + } + } } diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index c0a12d9..6b8972b 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -23,52 +23,52 @@ static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - /* Set the memreset low. */ - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); - /* Ensure the BIOS has control of the memory lines. */ - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); - } else { - /* Ensure the CPU has control of the memory lines. */ - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); - } + if (is_cpu_pre_c0()) { + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + } else { + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); + } } static void memreset(int controllers, const struct mem_controller *ctrl) { - if (is_cpu_pre_c0()) { - udelay(800); - /* Set memreset high. */ - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); - udelay(90); - } + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset high. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); + udelay(90); + } } #define SMBUS_HUB 0x18 static inline void activate_spd_rom(const struct mem_controller *ctrl) { - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); - smbus_write_byte(SMBUS_HUB, 0x03, 0); + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret!=0) && (i-->0)); + smbus_write_byte(SMBUS_HUB, 0x03, 0); } static inline void change_i2c_mux(unsigned device) { - int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); - } while ((ret!=0) && (i-->0)); - ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); + int ret, i; + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); + } while ((ret!=0) && (i-->0)); + ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } static inline int spd_read_byte(unsigned device, unsigned address) @@ -107,16 +107,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; unsigned bsp_apicid = 0; - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_dl145g1_resource_map(); //setup_default_resource_map(); @@ -127,12 +127,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif - ht_setup_chains_x(sysinfo); + ht_setup_chains_x(sysinfo); needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); @@ -156,13 +156,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //dump_spd_registers(&sysinfo->ctrl[1]); //dump_smbus_registers(); - allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl now; - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + //It's the time to set ctrl now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - memreset_setup(); - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + memreset_setup(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); //dump_pci_devices(); From paulepanter at users.sourceforge.net Tue Nov 8 17:17:36 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Tue, 08 Nov 2011 17:17:36 +0100 Subject: [coreboot] New patch to review for coreboot: 3575fdf Fixed whitespace and indentation In-Reply-To: References: Message-ID: <1320769056.3915.20.camel@mattotaupa> Am Dienstag, den 08.11.2011, 14:47 +0100 schrieb Oskar Enoksson: > Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/428 > > -gerrit > > commit 3575fdffeab51f4a8140067b82605beaca81e502 > Author: Oskar Enoksson > Date: Mon Nov 7 18:31:33 2011 +0100 > > Fixed whitespace and indentation > > Code style fixes for the hp/dl145_g1 system board code. > > Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e > Signed-off-by: Oskar Enoksson [?] I guess you could self approve such changes. If you diff the files created before and after this patch and they are the same and maybe even run test the tree with the white space clean up, this should be enough to ensure nothing breaks. Thanks, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From gerrit at coreboot.org Tue Nov 8 19:00:22 2011 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Tue, 8 Nov 2011 19:00:22 +0100 Subject: [coreboot] New patch to review for coreboot: 0b141d5 move function from header file to .c file References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/429 -gerrit commit 0b141d5dc0d97bbbedd514d19255d7eba096c645 Author: Stefan Reinauer Date: Tue Nov 8 09:58:29 2011 -0800 move function from header file to .c file http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h move this function to ctrl.c and add a prototype to the header file instead. Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923 Signed-off-by: Stefan Reinauer --- src/southbridge/via/k8t890/ctrl.c | 13 +++++++++++++ src/southbridge/via/k8t890/k8x8xx.h | 16 ++-------------- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..5fa6686 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -25,6 +25,19 @@ #include #include "k8x8xx.h" +void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs) + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index c61c984..908940a 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -28,6 +28,7 @@ #endif #include "k8t890.h" +#ifndef __PRE_RAM__ struct k8x8xx_vt8237_mirrored_regs { u16 low_top_address; u8 rom_shadow_ctrl_pg_c, @@ -38,20 +39,7 @@ struct k8x8xx_vt8237_mirrored_regs { shadow_mem_ctrl; }; -static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ - msr_t msr; - - regs->rom_shadow_ctrl_pg_c = 0xff; - regs->rom_shadow_ctrl_pg_d = 0xff; - regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; - regs->rom_shadow_ctrl_pg_f_memhole = 0x30; - regs->smm_apic_decoding = 0x19; - msr = rdmsr(TOP_MEM); - regs->shadow_mem_ctrl = msr.lo >> 24; - regs->low_top_address = msr.lo >> 16; -} - -#ifndef __PRE_RAM__ +void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs); void k8x8xx_vt8237r_cfg(struct device *, struct device *); #endif From gerrit at coreboot.org Tue Nov 8 19:01:45 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 8 Nov 2011 19:01:45 +0100 Subject: [coreboot] Patch merged into coreboot/master: 87407f2 Cleanup Persimmon mainboard whitespace. References: Message-ID: the following patch was just integrated into master: commit 87407f2e27b9dd3f2ba72c4e0f538843a436b2bc Author: Marc Jones Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Change-Id: I389bde86c5583a4fb37a699162b65b475ed94ddc Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Nov 8 07:40:11 2011, giving +1 Reviewed-By: Stefan Reinauer at Tue Nov 8 19:01:42 2011, giving +2 See http://review.coreboot.org/427 for details. -gerrit From gerrit at coreboot.org Tue Nov 8 19:12:21 2011 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Tue, 8 Nov 2011 19:12:21 +0100 Subject: [coreboot] Patch set updated for coreboot: 72bdd79 move function from header file to .c file References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/429 -gerrit commit 72bdd793d9be45d7ec995b0c015f4af68511722e Author: Stefan Reinauer Date: Tue Nov 8 09:58:29 2011 -0800 move function from header file to .c file http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h move this function to ctrl.c and add a prototype to the header file instead. Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923 Signed-off-by: Stefan Reinauer --- src/southbridge/via/k8t890/ctrl.c | 14 ++++++++++++++ src/southbridge/via/k8t890/k8x8xx.h | 16 ++-------------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..3180412 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -25,6 +25,20 @@ #include #include "k8x8xx.h" +void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs) +{ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index c61c984..908940a 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -28,6 +28,7 @@ #endif #include "k8t890.h" +#ifndef __PRE_RAM__ struct k8x8xx_vt8237_mirrored_regs { u16 low_top_address; u8 rom_shadow_ctrl_pg_c, @@ -38,20 +39,7 @@ struct k8x8xx_vt8237_mirrored_regs { shadow_mem_ctrl; }; -static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ - msr_t msr; - - regs->rom_shadow_ctrl_pg_c = 0xff; - regs->rom_shadow_ctrl_pg_d = 0xff; - regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; - regs->rom_shadow_ctrl_pg_f_memhole = 0x30; - regs->smm_apic_decoding = 0x19; - msr = rdmsr(TOP_MEM); - regs->shadow_mem_ctrl = msr.lo >> 24; - regs->low_top_address = msr.lo >> 16; -} - -#ifndef __PRE_RAM__ +void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs); void k8x8xx_vt8237r_cfg(struct device *, struct device *); #endif From gerrit at coreboot.org Tue Nov 8 21:19:24 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 8 Nov 2011 21:19:24 +0100 Subject: [coreboot] Patch merged into coreboot/master: e13a5ed selfboot: fix bug in valid_area() References: Message-ID: the following patch was just integrated into master: commit e13a5edca121b2781a3fa05f7b4b23476d60ee65 Author: Stefan Reinauer Date: Mon Nov 7 12:56:12 2011 -0800 selfboot: fix bug in valid_area() valid_area will accept a region as valid for the payload if only a part of coreboot fits in that region. This means if a payload reaches into a neighboring RESERVED region, coreboot would not care and happily overwrite that region, as long as the payload also writes to some RAM. Change-Id: Ie263f83be18009b01a31c71e7285c998747d097f Signed-off-by: Stefan Reinauer Reviewed-By: Patrick Georgi at Tue Nov 8 21:18:54 2011, giving +2 See http://review.coreboot.org/425 for details. -gerrit From gerrit at coreboot.org Tue Nov 8 21:22:00 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 8 Nov 2011 21:22:00 +0100 Subject: [coreboot] Patch merged into coreboot/master: c0ce7d7 selfboot: Don't include unneeded ip_checksum.h References: Message-ID: the following patch was just integrated into master: commit c0ce7d7b25f94be2e1ff3fe26253debead9dcf60 Author: Stefan Reinauer Date: Mon Nov 7 13:16:38 2011 -0800 selfboot: Don't include unneeded ip_checksum.h Change-Id: I09b888e70f7432f7025b0b851acfb0279553400f Signed-off-by: Stefan Reinauer Reviewed-By: Patrick Georgi at Tue Nov 8 21:01:13 2011, giving +2 See http://review.coreboot.org/426 for details. -gerrit From gerrit at coreboot.org Tue Nov 8 21:26:31 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 8 Nov 2011 21:26:31 +0100 Subject: [coreboot] Patch merged into coreboot/master: b4270b5 make w83697hf_set_clksel_48() non-static and add a prototype References: Message-ID: the following patch was just integrated into master: commit b4270b5a2814290f48386e6e1639fac5f84a469b Author: Florian Zumbiehl Date: Tue Nov 1 20:19:02 2011 +0100 make w83697hf_set_clksel_48() non-static and add a prototype make w83697hf_set_clksel_48() non-static and add a prototype so as to get rid of warnings about it being unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Sat Nov 5 00:20:50 2011, giving +1 Reviewed-By: Stefan Reinauer at Tue Nov 8 21:26:29 2011, giving +2 See http://review.coreboot.org/380 for details. -gerrit From gerrit at coreboot.org Tue Nov 8 21:16:37 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 8 Nov 2011 21:16:37 +0100 Subject: [coreboot] Patch merged into coreboot/master: 72bdd79 move function from header file to .c file References: Message-ID: the following patch was just integrated into master: commit 72bdd793d9be45d7ec995b0c015f4af68511722e Author: Stefan Reinauer Date: Tue Nov 8 09:58:29 2011 -0800 move function from header file to .c file http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h move this function to ctrl.c and add a prototype to the header file instead. Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923 Signed-off-by: Stefan Reinauer Reviewed-By: Patrick Georgi at Tue Nov 8 21:15:01 2011, giving +2 See http://review.coreboot.org/429 for details. -gerrit From gerrit at coreboot.org Tue Nov 8 22:38:43 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 8 Nov 2011 22:38:43 +0100 Subject: [coreboot] Patch set updated for coreboot: d3ad5d9 buildgcc: Add option to use ccache References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/400 -gerrit commit d3ad5d902bfb17b085a1d229e8fc0e87c1ccba0e Author: Patrick Georgi Date: Fri Nov 4 21:37:14 2011 +0100 buildgcc: Add option to use ccache This mimicks abuild: -y enables ccache. Change-Id: I3ac1f809729af816efbc64f5789ab430e1a6a6b2 Signed-off-by: Patrick Georgi --- util/crossgcc/buildgcc | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f86332d..d13e65d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -126,6 +126,7 @@ myhelp() printf " [-h|--help] print this help and exit\n" printf " [-c|--clean] remove temporary files before build\n" printf " [-t|--savetemps] don't remove temporary files after build\n" + printf " [-y|--ccache] Use ccache when building cross compiler\n" printf " [-j|--jobs ] run jobs in parallel in make\n" printf " [-p|--platform ] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" @@ -167,11 +168,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="`getopt -V | sed -e '1!d' -e 's,^\(......\).*,\1,'`" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps,skip-gdb Vhcd:p:j:D:tG -- "$@"` + args=`getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps,skip-gdb,ccache Vhcd:p:j:D:tGy -- "$@"` eval set "$args" else # Detected non-GNU getopt - args=`getopt Vhcd:p:j:D:tG $*` + args=`getopt Vhcd:p:j:D:tGy $*` set -- $args fi @@ -192,6 +193,7 @@ while true ; do -j|--jobs) shift; JOBS="-j $1"; shift;; -G|--gdb) shift; SKIPGDB=0;; -S|--scripting) shift; SKIPPYTHON=0;; + -y|--ccache) shift; USECCACHE=1;; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;; @@ -325,6 +327,10 @@ if [ `uname` = "Darwin" ]; then fi fi +if [ "$USECCACHE" = 1 ]; then + CC="ccache $CC" +fi + mkdir -p build-gmp build-mpfr build-mpc build-libelf build-binutils \ build-gcc build-python build-expat if [ $SKIPGDB -eq 0 ]; then From gerrit at coreboot.org Wed Nov 9 00:25:46 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 9 Nov 2011 00:25:46 +0100 Subject: [coreboot] Patch merged into coreboot/master: d3ad5d9 buildgcc: Add option to use ccache References: Message-ID: the following patch was just integrated into master: commit d3ad5d902bfb17b085a1d229e8fc0e87c1ccba0e Author: Patrick Georgi Date: Fri Nov 4 21:37:14 2011 +0100 buildgcc: Add option to use ccache This mimicks abuild: -y enables ccache. Change-Id: I3ac1f809729af816efbc64f5789ab430e1a6a6b2 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Tue Nov 8 22:51:16 2011, giving +1 Reviewed-By: Stefan Reinauer at Wed Nov 9 00:25:44 2011, giving +2 See http://review.coreboot.org/400 for details. -gerrit From gerrit at coreboot.org Wed Nov 9 00:26:25 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 9 Nov 2011 00:26:25 +0100 Subject: [coreboot] Patch merged into coreboot/master: 3575fdf Fixed whitespace and indentation References: Message-ID: the following patch was just integrated into master: commit 3575fdffeab51f4a8140067b82605beaca81e502 Author: Oskar Enoksson Date: Mon Nov 7 18:31:33 2011 +0100 Fixed whitespace and indentation Code style fixes for the hp/dl145_g1 system board code. Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e Signed-off-by: Oskar Enoksson Build-Tested: build bot (Jenkins) at Tue Nov 8 21:28:37 2011, giving +1 Reviewed-By: Stefan Reinauer at Wed Nov 9 00:26:22 2011, giving +2 See http://review.coreboot.org/428 for details. -gerrit From gerrit at coreboot.org Thu Nov 10 15:52:15 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Thu, 10 Nov 2011 15:52:15 +0100 Subject: [coreboot] New patch to review for coreboot: 20f62da libpayload: Fix handling of CAPS LOCK key on PS/2 keyboards References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/430 -gerrit commit 20f62dac1e7c8f6eb6116a88fc729794d05742d6 Author: Patrick Georgi Date: Thu Nov 10 15:48:37 2011 +0100 libpayload: Fix handling of CAPS LOCK key on PS/2 keyboards The PS/2 keyboard driver set and reset the caps LED to show the keyboard status. Unfortunately, that configuration happens over the same path used to transmit keypresses. In face of certain error conditions, the keyboard stopped working. This change makes keyboard handling more robust. Change-Id: I0489a9983ea7dab00357220e09398dd1a8538839 Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/keyboard.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/keyboard.c b/payloads/libpayload/drivers/keyboard.c index 0663f47..717ee55 100644 --- a/payloads/libpayload/drivers/keyboard.c +++ b/payloads/libpayload/drivers/keyboard.c @@ -166,11 +166,13 @@ static struct layout_maps keyboard_layouts[] = { static void keyboard_cmd(unsigned char cmd, unsigned char val) { + while (inb(0x64) & 2); outb(cmd, 0x60); - /* wait until keyboard controller accepts cmds: */ + mdelay(20); + while (inb(0x64) & 2); outb(val, 0x60); - while (inb(0x64) & 2); + mdelay(20); } int keyboard_havechar(void) From gerrit at coreboot.org Thu Nov 10 17:51:54 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 10 Nov 2011 17:51:54 +0100 Subject: [coreboot] Patch merged into coreboot/master: 20f62da libpayload: Fix handling of CAPS LOCK key on PS/2 keyboards References: Message-ID: the following patch was just integrated into master: commit 20f62dac1e7c8f6eb6116a88fc729794d05742d6 Author: Patrick Georgi Date: Thu Nov 10 15:48:37 2011 +0100 libpayload: Fix handling of CAPS LOCK key on PS/2 keyboards The PS/2 keyboard driver set and reset the caps LED to show the keyboard status. Unfortunately, that configuration happens over the same path used to transmit keypresses. In face of certain error conditions, the keyboard stopped working. This change makes keyboard handling more robust. Change-Id: I0489a9983ea7dab00357220e09398dd1a8538839 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Thu Nov 10 16:09:31 2011, giving +1 Reviewed-By: Stefan Reinauer at Thu Nov 10 17:51:53 2011, giving +2 See http://review.coreboot.org/430 for details. -gerrit From christian.suehs at online.de Thu Nov 10 19:05:31 2011 From: christian.suehs at online.de (Christian) Date: Thu, 10 Nov 2011 19:05:31 +0100 Subject: [coreboot] Read resources faild on MS-6159 / i440LX northbridge Message-ID: <1320948331.7307.14.camel@dance-or-die3.athome.de> Hello I'm back uuhhhhh :D I try currently to run a MS-6159 Mobo with coreboot. After a few changes in i440lx section, because gcc won't compile and a new folder for Winbond W83977EF (only a copy from W83977TF without CIR and GPIOIII) i got a rom file and gave it a chance. Here are the last debug lines (full debug attached) Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 at this point nothing happens anymore. I need an Idea to start searching ... Thanks Chris CPU: Intel Celeron 400MHz Socket: PGA370 Northbridge: i440lx Southbridge: i8237eb SuperIO: w83977ef -------------- next part -------------- coreboot-4.0-1853-gf285e04-dirty Thu Nov 10 17:41:13 CET 2011 starting... Loading image. Searching for fallback/coreboot_ram Check pci1002,4742.rom Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (278528 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-1853-gf285e04-dirty Thu Nov 10 17:41:13 CET 2011 booting... clocks_per_usec: 402 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:07.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 PCI: 00:14.0: enabled 0 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:07.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 PCI: 00:14.0: enabled 0 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/7180] ops PCI: 00:00.0 [8086/7180] enabled PCI: 00:01.0 [8086/7181] enabled PCI: 00:07.0 [8086/7110] bus ops PCI: 00:07.0 [8086/7110] enabled PCI: 00:07.1 [8086/7111] ops PCI: 00:07.1 [8086/7111] enabled PCI: 00:07.2 [8086/7112] ops PCI: 00:07.2 [8086/7112] enabled PCI: 00:07.3 [8086/7113] bus ops pwrmgt_enable: gpo default missing in devicetree.cb! PCI: 00:07.3 [8086/7113] enabled PCI: 00:14.0 [1274/1371] disabled PCI: 00:14.1, bad id 0x0 PCI: 00:14.2, bad id 0x0 PCI: 00:14.3, bad id 0x0 PCI: 00:14.4, bad id 0x0 PCI: 00:14.5, bad id 0x0 PCI: 00:14.6, bad id 0x0 PCI: 00:14.7, bad id 0x0 do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1002/4742] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:07.0 PNP: 03f0.0 enabled PNP: 03f0.1 enabled PNP: 03f0.2 enabled PNP: 03f0.3 enabled PNP: 03f0.5 enabled PNP: 03f0.7 enabled PNP: 03f0.8 enabled PNP: 03f0.a enabled scan_static_bus for PCI: 00:07.0 done scan_static_bus for PCI: 00:07.3 scan_static_bus for PCI: 00:07.3 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 -------------- next part -------------- chip northbridge/intel/i440lx # Northbridge device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_PGA370 # CPU device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge chip superio/winbond/w83977ef # Super I/O device pnp 3f0.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 3f0.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end device pnp 3f0.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 3f0.3 on # COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 3f0.5 on # PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 # PS/2 keyboard interrupt irq 0x72 = 12 # PS/2 mouse interrupt end device pnp 3f0.7 on # GPIO 1 end device pnp 3f0.8 on # GPIO 2 end device pnp 3f0.a on # ACPI end end end device pci 7.1 on end # IDE device pci 7.2 on end # USB device pci 7.3 on end # ACPI device pci 14.0 off end # onBoard Sound register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" # Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "1" register "ide0_drive1_udma33_enable" = "1" register "ide1_drive0_udma33_enable" = "1" register "ide1_drive1_udma33_enable" = "1" end end end From gerrit at coreboot.org Thu Nov 10 23:54:42 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 10 Nov 2011 23:54:42 +0100 Subject: [coreboot] Patch merged into coreboot/master: c5293fc support for different location of HT registers in old version of K8T800 References: Message-ID: the following patch was just integrated into master: commit c5293fc080bcb311e1277b2034051f4d22382745 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:14 2011 +0100 support for different location of HT registers in old version of K8T800 Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494 Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Fri Nov 4 23:38:26 2011, giving +1 Reviewed-By: Stefan Reinauer at Thu Nov 10 23:54:35 2011, giving +2 See http://review.coreboot.org/373 for details. -gerrit From gerrit at coreboot.org Thu Nov 10 23:55:25 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 10 Nov 2011 23:55:25 +0100 Subject: [coreboot] Patch merged into coreboot/master: 8509f26 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD References: Message-ID: the following patch was just integrated into master: commit 8509f2694fd0b03a15eadcbfe10e3c07e0d63cb3 Author: Florian Zumbiehl Date: Tue Nov 1 20:17:41 2011 +0100 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Fri Nov 4 23:50:01 2011, giving +1 Reviewed-By: Stefan Reinauer at Thu Nov 10 23:55:11 2011, giving +2 See http://review.coreboot.org/374 for details. -gerrit From gerrit at coreboot.org Fri Nov 11 10:22:45 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 11 Nov 2011 10:22:45 +0100 Subject: [coreboot] New patch to review for filo: 4ad8a22 Fix FILO colors References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/431 -gerrit commit 4ad8a2254d6b014079cc7129b196d9a574c5d0e7 Author: Patrick Georgi Date: Fri Nov 11 10:20:42 2011 +0100 Fix FILO colors FILO relied on tinycurses auto-initialization of colors, while PDcurses is more strict and requires start_color() before use. Change-Id: Icf185a2c593a96a6a132c8a32ead9da98644e982 Signed-off-by: Patrick Georgi --- main/grub/grub.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/main/grub/grub.c b/main/grub/grub.c index 0e8970c..b4bee04 100644 --- a/main/grub/grub.c +++ b/main/grub/grub.c @@ -1029,6 +1029,7 @@ void grub_main(void) /* Initialize TinyCurses */ initscr(); + start_color(); cbreak(); noecho(); nonl(); From gerrit at coreboot.org Fri Nov 11 11:06:56 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 11 Nov 2011 11:06:56 +0100 Subject: [coreboot] New patch to review for coreboot: 561223f libpayload: Enable colors in PDcurses References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/432 -gerrit commit 561223fbd9401700f1e0a1c85358e74da993a6bf Author: Patrick Georgi Date: Fri Nov 11 11:05:42 2011 +0100 libpayload: Enable colors in PDcurses PDcurses wants set_blink to determine color count. Not exactly obvious. Change-Id: I8b2a32f0095d5900fa7e01f04f3f1d565dc2bedf Signed-off-by: Patrick Georgi --- .../libpayload/curses/pdcurses-backend/pdcsetsc.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c b/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c index 49d66ab..f0e83cf 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c @@ -28,5 +28,8 @@ int PDC_curs_set(int visibility) int PDC_set_blink(bool blinkon) { + if (pdc_color_started) + COLORS = 16; + return ERR; } From gerrit at coreboot.org Fri Nov 11 18:24:50 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 11 Nov 2011 18:24:50 +0100 Subject: [coreboot] Patch merged into coreboot/master: 561223f libpayload: Enable colors in PDcurses References: Message-ID: the following patch was just integrated into master: commit 561223fbd9401700f1e0a1c85358e74da993a6bf Author: Patrick Georgi Date: Fri Nov 11 11:05:42 2011 +0100 libpayload: Enable colors in PDcurses PDcurses wants set_blink to determine color count. Not exactly obvious. Change-Id: I8b2a32f0095d5900fa7e01f04f3f1d565dc2bedf Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Nov 11 11:17:04 2011, giving +1 Reviewed-By: Stefan Reinauer at Fri Nov 11 18:24:47 2011, giving +2 See http://review.coreboot.org/432 for details. -gerrit From gerrit at coreboot.org Fri Nov 11 18:29:12 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 11 Nov 2011 18:29:12 +0100 Subject: [coreboot] Patch merged into filo/master: 4ad8a22 Fix FILO colors References: Message-ID: the following patch was just integrated into master: commit 4ad8a2254d6b014079cc7129b196d9a574c5d0e7 Author: Patrick Georgi Date: Fri Nov 11 10:20:42 2011 +0100 Fix FILO colors FILO relied on tinycurses auto-initialization of colors, while PDcurses is more strict and requires start_color() before use. Change-Id: Icf185a2c593a96a6a132c8a32ead9da98644e982 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Nov 11 10:24:09 2011, giving +1 Reviewed-By: Stefan Reinauer at Fri Nov 11 18:26:22 2011, giving +2 See http://review.coreboot.org/431 for details. -gerrit From r.marek at assembler.cz Fri Nov 11 18:33:35 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 11 Nov 2011 18:33:35 +0100 Subject: [coreboot] AMD UMA questions Message-ID: <4EBD5C6F.4030002@assembler.cz> Hi guys, I'm ccining coreboot ml. I still struggle with the flicker during LDTSTOP transitions on 785G (PCI ID 0x9710 of uma and NB same as RS880). I suspect that I need to setup something in graphics engine. I checked all possible settings in NB/SB so I guess it must be something which is set in gfx.c <------>/* Force allow LDT_STOP Cool'n'Quiet workaround. */ <------>*(GpuF0MMReg + 0x655c/4) |= 1<<4; I think those bits are read only on my system. Maybe it is something else. Any idea what to do with that? It seems it needs access to some more advanced documentation. Thanks Rudolf From c-d.hailfinger.devel.2006 at gmx.net Fri Nov 11 18:48:23 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 11 Nov 2011 18:48:23 +0100 Subject: [coreboot] FOSDEM 2012 Message-ID: <4EBD5FE7.3050609@gmx.net> Hey, it seems we forgot to apply for a devroom (well, at least I didn't see anything on the mailing list). Should we submit talks to the individual devrooms? Should we ask for a coreboot/flashrom booth/table? Regards, Carl-Daniel From GNUtoo at no-log.org Fri Nov 11 19:53:43 2011 From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli) Date: Fri, 11 Nov 2011 19:53:43 +0100 Subject: [coreboot] VGA issues on ASUS M4A785T-M Message-ID: <201111111953.43899.GNUtoo@no-log.org> hi, I'm "porting" coreboot to the Asus M4A785T-M ( http://www.coreboot.org/ASUS_M4A785T-M ) This board is very similar t othe M4A785-M (without the T). The details on the changes I did are on that page and can be summed up to that: - select DIMM_DDR2 + select DIMM_DDR3 + select DIMM_REGISTERED In the Kconfig of the M4A785-M mainboard. I also had to remove the microcode loading to make it pass the CPU init. The basics seem to work but I've some issues at the start of Xorg, So I investigated a bit and the display freezes when the radeon linux kernel driver is loaded(before that the display worked fine in VGA Mode, that is to say VGA is initialized etc... I can see grub2 and the "press F12" of SeaBios). I've investigated a bit and here are some kernel messages with the BIOS: [drm] fb mappable at 0xD0040000 [drm] vram apper at 0xD0000000 With Coreboot: [drm] fb mappable at 0xC0040000 [drm] vram apper at 0xC0000000 lspci with BIOS: # lspci -s 01:05.0 -vvv 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200] (prog-if 00 [VGA controller]) Subsystem: ASUSTeK Computer Inc. M4A785TD Motherboard Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR+ [disabled] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: radeon Kernel modules: radeon And lspci With the coreboot: # lspci -s 01:05.0 -vvv 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200] (prog-if 00 [VGA controller]) Subsystem: ATI Technologies Inc Device 0000 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- [disabled] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: radeon Kernel modules: radeon I've already tried to change some values in coreboot without success(sorry for the mangling of the code but I tought sending a patch for that was a bit overkill): in src/southbridge/amd/rs780/gfx.c (change 0xC0000000 in 0xD0000000) : -nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000); +nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xD0000000) & (~0xffff)) | 0xc000); in src/southbridge/amd/rs780/rs780.h( change 0xC0000000 in 0xD0000000 ): -#define TEMP_MMIO_BASE_ADDRESS 0xC0000000 +#define TEMP_MMIO_BASE_ADDRESS 0xD0000000 What should I do to change theses PCI address? And is it the cause of my problems? Denis. From kyosti.malkki at gmail.com Fri Nov 11 20:39:27 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Fri, 11 Nov 2011 21:39:27 +0200 Subject: [coreboot] VGA issues on ASUS M4A785T-M In-Reply-To: <201111111953.43899.GNUtoo@no-log.org> References: <201111111953.43899.GNUtoo@no-log.org> Message-ID: <1321040367.9998.216.camel@obelix> On Fri, 2011-11-11 at 19:53 +0100, Denis 'GNUtoo' Carikli wrote: > lspci with BIOS: > # lspci -s 01:05.0 -vvv > 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200] > (prog-if 00 [VGA controller]) > Subsystem: ASUSTeK Computer Inc. M4A785TD Motherboard > And lspci With the coreboot: > > # lspci -s 01:05.0 -vvv > 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200] > (prog-if 00 [VGA controller]) > Subsystem: ATI Technologies Inc Device 0000 > > What should I do to change theses PCI address? > And is it the cause of my problems? It is not abnormal that coreboot and original bios create different mappings for PCI addresses. I would leave those PCI addresses alone. Have you transferred the graphic controllers VGA bios from the original bios? At least your subsystem vendor/device ID pair does not match. These steps are required to tell software what type of hardware is designed around the controller chip. Ky?sti From GNUtoo at no-log.org Fri Nov 11 22:29:30 2011 From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli) Date: Fri, 11 Nov 2011 22:29:30 +0100 Subject: [coreboot] VGA issues on ASUS M4A785T-M In-Reply-To: <1321040367.9998.216.camel@obelix> References: <201111111953.43899.GNUtoo@no-log.org> <1321040367.9998.216.camel@obelix> Message-ID: <201111112229.30590.GNUtoo@no-log.org> >Have you transferred the graphic controllers VGA bios from the original >bios? yes I've added the VGA bios rom in my Image, it was extracted with the following command: cat /proc/iomem | grep 'Video ROM' | (read m; m=${m/ :*}; s=${m/-*}; e=${m/*-}; \ dd if=/dev/mem of=vgabios.bin bs=1c skip=$[0x$s] count=$[$[0x$e]-$[0x$s]+1]) (I followed the wiki at http://www.coreboot.org/VGA_support) If I put wrong PCI IDs it won't initialize the display at all during boot... >At least your subsystem vendor/device ID pair does not match. yes, how do I fix that? PS: some more verbose lspci infos: Coreboot: # lspci -s 01:05.0 -knnvvv 01:05.0 VGA compatible controller [0300]: ATI Technologies Inc RS880 [Radeon HD 4200] [1002:9710] (prog-if 00 [VGA controller]) Subsystem: ATI Technologies Inc Device [1002:0000] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- [disabled] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: radeon Kernel modules: radeon Bios: # lspci -s 01:05.0 -knnvvv 01:05.0 VGA compatible controller [0300]: ATI Technologies Inc RS880 [Radeon HD 4200] [1002:9710] (prog-if 00 [VGA controller]) Subsystem: ASUSTeK Computer Inc. M4A785TD Motherboard [1043:83a2] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR+ [disabled] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: radeon Kernel modules: radeon Thanks a lot for the Answer. Denis. From darmawan.salihun at gmail.com Sat Nov 12 09:41:15 2011 From: darmawan.salihun at gmail.com (Darmawan Salihun) Date: Sat, 12 Nov 2011 15:41:15 +0700 Subject: [coreboot] PCI Option ROM debugging with Coreboot+SeaBIOS (detailed steps) Message-ID: I made a blogpost detailing the steps to debug PCI Option ROM with Coreboot+SeaBIOS and a GDB-server-compatible debugger: http://bioshacking.blogspot.com/search/label/PCI%20Option%20ROM Hopefully would help those in need because it takes quite a while to get it right. Thanks to Kevin O'Connor for the helps :-) Regards, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- From svn at coreboot.org Mon Nov 14 16:00:01 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 14 Nov 2011 16:00:01 +0100 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From GNUtoo at no-log.org Mon Nov 14 18:23:20 2011 From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli) Date: Mon, 14 Nov 2011 18:23:20 +0100 Subject: [coreboot] VGA issues on ASUS M4A785T-M In-Reply-To: <4EC0F94E.4080707@tadpole.com> References: <201111111953.43899.GNUtoo@no-log.org> <201111112229.30590.GNUtoo@no-log.org> <4EC0F94E.4080707@tadpole.com> Message-ID: <201111141823.21331.GNUtoo@no-log.org> >So when you >extract an image from a live system it will probably be missing the >initialisation code and have a load of variables and flags that do not >accurately describe the state of the uninitialised card. I did that because It didn't work with the original extracted VGA bios rom: it failed the exact same way. How did I extract the original VGA bios rom the new way: I downloaded the bios from the manufacturer website and got that output: Using file "../M4A785T-M-ASUS-2302.ROM" (1024kB) AMI95 Version : 0800 () 0xA0000 (393216 bytes) -> amiboot.rom 0xA0000 ( 43896 bytes) -> amibody_40.rom "AMD CIM-X NB binary" 0xB0000 ( 13816 bytes) -> amibody_60.rom "AMD CIM-X SB binary" 0xB3620 ( 53344 bytes) -> amibody_e1.rom 0xC06A0 ( 48444 bytes) -> amibody_e1.rom 0xAABA0 ( 16392 bytes) -> amibody_11.rom "P6 Microcode" 0xAEBBC ( 2084 bytes) -> amibody_08.rom "Interface" 0xAF400 ( 76 bytes) -> amibody_30.rom "Font Database" 0xAF460 ( 16 bytes) -> amibody_fc.rom "Asrock LOGO JPG" 0xAF484 ( 8 bytes) -> amibody_0c.rom "ROM-ID" 0x2401C (214806 bytes) -> amibody_1b.rom (458702 bytes) "SLAB" 0x00024 ( 69587 bytes) -> amibody_f2.rom ( 70986 bytes) 0x1100C ( 39320 bytes) -> amipci_1002_4392.rom ( 62464 bytes) "PCI AddOn ROM" 0x58748 ( 38420 bytes) -> amipci_1002_FFF1.rom ( 60928 bytes) "PCI AddOn ROM" 0x61D70 ( 38414 bytes) -> amipci_1002_FFF2.rom ( 60416 bytes) "PCI AddOn ROM" 0x6B394 ( 34939 bytes) -> amibody_f5.rom ( 64200 bytes) 0x73C24 ( 31244 bytes) -> amibody_f0.rom ( 50176 bytes) "Asrock Backup Util" 0x7B644 ( 28305 bytes) -> amipci_10EC_8168.rom ( 49152 bytes) "PCI AddOn ROM" 0x824EC ( 26793 bytes) -> amibody_10.rom ( 58599 bytes) "ACPI AML" 0x88DAC ( 22150 bytes) -> amibody_04.rom ( 35891 bytes) "Setup Client" 0x1A9B8 ( 21750 bytes) -> amilang_US.rom ( 48087 bytes) "Multilanguage" 0xCC3F8 ( 10235 bytes) -> amibody_0e.rom (308216 bytes) "OEM Logo" 0x8E448 ( 6141 bytes) -> amibody_18.rom ( 16965 bytes) "ADM (Display MGR)" 0xCEC08 ( 5025 bytes) -> amibody_1f.rom ( 26676 bytes) 0x8FC5C ( 3640 bytes) -> amibody_ad.rom ( 8211 bytes) 0x90AA8 ( 2893 bytes) -> amibody_ae.rom ( 8208 bytes) 0xAF4A8 ( 1436 bytes) -> amibody_19.rom ( 4868 bytes) "ADM Font" 0xAFA58 ( 1330 bytes) -> amibody_1a.rom ( 9890 bytes) "Small Logo" 0x9160C ( 1002 bytes) -> amibody_06.rom ( 2560 bytes) "DMI Data" 0x1FEBC ( 136 bytes) -> amibody_80.rom the the 2 interesting roms are theses ones: amipci_1002_FFF1.rom and amipci_1002_FFF2.rom The problem is that both seem valid: $ romheaders amipci_1002_FFF1.rom Image 1: PCI Expansion ROM Header: Signature: 0x55aa (Ok) CPU unique data: 0x77 0xe9 0x11 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Pointer to PCI Data Structure: 0x01c4 PCI Data Structure: Signature: 0x50434952 'PCIR' (Ok) Vendor ID: 0x1002 Device ID: 0x9710 Vital Product Data: 0x0000 PCI Data Structure Length: 0x0018 (24 bytes) PCI Data Structure Revision: 0x00 Class Code: 0x030000 (VGA Display controller) Image Length: 0x0077 blocks (60928 bytes) Revision Level of Code/Data: 0x0a5e Code Type: 0x00 (Intel x86) Last-Image Flag: 0x80 (last image in rom) Reserved: 0x0000 Platform specific data for x86 compliant option rom: Initialization Size: 0x77 (60928 bytes) Entry point for INIT function: 0x217 $ romheaders amipci_1002_FFF2.rom Image 1: PCI Expansion ROM Header: Signature: 0x55aa (Ok) CPU unique data: 0x76 0xe9 0xfd 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Pointer to PCI Data Structure: 0x01b0 PCI Data Structure: Signature: 0x50434952 'PCIR' (Ok) Vendor ID: 0x1002 Device ID: 0x9710 Vital Product Data: 0x0000 PCI Data Structure Length: 0x0018 (24 bytes) PCI Data Structure Revision: 0x00 Class Code: 0x030000 (VGA Display controller) Image Length: 0x0076 blocks (60416 bytes) Revision Level of Code/Data: 0x0a5e Code Type: 0x00 (Intel x86) Last-Image Flag: 0x80 (last image in rom) Reserved: 0x0000 Platform specific data for x86 compliant option rom: Initialization Size: 0x76 (60416 bytes) Entry point for INIT function: 0x203 What should I try next? Denis. From kyosti.malkki at gmail.com Mon Nov 14 19:10:04 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Mon, 14 Nov 2011 20:10:04 +0200 Subject: [coreboot] VGA issues on ASUS M4A785T-M In-Reply-To: <201111141823.21331.GNUtoo@no-log.org> References: <201111111953.43899.GNUtoo@no-log.org> <201111112229.30590.GNUtoo@no-log.org> <4EC0F94E.4080707@tadpole.com> <201111141823.21331.GNUtoo@no-log.org> Message-ID: <1321294204.2048.19.camel@obelix> On Mon, 2011-11-14 at 18:23 +0100, Denis 'GNUtoo' Carikli wrote: > What should I try next? > > Denis. You can try to grep both all the ROMs for any instance of the PCI subsystem device/vendor IDs that were not set with coreboot. Remember endianess when searching, disassemble code around them and try to replicate with coreboot. Try if SerialICE works with your board, it can give you all the PCI I/O traffic your oem bios generates to the graphics chip. Ky?sti From jesus.guerrero.botella at gmail.com Mon Nov 14 23:51:00 2011 From: jesus.guerrero.botella at gmail.com (=?UTF-8?Q?Jes=C3=BAs_J=2E_Guerrero_Botella?=) Date: Mon, 14 Nov 2011 23:51:00 +0100 Subject: [coreboot] Asus M4A785TD-V Message-ID: Hello, everyone. My board is an ASUS M4A785TD-V EVO, and I wanted to know if it will work with coreboot. Attending to the FAQ here: http://www.coreboot.org/FAQ#Will_coreboot_work_on_my_machine.3F And before doing something silly, I am trying to find whether coreboot will work on my motherboard or not. The M4A785-M, which seems close enough, is listed in the coreboot site as "WIP" (work in progress). But I don't know what that really means, and it's not the same exact model anyway. Below I provide all the data that the FAQ says I should be providing. If you need something more just ask. Thank you beforehand :) # lspci -tvnn -[0000:00]-+-00.0 Advanced Micro Devices [AMD] RS880 Host Bridge [1022:9601] +-01.0-[01]--+-05.0 ATI Technologies Inc RS880 [Radeon HD 4200] [1002:9710] | \-05.1 ATI Technologies Inc RS880 Audio Device [Radeon HD 4200] [1002:970f] +-11.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] +-12.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-12.1 ATI Technologies Inc SB7x0 USB OHCI1 Controller [1002:4398] +-12.2 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-13.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-13.1 ATI Technologies Inc SB7x0 USB OHCI1 Controller [1002:4398] +-13.2 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] +-14.1 ATI Technologies Inc SB7x0/SB8x0/SB9x0 IDE Controller [1002:439c] +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] +-14.3 ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] +-14.4-[02]--+-05.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] | +-05.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] | +-05.2 VIA Technologies, Inc. USB 2.0 [1106:3104] | \-08.0 VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller [1106:3044] +-14.5 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2 Controller [1002:4399] +-18.0 Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] +-18.1 Advanced Micro Devices [AMD] Family 10h Processor Address Map [1022:1201] +-18.2 Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller [1022:1202] +-18.3 Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control [1022:1203] \-18.4 Advanced Micro Devices [AMD] Family 10h Processor Link Control [1022:1204] # superiotool -dV Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8712F (id=0x8712, rev=0x8) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 12 08 00 00 00 def 87 12 08 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 03 f0 06 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 00 02 f8 03 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 00 00 07 04 00 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 02 30 00 00 00 00 00 00 00 df def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 04 def 01 00 60 00 64 01 02 08 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val c0 e3 01 00 00 00 1f 00 00 03 00 00 00 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 e3 01 00 00 c0 e1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1a 00 00 00 00 00 00 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 # flashrom -V flashrom v0.9.4-r1395 on Linux 3.1.1 (x86_64), built with libpci 3.1.7, GCC 4.5.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1500M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 996 us, 10000 myus = 9975 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M4A785TD-V EVO" DMI string baseboard-version: "Rev X.0x" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. Enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 NormSpeed is 33 MHz GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK SB700 IMC is not active. ROM strap override is not active OK. This chipset supports the following protocols: LPC, FWH, SPI. Super I/O ID 0x8712 is not on the list of flash capable controllers. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x40, id2 0x40, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x40, id2 0x40, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x24, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x40, id2 0x40, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x40, id2 0x40, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x40, id2 0x40, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x40, id2 0x40, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x40, id2 0x40, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified. -- Jes?s Guerrero Botella From wangqingpei at gmail.com Tue Nov 15 04:12:43 2011 From: wangqingpei at gmail.com (QingPei Wang) Date: Tue, 15 Nov 2011 11:12:43 +0800 Subject: [coreboot] Asus M4A785TD-V In-Reply-To: References: Message-ID: hi, Since AMD785/710 are supported by coreboot for a long time. I guess your board can run coreboot well. And more, M4A785TD-M and M4A785TD-V are almost the same. Just try to use the bios of M4A785TD-M. Best wishes QingPei Wang Phone: 86+018930528086 2011/11/15 Jes?s J. Guerrero Botella > Hello, everyone. > > My board is an ASUS M4A785TD-V EVO, and I wanted to know if it will > work with coreboot. > > Attending to the FAQ here: > http://www.coreboot.org/FAQ#Will_coreboot_work_on_my_machine.3F > > And before doing something silly, I am trying to find whether coreboot > will work on my motherboard or not. The M4A785-M, which seems close > enough, is listed in the coreboot site as "WIP" (work in progress). > But I don't know what that really means, and it's not the same exact > model anyway. Below I provide all the data that the FAQ says I should > be providing. If you need something more just ask. Thank you > beforehand :) > > > # lspci -tvnn > -[0000:00]-+-00.0 Advanced Micro Devices [AMD] RS880 Host Bridge > [1022:9601] > +-01.0-[01]--+-05.0 ATI Technologies Inc RS880 [Radeon HD > 4200] [1002:9710] > | \-05.1 ATI Technologies Inc RS880 Audio > Device [Radeon HD 4200] [1002:970f] > +-11.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA > Controller [AHCI mode] [1002:4391] > +-12.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 > Controller [1002:4397] > +-12.1 ATI Technologies Inc SB7x0 USB OHCI1 Controller > [1002:4398] > +-12.2 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI > Controller [1002:4396] > +-13.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 > Controller [1002:4397] > +-13.1 ATI Technologies Inc SB7x0 USB OHCI1 Controller > [1002:4398] > +-13.2 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI > Controller [1002:4396] > +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] > +-14.1 ATI Technologies Inc SB7x0/SB8x0/SB9x0 IDE > Controller [1002:439c] > +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] > +-14.3 ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host > controller [1002:439d] > +-14.4-[02]--+-05.0 VIA Technologies, Inc. VT82xxxxx UHCI > USB 1.1 Controller [1106:3038] > | +-05.1 VIA Technologies, Inc. VT82xxxxx UHCI > USB 1.1 Controller [1106:3038] > | +-05.2 VIA Technologies, Inc. USB 2.0 [1106:3104] > | \-08.0 VIA Technologies, Inc. VT6306/7/8 > [Fire II(M)] IEEE 1394 OHCI Controller [1106:3044] > +-14.5 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2 > Controller [1002:4399] > +-18.0 Advanced Micro Devices [AMD] Family 10h Processor > HyperTransport Configuration [1022:1200] > +-18.1 Advanced Micro Devices [AMD] Family 10h Processor > Address Map [1022:1201] > +-18.2 Advanced Micro Devices [AMD] Family 10h Processor > DRAM Controller [1022:1202] > +-18.3 Advanced Micro Devices [AMD] Family 10h Processor > Miscellaneous Control [1022:1203] > \-18.4 Advanced Micro Devices [AMD] Family 10h Processor > Link Control [1022:1204] > > # superiotool -dV > Probing for ITE Super I/O (init=standard) at 0x2e... > Found ITE IT8712F (id=0x8712, rev=0x8) at 0x2e > Register dump: > idx 20 21 22 23 24 2b > val 87 12 08 00 00 00 > def 87 12 08 00 00 00 > LDN 0x00 (Floppy) > idx 30 60 61 70 74 f0 f1 > val 00 03 f0 06 02 00 00 > def 00 03 f0 06 02 00 00 > LDN 0x01 (COM1) > idx 30 60 61 70 f0 f1 f2 f3 > val 01 03 f8 04 00 50 00 7f > def 00 03 f8 04 00 50 00 7f > LDN 0x02 (COM2) > idx 30 60 61 70 f0 f1 f2 f3 > val 00 02 f8 03 00 50 00 7f > def 00 02 f8 03 00 50 00 7f > LDN 0x03 (Parallel port) > idx 30 60 61 62 63 70 74 f0 > val 01 03 78 00 00 07 04 00 > def 00 03 78 07 78 07 03 03 > LDN 0x04 (Environment controller) > idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 > val 01 02 90 02 30 00 00 00 00 00 00 00 df > def 00 02 90 02 30 09 00 00 00 00 00 NA NA > LDN 0x05 (Keyboard) > idx 30 60 61 62 63 70 71 f0 > val 01 00 60 00 64 01 02 04 > def 01 00 60 00 64 01 02 08 > LDN 0x06 (Mouse) > idx 30 70 71 f0 > val 01 0c 02 00 > def 00 0c 02 00 > LDN 0x07 (GPIO) > idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 > b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 > e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd > val c0 e3 01 00 00 00 1f 00 00 03 00 00 00 00 00 00 38 00 00 00 00 > 00 00 00 00 00 00 00 00 00 c0 e3 01 00 00 c0 e1 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 1a 00 00 00 00 00 00 00 > def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00 00 > 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 > LDN 0x08 (MIDI port) > idx 30 60 61 70 f0 > val 00 03 00 0a 00 > def 00 03 00 0a 00 > LDN 0x09 (Game port) > idx 30 60 61 > val 00 02 01 > def 00 02 01 > LDN 0x0a (Consumer IR) > idx 30 60 61 70 f0 > val 00 03 10 0b 06 > def 00 03 10 0b 00 > > # flashrom -V > flashrom v0.9.4-r1395 on Linux 3.1.1 (x86_64), built with libpci > 3.1.7, GCC 4.5.2, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 1500M loops > per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 996 us, > 10000 myus = 9975 us, 4 myus = 5 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "System manufacturer" > DMI string system-product-name: "System Product Name" > DMI string system-version: "System Version" > DMI string baseboard-manufacturer: "ASUSTeK Computer INC." > DMI string baseboard-product-name: "M4A785TD-V EVO" > DMI string baseboard-version: "Rev X.0x" > DMI string chassis-type: "Desktop" > Found ITE Super I/O, ID 0x8712 on port 0x2e > Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. > Enabling flash write... SPI base address is at 0xfec10000 > AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 > PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 > SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, > ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 > NormSpeed is 33 MHz > GPIO11 used for SPI_DO > GPIO12 used for SPI_DI > GPIO31 used for SPI_HOLD > GPIO32 used for SPI_CS > GPIO47 used for SPI_CLK > SB700 IMC is not active. > ROM strap override is not active > OK. > This chipset supports the following protocols: LPC, FWH, SPI. > Super I/O ID 0x8712 is not on the list of flash capable controllers. > Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x0c, id2 > 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x0c, id2 0x8e, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Chip status register is 00 > Chip status register: Status Register Write Disable (SRWD) is not set > Chip status register: Bit 6 is not set > Chip status register: Bit 5 / Block Protect 3 (BP3) is not set > Chip status register: Bit 4 / Block Protect 2 (BP2) is not set > Chip status register: Bit 3 / Block Protect 1 (BP1) is not set > Chip status register: Bit 2 / Block Protect 0 (BP0) is not set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical > address 0xfff00000. > Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x40, id2 > 0x40, id1 is normal flash content, id2 is normal flash content > Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x0c, id2 > 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 > Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 > Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 > Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 > 0x13 > Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x40, > id2 0x40, id1 is normal flash content, id2 is normal flash content > Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x24, > id2 0x41, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x0c, > id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x0c, id2 > 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, > id2 0xff, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x40, id2 > 0x40, id1 is normal flash content, id2 is normal flash content > Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x40, id2 > 0x40, id1 is normal flash content, id2 is normal flash content > Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x0c, id2 > 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x0c, id2 > 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing > information, using default 10mS/40uS. probe_jedec_common: id1 0xff, > id2 0xff, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. > Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. > Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. > Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x0c, id2 0x8e, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x0c, id2 0x8e, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x40, id2 0x40, > id1 is normal flash content, id2 is normal flash content > Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x0c, id2 0x8e, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x0c, > id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x0c, > id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x0c, > id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x0c, > id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x0c, > id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x0c, > id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, > id2 0xff, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x40, > id2 0x40, id1 is normal flash content, id2 is normal flash content > Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x40, > id2 0x40, id1 is normal flash content, id2 is normal flash content > Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, > id2 0xff, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: > id1 0x0c, id2 0x8e, id1 parity violation, id1 is normal flash content, > id2 is normal flash content > Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: > id1 0xc2, id2 0x2014 > Probing for Atmel unknown Atmel SPI chip, 0 kB: > probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: > id1 0xc2, id2 0x2014 > Probing for Macronix unknown Macronix SPI chip, 0 kB: > probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: > id1 0xc2, id2 0x2014 > Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: > id1 0xc2, id2 0x2014 > Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Sanyo unknown Sanyo SPI chip, 0 kB: > probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Generic unknown SPI chip (RDID), 0 kB: > probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 > 0xc2, id2 0x13 > No operations were specified. > > -- > Jes?s Guerrero Botella > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From wangqingpei at gmail.com Tue Nov 15 06:53:37 2011 From: wangqingpei at gmail.com (QingPei Wang) Date: Tue, 15 Nov 2011 13:53:37 +0800 Subject: [coreboot] VGA issues on ASUS M4A785T-M In-Reply-To: <201111112229.30590.GNUtoo@no-log.org> References: <201111111953.43899.GNUtoo@no-log.org> <1321040367.9998.216.camel@obelix> <201111112229.30590.GNUtoo@no-log.org> Message-ID: most of the time, the VGA bios extracted from the factory bios have the different device ID, the two different VGA bios which you extracted are both the VGA bios for different usage, one of them is used for DVI,and the other one is used for HDMI(not sure, i do not remember that very well). The VGA bios sometimes does not work, and my suggestion is trying to cat the VGA bios under Linux shell. The device ID of AMD VGA is a mess.... Best wishes QingPei Wang Phone: 86+018930528086 On Sat, Nov 12, 2011 at 5:29 AM, Denis 'GNUtoo' Carikli wrote: > >Have you transferred the graphic controllers VGA bios from the original > >bios? > yes I've added the VGA bios rom in my Image, it was extracted with the > following command: > > cat /proc/iomem | grep 'Video ROM' | (read m; m=${m/ :*}; s=${m/-*}; > e=${m/*-}; \ > dd if=/dev/mem of=vgabios.bin bs=1c skip=$[0x$s] > count=$[$[0x$e]-$[0x$s]+1]) > (I followed the wiki at http://www.coreboot.org/VGA_support) > > If I put wrong PCI IDs it won't initialize the display at all during > boot... > > >At least your subsystem vendor/device ID pair does not match. > yes, how do I fix that? > > > PS: some more verbose lspci infos: > > Coreboot: > # lspci -s 01:05.0 -knnvvv > 01:05.0 VGA compatible controller [0300]: ATI Technologies Inc RS880 > [Radeon > HD 4200] [1002:9710] (prog-if 00 [VGA controller]) > Subsystem: ATI Technologies Inc Device [1002:0000] > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- > SERR- Latency: 0, Cache Line Size: 64 bytes > Interrupt: pin A routed to IRQ 18 > Region 0: Memory at c0000000 (32-bit, prefetchable) [size=256M] > Region 1: I/O ports at 1000 [size=256] > Region 2: Memory at d8100000 (32-bit, non-prefetchable) [size=64K] > Region 5: Memory at d8000000 (32-bit, non-prefetchable) [size=1M] > Expansion ROM at [disabled] > Capabilities: [50] Power Management version 3 > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA > PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Kernel driver in use: radeon > Kernel modules: radeon > > > Bios: > # lspci -s 01:05.0 -knnvvv > 01:05.0 VGA compatible controller [0300]: ATI Technologies Inc RS880 > [Radeon > HD 4200] [1002:9710] (prog-if 00 [VGA controller]) > Subsystem: ASUSTeK Computer Inc. M4A785TD Motherboard [1043:83a2] > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR+ FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- > SERR+ Latency: 0, Cache Line Size: 64 bytes > Interrupt: pin A routed to IRQ 18 > Region 0: Memory at d0000000 (32-bit, prefetchable) [size=256M] > Region 1: I/O ports at d000 [size=256] > Region 2: Memory at fe9f0000 (32-bit, non-prefetchable) [size=64K] > Region 5: Memory at fe800000 (32-bit, non-prefetchable) [size=1M] > Expansion ROM at [disabled] > Capabilities: [50] Power Management version 3 > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA > PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Kernel driver in use: radeon > Kernel modules: radeon > > > Thanks a lot for the Answer. > > Denis. > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jesus.guerrero.botella at gmail.com Tue Nov 15 08:49:45 2011 From: jesus.guerrero.botella at gmail.com (=?UTF-8?Q?Jes=C3=BAs_J=2E_Guerrero_Botella?=) Date: Tue, 15 Nov 2011 08:49:45 +0100 Subject: [coreboot] Asus M4A785TD-V In-Reply-To: References: Message-ID: El d?a 15 de noviembre de 2011 04:12, QingPei Wang escribi?: > hi, > ??? Since AMD785/710 are supported by coreboot for a long time. I guess your > board can run coreboot well. And more, M4A785TD-M and M4A785TD-V are almost > the same. Just try to use the bios of M4A785TD-M. Ok, I am reading docs. I know about this project since years ago, when it was called linuxbios, but never dared (nor needed) to try it. If I have more doubts I'll ask here on due time, but now I have a little doubt. Is there any way to proceed safely other than backing up the bios in a separate chip? If that's the only way I think I'll need to buy one of those pdip 8-legged chips. I have lots of bioses that I removed from other boards but none of this kind. Thank you :) -- Jes?s Guerrero Botella From nrubinstein at proformatique.com Tue Nov 15 12:07:35 2011 From: nrubinstein at proformatique.com (=?iso-8859-1?B?Tm/p?= Rubinstein) Date: Tue, 15 Nov 2011 12:07:35 +0100 Subject: [coreboot] [RFC] A more robust fallback system Message-ID: <20111115110735.GA9578@xivo-clients.proformatique.com> Hi, This is an RFC. I'm currently working towards providing a more secure fallback mechanism to Coreboot. I had pushed some preliminary changes to Gerrit some weeks ago?, and I've tried to take the reviews in account. As the changes touch some pretty critical parts of Coreboot, I'm sending this to the mailing list for comments. The patches are not ready yet, and the changes that have been made to CBFStool and TINY_BOOTBLOCK et al. recently will prolly make the rebasing work non-trivial. On some chips, it is possible to block writing on some part of the ROM when the system is running. We (at my company) plan to use that to prevent a careless user updating or modifying their BIOS to brick their system, by putting a 'fallback' Coreboot in the high, write-blocked part of the boot ROM, and using the fallback mechanism already implemented in Coreboot in order to fallback in case the user-flashed firmware does not work. This requires an ability to specify that the components of a Coreboot build have to be written in the high part of the ROM. As cbfstool already supports setting the precise address at which a file must be mapped in memory, this could be implemented completely in the build system. However, this is non-trivial, so I really think it is better for cbfstool to handle the calculations. However, if the user writes in the low part of the ROM a Coreboot build with the "fallback" CBFS prefix (which is the default), the fallback mechanism won't work, as it will always boot on the first component found with the right name. That's why the fallback mechanism has to search for the fallback image only in the high part of the RAM. That requires modification of walkcbfs_asm and of cbfslib to be able to find a file after an offset. In order to do this, we add a build option named OFFSET_IN_ROM which defaults to 0x0 and enables putting Coreboot in the high part of the ROM. OFFSET_IN_ROM is used in the build system to call cbfstool (including in order to call link the romstage properly), and is used in Coreboot itself as an argument to the CBFS search functions. Note that in order to write a component after an offset in cbfstool, the whole beginning of the ROM has to be walked through in order not to overwrite part of another file. On the contrary, when looking for a fallback component, the file headers before the fallback offset should not be trusted (that's the whole point), so the beginning of the ROM should be entirely skipped. It is to be noted that this mechanism is still imperfect, as the CBFS header is at the bottom of the ROM and holds info about file alignment and offset. In order to prevent problems, the implementation should use conservative values instead of those written in the CBFS header. I'm preparing a changeset implementing this mechanism. I should post it to gerrit soon if the reactions to this RFC are positive. Later, we could implement a more robust solution would be storing another CBFS header in the middle of the ROM; either completely splitting the ROM in two or storing the second CBFS header as a CBFS file. In both cases, that would require much more effort to implement than the current proposal. Any idea/objection? Thanks in advance. ?: http://review.coreboot.org/284 http://review.coreboot.org/285 http://review.coreboot.org/286 -- No? Rubinstein Avencall - XiVO IPBX Open Hardware 10 bis, rue Lucien VOILIN - 92800 Puteaux From gerrit at coreboot.org Tue Nov 15 13:44:35 2011 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 15 Nov 2011 13:44:35 +0100 Subject: [coreboot] New patch to review for coreboot: a752a8e mainboard: Add AMD southstation RDK support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/433 -gerrit commit a752a8e33034d6e9be92b5edc4ff0023612d8873 Author: Kerry Sheh Date: Tue Nov 15 21:13:00 2011 +0800 mainboard: Add AMD southstation RDK support AMD southstation Reference Design Kit is designed for NAS application. This platform using family14 RevC0 processor, SB850 southbridge. Vgabios and Promise RAID Option ROM is required for hardware RAID support, can retrieve from the AMD NDA website. Verified feature: HDMI, LAN, usb and mini-pcie slot. RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10. Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a Signed-off-by: Kerry She Signed-off-by: Kerry She --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/south_station/BiosCallOuts.c | 614 +++++++ src/mainboard/amd/south_station/BiosCallOuts.h | 80 + src/mainboard/amd/south_station/Kconfig | 135 ++ src/mainboard/amd/south_station/Makefile.inc | 34 + src/mainboard/amd/south_station/OptionsIds.h | 64 + src/mainboard/amd/south_station/PlatformGnbPcie.c | 168 ++ .../amd/south_station/PlatformGnbPcieComplex.h | 72 + src/mainboard/amd/south_station/acpi/cpstate.asl | 75 + src/mainboard/amd/south_station/acpi/ide.asl | 244 +++ src/mainboard/amd/south_station/acpi/routing.asl | 398 +++++ src/mainboard/amd/south_station/acpi/sata.asl | 149 ++ src/mainboard/amd/south_station/acpi/ssdt2.asl | 84 + src/mainboard/amd/south_station/acpi/ssdt3.asl | 84 + src/mainboard/amd/south_station/acpi/ssdt4.asl | 84 + src/mainboard/amd/south_station/acpi/ssdt5.asl | 85 + src/mainboard/amd/south_station/acpi/usb.asl | 161 ++ src/mainboard/amd/south_station/acpi_tables.c | 248 +++ src/mainboard/amd/south_station/agesawrapper.c | 541 ++++++ src/mainboard/amd/south_station/agesawrapper.h | 90 + src/mainboard/amd/south_station/buildOpts.c | 458 +++++ src/mainboard/amd/south_station/chip.h | 23 + src/mainboard/amd/south_station/cmos.layout | 118 ++ src/mainboard/amd/south_station/devicetree.cb | 105 ++ src/mainboard/amd/south_station/dimmSpd.c | 166 ++ src/mainboard/amd/south_station/dimmSpd.h | 63 + src/mainboard/amd/south_station/dsdt.asl | 1806 ++++++++++++++++++++ src/mainboard/amd/south_station/fadt.c | 194 +++ src/mainboard/amd/south_station/get_bus_conf.c | 138 ++ src/mainboard/amd/south_station/irq_tables.c | 122 ++ src/mainboard/amd/south_station/mainboard.c | 143 ++ src/mainboard/amd/south_station/mptable.c | 158 ++ src/mainboard/amd/south_station/platform_cfg.h | 230 +++ src/mainboard/amd/south_station/reset.c | 66 + src/mainboard/amd/south_station/romstage.c | 110 ++ 35 files changed, 7313 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index 9ed3133..f9c406e 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -29,6 +29,8 @@ config BOARD_AMD_INAGUA bool "Inagua" config BOARD_AMD_PERSIMMON bool "Persimmon" +config BOARD_AMD_SOUTHSTATION + bool "Southstation" config BOARD_AMD_TORPEDO bool "Torpedo" endchoice @@ -46,6 +48,7 @@ source "src/mainboard/amd/tilapia_fam10/Kconfig" source "src/mainboard/amd/bimini_fam10/Kconfig" source "src/mainboard/amd/inagua/Kconfig" source "src/mainboard/amd/persimmon/Kconfig" +source "src/mainboard/amd/south_station/Kconfig" source "src/mainboard/amd/torpedo/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c new file mode 100644 index 0000000..3fb0e87 --- /dev/null +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -0,0 +1,614 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "BiosCallOuts.h" +#include "heapManager.h" +#include "SB800.h" + +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset + }, + + {AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, + + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + CalloutStatus = AGESA_UNSUPPORTED; + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + return CalloutStatus; + } + } + + return CalloutStatus; +} + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; + + FcnData = Data; + MemData = ConfigPtr; + + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + switch(MemData->ParameterListPtr->DDR3Voltage){ + case VOLT1_35: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_25: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_5: + default: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + } + return Status; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 4: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + } + break; + case 6: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + } + break; + case 7: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/amd/south_station/BiosCallOuts.h b/src/mainboard/amd/south_station/BiosCallOuts.h new file mode 100644 index 0000000..b187fa2 --- /dev/null +++ b/src/mainboard/amd/south_station/BiosCallOuts.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define REQUIRED_CALLOUTS 12 +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig new file mode 100644 index 0000000..3828054 --- /dev/null +++ b/src/mainboard/amd/south_station/Kconfig @@ -0,0 +1,135 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_SOUTHSTATION + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select TINY_BOOTBLOCK + select GFXUMA + select UDELAY_LAPIC + +config AMD_AGESA + bool + default y + +config MAINBOARD_DIR + string + default amd/south_station + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Southstation" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config SIO_PORT + hex + default 0x4e + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n +config VGA_BIOS_FILE + string + default "site-local/vgabios.bin" + +config VGA_BIOS_ID + string + default "1002,9806" + +config DRIVERS_PS2_KEYBOARD + bool + default n + +config WARNINGS_ARE_ERRORS + bool + default n + +endif # BOARD_AMD_SOUTHSTATION + diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc new file mode 100644 index 0000000..1cb32b3 --- /dev/null +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -0,0 +1,34 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c + +ramstage-y += reset.c + +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14 diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h new file mode 100644 index 0000000..028d58f --- /dev/null +++ b/src/mainboard/amd/south_station/OptionsIds.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c new file mode 100644 index 0000000..59d31ef --- /dev/null +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + }, + #if 1 + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + }, + #endif + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeDP, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (BrazosPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 5, + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 2, + &InitEarly->StdHeader); + + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; +} + diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..f35d8db --- /dev/null +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/south_station/acpi/cpstate.asl b/src/mainboard/amd/south_station/acpi/cpstate.asl new file mode 100644 index 0000000..5eca9cc --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/south_station/acpi/ide.asl b/src/mainboard/amd/south_station/acpi/ide.asl new file mode 100644 index 0000000..c79c18c --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl new file mode 100644 index 0000000..cb50394 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -0,0 +1,398 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + Package(){0x0009FFFF, 0, INTB, 0 }, + Package(){0x0009FFFF, 1, INTC, 0 }, + Package(){0x0009FFFF, 2, INTD, 0 }, + Package(){0x0009FFFF, 3, INTA, 0 }, + + Package(){0x000AFFFF, 0, INTC, 0 }, + Package(){0x000AFFFF, 1, INTD, 0 }, + Package(){0x000AFFFF, 2, INTA, 0 }, + Package(){0x000AFFFF, 3, INTB, 0 }, + + Package(){0x000BFFFF, 0, INTD, 0 }, + Package(){0x000BFFFF, 1, INTA, 0 }, + Package(){0x000BFFFF, 2, INTB, 0 }, + Package(){0x000BFFFF, 3, INTC, 0 }, + + Package(){0x000CFFFF, 0, INTA, 0 }, + Package(){0x000CFFFF, 1, INTB, 0 }, + Package(){0x000CFFFF, 2, INTC, 0 }, + Package(){0x000CFFFF, 3, INTD, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Package(){0x0014FFFF, 1, INTA, 0 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + /* Package(){0x0012FFFF, 2, 0, 18 }, */ + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + /* Package(){0x0013FFFF, 2, 0, 16 }, */ + + /* Package(){0x00140000, 0, 0, 16 }, */ + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl new file mode 100644 index 0000000..bd4acf0 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/south_station/acpi/ssdt2.asl b/src/mainboard/amd/south_station/acpi/ssdt2.asl new file mode 100644 index 0000000..ef1a4bf --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/ssdt2.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci2_hc.asl" + } + } + +} + diff --git a/src/mainboard/amd/south_station/acpi/ssdt3.asl b/src/mainboard/amd/south_station/acpi/ssdt3.asl new file mode 100644 index 0000000..68a4b95 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/ssdt3.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci3_hc.asl" + } + } + +} + diff --git a/src/mainboard/amd/south_station/acpi/ssdt4.asl b/src/mainboard/amd/south_station/acpi/ssdt4.asl new file mode 100644 index 0000000..e06fe8a --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/ssdt4.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci4_hc.asl" + } + } + +} + diff --git a/src/mainboard/amd/south_station/acpi/ssdt5.asl b/src/mainboard/amd/south_station/acpi/ssdt5.asl new file mode 100644 index 0000000..a141a37 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/ssdt5.asl @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci5_hc.asl" + } + } + +} + diff --git a/src/mainboard/amd/south_station/acpi/usb.asl b/src/mainboard/amd/south_station/acpi/usb.asl new file mode 100644 index 0000000..181d685 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/usb.asl @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c new file mode 100644 index 0000000..2a299d8 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include +#include + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 + +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; +extern const unsigned char AmlCode_ssdt[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FDAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + ssdt = (acpi_header_t *) current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + char *position = ssdt; + if (memcmp(position + 50, "TOM1", 4) == 0) + *(u32 *)(position + 55) = __readmsr(0xc001001a); + + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c new file mode 100644 index 0000000..74aa73d --- /dev/null +++ b/src/mainboard/amd/south_station/agesawrapper.c @@ -0,0 +1,541 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include +#include +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" +#include + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define MMCONF_ENABLE 1 + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; // last address before non-posted range + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } + + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000ull; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; + } + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + /* Write to D1F0x18 */ + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x00010100; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Legacy Bridge Mode + * Modify B1D5F0x18 + */ + PciAddress.Address.Bus = 1; + PciAddress.Address.Device = 5; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Legacy Bridge Mode + * Modify B1D5F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Pcie Mode + * Modify B0D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Pcie Mode + * Modify B0D1F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Base and Limit Address + * Modify B0D1F0x20 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x20; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96009600; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Prefetchable Memory Limit and Base + * Modify B0D1F0x24 + */ + PciAddress.Address.Register = 0x24; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x8FF18001; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; + + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdreadeventlog ( + VOID + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/south_station/agesawrapper.h b/src/mainboard/amd/south_station/agesawrapper.h new file mode 100644 index 0000000..f8d924e --- /dev/null +++ b/src/mainboard/amd/south_station/agesawrapper.h @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); + +UINT32 agesawrapper_amdreadeventlog (void); + +UINT32 agesawrapper_amdinitcpuio (void); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +void *agesawrapper_getlateinitptr (int pick); + +#endif diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c new file mode 100644 index 0000000..48e18a6 --- /dev/null +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -0,0 +1,458 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + */ + +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + +/* + * Agesa entry points used in this implementation. + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE//TRUE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" +#include "CommonReturns.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +//DA Customer table +CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + + diff --git a/src/mainboard/amd/south_station/chip.h b/src/mainboard/amd/south_station/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/amd/south_station/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout new file mode 100644 index 0000000..8315401 --- /dev/null +++ b/src/mainboard/amd/south_station/cmos.layout @@ -0,0 +1,118 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb new file mode 100644 index 0000000..f0b471a --- /dev/null +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -0,0 +1,105 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family14/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM +## chip drivers/generic/generic #dimm 0-0-0 +## device i2c 50 on end +## end +## chip drivers/generic/generic #dimm 0-0-1 +## device i2c 51 on end +## end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family14/root_complex + diff --git a/src/mainboard/amd/south_station/dimmSpd.c b/src/mainboard/amd/south_station/dimmSpd.c new file mode 100644 index 0000000..9da0e0e --- /dev/null +++ b/src/mainboard/amd/south_station/dimmSpd.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*#pragma optimize ("", off) // for source level debug +*--------------------------------------------------------------------------- +* +* SPD address table - porting required +*/ + +static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm + { + // socket 0 + { + {0xA0, 0xA2}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + // socket 1 + { + {0x00, 0x00}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + }; + +/*----------------------------------------------------------------------------- + * + * readSmbusByteData - read a single SPD byte from any offset + */ + +static int readSmbusByteData (int iobase, int address, char *buffer, int offset) + { + unsigned int status; + UINT64 limit; + + address |= 1; // set read bit + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command + + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; + } + +/*----------------------------------------------------------------------------- + * + * readSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + */ + +static int readSmbusByte (int iobase, int address, char *buffer) + { + unsigned int status; + UINT64 limit; + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; + } + +/*--------------------------------------------------------------------------- + * + * readspd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ + +static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) + { + int index, error; + + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; + + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) + { + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } + + return 0; + } + +static void writePmReg (int reg, int data) + { + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); + } + +static void setupFch (int ioBase) + { + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + writePmReg (0x29, 0x80); + writePmReg (0x28, 0x61); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + } + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) + { + int spdAddress, ioBase; + + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + ioBase = 0xB00; + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); + } diff --git a/src/mainboard/amd/south_station/dimmSpd.h b/src/mainboard/amd/south_station/dimmSpd.h new file mode 100644 index 0000000..069c34a --- /dev/null +++ b/src/mainboard/amd/south_station/dimmSpd.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl new file mode 100644 index 0000000..c4b69bd --- /dev/null +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -0,0 +1,1806 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "SOUTHSTN", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x808, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PIRA) + Store(0, PIRB) + Store(0, PIRC) + Store(0, PIRD) + Store(0, PIRE) + Store(0, PIRF) + Store(0, PIRG) + Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#if 0 + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#endif + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ +#if 0 + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PEBM + ) +#endif + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ +#if 0 + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * Subtract(TOM2, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } +#endif + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ +#if 0 + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +#endif +} +/* End of ASL file */ diff --git a/src/mainboard/amd/south_station/fadt.c b/src/mainboard/amd/south_station/fadt.c new file mode 100644 index 0000000..020d011 --- /dev/null +++ b/src/mainboard/amd/south_station/fadt.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + + +#include +#include +#include +#include +#include +#include "SBPLATFORM.h" + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + u16 val = 0; + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + val = PM1_EVT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); + val = PM1_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); + val = PM1_TMR_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); + val = GPE0_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + val = CPU_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); + val = 0; + WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); + val = ACPI_PMA_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val); + + /* AcpiDecodeEnable, When set, SB uses the contents of the + * PM registers at index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + val = BIT0 | BIT1 | BIT2 | BIT4; + WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c new file mode 100644 index 0000000..4bc5b48 --- /dev/null +++ b/src/mainboard/amd/south_station/get_bus_conf.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif + + +/* Global variables for MB layouts and these will be shared by irqtable mptable +* and acpi_tables busnum is default. +*/ +u8 bus_isa; +u8 bus_sb800[3]; +u32 apicid_sb800; + +/* +* Here you only need to set value in pci1234 for HT-IO that could be installed or not +* You may need to preset pci1234 for HTIO board, +* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +*/ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_sb800; + +static u32 get_bus_conf_done = 0; + + +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + +/* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + + sbdn_sb800 = 0; + + for (i = 0; i < 3; i++) { + bus_sb800[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + + bus_type[0] = 1; /* pci */ + +// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + + /* sb800 */ + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + + + + if (dev) { + bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb800[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + if (dev) { + bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sb800[2]; j < bus_isa; j++) + bus_type[j] = 1; + + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_sb800 = apicid_base; + +#if CONFIG_AMD_SB_CIMX + sb_Late_Post(); +#endif +} diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c new file mode 100644 index 0000000..28432dd --- /dev/null +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sb800[2]; +extern unsigned long sbdn_sb800; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb800[0]; + pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c new file mode 100644 index 0000000..990c8b9 --- /dev/null +++ b/src/mainboard/amd/south_station/mainboard.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "chip.h" + +uint64_t uma_memory_base, uma_memory_size; + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + +/** + * Southstation using SB GPIO 17/18 to control the Red/Green LED + * These two LEDs can be used to show the OS booting status. + */ +static void southstation_led_init(void) +{ +#define GPIO_FUNCTION 2 //GPIO function +#define SB_GPIO_REG17 17 //Red Light +#define SB_GPIO_REG18 18 //Green Light + + /* multi-function pins switch to GPIO0-35 */ + RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); + + /* select IOMux to function2, corresponds to GPIO */ + RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); + RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); + + /* Lighting test */ + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08); + mdelay(100); + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48); +} + + +/************************************************* +* enable the dedicated function in southstation board. +*************************************************/ +static void southstation_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + uint32_t sys_mem; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 0x10000000; /* 256M recommended UMA */ + uma_memory_base = 0x30000000; /* 1GB system memory supported */ +#endif + southstation_led_init(); +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = southstation_enable, +}; diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c new file mode 100644 index 0000000..a3b4b5c --- /dev/null +++ b/src/mainboard/amd/south_station/mptable.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +extern u8 bus_sb800[2]; + +extern u32 apicid_sb800; + +extern u32 bus_type[256]; +extern u32 sbdn_sb800; + +u8 intr_data[] = { + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + get_bus_conf(); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + + u32 dword; + u8 byte; + + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + dword &= 0xFFFFFFF0; + smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#if CONFIG_GENERATE_ACPI_TABLES == 0 +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif + + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + /* HD Audio: */ + PCI_INT(0x0, 0x14, 0x2, 0x12); + + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); + PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); + PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h new file mode 100644 index 0000000..66aab8b --- /dev/null +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _PERSIMMON_CFG_H_ +#define _PERSIMMON_CFG_H_ + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 + #define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 + #define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 + #define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 + #define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +#endif diff --git a/src/mainboard/amd/south_station/reset.c b/src/mainboard/amd/south_station/reset.c new file mode 100644 index 0000000..36bc6e0 --- /dev/null +++ b/src/mainboard/amd/south_station/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c new file mode 100644 index 0000000..95f27bd --- /dev/null +++ b/src/mainboard/amd/south_station/romstage.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include "cpu/x86/bist.h" +#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "sb_cimx.h" +#include "SBPLATFORM.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + __writemsr (0xc0010062, 0); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x35); + val = agesawrapper_amdinitmmio(); + + post_code(0x37); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + + post_code(0x38); + printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + + post_code(0x39); + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + + post_code(0x50); + copy_and_run(0); + + post_code(0x54); // Should never see this post code. +} + From gerrit at coreboot.org Tue Nov 15 13:44:36 2011 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 15 Nov 2011 13:44:36 +0100 Subject: [coreboot] New patch to review for coreboot: 14e5797 mainboard: Add AMD unionstation RDK support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/434 -gerrit commit 14e579769a5d6cbd65f29351a82368b991156b66 Author: Kerry Sheh Date: Tue Nov 15 21:15:12 2011 +0800 mainboard: Add AMD unionstation RDK support AMD unionstation Reference Design Kit is Designed for hd settop box application. This platform using family14 APU, SB800 southbridge. Vgabios is required, can download vgabios from AMD NDA website. Verified Feature: HDMI, LAN, mini-pcie slots, sata, usb, analog audio and optical fiber digital audio output. Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c Signed-off-by: Kerry She Signed-off-by: Kerry She --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/union_station/BiosCallOuts.c | 614 +++++++ src/mainboard/amd/union_station/BiosCallOuts.h | 80 + src/mainboard/amd/union_station/Kconfig | 135 ++ src/mainboard/amd/union_station/Makefile.inc | 34 + src/mainboard/amd/union_station/OptionsIds.h | 64 + src/mainboard/amd/union_station/PlatformGnbPcie.c | 168 ++ .../amd/union_station/PlatformGnbPcieComplex.h | 72 + src/mainboard/amd/union_station/acpi/cpstate.asl | 75 + src/mainboard/amd/union_station/acpi/ide.asl | 244 +++ src/mainboard/amd/union_station/acpi/routing.asl | 398 +++++ src/mainboard/amd/union_station/acpi/sata.asl | 149 ++ src/mainboard/amd/union_station/acpi/ssdt2.asl | 84 + src/mainboard/amd/union_station/acpi/ssdt3.asl | 84 + src/mainboard/amd/union_station/acpi/ssdt4.asl | 84 + src/mainboard/amd/union_station/acpi/ssdt5.asl | 85 + src/mainboard/amd/union_station/acpi/usb.asl | 161 ++ src/mainboard/amd/union_station/acpi_tables.c | 248 +++ src/mainboard/amd/union_station/agesawrapper.c | 541 ++++++ src/mainboard/amd/union_station/agesawrapper.h | 90 + src/mainboard/amd/union_station/buildOpts.c | 458 +++++ src/mainboard/amd/union_station/chip.h | 23 + src/mainboard/amd/union_station/cmos.layout | 118 ++ src/mainboard/amd/union_station/devicetree.cb | 105 ++ src/mainboard/amd/union_station/dimmSpd.c | 166 ++ src/mainboard/amd/union_station/dimmSpd.h | 63 + src/mainboard/amd/union_station/dsdt.asl | 1806 ++++++++++++++++++++ src/mainboard/amd/union_station/fadt.c | 194 +++ src/mainboard/amd/union_station/get_bus_conf.c | 138 ++ src/mainboard/amd/union_station/irq_tables.c | 122 ++ src/mainboard/amd/union_station/mainboard.c | 117 ++ src/mainboard/amd/union_station/mptable.c | 158 ++ src/mainboard/amd/union_station/platform_cfg.h | 230 +++ src/mainboard/amd/union_station/reset.c | 66 + src/mainboard/amd/union_station/romstage.c | 107 ++ 35 files changed, 7284 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index f9c406e..62ae584 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -33,6 +33,8 @@ config BOARD_AMD_SOUTHSTATION bool "Southstation" config BOARD_AMD_TORPEDO bool "Torpedo" +config BOARD_AMD_UNIONSTATION + bool "Unionstation" endchoice source "src/mainboard/amd/db800/Kconfig" @@ -50,6 +52,7 @@ source "src/mainboard/amd/inagua/Kconfig" source "src/mainboard/amd/persimmon/Kconfig" source "src/mainboard/amd/south_station/Kconfig" source "src/mainboard/amd/torpedo/Kconfig" +source "src/mainboard/amd/union_station/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c new file mode 100644 index 0000000..3fb0e87 --- /dev/null +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -0,0 +1,614 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "BiosCallOuts.h" +#include "heapManager.h" +#include "SB800.h" + +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset + }, + + {AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, + + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + CalloutStatus = AGESA_UNSUPPORTED; + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + return CalloutStatus; + } + } + + return CalloutStatus; +} + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; + + FcnData = Data; + MemData = ConfigPtr; + + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + switch(MemData->ParameterListPtr->DDR3Voltage){ + case VOLT1_35: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_25: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_5: + default: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + } + return Status; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 4: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + } + break; + case 6: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + } + break; + case 7: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/amd/union_station/BiosCallOuts.h b/src/mainboard/amd/union_station/BiosCallOuts.h new file mode 100644 index 0000000..b187fa2 --- /dev/null +++ b/src/mainboard/amd/union_station/BiosCallOuts.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define REQUIRED_CALLOUTS 12 +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig new file mode 100644 index 0000000..db0d1e4 --- /dev/null +++ b/src/mainboard/amd/union_station/Kconfig @@ -0,0 +1,135 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_UNIONSTATION + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_2048 + select TINY_BOOTBLOCK + select GFXUMA + select UDELAY_LAPIC + +config AMD_AGESA + bool + default y + +config MAINBOARD_DIR + string + default amd/union_station + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Unionstation" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config SIO_PORT + hex + default 0x4e + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n +config VGA_BIOS_FILE + string + default "site-local/vgabios.bin" + +config VGA_BIOS_ID + string + default "1002,9802" + +config DRIVERS_PS2_KEYBOARD + bool + default n + +config WARNINGS_ARE_ERRORS + bool + default n + +endif # BOARD_AMD_UNIONSTATION + diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc new file mode 100644 index 0000000..1cb32b3 --- /dev/null +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -0,0 +1,34 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c + +ramstage-y += reset.c + +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14 diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h new file mode 100644 index 0000000..028d58f --- /dev/null +++ b/src/mainboard/amd/union_station/OptionsIds.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c new file mode 100644 index 0000000..59d31ef --- /dev/null +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + }, + #if 1 + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + }, + #endif + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeDP, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (BrazosPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 5, + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 2, + &InitEarly->StdHeader); + + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; +} + diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..f35d8db --- /dev/null +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/union_station/acpi/cpstate.asl b/src/mainboard/amd/union_station/acpi/cpstate.asl new file mode 100644 index 0000000..5eca9cc --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/union_station/acpi/ide.asl b/src/mainboard/amd/union_station/acpi/ide.asl new file mode 100644 index 0000000..c79c18c --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl new file mode 100644 index 0000000..cb50394 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/routing.asl @@ -0,0 +1,398 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + Package(){0x0009FFFF, 0, INTB, 0 }, + Package(){0x0009FFFF, 1, INTC, 0 }, + Package(){0x0009FFFF, 2, INTD, 0 }, + Package(){0x0009FFFF, 3, INTA, 0 }, + + Package(){0x000AFFFF, 0, INTC, 0 }, + Package(){0x000AFFFF, 1, INTD, 0 }, + Package(){0x000AFFFF, 2, INTA, 0 }, + Package(){0x000AFFFF, 3, INTB, 0 }, + + Package(){0x000BFFFF, 0, INTD, 0 }, + Package(){0x000BFFFF, 1, INTA, 0 }, + Package(){0x000BFFFF, 2, INTB, 0 }, + Package(){0x000BFFFF, 3, INTC, 0 }, + + Package(){0x000CFFFF, 0, INTA, 0 }, + Package(){0x000CFFFF, 1, INTB, 0 }, + Package(){0x000CFFFF, 2, INTC, 0 }, + Package(){0x000CFFFF, 3, INTD, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Package(){0x0014FFFF, 1, INTA, 0 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + /* Package(){0x0012FFFF, 2, 0, 18 }, */ + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + /* Package(){0x0013FFFF, 2, 0, 16 }, */ + + /* Package(){0x00140000, 0, 0, 16 }, */ + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/amd/union_station/acpi/sata.asl b/src/mainboard/amd/union_station/acpi/sata.asl new file mode 100644 index 0000000..bd4acf0 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/union_station/acpi/ssdt2.asl b/src/mainboard/amd/union_station/acpi/ssdt2.asl new file mode 100644 index 0000000..ef1a4bf --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/ssdt2.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci2_hc.asl" + } + } + +} + diff --git a/src/mainboard/amd/union_station/acpi/ssdt3.asl b/src/mainboard/amd/union_station/acpi/ssdt3.asl new file mode 100644 index 0000000..68a4b95 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/ssdt3.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci3_hc.asl" + } + } + +} + diff --git a/src/mainboard/amd/union_station/acpi/ssdt4.asl b/src/mainboard/amd/union_station/acpi/ssdt4.asl new file mode 100644 index 0000000..e06fe8a --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/ssdt4.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci4_hc.asl" + } + } + +} + diff --git a/src/mainboard/amd/union_station/acpi/ssdt5.asl b/src/mainboard/amd/union_station/acpi/ssdt5.asl new file mode 100644 index 0000000..a141a37 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/ssdt5.asl @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci5_hc.asl" + } + } + +} + diff --git a/src/mainboard/amd/union_station/acpi/usb.asl b/src/mainboard/amd/union_station/acpi/usb.asl new file mode 100644 index 0000000..181d685 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/usb.asl @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c new file mode 100644 index 0000000..2a299d8 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include +#include + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 + +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; +extern const unsigned char AmlCode_ssdt[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FDAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + ssdt = (acpi_header_t *) current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + char *position = ssdt; + if (memcmp(position + 50, "TOM1", 4) == 0) + *(u32 *)(position + 55) = __readmsr(0xc001001a); + + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c new file mode 100644 index 0000000..74aa73d --- /dev/null +++ b/src/mainboard/amd/union_station/agesawrapper.c @@ -0,0 +1,541 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include +#include +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" +#include + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define MMCONF_ENABLE 1 + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; // last address before non-posted range + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } + + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000ull; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; + } + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + /* Write to D1F0x18 */ + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x00010100; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Legacy Bridge Mode + * Modify B1D5F0x18 + */ + PciAddress.Address.Bus = 1; + PciAddress.Address.Device = 5; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Legacy Bridge Mode + * Modify B1D5F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Pcie Mode + * Modify B0D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Pcie Mode + * Modify B0D1F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Base and Limit Address + * Modify B0D1F0x20 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x20; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96009600; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Prefetchable Memory Limit and Base + * Modify B0D1F0x24 + */ + PciAddress.Address.Register = 0x24; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x8FF18001; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; + + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdreadeventlog ( + VOID + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/union_station/agesawrapper.h b/src/mainboard/amd/union_station/agesawrapper.h new file mode 100644 index 0000000..f8d924e --- /dev/null +++ b/src/mainboard/amd/union_station/agesawrapper.h @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); + +UINT32 agesawrapper_amdreadeventlog (void); + +UINT32 agesawrapper_amdinitcpuio (void); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +void *agesawrapper_getlateinitptr (int pick); + +#endif diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c new file mode 100644 index 0000000..48e18a6 --- /dev/null +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -0,0 +1,458 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + */ + +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + +/* + * Agesa entry points used in this implementation. + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE//TRUE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" +#include "CommonReturns.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +//DA Customer table +CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + + diff --git a/src/mainboard/amd/union_station/chip.h b/src/mainboard/amd/union_station/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/amd/union_station/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout new file mode 100644 index 0000000..8315401 --- /dev/null +++ b/src/mainboard/amd/union_station/cmos.layout @@ -0,0 +1,118 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb new file mode 100644 index 0000000..f0b471a --- /dev/null +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -0,0 +1,105 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family14/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM +## chip drivers/generic/generic #dimm 0-0-0 +## device i2c 50 on end +## end +## chip drivers/generic/generic #dimm 0-0-1 +## device i2c 51 on end +## end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family14/root_complex + diff --git a/src/mainboard/amd/union_station/dimmSpd.c b/src/mainboard/amd/union_station/dimmSpd.c new file mode 100644 index 0000000..9da0e0e --- /dev/null +++ b/src/mainboard/amd/union_station/dimmSpd.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*#pragma optimize ("", off) // for source level debug +*--------------------------------------------------------------------------- +* +* SPD address table - porting required +*/ + +static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm + { + // socket 0 + { + {0xA0, 0xA2}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + // socket 1 + { + {0x00, 0x00}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + }; + +/*----------------------------------------------------------------------------- + * + * readSmbusByteData - read a single SPD byte from any offset + */ + +static int readSmbusByteData (int iobase, int address, char *buffer, int offset) + { + unsigned int status; + UINT64 limit; + + address |= 1; // set read bit + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command + + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; + } + +/*----------------------------------------------------------------------------- + * + * readSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + */ + +static int readSmbusByte (int iobase, int address, char *buffer) + { + unsigned int status; + UINT64 limit; + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; + } + +/*--------------------------------------------------------------------------- + * + * readspd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ + +static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) + { + int index, error; + + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; + + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) + { + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } + + return 0; + } + +static void writePmReg (int reg, int data) + { + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); + } + +static void setupFch (int ioBase) + { + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + writePmReg (0x29, 0x80); + writePmReg (0x28, 0x61); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + } + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) + { + int spdAddress, ioBase; + + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + ioBase = 0xB00; + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); + } diff --git a/src/mainboard/amd/union_station/dimmSpd.h b/src/mainboard/amd/union_station/dimmSpd.h new file mode 100644 index 0000000..069c34a --- /dev/null +++ b/src/mainboard/amd/union_station/dimmSpd.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl new file mode 100644 index 0000000..04952d3 --- /dev/null +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -0,0 +1,1806 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "UNIONSTN", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x808, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PIRA) + Store(0, PIRB) + Store(0, PIRC) + Store(0, PIRD) + Store(0, PIRE) + Store(0, PIRF) + Store(0, PIRG) + Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#if 0 + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#endif + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ +#if 0 + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PEBM + ) +#endif + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ +#if 0 + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * Subtract(TOM2, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } +#endif + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ +#if 0 + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +#endif +} +/* End of ASL file */ diff --git a/src/mainboard/amd/union_station/fadt.c b/src/mainboard/amd/union_station/fadt.c new file mode 100644 index 0000000..020d011 --- /dev/null +++ b/src/mainboard/amd/union_station/fadt.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + + +#include +#include +#include +#include +#include +#include "SBPLATFORM.h" + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + u16 val = 0; + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + val = PM1_EVT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); + val = PM1_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); + val = PM1_TMR_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); + val = GPE0_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + val = CPU_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); + val = 0; + WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); + val = ACPI_PMA_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val); + + /* AcpiDecodeEnable, When set, SB uses the contents of the + * PM registers at index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + val = BIT0 | BIT1 | BIT2 | BIT4; + WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c new file mode 100644 index 0000000..4bc5b48 --- /dev/null +++ b/src/mainboard/amd/union_station/get_bus_conf.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif + + +/* Global variables for MB layouts and these will be shared by irqtable mptable +* and acpi_tables busnum is default. +*/ +u8 bus_isa; +u8 bus_sb800[3]; +u32 apicid_sb800; + +/* +* Here you only need to set value in pci1234 for HT-IO that could be installed or not +* You may need to preset pci1234 for HTIO board, +* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +*/ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_sb800; + +static u32 get_bus_conf_done = 0; + + +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + +/* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + + sbdn_sb800 = 0; + + for (i = 0; i < 3; i++) { + bus_sb800[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + + bus_type[0] = 1; /* pci */ + +// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + + /* sb800 */ + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + + + + if (dev) { + bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb800[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + if (dev) { + bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sb800[2]; j < bus_isa; j++) + bus_type[j] = 1; + + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_sb800 = apicid_base; + +#if CONFIG_AMD_SB_CIMX + sb_Late_Post(); +#endif +} diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c new file mode 100644 index 0000000..28432dd --- /dev/null +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sb800[2]; +extern unsigned long sbdn_sb800; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb800[0]; + pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c new file mode 100644 index 0000000..800d64d --- /dev/null +++ b/src/mainboard/amd/union_station/mainboard.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "chip.h" + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + +uint64_t uma_memory_base, uma_memory_size; + +/************************************************* +* enable the dedicated function in unionstation board. +*************************************************/ +static void unionstation_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + uint32_t sys_mem; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 0x10000000; /* 256M recommended UMA */ + uma_memory_base = 0x30000000; /* 1GB system memory supported */ +#endif + +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = unionstation_enable, +}; diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c new file mode 100644 index 0000000..a3b4b5c --- /dev/null +++ b/src/mainboard/amd/union_station/mptable.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +extern u8 bus_sb800[2]; + +extern u32 apicid_sb800; + +extern u32 bus_type[256]; +extern u32 sbdn_sb800; + +u8 intr_data[] = { + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + get_bus_conf(); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + + u32 dword; + u8 byte; + + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + dword &= 0xFFFFFFF0; + smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#if CONFIG_GENERATE_ACPI_TABLES == 0 +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif + + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + /* HD Audio: */ + PCI_INT(0x0, 0x14, 0x2, 0x12); + + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); + PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); + PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h new file mode 100644 index 0000000..66aab8b --- /dev/null +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _PERSIMMON_CFG_H_ +#define _PERSIMMON_CFG_H_ + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 + #define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 + #define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 + #define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 + #define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +#endif diff --git a/src/mainboard/amd/union_station/reset.c b/src/mainboard/amd/union_station/reset.c new file mode 100644 index 0000000..36bc6e0 --- /dev/null +++ b/src/mainboard/amd/union_station/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c new file mode 100644 index 0000000..e7f05e8 --- /dev/null +++ b/src/mainboard/amd/union_station/romstage.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include "cpu/x86/bist.h" +#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "sb_cimx.h" +#include "SBPLATFORM.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x35); + val = agesawrapper_amdinitmmio(); + + post_code(0x37); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + + post_code(0x38); + printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + + post_code(0x39); + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + + post_code(0x50); + copy_and_run(0); + + post_code(0x54); // Should never see this post code. +} + From gerrit at coreboot.org Tue Nov 15 13:53:44 2011 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 15 Nov 2011 13:53:44 +0100 Subject: [coreboot] Patch set updated for coreboot: 8558795 mainboard: Add AMD southstation RDK support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/433 -gerrit commit 8558795ef1369052cf634e2d6c5f33a2a11ad718 Author: Kerry Sheh Date: Tue Nov 15 21:27:07 2011 +0800 mainboard: Add AMD southstation RDK support AMD southstation Reference Design Kit is designed for NAS application. This platform using family14 RevC0 processor, SB850 southbridge. Vgabios and Promise RAID Option ROM is required for hardware RAID support, can retrieve from the AMD NDA website. Verified feature: HDMI, LAN, usb and mini-pcie slot. RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10. Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a Signed-off-by: Kerry She Signed-off-by: Kerry She --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/south_station/BiosCallOuts.c | 614 +++++++ src/mainboard/amd/south_station/BiosCallOuts.h | 80 + src/mainboard/amd/south_station/Kconfig | 135 ++ src/mainboard/amd/south_station/Makefile.inc | 34 + src/mainboard/amd/south_station/OptionsIds.h | 64 + src/mainboard/amd/south_station/PlatformGnbPcie.c | 168 ++ .../amd/south_station/PlatformGnbPcieComplex.h | 72 + src/mainboard/amd/south_station/acpi/cpstate.asl | 75 + src/mainboard/amd/south_station/acpi/ide.asl | 244 +++ src/mainboard/amd/south_station/acpi/routing.asl | 398 +++++ src/mainboard/amd/south_station/acpi/sata.asl | 149 ++ src/mainboard/amd/south_station/acpi/usb.asl | 161 ++ src/mainboard/amd/south_station/acpi_tables.c | 248 +++ src/mainboard/amd/south_station/agesawrapper.c | 541 ++++++ src/mainboard/amd/south_station/agesawrapper.h | 90 + src/mainboard/amd/south_station/buildOpts.c | 458 +++++ src/mainboard/amd/south_station/chip.h | 23 + src/mainboard/amd/south_station/cmos.layout | 118 ++ src/mainboard/amd/south_station/devicetree.cb | 105 ++ src/mainboard/amd/south_station/dimmSpd.c | 166 ++ src/mainboard/amd/south_station/dimmSpd.h | 63 + src/mainboard/amd/south_station/dsdt.asl | 1806 ++++++++++++++++++++ src/mainboard/amd/south_station/fadt.c | 194 +++ src/mainboard/amd/south_station/get_bus_conf.c | 138 ++ src/mainboard/amd/south_station/irq_tables.c | 122 ++ src/mainboard/amd/south_station/mainboard.c | 143 ++ src/mainboard/amd/south_station/mptable.c | 158 ++ src/mainboard/amd/south_station/platform_cfg.h | 230 +++ src/mainboard/amd/south_station/reset.c | 66 + src/mainboard/amd/south_station/romstage.c | 110 ++ 31 files changed, 6976 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index 9ed3133..f9c406e 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -29,6 +29,8 @@ config BOARD_AMD_INAGUA bool "Inagua" config BOARD_AMD_PERSIMMON bool "Persimmon" +config BOARD_AMD_SOUTHSTATION + bool "Southstation" config BOARD_AMD_TORPEDO bool "Torpedo" endchoice @@ -46,6 +48,7 @@ source "src/mainboard/amd/tilapia_fam10/Kconfig" source "src/mainboard/amd/bimini_fam10/Kconfig" source "src/mainboard/amd/inagua/Kconfig" source "src/mainboard/amd/persimmon/Kconfig" +source "src/mainboard/amd/south_station/Kconfig" source "src/mainboard/amd/torpedo/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c new file mode 100644 index 0000000..3fb0e87 --- /dev/null +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -0,0 +1,614 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "BiosCallOuts.h" +#include "heapManager.h" +#include "SB800.h" + +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset + }, + + {AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, + + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + CalloutStatus = AGESA_UNSUPPORTED; + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + return CalloutStatus; + } + } + + return CalloutStatus; +} + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; + + FcnData = Data; + MemData = ConfigPtr; + + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + switch(MemData->ParameterListPtr->DDR3Voltage){ + case VOLT1_35: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_25: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_5: + default: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + } + return Status; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 4: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + } + break; + case 6: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + } + break; + case 7: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/amd/south_station/BiosCallOuts.h b/src/mainboard/amd/south_station/BiosCallOuts.h new file mode 100644 index 0000000..b187fa2 --- /dev/null +++ b/src/mainboard/amd/south_station/BiosCallOuts.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define REQUIRED_CALLOUTS 12 +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig new file mode 100644 index 0000000..3828054 --- /dev/null +++ b/src/mainboard/amd/south_station/Kconfig @@ -0,0 +1,135 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_SOUTHSTATION + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select TINY_BOOTBLOCK + select GFXUMA + select UDELAY_LAPIC + +config AMD_AGESA + bool + default y + +config MAINBOARD_DIR + string + default amd/south_station + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Southstation" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config SIO_PORT + hex + default 0x4e + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n +config VGA_BIOS_FILE + string + default "site-local/vgabios.bin" + +config VGA_BIOS_ID + string + default "1002,9806" + +config DRIVERS_PS2_KEYBOARD + bool + default n + +config WARNINGS_ARE_ERRORS + bool + default n + +endif # BOARD_AMD_SOUTHSTATION + diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc new file mode 100644 index 0000000..1cb32b3 --- /dev/null +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -0,0 +1,34 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c + +ramstage-y += reset.c + +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14 diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h new file mode 100644 index 0000000..028d58f --- /dev/null +++ b/src/mainboard/amd/south_station/OptionsIds.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c new file mode 100644 index 0000000..59d31ef --- /dev/null +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + }, + #if 1 + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + }, + #endif + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeDP, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (BrazosPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 5, + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 2, + &InitEarly->StdHeader); + + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; +} + diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..f35d8db --- /dev/null +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/south_station/acpi/cpstate.asl b/src/mainboard/amd/south_station/acpi/cpstate.asl new file mode 100644 index 0000000..5eca9cc --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/south_station/acpi/ide.asl b/src/mainboard/amd/south_station/acpi/ide.asl new file mode 100644 index 0000000..c79c18c --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl new file mode 100644 index 0000000..cb50394 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -0,0 +1,398 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + Package(){0x0009FFFF, 0, INTB, 0 }, + Package(){0x0009FFFF, 1, INTC, 0 }, + Package(){0x0009FFFF, 2, INTD, 0 }, + Package(){0x0009FFFF, 3, INTA, 0 }, + + Package(){0x000AFFFF, 0, INTC, 0 }, + Package(){0x000AFFFF, 1, INTD, 0 }, + Package(){0x000AFFFF, 2, INTA, 0 }, + Package(){0x000AFFFF, 3, INTB, 0 }, + + Package(){0x000BFFFF, 0, INTD, 0 }, + Package(){0x000BFFFF, 1, INTA, 0 }, + Package(){0x000BFFFF, 2, INTB, 0 }, + Package(){0x000BFFFF, 3, INTC, 0 }, + + Package(){0x000CFFFF, 0, INTA, 0 }, + Package(){0x000CFFFF, 1, INTB, 0 }, + Package(){0x000CFFFF, 2, INTC, 0 }, + Package(){0x000CFFFF, 3, INTD, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Package(){0x0014FFFF, 1, INTA, 0 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + /* Package(){0x0012FFFF, 2, 0, 18 }, */ + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + /* Package(){0x0013FFFF, 2, 0, 16 }, */ + + /* Package(){0x00140000, 0, 0, 16 }, */ + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl new file mode 100644 index 0000000..bd4acf0 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/south_station/acpi/usb.asl b/src/mainboard/amd/south_station/acpi/usb.asl new file mode 100644 index 0000000..181d685 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi/usb.asl @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c new file mode 100644 index 0000000..2a299d8 --- /dev/null +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include +#include + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 + +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; +extern const unsigned char AmlCode_ssdt[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FDAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + ssdt = (acpi_header_t *) current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + char *position = ssdt; + if (memcmp(position + 50, "TOM1", 4) == 0) + *(u32 *)(position + 55) = __readmsr(0xc001001a); + + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c new file mode 100644 index 0000000..74aa73d --- /dev/null +++ b/src/mainboard/amd/south_station/agesawrapper.c @@ -0,0 +1,541 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include +#include +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" +#include + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define MMCONF_ENABLE 1 + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; // last address before non-posted range + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } + + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000ull; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; + } + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + /* Write to D1F0x18 */ + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x00010100; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Legacy Bridge Mode + * Modify B1D5F0x18 + */ + PciAddress.Address.Bus = 1; + PciAddress.Address.Device = 5; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Legacy Bridge Mode + * Modify B1D5F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Pcie Mode + * Modify B0D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Pcie Mode + * Modify B0D1F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Base and Limit Address + * Modify B0D1F0x20 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x20; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96009600; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Prefetchable Memory Limit and Base + * Modify B0D1F0x24 + */ + PciAddress.Address.Register = 0x24; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x8FF18001; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; + + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdreadeventlog ( + VOID + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/south_station/agesawrapper.h b/src/mainboard/amd/south_station/agesawrapper.h new file mode 100644 index 0000000..f8d924e --- /dev/null +++ b/src/mainboard/amd/south_station/agesawrapper.h @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); + +UINT32 agesawrapper_amdreadeventlog (void); + +UINT32 agesawrapper_amdinitcpuio (void); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +void *agesawrapper_getlateinitptr (int pick); + +#endif diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c new file mode 100644 index 0000000..48e18a6 --- /dev/null +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -0,0 +1,458 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + */ + +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + +/* + * Agesa entry points used in this implementation. + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE//TRUE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" +#include "CommonReturns.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +//DA Customer table +CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + + diff --git a/src/mainboard/amd/south_station/chip.h b/src/mainboard/amd/south_station/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/amd/south_station/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout new file mode 100644 index 0000000..8315401 --- /dev/null +++ b/src/mainboard/amd/south_station/cmos.layout @@ -0,0 +1,118 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb new file mode 100644 index 0000000..f0b471a --- /dev/null +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -0,0 +1,105 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family14/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM +## chip drivers/generic/generic #dimm 0-0-0 +## device i2c 50 on end +## end +## chip drivers/generic/generic #dimm 0-0-1 +## device i2c 51 on end +## end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family14/root_complex + diff --git a/src/mainboard/amd/south_station/dimmSpd.c b/src/mainboard/amd/south_station/dimmSpd.c new file mode 100644 index 0000000..9da0e0e --- /dev/null +++ b/src/mainboard/amd/south_station/dimmSpd.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*#pragma optimize ("", off) // for source level debug +*--------------------------------------------------------------------------- +* +* SPD address table - porting required +*/ + +static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm + { + // socket 0 + { + {0xA0, 0xA2}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + // socket 1 + { + {0x00, 0x00}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + }; + +/*----------------------------------------------------------------------------- + * + * readSmbusByteData - read a single SPD byte from any offset + */ + +static int readSmbusByteData (int iobase, int address, char *buffer, int offset) + { + unsigned int status; + UINT64 limit; + + address |= 1; // set read bit + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command + + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; + } + +/*----------------------------------------------------------------------------- + * + * readSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + */ + +static int readSmbusByte (int iobase, int address, char *buffer) + { + unsigned int status; + UINT64 limit; + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; + } + +/*--------------------------------------------------------------------------- + * + * readspd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ + +static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) + { + int index, error; + + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; + + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) + { + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } + + return 0; + } + +static void writePmReg (int reg, int data) + { + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); + } + +static void setupFch (int ioBase) + { + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + writePmReg (0x29, 0x80); + writePmReg (0x28, 0x61); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + } + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) + { + int spdAddress, ioBase; + + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + ioBase = 0xB00; + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); + } diff --git a/src/mainboard/amd/south_station/dimmSpd.h b/src/mainboard/amd/south_station/dimmSpd.h new file mode 100644 index 0000000..069c34a --- /dev/null +++ b/src/mainboard/amd/south_station/dimmSpd.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl new file mode 100644 index 0000000..c4b69bd --- /dev/null +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -0,0 +1,1806 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "SOUTHSTN", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x808, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PIRA) + Store(0, PIRB) + Store(0, PIRC) + Store(0, PIRD) + Store(0, PIRE) + Store(0, PIRF) + Store(0, PIRG) + Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#if 0 + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#endif + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ +#if 0 + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PEBM + ) +#endif + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ +#if 0 + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * Subtract(TOM2, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } +#endif + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ +#if 0 + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +#endif +} +/* End of ASL file */ diff --git a/src/mainboard/amd/south_station/fadt.c b/src/mainboard/amd/south_station/fadt.c new file mode 100644 index 0000000..020d011 --- /dev/null +++ b/src/mainboard/amd/south_station/fadt.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + + +#include +#include +#include +#include +#include +#include "SBPLATFORM.h" + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + u16 val = 0; + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + val = PM1_EVT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); + val = PM1_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); + val = PM1_TMR_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); + val = GPE0_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + val = CPU_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); + val = 0; + WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); + val = ACPI_PMA_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val); + + /* AcpiDecodeEnable, When set, SB uses the contents of the + * PM registers at index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + val = BIT0 | BIT1 | BIT2 | BIT4; + WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c new file mode 100644 index 0000000..4bc5b48 --- /dev/null +++ b/src/mainboard/amd/south_station/get_bus_conf.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif + + +/* Global variables for MB layouts and these will be shared by irqtable mptable +* and acpi_tables busnum is default. +*/ +u8 bus_isa; +u8 bus_sb800[3]; +u32 apicid_sb800; + +/* +* Here you only need to set value in pci1234 for HT-IO that could be installed or not +* You may need to preset pci1234 for HTIO board, +* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +*/ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_sb800; + +static u32 get_bus_conf_done = 0; + + +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + +/* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + + sbdn_sb800 = 0; + + for (i = 0; i < 3; i++) { + bus_sb800[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + + bus_type[0] = 1; /* pci */ + +// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + + /* sb800 */ + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + + + + if (dev) { + bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb800[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + if (dev) { + bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sb800[2]; j < bus_isa; j++) + bus_type[j] = 1; + + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_sb800 = apicid_base; + +#if CONFIG_AMD_SB_CIMX + sb_Late_Post(); +#endif +} diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c new file mode 100644 index 0000000..28432dd --- /dev/null +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sb800[2]; +extern unsigned long sbdn_sb800; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb800[0]; + pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c new file mode 100644 index 0000000..990c8b9 --- /dev/null +++ b/src/mainboard/amd/south_station/mainboard.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "chip.h" + +uint64_t uma_memory_base, uma_memory_size; + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + +/** + * Southstation using SB GPIO 17/18 to control the Red/Green LED + * These two LEDs can be used to show the OS booting status. + */ +static void southstation_led_init(void) +{ +#define GPIO_FUNCTION 2 //GPIO function +#define SB_GPIO_REG17 17 //Red Light +#define SB_GPIO_REG18 18 //Green Light + + /* multi-function pins switch to GPIO0-35 */ + RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); + + /* select IOMux to function2, corresponds to GPIO */ + RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); + RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); + + /* Lighting test */ + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08); + mdelay(100); + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48); +} + + +/************************************************* +* enable the dedicated function in southstation board. +*************************************************/ +static void southstation_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + uint32_t sys_mem; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 0x10000000; /* 256M recommended UMA */ + uma_memory_base = 0x30000000; /* 1GB system memory supported */ +#endif + southstation_led_init(); +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = southstation_enable, +}; diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c new file mode 100644 index 0000000..a3b4b5c --- /dev/null +++ b/src/mainboard/amd/south_station/mptable.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +extern u8 bus_sb800[2]; + +extern u32 apicid_sb800; + +extern u32 bus_type[256]; +extern u32 sbdn_sb800; + +u8 intr_data[] = { + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + get_bus_conf(); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + + u32 dword; + u8 byte; + + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + dword &= 0xFFFFFFF0; + smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#if CONFIG_GENERATE_ACPI_TABLES == 0 +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif + + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + /* HD Audio: */ + PCI_INT(0x0, 0x14, 0x2, 0x12); + + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); + PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); + PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h new file mode 100644 index 0000000..66aab8b --- /dev/null +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _PERSIMMON_CFG_H_ +#define _PERSIMMON_CFG_H_ + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 + #define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 + #define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 + #define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 + #define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +#endif diff --git a/src/mainboard/amd/south_station/reset.c b/src/mainboard/amd/south_station/reset.c new file mode 100644 index 0000000..36bc6e0 --- /dev/null +++ b/src/mainboard/amd/south_station/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c new file mode 100644 index 0000000..95f27bd --- /dev/null +++ b/src/mainboard/amd/south_station/romstage.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include "cpu/x86/bist.h" +#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "sb_cimx.h" +#include "SBPLATFORM.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + __writemsr (0xc0010062, 0); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x35); + val = agesawrapper_amdinitmmio(); + + post_code(0x37); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + + post_code(0x38); + printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + + post_code(0x39); + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + + post_code(0x50); + copy_and_run(0); + + post_code(0x54); // Should never see this post code. +} + From gerrit at coreboot.org Tue Nov 15 13:54:01 2011 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 15 Nov 2011 13:54:01 +0100 Subject: [coreboot] Patch set updated for coreboot: ac9431d mainboard: Add AMD unionstation RDK support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/434 -gerrit commit ac9431d26ba477811c2e27c8ee1a70109ca671fb Author: Kerry Sheh Date: Tue Nov 15 21:27:57 2011 +0800 mainboard: Add AMD unionstation RDK support AMD unionstation Reference Design Kit is Designed for hd settop box application. This platform using family14 APU, SB800 southbridge. Vgabios is required, can download vgabios from AMD NDA website. Verified Feature: HDMI, LAN, mini-pcie slots, sata, usb, analog audio and optical fiber digital audio output. Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c Signed-off-by: Kerry She Signed-off-by: Kerry She --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/union_station/BiosCallOuts.c | 614 +++++++ src/mainboard/amd/union_station/BiosCallOuts.h | 80 + src/mainboard/amd/union_station/Kconfig | 135 ++ src/mainboard/amd/union_station/Makefile.inc | 34 + src/mainboard/amd/union_station/OptionsIds.h | 64 + src/mainboard/amd/union_station/PlatformGnbPcie.c | 168 ++ .../amd/union_station/PlatformGnbPcieComplex.h | 72 + src/mainboard/amd/union_station/acpi/cpstate.asl | 75 + src/mainboard/amd/union_station/acpi/ide.asl | 244 +++ src/mainboard/amd/union_station/acpi/routing.asl | 398 +++++ src/mainboard/amd/union_station/acpi/sata.asl | 149 ++ src/mainboard/amd/union_station/acpi/usb.asl | 161 ++ src/mainboard/amd/union_station/acpi_tables.c | 248 +++ src/mainboard/amd/union_station/agesawrapper.c | 541 ++++++ src/mainboard/amd/union_station/agesawrapper.h | 90 + src/mainboard/amd/union_station/buildOpts.c | 458 +++++ src/mainboard/amd/union_station/chip.h | 23 + src/mainboard/amd/union_station/cmos.layout | 118 ++ src/mainboard/amd/union_station/devicetree.cb | 105 ++ src/mainboard/amd/union_station/dimmSpd.c | 166 ++ src/mainboard/amd/union_station/dimmSpd.h | 63 + src/mainboard/amd/union_station/dsdt.asl | 1806 ++++++++++++++++++++ src/mainboard/amd/union_station/fadt.c | 194 +++ src/mainboard/amd/union_station/get_bus_conf.c | 138 ++ src/mainboard/amd/union_station/irq_tables.c | 122 ++ src/mainboard/amd/union_station/mainboard.c | 117 ++ src/mainboard/amd/union_station/mptable.c | 158 ++ src/mainboard/amd/union_station/platform_cfg.h | 230 +++ src/mainboard/amd/union_station/reset.c | 66 + src/mainboard/amd/union_station/romstage.c | 107 ++ 31 files changed, 6947 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index f9c406e..62ae584 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -33,6 +33,8 @@ config BOARD_AMD_SOUTHSTATION bool "Southstation" config BOARD_AMD_TORPEDO bool "Torpedo" +config BOARD_AMD_UNIONSTATION + bool "Unionstation" endchoice source "src/mainboard/amd/db800/Kconfig" @@ -50,6 +52,7 @@ source "src/mainboard/amd/inagua/Kconfig" source "src/mainboard/amd/persimmon/Kconfig" source "src/mainboard/amd/south_station/Kconfig" source "src/mainboard/amd/torpedo/Kconfig" +source "src/mainboard/amd/union_station/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c new file mode 100644 index 0000000..3fb0e87 --- /dev/null +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -0,0 +1,614 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "BiosCallOuts.h" +#include "heapManager.h" +#include "SB800.h" + +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset + }, + + {AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, + + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + CalloutStatus = AGESA_UNSUPPORTED; + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + return CalloutStatus; + } + } + + return CalloutStatus; +} + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; + + FcnData = Data; + MemData = ConfigPtr; + + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + switch(MemData->ParameterListPtr->DDR3Voltage){ + case VOLT1_35: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_25: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_5: + default: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + } + return Status; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 4: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + } + break; + case 6: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + } + break; + case 7: + switch (ResetInfo->ResetControl) + { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; +} diff --git a/src/mainboard/amd/union_station/BiosCallOuts.h b/src/mainboard/amd/union_station/BiosCallOuts.h new file mode 100644 index 0000000..b187fa2 --- /dev/null +++ b/src/mainboard/amd/union_station/BiosCallOuts.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define REQUIRED_CALLOUTS 12 +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig new file mode 100644 index 0000000..db0d1e4 --- /dev/null +++ b/src/mainboard/amd/union_station/Kconfig @@ -0,0 +1,135 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_UNIONSTATION + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_FINTEK_F81865F + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_2048 + select TINY_BOOTBLOCK + select GFXUMA + select UDELAY_LAPIC + +config AMD_AGESA + bool + default y + +config MAINBOARD_DIR + string + default amd/union_station + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Unionstation" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config SIO_PORT + hex + default 0x4e + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n +config VGA_BIOS_FILE + string + default "site-local/vgabios.bin" + +config VGA_BIOS_ID + string + default "1002,9802" + +config DRIVERS_PS2_KEYBOARD + bool + default n + +config WARNINGS_ARE_ERRORS + bool + default n + +endif # BOARD_AMD_UNIONSTATION + diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc new file mode 100644 index 0000000..1cb32b3 --- /dev/null +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -0,0 +1,34 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c + +ramstage-y += reset.c + +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14 diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h new file mode 100644 index 0000000..028d58f --- /dev/null +++ b/src/mainboard/amd/union_station/OptionsIds.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c new file mode 100644 index 0000000..59d31ef --- /dev/null +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + }, + #if 1 + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + }, + #endif + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeDP, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } +}; + +PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (BrazosPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 5, + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 2, + &InitEarly->StdHeader); + + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; +} + diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..f35d8db --- /dev/null +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/union_station/acpi/cpstate.asl b/src/mainboard/amd/union_station/acpi/cpstate.asl new file mode 100644 index 0000000..5eca9cc --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/union_station/acpi/ide.asl b/src/mainboard/amd/union_station/acpi/ide.asl new file mode 100644 index 0000000..c79c18c --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl new file mode 100644 index 0000000..cb50394 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/routing.asl @@ -0,0 +1,398 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + Package(){0x0009FFFF, 0, INTB, 0 }, + Package(){0x0009FFFF, 1, INTC, 0 }, + Package(){0x0009FFFF, 2, INTD, 0 }, + Package(){0x0009FFFF, 3, INTA, 0 }, + + Package(){0x000AFFFF, 0, INTC, 0 }, + Package(){0x000AFFFF, 1, INTD, 0 }, + Package(){0x000AFFFF, 2, INTA, 0 }, + Package(){0x000AFFFF, 3, INTB, 0 }, + + Package(){0x000BFFFF, 0, INTD, 0 }, + Package(){0x000BFFFF, 1, INTA, 0 }, + Package(){0x000BFFFF, 2, INTB, 0 }, + Package(){0x000BFFFF, 3, INTC, 0 }, + + Package(){0x000CFFFF, 0, INTA, 0 }, + Package(){0x000CFFFF, 1, INTB, 0 }, + Package(){0x000CFFFF, 2, INTC, 0 }, + Package(){0x000CFFFF, 3, INTD, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Package(){0x0014FFFF, 1, INTA, 0 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + /* Package(){0x0012FFFF, 2, 0, 18 }, */ + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + /* Package(){0x0013FFFF, 2, 0, 16 }, */ + + /* Package(){0x00140000, 0, 0, 16 }, */ + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/amd/union_station/acpi/sata.asl b/src/mainboard/amd/union_station/acpi/sata.asl new file mode 100644 index 0000000..bd4acf0 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/union_station/acpi/usb.asl b/src/mainboard/amd/union_station/acpi/usb.asl new file mode 100644 index 0000000..181d685 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi/usb.asl @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c new file mode 100644 index 0000000..2a299d8 --- /dev/null +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include +#include + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 + +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; +extern const unsigned char AmlCode_ssdt[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FDAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + ssdt = (acpi_header_t *) current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + char *position = ssdt; + if (memcmp(position + 50, "TOM1", 4) == 0) + *(u32 *)(position + 55) = __readmsr(0xc001001a); + + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c new file mode 100644 index 0000000..74aa73d --- /dev/null +++ b/src/mainboard/amd/union_station/agesawrapper.c @@ -0,0 +1,541 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include +#include +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" +#include + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define MMCONF_ENABLE 1 + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; // last address before non-posted range + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } + + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000ull; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; + } + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + /* Write to D1F0x18 */ + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x00010100; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Legacy Bridge Mode + * Modify B1D5F0x18 + */ + PciAddress.Address.Bus = 1; + PciAddress.Address.Device = 5; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Legacy Bridge Mode + * Modify B1D5F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Pcie Mode + * Modify B0D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Pcie Mode + * Modify B0D1F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Base and Limit Address + * Modify B0D1F0x20 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x20; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96009600; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Prefetchable Memory Limit and Base + * Modify B0D1F0x24 + */ + PciAddress.Address.Register = 0x24; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x8FF18001; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; + + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdreadeventlog ( + VOID + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/union_station/agesawrapper.h b/src/mainboard/amd/union_station/agesawrapper.h new file mode 100644 index 0000000..f8d924e --- /dev/null +++ b/src/mainboard/amd/union_station/agesawrapper.h @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); + +UINT32 agesawrapper_amdreadeventlog (void); + +UINT32 agesawrapper_amdinitcpuio (void); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +void *agesawrapper_getlateinitptr (int pick); + +#endif diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c new file mode 100644 index 0000000..48e18a6 --- /dev/null +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -0,0 +1,458 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + */ + +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE + +/* + * Agesa entry points used in this implementation. + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE//TRUE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 + +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" +#include "CommonReturns.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + +/* Include the files that instantiate the configuration definitions. */ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +//DA Customer table +CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + + diff --git a/src/mainboard/amd/union_station/chip.h b/src/mainboard/amd/union_station/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/amd/union_station/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout new file mode 100644 index 0000000..8315401 --- /dev/null +++ b/src/mainboard/amd/union_station/cmos.layout @@ -0,0 +1,118 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb new file mode 100644 index 0000000..f0b471a --- /dev/null +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -0,0 +1,105 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family14/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge + + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM +## chip drivers/generic/generic #dimm 0-0-0 +## device i2c 50 on end +## end +## chip drivers/generic/generic #dimm 0-0-1 +## device i2c 51 on end +## end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 +# These seem unnecessary + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family14/root_complex + diff --git a/src/mainboard/amd/union_station/dimmSpd.c b/src/mainboard/amd/union_station/dimmSpd.c new file mode 100644 index 0000000..9da0e0e --- /dev/null +++ b/src/mainboard/amd/union_station/dimmSpd.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*#pragma optimize ("", off) // for source level debug +*--------------------------------------------------------------------------- +* +* SPD address table - porting required +*/ + +static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm + { + // socket 0 + { + {0xA0, 0xA2}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + // socket 1 + { + {0x00, 0x00}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, + }; + +/*----------------------------------------------------------------------------- + * + * readSmbusByteData - read a single SPD byte from any offset + */ + +static int readSmbusByteData (int iobase, int address, char *buffer, int offset) + { + unsigned int status; + UINT64 limit; + + address |= 1; // set read bit + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command + + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; + } + +/*----------------------------------------------------------------------------- + * + * readSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + */ + +static int readSmbusByte (int iobase, int address, char *buffer) + { + unsigned int status; + UINT64 limit; + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; + } + +/*--------------------------------------------------------------------------- + * + * readspd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ + +static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) + { + int index, error; + + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; + + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) + { + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } + + return 0; + } + +static void writePmReg (int reg, int data) + { + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); + } + +static void setupFch (int ioBase) + { + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + writePmReg (0x29, 0x80); + writePmReg (0x28, 0x61); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + } + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) + { + int spdAddress, ioBase; + + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + ioBase = 0xB00; + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); + } diff --git a/src/mainboard/amd/union_station/dimmSpd.h b/src/mainboard/amd/union_station/dimmSpd.h new file mode 100644 index 0000000..069c34a --- /dev/null +++ b/src/mainboard/amd/union_station/dimmSpd.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl new file mode 100644 index 0000000..04952d3 --- /dev/null +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -0,0 +1,1806 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "UNIONSTN", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x808, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PIRA) + Store(0, PIRB) + Store(0, PIRC) + Store(0, PIRD) + Store(0, PIRE) + Store(0, PIRF) + Store(0, PIRG) + Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#if 0 + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#endif + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ +#if 0 + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PEBM + ) +#endif + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ +#if 0 + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * Subtract(TOM2, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } +#endif + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ +#if 0 + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +#endif +} +/* End of ASL file */ diff --git a/src/mainboard/amd/union_station/fadt.c b/src/mainboard/amd/union_station/fadt.c new file mode 100644 index 0000000..020d011 --- /dev/null +++ b/src/mainboard/amd/union_station/fadt.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + + +#include +#include +#include +#include +#include +#include "SBPLATFORM.h" + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + u16 val = 0; + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + val = PM1_EVT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); + val = PM1_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); + val = PM1_TMR_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); + val = GPE0_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + val = CPU_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); + val = 0; + WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); + val = ACPI_PMA_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val); + + /* AcpiDecodeEnable, When set, SB uses the contents of the + * PM registers at index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + val = BIT0 | BIT1 | BIT2 | BIT4; + WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c new file mode 100644 index 0000000..4bc5b48 --- /dev/null +++ b/src/mainboard/amd/union_station/get_bus_conf.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif + + +/* Global variables for MB layouts and these will be shared by irqtable mptable +* and acpi_tables busnum is default. +*/ +u8 bus_isa; +u8 bus_sb800[3]; +u32 apicid_sb800; + +/* +* Here you only need to set value in pci1234 for HT-IO that could be installed or not +* You may need to preset pci1234 for HTIO board, +* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +*/ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_sb800; + +static u32 get_bus_conf_done = 0; + + +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + +/* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + + sbdn_sb800 = 0; + + for (i = 0; i < 3; i++) { + bus_sb800[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + + bus_type[0] = 1; /* pci */ + +// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + + /* sb800 */ + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + + + + if (dev) { + bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb800[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + if (dev) { + bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sb800[2]; j < bus_isa; j++) + bus_type[j] = 1; + + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_sb800 = apicid_base; + +#if CONFIG_AMD_SB_CIMX + sb_Late_Post(); +#endif +} diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c new file mode 100644 index 0000000..28432dd --- /dev/null +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sb800[2]; +extern unsigned long sbdn_sb800; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb800[0]; + pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c new file mode 100644 index 0000000..800d64d --- /dev/null +++ b/src/mainboard/amd/union_station/mainboard.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "chip.h" + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void) +{ +} + +/** + * TODO + * mainboard specific SB CIMx callback + */ +void set_pcie_dereset(void) +{ +} + +uint64_t uma_memory_base, uma_memory_size; + +/************************************************* +* enable the dedicated function in unionstation board. +*************************************************/ +static void unionstation_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + uint32_t sys_mem; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 0x10000000; /* 256M recommended UMA */ + uma_memory_base = 0x30000000; /* 1GB system memory supported */ +#endif + +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = unionstation_enable, +}; diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c new file mode 100644 index 0000000..a3b4b5c --- /dev/null +++ b/src/mainboard/amd/union_station/mptable.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +extern u8 bus_sb800[2]; + +extern u32 apicid_sb800; + +extern u32 bus_type[256]; +extern u32 sbdn_sb800; + +u8 intr_data[] = { + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + get_bus_conf(); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + + u32 dword; + u8 byte; + + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + dword &= 0xFFFFFFF0; + smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#if CONFIG_GENERATE_ACPI_TABLES == 0 +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif + + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + /* HD Audio: */ + PCI_INT(0x0, 0x14, 0x2, 0x12); + + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); + PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); + PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + + /* PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h new file mode 100644 index 0000000..66aab8b --- /dev/null +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _PERSIMMON_CFG_H_ +#define _PERSIMMON_CFG_H_ + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 + #define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 + #define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 + #define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 + #define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CONFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#define SATA_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_MODE CONFIG_SB800_SATA_MODE + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#define SATA_IDE_MODE IDE_LEGACY_MODE + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#define AZALIA_CONTROLLER AZALIA_AUTO + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#define AZALIA_PIN_CONFIG 1 + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A + +/** + * @def GPP_CONTROLLER + */ +#define GPP_CONTROLLER CIMX_OPTION_ENABLED + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#define GPP_CFGMODE GPP_CFGMODE_X1111 + +/** + * @def NB_SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define NB_SB_GEN2 TRUE + +/** + * @def SB_GEN2 + * 0 - Disable + * 1 - Enable + */ +#define SB_GPP_GEN2 TRUE + +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE + +/** + * @def GEC_CONFIG + * 0 - Enable + * 1 - Disable + */ +#define GEC_CONFIG 0 + +#endif diff --git a/src/mainboard/amd/union_station/reset.c b/src/mainboard/amd/union_station/reset.c new file mode 100644 index 0000000..36bc6e0 --- /dev/null +++ b/src/mainboard/amd/union_station/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c new file mode 100644 index 0000000..e7f05e8 --- /dev/null +++ b/src/mainboard/amd/union_station/romstage.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include "cpu/x86/bist.h" +#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "sb_cimx.h" +#include "SBPLATFORM.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + sb_Poweron_Init(); + + post_code(0x31); + f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x35); + val = agesawrapper_amdinitmmio(); + + post_code(0x37); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + + post_code(0x38); + printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + + post_code(0x39); + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + + post_code(0x50); + copy_and_run(0); + + post_code(0x54); // Should never see this post code. +} + From christian.suehs at online.de Tue Nov 15 19:05:42 2011 From: christian.suehs at online.de (Christian) Date: Tue, 15 Nov 2011 19:05:42 +0100 Subject: [coreboot] Read resources faild on MS-6159 / i440LX northbridge In-Reply-To: <1320948331.7307.14.camel@dance-or-die3.athome.de> References: <1320948331.7307.14.camel@dance-or-die3.athome.de> Message-ID: <1321380342.18712.13.camel@dance-or-die3.athome.de> Ok, I have put back the debug.c stuff for the i440lx chipset. Here is the result: coreboot-4.0-1853-gf285e04-dirty Mon Nov 14 21:02:02 CET 2011 starting... Northbridge prior to SDRAM init: PCI: 00:00.00 00: 86 80 80 71 06 00 90 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 04 00 00 83 00 00 00 01 00 00 00 00 00 00 00 00 60: 01 01 01 01 01 01 01 01 00 00 00 00 55 55 55 55 70: 00 10 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: c0 00 00 00 10 18 00 00 00 00 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 fd 03 20 0f 00 00 00 00 00 00 APBASE 000000a0 ******************* *** Here the first value is missing, because of compiler trouble ******************* Set register 0x to 0x84 readed 0x84 OK Set register 0x to 0xc3 readed 0xc3 OK Set register 0x to 0xff readed 0xff OK Set register 0x to 0xff readed 0xff OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x30 readed 0x30 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Northbridge atexit sdram set registers PCI: 00:00.00 00: 86 80 80 71 06 00 90 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 04 84 00 c3 00 ff ff 00 00 30 33 33 33 33 33 33 60: 00 00 00 00 00 00 00 00 00 00 00 00 55 55 55 55 70: 00 10 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: c0 00 00 00 10 18 00 00 00 00 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 fd 03 20 0f 00 00 00 00 00 00 DIMM00 rows: 01 rowsize: 10 modulesize: 0008 DRT ffff fffe DIMM01 rows: ff rowsize: ff modulesize: 0000 DIMM02 rows: ff rowsize: ff modulesize: 0000 DIMM03 rows: ff rowsize: ff modulesize: 0000 RAM Enable 1: Apply NOP RAM Enable 2: Precharge all RAM Enable 3: CBR RAM Enable 4: Mode register set RAM Enable 5: Normal operation RAM Enable 6: Enable refresh spd_enable_refresh: dramc = 0x01 Northbridge following SDRAM init: Loading image. Searching for fallback/coreboot_ram Check pci1002,4742.rom Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (278528 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-1853-gf285e04-dirty Mon Nov 14 21:02:02 CET 2011 booting... clocks_per_usec: 402 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:07.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 PCI: 00:14.0: enabled 0 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:07.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 PCI: 00:14.0: enabled 0 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/7180] ops PCI: 00:00.0 [8086/7180] enabled PCI: 00:01.0 [8086/7181] enabled PCI: 00:07.0 [8086/7110] bus ops PCI: 00:07.0 [8086/7110] enabled PCI: 00:07.1 [8086/7111] ops PCI: 00:07.1 [8086/7111] enabled PCI: 00:07.2 [8086/7112] ops PCI: 00:07.2 [8086/7112] enabled PCI: 00:07.3 [8086/7113] bus ops pwrmgt_enable: gpo default missing in devicetree.cb! PCI: 00:07.3 [8086/7113] enabled PCI: 00:14.0 [1274/1371] disabled PCI: 00:14.1, bad id 0x0 PCI: 00:14.2, bad id 0x0 PCI: 00:14.3, bad id 0x0 PCI: 00:14.4, bad id 0x0 PCI: 00:14.5, bad id 0x0 PCI: 00:14.6, bad id 0x0 PCI: 00:14.7, bad id 0x0 do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1002/4742] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:07.0 PNP: 03f0.0 enabled PNP: 03f0.1 enabled PNP: 03f0.2 enabled PNP: 03f0.3 enabled PNP: 03f0.5 enabled PNP: 03f0.7 enabled PNP: 03f0.8 enabled PNP: 03f0.a enabled scan_static_bus for PCI: 00:07.0 done scan_static_bus for PCI: 00:07.3 scan_static_bus for PCI: 00:07.3 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 *************************** And here it stops. What happens in this stage? Thanks for help. chris From r.marek at assembler.cz Tue Nov 15 20:28:06 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 15 Nov 2011 20:28:06 +0100 Subject: [coreboot] Read resources faild on MS-6159 / i440LX northbridge In-Reply-To: <1321380342.18712.13.camel@dance-or-die3.athome.de> References: <1320948331.7307.14.camel@dance-or-die3.athome.de> <1321380342.18712.13.camel@dance-or-die3.athome.de> Message-ID: <4EC2BD46.5020503@assembler.cz> Hi, If you deselect "GDB" support in debug menu, maybe the tracing will print out what it is executing. You just need to turn on tracing support in debug menu. Thanks Rudolf From christian.suehs at online.de Tue Nov 15 20:45:10 2011 From: christian.suehs at online.de (Christian) Date: Tue, 15 Nov 2011 20:45:10 +0100 Subject: [coreboot] Read resources faild on MS-6159 / i440LX northbridge In-Reply-To: <4EC2BD46.5020503@assembler.cz> References: <1320948331.7307.14.camel@dance-or-die3.athome.de> <1321380342.18712.13.camel@dance-or-die3.athome.de> <4EC2BD46.5020503@assembler.cz> Message-ID: <1321386310.18712.15.camel@dance-or-die3.athome.de> Am Dienstag, den 15.11.2011, 20:28 +0100 schrieb Rudolf Marek: > Hi, > > If you deselect "GDB" support in debug menu, maybe the tracing will print out I will try it tomorrow Thanks for the hint chris From patrick at georgi-clan.de Tue Nov 15 21:43:47 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Tue, 15 Nov 2011 21:43:47 +0100 Subject: [coreboot] [RFC] A more robust fallback system In-Reply-To: <20111115110735.GA9578@xivo-clients.proformatique.com> References: <20111115110735.GA9578@xivo-clients.proformatique.com> Message-ID: <4EC2CF03.4040309@georgi-clan.de> Hello No?, first, welcome to the coreboot community! Am 15.11.2011 12:07, schrieb No? Rubinstein: > system, by putting a 'fallback' Coreboot in the high, write-blocked part > of the boot ROM, and using the fallback mechanism already implemented in > Coreboot in order to fallback in case the user-flashed firmware does not > work. Why put the fallback in the high parts? The only reason I could find is that you intend to use a boot block protection scheme (as these provide protection only for some high region), but they usually cover only a rather small area - too small for coreboot. > found with the right name. That's why the fallback mechanism has to > search for the fallback image only in the high part of the RAM. That > requires modification of walkcbfs_asm and of cbfslib to be able to find > a file after an offset. > [...] > overwrite part of another file. On the contrary, when looking for a > fallback component, the file headers before the fallback offset should > not be trusted (that's the whole point), so the beginning of the ROM > should be entirely skipped. These two special cases can be dropped if fallback is aligned to the low end of the image: It's always encountered first, and the CBFS alignment data is protected, too. I'm snipping away your other proposals for now. The reason is that there are various projects out there that use coreboot and have safe updates on their agenda, and I'd rather have a complete set of constraints (eg. limitations due to flash chips that only provide boot block protection) before planning what to do about them. Patrick From wangqingpei at gmail.com Wed Nov 16 03:52:01 2011 From: wangqingpei at gmail.com (QingPei Wang) Date: Wed, 16 Nov 2011 10:52:01 +0800 Subject: [coreboot] Asus M4A785TD-V In-Reply-To: References: Message-ID: if the chips are the same as the M4A785TD-V has, And you have a programmer, you can use them. Best wishes QingPei Wang Phone: 86+018930528086 2011/11/15 Jes?s J. Guerrero Botella > El d?a 15 de noviembre de 2011 04:12, QingPei Wang > escribi?: > > hi, > > Since AMD785/710 are supported by coreboot for a long time. I guess > your > > board can run coreboot well. And more, M4A785TD-M and M4A785TD-V are > almost > > the same. Just try to use the bios of M4A785TD-M. > > Ok, I am reading docs. I know about this project since years ago, when > it was called linuxbios, but never dared (nor needed) to try it. If I > have more doubts I'll ask here on due time, but now I have a little > doubt. Is there any way to proceed safely other than backing up the > bios in a separate chip? If that's the only way I think I'll need to > buy one of those pdip 8-legged chips. I have lots of bioses that I > removed from other boards but none of this kind. > > Thank you :) > -- > Jes?s Guerrero Botella > -------------- next part -------------- An HTML attachment was scrubbed... URL: From svens at stackframe.org Wed Nov 16 09:05:29 2011 From: svens at stackframe.org (Sven Schnelle) Date: Wed, 16 Nov 2011 09:05:29 +0100 Subject: [coreboot] Lenovo T60p 8742 Y19 - Black screen In-Reply-To: References: Message-ID: <4EC36EC9.1050505@stackframe.org> Hi Matias, On 10/27/2011 01:12 AM, Matias Jose Seco wrote: > currently i'm trying to boot my laptop over the newly flashed > bios with coreboot, but actually, despite power button, leds and cd > player working properly i dont get any response from the display. you can download the coreboot Image i'm running on my T60p from http://stackframe.org/coreboot_t60p.rom, which should also run on your system. Did you extract and add a VGA BIOS image? Note that you have to capture the vgabios during runtime from Linux, because the Lenovo BIOS does some Table patching at boot to enable the LVDS (=TFT) Display port. You might also extract the VGA BIOS image from my coreboot.rom file: cbfstool coreboot_t60p.rom extract pci1003,71c4.rom vgabios.rom Regards, Sven From fijam at archlinux.us Wed Nov 16 17:06:21 2011 From: fijam at archlinux.us (JM) Date: Wed, 16 Nov 2011 17:06:21 +0100 Subject: [coreboot] Current status of WYSE S50 support Message-ID: Hello, I am interested in replacing the BIOS on WYSE S50 with coreboot. I have browsed the mailing list archives, however, some of the reports are a bit unclear. I'd appreciate if someone could shed some light on the following concerns of mine: 1. Does the board work after RAMBASE rework (i.e. is ticket #163 really fixed)? 2. Is the current support of this board sufficient to boot Linux? More specifically, I have come across some reports of broken vsa and acpi, is this still an issue? If so, how does the lack of those features affect normal Linux operation? 3. When booting Linux from USB using default manufacturer's BIOS the ATA port is being disabled. Is this a software or hardware limitation? In other words, if I boot from USB with coreboot/SeaBIOS would I have ATA enabled? 4. When I boot the Linux kernel with the default BIOS it occasionally hangs on initializing the PCI subsystem. Is this a result of a bug in vsa code (virtualized pci) or BIOS? Does the problem persist with coreboot/SeaBIOS and AMD's vsa? I noticed something called OpenVSA, does it support Geode GX? 5. Can I help in any way with the development not being a programmer? Thanks, JM From christian.suehs at online.de Wed Nov 16 19:24:43 2011 From: christian.suehs at online.de (Christian) Date: Wed, 16 Nov 2011 19:24:43 +0100 Subject: [coreboot] Read resources faild on MS-6159 / i440LX northbridge In-Reply-To: <4EC2BD46.5020503@assembler.cz> References: <1320948331.7307.14.camel@dance-or-die3.athome.de> <1321380342.18712.13.camel@dance-or-die3.athome.de> <4EC2BD46.5020503@assembler.cz> Message-ID: <1321467883.4498.3.camel@dance-or-die3.athome.de> > If you deselect "GDB" support in debug menu, maybe the tracing will print out > what it is executing. You just need to turn on tracing support in debug menu. > Ok, I have enabled tracing support and after read resources of PCI DOMAIN 0000 following happens: PCI_DOMAIN: 0000 read_resources bus 0 link: 0 ~0x00107c79(0x00104779) ~0x00107a98(0x00107c9e) ~0x001078c7(0x00107ac9) ~0x0010630e(0x001078ec) ~0x00106236(0x00106333) ~0x001062c7(0x0010633c) ~0x0010aae4(0x001063e5) ~0x00108738(0x001078fa) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00107658(0x00107908) ~0x00108738(0x0010767e) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x0010768c) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x00107695) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076a3) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x001076ac) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076bb) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x001078c7(0x00107ac9) ~0x0010630e(0x001078ec) ~0x00106236(0x00106333) ~0x001062c7(0x0010633c) ~0x0010aae4(0x001063e5) ~0x00108738(0x001078fa) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00107658(0x00107908) ~0x00108738(0x0010767e) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x0010768c) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x00107695) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076a3) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x001076ac) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076bb) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x001078c7(0x00107ac9) ~0x0010630e(0x001078ec) ~0x00106236(0x00106333) ~0x00106236(0x00106333) ~0x001062c7(0x0010633c) ~0x0010aae4(0x001063e5) ~0x00108738(0x001078fa) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00107658(0x00107908) ~0x00108738(0x0010767e) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x0010768c) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x00107695) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076a3) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x001076ac) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076bb) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x001078c7(0x00107ac9) ~0x0010630e(0x001078ec) ~0x00106236(0x00106333) ~0x00106236(0x00106333) ~0x001062c7(0x0010633c) ~0x0010aae4(0x001063e5) ~0x00108738(0x001078fa) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00107658(0x00107908) ~0x00108738(0x0010767e) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x0010768c) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x00107695) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076a3) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x001076ac) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076bb) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x001078c7(0x00107ac9) ~0x0010630e(0x001078ec) ~0x00106236(0x00106333) ~0x00106236(0x00106333) ~0x001062c7(0x0010633c) ~0x0010aae4(0x001063e5) ~0x00108738(0x001078fa) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00107658(0x00107908) ~0x00108738(0x0010767e) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x0010768c) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x00107695) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076a3) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x001076ac) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076bb) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x001078c7(0x00107ac9) ~0x0010630e(0x001078ec) ~0x00106236(0x00106333) ~0x00106236(0x00106333) ~0x001062c7(0x0010633c) ~0x0010aae4(0x001063e5) ~0x00108738(0x001078fa) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00107658(0x00107908) ~0x00108738(0x0010767e) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x0010768c) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x00107695) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076a3) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x001076ac) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076bb) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00106236(0x00107aeb) ~0x00106236(0x00107aeb) ~0x001076d9(0x00107caa) ~0x0010630e(0x001076fb) ~0x00106236(0x00106333) ~0x001062c7(0x0010633c) ~0x0010aae4(0x001063e5) ~0x00108738(0x00107706) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00107658(0x00107711) ~0x00108738(0x0010767e) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x0010768c) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x00107695) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076a3) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00108738(0x001076ac) ~0x001085f1(0x00108759) ~0x001085a0(0x00108658) ~0x001085a0(0x00108760) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00100f9a(0x00108772) ~0x00108849(0x001076bb) ~0x001085f1(0x0010886a) ~0x001085a0(0x00108658) ~0x001085a0(0x00108871) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00100dc4(0x0010888a) ~0x00106236(0x00107793) ~0x00106236(0x00107793) ~0x00107b02(0x00104779) ~0x00107b02(0x00104779) ~0x00107547(0x00107b35) ~0x00108689(0x0010756d) ~0x001085f1(0x001086aa) ~0x001085a0(0x00108658) ~0x001085a0(0x001086b1) ~0x001010d1(0x001086c2) ~0x001010d1(0x001086c2) ~0x001010d1(0x001086c2) ~0x00108790(0x0010757e) ~0x001085f1(0x001087bb) ~0x001085a0(0x00108658) ~0x001085a0(0x001087c2) ~0x00100ef7(0x001087d8) ~0x00100ef7(0x001087d8) ~0x00100ef7(0x001087d8) ~0x00108689(0x0010758d) ~0x001085f1(0x001086aa) ~0x001085a0(0x00108658) ~0x001085a0(0x001086b1) ~0x001010d1(0x001086c2) ~0x001010d1(0x001086c2) ~0x001010d1(0x001086c2) ~0x00108790(0x0010759b) ~0x001085f1(0x001087bb) ~0x001085a0(0x00108658) ~0x001085a0(0x001087c2) ~0x00100ef7(0x001087d8) ~0x00100ef7(0x001087d8) ~0x00100ef7(0x001087d8) I hope somebody can read this cryptic stuff :D chris From patrick at georgi-clan.de Wed Nov 16 21:50:59 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 16 Nov 2011 21:50:59 +0100 Subject: [coreboot] [RFC] A more robust fallback system In-Reply-To: <20111115234231.13f629a1@xilun> References: <20111115110735.GA9578@xivo-clients.proformatique.com> <4EC2CF03.4040309@georgi-clan.de> <20111115234231.13f629a1@xilun> Message-ID: <4EC42233.10201@georgi-clan.de> Am 15.11.2011 23:42, schrieb Guillaume Knispel: > We can't put the fallback at the beginning of the image because that > area can't be locked on the chip we are using. (SST25VF016B) Thanks! That was the missing part in your scenario. Most current chips support sector granularity (usually 4kb, sometimes rather weird combinations of different sizes). Current idea under consideration: Modify CBFS to work from top to bottom. That way, you could place all immutable data at the beginning of the chain (ie. top-most). That way all kind of headers, as well as fallback-versions of code, can be in the protected area. If updates fail, some mechanism (counter in nvram, jumper, ...) can be used to tell the bootblock to use the fallback version. Of course, this is a rather severe change, but actually not that hard in implementation: a couple of additions replaced by subtraction, and different exit conditions. As it also affects payload compatibility (libpayload and seabios at least), it requires some thought. The only option I see to lock down your system (given that chip) that won't change the format will introduce a much more complex CBFS evaluator: In the easiest case, it would walk the entire flash and return the _last_ occurrence of the requested file name. As it can't trust any file headers, it would have to look for headers in 16byte increments. That's not really a useful solution. ;-) Regards, Patrick From gerrit at coreboot.org Wed Nov 16 22:40:22 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 16 Nov 2011 22:40:22 +0100 Subject: [coreboot] Patch merged into coreboot/master: 4dbddae fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit References: Message-ID: the following patch was just integrated into master: commit 4dbddae0403b2cbe227820ee2dedf498f5f149e3 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Sat Nov 5 01:01:54 2011, giving +1 Reviewed-By: Rudolf Marek at Wed Nov 16 22:40:21 2011, giving +2 See http://review.coreboot.org/376 for details. -gerrit From r.marek at assembler.cz Thu Nov 17 00:29:40 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Thu, 17 Nov 2011 00:29:40 +0100 Subject: [coreboot] Read resources faild on MS-6159 / i440LX northbridge In-Reply-To: <1321467883.4498.3.camel@dance-or-die3.athome.de> References: <1320948331.7307.14.camel@dance-or-die3.athome.de> <1321380342.18712.13.camel@dance-or-die3.athome.de> <4EC2BD46.5020503@assembler.cz> <1321467883.4498.3.camel@dance-or-die3.athome.de> Message-ID: <4EC44764.5000904@assembler.cz> Hi, Check coreboot/util/genprof/README which I forgot to mention. There is a script which transforms that into human readable symbols. Just make sure the build directory contains what has been actually used to run it. Thanks Rudolf Function tracing ---------------- Enable CONFIG_TRACE in debug menu. Run the compiled image on target. You will get a log with a lot of lines like: ... ~0x001072e8(0x00100099) ~0x00108bc0(0x0010730a) ... First address is address of function which was just entered, the second address is address of functions which call that. You can use the log2dress to dress the log again: ... src/arch/x86/lib/c_start.S:85 calls /home/ruik/coreboot/src/boot/selfboot.c:367 /home/ruik/coreboot/src/boot/selfboot.c:370 calls /home/ruik/coreboot/src/devices/device.c:325 ... Alternatively, you can use genprof to generate a gmon.out file, which can be used by gprof to show the call traces. You will need to install uthash library to compile that. Great use is: make ./genprof /tmp/yourlog ; gprof ../../build/coreboot_ram | ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png Which generates a PNG with a call graph. On 16.11.2011 19:24, Christian wrote: > >> If you deselect "GDB" support in debug menu, maybe the tracing will print out >> what it is executing. You just need to turn on tracing support in debug menu. >> > > Ok, I have enabled tracing support and after read resources of > PCI DOMAIN 0000 following happens: > > > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 > ~0x00107c79(0x00104779) > ~0x00107a98(0x00107c9e) > ~0x001078c7(0x00107ac9) > ~0x0010630e(0x001078ec) > ~0x00106236(0x00106333) > ~0x001062c7(0x0010633c) > ~0x0010aae4(0x001063e5) > ~0x00108738(0x001078fa) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00107658(0x00107908) > ~0x00108738(0x0010767e) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x0010768c) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x00107695) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076a3) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x001076ac) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076bb) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x001078c7(0x00107ac9) > ~0x0010630e(0x001078ec) > ~0x00106236(0x00106333) > ~0x001062c7(0x0010633c) > ~0x0010aae4(0x001063e5) > ~0x00108738(0x001078fa) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00107658(0x00107908) > ~0x00108738(0x0010767e) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x0010768c) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x00107695) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076a3) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x001076ac) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076bb) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x001078c7(0x00107ac9) > ~0x0010630e(0x001078ec) > ~0x00106236(0x00106333) > ~0x00106236(0x00106333) > ~0x001062c7(0x0010633c) > ~0x0010aae4(0x001063e5) > ~0x00108738(0x001078fa) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00107658(0x00107908) > ~0x00108738(0x0010767e) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x0010768c) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x00107695) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076a3) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x001076ac) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076bb) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x001078c7(0x00107ac9) > ~0x0010630e(0x001078ec) > ~0x00106236(0x00106333) > ~0x00106236(0x00106333) > ~0x001062c7(0x0010633c) > ~0x0010aae4(0x001063e5) > ~0x00108738(0x001078fa) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00107658(0x00107908) > ~0x00108738(0x0010767e) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x0010768c) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x00107695) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076a3) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x001076ac) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076bb) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x001078c7(0x00107ac9) > ~0x0010630e(0x001078ec) > ~0x00106236(0x00106333) > ~0x00106236(0x00106333) > ~0x001062c7(0x0010633c) > ~0x0010aae4(0x001063e5) > ~0x00108738(0x001078fa) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00107658(0x00107908) > ~0x00108738(0x0010767e) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x0010768c) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x00107695) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076a3) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x001076ac) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076bb) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x001078c7(0x00107ac9) > ~0x0010630e(0x001078ec) > ~0x00106236(0x00106333) > ~0x00106236(0x00106333) > ~0x001062c7(0x0010633c) > ~0x0010aae4(0x001063e5) > ~0x00108738(0x001078fa) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00107658(0x00107908) > ~0x00108738(0x0010767e) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x0010768c) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x00107695) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076a3) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x001076ac) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076bb) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00106236(0x00107aeb) > ~0x00106236(0x00107aeb) > ~0x001076d9(0x00107caa) > ~0x0010630e(0x001076fb) > ~0x00106236(0x00106333) > ~0x001062c7(0x0010633c) > ~0x0010aae4(0x001063e5) > ~0x00108738(0x00107706) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00107658(0x00107711) > ~0x00108738(0x0010767e) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x0010768c) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x00107695) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076a3) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00108738(0x001076ac) > ~0x001085f1(0x00108759) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108760) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00100f9a(0x00108772) > ~0x00108849(0x001076bb) > ~0x001085f1(0x0010886a) > ~0x001085a0(0x00108658) > ~0x001085a0(0x00108871) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00100dc4(0x0010888a) > ~0x00106236(0x00107793) > ~0x00106236(0x00107793) > ~0x00107b02(0x00104779) > ~0x00107b02(0x00104779) > ~0x00107547(0x00107b35) > ~0x00108689(0x0010756d) > ~0x001085f1(0x001086aa) > ~0x001085a0(0x00108658) > ~0x001085a0(0x001086b1) > ~0x001010d1(0x001086c2) > ~0x001010d1(0x001086c2) > ~0x001010d1(0x001086c2) > ~0x00108790(0x0010757e) > ~0x001085f1(0x001087bb) > ~0x001085a0(0x00108658) > ~0x001085a0(0x001087c2) > ~0x00100ef7(0x001087d8) > ~0x00100ef7(0x001087d8) > ~0x00100ef7(0x001087d8) > ~0x00108689(0x0010758d) > ~0x001085f1(0x001086aa) > ~0x001085a0(0x00108658) > ~0x001085a0(0x001086b1) > ~0x001010d1(0x001086c2) > ~0x001010d1(0x001086c2) > ~0x001010d1(0x001086c2) > ~0x00108790(0x0010759b) > ~0x001085f1(0x001087bb) > ~0x001085a0(0x00108658) > ~0x001085a0(0x001087c2) > ~0x00100ef7(0x001087d8) > ~0x00100ef7(0x001087d8) > ~0x00100ef7(0x001087d8) > > I hope somebody can read this cryptic stuff :D > chris > From c-d.hailfinger.devel.2006 at gmx.net Thu Nov 17 00:13:35 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 17 Nov 2011 00:13:35 +0100 Subject: [coreboot] FOSDEM 2012 In-Reply-To: <4EBD5FE7.3050609@gmx.net> References: <4EBD5FE7.3050609@gmx.net> Message-ID: <4EC4439F.5020406@gmx.net> Call for lightning talks and stands is NOW! http://fosdem.org/2012/call-for-participation I will be at FOSDEM. Anybody else? Regards, Carl-Daniel Am 11.11.2011 18:48 schrieb Carl-Daniel Hailfinger: > Hey, > > it seems we forgot to apply for a devroom (well, at least I didn't see > anything on the mailing list). > Should we submit talks to the individual devrooms? > Should we ask for a coreboot/flashrom booth/table? > > Regards, > Carl-Daniel -- http://www.hailfinger.org/ From gknispel at proformatique.com Tue Nov 15 23:42:31 2011 From: gknispel at proformatique.com (Guillaume Knispel) Date: Tue, 15 Nov 2011 23:42:31 +0100 Subject: [coreboot] [RFC] A more robust fallback system In-Reply-To: <4EC2CF03.4040309@georgi-clan.de> References: <20111115110735.GA9578@xivo-clients.proformatique.com> <4EC2CF03.4040309@georgi-clan.de> Message-ID: <20111115234231.13f629a1@xilun> Hi, Following up about No? RFC, who I work with: On Tue, 15 Nov 2011 21:43:47 +0100 Patrick Georgi wrote: > > system, by putting a 'fallback' Coreboot in the high, write-blocked part > > of the boot ROM, and using the fallback mechanism already implemented in > > Coreboot in order to fallback in case the user-flashed firmware does not > > work. > Why put the fallback in the high parts? The only reason I could find is > that you intend to use a boot block protection scheme (as these provide > protection only for some high region), but they usually cover only a > rather small area - too small for coreboot. The upper area that we plan to store the safe code in would actually be the upper half of the flash, which can be soft-locked RO. That is big enough to contain a coreboot and even more. > > found with the right name. That's why the fallback mechanism has to > > search for the fallback image only in the high part of the RAM. That > > requires modification of walkcbfs_asm and of cbfslib to be able to find > > a file after an offset. > > [...] > > overwrite part of another file. On the contrary, when looking for a > > fallback component, the file headers before the fallback offset should > > not be trusted (that's the whole point), so the beginning of the ROM > > should be entirely skipped. > These two special cases can be dropped if fallback is aligned to the low > end of the image: It's always encountered first, and the CBFS alignment > data is protected, too. We can't put the fallback at the beginning of the image because that area can't be locked on the chip we are using. (SST25VF016B) > I'm snipping away your other proposals for now. The reason is that there > are various projects out there that use coreboot and have safe updates > on their agenda, and I'd rather have a complete set of constraints (eg. > limitations due to flash chips that only provide boot block protection) > before planning what to do about them. On our side, the essential requirement is that the fallback can be put in an upper area of the chip, because the lower area can't be locked (The SST25VF016B can lock its upper 1/32, 1/16, 1/8, 1/4 or 1/2 -- we were thinking about locking the whole upper half, maybe to switch at a late stage of FW development to something just large enough to fit what we need.) Our idea was that the owner should be allowed to write whatever CBFS image he wants in the unlocked area of the chip, without the need to first extract parameters from a protected header in his target board before using the same to build his own image, and without any impact on the behavior of the fallback image. So I think it would be better to have two clearly separated areas, maybe each one with its own header. If using only one header is mandatory, then it clearly must be in the protected area, which might not be possible to put at the bottom of the chip on some refs (like the SST25VF016B we are using). It definitely would be great to come with a general solution that works for everybody and is maintained for a long time in a compatible way in coreboot, because obviously we won't be able to change the structure easily in the field once they have been bumped in protected areas of deployed products, and we also would prefer not to maintain a patch set specific to our board on this subject forever... (we could put a jumper to disable the write protection, but because that could defeat the whole purpose of the protected fallback if misused, we are not yet sure, and we might end up with just an ISP header for those who really want to change the protected area). Cheers! Guillaume Knispel -- Avencall - 10 bis, rue Lucien Voilin - 92800 Puteaux Tel. : +33 141 389 960 From gknispel at proformatique.com Wed Nov 16 22:54:37 2011 From: gknispel at proformatique.com (Guillaume Knispel) Date: Wed, 16 Nov 2011 22:54:37 +0100 Subject: [coreboot] [RFC] A more robust fallback system In-Reply-To: <4EC42233.10201@georgi-clan.de> References: <20111115110735.GA9578@xivo-clients.proformatique.com> <4EC2CF03.4040309@georgi-clan.de> <20111115234231.13f629a1@xilun> <4EC42233.10201@georgi-clan.de> Message-ID: <20111116225437.002dca56@xilun> On Wed, 16 Nov 2011 21:50:59 +0100 Patrick Georgi wrote: > Am 15.11.2011 23:42, schrieb Guillaume Knispel: > > We can't put the fallback at the beginning of the image because that > > area can't be locked on the chip we are using. (SST25VF016B) > Thanks! That was the missing part in your scenario. Most current chips > support sector granularity (usually 4kb, sometimes rather weird > combinations of different sizes). > > Current idea under consideration: Modify CBFS to work from top to > bottom. That way, you could place all immutable data at the beginning of > the chain (ie. top-most). That way all kind of headers, as well as > fallback-versions of code, can be in the protected area. > If updates fail, some mechanism (counter in nvram, jumper, ...) can be > used to tell the bootblock to use the fallback version. I think the most useful thing for the long term would be to come up with data structures that allow use on all currently know chips, so in the future every tool will be standard and there won't be a sort of maintenance hell like "card X requires option Y during build of soft Z then don't forget to use the following offsets and order when building the cbfs image, and oh BTW here is a patch you should apply to your toolchain first -- and remember to configure T exactly the same way or they will be incompatible". It would also be more approachable for users who want to modify their firmware if we avoid that mess. > Of course, this is a rather severe change, but actually not that hard in > implementation: a couple of additions replaced by subtraction, and > different exit conditions. As it also affects payload compatibility > (libpayload and seabios at least), it requires some thought. I think if we are going to modify payload compatibility, the right way is to aim at a generic solution that would work well on all kind of chips. The advantage of having two clearly separated CBFS, one for the protected area and one for the rest is that it would be clean (no hack, no need to scan the whole chip, etc.), and would work with both chips protected in the lower and chips protected in the upper area. Also I think the CBFS structures would not need to be modified if there are only contiguous areas. We maybe even could manage to keep backward compatibility with older bootblocks (but they would not provide the same level of protection) and tools? Cheers, Guillaume Knispel -- Avencall - 10 bis, rue Lucien Voilin - 92800 Puteaux Tel. : (+33) 141 389 960 From christian.suehs at online.de Thu Nov 17 20:13:44 2011 From: christian.suehs at online.de (Christian) Date: Thu, 17 Nov 2011 20:13:44 +0100 Subject: [coreboot] Read resources faild on MS-6159 / i440LX northbridge In-Reply-To: <4EC44764.5000904@assembler.cz> References: <1320948331.7307.14.camel@dance-or-die3.athome.de> <1321380342.18712.13.camel@dance-or-die3.athome.de> <4EC2BD46.5020503@assembler.cz> <1321467883.4498.3.camel@dance-or-die3.athome.de> <4EC44764.5000904@assembler.cz> Message-ID: <1321557224.2449.4.camel@dance-or-die3.athome.de> Thank you > src/arch/x86/lib/c_start.S:85 calls /home/ruik/coreboot/src/boot/selfboot.c:367 > /home/ruik/coreboot/src/boot/selfboot.c:370 calls > /home/ruik/coreboot/src/devices/device.c:325 > ... here are the calls after PCI DOMAIN 0000 last lines /home/chris/coreboot/src/devices/pci_device.c:64 calls /home/chris/coreboot/src/devices/pci_ops.c:65 /home/chris/coreboot/src/devices/pci_ops.c:66 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:18 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:18 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:18 /home/chris/coreboot/src/devices/pci_device.c:65 calls /home/chris/coreboot/src/devices/pci_ops.c:86 /home/chris/coreboot/src/devices/pci_ops.c:87 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:36 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:36 full log after PCI DOMAIN 0000 attached chris -------------- next part -------------- /home/chris/coreboot/src/devices/device.c:132 calls /home/chris/coreboot/src/console/printk.c:19 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 /home/chris/coreboot/src/devices/device.c:146 calls /home/chris/coreboot/src/devices/pci_device.c:432 /home/chris/coreboot/src/devices/pci_device.c:434 calls /home/chris/coreboot/src/devices/pci_device.c:343 /home/chris/coreboot/src/devices/pci_device.c:350 calls /home/chris/coreboot/src/devices/pci_device.c:181 /home/chris/coreboot/src/devices/pci_device.c:190 calls /home/chris/coreboot/src/devices/device_util.c:373 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:381 calls /home/chris/coreboot/src/devices/device_util.c:350 /home/chris/coreboot/src/devices/device_util.c:389 calls /home/chris/coreboot/src/lib/memset.c:4 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_device.c:90 /home/chris/coreboot/src/devices/pci_device.c:95 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:96 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:98 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:99 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:350 calls /home/chris/coreboot/src/devices/pci_device.c:181 /home/chris/coreboot/src/devices/pci_device.c:190 calls /home/chris/coreboot/src/devices/device_util.c:373 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:381 calls /home/chris/coreboot/src/devices/device_util.c:350 /home/chris/coreboot/src/devices/device_util.c:389 calls /home/chris/coreboot/src/lib/memset.c:4 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_device.c:90 /home/chris/coreboot/src/devices/pci_device.c:95 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:96 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:98 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:99 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:350 calls /home/chris/coreboot/src/devices/pci_device.c:181 /home/chris/coreboot/src/devices/pci_device.c:190 calls /home/chris/coreboot/src/devices/device_util.c:373 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:381 calls /home/chris/coreboot/src/devices/device_util.c:350 /home/chris/coreboot/src/devices/device_util.c:389 calls /home/chris/coreboot/src/lib/memset.c:4 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_device.c:90 /home/chris/coreboot/src/devices/pci_device.c:95 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:96 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:98 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:99 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:350 calls /home/chris/coreboot/src/devices/pci_device.c:181 /home/chris/coreboot/src/devices/pci_device.c:190 calls /home/chris/coreboot/src/devices/device_util.c:373 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:381 calls /home/chris/coreboot/src/devices/device_util.c:350 /home/chris/coreboot/src/devices/device_util.c:389 calls /home/chris/coreboot/src/lib/memset.c:4 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_device.c:90 /home/chris/coreboot/src/devices/pci_device.c:95 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:96 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:98 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:99 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:350 calls /home/chris/coreboot/src/devices/pci_device.c:181 /home/chris/coreboot/src/devices/pci_device.c:190 calls /home/chris/coreboot/src/devices/device_util.c:373 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:381 calls /home/chris/coreboot/src/devices/device_util.c:350 /home/chris/coreboot/src/devices/device_util.c:389 calls /home/chris/coreboot/src/lib/memset.c:4 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_device.c:90 /home/chris/coreboot/src/devices/pci_device.c:95 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:96 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:98 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:99 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:350 calls /home/chris/coreboot/src/devices/pci_device.c:181 /home/chris/coreboot/src/devices/pci_device.c:190 calls /home/chris/coreboot/src/devices/device_util.c:373 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:381 calls /home/chris/coreboot/src/devices/device_util.c:350 /home/chris/coreboot/src/devices/device_util.c:389 calls /home/chris/coreboot/src/lib/memset.c:4 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:193 calls /home/chris/coreboot/src/devices/pci_device.c:90 /home/chris/coreboot/src/devices/pci_device.c:95 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:96 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:98 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:99 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:353 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/pci_device.c:353 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/pci_device.c:434 calls /home/chris/coreboot/src/devices/pci_device.c:292 /home/chris/coreboot/src/devices/pci_device.c:301 calls /home/chris/coreboot/src/devices/device_util.c:373 /home/chris/coreboot/src/devices/device_util.c:380 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device_util.c:381 calls /home/chris/coreboot/src/devices/device_util.c:350 /home/chris/coreboot/src/devices/device_util.c:389 calls /home/chris/coreboot/src/lib/memset.c:4 /home/chris/coreboot/src/devices/pci_device.c:301 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:315 calls /home/chris/coreboot/src/devices/pci_device.c:90 /home/chris/coreboot/src/devices/pci_device.c:95 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:96 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:98 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:99 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:79 /home/chris/coreboot/src/devices/pci_ops.c:80 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_ops.c:81 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:30 /home/chris/coreboot/src/devices/pci_device.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:100 /home/chris/coreboot/src/devices/pci_ops.c:101 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_ops.c:102 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:48 /home/chris/coreboot/src/devices/pci_device.c:333 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/pci_device.c:333 calls /home/chris/coreboot/src/devices/device_util.c:329 /home/chris/coreboot/src/devices/device.c:146 calls /home/chris/coreboot/src/devices/pci_device.c:438 /home/chris/coreboot/src/devices/device.c:146 calls /home/chris/coreboot/src/devices/pci_device.c:438 /home/chris/coreboot/src/devices/pci_device.c:389 calls /home/chris/coreboot/src/devices/pci_device.c:56 /home/chris/coreboot/src/devices/pci_device.c:61 calls /home/chris/coreboot/src/devices/pci_ops.c:65 /home/chris/coreboot/src/devices/pci_ops.c:66 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:18 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:18 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:18 /home/chris/coreboot/src/devices/pci_device.c:67 calls /home/chris/coreboot/src/devices/pci_ops.c:86 /home/chris/coreboot/src/devices/pci_ops.c:87 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:36 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:36 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:36 /home/chris/coreboot/src/devices/pci_device.c:64 calls /home/chris/coreboot/src/devices/pci_ops.c:65 /home/chris/coreboot/src/devices/pci_ops.c:66 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:18 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:18 /home/chris/coreboot/src/devices/pci_ops.c:67 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:18 /home/chris/coreboot/src/devices/pci_device.c:65 calls /home/chris/coreboot/src/devices/pci_ops.c:86 /home/chris/coreboot/src/devices/pci_ops.c:87 calls /home/chris/coreboot/src/devices/pci_ops.c:33 /home/chris/coreboot/src/devices/pci_ops.c:41 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/include/device/pci.h:95 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:36 /home/chris/coreboot/src/devices/pci_ops.c:88 calls /home/chris/coreboot/src/arch/x86/lib/pci_ops_conf1.c:36 From hamo.by at gmail.com Fri Nov 18 07:21:08 2011 From: hamo.by at gmail.com (Hamo) Date: Fri, 18 Nov 2011 14:21:08 +0800 Subject: [coreboot] [RFC] A more robust fallback system In-Reply-To: <20111115110735.GA9578@xivo-clients.proformatique.com> References: <20111115110735.GA9578@xivo-clients.proformatique.com> Message-ID: On Tue, Nov 15, 2011 at 7:07 PM, No? Rubinstein wrote: > Hi, > > This is an RFC. > > I'm currently working towards providing a more secure fallback mechanism > to Coreboot. ?I had pushed some preliminary changes to Gerrit some weeks > ago?, and I've tried to take the reviews in account. ?As the changes > touch some pretty critical parts of Coreboot, I'm sending this to the > mailing list for comments. ?The patches are not ready yet, and the > changes that have been made to CBFStool and TINY_BOOTBLOCK et al. > recently will prolly make the rebasing work non-trivial. > > On some chips, it is possible to block writing on some part of the ROM > when the system is running. ?We (at my company) plan to use that to > prevent a careless user updating or modifying their BIOS to brick their > system, by putting a 'fallback' Coreboot in the high, write-blocked part > of the boot ROM, and using the fallback mechanism already implemented in > Coreboot in order to fallback in case the user-flashed firmware does not > work. > > This requires an ability to specify that the components of a Coreboot > build have to be written in the high part of the ROM. ?As cbfstool > already supports setting the precise address at which a file must be > mapped in memory, this could be implemented completely in the build > system. ?However, this is non-trivial, so I really think it is better > for cbfstool to handle the calculations. > > However, if the user writes in the low part of the ROM a Coreboot build > with the "fallback" CBFS prefix (which is the default), the fallback > mechanism won't work, as it will always boot on the first component > found with the right name. ?That's why the fallback mechanism has to > search for the fallback image only in the high part of the RAM. ?That > requires modification of walkcbfs_asm and of cbfslib to be able to find > a file after an offset. > > In order to do this, we add a build option named OFFSET_IN_ROM which > defaults to 0x0 and enables putting Coreboot in the high part of the > ROM. ?OFFSET_IN_ROM is used in the build system to call cbfstool > (including in order to call link the romstage properly), and is used in > Coreboot itself as an argument to the CBFS search functions. > This method looks like the same as what I have done when dealing with different ARM boot rom address mapping. The different is that I also put this address into the master header so that other component or walk_cbfs can get it there. > Note that in order to write a component after an offset in cbfstool, the > whole beginning of the ROM has to be walked through in order not to > overwrite part of another file. ?On the contrary, when looking for a > fallback component, the file headers before the fallback offset should > not be trusted (that's the whole point), so the beginning of the ROM > should be entirely skipped. > > It is to be noted that this mechanism is still imperfect, as the CBFS > header is at the bottom of the ROM and holds info about file alignment > and offset. ?In order to prevent problems, the implementation should use > conservative values instead of those written in the CBFS header. > > I'm preparing a changeset implementing this mechanism. ?I should post it > to gerrit soon if the reactions to this RFC are positive. > > Later, we could implement a more robust solution would be storing > another CBFS header in the middle of the ROM; either completely > splitting the ROM in two or storing the second CBFS header as a CBFS > file. ?In both cases, that would require much more effort to implement > than the current proposal. > > Any idea/objection? > > Thanks in advance. > > ?: http://review.coreboot.org/284 > ? http://review.coreboot.org/285 > ? http://review.coreboot.org/286 > -- > No? Rubinstein > Avencall - XiVO IPBX Open Hardware > 10 bis, rue Lucien VOILIN - 92800 Puteaux > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From gerrit at coreboot.org Fri Nov 18 12:08:07 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 18 Nov 2011 12:08:07 +0100 Subject: [coreboot] Patch set updated for coreboot: c62ee4b Replace ramtest pattern to assist in DIMM configuration References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/294 -gerrit commit c62ee4b1f3f61d9913caa6cc54edc30fa85c99b8 Author: Ky?sti M?lkki Date: Fri Nov 18 12:38:37 2011 +0200 Replace ramtest pattern to assist in DIMM configuration This is developer's testtool. Output from a "rotate ones" -style pattern helps figure out how DIMM addresses are encoded or routed on a certain mainboard. Scattered test should cover every data and address lines on the memory bus, but is probably limited to the first bank of first DIMM. Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196 Signed-off-by: Ky?sti M?lkki --- src/lib/ramtest.c | 187 ++++++++++++++++++++++++++--------------------------- 1 files changed, 91 insertions(+), 96 deletions(-) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index b35c36d..e09d0d1 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -47,117 +47,118 @@ static void phys_memory_barrier(void) #endif } -static void ram_fill(unsigned long start, unsigned long stop) +/** + * Rotate ones test pattern that access every bit on a 128bit wide + * memory bus. To test most address lines, addresses are scattered + * using 256B, 4kB and 64kB increments. + * + * @idx Index to test pattern (0=> 8) + 1; + j = (idx >> 4) & 0x0f; + *addr = idx & 0x0f; + *addr |= j << (4*k); + *value = 0x01010101 << (j & 7); + if (j & 8) + *value = ~(*value); } -static void ram_verify(unsigned long start, unsigned long stop) +/** + * Simple write-read-verify memory test. See console debug output for + * any dislocated bytes. + * + * @start System memory offset, aligned to 128bytes + */ +static void ram_bitset(unsigned long start) { - unsigned long addr; - int i = 0; - /* - * Verify. - */ + unsigned long addr, value, value2; + unsigned short int idx; + unsigned char failed, failures; + uint8_t verbose = 0; + #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop); + printk(BIOS_DEBUG, "DRAM bitset write: 0x%08lx\n", start); #else - print_debug("DRAM verify: "); + print_debug("DRAM bitset write: 0x"); print_debug_hex32(start); - print_debug_char('-'); - print_debug_hex32(stop); print_debug("\n"); #endif - for(addr = start; addr < stop ; addr += 4) { - unsigned long value; - /* Display address being tested */ - if (!(addr & 0xfffff)) { + for (idx=0; idx<0x400; idx+=4) { + test_pattern(idx, &addr, &value); + write_phys(start + addr, value); + } + + /* Make sure we don't read before we wrote */ + phys_memory_barrier(); + #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%08lx \r", addr); + printk(BIOS_DEBUG, "DRAM bitset verify: 0x%08lx\n", start); #else - print_debug_hex32(addr); - print_debug(" \r"); + print_debug("DRAM bitset verify: 0x"); + print_debug_hex32(start); + print_debug("\n"); #endif - } - value = read_phys(addr); - if (value != addr) { - /* Display address with error */ + failures = 0; + for (idx=0; idx<0x400; idx+=4) { + test_pattern(idx, &addr, &value); + value2 = read_phys(start + addr); + + failed = (value2 != value); + failures |= failed; + if (failed && !verbose) { #if !defined(__ROMCC__) - printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value); + printk(BIOS_ERR, "0x%08lx wr: 0x%08lx rd: 0x%08lx FAIL\n", + start + addr, value, value2); #else - print_err("Fail: @0x"); - print_err_hex32(addr); - print_err(" Read value=0x"); + print_err_hex32(start + addr); + print_err(" wr: 0x"); print_err_hex32(value); - print_err("\n"); -#endif - i++; - if(i>256) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "Aborting.\n"); -#else - print_debug("Aborting.\n"); + print_err(" rd: 0x"); + print_err_hex32(value2); + print_err(" FAIL\n"); #endif - break; - } } - } - /* Display final address */ -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%08lx", addr); -#else - print_debug_hex32(addr); -#endif - - if (i) { + if (verbose) { #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); + if ((addr & 0x0f) == 0) + printk(BIOS_DEBUG, "%08lx wr: %08lx rd:", + start + addr, value); + if (failed) + printk(BIOS_DEBUG, " %08lx!", value2); + else + printk(BIOS_DEBUG, " %08lx ", value2); + if ((addr & 0x0f) == 0xc) + printk(BIOS_DEBUG, "\n"); #else - print_debug("\nDRAM did _NOT_ verify!\n"); + if ((addr & 0x0f) == 0) { + print_dbg_hex32(start + addr); + print_dbg(" wr: "); + print_dbg_hex32(value); + print_dbg(" rd: "); + } + print_dbg_hex32(value2); + if (failed) + print_dbg("! "); + else + print_dbg(" "); + if ((addr & 0x0f) == 0xc) + print_dbg("\n"); #endif - die("DRAM ERROR"); + } } - else { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\nDRAM range verified.\n"); -#else - print_debug("\nDRAM range verified.\n"); -#endif + if (failures) { + post_code(0xea); + die("RAM INIT FAILURE!\n"); } } - void ram_check(unsigned long start, unsigned long stop) { /* @@ -166,18 +167,13 @@ void ram_check(unsigned long start, unsigned long stop) * are tested. -Tyson */ #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop); + printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start); #else - print_debug("Testing DRAM : "); + print_debug("Testing DRAM at: "); print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); print_debug("\n"); #endif - ram_fill(start, stop); - /* Make sure we don't read before we wrote */ - phys_memory_barrier(); - ram_verify(start, stop); + ram_bitset(start); #if !defined(__ROMCC__) printk(BIOS_DEBUG, "Done.\n"); #else @@ -214,4 +210,3 @@ void quick_ram_check(void) } phys_memory_barrier(); } - From marcj303 at gmail.com Fri Nov 18 21:00:26 2011 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 18 Nov 2011 13:00:26 -0700 Subject: [coreboot] Current status of WYSE S50 support In-Reply-To: References: Message-ID: On Wed, Nov 16, 2011 at 9:06 AM, JM wrote: > Hello, > > I am interested in replacing the BIOS on WYSE S50 with coreboot. I > have browsed the mailing list archives, however, some of the reports > are a bit unclear. I'd appreciate if someone could shed some light on > the following concerns of mine: > > 1. Does the board work after RAMBASE rework (i.e. is ticket #163 really fixed)? > > 2. Is the current support of this board sufficient to boot Linux? More > specifically, I have come across some reports of broken vsa and acpi, > is this still an issue? If so, how does the lack of those features > affect normal Linux operation? > > 3. When booting Linux from USB using default manufacturer's BIOS the > ATA port is being disabled. Is this a software or hardware limitation? > In other words, if I boot from USB with coreboot/SeaBIOS would I have > ATA enabled? > > 4. When I boot the Linux kernel with the default BIOS it occasionally > hangs on initializing the PCI subsystem. Is this a result of a bug in > vsa code (virtualized pci) or BIOS? Does the problem persist with > coreboot/SeaBIOS and AMD's vsa? I noticed something called OpenVSA, > does it support Geode GX? > > 5. Can I help in any way with the development not being a programmer? > > Thanks, > JM Hi JM, It has been some time since anyone has worked on Geode. You may have to try it to find out. Before you do, make sure you have a way to recover the BIOS image. It is dated and the build process has changed, but you should read the geode porting page. It talks about VSA and graphics and stuff. The VSA was openned and used on the OLPC project. It requires the Microsoft tools to build and no one has ported it to gcc yet. There is a link to the binary on the geode page. You should stop by the IRC #coreboot if you need a hand building coreboot. http://www.coreboot.org/AMD_Geode_Porting_Guide Marc -- http://se-eng.com From gerrit at coreboot.org Fri Nov 18 21:39:00 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 18 Nov 2011 21:39:00 +0100 Subject: [coreboot] Patch merged into coreboot/master: 8558795 mainboard: Add AMD southstation RDK support References: Message-ID: the following patch was just integrated into master: commit 8558795ef1369052cf634e2d6c5f33a2a11ad718 Author: Kerry Sheh Date: Tue Nov 15 21:27:07 2011 +0800 mainboard: Add AMD southstation RDK support AMD southstation Reference Design Kit is designed for NAS application. This platform using family14 RevC0 processor, SB850 southbridge. Vgabios and Promise RAID Option ROM is required for hardware RAID support, can retrieve from the AMD NDA website. Verified feature: HDMI, LAN, usb and mini-pcie slot. RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10. Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a Signed-off-by: Kerry She Signed-off-by: Kerry She Build-Tested: build bot (Jenkins) at Tue Nov 15 14:33:48 2011, giving +1 Reviewed-By: Marc Jones at Fri Nov 18 21:38:58 2011, giving +2 See http://review.coreboot.org/433 for details. -gerrit From gerrit at coreboot.org Fri Nov 18 21:45:04 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 18 Nov 2011 21:45:04 +0100 Subject: [coreboot] Patch merged into coreboot/master: ac9431d mainboard: Add AMD unionstation RDK support References: Message-ID: the following patch was just integrated into master: commit ac9431d26ba477811c2e27c8ee1a70109ca671fb Author: Kerry Sheh Date: Tue Nov 15 21:27:57 2011 +0800 mainboard: Add AMD unionstation RDK support AMD unionstation Reference Design Kit is Designed for hd settop box application. This platform using family14 APU, SB800 southbridge. Vgabios is required, can download vgabios from AMD NDA website. Verified Feature: HDMI, LAN, mini-pcie slots, sata, usb, analog audio and optical fiber digital audio output. Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c Signed-off-by: Kerry She Signed-off-by: Kerry She Build-Tested: build bot (Jenkins) at Tue Nov 15 14:43:53 2011, giving +1 Reviewed-By: Marc Jones at Fri Nov 18 21:43:19 2011, giving +2 See http://review.coreboot.org/434 for details. -gerrit From fijam at archlinux.us Fri Nov 18 22:05:11 2011 From: fijam at archlinux.us (JM) Date: Fri, 18 Nov 2011 22:05:11 +0100 Subject: [coreboot] Current status of WYSE S50 support In-Reply-To: References: Message-ID: > It has been some time since anyone has worked on Geode. You may have > to try it to find out. Before you do, make sure you have a way to > recover the BIOS image. Thanks for your reply. The chip in question (SST49LF020A in PLCC) only supports LPC and parallel programming. Do you think it would be feasible to purchase another device (they come at about 10 euros) and hot-swap the ROM for reflashing if something went wrong? Alternatively, any hints for 'pulling out' the LPC interface from another device? Sorry if my questions are a bit elementary. > It is dated and the build process has changed, but you should read the > geode porting page. It talks about VSA and graphics and stuff. The VSA > was openned and used on the OLPC project. It requires the Microsoft > tools to build and no one has ported it to gcc yet. There is a link to > the binary on the geode page. You should stop by the IRC #coreboot if > you need a hand building coreboot. > > http://www.coreboot.org/AMD_Geode_Porting_Guide I'll be sure to take a look at that. Regards, Jan From paulk at paulk.fr Sat Nov 19 12:53:33 2011 From: paulk at paulk.fr (PaulK) Date: Sat, 19 Nov 2011 12:53:33 +0100 Subject: [coreboot] ASRock ConRoeXFire-eSATA2 board support Message-ID: <1321703614.1585.36.camel@aldrin> Hi! I'm new to this list so I'll start by introducing myself a bit: I'm a french student involved in free software: I use GNU/Linux distros on all my PCs, mostly with the fully free Trisquel distro and I'm also a developer (I know C quite well) mostly involved in the Replicant project (fully free Android derivate) as a hacker (lower-level stuff). The lead dev on the project (GNUtoo) decided to look at how doable it is to port his board to coreboot, so I decided to follow his lead and look at which of the motherboards I own would be the best one for coreboot. I have 2 boards that might be good candidates, ASRock ConRoeXFire-eSATA2 (which has a socketed PLCC32 chip) and Asus P5LP-LE (Lithium) with a soldered PLCC32 chip. Both boards should have supported North/Southbridge and SuperIO already supported in coreboot. I decided to start the work on the ASRock ConRoeXFire-eSATA2 one and thanks to the help I got on IRC, it has been possible to add support for the board on flashrom in a few hours. I also found another compatible flash (same size, even same model apparently) so I can use it to flash coreboot images. So here are the technical details now: * northbridge is Intel Corporation 82945G/GZ/P/PL * southbridge is Intel Corporation N10/ICH 7 Family * superio is Winbond W83627EHG (see lspci out for more details) So the board coming closer to mine is Kontron 986LCD-M/mITX. I forked the device files for this one and I did this: * replaced W83627THG references to W83627EHG * used superio init function from another board (ASUS A8V-E SE) * modified this function to have clcksel to 48MHz (as told on IRC) * called w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); between superio init and console init So far I got serial working, but the northbridge I use isn't the exact model on the board and the model on the board isn't supported by coreboot. Though: some stuff seems to work with the other northbridge code and I found wide documentation about the intel 945G/GZ/P/PL chip used. So I'm wondering what the next steps are? Adding support for the correct northbridge? -- Paul Kocialkowski * Website : http://www.paulk.fr/ * Blog : http://blog.paulk.fr/ * Microblogging : http://status.paulk.fr/ -------------- next part -------------- A non-text attachment was scrubbed... Name: conroexfire-esata2-coreboot-20111119.log Type: text/x-log Size: 3150 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: lspci-full.log Type: text/x-log Size: 41133 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: superio-deV.log Type: text/x-log Size: 359646 bytes Desc: not available URL: From oliver at schinagl.nl Sat Nov 19 13:18:00 2011 From: oliver at schinagl.nl (Oliver Schinagl) Date: Sat, 19 Nov 2011 13:18:00 +0100 Subject: [coreboot] Current status of WYSE S50 support In-Reply-To: References: Message-ID: <4EC79E78.9080601@schinagl.nl> Having put off to reply, this may be a reason to do so once more :) I have 5 or 6 Wyse S10 (which are very very similar to the S50's) thinclients with 1gb 'disk-on-chip' IDE disks and 256MB Ram (over the stock 128mb ram and no d-o-c, e.g. using bios only) of which I'm willing to donate 1 or even 2 if demand is high enough. I'll cover shipping within europe (and other places we can talk) and throw in the 100-240V adapter with EU power plug. I'm not skilled enough to do the porting myself, unless i'd have loads of help (i know C but no clue where to state and little time). Let me know if your interested, or if there's some other procedure i'd have to adhere to when donating 'stuff'. oliver On 18-11-11 21:00, Marc Jones wrote: > On Wed, Nov 16, 2011 at 9:06 AM, JM wrote: >> Hello, >> >> I am interested in replacing the BIOS on WYSE S50 with coreboot. I >> have browsed the mailing list archives, however, some of the reports >> are a bit unclear. I'd appreciate if someone could shed some light on >> the following concerns of mine: >> >> 1. Does the board work after RAMBASE rework (i.e. is ticket #163 really fixed)? >> >> 2. Is the current support of this board sufficient to boot Linux? More >> specifically, I have come across some reports of broken vsa and acpi, >> is this still an issue? If so, how does the lack of those features >> affect normal Linux operation? >> >> 3. When booting Linux from USB using default manufacturer's BIOS the >> ATA port is being disabled. Is this a software or hardware limitation? >> In other words, if I boot from USB with coreboot/SeaBIOS would I have >> ATA enabled? >> >> 4. When I boot the Linux kernel with the default BIOS it occasionally >> hangs on initializing the PCI subsystem. Is this a result of a bug in >> vsa code (virtualized pci) or BIOS? Does the problem persist with >> coreboot/SeaBIOS and AMD's vsa? I noticed something called OpenVSA, >> does it support Geode GX? >> >> 5. Can I help in any way with the development not being a programmer? >> >> Thanks, >> JM > Hi JM, > > It has been some time since anyone has worked on Geode. You may have > to try it to find out. Before you do, make sure you have a way to > recover the BIOS image. > > It is dated and the build process has changed, but you should read the > geode porting page. It talks about VSA and graphics and stuff. The VSA > was openned and used on the OLPC project. It requires the Microsoft > tools to build and no one has ported it to gcc yet. There is a link to > the binary on the geode page. You should stop by the IRC #coreboot if > you need a hand building coreboot. > > http://www.coreboot.org/AMD_Geode_Porting_Guide > > Marc > > -- > http://se-eng.com > From zeonglow at googlemail.com Sat Nov 19 18:33:13 2011 From: zeonglow at googlemail.com (Christopher Huang-Leaver) Date: Sat, 19 Nov 2011 17:33:13 +0000 Subject: [coreboot] Coreboot support for ASUS M5 A99X EVO ? Message-ID: Hello, I noticed earlier versions of this board are fully supported, but not this one. I have attached the output of, lspci, flashrom and dmidecode, if that is any use to anyone. The spec sheet is easy to find by typing ASUS M5 A99X into Google. The board does have a neat feature of being able to flash the BIOS from within the BIOS menu, which I have already used to update it. Many thanks Chris -[0000:00]-+-00.0 ATI Technologies Inc RD890 PCI to PCI bridge (external gfx0 port B) [1002:5a14] +-00.2 ATI Technologies Inc Device [1002:5a23] +-03.0-[01]----00.0 nVidia Corporation G92 [GeForce 9800 GT] [10de:0605] +-04.0-[02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] +-05.0-[03]----00.0 Device [1b21:1042] +-06.0-[04]----00.0 JMicron Technology Corp. Device [197b:2362] +-07.0-[05]----00.0 Device [1b21:1042] +-0a.0-[06]----00.0 JMicron Technology Corp. Device [197b:2362] +-11.0 ATI Technologies Inc SB700/SB800 SATA Controller [AHCI mode] [1002:4391] +-12.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] +-12.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] +-13.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] +-13.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] +-14.3 ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] +-14.4-[07]----06.0 VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044] +-14.5 ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399] +-16.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] +-16.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] +-18.0 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] +-18.1 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Address Map [1022:1201] +-18.2 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] +-18.3 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] \-18.4 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Link Control [1022:1204] flashrom v0.9.4-r1395 on Linux 3.0.6-gentoo (x86_64), built with libpci 3.1.7, GCC 4.5.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1601M loops per second, 10 myus = 10 us, 100 myus = 105 us, 1000 myus = 999 us, 10000 myus = 10010 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To be filled by O.E.M." DMI string system-product-name: "To be filled by O.E.M." DMI string system-version: "To be filled by O.E.M." DMI string baseboard-manufacturer: "ASUSTeK COMPUTER INC." DMI string baseboard-product-name: "M5A99X EVO" DMI string baseboard-version: "Rev 1.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8721 on port 0x2e Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. Enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=0, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 NormSpeed is 16.5 MHz GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK SB700 IMC is not active. ROM strap override is not active OK. This chipset supports the following protocols: LPC, FWH, SPI. Super I/O ID 0x8721 is not on the list of flash capable controllers. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x49, id2 0xbb, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0x49, id2 0xbb, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x49, id2 0xbb, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0x49, id2 0xbb, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 00 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xbc, id2 0xfb, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x15 No operations were specified. # dmidecode 2.10 SMBIOS 2.7 present. 55 structures occupying 2517 bytes. Table at 0x000EED90. Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: American Megatrends Inc. Version: 0813 Release Date: 10/24/2011 Address: 0xF0000 Runtime Size: 64 kB ROM Size: 4096 kB Characteristics: PCI is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 kB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) ACPI is supported USB legacy is supported BIOS boot specification is supported Targeted content distribution is supported BIOS Revision: 4.6 Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: To be filled by O.E.M. Product Name: To be filled by O.E.M. Version: To be filled by O.E.M. Serial Number: To be filled by O.E.M. UUID: 1F002720-00C6-1700-CB24-14DAE94E0438 Wake-up Type: Power Switch SKU Number: To be filled by O.E.M. Family: To be filled by O.E.M. Handle 0x0002, DMI type 2, 15 bytes Base Board Information Manufacturer: ASUSTeK COMPUTER INC. Product Name: M5A99X EVO Version: Rev 1.xx Serial Number: 111212280000687 Asset Tag: To be filled by O.E.M. Features: Board is a hosting board Board is replaceable Location In Chassis: To be filled by O.E.M. Chassis Handle: 0x0003 Type: Motherboard Contained Object Handles: 0 Handle 0x0003, DMI type 3, 22 bytes Chassis Information Manufacturer: To Be Filled By O.E.M. Type: Desktop Lock: Not Present Version: To Be Filled By O.E.M. Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00000000 Height: Unspecified Number Of Power Cords: 1 Contained Elements: 0 Handle 0x0004, DMI type 4, 42 bytes Processor Information Socket Designation: AM3r2 Type: Central Processor Family: Manufacturer: AMD ID: 43 0F 10 00 FF FB 8B 17 Version: AMD Phenom(tm) II X4 955 Processor Voltage: 1.4 V External Clock: 200 MHz Max Speed: 3200 MHz Current Speed: 3200 MHz Status: Populated, Enabled Upgrade: L1 Cache Handle: 0x0005 L2 Cache Handle: 0x0006 L3 Cache Handle: 0x0007 Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Part Number: To Be Filled By O.E.M. Core Count: 4 Core Enabled: 4 Thread Count: 4 Characteristics: 64-bit capable Handle 0x0005, DMI type 7, 19 bytes Cache Information Socket Designation: L1-Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 512 kB Maximum Size: 512 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 1 ns Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 2-way Set-associative Handle 0x0006, DMI type 7, 19 bytes Cache Information Socket Designation: L2-Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 2048 kB Maximum Size: 2048 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 1 ns Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 16-way Set-associative Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: L3-Cache Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Write Back Location: Internal Installed Size: 6144 kB Maximum Size: 6144 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 1 ns Error Correction Type: Multi-bit ECC System Type: Unified Associativity: Other Handle 0x0008, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1A1 Internal Connector Type: None External Reference Designator: PS2Mouse External Connector Type: PS/2 Port Type: Mouse Port Handle 0x0009, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1A1 Internal Connector Type: None External Reference Designator: Keyboard External Connector Type: PS/2 Port Type: Keyboard Port Handle 0x000A, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A1 Internal Connector Type: None External Reference Designator: TV Out External Connector Type: Mini Centronics Type-14 Port Type: Other Handle 0x000B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A2A Internal Connector Type: None External Reference Designator: COM A External Connector Type: DB-9 male Port Type: Serial Port 16550A Compatible Handle 0x000C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A2B Internal Connector Type: None External Reference Designator: Video External Connector Type: DB-15 female Port Type: Video Port Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J3A1 Internal Connector Type: None External Reference Designator: USB1 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J3A1 Internal Connector Type: None External Reference Designator: USB2 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J3A1 Internal Connector Type: None External Reference Designator: USB3 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9A1 - TPM HDR Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0011, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9C1 - PCIE DOCKING CONN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0012, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2B3 - CPU FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0013, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6C2 - EXT HDMI Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0014, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J3C1 - GMCH FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0015, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1D1 - ITP Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0016, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9E2 - MDC INTPSR Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0017, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9E4 - MDC INTPSR Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0018, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9E3 - LPC HOT DOCKING Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0019, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9E1 - SCAN MATRIX Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001A, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9G1 - LPC SIDE BAND Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J8F1 - UNIFIED Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6F1 - LVDS Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2F1 - LAI FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2G1 - GFX VID Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1G6 - AC JACK Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0020, DMI type 9, 17 bytes System Slot Information Designation: J6B2 Type: x16 PCI Express Current Usage: In Use Length: Long ID: 0 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Bus Address: 0000:00:01.0 Handle 0x0021, DMI type 9, 17 bytes System Slot Information Designation: J6B1 Type: x1 PCI Express Current Usage: In Use Length: Short ID: 1 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Bus Address: 0000:00:1c.3 Handle 0x0022, DMI type 9, 17 bytes System Slot Information Designation: J6D1 Type: x1 PCI Express Current Usage: In Use Length: Short ID: 2 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Bus Address: 0000:00:1c.4 Handle 0x0023, DMI type 10, 6 bytes On Board Device Information Type: Video Status: Enabled Description: To Be Filled By O.E.M. Handle 0x0024, DMI type 11, 5 bytes OEM Strings String 1: To Be Filled By O.E.M. String 2: To Be Filled By O.E.M. String 3: To Be Filled By O.E.M. String 4: To Be Filled By O.E.M. Handle 0x0025, DMI type 12, 5 bytes System Configuration Options Option 1: To Be Filled By O.E.M. Handle 0x0026, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: Multi-bit ECC Maximum Capacity: 32 GB Error Information Handle: Not Provided Number Of Devices: 4 Handle 0x0027, DMI type 19, 31 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x001400003FF Range Size: 5242881 kB Physical Array Handle: 0x0026 Partition Width: 0 Handle 0x0028, DMI type 17, 34 bytes Memory Device Array Handle: 0x0026 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM0 Bank Locator: BANK0 Type: Type Detail: Synchronous Speed: 1333 MHz Manufacturer: Manufacturer0 Serial Number: SerNum0 Asset Tag: AssetTagNum0 Part Number: Array1_PartNumber0 Rank: Unknown Handle 0x0029, DMI type 20, 35 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000000003FF Range Size: 1 kB Physical Device Handle: 0x0028 Memory Array Mapped Address Handle: 0x0027 Partition Row Position: Interleave Position: Unknown Interleaved Data Depth: Unknown Handle 0x002A, DMI type 17, 34 bytes Memory Device Array Handle: 0x0026 Error Information Handle: Not Provided Total Width: Unknown Data Width: 64 bits Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM1 Bank Locator: BANK1 Type: Unknown Type Detail: Synchronous Speed: Unknown Manufacturer: Manufacturer1 Serial Number: SerNum1 Asset Tag: AssetTagNum1 Part Number: Array1_PartNumber1 Rank: Unknown Handle 0x002B, DMI type 126, 35 bytes Inactive Handle 0x002C, DMI type 17, 34 bytes Memory Device Array Handle: 0x0026 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM2 Bank Locator: BANK2 Type: Type Detail: Synchronous Speed: 1333 MHz Manufacturer: Manufacturer2 Serial Number: SerNum2 Asset Tag: AssetTagNum2 Part Number: Array1_PartNumber2 Rank: Unknown Handle 0x002D, DMI type 20, 35 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x002C Memory Array Mapped Address Handle: 0x0027 Partition Row Position: Interleave Position: Unknown Interleaved Data Depth: Unknown Handle 0x002E, DMI type 17, 34 bytes Memory Device Array Handle: 0x0026 Error Information Handle: Not Provided Total Width: Unknown Data Width: 64 bits Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM3 Bank Locator: BANK3 Type: Unknown Type Detail: Synchronous Speed: Unknown Manufacturer: Manufacturer3 Serial Number: SerNum3 Asset Tag: AssetTagNum3 Part Number: Array1_PartNumber3 Rank: Unknown Handle 0x002F, DMI type 126, 35 bytes Inactive Handle 0x0030, DMI type 32, 20 bytes System Boot Information Status: No errors detected Handle 0x0031, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard IGD Type: Video Status: Enabled Type Instance: 1 Bus Address: 0000:00:02.0 Handle 0x0032, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard LAN Type: Ethernet Status: Enabled Type Instance: 1 Bus Address: 0000:00:19.0 Handle 0x0033, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard 1394 Type: Other Status: Enabled Type Instance: 1 Bus Address: 0000:03:1c.2 Handle 0x0034, DMI type 139, 54 bytes OEM-specific Type Header and Data: 8B 36 34 00 00 1F C6 00 00 17 CB 24 04 04 32 55 F8 00 A2 02 A1 00 40 63 43 10 FE 81 03 DF 40 B2 00 20 00 73 3C 10 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 Strings: V1394GUID Handle 0x0035, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 8 en|US|iso8859-1 fr|FR|iso8859-1 es|ES|iso8859-1 de|DE|iso8859-1 ru|RU|iso8859-5 zh|TW|unicode zh|CN|unicode ja|JP|unicode Currently Installed Language: en|US|iso8859-1 Handle 0x0037, DMI type 127, 4 bytes End Of Table -- "They say great science is built on the shoulders of giants - not here. At Aperture we do all our science from scratch; no hand holding." - Cave Johnson, CEO Aperture Science. Follow me on twitter: @zeonglow -------------- next part -------------- An HTML attachment was scrubbed... URL: From christian.suehs at online.de Sun Nov 20 11:43:32 2011 From: christian.suehs at online.de (Christian) Date: Sun, 20 Nov 2011 11:43:32 +0100 Subject: [coreboot] Can't disable serial console debug for MS-6178 Message-ID: <1321785812.10993.5.camel@dance-or-die3.athome.de> Hello, if I disable serial console debug in KConfig I get a compiling error in src/include/uart8250.h at line 31/32 Is that a known issue? chris From sibradzic at gmail.com Sun Nov 20 18:35:01 2011 From: sibradzic at gmail.com (=?UTF-8?B?U2FtaXIgSWJyYWTFvmnEhw==?=) Date: Mon, 21 Nov 2011 02:35:01 +0900 Subject: [coreboot] Issues with Supermicro H8SCM In-Reply-To: References: <20111014212645.GA29984@coreboot.org> <20111017224402.GA20387@coreboot.org> Message-ID: <4EC93A45.9040406@gmail.com> Hello Kerry, Thomas, Marc, I got this board for a personal server project, as well as test platform to dive into coreboot. Board is H8SCM-F rev 1.02, one with BMC. Had build nice external FT2232 programmer for bailing out of broken flash situation, works great. I've experimented with recent coreboot revision, ea5c2b6 + Kerry's AGESA patches (thanks a bunch!), and had experienced same problem as Thomas, plus some more; 1. Two DIMMs in dual-channel setup wont work, same issue as Thomas, 2x4GB ECC DIMMs here. 2. After booting via coreboot with same Linux distro, SR5850 NorthBridge heatsink instantly gets much more hot than booting via SuperMicro BIOS. The temperature is MUCH higher, on idle system, though i can not measure this by other method than putting my finger there, and i got instantly BURNED when coreboot is being used. I am afraid to fry my board if it runs longer this way, it is really that hot. 3. HPET is not being reported at all by coreboot ACPI, OS timer precision suffers big deal. Dont know if this is a feature or bug? Dmesg clearly shows the difference, all these lines are missing when booting via coreboot: # dmesg | grep -i hpet [ 0.000000] ACPI: HPET 00000000cfeaa5e0 00038 (v01 062911 OEMHPET 20110629 MSFT 00000097) [ 0.000000] ACPI: HPET id: 0x8300 base: 0xfed00000 [ 0.000000] hpet clockevent registered [ 1.132106] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 [ 1.140072] hpet0: 4 comparators, 32-bit 14.318180 MHz counter [ 1.146104] Switching to clocksource hpet [ 3.499557] rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs 4. CPU (got 4170 HE) frequency scaling only goes as low as 1800MHz in coreboot when idle. SuperMicro BIOS easily goes all the way down to 800MHz. Spotted this in /proc/cpuinfo 5. USB/EHCI - i haven't really tested this, but it seems minor compared to 1 & 2. Now, i know this board is not exactly supported, most probably being an AGESA problem, but i would really like to do my best to help to make it work better if possible. @ Kerry, I was trying to analyze some AGESA code to get to the DIMM problem, but most of it is a mystery to me. Could you please point me to the right place for "DRAM training" in the code, i am willing to invest some time and nerves to test & investigate this, as well as NB overheating problem. Any plans to update those AGESA patches for this board? One strange thing about RAM init is that the coreboot somehow thinks the board has 8 slots, but it has only four (there should be no channels 2 & 3); Socket 0 Channel 0 Dimm 0 found dimm: 00400745 Socket 0 Channel 0 Dimm 1 not found dimm Socket 0 Channel 1 Dimm 0 found dimm: 00400947 Socket 0 Channel 1 Dimm 1 not found dimm Socket 0 Channel 2 Dimm 0 not found dimm Socket 0 Channel 2 Dimm 1 not found dimm Socket 0 Channel 3 Dimm 0 not found dimm Socket 0 Channel 3 Dimm 1 not found dimm Dct 0 Channel 0 RegDimmPresent: 1 SODimmPresent: 0 ChDimmValid: 1 DimmPlPresent: 0 DimmQrPresent: 0 DimmDrPresent: 0 DimmSRPresent: 1 Dimmx4Present: 1 DimmX8Present: 0 DimmX16Present: 0 DimmMirrorPresent: 0 Dct 1 Channel 0 RegDimmPresent: 1 SODimmPresent: 0 ChDimmValid: 1 DimmPlPresent: 0 DimmQrPresent: 0 DimmDrPresent: 0 DimmSRPresent: 1 Dimmx4Present: 1 DimmX8Present: 0 DimmX16Present: 0 DimmMirrorPresent: 0 ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c', line 163 Thanks, Samir From roysjosh at gmail.com Sun Nov 20 21:07:29 2011 From: roysjosh at gmail.com (Joshua Roys) Date: Sun, 20 Nov 2011 15:07:29 -0500 Subject: [coreboot] [PATCH] superiotool: add EOT for Infineon ports Message-ID: <4EC95E01.6070405@gmail.com> Hello, This patch prevents a long loop through memory until superiotool finds an EOT. Signed-off-by: Joshua Roys Thanks, Josh -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 0001-superiotool-add-EOT-for-Infineon-ports.patch URL: From gerrit at coreboot.org Sun Nov 20 22:08:17 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sun, 20 Nov 2011 22:08:17 +0100 Subject: [coreboot] New patch to review for coreboot: 1eefdb3 Via Epia-N and C3: Set ioapic delivery type in Kconfig References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/435 -gerrit commit 1eefdb3bbbd582042a2b332f55df0a54c3d8cae9 Author: Ky?sti M?lkki Date: Sun Nov 20 20:08:15 2011 +0200 Via Epia-N and C3: Set ioapic delivery type in Kconfig The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. If someone can confirm this, set delivery type under cpu/via/model_c3 instead. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Ky?sti M?lkki --- src/Kconfig | 4 ++++ src/arch/x86/lib/ioapic.c | 9 --------- src/mainboard/via/epia-n/Kconfig | 5 +++++ 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 525d452..1df339d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -239,6 +239,10 @@ config IOAPIC bool default n +config IOAPIC_DELIVERY_TYPE + int + default 1 + # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB int diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 91e43a6..fee2ca1 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -180,15 +180,6 @@ static void load_vectors(u32 ioapic_base, u8 bsp_lapicid) } } -// XXX this decision should probably be made elsewhere, and -// it's the C3, not the EPIA this depends on. - -#if CONFIG_EPIA_VT8237R_INIT -#define CONFIG_IOAPIC_DELIVERY_TYPE 0 -#else -#define CONFIG_IOAPIC_DELIVERY_TYPE 1 -#endif - /** * Assign IOAPIC with an ID * diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig index 4806753..5a88f6a 100644 --- a/src/mainboard/via/epia-n/Kconfig +++ b/src/mainboard/via/epia-n/Kconfig @@ -28,4 +28,9 @@ config IRQ_SLOT_COUNT int default 7 +# IRQ delivery on APIC bus may be a Via C3 CPU requirement. +config IOAPIC_DELIVERY_TYPE + int + default 0 + endif # BOARD_VIA_EPIA_N From gerrit at coreboot.org Sun Nov 20 22:08:18 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sun, 20 Nov 2011 22:08:18 +0100 Subject: [coreboot] Patch set updated for coreboot: 3665162 IOAPIC: Divide setup_ioapic() in two parts. References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/300 -gerrit commit 3665162140efa06ea97201642f6d74cb945efd87 Author: Ky?sti M?lkki Date: Sun Nov 20 20:36:21 2011 +0200 IOAPIC: Divide setup_ioapic() in two parts. Currently some southbridge codes implement the init_ioapic() part locally and do not implement the load_vectors() part at all. I suspect that load_vectors() should always be called. Revised init_ioapic() to log on a critical level if one tries to change an already assigned (non-zero) APIC ID, or when the APIC ID is not assigned. Change-Id: Ic5e860b9b669ecd1e9ddac4bbb92d80bdb9c2fca Signed-off-by: Ky?sti M?lkki --- src/arch/x86/lib/ioapic.c | 152 +++++++++++++++++++++++++++++++++----------- 1 files changed, 114 insertions(+), 38 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 81d964c..91e43a6 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -34,6 +34,11 @@ static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) write32(ioapic_base + 0x10, value); } +/** + * Clear all IOAPIC vectors. + * + * @ioapic_base IOAPIC base address + */ void clear_ioapic(u32 ioapic_base) { u32 low, high; @@ -64,24 +69,85 @@ void clear_ioapic(u32 ioapic_base) } } -void setup_ioapic(u32 ioapic_base, u8 ioapic_id) +/** + * Assign IOAPIC with an ID and set delivery type. + * + * @ioapic_base IOAPIC base address + * @new_id If non-zero (1-15), assign new apic ID. + * If zero, use previously assigned apic ID. + * @delivery If 0x0, deliver interrupts on APIC serial bus + * If 0x1, deliver interrupts on FSB + */ +static void init_ioapic(u32 ioapic_base, u8 new_id, u8 delivery) { - u32 bsp_lapicid = lapicid(); - u32 low, high; - u32 i, ioapic_interrupts; + u8 loud = 0; + u8 active_id; + u32 reg32; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", - ioapic_base); - printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", - bsp_lapicid); + reg32 = io_apic_read(ioapic_base, 0x00); + active_id = (reg32 >> 24) & 0xf; + + /* Changing a previously assigned ID and attempting + * to use ID=0 here are logged at a critical level. + */ + if ( ((active_id && new_id) && (active_id != new_id)) || + !(active_id || new_id)) + loud = 1; + + if (!new_id) { + printk(loud ? BIOS_CRIT : BIOS_DEBUG, + "IOAPIC: 0x%08x using old ID = %d\n", + ioapic_base, active_id); + + } else { + reg32 &= 0xf0ffffff; + reg32 |= (new_id & 0xf) << 24; + io_apic_write(ioapic_base, 0x00, reg32); + + printk(loud ? BIOS_CRIT : BIOS_DEBUG, + "IOAPIC: 0x%08x changing ID = %d->%d\n", + ioapic_base, active_id, new_id); + + reg32 = io_apic_read(ioapic_base, 0x00); + active_id = (reg32 >> 24) & 0xf; + if (active_id != new_id) + printk(BIOS_CRIT, + "IOAPIC: 0x%08x changing ID failed (%d!=%d)\n", + ioapic_base, active_id, new_id); + } - if (ioapic_id) { - printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); - /* Set IOAPIC ID if it has been specified. */ - io_apic_write(ioapic_base, 0x00, - (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | - (ioapic_id << 24)); + /* Assign interrupt delivery type. */ + reg32 = io_apic_read(ioapic_base, 0x03); + switch (delivery) { + case 0: + printk(BIOS_DEBUG, "IOAPIC: Delivery is on APIC serial bus\n"); + reg32 = 0x00; + break; + case 1: + printk(BIOS_DEBUG, "IOAPIC: Delivery is on FSB\n"); + reg32 = 0x01; + break; + default: + printk(BIOS_CRIT, "IOAPIC: Delivery is reverted to FSB\n"); + reg32 = 0x01; + break; } + io_apic_write(ioapic_base, 0x03, reg32); +} + +/** + * Fill IOAPIC vectors all targeting the same processor. + * Virtual Wire Mode on vector 0 is enabled, others remain disabled. + * + * + * @ioapic_base IOAPIC base address + * @bsp_lapicid APIC ID of a CPU to receive the interrupts + * + */ +static void load_vectors(u32 ioapic_base, u8 bsp_lapicid) +{ + u32 low, high; + u32 i, ioapic_interrupts; /* Read the available number of interrupts. */ ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; @@ -89,28 +155,6 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = 24; printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); -// XXX this decision should probably be made elsewhere, and -// it's the C3, not the EPIA this depends on. -#if CONFIG_EPIA_VT8237R_INIT -#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS -#else -#define IOAPIC_INTERRUPTS_ON_FSB -#endif - -#ifdef IOAPIC_INTERRUPTS_ON_FSB - /* - * For the Pentium 4 and above APICs deliver their interrupts - * on the front side bus, enable that. - */ - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); - io_apic_write(ioapic_base, 0x03, - io_apic_read(ioapic_base, 0x03) | (1 << 0)); -#endif -#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); - io_apic_write(ioapic_base, 0x03, 0); -#endif - /* Enable Virtual Wire Mode. */ low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; high = bsp_lapicid << (56 - 32); @@ -125,10 +169,8 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); - low = DISABLED; high = NONE; - for (i = 1; i < ioapic_interrupts; i++) { io_apic_write(ioapic_base, i * 2 + 0x10, low); io_apic_write(ioapic_base, i * 2 + 0x11, high); @@ -137,3 +179,37 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) i, high, low); } } + +// XXX this decision should probably be made elsewhere, and +// it's the C3, not the EPIA this depends on. + +#if CONFIG_EPIA_VT8237R_INIT +#define CONFIG_IOAPIC_DELIVERY_TYPE 0 +#else +#define CONFIG_IOAPIC_DELIVERY_TYPE 1 +#endif + +/** + * Assign IOAPIC with an ID + * + * Compile-time options from mainboard Kconfig can affect the + * chosen IOAPIC operational mode. + * + * @ioapic_base IOAPIC base address + * @new_id If non-zero (1-15), assign new apic ID. + * If zero, use previously assigned apic ID. + */ +void setup_ioapic(u32 ioapic_base, u8 new_id) +{ + u8 bsp_lapicid = lapicid(); + u8 ioapic_dt = CONFIG_IOAPIC_DELIVERY_TYPE; + + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", + ioapic_base); + init_ioapic(ioapic_base, new_id, ioapic_dt); + + printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC ID = %d\n", + bsp_lapicid); + load_vectors(ioapic_base, bsp_lapicid); +} + From gerrit at coreboot.org Sun Nov 20 22:08:18 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sun, 20 Nov 2011 22:08:18 +0100 Subject: [coreboot] Patch set updated for coreboot: 3a2acbb IOAPIC: add setup_ioapic_novectors() References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/301 -gerrit commit 3a2acbbf9ddf661ebbdfde927a55a31cfd673788 Author: Ky?sti M?lkki Date: Sun Nov 20 20:24:59 2011 +0200 IOAPIC: add setup_ioapic_novectors() A little helper until we figure out if there is a reason not to call setup_ioapic() instead on many southbridge codes. Change-Id: Ia28036f2942efd382f20f27cf94117853f88cade Signed-off-by: Ky?sti M?lkki --- src/arch/x86/include/arch/ioapic.h | 1 + src/arch/x86/lib/ioapic.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 623f617..3eabcdc 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -40,5 +40,6 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); +void setup_ioapic_novectors(u32 ioapic_base, u8 new_id); #endif diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index fee2ca1..189c407 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -204,3 +204,14 @@ void setup_ioapic(u32 ioapic_base, u8 new_id) load_vectors(ioapic_base, bsp_lapicid); } +void setup_ioapic_novectors(u32 ioapic_base, u8 new_id) +{ + u8 ioapic_dt = CONFIG_IOAPIC_DELIVERY_TYPE; + + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", + ioapic_base); + init_ioapic(ioapic_base, new_id, ioapic_dt); + + printk(BIOS_CRIT, "IOAPIC: Interrupt Vectors were not initialized\n"); +} + From gerrit at coreboot.org Sun Nov 20 22:08:19 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sun, 20 Nov 2011 22:08:19 +0100 Subject: [coreboot] Patch set updated for coreboot: 5bfd2a7 Cleaning i82801 LPC codes References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/302 -gerrit commit 5bfd2a7a421985d18d266f71d5e806042bf3878c Author: Ky?sti M?lkki Date: Sun Nov 20 21:46:42 2011 +0200 Cleaning i82801 LPC codes Replace ioapic initialisation with global setup_ioapic() or setup_ioapic_novectors(). Unify handling of ACPI BARs. Select IOAPIC as the southbridge has one and now requires that arch/x86/lib/ioapic.c is compiled in. Enable device resources during dev->ops->enable() and not during dev->ops->init(). Change-Id: I8ad80fdd0913995471269f33293c4a4b8cf1de83 Signed-off-by: Ky?sti M?lkki --- src/southbridge/intel/i82801ax/Kconfig | 1 + src/southbridge/intel/i82801ax/lpc.c | 59 ++++++++++------ src/southbridge/intel/i82801bx/Kconfig | 1 + src/southbridge/intel/i82801bx/lpc.c | 58 +++++++++------ src/southbridge/intel/i82801cx/Kconfig | 1 + src/southbridge/intel/i82801cx/lpc.c | 107 ++++++++++++++++------------- src/southbridge/intel/i82801dx/i82801dx.h | 1 + src/southbridge/intel/i82801dx/lpc.c | 68 +++++++++++-------- src/southbridge/intel/i82801ex/i82801ex.h | 9 +++ src/southbridge/intel/i82801ex/lpc.c | 82 +++++++++++++++------- src/southbridge/intel/i82801gx/i82801gx.h | 1 + src/southbridge/intel/i82801gx/lpc.c | 77 ++++++++++++--------- 12 files changed, 285 insertions(+), 180 deletions(-) diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig index 70734a7..71ae016 100644 --- a/src/southbridge/intel/i82801ax/Kconfig +++ b/src/southbridge/intel/i82801ax/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801AX bool + select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index c9404ed..9c115d1 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -70,17 +70,30 @@ typedef struct southbridge_intel_i82801ax_config config_t; * Use the defined IRQ values above or set mainboard * specific IRQ values in your devicetree.cb. */ -static void i82801ax_enable_apic(struct device *dev) -{ - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR; - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + +/** + * Enable ACPI I/O range. + * + * @dev PCI device with ACPI and PM BAR's + */ +static void i82801ax_enable_acpi(struct device *dev) +{ /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @dev PCI device with I/O APIC control registers + */ +static void i82801ax_general_cntl(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ @@ -88,20 +101,8 @@ static void i82801ax_enable_apic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801ax_enable_serial_irqs(struct device *dev) @@ -216,11 +217,8 @@ static void i82801ax_lpc_decode_en(device_t dev) static void lpc_init(struct device *dev) { - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801ax_enable_apic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801ax_enable_serial_irqs(dev); @@ -272,10 +270,25 @@ static void i82801ax_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801ax_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801ax_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801ax_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct device_operations lpc_ops = { .read_resources = i82801ax_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801ax_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801ax_enable, diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig index 00cb5bf..3d725d4 100644 --- a/src/southbridge/intel/i82801bx/Kconfig +++ b/src/southbridge/intel/i82801bx/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801BX bool + select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 0ff44e6..ac72131 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -72,17 +72,29 @@ typedef struct southbridge_intel_i82801bx_config config_t; * Use the defined IRQ values above or set mainboard * specific IRQ values in your devicetree.cb. */ -static void i82801bx_enable_apic(struct device *dev) -{ - uint32_t reg32; - volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR; - volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10); +/** + * Enable ACPI I/O range. + * + * @dev PCI device with ACPI and PM BAR's + */ +static void i82801bx_enable_acpi(struct device *dev) +{ /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @dev PCI device with I/O APIC control registers + */ +static void i82801bx_general_cntl(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ @@ -90,20 +102,8 @@ static void i82801bx_enable_apic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801bx_enable_serial_irqs(struct device *dev) @@ -234,11 +234,8 @@ static void lpc_init(struct device *dev) { uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801bx_enable_apic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801bx_enable_serial_irqs(dev); @@ -290,10 +287,25 @@ static void i82801bx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801bx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801bx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801bx_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct device_operations lpc_ops = { .read_resources = i82801bx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801bx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801bx_enable, diff --git a/src/southbridge/intel/i82801cx/Kconfig b/src/southbridge/intel/i82801cx/Kconfig index a0c775d..7534cbb 100644 --- a/src/southbridge/intel/i82801cx/Kconfig +++ b/src/southbridge/intel/i82801cx/Kconfig @@ -1,2 +1,3 @@ config SOUTHBRIDGE_INTEL_I82801CX bool + select IOAPIC diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index a1ffb8f..67459a6 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -24,34 +24,43 @@ #define MAINBOARD_POWER_ON 1 -static void i82801cx_enable_ioapic( struct device *dev) +/** + * Enable ACPI I/O range. + * + * @dev PCI device with ACPI and PM BAR's + */ +static void i82801cx_enable_acpi(struct device *dev) +{ + // Set ACPI base address to 0x1100 (I/O space) + pci_write_config32(dev, PMBASE, 0x00001101); + + // Enable ACPI I/O and power management + pci_write_config8(dev, ACPI_CNTL, 0x10); + + // Set GPIO base address to 0x1180 (I/O space) + pci_write_config32(dev, GPIO_BASE, 0x00001181); + + // Enable GPIO + pci_write_config8(dev, GPIO_CNTL, 0x10); +} + +/** + * Set miscellanous static southbridge features. + * + * @dev PCI device with I/O APIC control registers + */ +static void i82801cx_general_cntl(struct device *dev) { - uint32_t dword; - volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR; - volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10); - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */ - dword |= (1 <<13); /* coprocessor error enable */ - dword |= (1 << 1); /* delay transaction enable */ - dword |= (1 << 2); /* DMA collection buf enable */ - pci_write_config32(dev, GEN_CNTL, dword); - printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); - - // Must program the APIC's ID before using it - - *ioapic_index = 0; // Select APIC ID register - *ioapic_data = (2<<24); - - // Hang if the ID didn't take (chip not present?) - *ioapic_index = 0; - dword = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF); - if(dword != (2<<24)) - die(""); - - *ioapic_index = 3; // Select Boot Configuration register - *ioapic_data = 1; // Use Processor System Bus to deliver interrupts + u32 reg32; + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); + } // This is how interrupts are received from the Super I/O chip @@ -118,20 +127,6 @@ static void i82801cx_rtc_init(struct device *dev) static void i82801cx_1f0_misc(struct device *dev) { - // Prevent LPC disabling, enable parity errors, and SERR# (System Error) - pci_write_config16(dev, PCI_COMMAND, 0x014f); - - // Set ACPI base address to 0x1100 (I/O space) - pci_write_config32(dev, PMBASE, 0x00001101); - - // Enable ACPI I/O and power management - pci_write_config8(dev, ACPI_CNTL, 0x10); - - // Set GPIO base address to 0x1180 (I/O space) - pci_write_config32(dev, GPIO_BASE, 0x00001181); - - // Enable GPIO - pci_write_config8(dev, GPIO_CNTL, 0x10); // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); @@ -160,8 +155,9 @@ static void lpc_init(struct device *dev) int pwr_on=-1; int nmi_option; + i82801cx_general_cntl(dev); /* IO APIC initialization */ - i82801cx_enable_ioapic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801cx_enable_serial_irqs(dev); @@ -229,13 +225,28 @@ static void i82801cx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801cx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801cx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801cx_general_cntl(dev); + + /* Prevent LPC disabling, enable parity errors, and SERR# (System Error). */ + pci_write_config16(dev, PCI_COMMAND, 0x014f); +} + static struct device_operations lpc_ops = { - .read_resources = i82801cx_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = 0, + .read_resources = i82801cx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = i82801cx_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = 0, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index a38c793..2484eb1 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -86,6 +86,7 @@ extern void i82801dx_enable(device_t dev); #define PMBASE_ADDR 0x0400 #define DEFAULT_PMBASE PMBASE_ADDR #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E #define GPIO_BASE 0x58 #define GPIO_CNTL 0x5C diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 768e700..1cee088 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -36,37 +36,37 @@ typedef struct southbridge_intel_i82801dx_config config_t; -static void i82801dx_enable_ioapic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @dev PCI device with ACPI and PM BAR's + */ +static void i82801dx_enable_acpi(struct device *dev) { - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - /* Enable ACPI I/O and power management. */ - pci_write_config8(dev, ACPI_CNTL, 0x10); + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @dev PCI device with I/O APIC control registers + */ +static void i82801dx_general_cntl(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (3 << 7); /* Enable IOAPIC */ - reg32 |= (1 << 13); /* Coprocessor error enable */ - reg32 |= (1 << 1); /* Delayed transaction enable */ - reg32 |= (1 << 2); /* DMA collection buffer enable */ + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801dx_enable_serial_irqs(struct device *dev) @@ -264,11 +264,8 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801dx_enable_ioapic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801dx_enable_serial_irqs(dev); @@ -323,10 +320,25 @@ static void i82801dx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801dx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801dx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801dx_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct device_operations lpc_ops = { .read_resources = i82801dx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801dx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801dx_enable, diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 67fecdd..22a29f3 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -12,4 +12,13 @@ extern void i82801ex_enable(device_t dev); #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define GPIO_EN (1 << 4) + + #endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 998360c..aadc10e 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -12,8 +12,6 @@ #include #include "i82801ex.h" -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x58 #define NMI_OFF 0 #define MAINBOARD_POWER_OFF 0 @@ -23,6 +21,52 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif +typedef struct southbridge_intel_i82801ex_config config_t; + +/** + * Enable ACPI I/O range. + * + * @dev PCI device with ACPI and PM BAR's + */ +static void i82801ex_enable_acpi(struct device *dev) +{ + u8 gpio_cntl; +#if 0 + /* many i82801's set pmbase here */ + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); +#endif + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); + + /* Enable the GPIO bar */ + gpio_cntl = pci_read_config8(dev, GPIO_CNTL); + gpio_cntl |= GPIO_EN; + pci_write_config8(dev, GPIO_CNTL, gpio_cntl); +} + +/** + * Set miscellanous static southbridge features. + * + * @dev PCI device with I/O APIC configuration registers + */ +static void i82801ex_general_cntl(struct device *dev) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); + + reg32 = pci_read_config32(dev, GEN_STS); + reg32 |= (1<<1); + pci_write_config32(dev, GEN_STS, reg32); + +} + #define SERIRQ_CNTL 0x64 static void i82801ex_enable_serial_irqs(device_t dev) { @@ -45,7 +89,6 @@ static void i82801ex_enable_lpc(device_t dev) pci_write_config8(dev, LPC_EN, 0x0d); } -typedef struct southbridge_intel_i82801ex_config config_t; static void set_i82801ex_gpio_use_sel( device_t dev, struct resource *res, config_t *config) @@ -193,7 +236,7 @@ static void i82801ex_gpio_init(device_t dev) /* Get the chip configuration */ config = dev->chip_info; /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BAR); + res = find_resource(dev, GPIO_BASE); if (!res) { return; } @@ -239,17 +282,10 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { uint8_t byte; - uint32_t value; int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - /* IO APIC initialization */ - value = pci_read_config32(dev, 0xd0); - value |= (1 << 8)|(1<<7)|(1<<1); - pci_write_config32(dev, 0xd0, value); - value = pci_read_config32(dev, 0xd4); - value |= (1<<1); - pci_write_config32(dev, 0xd4, value); - setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. + /* IO APIC initialization. */ + setup_ioapic(IO_APIC_ADDR, 0); /* No APIC ID ?? */ i82801ex_enable_serial_irqs(dev); @@ -295,10 +331,10 @@ static void i82801ex_lpc_read_resources(device_t dev) pci_dev_read_resources(dev); /* Add the ACPI BAR */ - res = pci_get_resource(dev, ACPI_BAR); + res = pci_get_resource(dev, PMBASE); /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BAR); + res = pci_get_resource(dev, GPIO_BASE); /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -321,20 +357,14 @@ static void i82801ex_lpc_read_resources(device_t dev) static void i82801ex_lpc_enable_resources(device_t dev) { - uint8_t acpi_cntl, gpio_cntl; - - /* Enable the normal pci resources */ + /* Enable the normal PCI resources. */ pci_dev_enable_resources(dev); - /* Enable the ACPI bar */ - acpi_cntl = pci_read_config8(dev, 0x44); - acpi_cntl |= (1 << 4); - pci_write_config8(dev, 0x44, acpi_cntl); + /* Enable ACPI and GPIO BARs. */ + i82801ex_enable_acpi(dev); - /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, 0x5c); - gpio_cntl |= (1 << 4); - pci_write_config8(dev, 0x5c, gpio_cntl); + /* Set features (most important: IOAPIC). */ + i82801ex_general_cntl(dev); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 8fb5b92..7b93cbd 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -81,6 +81,7 @@ int smbus_read_byte(unsigned device, unsigned address); #define PMBASE 0x40 #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 7) /* NOTE: was 1<<4 until ICH7 */ #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index c6b76d3..55c8ee0 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,38 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) { - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); +#if 0 + /* many i82801's set pmbase here */ + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); +#endif - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 + /* Enable ACPI I/O range decode and ACPI power management. + * Select SCI IRQ as IRQ9. */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @dev PCI device with I/O APIC configuration registers + */ +static void i82801gx_general_cntl(struct device *dev) +{ + u32 reg32 = 0xABADBEEF; + + /* FIXME: Who sets OIC register @ 0x3155 ?? + */ + printk(BIOS_DEBUG, "Southbridge OIC 0x%08x.\n", reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -418,11 +419,8 @@ static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "i82801gx: lpc_init\n"); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801gx_enable_serial_irqs(dev); @@ -502,6 +500,21 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void i82801gx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801gx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801gx_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -509,7 +522,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = i82801gx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801gx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801gx_enable, From GNUtoo at no-log.org Sun Nov 20 22:44:59 2011 From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli) Date: Sun, 20 Nov 2011 22:44:59 +0100 Subject: [coreboot] VGA issues on ASUS M4A785T-M In-Reply-To: References: <201111111953.43899.GNUtoo@no-log.org> <201111112229.30590.GNUtoo@no-log.org> Message-ID: <201111202245.00020.GNUtoo@no-log.org> >The VGA bios sometimes does not work, and my suggestion is trying to cat >the VGA bios under Linux shell. What do you mean exactly? If you mean running the command advised at the end of www.coreboot.org/VGA_support, I've already done that with the bios shipped with my mainboard and the last version of it. should I look if the images changes (with md5sum) between 2 extractions after reboots ? Denis. From gerrit at coreboot.org Mon Nov 21 03:27:41 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:41 +0100 Subject: [coreboot] New patch to review for coreboot: 76533a8 k8 raminit: comment out code that sets Memory DQ Drive Strength References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/436 -gerrit commit 76533a84e63e9953c82df9898d4de6930c5a1183 Author: Florian Zumbiehl Date: Mon Nov 21 02:51:01 2011 +0100 k8 raminit: comment out code that sets Memory DQ Drive Strength It is unknown what exactly this code was intended to do, but as it stands, it sets Memory DQ Drive Strength to be reduced by 30%, which is a bad idea because of erratum 114, so the code is just commented out for now. Change-Id: I08e4752923c286f9d22c1bab562f3bb3678742dd Signed-off-by: Florian Zumbiehl --- src/cpu/amd/model_fxx/fidvid.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 6395a1e..77ff084 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -44,11 +44,16 @@ static void enable_fid_change(void) dword = 0x04e2a707; pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0xd4, dword); +#if 0 +/* It is unknown what exactly this code was intended to do, but as it stands, + * it sets Memory DQ Drive Strength to be reduced by 30%, which is a bad idea + * because of erratum 114, so the code is just commented out for now. */ /* disable the DRAM interface at first, it will be enabled * by raminit again */ dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94); dword |= (1 << 14); pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword); +#endif dword = 0x23070700; /* enable FID/VID change */ // dword = 0x00070000; /* enable FID/VID change */ From gerrit at coreboot.org Mon Nov 21 03:27:42 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:42 +0100 Subject: [coreboot] New patch to review for coreboot: 20ebb05 vt8237: add support for setting the power state after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/437 -gerrit commit 20ebb056d1fe0a5084dc9203a59a59a10aa184d2 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 vt8237: add support for setting the power state after loss of power Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/lpc.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..e5f2355 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -421,6 +421,7 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + unsigned char pwr_on; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -508,6 +509,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); + /* configure power state of the board after loss of power */ + if (get_option(&pwr_on, "power_on_after_fail") < 0) + pwr_on = 1; + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(pwr_on ? 0x00 : 0x80, 0x71); + pci_write_config8(dev, 0x58, enables); + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Mon Nov 21 03:27:42 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:42 +0100 Subject: [coreboot] Patch set updated for coreboot: 9caded0 make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 9caded0286f027543feae662d19e239fba446930 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index ca52bae..be03cdc 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Mon Nov 21 03:27:43 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:43 +0100 Subject: [coreboot] Patch set updated for coreboot: c90044b make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit c90044b1cae462cdaaf4d41d9dcf7f21429999dd Author: Florian Zumbiehl Date: Mon Nov 21 03:10:47 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index e5f2355..ca52bae 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -422,6 +430,9 @@ static void vt8237_common_init(struct device *dev) { u8 enables, byte; unsigned char pwr_on; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -507,7 +518,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } /* configure power state of the board after loss of power */ if (get_option(&pwr_on, "power_on_after_fail") < 0) From gerrit at coreboot.org Mon Nov 21 03:27:43 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:43 +0100 Subject: [coreboot] Patch set updated for coreboot: dc31f6f implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit dc31f6f11bb92867bc58b582a90f0b105b0062c1 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..2bdcf9d 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | + (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | + (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | + (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | + (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, + (pci_read_config8(dev, 0x5c) & ~0x70) | + (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Mon Nov 21 03:27:44 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:44 +0100 Subject: [coreboot] Patch set updated for coreboot: e6817ca implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit e6817cafe94d64953fa5590c37bf58d76759f14b Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 34 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..8f090d0 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,44 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + /* the above inb() auto-increments the address pointer ... */ + outb(0x5d, base + 5); + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Mon Nov 21 03:27:45 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:45 +0100 Subject: [coreboot] Patch set updated for coreboot: d7bcac8 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit d7bcac8e6f4f20d8504563317a9e23013cac16c4 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl --- src/northbridge/amd/amdk8/raminit.c | 349 +++++++++++++++++------------------ 1 files changed, 166 insertions(+), 183 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..98044d4 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1230,8 +1230,8 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 17, /* *Logical Banks */ 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ - 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 23, /* *Cycle time at CAS Latency (CLX - 0.5) */ + 25, /* *Cycle time at CAS Latency (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,11 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) +{ #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1441,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos = 0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1475,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1484,190 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; + } + +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table + * are to be understood: + */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; - return dloading_cycle_time; -} +#else /* CONFIG_CPU_AMD_SOCKET_* */ + +/* well, there are socket 940 boards supported which obviously fail to + * compile with this */ +// #error load dependent memory clock limiting is not implemented for this socket + + /* see BKDG 4.1.3--if you just want to test a setup that doesn't + * require limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what + * would be intuitive. 200 MHz has the lowest constant, 100 MHz the + * highest. Thus, all comparisons and traversal directions having to + * do with frequencies are/have to be the opposite of what would be + * intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { + /* the CLs supported by the controller: */ + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); + memset(cl_at_freq, 0x00, + (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> + NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; + + if (!(dimm_mask & (1 << dimm))) continue; - } - - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle + * shorter, select that (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#if CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1689,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; From gerrit at coreboot.org Mon Nov 21 03:27:46 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:46 +0100 Subject: [coreboot] Patch set updated for coreboot: 5cf1792 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 5cf17928b5f8a667b97824fa4c363b3d01e414fe Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 20 ++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 115 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..d297143 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,24 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +42,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +72,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Mon Nov 21 03:27:47 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:47 +0100 Subject: [coreboot] Patch set updated for coreboot: ffd09cd copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit ffd09cd594441b0dadf9d25075aacd625ef3b8bd Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Mon Nov 21 03:27:48 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 03:27:48 +0100 Subject: [coreboot] Patch set updated for coreboot: 4a57bd4 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 4a57bd413f93ef5bf639306409baea278608eff9 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 3180412..6e5dbf7 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -51,12 +51,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -151,7 +160,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From Kerry.She at amd.com Mon Nov 21 04:00:47 2011 From: Kerry.She at amd.com (She, Kerry) Date: Mon, 21 Nov 2011 11:00:47 +0800 Subject: [coreboot] Issues with Supermicro H8SCM In-Reply-To: <4EC93A45.9040406@gmail.com> References: <20111014212645.GA29984@coreboot.org> <20111017224402.GA20387@coreboot.org> <4EC93A45.9040406@gmail.com> Message-ID: Hello, Samir > -----Original Message----- > From: Samir Ibrad?i? [mailto:sibradzic at gmail.com] > Sent: Monday, November 21, 2011 1:35 AM > To: She, Kerry > Cc: Thomas Gst?dtner; Marc Jones; coreboot > Subject: Re: [coreboot] Issues with Supermicro H8SCM > > Hello Kerry, Thomas, Marc, > > I got this board for a personal server project, as well as test platform > to dive into coreboot. Board is H8SCM-F rev 1.02, one with BMC. Had > build nice external FT2232 programmer for bailing out of broken flash > situation, works great. I've experimented with recent coreboot revision, > ea5c2b6 + Kerry's AGESA patches (thanks a bunch!), and had experienced > same problem as Thomas, plus some more; > > 1. Two DIMMs in dual-channel setup wont work, same issue as Thomas, > 2x4GB ECC DIMMs here. > 2. After booting via coreboot with same Linux distro, SR5850 NorthBridge > heatsink instantly gets much more hot than booting via SuperMicro BIOS. > The temperature is MUCH higher, on idle system, though i can not measure > this by other method than putting my finger there, and i got instantly > BURNED when coreboot is being used. I am afraid to fry my board if it > runs longer this way, it is really that hot. The hardware monitor is not enable in coreboot. > 3. HPET is not being reported at all by coreboot ACPI, OS timer > precision suffers big deal. Dont know if this is a feature or bug? Dmesg > clearly shows the difference, all these lines are missing when booting > via coreboot: > > # dmesg | grep -i hpet > [ 0.000000] ACPI: HPET 00000000cfeaa5e0 00038 (v01 062911 OEMHPET > 20110629 MSFT 00000097) > [ 0.000000] ACPI: HPET id: 0x8300 base: 0xfed00000 > [ 0.000000] hpet clockevent registered > [ 1.132106] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 > [ 1.140072] hpet0: 4 comparators, 32-bit 14.318180 MHz counter > [ 1.146104] Switching to clocksource hpet > [ 3.499557] rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet > irqs > > 4. CPU (got 4170 HE) frequency scaling only goes as low as 1800MHz in > coreboot when idle. SuperMicro BIOS easily goes all the way down to > 800MHz. Spotted this in /proc/cpuinfo > > 5. USB/EHCI - i haven't really tested this, but it seems minor compared > to 1 & 2. Kevin have fixed some usb-msc bugs in seabios recently, you may need to check the seabios maillist. > Now, i know this board is not exactly supported, most probably being an > AGESA problem, but i would really like to do my best to help to make it > work better if possible. > > > @ Kerry, > > I was trying to analyze some AGESA code to get to the DIMM problem, but > most of it is a mystery to me. Could you please point me to the right > place for "DRAM training" in the code, i am willing to invest some time > and nerves to test & investigate this, as well as NB overheating > problem. Any plans to update those AGESA patches for this board? We have made some update for h8scm mainboard. In order to support new Orochi platform, Except the mainboard code, agesa wrapper, sr56x0 cimx wrapper and sb700/sp5100 cimx wrapper are also included in the change set. But the patch set still pending to release to the community for review. We need some time to get the release process done. Hope the code would be available soon. > One strange thing about RAM init is that the coreboot somehow thinks the > board has 8 slots, but it has only four (there should be no channels 2 & > 3); AGESA support 4 channels. But family10 processor for h8scm only have 2 channels. > Socket 0 Channel 0 Dimm 0 found dimm: 00400745 > Socket 0 Channel 0 Dimm 1 not found dimm > Socket 0 Channel 1 Dimm 0 found dimm: 00400947 > Socket 0 Channel 1 Dimm 1 not found dimm > Socket 0 Channel 2 Dimm 0 not found dimm > Socket 0 Channel 2 Dimm 1 not found dimm > Socket 0 Channel 3 Dimm 0 not found dimm > Socket 0 Channel 3 Dimm 1 not found dimm > Dct 0 Channel 0 > RegDimmPresent: 1 > SODimmPresent: 0 > ChDimmValid: 1 > DimmPlPresent: 0 > DimmQrPresent: 0 > DimmDrPresent: 0 > DimmSRPresent: 1 > Dimmx4Present: 1 > DimmX8Present: 0 > DimmX16Present: 0 > DimmMirrorPresent: 0 > Dct 1 Channel 0 > RegDimmPresent: 1 > SODimmPresent: 0 > ChDimmValid: 1 > DimmPlPresent: 0 > DimmQrPresent: 0 > DimmDrPresent: 0 > DimmSRPresent: 1 > Dimmx4Present: 1 > DimmX8Present: 0 > DimmX16Present: 0 > DimmMirrorPresent: 0 > ASSERTION FAILED: file > 'src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c', line 163 Maybe a dimm spd address problem, you can try following patch: --- a/src/mainboard/supermicro/h8scm_fam10/dimmSpd.c +++ b/src/mainboard/supermicro/h8scm_fam10/dimmSpd.c @@ -55,8 +55,11 @@ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) static const UINT8 spdAddressLookup [1] [2] [2] = { // socket, channel, dimm /* socket 0 */ { - {0xA6, 0xA4}, - {0xA2, 0xA0}, + /* silkprint: DIMM1A DIMM2A DIMM1B DIMM2B + * i2c addr: A6 A2 A4 A0 + */ + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, }; Thanks Kerry From svn at coreboot.org Mon Nov 21 16:00:02 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 21 Nov 2011 16:00:02 +0100 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Mon Nov 21 18:26:01 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 21 Nov 2011 18:26:01 +0100 Subject: [coreboot] Patch set updated for coreboot: 887edeb Via Epia-N and C3: Set ioapic delivery type in Kconfig References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/435 -gerrit commit 887edeb201b646ca51fd92a866b4cac087c99a4c Author: Ky?sti M?lkki Date: Mon Nov 21 19:12:50 2011 +0200 Via Epia-N and C3: Set ioapic delivery type in Kconfig The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. If someone can confirm this, set delivery type under cpu/via/model_c3 instead. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Ky?sti M?lkki --- src/Kconfig | 5 +++++ src/arch/x86/lib/ioapic.c | 9 --------- src/mainboard/via/epia-n/Kconfig | 5 +++++ 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 525d452..cbb95cb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -239,6 +239,11 @@ config IOAPIC bool default n +# Boards with CPU_VIA_C3 may need to override delivery type. +config IOAPIC_DELIVERY_TYPE + int + default 1 + # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB int diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 91e43a6..fee2ca1 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -180,15 +180,6 @@ static void load_vectors(u32 ioapic_base, u8 bsp_lapicid) } } -// XXX this decision should probably be made elsewhere, and -// it's the C3, not the EPIA this depends on. - -#if CONFIG_EPIA_VT8237R_INIT -#define CONFIG_IOAPIC_DELIVERY_TYPE 0 -#else -#define CONFIG_IOAPIC_DELIVERY_TYPE 1 -#endif - /** * Assign IOAPIC with an ID * diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig index 4806753..5a88f6a 100644 --- a/src/mainboard/via/epia-n/Kconfig +++ b/src/mainboard/via/epia-n/Kconfig @@ -28,4 +28,9 @@ config IRQ_SLOT_COUNT int default 7 +# IRQ delivery on APIC bus may be a Via C3 CPU requirement. +config IOAPIC_DELIVERY_TYPE + int + default 0 + endif # BOARD_VIA_EPIA_N From gerrit at coreboot.org Mon Nov 21 19:01:52 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 21 Nov 2011 19:01:52 +0100 Subject: [coreboot] New patch to review for coreboot: f6be792 Eliminate bad menuconfig combinations References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/438 -gerrit commit f6be7926e0d91a280ea097e510913eacc3606d20 Author: Ky?sti M?lkki Date: Mon Nov 21 08:15:39 2011 +0200 Eliminate bad menuconfig combinations Offer only CBFS_PREFIX "fallback" or "normal", as those names are hard-coded in the bootblock. Only with the choice "fallback" user is provided with the option to select bootblock behaviour. With choice "normal" build runs in image update mode and user has to provide a template (with bootblock and fallback) as build/coreboot.rom. Change-Id: Ie89c2f89245beec70ebb14326437d71699c367b8 Signed-off-by: Ky?sti M?lkki --- src/Kconfig | 20 +++++++++++++++----- src/arch/x86/Kconfig | 9 ++------- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 525d452..fcea4f3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -39,12 +39,22 @@ config LOCALVERSION the coreboot version number, so that you can easily distinguish boot logs of different boards from each other. +choice + prompt "CBFS prefix to use" + default CBFS_PREFIX_FALLBACK + +config CBFS_PREFIX_FALLBACK + bool "fallback" + +config CBFS_PREFIX_NORMAL + bool "normal" + +endchoice + config CBFS_PREFIX - string "CBFS prefix to use" - default "fallback" - help - Select the prefix to all files put into the image. It's "fallback" - by default, "normal" is a common alternative. + string + default "fallback" if CBFS_PREFIX_FALLBACK + default "normal" if CBFS_PREFIX_NORMAL choice prompt "Compiler" diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e71d0f3..d8e584c 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -36,6 +36,7 @@ config MAX_REBOOT_CNT choice prompt "Bootblock behaviour" default X86_BOOTBLOCK_SIMPLE + depends on !UPDATE_IMAGE config X86_BOOTBLOCK_SIMPLE bool "Always load fallback" @@ -51,13 +52,7 @@ config BOOTBLOCK_SOURCE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL config UPDATE_IMAGE - bool "Update existing coreboot.rom image" - default n - help - If this option is enabled, no new coreboot.rom file - is created. Instead it is expected that there already - is a suitable file for further processing. - The bootblock will not be modified. + def_bool !CBFS_PREFIX_FALLBACK config ROMCC bool From gerrit at coreboot.org Mon Nov 21 20:03:26 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 20:03:26 +0100 Subject: [coreboot] Patch set updated for coreboot: 0d79599 make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 0d795995806f6bbdcb2f63c572bb93979f870f29 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 5aac518..ceb6d2c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Mon Nov 21 20:03:26 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 20:03:26 +0100 Subject: [coreboot] Patch set updated for coreboot: cf238a8 make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit cf238a82b5d986bfeb66b74b2d2f57147526a555 Author: Florian Zumbiehl Date: Mon Nov 21 03:10:47 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 207dfdb..5aac518 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,10 +429,13 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; #if !CONFIG_EPIA_VT8237R_INIT unsigned char pwr_on; #endif + cfg = dev->chip_info; + /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); byte |= PCI_COMMAND_WAIT; @@ -509,7 +520,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } /* configure power state of the board after loss of power */ if (get_option(&pwr_on, "power_on_after_fail") < 0) From gerrit at coreboot.org Mon Nov 21 20:03:27 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 20:03:27 +0100 Subject: [coreboot] Patch set updated for coreboot: c9bd389 implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit c9bd389b8a381a48611a5e4b8e0bc399cfb9f6fb Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..2bdcf9d 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | + (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | + (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | + (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | + (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, + (pci_read_config8(dev, 0x5c) & ~0x70) | + (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Mon Nov 21 20:03:27 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 20:03:27 +0100 Subject: [coreboot] Patch set updated for coreboot: cb741e3 implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit cb741e3b5dc67318bfbfa164b673ba64e275db94 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 34 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..8f090d0 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,44 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + /* the above inb() auto-increments the address pointer ... */ + outb(0x5d, base + 5); + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Mon Nov 21 20:03:28 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 20:03:28 +0100 Subject: [coreboot] Patch set updated for coreboot: cd69031 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit cd690313545a5ead0ed2d883266466a90f1c41ad Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 20 ++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 115 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..d297143 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,24 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +42,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +72,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Mon Nov 21 20:03:28 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 20:03:28 +0100 Subject: [coreboot] Patch set updated for coreboot: 1b984b1 vt8237: add support for setting the power state after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/437 -gerrit commit 1b984b1faf8eba8c9a9133b18f1820008e3ba780 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 vt8237: add support for setting the power state after loss of power Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/lpc.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..207dfdb 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -421,6 +421,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; +#if !CONFIG_EPIA_VT8237R_INIT + unsigned char pwr_on; +#endif /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -508,6 +511,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); + /* configure power state of the board after loss of power */ + if (get_option(&pwr_on, "power_on_after_fail") < 0) + pwr_on = 1; + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(pwr_on ? 0x00 : 0x80, 0x71); + pci_write_config8(dev, 0x58, enables); + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Mon Nov 21 20:03:29 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 20:03:29 +0100 Subject: [coreboot] Patch set updated for coreboot: 14717a7 copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit 14717a7f03edd1747dfffccfb46b48746ff8779a Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Mon Nov 21 20:03:31 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Mon, 21 Nov 2011 20:03:31 +0100 Subject: [coreboot] Patch set updated for coreboot: 94c6aa8 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 94c6aa84bb6ca902c2a8b7dc147864dd8193d05f Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 3180412..6e5dbf7 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -51,12 +51,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -151,7 +160,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From kyosti.malkki at gmail.com Mon Nov 21 21:20:18 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Mon, 21 Nov 2011 22:20:18 +0200 Subject: [coreboot] Init for multi-processor Message-ID: <1321906818.7164.13.camel@obelix> Hi Could someone explain the use of boot_cpu() in bootblock_normal.c main()? I thought only the BSP CPU executes this code (currently)? I am about to push a change that does early SMP init for hyper-threading CPUs to allow cache-as-ram implementation. Shared cache remains disabled until both/all logical CPUs enable it. Thanks, Ky?sti From stefan.reinauer at coreboot.org Mon Nov 21 22:30:55 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Tue, 22 Nov 2011 06:30:55 +0900 Subject: [coreboot] Init for multi-processor In-Reply-To: <1321906818.7164.13.camel@obelix> References: <1321906818.7164.13.camel@obelix> Message-ID: <4ECAC30F.8030602@coreboot.org> On 11/22/11 5:20 AM, Ky?sti M?lkki wrote: > Hi > > Could someone explain the use of boot_cpu() in bootblock_normal.c > main()? I thought only the BSP CPU executes this code (currently)? > > I am about to push a change that does early SMP init for hyper-threading > CPUs to allow cache-as-ram implementation. Shared cache remains disabled > until both/all logical CPUs enable it. > For some CPUs types (like AMD K8) all CPUs / cores start running the reset vector code after power-on. Stefan From gerrit at coreboot.org Mon Nov 21 22:47:33 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 21 Nov 2011 22:47:33 +0100 Subject: [coreboot] New patch to review for coreboot: 0ac8b94 Fix post_code in 16bit entry References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/439 -gerrit commit 0ac8b94d07a5b2f4f8bced6f17c44816f79c5b55 Author: Ky?sti M?lkki Date: Mon Nov 21 08:16:20 2011 +0200 Fix post_code in 16bit entry Relocate early post_code() so it gets executed and does not corrupt BIST at %eax. Change-Id: Ieeebcb23f7c327e501b410eaa60d1e49110ee988 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/init/prologue.inc | 4 ---- src/cpu/x86/16bit/entry16.inc | 2 ++ 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/init/prologue.inc b/src/arch/x86/init/prologue.inc index b85c5c0..84e465c 100644 --- a/src/arch/x86/init/prologue.inc +++ b/src/arch/x86/init/prologue.inc @@ -23,7 +23,3 @@ .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits -/* This is the entry code. The code in the .reset section jumps here. */ - - post_code(POST_RESET_VECTOR_CORRECT) - diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 9f4c0e3..9b7b69c 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -36,6 +36,8 @@ _start: /* Save the BIST result */ movl %eax, %ebp + post_code(POST_RESET_VECTOR_CORRECT) + /* thanks to kmliu at sis.tw.com for this TBL fix ... */ /**/ /* IMMEDIATELY invalidate the translation lookaside buffer before executing*/ From gerrit at coreboot.org Mon Nov 21 22:47:33 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 21 Nov 2011 22:47:33 +0100 Subject: [coreboot] New patch to review for coreboot: 481e591 Cosmetic bootblock code changes References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/440 -gerrit commit 481e591ba5ce60ce0ad75f0035fc7e799a8995a6 Author: Ky?sti M?lkki Date: Mon Nov 21 08:16:45 2011 +0200 Cosmetic bootblock code changes Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b Signed-off-by: Ky?sti M?lkki --- src/arch/x86/init/entry.S | 149 ----------------------------------------- src/arch/x86/init/ldscript.ld | 40 ----------- src/cpu/x86/16bit/entry16.inc | 57 ++++++++-------- 3 files changed, 29 insertions(+), 217 deletions(-) diff --git a/src/arch/x86/init/entry.S b/src/arch/x86/init/entry.S deleted file mode 100644 index af29296..0000000 --- a/src/arch/x86/init/entry.S +++ /dev/null @@ -1,149 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 1999 Ronald G. Minnich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include - .code16 - .globl _stage0 -_stage0: - cli - - /* Save the BIST result. */ - movl %eax, %ebp; - - /* thanks to kmliu at sis.com.tw for this TLB fix */ - /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before - * executing any further code. Even though paging is disabled we - * could still get false address translations due to the TLB if we - * didn't invalidate it. - */ - xorl %eax, %eax - movl %eax, %cr3 /* Invalidate TLB. */ - - /* Switch to protected mode. */ - - /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) - * using BFD version 2.15.94.0.2.2 20041220 this works fine without all - * the ld hackery and other things. So leave it as is with this comment. - */ - - data32 lgdt %cs:gdtptr - - movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 - - /* Restore BIST result. */ - movl %ebp, %eax - - // port80_post(0x23) - /* Now we are in protected mode. Jump to a 32 bit code segment. */ - data32 ljmp $ROM_CODE_SEG, $protected_stage0 - - /* I am leaving this weird jump in here in the event that future gas - * bugs force it to be used. - */ - /* .byte 0x66 */ - .code32 - /* ljmp $ROM_CODE_SEG, $protected_stage0 */ - - /* .code16 */ - .align 4 - .globl gdt16 -gdt16 = . - _stage0 -gdt16x: - .word gdt16xend - gdt16x -1 /* Compute the table limit. */ - .long gdt16x - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 -gdt16xend: - - /* From now on we are 32 bit. */ - .code32 - - /* We have two gdts where we could have one. That is ok. - * - * Let's not worry about this -- optimizing gdt is pointless since - * we're only in it for a little bit. - * - * Btw. note the trick below: The GDT points to ITSELF, and the first - * good descriptor is at offset 8. So you word-align the table, and - * then because you chose 8, you get a nice 64-bit aligned GDT entry, - * which is good as this is the size of the entry. - * Just in case you ever wonder why people do this. - */ - .align 4 - .globl gdtptr - .globl gdt_limit -gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ - -gdt: -gdtptr: - .word gdt_end - gdt -1 /* Compute the table limit. */ - .long gdt /* We know the offset. */ - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - -gdt_end: - -/* Reset vector. */ - -/* - * RVECTOR: Size of reset vector, default is 0x10. - * RESRVED: Size of vpd code, default is 0xf0. - * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b). - */ - -SEGMENT_SIZE = 0x10000 -RVECTOR = 0x00010 - -/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here. - * I think we should leave it this way forever, as the bugs come and - * go -- and come again. - * - * .code16 - * .section ".rom.text" - */ -.section ".reset", "ax" - .globl _resetjump -_resetjump: - /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */ - /* jmp _stage0 */ - .byte 0xe9 - .int _stage0 - ( . + 2 ) - - /* Note: The above jump is hand coded to work around bugs in binutils. - * 5 bytes are used for a 3 byte instruction. This works because x86 - * is little endian and allows us to use supported 32 bit relocations - * instead of the weird 16 bit relocations that binutils does not - * handle consistenly between versions because they are used so rarely. - */ diff --git a/src/arch/x86/init/ldscript.ld b/src/arch/x86/init/ldscript.ld deleted file mode 100644 index 149f048..0000000 --- a/src/arch/x86/init/ldscript.ld +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Ronald G. Minnich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -TARGET(binary) -SECTIONS -{ - /DISCARD/ : { - *(.comment) - *(.note.*) - *(.note) - } -} - -SECTIONS { - _ROMTOP = 0xfffffff0; - . = _ROMTOP; - .resetvector . : { - *(.reset) - . = 15 ; - BYTE(0x00); - } -} - diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 9b7b69c..3af718f 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -1,31 +1,32 @@ /* -This software and ancillary information (herein called SOFTWARE ) -called LinuxBIOS is made available under the terms described -here. The SOFTWARE has been approved for release with associated -LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has -been authored by an employee or employees of the University of -California, operator of the Los Alamos National Laboratory under -Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The -U.S. Government has rights to use, reproduce, and distribute this -SOFTWARE. The public may copy, distribute, prepare derivative works -and publicly display this SOFTWARE without charge, provided that this -Notice and any statement of authorship are reproduced on all copies. -Neither the Government nor the University makes any warranty, express -or implied, or assumes any liability or responsibility for the use of -this SOFTWARE. If SOFTWARE is modified to produce derivative works, -such modified SOFTWARE should be clearly marked, so as not to confuse -it with the version available from LANL. - */ -/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL - * rminnich at lanl.gov + * This software and ancillary information (herein called SOFTWARE) + * called LinuxBIOS is made available under the terms described here. + * + * The SOFTWARE has been approved for release with associated + * LA-CC Number 00-34. Unless otherwise indicated, this SOFTWARE has + * been authored by an employee or employees of the University of + * California, operator of the Los Alamos National Laboratory under + * Contract No. W-7405-ENG-36 with the U.S. Department of Energy. + * + * The U.S. Government has rights to use, reproduce, and distributethis + * SOFTWARE. The public may copy, distribute, prepare derivative works + * and publicly display this SOFTWARE without charge, provided that this + * Notice and any statement of authorship are reproduced on all copies. + * + * Neither the Government nor the University makes any warranty, express + * or implied, or assumes any liability or responsibility for the use of + * this SOFTWARE. If SOFTWARE is modified to produce derivative works, + * such modified SOFTWARE should be clearly marked, so as not to confuse + * it with the version available from LANL. + * + * Copyright (C) 2000, Ron Minnich rminnich at lanl.gov + * Advanced Computing Lab, LANL */ -/** Start code to put an i386 or later processor into 32-bit - * protected mode. +/* Start code to put an i386 or later processor into 32-bit protected mode. */ -/* .section ".rom.text" */ #include .code16 .globl _start @@ -38,12 +39,12 @@ _start: post_code(POST_RESET_VECTOR_CORRECT) -/* thanks to kmliu at sis.tw.com for this TBL fix ... */ -/**/ -/* IMMEDIATELY invalidate the translation lookaside buffer before executing*/ -/* any further code. Even though paging is disabled we could still get*/ -/*false address translations due to the TLB if we didn't invalidate it.*/ -/**/ + /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before + * executing any further code. Even though paging is disabled we + * could still get false address translations due to the TLB if we + * didn't invalidate it. Thanks to kmliu at sis.com.tw for this TLB fix. + */ + xorl %eax, %eax movl %eax, %cr3 /* Invalidate TLB*/ From kevin at koconnor.net Tue Nov 22 01:53:44 2011 From: kevin at koconnor.net (Kevin O'Connor) Date: Mon, 21 Nov 2011 19:53:44 -0500 Subject: [coreboot] SeaBIOS USB fixes Message-ID: <20111122005344.GA6282@morn.localdomain> Hi, The current SeaBIOS git master branch now has some important fixes for handling USB drives. These fixes have improved the stability of both UHCI and EHCI controllers. If you were seeing issues booting from USB with SeaBIOS, please retry with the latest SeaBIOS git. If you continue to see failures, please capture the output of the serial log and send it to the SeaBIOS mailing list. Thanks, -Kevin From kyosti.malkki at gmail.com Tue Nov 22 07:01:01 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Tue, 22 Nov 2011 08:01:01 +0200 Subject: [coreboot] Init for multi-processor In-Reply-To: <4ECAC30F.8030602@coreboot.org> References: <1321906818.7164.13.camel@obelix> <4ECAC30F.8030602@coreboot.org> Message-ID: <1321941661.7164.137.camel@obelix> On Tue, 2011-11-22 at 06:30 +0900, Stefan Reinauer wrote: > On 11/22/11 5:20 AM, Ky?sti M?lkki wrote: > > Hi > > > > Could someone explain the use of boot_cpu() in bootblock_normal.c > > main()? I thought only the BSP CPU executes this code (currently)? > > > > I am about to push a change that does early SMP init for hyper-threading > > CPUs to allow cache-as-ram implementation. Shared cache remains disabled > > until both/all logical CPUs enable it. > > > For some CPUs types (like AMD K8) all CPUs / cores start running the > reset vector code after power-on. > > Stefan Do the BSP CPU and/or AP CPUs execute bootblock_normal: main() and mainboard/romstage: cache_as_ram_main() in parallel then? Remember there are no semaphores for shared resources like CMOS_BOOT_BYTE in do_normal_boot() nor any spinlocks for pci_write_config() etc. Ky?sti From stepan at coresystems.de Tue Nov 22 07:17:03 2011 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 22 Nov 2011 15:17:03 +0900 Subject: [coreboot] Init for multi-processor In-Reply-To: <1321941661.7164.137.camel@obelix> References: <1321906818.7164.13.camel@obelix> <4ECAC30F.8030602@coreboot.org> <1321941661.7164.137.camel@obelix> Message-ID: On Tue, 22 Nov 2011 08:01:01 +0200, Ky?sti M?lkki wrote: > On Tue, 2011-11-22 at 06:30 +0900, Stefan Reinauer wrote: >> On 11/22/11 5:20 AM, Ky?sti M?lkki wrote: >> > Hi >> > >> > Could someone explain the use of boot_cpu() in bootblock_normal.c >> > main()? I thought only the BSP CPU executes this code (currently)? >> > >> > I am about to push a change that does early SMP init for >> hyper-threading >> > CPUs to allow cache-as-ram implementation. Shared cache remains >> disabled >> > until both/all logical CPUs enable it. >> > >> For some CPUs types (like AMD K8) all CPUs / cores start running the >> reset vector code after power-on. >> >> Stefan > > Do the BSP CPU and/or AP CPUs execute bootblock_normal: main() and > mainboard/romstage: cache_as_ram_main() in parallel then? > > Remember there are no semaphores for shared resources like > CMOS_BOOT_BYTE in do_normal_boot() nor any spinlocks for > pci_write_config() etc. non-AP CPUs have to make sure they don't do (non-memory mapped) PCI config space access cycles. This has actually been an issue before and it is a very bad idea to run rom stage on all CPUs. reading CMOS_BOOT_BYTE should be fine. Writing to it should only happen on the BSP. A lot of K8 boards send their non-BSP processors to sleep in romstage. Stefan From gerrit at coreboot.org Tue Nov 22 08:41:32 2011 From: gerrit at coreboot.org (QingPei Wang (wangqingpei@gmail.com)) Date: Tue, 22 Nov 2011 08:41:32 +0100 Subject: [coreboot] New patch to review for coreboot: 8bb1751 Mirror Fix coreinfo usage of cb_info References: Message-ID: QingPei Wang (wangqingpei at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/441 -gerrit commit 8bb17510476ea1abaf941d443771fc95a2e849e3 Author: QingPei Wang Date: Tue Nov 22 15:24:12 2011 +0800 Mirror Fix coreinfo usage of cb_info fix cb_info.serial.ioport to cb_info.serial.baseaddr Change-Id: I32f261e4be927555979eb833d0251fce2c6a5c47 Signed-off-by: QingPei Wang --- payloads/coreinfo/coreboot_module.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index c8694f4..dd589ac 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -68,7 +68,7 @@ int coreboot_module_redraw(WINDOW *win) if (cb_info.serial.tag != 0x0) { mvwprintw(win, row++, 1, "Serial Port I/O base: 0x%x", - cb_info.serial.ioport); + cb_info.serial.baseaddr); } if (cb_info.console.tag != 0x0) { From gerrit at coreboot.org Tue Nov 22 11:17:09 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 22 Nov 2011 11:17:09 +0100 Subject: [coreboot] Patch merged into coreboot/master: 0ac8b94 Fix post_code in 16bit entry References: Message-ID: the following patch was just integrated into master: commit 0ac8b94d07a5b2f4f8bced6f17c44816f79c5b55 Author: Ky??sti M??lkki Date: Mon Nov 21 08:16:20 2011 +0200 Fix post_code in 16bit entry Relocate early post_code() so it gets executed and does not corrupt BIST at %eax. Change-Id: Ieeebcb23f7c327e501b410eaa60d1e49110ee988 Signed-off-by: Ky??sti M??lkki Reviewed-By: Patrick Georgi at Tue Nov 22 11:17:07 2011, giving +2 See http://review.coreboot.org/439 for details. -gerrit From gerrit at coreboot.org Tue Nov 22 14:14:07 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 22 Nov 2011 14:14:07 +0100 Subject: [coreboot] New patch to review for coreboot: 47c17ed Fix CMOS handling for non-USE_OPTION_TABLE configuration References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/442 -gerrit commit 47c17ed4903029017a2e2cce390e549e3dce7f19 Author: Patrick Georgi Date: Tue Nov 22 10:27:24 2011 +0100 Fix CMOS handling for non-USE_OPTION_TABLE configuration The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols, which fail without an option table (as no option_table.h defines them). Discard them by using a macro instead of a static inline function. Change-Id: I8d001f971681277a344b6788725746491546b607 Signed-off-by: Patrick Georgi --- src/include/pc80/mc146818rtc.h | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index d6dcf01..3e5a61a 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -116,8 +116,7 @@ unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); static inline int set_option(const char *name __attribute__((unused)), void *val __attribute__((unused))) { return -2; }; static inline int get_option(void *dest __attribute__((unused)), const char *name __attribute__((unused))) { return -2; } -static inline unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) - { return def; } +#define read_option_lowlevel(start, size, def) def #endif #else #include From gerrit at coreboot.org Tue Nov 22 14:14:16 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 22 Nov 2011 14:14:16 +0100 Subject: [coreboot] New patch to review for coreboot: c7965e3 i82801gx: Use CMOS variable if available for power-on on power failure References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/443 -gerrit commit c7965e36565a1674eb8fbb7167b5390dd543a3a4 Author: Patrick Georgi Date: Tue Nov 22 10:28:46 2011 +0100 i82801gx: Use CMOS variable if available for power-on on power failure We used a hard coded value for some reason. Don't do that, but use CMOS instead. Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7 Signed-off-by: Patrick Georgi --- src/southbridge/intel/i82801gx/smihandler.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 48375e4..85ee2b4 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -279,11 +279,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat u8 reg8; u32 reg32; u8 slp_typ; - /* FIXME: the power state on boot should be read from - * CMOS or even better from GNVS. Right now it's hard - * coded at compile time. - */ + u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&s5pwr, "power_on_after_fail"); /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); From gerrit at coreboot.org Tue Nov 22 14:14:17 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 22 Nov 2011 14:14:17 +0100 Subject: [coreboot] New patch to review for coreboot: 66e420b i82801gx: Support power-on-after-power-fail better References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/444 -gerrit commit 66e420bb2be78c6062c2b5a7266f9c56b5abd911 Author: Patrick Georgi Date: Tue Nov 22 10:52:43 2011 +0100 i82801gx: Support power-on-after-power-fail better Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615 Signed-off-by: Patrick Georgi --- src/southbridge/intel/i82801gx/smihandler.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 85ee2b4..a021d1f 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -310,16 +310,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat outl(0, pmbase + GPE0_EN); - /* Should we keep the power state after a power loss? - * In case the setting is "ON" or "OFF" we don't have - * to do anything. But if it's "KEEP" we have to switch - * to "OFF" before entering S5. + /* Always set the flag in case CMOS was changed on runtime. For + * "KEEP", switch to "OFF" - KEEP is software emulated */ - if (s5pwr == MAINBOARD_POWER_KEEP) { - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + if (s5pwr == MAINBOARD_POWER_ON) { + reg8 &= ~1; + } else { reg8 |= 1; - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); } + pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); From gerrit at coreboot.org Tue Nov 22 14:14:24 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 22 Nov 2011 14:14:24 +0100 Subject: [coreboot] New patch to review for coreboot: 38d51a3 libpayload: add set_option() function References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/445 -gerrit commit 38d51a3033e667fbde619793de3f8dc127669da6 Author: Patrick Georgi Date: Tue Nov 22 13:07:45 2011 +0100 libpayload: add set_option() function It allows to change CMOS values from payloads Change-Id: I4872fc27476923adafe13504126235b92b30de85 Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/options.c | 57 ++++++++++++++++++++++++++++-- payloads/libpayload/include/libpayload.h | 1 + 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 394c792..e3f0847 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -91,7 +91,36 @@ static int get_cmos_value(u32 bitnum, u32 len, void *valptr) return 0; } -int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name) +static int set_cmos_value(u32 bitnum, u32 len, void *valptr) +{ + u8 *value = (u8 *)valptr; + int offs = 0; + u32 addr, bit; + u8 reg8; + + /* Convert to byte borders */ + addr=(bitnum / 8); + bit=(bitnum % 8); + + /* Handle single byte or less */ + if (len <= 8) { + reg8 = nvram_read(addr); + reg8 &= ~(((1 << len) - 1) << bit); + reg8 |= (value[0] & ((1 << len) - 1)) << bit; + nvram_write(reg8, addr); + return 0; + } + + /* When handling more than a byte, copy whole bytes */ + while (len > 0) { + len -= 8; + nvram_write(value[offs++], addr++); + } + + return 0; +} + +static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, char *name) { struct cb_cmos_entries *cmos_entry; int len = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -103,6 +132,17 @@ int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char cmos_entry = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size)) { if (memcmp((const char*)cmos_entry->name, name, len)) continue; + return cmos_entry; + } + + printf("ERROR: No such CMOS option (%s)\n", name); + return NULL; +} + +int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name) +{ + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); + if (cmos_entry) { if(get_cmos_value(cmos_entry->bit, cmos_entry->length, dest)) return 1; @@ -111,8 +151,6 @@ int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char return 0; } - - printf("ERROR: No such CMOS option (%s)\n", name); return 1; } @@ -121,3 +159,16 @@ int get_option(void *dest, char *name) struct cb_cmos_option_table *option_table = phys_to_virt(lib_sysinfo.option_table); return get_option_from(option_table, dest, name); } + +int set_option(void *value, char *name) +{ + struct cb_cmos_option_table *option_table = phys_to_virt(lib_sysinfo.option_table); + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); + if (cmos_entry) { + set_cmos_value(cmos_entry->bit, cmos_entry->length, value); + fix_options_checksum(); + return 0; + } + return 1; +} + diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 0e892c8..8c8abc4 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -197,6 +197,7 @@ void video_console_set_cursor(unsigned int cursorx, unsigned int cursory); void fix_options_checksum(void); int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name); int get_option(void *dest, char *name); +int set_option(void *value, char *name); /** * @defgroup console Console functions From kyosti.malkki at gmail.com Tue Nov 22 18:05:08 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Tue, 22 Nov 2011 19:05:08 +0200 Subject: [coreboot] Init for multi-processor In-Reply-To: References: <1321906818.7164.13.camel@obelix> <4ECAC30F.8030602@coreboot.org> <1321941661.7164.137.camel@obelix> Message-ID: <1321981508.7164.154.camel@obelix> On Tue, 2011-11-22 at 15:17 +0900, Stefan Reinauer wrote: > On Tue, 22 Nov 2011 08:01:01 +0200, Ky?sti M?lkki wrote: > > On Tue, 2011-11-22 at 06:30 +0900, Stefan Reinauer wrote: > >> On 11/22/11 5:20 AM, Ky?sti M?lkki wrote: > >> > Hi > >> > > >> > Could someone explain the use of boot_cpu() in bootblock_normal.c > >> > main()? I thought only the BSP CPU executes this code (currently)? > >> > > >> > I am about to push a change that does early SMP init for > >> hyper-threading > >> > CPUs to allow cache-as-ram implementation. Shared cache remains > >> disabled > >> > until both/all logical CPUs enable it. > >> > > >> For some CPUs types (like AMD K8) all CPUs / cores start running the > >> reset vector code after power-on. > >> > >> Stefan > > > > Do the BSP CPU and/or AP CPUs execute bootblock_normal: main() and > > mainboard/romstage: cache_as_ram_main() in parallel then? > > > > Remember there are no semaphores for shared resources like > > CMOS_BOOT_BYTE in do_normal_boot() nor any spinlocks for > > pci_write_config() etc. > > non-AP CPUs have to make sure they don't do (non-memory mapped) PCI > config space access cycles. > This has actually been an issue before and it is a very bad idea to run > rom stage on all CPUs. > reading CMOS_BOOT_BYTE should be fine. Writing to it should only happen > on the BSP. > > A lot of K8 boards send their non-BSP processors to sleep in romstage. > > Stefan Then the current bootblock_normal.c and bootblock_common.h are a bit questionable, also AP CPUs do CMOS writes. Reading CMOS is safe only as long as just that one CMOS_BOOT_BYTE is addressed. The bootblock_common.h directives redefine boot_cpu(). I would understand a non-SMP case where the only CPU may not have a lapic, but otherwise, why? Ky?sti From gerrit at coreboot.org Tue Nov 22 19:17:23 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 22 Nov 2011 19:17:23 +0100 Subject: [coreboot] New patch to review for coreboot: 4f13c1e Only BSP CPU writes CMOS in bootblock code References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/446 -gerrit commit 4f13c1e5ae4dc77e33b30af056fcdee4fea892e8 Author: Ky?sti M?lkki Date: Tue Nov 22 19:20:22 2011 +0200 Only BSP CPU writes CMOS in bootblock code CMOS accesses are not safe for multi-processor and only the BSP CPU should count reboots and test CMOS sanity. A questionable single byte CMOS read access from AP CPUs remains. Change-Id: I29118e33c07c0080c94abb90f703e38312c72432 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/init/bootblock_normal.c | 18 ++++++++++++++---- src/arch/x86/init/bootblock_simple.c | 4 ++-- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c index db9d0f9..a0b7b37 100644 --- a/src/arch/x86/init/bootblock_normal.c +++ b/src/arch/x86/init/bootblock_normal.c @@ -3,18 +3,28 @@ static void main(unsigned long bist) { + unsigned long entry; + int boot_mode; + if (boot_cpu()) { bootblock_northbridge_init(); bootblock_southbridge_init(); bootblock_cpu_init(); - } #if CONFIG_USE_OPTION_TABLE - sanitize_cmos(); + sanitize_cmos(); #endif + boot_mode = do_normal_boot(); + } else { + + /* Questionable single byte read from CMOS. + * Do not add any other CMOS access in the + * bootblock for AP CPUs. + */ + boot_mode = last_boot_normal(); + } - unsigned long entry; - if (do_normal_boot()) + if (boot_mode) entry = findstage("normal/romstage"); else entry = findstage("fallback/romstage"); diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 5d7c611..41f73b4 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -6,11 +6,11 @@ static void main(unsigned long bist) bootblock_northbridge_init(); bootblock_southbridge_init(); bootblock_cpu_init(); - } #if CONFIG_USE_OPTION_TABLE - sanitize_cmos(); + sanitize_cmos(); #endif + } const char* target1 = "fallback/romstage"; unsigned long entry; From gerrit at coreboot.org Tue Nov 22 19:17:24 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 22 Nov 2011 19:17:24 +0100 Subject: [coreboot] New patch to review for coreboot: 25a3cef Bootblock does not need a unique boot_cpu() References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/447 -gerrit commit 25a3cef94d64e5aa954e9b61dd9432c1acc2d230 Author: Ky?sti M?lkki Date: Tue Nov 22 19:44:45 2011 +0200 Bootblock does not need a unique boot_cpu() Detection of a CPU being a BSP CPU is not dependent of the existence of northbridge and/or southbridge init code in the bootblock. Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP CPU of a hyper-threading CPU and needs to return actual BSP bit from MSR. Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/include/bootblock_common.h | 5 ----- src/cpu/x86/lapic/boot_cpu.c | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h index 4c4a092..bd19682 100644 --- a/src/arch/x86/include/bootblock_common.h +++ b/src/arch/x86/include/bootblock_common.h @@ -1,9 +1,4 @@ -#if CONFIG_LOGICAL_CPUS && \ - (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) #include -#else -#define boot_cpu(x) 1 -#endif #ifdef CONFIG_BOOTBLOCK_CPU_INIT #include CONFIG_BOOTBLOCK_CPU_INIT diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index bca73e1..87418d0 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -1,5 +1,6 @@ #include +#if CONFIG_SMP static int boot_cpu(void) { int bsp; @@ -8,3 +9,7 @@ static int boot_cpu(void) bsp = !!(msr.lo & (1 << 8)); return bsp; } +#else +#define boot_cpu(x) 1 +#endif + From gerrit at coreboot.org Tue Nov 22 19:40:44 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 22 Nov 2011 19:40:44 +0100 Subject: [coreboot] Patch set updated for coreboot: 1e2bec3 Remove unused code files and cosmetic changes References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/440 -gerrit commit 1e2bec3cb90b23b7b69236c14b882b771e431bdc Author: Ky?sti M?lkki Date: Tue Nov 22 20:21:06 2011 +0200 Remove unused code files and cosmetic changes Following files were no longer used in the build and are deleted: src/arch/x86/init/entry.S src/arch/x86/init/ldscript.ld Also fix ugly whitespace in code copyrights and comments. Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b Signed-off-by: Ky?sti M?lkki --- src/arch/x86/init/entry.S | 149 ----------------------------------------- src/arch/x86/init/ldscript.ld | 40 ----------- src/cpu/x86/16bit/entry16.inc | 57 ++++++++-------- 3 files changed, 29 insertions(+), 217 deletions(-) diff --git a/src/arch/x86/init/entry.S b/src/arch/x86/init/entry.S deleted file mode 100644 index af29296..0000000 --- a/src/arch/x86/init/entry.S +++ /dev/null @@ -1,149 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 1999 Ronald G. Minnich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include - .code16 - .globl _stage0 -_stage0: - cli - - /* Save the BIST result. */ - movl %eax, %ebp; - - /* thanks to kmliu at sis.com.tw for this TLB fix */ - /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before - * executing any further code. Even though paging is disabled we - * could still get false address translations due to the TLB if we - * didn't invalidate it. - */ - xorl %eax, %eax - movl %eax, %cr3 /* Invalidate TLB. */ - - /* Switch to protected mode. */ - - /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) - * using BFD version 2.15.94.0.2.2 20041220 this works fine without all - * the ld hackery and other things. So leave it as is with this comment. - */ - - data32 lgdt %cs:gdtptr - - movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 - - /* Restore BIST result. */ - movl %ebp, %eax - - // port80_post(0x23) - /* Now we are in protected mode. Jump to a 32 bit code segment. */ - data32 ljmp $ROM_CODE_SEG, $protected_stage0 - - /* I am leaving this weird jump in here in the event that future gas - * bugs force it to be used. - */ - /* .byte 0x66 */ - .code32 - /* ljmp $ROM_CODE_SEG, $protected_stage0 */ - - /* .code16 */ - .align 4 - .globl gdt16 -gdt16 = . - _stage0 -gdt16x: - .word gdt16xend - gdt16x -1 /* Compute the table limit. */ - .long gdt16x - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 -gdt16xend: - - /* From now on we are 32 bit. */ - .code32 - - /* We have two gdts where we could have one. That is ok. - * - * Let's not worry about this -- optimizing gdt is pointless since - * we're only in it for a little bit. - * - * Btw. note the trick below: The GDT points to ITSELF, and the first - * good descriptor is at offset 8. So you word-align the table, and - * then because you chose 8, you get a nice 64-bit aligned GDT entry, - * which is good as this is the size of the entry. - * Just in case you ever wonder why people do this. - */ - .align 4 - .globl gdtptr - .globl gdt_limit -gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ - -gdt: -gdtptr: - .word gdt_end - gdt -1 /* Compute the table limit. */ - .long gdt /* We know the offset. */ - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - -gdt_end: - -/* Reset vector. */ - -/* - * RVECTOR: Size of reset vector, default is 0x10. - * RESRVED: Size of vpd code, default is 0xf0. - * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b). - */ - -SEGMENT_SIZE = 0x10000 -RVECTOR = 0x00010 - -/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here. - * I think we should leave it this way forever, as the bugs come and - * go -- and come again. - * - * .code16 - * .section ".rom.text" - */ -.section ".reset", "ax" - .globl _resetjump -_resetjump: - /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */ - /* jmp _stage0 */ - .byte 0xe9 - .int _stage0 - ( . + 2 ) - - /* Note: The above jump is hand coded to work around bugs in binutils. - * 5 bytes are used for a 3 byte instruction. This works because x86 - * is little endian and allows us to use supported 32 bit relocations - * instead of the weird 16 bit relocations that binutils does not - * handle consistenly between versions because they are used so rarely. - */ diff --git a/src/arch/x86/init/ldscript.ld b/src/arch/x86/init/ldscript.ld deleted file mode 100644 index 149f048..0000000 --- a/src/arch/x86/init/ldscript.ld +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Ronald G. Minnich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -TARGET(binary) -SECTIONS -{ - /DISCARD/ : { - *(.comment) - *(.note.*) - *(.note) - } -} - -SECTIONS { - _ROMTOP = 0xfffffff0; - . = _ROMTOP; - .resetvector . : { - *(.reset) - . = 15 ; - BYTE(0x00); - } -} - diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 9b7b69c..fb21155 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -1,31 +1,32 @@ /* -This software and ancillary information (herein called SOFTWARE ) -called LinuxBIOS is made available under the terms described -here. The SOFTWARE has been approved for release with associated -LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has -been authored by an employee or employees of the University of -California, operator of the Los Alamos National Laboratory under -Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The -U.S. Government has rights to use, reproduce, and distribute this -SOFTWARE. The public may copy, distribute, prepare derivative works -and publicly display this SOFTWARE without charge, provided that this -Notice and any statement of authorship are reproduced on all copies. -Neither the Government nor the University makes any warranty, express -or implied, or assumes any liability or responsibility for the use of -this SOFTWARE. If SOFTWARE is modified to produce derivative works, -such modified SOFTWARE should be clearly marked, so as not to confuse -it with the version available from LANL. - */ -/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL - * rminnich at lanl.gov + * This software and ancillary information (herein called SOFTWARE) + * called LinuxBIOS is made available under the terms described here. + * + * The SOFTWARE has been approved for release with associated + * LA-CC Number 00-34. Unless otherwise indicated, this SOFTWARE has + * been authored by an employee or employees of the University of + * California, operator of the Los Alamos National Laboratory under + * Contract No. W-7405-ENG-36 with the U.S. Department of Energy. + * + * The U.S. Government has rights to use, reproduce, and distribute this + * SOFTWARE. The public may copy, distribute, prepare derivative works + * and publicly display this SOFTWARE without charge, provided that this + * Notice and any statement of authorship are reproduced on all copies. + * + * Neither the Government nor the University makes any warranty, express + * or implied, or assumes any liability or responsibility for the use of + * this SOFTWARE. If SOFTWARE is modified to produce derivative works, + * such modified SOFTWARE should be clearly marked, so as not to confuse + * it with the version available from LANL. + * + * Copyright (C) 2000, Ron Minnich rminnich at lanl.gov + * Advanced Computing Lab, LANL */ -/** Start code to put an i386 or later processor into 32-bit - * protected mode. +/* Start code to put an i386 or later processor into 32-bit protected mode. */ -/* .section ".rom.text" */ #include .code16 .globl _start @@ -38,12 +39,12 @@ _start: post_code(POST_RESET_VECTOR_CORRECT) -/* thanks to kmliu at sis.tw.com for this TBL fix ... */ -/**/ -/* IMMEDIATELY invalidate the translation lookaside buffer before executing*/ -/* any further code. Even though paging is disabled we could still get*/ -/*false address translations due to the TLB if we didn't invalidate it.*/ -/**/ + /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before + * executing any further code. Even though paging is disabled we + * could still get false address translations due to the TLB if we + * didn't invalidate it. Thanks to kmliu at sis.com.tw for this TLB fix. + */ + xorl %eax, %eax movl %eax, %cr3 /* Invalidate TLB*/ From dspjm1 at gmail.com Tue Nov 22 17:41:05 2011 From: dspjm1 at gmail.com (Jimmy Pan) Date: Wed, 23 Nov 2011 00:41:05 +0800 Subject: [coreboot] (no subject) In-Reply-To: References: Message-ID: Sorry for the spam here, my email account was stolen. On Mon, Nov 21, 2011 at 11:22 PM, Jimmy Pan wrote: > ..Do you want to feel something new? Do you want to feel new > unforgettable sensations? This is for you! > http://un-ocean.fr/p.g.php?wellink_friend_id=14ox0 > From sibradzic at gmail.com Tue Nov 22 20:34:19 2011 From: sibradzic at gmail.com (=?UTF-8?B?U2FtaXIgSWJyYWTFvmnEhw==?=) Date: Wed, 23 Nov 2011 04:34:19 +0900 Subject: [coreboot] Issues with Supermicro H8SCM In-Reply-To: References: <20111014212645.GA29984@coreboot.org> <20111017224402.GA20387@coreboot.org> <4EC93A45.9040406@gmail.com> Message-ID: <4ECBF93B.5060505@gmail.com> Kairui, I honestly appreciate your help. On 2011?11?21? 12:00, She, Kerry wrote: > Hello, Samir > >> -----Original Message----- >> From: Samir Ibrad?i? [mailto:sibradzic at gmail.com] >> Sent: Monday, November 21, 2011 1:35 AM >> To: She, Kerry >> Cc: Thomas Gst?dtner; Marc Jones; coreboot >> Subject: Re: [coreboot] Issues with Supermicro H8SCM >> >> Hello Kerry, Thomas, Marc, >> >> I got this board for a personal server project, as well as test platform >> to dive into coreboot. Board is H8SCM-F rev 1.02, one with BMC. Had >> build nice external FT2232 programmer for bailing out of broken flash >> situation, works great. I've experimented with recent coreboot revision, >> ea5c2b6 + Kerry's AGESA patches (thanks a bunch!), and had experienced >> same problem as Thomas, plus some more; >> >> 1. Two DIMMs in dual-channel setup wont work, same issue as Thomas, >> 2x4GB ECC DIMMs here. > > >> 2. After booting via coreboot with same Linux distro, SR5850 NorthBridge >> heatsink instantly gets much more hot than booting via SuperMicro BIOS. >> The temperature is MUCH higher, on idle system, though i can not measure >> this by other method than putting my finger there, and i got instantly >> BURNED when coreboot is being used. I am afraid to fry my board if it >> runs longer this way, it is really that hot. > The hardware monitor is not enable in coreboot. Not sure what do you mean by that. SR56x0 power management is not working in coreboot? It really gets dangerously hot. If only there was some workaround for this, i would switch 100% to corebot. > >> 3. HPET is not being reported at all by coreboot ACPI, OS timer >> precision suffers big deal. Dont know if this is a feature or bug? Dmesg >> clearly shows the difference, all these lines are missing when booting >> via coreboot: >> >> # dmesg | grep -i hpet >> [ 0.000000] ACPI: HPET 00000000cfeaa5e0 00038 (v01 062911 OEMHPET >> 20110629 MSFT 00000097) >> [ 0.000000] ACPI: HPET id: 0x8300 base: 0xfed00000 >> [ 0.000000] hpet clockevent registered >> [ 1.132106] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 >> [ 1.140072] hpet0: 4 comparators, 32-bit 14.318180 MHz counter >> [ 1.146104] Switching to clocksource hpet >> [ 3.499557] rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet >> irqs >> Nothing about this? >> 4. CPU (got 4170 HE) frequency scaling only goes as low as 1800MHz in >> coreboot when idle. SuperMicro BIOS easily goes all the way down to >> 800MHz. Spotted this in /proc/cpuinfo >> >> 5. USB/EHCI - i haven't really tested this, but it seems minor compared >> to 1& 2. > > Kevin have fixed some usb-msc bugs in seabios recently, > you may need to check the seabios maillist. > >> Now, i know this board is not exactly supported, most probably being an >> AGESA problem, but i would really like to do my best to help to make it >> work better if possible. >> >> >> @ Kerry, >> >> I was trying to analyze some AGESA code to get to the DIMM problem, but >> most of it is a mystery to me. Could you please point me to the right >> place for "DRAM training" in the code, i am willing to invest some time >> and nerves to test& investigate this, as well as NB overheating >> problem. Any plans to update those AGESA patches for this board? > > We have made some update for h8scm mainboard. > In order to support new Orochi platform, > Except the mainboard code, agesa wrapper, sr56x0 cimx wrapper and > sb700/sp5100 cimx wrapper are also included in the change set. > But the patch set still pending to release to the community for review. > We need some time to get the release process done. > Hope the code would be available soon. > I am really looking forward for this update. Latest coreboot git head will not compile with your previous patches, something got broken again. >> One strange thing about RAM init is that the coreboot somehow thinks the >> board has 8 slots, but it has only four (there should be no channels 2& >> 3); > > AGESA support 4 channels. > But family10 processor for h8scm only have 2 channels. > >> Socket 0 Channel 0 Dimm 0 found dimm: 00400745 >> Socket 0 Channel 0 Dimm 1 not found dimm >> Socket 0 Channel 1 Dimm 0 found dimm: 00400947 >> Socket 0 Channel 1 Dimm 1 not found dimm >> Socket 0 Channel 2 Dimm 0 not found dimm >> Socket 0 Channel 2 Dimm 1 not found dimm >> Socket 0 Channel 3 Dimm 0 not found dimm >> Socket 0 Channel 3 Dimm 1 not found dimm >> Dct 0 Channel 0 >> RegDimmPresent: 1 >> SODimmPresent: 0 >> ChDimmValid: 1 >> DimmPlPresent: 0 >> DimmQrPresent: 0 >> DimmDrPresent: 0 >> DimmSRPresent: 1 >> Dimmx4Present: 1 >> DimmX8Present: 0 >> DimmX16Present: 0 >> DimmMirrorPresent: 0 >> Dct 1 Channel 0 >> RegDimmPresent: 1 >> SODimmPresent: 0 >> ChDimmValid: 1 >> DimmPlPresent: 0 >> DimmQrPresent: 0 >> DimmDrPresent: 0 >> DimmSRPresent: 1 >> Dimmx4Present: 1 >> DimmX8Present: 0 >> DimmX16Present: 0 >> DimmMirrorPresent: 0 >> ASSERTION FAILED: file >> 'src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c', line 163 > > Maybe a dimm spd address problem, you can try following patch: > --- a/src/mainboard/supermicro/h8scm_fam10/dimmSpd.c > +++ b/src/mainboard/supermicro/h8scm_fam10/dimmSpd.c > @@ -55,8 +55,11 @@ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) > static const UINT8 spdAddressLookup [1] [2] [2] = { // socket, channel, dimm > /* socket 0 */ > { > - {0xA6, 0xA4}, > - {0xA2, 0xA0}, > + /* silkprint: DIMM1A DIMM2A DIMM1B DIMM2B > + * i2c addr: A6 A2 A4 A0 > + */ > + {0xA4, 0xA6}, > + {0xA0, 0xA2}, > }, > }; Tested-by: Samir Ibrad?i? Thanks, looks like this had fixed the issue! Socket 0 Channel 0 Dimm 0 not found dimm Socket 0 Channel 0 Dimm 1 found dimm: 00400846 Socket 0 Channel 1 Dimm 0 not found dimm Socket 0 Channel 1 Dimm 1 found dimm: 00400a48 Socket 0 Channel 2 Dimm 0 not found dimm Socket 0 Channel 2 Dimm 1 not found dimm Socket 0 Channel 3 Dimm 0 not found dimm Socket 0 Channel 3 Dimm 1 not found dimm Dct 0 Channel 0 RegDimmPresent: 2 SODimmPresent: 0 ChDimmValid: 2 DimmPlPresent: 0 DimmQrPresent: 0 DimmDrPresent: 0 DimmSRPresent: 2 Dimmx4Present: 2 DimmX8Present: 0 DimmX16Present: 0 DimmMirrorPresent: 0 Dct 1 Channel 0 RegDimmPresent: 2 SODimmPresent: 0 ChDimmValid: 2 DimmPlPresent: 0 DimmQrPresent: 0 DimmDrPresent: 0 DimmSRPresent: 2 Dimmx4Present: 2 DimmX8Present: 0 DimmX16Present: 0 DimmMirrorPresent: 0 BSP Frequency: 2100MHz agesawrapper_amdinitpost passed agesawrapper_amdinitenv passed > > Thanks > Kerry Thanks, Samir From gerrit at coreboot.org Tue Nov 22 21:37:07 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Tue, 22 Nov 2011 21:37:07 +0100 Subject: [coreboot] New patch to review for coreboot: 5b687b2 k8 raminit: add workaround for erratum #181 on non-fam-f References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/448 -gerrit commit 5b687b2c7ab6c1ca9647e9e714f87a619029777f Author: Florian Zumbiehl Date: Tue Nov 22 21:32:31 2011 +0100 k8 raminit: add workaround for erratum #181 on non-fam-f Disable DRAM controller on non-fam-f CPUs not using fam-f register layout. Change-Id: I2cc87857452555011d69bfebe9f9c4c17cef8f6c Signed-off-by: Florian Zumbiehl --- src/cpu/amd/model_fxx/fidvid.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 6395a1e..06ff636 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -45,10 +45,19 @@ static void enable_fid_change(void) pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0xd4, dword); /* disable the DRAM interface at first, it will be enabled - * by raminit again */ + * by raminit again (see also erratum #181) */ +#if CONFIG_K8_REV_F_SUPPORT dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94); dword |= (1 << 14); pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword); +#else + dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x90); + dword |= (1 << 24); + pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x90, dword); + dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94); + dword |= (1 << 25); + pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword); +#endif dword = 0x23070700; /* enable FID/VID change */ // dword = 0x00070000; /* enable FID/VID change */ From gerrit at coreboot.org Tue Nov 22 21:37:07 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Tue, 22 Nov 2011 21:37:07 +0100 Subject: [coreboot] Patch set updated for coreboot: 2cc61ee make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 2cc61ee0fcf4305e54cb12949bb79c325e1b0a74 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 5aac518..ceb6d2c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Tue Nov 22 21:37:08 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Tue, 22 Nov 2011 21:37:08 +0100 Subject: [coreboot] Patch set updated for coreboot: 75cc36e make INT[EFGH]# of vt8237 configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 75cc36ec6a857bfcd6701e3662f5ba0efb1abc95 Author: Florian Zumbiehl Date: Mon Nov 21 03:10:47 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 207dfdb..5aac518 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,10 +429,13 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; #if !CONFIG_EPIA_VT8237R_INIT unsigned char pwr_on; #endif + cfg = dev->chip_info; + /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); byte |= PCI_COMMAND_WAIT; @@ -509,7 +520,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } /* configure power state of the board after loss of power */ if (get_option(&pwr_on, "power_on_after_fail") < 0) From gerrit at coreboot.org Tue Nov 22 21:37:08 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Tue, 22 Nov 2011 21:37:08 +0100 Subject: [coreboot] Patch set updated for coreboot: e233152 implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit e233152c3a7ca9c217981cd65a8cbbd27d64ad56 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..2bdcf9d 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | + (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | + (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | + (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | + (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, + (pci_read_config8(dev, 0x5c) & ~0x70) | + (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Tue Nov 22 21:37:09 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Tue, 22 Nov 2011 21:37:09 +0100 Subject: [coreboot] Patch set updated for coreboot: 2f4e649 implement hwmon fan divisor setting for w83697hf References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit 2f4e6497a7f625e2dc8fe44f2c77fc655e7d41e5 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 34 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..8f090d0 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,44 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + /* the above inb() auto-increments the address pointer ... */ + outb(0x5d, base + 5); + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev) From gerrit at coreboot.org Tue Nov 22 21:37:09 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Tue, 22 Nov 2011 21:37:09 +0100 Subject: [coreboot] Patch set updated for coreboot: 07516df adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 07516df69f509f4b30c62a4443850e446f25e696 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 20 ++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 115 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..d297143 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,24 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +42,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +72,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Tue Nov 22 21:37:10 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Tue, 22 Nov 2011 21:37:10 +0100 Subject: [coreboot] Patch set updated for coreboot: 4d88dfe vt8237: add support for setting the power state after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/437 -gerrit commit 4d88dfe002949512b83316a5e242f431f8b422fe Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 vt8237: add support for setting the power state after loss of power Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/lpc.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..207dfdb 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -421,6 +421,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; +#if !CONFIG_EPIA_VT8237R_INIT + unsigned char pwr_on; +#endif /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -508,6 +511,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); + /* configure power state of the board after loss of power */ + if (get_option(&pwr_on, "power_on_after_fail") < 0) + pwr_on = 1; + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(pwr_on ? 0x00 : 0x80, 0x71); + pci_write_config8(dev, 0x58, enables); + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Tue Nov 22 21:37:11 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Tue, 22 Nov 2011 21:37:11 +0100 Subject: [coreboot] Patch set updated for coreboot: f4a8bfb copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit f4a8bfba0f644a9544f9f4a56ed51b6407b124ee Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Tue Nov 22 21:37:12 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Tue, 22 Nov 2011 21:37:12 +0100 Subject: [coreboot] Patch set updated for coreboot: 6292139 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 6292139eaafae8b0473b88cea457c3ef519d7dbf Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 3180412..6e5dbf7 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -51,12 +51,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -151,7 +160,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From gerrit at coreboot.org Tue Nov 22 22:20:32 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 22 Nov 2011 22:20:32 +0100 Subject: [coreboot] Patch merged into coreboot/master: 5b687b2 k8 raminit: add workaround for erratum #181 on non-fam-f References: Message-ID: the following patch was just integrated into master: commit 5b687b2c7ab6c1ca9647e9e714f87a619029777f Author: Florian Zumbiehl Date: Tue Nov 22 21:32:31 2011 +0100 k8 raminit: add workaround for erratum #181 on non-fam-f Disable DRAM controller on non-fam-f CPUs not using fam-f register layout. Change-Id: I2cc87857452555011d69bfebe9f9c4c17cef8f6c Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Tue Nov 22 21:51:53 2011, giving +1 Reviewed-By: Marc Jones at Tue Nov 22 22:20:30 2011, giving +2 See http://review.coreboot.org/448 for details. -gerrit From gerrit at coreboot.org Tue Nov 22 23:07:12 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 22 Nov 2011 23:07:12 +0100 Subject: [coreboot] Patch merged into coreboot/master: 2f4e649 implement hwmon fan divisor setting for w83697hf References: Message-ID: the following patch was just integrated into master: commit 2f4e6497a7f625e2dc8fe44f2c77fc655e7d41e5 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Tue Nov 22 22:46:03 2011, giving +1 Reviewed-By: Rudolf Marek at Tue Nov 22 22:34:56 2011, giving +2 See http://review.coreboot.org/384 for details. -gerrit From gerrit at coreboot.org Wed Nov 23 00:26:26 2011 From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz)) Date: Wed, 23 Nov 2011 00:26:26 +0100 Subject: [coreboot] New patch to review for coreboot: 3344880 Fix the DIMM slot mapping References: Message-ID: Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/449 -gerrit commit 3344880a57c8e1083f5580d6990885f3b976ae6c Author: Rudolf Marek Date: Wed Nov 23 00:23:43 2011 +0100 Fix the DIMM slot mapping Fix the DIMM mappings, channel 0 is "B" on board, and secondary channel is on 0x51,0x53 Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a Signed-off-by: Rudolf Marek --- src/mainboard/asus/a8v-e_se/romstage.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 4e08859..4193452 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -147,10 +147,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + DIMM1, DIMM3, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; From gerrit at coreboot.org Wed Nov 23 01:05:41 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 23 Nov 2011 01:05:41 +0100 Subject: [coreboot] Patch merged into coreboot/master: d7bcac8 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 References: Message-ID: the following patch was just integrated into master: commit d7bcac8e6f4f20d8504563317a9e23013cac16c4 Author: Florian Zumbiehl Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Mon Nov 21 04:49:37 2011, giving +1 Reviewed-By: Rudolf Marek at Wed Nov 23 01:05:39 2011, giving +2 See http://review.coreboot.org/377 for details. -gerrit From gerrit at coreboot.org Wed Nov 23 07:32:10 2011 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 23 Nov 2011 07:32:10 +0100 Subject: [coreboot] New patch to review for coreboot: 7b5f093 south_station: Enable GNB hd audio References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/450 -gerrit commit 7b5f093920dc0918eb620bac184588333e7ef7cc Author: Kerry Sheh Date: Wed Nov 23 15:04:13 2011 +0800 south_station: Enable GNB hd audio Enable HD audio over HDMI. Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed. Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/amd/south_station/PlatformGnbPcie.c | 18 ++++++++---------- src/mainboard/amd/south_station/buildOpts.c | 2 +- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index 59d31ef..8749e3d 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -90,19 +90,17 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */ { - 0, //Descriptor flags - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeDP, Aux1, Hdp1} + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux1, Hdp1) } }; diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 48e18a6..63f12f0 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -176,7 +176,7 @@ //#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE //#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE//TRUE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE //#define BLDCFG_CFG_ABM_SUPPORT FALSE //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 From gerrit at coreboot.org Wed Nov 23 07:32:11 2011 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 23 Nov 2011 07:32:11 +0100 Subject: [coreboot] New patch to review for coreboot: 3f26722 south_station: mptable add GNB internal graphic interrupt References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/451 -gerrit commit 3f26722935da7e5267acc731dc3ca06d04bd9f3d Author: Kerry Sheh Date: Wed Nov 23 15:08:36 2011 +0800 south_station: mptable add GNB internal graphic interrupt Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/amd/south_station/mptable.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index a3b4b5c..9f3e02c 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, fn, pin) #endif + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); - /* HD Audio: */ + /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ From gerrit at coreboot.org Wed Nov 23 07:32:11 2011 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 23 Nov 2011 07:32:11 +0100 Subject: [coreboot] New patch to review for coreboot: 6fcc2b5 south_station: apic interrupt routing update References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/452 -gerrit commit 6fcc2b506dce063cde6cdd0c18b7d580c248ed05 Author: Kerry Sheh Date: Wed Nov 23 15:08:51 2011 +0800 south_station: apic interrupt routing update Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/amd/south_station/acpi/routing.asl | 59 ++++++++++++--------- 1 files changed, 34 insertions(+), 25 deletions(-) diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl index cb50394..d7e4687 100644 --- a/src/mainboard/amd/south_station/acpi/routing.asl +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -31,22 +31,28 @@ Scope(\_SB) { /* NB devices */ /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, Package(){0x0004FFFF, 2, INTC, 0 }, Package(){0x0004FFFF, 3, INTD, 0 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ Package(){0x0006FFFF, 0, INTC, 0 }, Package(){0x0006FFFF, 1, INTD, 0 }, @@ -126,41 +132,44 @@ Scope(\_SB) { /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, /* Bus 0, Dev 9 - PCIe Bridge for network card */ Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ + Package(){0x0009FFFF, 1, 0, 16 }, + Package(){0x0009FFFF, 2, 0, 17 }, + Package(){0x0009FFFF, 3, 0, 18 }, /* Bus 0, Dev A - PCIe Bridge for network card */ Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ + Package(){0x000AFFFF, 1, 0, 16 }, + Package(){0x000AFFFF, 2, 0, 17 }, + Package(){0x000AFFFF, 3, 0, 18 }, /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */ From heemeli at hotmail.com Wed Nov 23 12:30:14 2011 From: heemeli at hotmail.com (Saku Sammakko) Date: Wed, 23 Nov 2011 13:30:14 +0200 Subject: [coreboot] FWD: This Kit changed all my life... Message-ID: hey there! i have full control over my fortune http://184.106.1.65/PUB/profile/60WayneMiller/ talk to you later. -------------- next part -------------- An HTML attachment was scrubbed... URL: From paulepanter at users.sourceforge.net Wed Nov 23 13:05:52 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Wed, 23 Nov 2011 13:05:52 +0100 Subject: [coreboot] New patch to review for coreboot: 3344880 Fix the DIMM slot mapping In-Reply-To: References: Message-ID: <1322049952.3740.7.camel@mattotaupa> Am Mittwoch, den 23.11.2011, 00:26 +0100 schrieb Rudolf Marek: > Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/449 > > -gerrit > > commit 3344880a57c8e1083f5580d6990885f3b976ae6c > Author: Rudolf Marek > Date: Wed Nov 23 00:23:43 2011 +0100 > > Fix the DIMM slot mapping Maybe prefix that with ?asus a8v-e se: ??. > Fix the DIMM mappings, channel 0 is "B" on board, > and secondary channel is on 0x51,0x53 I guess you have tested that. This would make approving this patch much easier if you add that. > Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a > Signed-off-by: Rudolf Marek [?] Thanks, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From heemeli at hotmail.com Wed Nov 23 16:02:25 2011 From: heemeli at hotmail.com (Saku Sammakko) Date: Wed, 23 Nov 2011 17:02:25 +0200 Subject: [coreboot] FWD: Hey there How are you. Message-ID: Hey friend... I wasnt acting like myself thought you would take interest in this now I can be my own boss you would excell at this http://www.pupuksurpluss.com/profile/47AnthonyEdwards/ talk to you later -------------- next part -------------- An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Wed Nov 23 19:12:45 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 23 Nov 2011 19:12:45 +0100 Subject: [coreboot] Patch set updated for coreboot: fd6fdfa make GPIOs and misc configurable via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit fd6fdfa88c27551aa1169dac6616e0c7381edbb0 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index bbba5e4..5108547 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 int_efgh_as_gpio; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 43a9394..cd1064f 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -151,6 +151,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -179,7 +183,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -195,7 +202,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -247,6 +261,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -282,8 +299,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ From gerrit at coreboot.org Wed Nov 23 19:12:46 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 23 Nov 2011 19:12:46 +0100 Subject: [coreboot] Patch set updated for coreboot: 80f52b7 make INT[EFGH]# of vt8237 configurable as gpio via devicetree References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 80f52b7bcd10a5c28ffa9a7ad3e64529df6f7085 Author: Florian Zumbiehl Date: Mon Nov 21 03:10:47 2011 +0100 make INT[EFGH]# of vt8237 configurable as gpio via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 9 ++++++++- 2 files changed, 10 insertions(+), 1 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..bbba5e4 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 int_efgh_as_gpio; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 207dfdb..43a9394 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -421,10 +421,13 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; #if !CONFIG_EPIA_VT8237R_INIT unsigned char pwr_on; #endif + cfg = dev->chip_info; + /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); byte |= PCI_COMMAND_WAIT; @@ -509,7 +512,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->int_efgh_as_gpio) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } /* configure power state of the board after loss of power */ if (get_option(&pwr_on, "power_on_after_fail") < 0) From gerrit at coreboot.org Wed Nov 23 19:12:46 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 23 Nov 2011 19:12:46 +0100 Subject: [coreboot] Patch set updated for coreboot: 2797390 implement usb2 termination and dpll delay setting for vt8237r References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit 2797390a25514005e59daa6a79b7acaf123f5946 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..2bdcf9d 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | + (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | + (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | + (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | + (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, + (pci_read_config8(dev, 0x5c) & ~0x70) | + (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev) From gerrit at coreboot.org Wed Nov 23 19:12:47 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 23 Nov 2011 19:12:47 +0100 Subject: [coreboot] Patch set updated for coreboot: 9063080 adding support for the Asus K8V-X References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 9063080412ae8b7a48b89d065bdc40eeaf904c85 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 20 ++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 115 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..d297143 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,24 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +42,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +72,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..61c5a2d 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "int_efgh_as_gpio" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2010 Tobias Diedrich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include #include #include +#include +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include #include #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } From gerrit at coreboot.org Wed Nov 23 19:12:47 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 23 Nov 2011 19:12:47 +0100 Subject: [coreboot] Patch set updated for coreboot: 6382d1b vt8237: add support for setting the power state after loss of power References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/437 -gerrit commit 6382d1b4a7cc5d71f2b6d2e912dac01698147d45 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 vt8237: add support for setting the power state after loss of power Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a Signed-off-by: Florian Zumbiehl --- src/southbridge/via/vt8237r/lpc.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..207dfdb 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -421,6 +421,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; +#if !CONFIG_EPIA_VT8237R_INIT + unsigned char pwr_on; +#endif /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -508,6 +511,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); + /* configure power state of the board after loss of power */ + if (get_option(&pwr_on, "power_on_after_fail") < 0) + pwr_on = 1; + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(pwr_on ? 0x00 : 0x80, 0x71); + pci_write_config8(dev, 0x58, enables); + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43); From gerrit at coreboot.org Wed Nov 23 19:12:48 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 23 Nov 2011 19:12:48 +0100 Subject: [coreboot] Patch set updated for coreboot: 423d321 copied asus a8v-e_se to k8v-x References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit 423d3214899d68fb7e0c040b068c72517077fa4e Author: Florian Zumbiehl Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer . + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2005 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi for MSI) + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} From gerrit at coreboot.org Wed Nov 23 19:12:49 2011 From: gerrit at coreboot.org (Florian Zumbiehl) Date: Wed, 23 Nov 2011 19:12:49 +0100 Subject: [coreboot] Patch set updated for coreboot: 3fc0235 some black magic for initializing the old version of the k8t800 References: Message-ID: Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 3fc0235c1a85eb1bf977be201f5d174ce91a3196 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 3180412..6e5dbf7 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -51,12 +51,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -151,7 +160,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */ From gerrit at coreboot.org Wed Nov 23 19:39:41 2011 From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz)) Date: Wed, 23 Nov 2011 19:39:41 +0100 Subject: [coreboot] Patch set updated for coreboot: 82565a8 Fix Asus A8V-E SE DIMM slot mapping References: Message-ID: Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/449 -gerrit commit 82565a8f061bd46f0d8625a848ea49e97cba8751 Author: Rudolf Marek Date: Wed Nov 23 00:23:43 2011 +0100 Fix Asus A8V-E SE DIMM slot mapping Fix the DIMM mappings, channel 0 is "B" on board, and secondary channel is on 0x51,0x53 Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a Signed-off-by: Rudolf Marek --- src/mainboard/asus/a8v-e_se/romstage.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 4e08859..4193452 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -147,10 +147,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + DIMM1, DIMM3, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; From gerrit at coreboot.org Wed Nov 23 20:02:17 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 23 Nov 2011 20:02:17 +0100 Subject: [coreboot] New patch to review for coreboot: dcc9ad3 Fix ldscript for bootblock .rom section References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/453 -gerrit commit dcc9ad3b26c55474029db74e1f503fb6b82dedd6 Author: Ky?sti M?lkki Date: Wed Nov 23 16:33:12 2011 +0200 Fix ldscript for bootblock .rom section Allocation size for the section was miscalculated, so the section did not honour its upper-bound address. Also align the section start to 4 bytes, so it starts with code instead of pad bytes. Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d Signed-off-by: Ky?sti M?lkki --- src/arch/x86/init/ldscript_failover.lb | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 7e48dc1..83e5eb3 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,6 +29,14 @@ MEMORY { TARGET(binary) SECTIONS { + /* Align .rom to next 4 byte boundary so no pad byte appears + * between _rom and _start. + */ + .bogus ROMLOC_MIN : { + . = ALIGN(4); + ROMLOC = .; + } >rom = 0xff + /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; @@ -39,7 +47,11 @@ SECTIONS _erom = .; } >rom = 0xff - ROMLOC = 0xffffff00 - (_erom - _rom) + 1; + /* Allocation reserves extra 16 bytes here. Alignment requirements + * may cause the total size of a section to change when the start + * address gets applied. + */ + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); /DISCARD/ : { *(.comment) From gerrit at coreboot.org Wed Nov 23 20:02:22 2011 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 23 Nov 2011 20:02:22 +0100 Subject: [coreboot] New patch to review for coreboot: b76e507 Add support for RAM-less multi-processor init References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit b76e507f4d76e75df84a25b52b58e23ec029e6b0 Author: Ky?sti M?lkki Date: Wed Nov 23 20:59:57 2011 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB when Kconfig option SIPI_VECTOR_IN_ROM is set. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Ky?sti M?lkki --- src/arch/x86/Kconfig | 7 +++++++ src/arch/x86/init/ldscript_failover.lb | 13 ++++++++----- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e71d0f3..9e8e82f 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -8,6 +8,13 @@ config AP_IN_SIPI_WAIT default n depends on ARCH_X86 +# Aligns 16bit entry code in bootblock so that hyper-threading CPUs +# can boot AP CPUs to enable their shared caches. +config SIPI_VECTOR_IN_ROM + bool + default n + depends on ARCH_X86 + config ROMBASE hex default 0xffff0000 diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..6f7d6fa 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,19 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. Align .rom to next 4 byte + * boundary anyway, so no pad byte appears between _rom and _start. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); - ROMLOC = .; + . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + ROMLOC = . ; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +53,8 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - + (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); /DISCARD/ : { *(.comment) From kyosti.malkki at gmail.com Wed Nov 23 20:09:02 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Wed, 23 Nov 2011 21:09:02 +0200 Subject: [coreboot] New patch to review for coreboot: dcc9ad3 Fix ldscript for bootblock .rom section In-Reply-To: References: Message-ID: <1322075342.2031.196.camel@obelix> On Wed, 2011-11-23 at 20:02 +0100, Ky?sti M?lkki wrote: > Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/453 > build/bootblock.map without patch: fffffbfb A ROMLOC fffffc02 T _rom <-- pad bytes here fffffc04 T _start <-- (not invalid, just confusing) fffffc48 T gdtptr16 ... fffffef2 t L1005 ffffff04 t L1033 <-- over upper-bound ffffff08 T _erom build/bootblock.map with patch: fffffbe8 A ROMLOC_MIN fffffbf0 T _rom fffffbf0 T ROMLOC fffffbf0 T _start fffffc34 T gdtptr16 ... fffffee2 t L1005 fffffef4 t L1033 fffffef8 T _erom From paulepanter at users.sourceforge.net Wed Nov 23 20:49:44 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Wed, 23 Nov 2011 20:49:44 +0100 Subject: [coreboot] New patch to review for coreboot: dcc9ad3 Fix ldscript for bootblock .rom section In-Reply-To: <1322075342.2031.196.camel@obelix> References: <1322075342.2031.196.camel@obelix> Message-ID: <1322077784.3740.42.camel@mattotaupa> Am Mittwoch, den 23.11.2011, 21:09 +0200 schrieb Ky?sti M?lkki: > On Wed, 2011-11-23 at 20:02 +0100, Ky?sti M?lkki wrote: > > Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/453 > > > build/bootblock.map without patch: > > fffffbfb A ROMLOC > fffffc02 T _rom <-- pad bytes here > fffffc04 T _start <-- (not invalid, just confusing) > fffffc48 T gdtptr16 > ... > fffffef2 t L1005 > ffffff04 t L1033 <-- over upper-bound > ffffff08 T _erom > > > build/bootblock.map with patch: > > fffffbe8 A ROMLOC_MIN > fffffbf0 T _rom > fffffbf0 T ROMLOC > fffffbf0 T _start > fffffc34 T gdtptr16 > ... > fffffee2 t L1005 > fffffef4 t L1033 > fffffef8 T _erom I guess that would be useful in the commit message, would not it? Thanks, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From lewurm at gmail.com Wed Nov 23 22:29:56 2011 From: lewurm at gmail.com (Bernhard Urban) Date: Wed, 23 Nov 2011 22:29:56 +0100 Subject: [coreboot] Coreboot support for ASUS M5 A99X EVO ? In-Reply-To: References: Message-ID: Hi Chris, I reported flashrom compatibility here: http://www.flashrom.org/pipermail/flashrom/2011-October/008152.html Regarding coreboot support: I'll try to port coreboot to this board. I already have two additional flashchips and at the moment I'm waiting for a serial port connector. I don't know how long it'll talke to port it, but don't except anything useful in less than three months, since I'm new to coreboot (and lazy :-)) Bernhard On Sat, Nov 19, 2011 at 6:33 PM, Christopher Huang-Leaver wrote: > Hello, > I noticed earlier versions of this board are fully supported, but not this > one. > I have attached the output of, ?lspci, ?flashrom and dmidecode, if that is > any use to anyone. > The spec sheet is easy to find by typing ASUS M5 A99X into Google. ?The > board does have a neat feature of being able to flash the BIOS from within > the BIOS menu, which I have already used to update it. > Many thanks > Chris From gerrit at coreboot.org Thu Nov 24 00:12:42 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 24 Nov 2011 00:12:42 +0100 Subject: [coreboot] Patch merged into coreboot/master: 6382d1b vt8237: add support for setting the power state after loss of power References: Message-ID: the following patch was just integrated into master: commit 6382d1b4a7cc5d71f2b6d2e912dac01698147d45 Author: Florian Zumbiehl Date: Tue Nov 1 20:19:04 2011 +0100 vt8237: add support for setting the power state after loss of power Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a Signed-off-by: Florian Zumbiehl Build-Tested: build bot (Jenkins) at Wed Nov 23 20:20:39 2011, giving +1 Reviewed-By: Rudolf Marek at Thu Nov 24 00:12:41 2011, giving +2 See http://review.coreboot.org/437 for details. -gerrit From gerrit at coreboot.org Thu Nov 24 01:53:33 2011 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Thu, 24 Nov 2011 01:53:33 +0100 Subject: [coreboot] New patch to review for coreboot: e86d9b4 Use MMCONF for all AMD family 10 CPUs. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/455 -gerrit commit e86d9b43328f703f2b67c8555ba74d905f8579e9 Author: Marc Jones Date: Wed Nov 23 17:49:19 2011 -0700 Use MMCONF for all AMD family 10 CPUs. This fixes problems in AP init when multiple APs are trying to access PCI config space. All Fam10 CPUs setup and support MMCONF. Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128 Signed-off-by: Marc Jones --- src/cpu/amd/model_10xxx/Kconfig | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 6aab30a..35fa069 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -82,3 +82,7 @@ config UPDATE_CPU_MICROCODE Note that some operating system include these same microcode patches, so you may need to also disable microcode updates in your operating system in order for this option to matter. + +config MMCONF_SUPPORT_DEFAULT + bool + default y From gerrit at coreboot.org Thu Nov 24 11:43:12 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 24 Nov 2011 11:43:12 +0100 Subject: [coreboot] Patch merged into coreboot/master: 1e2bec3 Remove unused code files and cosmetic changes References: Message-ID: the following patch was just integrated into master: commit 1e2bec3cb90b23b7b69236c14b882b771e431bdc Author: Ky??sti M??lkki Date: Tue Nov 22 20:21:06 2011 +0200 Remove unused code files and cosmetic changes Following files were no longer used in the build and are deleted: src/arch/x86/init/entry.S src/arch/x86/init/ldscript.ld Also fix ugly whitespace in code copyrights and comments. Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b Signed-off-by: Ky??sti M??lkki Reviewed-By: Patrick Georgi at Thu Nov 24 11:43:10 2011, giving +2 See http://review.coreboot.org/440 for details. -gerrit From r.marek at assembler.cz Fri Nov 25 13:56:00 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 25 Nov 2011 13:56:00 +0100 Subject: [coreboot] [RFC] what new motherboard should I get (buy/donate)? Message-ID: <4ECF9060.5010402@assembler.cz> Hi all I think to get new motherboard for some more recent CPU/Chipset. Any clue what should I get? Also is willing someone to donate? How it looks like with datasheets for A75 SB900 or later? Does it make sense to buy some socket FM1 board? Thanks Rudolf From matiasjoseseco at care2.com Sat Nov 26 22:18:04 2011 From: matiasjoseseco at care2.com (Matias Jose Seco) Date: Sat, 26 Nov 2011 13:18:04 -0800 Subject: [coreboot] Lenovo T60p 8742 Y19 - Black screen Message-ID: <18117B307FBF4090BF54A88566FDE98E@mail2world.com> >Did you extract and add a VGA BIOS image? Note that you have to capture >the vgabios during runtime from Linux, because >the Lenovo BIOS does some Table patching at boot to enable the LVDS >(=TFT) Display port. Manual didn't says that if i have a video card upon PCIe interface, any action for Video config. is requiered? Thanks, Matias

_______________________________________________________________
Care2 makes it easy for everyone to live a healthy, green lifestyle and impact the causes you care about most. Over 12 Million members! http://www.care2.com Feed a child by searching the web! Learn how http://www.care2.com/toolbar -------------- next part -------------- An HTML attachment was scrubbed... URL: From matiasjoseseco at care2.com Sat Nov 26 22:16:21 2011 From: matiasjoseseco at care2.com (Matias Jose Seco) Date: Sat, 26 Nov 2011 13:16:21 -0800 Subject: [coreboot] Lenovo T60p 8742 Y19 - Black screen Message-ID: <2BE744324F184843A76C34FDA43587A0@mail2world.com> >Was your gcc and binutils built with USE=vanilla? If not, it is >completely possible that your toolchain produced a broken image. >I've had this happen with some gcc versions. I didn't use that flag, but flashrom returned no error after veryfing emage, but i think this don't excludes broken image? >> - Dont save config options >CMOS/NVRAM? That may need to be enabled for image to work. if this is enabled by defualt, i left it enabled it (the one i mentioned is 'INCLUDE_CONFIG_FILE') >> - mmx,smp,sse,sse2 > >How did you set this exactly? I don't remember^^, but if i dont remember bad, i've enabled them under some section (im sure about smp) >Get a docking station, port replicator or ultrabay superio module, so >that you get a serial port, and connect that to another computer. >coreboot should output debug information there when starting, and it >may be clear what the problem is. I will ;) >Also, does it seem like the system boots? Is there some hard drive >access after you power on? The HD led it just blink ones when switched on... >And, does caps lock work after you power on? no :( >Finally, did you include a VGA BIOS into your coreboot.rom? This is >easiest done by configuring the filename in menuconfig. Note that >coreboot should not execute the VGA BIOS, the file should only be >added. You may need to change the defaults for this. But the manual said that if my video card was upon a PCIe interface, ishould't do anything, right? Thanks, Matias

_______________________________________________________________
Care2 makes it easy for everyone to live a healthy, green lifestyle and impact the causes you care about most. Over 12 Million members! http://www.care2.com Feed a child by searching the web! Learn how http://www.care2.com/toolbar -------------- next part -------------- An HTML attachment was scrubbed... URL: From GNUtoo at no-log.org Sat Nov 26 22:53:27 2011 From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli) Date: Sat, 26 Nov 2011 22:53:27 +0100 Subject: [coreboot] VGA issues on ASUS M4A785T-M In-Reply-To: <201111202245.00020.GNUtoo@no-log.org> References: <201111111953.43899.GNUtoo@no-log.org> <201111202245.00020.GNUtoo@no-log.org> Message-ID: <201111262253.27527.GNUtoo@no-log.org> it now works better: with pci=nocrs the radeon card initialize and kdm+Xorg works somehow.... I've now the screen flickering problem at high resolutions(starting at 1024x768, 800x600 is fine). if the problem can't be fixed, would buying an nvidia nv50 workarround the issue and permit me to have a resolution up to 1440x900 (that would also give me 3d acceleration(trisquel,the distribution that I use, don't include the non-free 3d microcode for ATI cards) with nouveau,if I understood well they have no non-free microcode requirement and I was told theses cards were stable enough now). Altough if I understand well the PCI express reset gpio has to work to be able to enable graphics on the PCI express slot. Denis. From peter at stuge.se Sat Nov 26 23:26:28 2011 From: peter at stuge.se (Peter Stuge) Date: Sat, 26 Nov 2011 23:26:28 +0100 Subject: [coreboot] VGA issues on ASUS M4A785T-M In-Reply-To: <201111262253.27527.GNUtoo@no-log.org> References: <201111111953.43899.GNUtoo@no-log.org> <201111202245.00020.GNUtoo@no-log.org> <201111262253.27527.GNUtoo@no-log.org> Message-ID: <20111126222628.12896.qmail@stuge.se> Denis 'GNUtoo' Carikli wrote: > it now works better: > with pci=nocrs the radeon card initialize and kdm+Xorg works somehow.... > I've now the screen flickering problem at high resolutions(starting at > 1024x768, 800x600 is fine). > > if the problem can't be fixed, would buying an nvidia nv50 workarround the > issue and permit me to have a resolution up to 1440x900 pci=nocrs should not be required, and regardless of what graphics card you buy the issue that requires pci=nocrs will remain. Best would be to look into that issue and fix it. Then there's a chance that your radeon graphics will work flawlessly, and then you could of course buy another graphics card if you wanted to. //Peter From gerrit at coreboot.org Sun Nov 27 18:59:48 2011 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Sun, 27 Nov 2011 18:59:48 +0100 Subject: [coreboot] New patch to review for coreboot: e8d0122 RS780: print the vgainfo References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/456 -gerrit commit e8d0122db0712a3a188c9ca85e1fb6325f2eb592 Author: Denis 'GNUtoo' Carikli Date: Sun Nov 27 13:43:16 2011 +0100 RS780: print the vgainfo Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524 Signed-off-by: Denis 'GNUtoo' Carikli --- src/southbridge/amd/rs780/gfx.c | 80 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 80 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 65a5e2b..29a6394 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -575,6 +575,86 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Poweron DDI Lanes */ poweron_ddi_lanes(nb_dev); + printk(BIOS_DEBUG,"vgainfo:\n" + " ulBootUpEngineClock:%lu \n" + " ulBootUpUMAClock:%lu \n" + " ulBootUpSidePortClock:%lu \n" + " ulMinSidePortClock:%lu \n" + " ulSystemConfig:%lu \n" + " ulBootUpReqDisplayVector:%lu \n" + " ulOtherDisplayMisc:%lu \n" + " ulDDISlot1Config:%lu \n" + " ulDDISlot2Config:%lu \n" + + " ucMemoryType:%u \n" + " ucUMAChannelNumber:%u \n" + " ucDockingPinBit:%u \n" + " ucDockingPinPolarity:%u \n" + + " ulDockingPinCFGInfo:%lu \n" + " ulCPUCapInfo: %lu \n" + + " usNumberOfCyclesInPeriod:%hu \n" + " usMaxNBVoltage:%hu \n" + " usMinNBVoltage:%hu \n" + " usBootUpNBVoltage:%hu \n" + + " ulHTLinkFreq:%lu \n" + + " usMinHTLinkWidth:%hu \n" + " usMaxHTLinkWidth:%hu \n" + " usUMASyncStartDelay:%hu \n" + " usUMADataReturnTime:%hu \n" + " usLinkStatusZeroTime:%hu \n" + + " ulHighVoltageHTLinkFreq:%lu \n" + " ulLowVoltageHTLinkFreq:%lu \n" + + " usMaxUpStreamHTLinkWidth:%hu \n" + " usMaxDownStreamHTLinkWidth:%hu \n" + " usMinUpStreamHTLinkWidth:%hu \n" + " usMinDownStreamHTLinkWidth:%hu \n", + + (unsigned long)vgainfo.ulBootUpEngineClock, + (unsigned long)vgainfo.ulBootUpUMAClock, + (unsigned long)vgainfo.ulBootUpSidePortClock, + (unsigned long)vgainfo.ulMinSidePortClock, + (unsigned long)vgainfo.ulSystemConfig, + (unsigned long)vgainfo.ulBootUpReqDisplayVector, + (unsigned long)vgainfo.ulOtherDisplayMisc, + (unsigned long)vgainfo.ulDDISlot1Config, + (unsigned long)vgainfo.ulDDISlot2Config, + + vgainfo.ucMemoryType, + vgainfo.ucUMAChannelNumber, + vgainfo.ucDockingPinBit, + vgainfo.ucDockingPinPolarity, + + (unsigned long)vgainfo.ulDockingPinCFGInfo, + (unsigned long)vgainfo.ulCPUCapInfo, + + vgainfo.usNumberOfCyclesInPeriod, + vgainfo.usMaxNBVoltage, + vgainfo.usMinNBVoltage, + vgainfo.usBootUpNBVoltage, + + (unsigned long)vgainfo.ulHTLinkFreq, + + vgainfo.usMinHTLinkWidth, + vgainfo.usMaxHTLinkWidth, + vgainfo.usUMASyncStartDelay, + vgainfo.usUMADataReturnTime, + vgainfo.usLinkStatusZeroTime, + + (unsigned long)vgainfo.ulHighVoltageHTLinkFreq, + (unsigned long)vgainfo.ulLowVoltageHTLinkFreq, + + vgainfo.usMaxUpStreamHTLinkWidth, + vgainfo.usMaxDownStreamHTLinkWidth, + vgainfo.usMinUpStreamHTLinkWidth, + vgainfo.usMinDownStreamHTLinkWidth); + + /* Transfer the Table to VBIOS. */ pointer = (u32 *)&vgainfo; for(i=0; i Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/457 -gerrit commit 1eb55d026f9d364eb8f3d7ededc4dc7f98deafef Author: Denis 'GNUtoo' Carikli Date: Sun Nov 27 15:58:38 2011 +0100 Add ASUS M4A785T-M mainboard support This mainboard is very similar to the M4A785-M, but it has DDR3 instead of DDR2. That's why most of the code was copied or included from the m4a785-m directory Notable changes between the two mainboards include: * the selection of the last microcode (mc_patch_010000b6.h) which made it pass the CPU init. * the selection of DDR3 which made it pass the ram init Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/m4a785-m/mainboard.c | 4 + src/mainboard/asus/m4a785t-m/Kconfig | 86 ++ src/mainboard/asus/m4a785t-m/acpi/cpstate.asl | 75 + src/mainboard/asus/m4a785t-m/acpi/ide.asl | 244 ++++ src/mainboard/asus/m4a785t-m/acpi/routing.asl | 300 ++++ src/mainboard/asus/m4a785t-m/acpi/sata.asl | 149 ++ src/mainboard/asus/m4a785t-m/acpi/usb.asl | 161 +++ src/mainboard/asus/m4a785t-m/acpi_tables.c | 21 + src/mainboard/asus/m4a785t-m/chip.h | 23 + src/mainboard/asus/m4a785t-m/cmos.layout | 98 ++ src/mainboard/asus/m4a785t-m/devicetree.cb | 106 ++ src/mainboard/asus/m4a785t-m/dsdt.asl | 1850 +++++++++++++++++++++++++ src/mainboard/asus/m4a785t-m/get_bus_conf.c | 21 + src/mainboard/asus/m4a785t-m/irq_tables.c | 21 + src/mainboard/asus/m4a785t-m/mainboard.c | 21 + src/mainboard/asus/m4a785t-m/mptable.c | 21 + src/mainboard/asus/m4a785t-m/romstage.c | 21 + 18 files changed, 3225 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..bdc1709 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -35,6 +35,8 @@ config BOARD_ASUS_M2V_MX_SE bool "M2V-MX SE" config BOARD_ASUS_M4A785M bool "M4A785-M" +config BOARD_ASUS_M4A785TM + bool "M4A785T-M" config BOARD_ASUS_M4A78_EM bool "M4A78-EM" config BOARD_ASUS_M5A88_V @@ -65,6 +67,7 @@ source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" source "src/mainboard/asus/m4a785-m/Kconfig" +source "src/mainboard/asus/m4a785t-m/Kconfig" source "src/mainboard/asus/m4a78-em/Kconfig" source "src/mainboard/asus/m5a88-v/Kconfig" source "src/mainboard/asus/mew-am/Kconfig" diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 8a96476..d152f71 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -242,6 +242,10 @@ static void m4a785m_enable(device_t dev) } struct chip_operations mainboard_ops = { +#ifdef CONFIG_BOARD_ASUS_M4A785TM + CHIP_NAME("ASUS M4A785T-M Mainboard") +#else CHIP_NAME("ASUS M4A785-M Mainboard") +#endif .enable_dev = m4a785m_enable, }; diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig new file mode 100644 index 0000000..e3893b2 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -0,0 +1,86 @@ +if BOARD_ASUS_M4A785TM + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_AM3 + select DIMM_DDR3 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_AMD_RS780 + select SOUTHBRIDGE_AMD_SB700 + select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT + select SUPERIO_ITE_IT8712F + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO + select ENABLE_APIC_EXT_ID + select GFXUMA + select QRANK_DIMM_SUPPORT + +config MAINBOARD_DIR + string + default asus/m4a785t-m + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "M4A785T-M" + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config MEM_TRAIN_SEQ + int + default 2 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config IRQ_SLOT_COUNT + int + default 19 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_010000c4.h" + +config RAMTOP + hex + default 0x2000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config RAMBASE + hex + default 0x200000 + +endif diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl new file mode 100644 index 0000000..6a1b002 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/m4a785t-m/acpi/ide.asl b/src/mainboard/asus/m4a785t-m/acpi/ide.asl new file mode 100644 index 0000000..6ea2b09 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/routing.asl b/src/mainboard/asus/m4a785t-m/acpi/routing.asl new file mode 100644 index 0000000..ad51815 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/routing.asl @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 1, INTA, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + Package(){0x0012FFFF, 0, INTA, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + Package(){0x0013FFFF, 0, INTA, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTA, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Package(){0x0001FFFF, 0, 0, 18 }, */ + /* package(){0x0001FFFF, 1, 0, 19 }, */ + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 22 }, + + /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + Package(){0x0012FFFF, 0, 0, 16 }, + Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 19 }, + Package(){0x0014FFFF, 0, 0, 16 }, + /* Package(){0x00130004, 2, 0, 18 }, */ + /* Package(){0x00130005, 3, 0, 19 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/sata.asl b/src/mainboard/asus/m4a785t-m/acpi/sata.asl new file mode 100644 index 0000000..b5e6fc5 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/usb.asl b/src/mainboard/asus/m4a785t-m/acpi/usb.asl new file mode 100644 index 0000000..203e0ad --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/usb.asl @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/asus/m4a785t-m/acpi_tables.c b/src/mainboard/asus/m4a785t-m/acpi_tables.c new file mode 100644 index 0000000..a7ffc02 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/acpi_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/chip.h b/src/mainboard/asus/m4a785t-m/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m4a785t-m/cmos.layout b/src/mainboard/asus/m4a785t-m/cmos.layout new file mode 100644 index 0000000..53fdef5 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb new file mode 100644 index 0000000..e8764b1 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -0,0 +1,106 @@ +chip northbridge/amd/amdfam10/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR2 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1043 0x83a2 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 off end # + device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "2" + + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8712f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + end + device pnp 2e.9 off # GAME + end + device pnp 2e.a off end # CIR + end #superio + end #LPC + device pci 14.4 on end # PCI to PCI Bridge [1002:4384] + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # chip northbridge + end #pci_domain +end # northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl new file mode 100644 index 0000000..34ddd3a --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -0,0 +1,1850 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "M4A785-M ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x808, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU2, /* name space name */ + 2, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU3, /* name space name */ + 3, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PINA, 0x00000008, /* Index 0 */ + PINB, 0x00000008, /* Index 1 */ + PINC, 0x00000008, /* Index 2 */ + PIND, 0x00000008, /* Index 3 */ + AINT, 0x00000008, /* Index 4 */ + SINT, 0x00000008, /* Index 5 */ + , 0x00000008, /* Index 6 */ + AAUD, 0x00000008, /* Index 7 */ + AMOD, 0x00000008, /* Index 8 */ + PINE, 0x00000008, /* Index 9 */ + PINF, 0x00000008, /* Index A */ + PING, 0x00000008, /* Index B */ + PINH, 0x00000008, /* Index C */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PINA) + Store(0, PINB) + Store(0, PINC) + Store(0, PIND) + Store(0, PINE) + Store(0, PINF) + Store(0, PING) + Store(0, PINH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PINA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PINA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PINB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PINB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PINC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PINC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIND) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIND) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIND, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIND) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PINE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PINE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PINF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PINF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PING) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PING) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PING, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PING) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PINH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PINH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + \_SB.PCI0.SIOS (Arg0) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + \_SB.PCI0.SIOW (Arg0) + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + Notify (\_TZ.TZ00, 0x80) + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00130001) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130003) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00130004) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00130005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + /* ITE8718 Support */ + OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ + Field (IOID, ByteAcc, NoLock, Preserve) + { + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + } + + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + LDN, 8, /* Logical Device Number */ + Offset (0x20), + CID1, 8, /* Chip ID Byte 1, 0x87 */ + CID2, 8, /* Chip ID Byte 2, 0x12 */ + Offset (0x30), + ACTR, 8, /* Function activate */ + Offset (0xF0), + APC0, 8, /* APC/PME Event Enable Register */ + APC1, 8, /* APC/PME Status Register */ + APC2, 8, /* APC/PME Control Register 1 */ + APC3, 8, /* Environment Controller Special Configuration Register */ + APC4, 8 /* APC/PME Control Register 2 */ + } + + /* Enter the 8718 MB PnP Mode */ + Method (EPNP) + { + Store(0x87, SIOI) + Store(0x01, SIOI) + Store(0x55, SIOI) + Store(0x55, SIOI) /* 8718 magic number */ + } + /* Exit the 8718 MB PnP Mode */ + Method (XPNP) + { + Store (0x02, SIOI) + Store (0x02, SIOD) + } + /* + * Keyboard PME is routed to SB700 Gevent3. We can wake + * up the system by pressing the key. + */ + Method (SIOS, 1) + { + /* We only enable KBD PME for S5. */ + If (LLess (Arg0, 0x05)) + { + EPNP() + /* DBGO("8718F\n") */ + + Store (0x4, LDN) + Store (One, ACTR) /* Enable EC */ + /* + Store (0x4, LDN) + Store (0x04, APC4) + */ /* falling edge. which mode? Not sure. */ + + Store (0x4, LDN) + Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ + Store (0x4, LDN) + Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + + XPNP() + } + } + Method (SIOW, 1) + { + EPNP() + Store (0x4, LDN) + Store (Zero, APC0) /* disable keyboard PME */ + Store (0x4, LDN) + Store (0xFF, APC1) /* clear keyboard PME status */ + XPNP() + } + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PEBM + ) + + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ + + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +} +/* End of ASL file */ diff --git a/src/mainboard/asus/m4a785t-m/get_bus_conf.c b/src/mainboard/asus/m4a785t-m/get_bus_conf.c new file mode 100644 index 0000000..577b51c --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/get_bus_conf.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/get_bus_conf.c" diff --git a/src/mainboard/asus/m4a785t-m/irq_tables.c b/src/mainboard/asus/m4a785t-m/irq_tables.c new file mode 100644 index 0000000..b4c030f --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/irq_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/irq_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/mainboard.c b/src/mainboard/asus/m4a785t-m/mainboard.c new file mode 100644 index 0000000..76a2a68 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/mainboard.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/mainboard.c" diff --git a/src/mainboard/asus/m4a785t-m/mptable.c b/src/mainboard/asus/m4a785t-m/mptable.c new file mode 100644 index 0000000..c6e4b88 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/mptable.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/mptable.c" diff --git a/src/mainboard/asus/m4a785t-m/romstage.c b/src/mainboard/asus/m4a785t-m/romstage.c new file mode 100644 index 0000000..43cd523 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/romstage.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/romstage.c" From paulepanter at users.sourceforge.net Sun Nov 27 20:42:22 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Sun, 27 Nov 2011 20:42:22 +0100 Subject: [coreboot] New patch to review for coreboot: e8d0122 RS780: print the vgainfo In-Reply-To: References: Message-ID: <1322422942.7998.54.camel@mattotaupa> Am Sonntag, den 27.11.2011, 18:59 +0100 schrieb Denis Carikli: > Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/456 > > -gerrit > > commit e8d0122db0712a3a188c9ca85e1fb6325f2eb592 > Author: Denis 'GNUtoo' Carikli > Date: Sun Nov 27 13:43:16 2011 +0100 > > RS780: print the vgainfo Could you add an example output to the commit message? Just amend the commit message and push the change again. Just make sure the Change-Id stays the same. > Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524 > Signed-off-by: Denis 'GNUtoo' Carikli > --- > src/southbridge/amd/rs780/gfx.c | 80 +++++++++++++++++++++++++++++++++++++++ > 1 files changed, 80 insertions(+), 0 deletions(-) Otherwise this looks good. I hope somebody else will approve this in Gerrit. [?] Thanks, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From paulepanter at users.sourceforge.net Sun Nov 27 20:46:22 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Sun, 27 Nov 2011 20:46:22 +0100 Subject: [coreboot] New patch to review for coreboot: 1eb55d0 Add ASUS M4A785T-M mainboard support In-Reply-To: References: Message-ID: <1322423182.7998.58.camel@mattotaupa> Am Sonntag, den 27.11.2011, 18:59 +0100 schrieb Denis Carikli: > Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/457 > > -gerrit > > commit 1eb55d026f9d364eb8f3d7ededc4dc7f98deafef > Author: Denis 'GNUtoo' Carikli > Date: Sun Nov 27 15:58:38 2011 +0100 > > Add ASUS M4A785T-M mainboard support > > This mainboard is very similar to the M4A785-M, but it has > DDR3 instead of DDR2. > > That's why most of the code was copied or included from > the m4a785-m directory > > Notable changes between the two mainboards include: > * the selection of the last microcode (mc_patch_010000b6.h) > which made it pass the CPU init. > * the selection of DDR3 which made it pass the ram init Thank you very much for the patch. Could you add what you have tested and not, what works and what does not (flickering)? The OS you tested with. You need to add pci=nocrs currently to the command line if I remember correctly. You have a Wiki page already. Could you add the URL to this page too? Also URLs to messages in the list archives with the boot log and for example `dmesg`. > Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 > Signed-off-by: Denis 'GNUtoo' Carikli [?] Thanks, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From gerrit at coreboot.org Sun Nov 27 22:41:44 2011 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Sun, 27 Nov 2011 22:41:44 +0100 Subject: [coreboot] New patch to review for coreboot: 2687844 M4A785T-M: fix ACPI's P-States Table References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/458 -gerrit commit 2687844d07b04894bc411d221efd1b98929f4562 Author: Denis 'GNUtoo' Carikli Date: Sun Nov 27 22:04:02 2011 +0100 M4A785T-M: fix ACPI's P-States Table Without that fix the linux kernel cannot change the frequency of the CPUs with cpufreq. Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/m4a785t-m/acpi/cpstate.asl | 36 +++++++++++++++++++----- 1 files changed, 28 insertions(+), 8 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl index 6a1b002..0ee537d 100644 --- a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl +++ b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl @@ -46,22 +46,42 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) Name(_PSS, Package(){ Package () { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, + 0x00000BB8, + 0x000078D9, + 0x00000004, + 0x00000004, 0x00000000, 0x00000000 }, Package () { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, + 0x000008FC, + 0x0000659A, + 0x00000004, + 0x00000004, 0x00000001, 0x00000001 + }, + + Package () + { + 0x00000708, + 0x000056BF, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package () + { + 0x00000320, + 0x00001FA1, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 } }) From eldmannen at gmail.com Sun Nov 27 22:33:51 2011 From: eldmannen at gmail.com (Fred .) Date: Sun, 27 Nov 2011 22:33:51 +0100 Subject: [coreboot] Contribute: USB debug port info Message-ID: $ lspci|grep EHCI|cut -f1 -d' ' 00:1a.7 00:1d.7 $ sudo lspci -vs 00:1a.7 00:1a.7 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #2 (prog-if 20 [EHCI]) Subsystem: Giga-byte Technology GA-EP45-DS5 Motherboard Flags: bus master, medium devsel, latency 0, IRQ 18 Memory at fdfff000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Kernel driver in use: ehci_hcd $ sudo lspci -ns 00:1a.7 00:1a.7 0c03: 8086:3a3c $ sudo ./attachment.sh The following PCI devices support a USB debug port (says lspci): None Possible reasons: lspci not run as root, lspci too old, USB controller does not support a debug device The following PCI devices support a USB debug port (says the kernel): None Possible reasons: dmesg scrolled off, kernel too old, USB controller does not support a debug device No USB controller with debug capability found http://www.coreboot.org/EHCI_Debug_Port From peter at stuge.se Sun Nov 27 23:17:29 2011 From: peter at stuge.se (Peter Stuge) Date: Sun, 27 Nov 2011 23:17:29 +0100 Subject: [coreboot] Contribute: USB debug port info In-Reply-To: References: Message-ID: <20111127221729.7954.qmail@stuge.se> Fred . wrote: > $ lspci|grep EHCI|cut -f1 -d' ' > 00:1a.7 > 00:1d.7 > > $ sudo lspci -vs 00:1a.7 > 00:1a.7 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB2 > EHCI Controller #2 (prog-if 20 [EHCI]) > Subsystem: Giga-byte Technology GA-EP45-DS5 Motherboard > Flags: bus master, medium devsel, latency 0, IRQ 18 > Memory at fdfff000 (32-bit, non-prefetchable) [size=1K] > Capabilities: [50] Power Management version 2 > Kernel driver in use: ehci_hcd > > $ sudo lspci -ns 00:1a.7 > 00:1a.7 0c03: 8086:3a3c And what about 1d.7? //Peter From gerrit at coreboot.org Mon Nov 28 03:49:08 2011 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Mon, 28 Nov 2011 03:49:08 +0100 Subject: [coreboot] Patch set updated for coreboot: e50d8e9 Use MMCONF for all AMD family 10 CPUs. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/455 -gerrit commit e50d8e9242f0eadfe24d6a5f1f3fe8247c8f3afa Author: Marc Jones Date: Wed Nov 23 17:49:19 2011 -0700 Use MMCONF for all AMD family 10 CPUs. This fixes problems in AP init when multiple APs are trying to access PCI config space. All Fam10 CPUs setup and support MMCONF. Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128 Signed-off-by: Marc Jones --- src/cpu/amd/model_10xxx/Kconfig | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 6aab30a..6c00243 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -48,8 +48,7 @@ config SET_FIDVID_CORE_RANGE int default 0 -endif -endif +endif # SET_FIDVID config UPDATE_CPU_MICROCODE bool @@ -82,3 +81,9 @@ config UPDATE_CPU_MICROCODE Note that some operating system include these same microcode patches, so you may need to also disable microcode updates in your operating system in order for this option to matter. + +config MMCONF_SUPPORT_DEFAULT + bool + default y + +endif # CPU_AMD_MODEL_10XXX From heemeli at hotmail.com Mon Nov 28 04:58:28 2011 From: heemeli at hotmail.com (Saku Sammakko) Date: Mon, 28 Nov 2011 05:58:28 +0200 Subject: [coreboot] I DID IT!!! Message-ID: Hey Friend! this has been how to start your new life http://www.WhyGrowUp.in/profile/67DarrenWallace/ talk to you later. -------------- next part -------------- An HTML attachment was scrubbed... URL: From GNUtoo at no-log.org Mon Nov 28 05:27:50 2011 From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli) Date: Mon, 28 Nov 2011 05:27:50 +0100 Subject: [coreboot] New patch to review for coreboot: 1eb55d0 Add ASUS M4A785T-M mainboard support In-Reply-To: <1322423182.7998.58.camel@mattotaupa> References: <1322423182.7998.58.camel@mattotaupa> Message-ID: <201111280527.50386.GNUtoo@no-log.org> here's dmesg: [ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Linux version 2.6.38-12-generic (root at devel.trisquel.info) (gcc version 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu4) ) #0trisquel1 SMP Tue Oct 25 15:17:30 UTC 2011 (Ubuntu 2.6.38-12.51+5.0trisquel1-generic 2.6.38.8-libre) [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009f800 (usable) [ 0.000000] BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved) [ 0.000000] BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) [ 0.000000] BIOS-e820: 0000000000100000 - 000000006ffee000 (usable) [ 0.000000] BIOS-e820: 000000006ffee000 - 0000000080000000 (reserved) [ 0.000000] BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved) [ 0.000000] BIOS-e820: 00000000fec00000 - 00000000fec01000 (reserved) [ 0.000000] BIOS-e820: 00000000fed00000 - 00000000fed00400 (reserved) [ 0.000000] Notice: NX (Execute Disable) protection cannot be enabled in hardware: non-PAE kernel! [ 0.000000] NX (Execute Disable) protection: approximated by x86 segment limits [ 0.000000] DMI present. [ 0.000000] DMI: ASUS M4A785T-M, BIOS 4.0-1889-gac9f320 11/27/2011 [ 0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved) [ 0.000000] e820 remove range: 00000000000a0000 - 0000000000100000 (usable) [ 0.000000] last_pfn = 0x6ffee max_arch_pfn = 0x100000 [ 0.000000] MTRR default type: uncachable [ 0.000000] MTRR fixed ranges enabled: [ 0.000000] 00000-9FFFF write-back [ 0.000000] A0000-BFFFF uncachable [ 0.000000] C0000-FFFFF write-back [ 0.000000] MTRR variable ranges enabled: [ 0.000000] 0 base 000000000000 mask FFFF80000000 write-back [ 0.000000] 1 base 000070000000 mask FFFFF0000000 uncachable [ 0.000000] 2 disabled [ 0.000000] 3 disabled [ 0.000000] 4 disabled [ 0.000000] 5 disabled [ 0.000000] 6 disabled [ 0.000000] 7 disabled [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 [ 0.000000] found SMP MP-table at [c00fd980] fd980 [ 0.000000] initial memory mapped : 0 - 01c00000 [ 0.000000] init_memory_mapping: 0000000000000000-00000000377fe000 [ 0.000000] 0000000000 - 0000400000 page 4k [ 0.000000] 0000400000 - 0037400000 page 2M [ 0.000000] 0037400000 - 00377fe000 page 4k [ 0.000000] kernel direct mapping tables up to 377fe000 @ 1bfb000-1c00000 [ 0.000000] RAMDISK: 35fd6000 - 36fe3000 [ 0.000000] ACPI: RSDP 000fd960 00014 (v00 CORE ) [ 0.000000] ACPI: RSDT 6fff2424 0003C (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: HPET 6fff24c8 00038 (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: APIC 6fff2500 0005C (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: SRAT 6fff2560 000A0 (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: SLIT 6fff2600 0002D (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: SSDT 6fff2630 00635 (v01 AMD-FA AMD-ACPI 06040000 INTL 20110922) [ 0.000000] ACPI: FACP 6fff56c0 000F4 (v03 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: DSDT 6fff2c68 02A18 (v02 ASUS M4A785-M 00010001 INTL 20110922) [ 0.000000] ACPI: FACS 6fff5680 00040 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] 903MB HIGHMEM available. [ 0.000000] 887MB LOWMEM available. [ 0.000000] mapped low ram: 0 - 377fe000 [ 0.000000] low ram: 0 - 377fe000 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0x00000010 -> 0x00001000 [ 0.000000] Normal 0x00001000 -> 0x000377fe [ 0.000000] HighMem 0x000377fe -> 0x0006ffee [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[2] active PFN ranges [ 0.000000] 0: 0x00000010 -> 0x0000009f [ 0.000000] 0: 0x00000100 -> 0x0006ffee [ 0.000000] On node 0 totalpages: 458621 [ 0.000000] free_area_init_node: node 0, pgdat c1770140, node_mem_map f51d6200 [ 0.000000] DMA zone: 32 pages used for memmap [ 0.000000] DMA zone: 0 pages reserved [ 0.000000] DMA zone: 3951 pages, LIFO batch:0 [ 0.000000] Normal zone: 1744 pages used for memmap [ 0.000000] Normal zone: 221486 pages, LIFO batch:31 [ 0.000000] HighMem zone: 1808 pages used for memmap [ 0.000000] HighMem zone: 229600 pages, LIFO batch:31 [ 0.000000] Using APIC driver default [ 0.000000] ACPI: PM-Timer IO Port: 0x818 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) [ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0]) [ 0.000000] IOAPIC[0]: apic_id 2, version 33, address 0xfec00000, GSI 0-23 [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) [ 0.000000] ACPI: IRQ0 used by override. [ 0.000000] ACPI: IRQ2 used by override. [ 0.000000] ACPI: IRQ9 used by override. [ 0.000000] Using ACPI (MADT) for SMP configuration information [ 0.000000] ACPI: HPET id: 0x102282a0 base: 0xfed00000 [ 0.000000] SMP: Allowing 2 CPUs, 0 hotplug CPUs [ 0.000000] nr_irqs_gsi: 40 [ 0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000 [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000 [ 0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000 [ 0.000000] Allocating PCI resources starting at 80000000 (gap: 80000000:60000000) [ 0.000000] Booting paravirtualized kernel on bare hardware [ 0.000000] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:2 nr_node_ids:1 [ 0.000000] PERCPU: Embedded 13 pages/cpu @f7000000 s28800 r0 d24448 u2097152 [ 0.000000] pcpu-alloc: s28800 r0 d24448 u2097152 alloc=1*4194304 [ 0.000000] pcpu-alloc: [0] 0 1 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 455037 [ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-2.6.38-12-generic root=/dev/mapper/root ro console=ttyS0,115200 console=tty0 modeset=1 pci=nocrs [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Initializing CPU#0 [ 0.000000] allocated 9174360 bytes of page_cgroup [ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups [ 0.000000] Initializing HighMem for node 0 (000377fe:0006ffee) [ 0.000000] Memory: 1784528k/1834936k available (5190k kernel code, 49956k reserved, 2458k data, 700k init, 925632k highmem) [ 0.000000] virtual kernel memory layout: [ 0.000000] fixmap : 0xfff16000 - 0xfffff000 ( 932 kB) [ 0.000000] pkmap : 0xff800000 - 0xffc00000 (4096 kB) [ 0.000000] vmalloc : 0xf7ffe000 - 0xff7fe000 ( 120 MB) [ 0.000000] lowmem : 0xc0000000 - 0xf77fe000 ( 887 MB) [ 0.000000] .init : 0xc1779000 - 0xc1828000 ( 700 kB) [ 0.000000] .data : 0xc1511b51 - 0xc17784c0 (2458 kB) [ 0.000000] .text : 0xc1000000 - 0xc1511b51 (5190 kB) [ 0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok. [ 0.000000] SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU dyntick-idle grace-period acceleration is enabled. [ 0.000000] RCU-based detection of stalled CPUs is disabled. [ 0.000000] NR_IRQS:2304 nr_irqs:512 16 [ 0.000000] CPU 0 irqstacks, hard=f4408000 soft=f440a000 [ 0.000000] spurious 8259A interrupt: IRQ7. [ 0.000000] Console: colour VGA+ 80x25 [ 0.000000] console [tty0] enabled [ 0.000000] console [ttyS0] enabled [ 0.000000] hpet clockevent registered [ 0.000000] Fast TSC calibration using PIT [ 0.000000] Detected 3000.540 MHz processor. [ 0.012002] Calibrating delay loop (skipped), value calculated using timer frequency.. 6001.08 BogoMIPS (lpj=12002160) [ 0.020006] pid_max: default: 32768 minimum: 301 [ 0.024023] Security Framework initialized [ 0.028018] AppArmor: AppArmor initialized [ 0.032005] Yama: becoming mindful. [ 0.036056] Mount-cache hash table entries: 512 [ 0.040107] Initializing cgroup subsys ns [ 0.044008] ns_cgroup deprecated: consider using the 'clone_children' flag without the ns_cgroup. [ 0.048007] Initializing cgroup subsys cpuacct [ 0.052008] Initializing cgroup subsys memory [ 0.056013] Initializing cgroup subsys devices [ 0.060010] Initializing cgroup subsys freezer [ 0.064007] Initializing cgroup subsys net_cls [ 0.068006] Initializing cgroup subsys blkio [ 0.072032] CPU: Physical Processor ID: 0 [ 0.076007] CPU: Processor Core ID: 0 [ 0.080009] mce: CPU supports 6 MCE banks [ 0.089049] ACPI: Core revision 20110112 [ 0.094004] ftrace: allocating 23652 entries in 47 pages [ 0.100066] Enabling APIC mode: Flat. Using 1 I/O APICs [ 0.108648] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.154477] CPU0: AMD Athlon(tm) II X2 250 Processor stepping 02 [ 0.164009] Performance Events: AMD PMU driver. [ 0.164012] ... version: 0 [ 0.168010] ... bit width: 48 [ 0.172010] ... generic registers: 4 [ 0.176011] ... value mask: 0000ffffffffffff [ 0.180011] ... max period: 00007fffffffffff [ 0.184011] ... fixed-purpose events: 0 [ 0.188012] ... event mask: 000000000000000f [ 0.192410] CPU 1 irqstacks, hard=f44aa000 soft=f44ac000 [ 0.192414] Booting Node 0, Processors #1 Ok. [ 0.012000] Initializing CPU#1 [ 0.292017] TSC synchronization [CPU#0 -> CPU#1]: [ 0.292017] Measured 37471011521 cycles TSC warp between CPUs, turning off TSC clock. [ 0.292017] Marking TSC unstable due to check_tsc_sync_source failed [ 0.292026] Brought up 2 CPUs [ 0.296019] Total of 2 processors activated (10001.42 BogoMIPS). [ 0.300851] devtmpfs: initialized [ 0.308517] print_constraints: dummy: [ 0.312055] Time: 4:11:53 Date: 11/28/11 [ 0.316071] NET: Registered protocol family 16 [ 0.320059] Trying to unpack rootfs image as initramfs... [ 0.320179] EISA bus registered [ 0.320187] node 0 link 0: io port [1000, 3fff] [ 0.320192] TOM: 0000000080000000 aka 2048M [ 0.320195] Fam 10h mmconf [e0000000, efffffff] [ 0.320200] node 0 link 0: mmio [d4000000, d84fffff] [ 0.320204] node 0 link 0: mmio [c0000000, d00fffff] [ 0.320209] bus: [00, 03] on node 0 link 0 [ 0.320213] bus: 00 index 0 [io 0x0000-0xffff] [ 0.320217] bus: 00 index 1 [mem 0xd0100000-0xdfffffff] [ 0.320221] bus: 00 index 2 [mem 0x80000000-0xd00fffff] [ 0.320224] bus: 00 index 3 [mem 0xf0000000-0xffffffff] [ 0.320253] Extended Config Space enabled on 1 nodes [ 0.320263] ACPI: bus type pci registered [ 0.320463] PCI: PCI BIOS revision 2.10 entry at 0xfc839, last bus=3 [ 0.320466] PCI: Using configuration type 1 for base access [ 0.320468] PCI: Using configuration type 1 for extended access [ 0.320492] mtrr: your CPUs had inconsistent variable MTRR settings [ 0.320494] mtrr: probably your BIOS does not setup all CPUs. [ 0.320496] mtrr: corrected configuration. [ 0.320496] bio: create slab at 0 [ 0.321495] ACPI: EC: Look up EC in DSDT [ 0.321495] ACPI: Executed 2 blocks of module-level executable AML code [ 0.321495] ACPI: Interpreter enabled [ 0.328024] ACPI: (supports S0 S1 S2 S3 S4 S5) [ 0.333620] ACPI: BIOS offers _BFS [ 0.336023] ACPI: If "acpi.bfs=1" improves resume, please notify linux- acpi at vger.kernel.org [ 0.348024] ACPI: Using IOAPIC for interrupt routing [ 0.377796] ACPI: Power Resource [PFN0] (on) [ 0.412155] ACPI: No dock devices found. [ 0.416028] HEST: Table not found. [ 0.418382] PCI: Ignoring host bridge windows from ACPI; if necessary, use "pci=use_crs" and report a bug [ 0.428130] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.437523] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536) [ 0.448036] [Firmware Bug]: ACPI: no secondary bus range in _CRS [ 0.456041] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.464166] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.469530] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536) [ 0.482505] pci 0000:00:00.0: [1022:9601] type 0 class 0x000600 [ 0.482652] pci 0000:00:01.0: [1022:9602] type 1 class 0x000604 [ 0.484130] pci 0000:00:0a.0: [1022:9609] type 1 class 0x000604 [ 0.484219] pci 0000:00:0a.0: PME# supported from D0 D3hot D3cold [ 0.484226] pci 0000:00:0a.0: PME# disabled [ 0.484280] pci 0000:00:11.0: [1002:4390] type 0 class 0x000101 [ 0.484314] pci 0000:00:11.0: reg 10: [io 0x3020-0x3027] [ 0.484331] pci 0000:00:11.0: reg 14: [io 0x3040-0x3043] [ 0.484347] pci 0000:00:11.0: reg 18: [io 0x3028-0x302f] [ 0.484363] pci 0000:00:11.0: reg 1c: [io 0x3044-0x3047] [ 0.484382] pci 0000:00:11.0: reg 20: [io 0x3000-0x300f] [ 0.484399] pci 0000:00:11.0: reg 24: [mem 0xd8409000-0xd84093ff] [ 0.484437] pci 0000:00:11.0: set SATA to AHCI mode [ 0.488090] pci 0000:00:12.0: [1002:4397] type 0 class 0x000c03 [ 0.488113] pci 0000:00:12.0: reg 10: [mem 0xd8404000-0xd8404fff] [ 0.488224] pci 0000:00:12.1: [1002:4398] type 0 class 0x000c03 [ 0.488252] pci 0000:00:12.1: reg 10: [mem 0xd8405000-0xd8405fff] [ 0.488370] pci 0000:00:12.2: [1002:4396] type 0 class 0x000c03 [ 0.488407] pci 0000:00:12.2: reg 10: [mem 0xd8409400-0xd84094ff] [ 0.488528] pci 0000:00:12.2: supports D1 D2 [ 0.488532] pci 0000:00:12.2: PME# supported from D0 D1 D2 D3hot [ 0.488538] pci 0000:00:12.2: PME# disabled [ 0.488576] pci 0000:00:13.0: [1002:4397] type 0 class 0x000c03 [ 0.488597] pci 0000:00:13.0: reg 10: [mem 0xd8406000-0xd8406fff] [ 0.488712] pci 0000:00:13.1: [1002:4398] type 0 class 0x000c03 [ 0.488736] pci 0000:00:13.1: reg 10: [mem 0xd8407000-0xd8407fff] [ 0.488855] pci 0000:00:13.2: [1002:4396] type 0 class 0x000c03 [ 0.488891] pci 0000:00:13.2: reg 10: [mem 0xd8409500-0xd84095ff] [ 0.489013] pci 0000:00:13.2: supports D1 D2 [ 0.489017] pci 0000:00:13.2: PME# supported from D0 D1 D2 D3hot [ 0.489024] pci 0000:00:13.2: PME# disabled [ 0.489067] pci 0000:00:14.0: [1002:4385] type 0 class 0x000c05 [ 0.489209] pci 0000:00:14.1: [1002:439c] type 0 class 0x000101 [ 0.489227] pci 0000:00:14.1: reg 10: [io 0x3030-0x3037] [ 0.489245] pci 0000:00:14.1: reg 14: [io 0x3048-0x304b] [ 0.489258] pci 0000:00:14.1: reg 18: [io 0x3038-0x303f] [ 0.489271] pci 0000:00:14.1: reg 1c: [io 0x304c-0x304f] [ 0.489284] pci 0000:00:14.1: reg 20: [io 0x3010-0x301f] [ 0.489336] pci 0000:00:14.2: [1002:4383] type 0 class 0x000403 [ 0.489371] pci 0000:00:14.2: reg 10: [mem 0xd8400000-0xd8403fff 64bit] [ 0.489449] pci 0000:00:14.2: PME# supported from D0 D3hot D3cold [ 0.489455] pci 0000:00:14.2: PME# disabled [ 0.489478] pci 0000:00:14.3: [1002:439d] type 0 class 0x000601 [ 0.489584] pci 0000:00:14.4: [1002:4384] type 1 class 0x000604 [ 0.492072] pci 0000:00:14.5: [1002:4399] type 0 class 0x000c03 [ 0.492090] pci 0000:00:14.5: reg 10: [mem 0xd8408000-0xd8408fff] [ 0.492184] pci 0000:00:18.0: [1022:1200] type 0 class 0x000600 [ 0.492211] pci 0000:00:18.1: [1022:1201] type 0 class 0x000600 [ 0.492234] pci 0000:00:18.2: [1022:1202] type 0 class 0x000600 [ 0.492258] pci 0000:00:18.3: [1022:1203] type 0 class 0x000600 [ 0.492284] pci 0000:00:18.4: [1022:1204] type 0 class 0x000600 [ 0.492318] PCI: peer root bus 00 res updated from pci conf [ 0.492375] pci 0000:01:05.0: [1002:9710] type 0 class 0x000300 [ 0.492393] pci 0000:01:05.0: reg 10: [mem 0xc0000000-0xcfffffff pref] [ 0.492403] pci 0000:01:05.0: reg 14: [io 0x1000-0x10ff] [ 0.492413] pci 0000:01:05.0: reg 18: [mem 0xd8100000-0xd810ffff] [ 0.492441] pci 0000:01:05.0: reg 24: [mem 0xd8000000-0xd80fffff] [ 0.492466] pci 0000:01:05.0: supports D1 D2 [ 0.492491] pci 0000:01:05.1: [1002:970f] type 0 class 0x000403 [ 0.492508] pci 0000:01:05.1: reg 10: [mem 0xd8110000-0xd8113fff] [ 0.492570] pci 0000:01:05.1: supports D1 D2 [ 0.492634] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.496038] pci 0000:00:01.0: bridge window [io 0x1000-0x1fff] [ 0.496044] pci 0000:00:01.0: bridge window [mem 0xd8000000-0xd81fffff] [ 0.496053] pci 0000:00:01.0: bridge window [mem 0xc0000000-0xcfffffff 64bit pref] [ 0.496152] pci 0000:02:00.0: [10ec:8168] type 0 class 0x000200 [ 0.496173] pci 0000:02:00.0: reg 10: [io 0x2000-0x20ff] [ 0.496217] pci 0000:02:00.0: reg 18: [mem 0xd0004000-0xd0004fff 64bit pref] [ 0.496244] pci 0000:02:00.0: reg 20: [mem 0xd0000000-0xd0003fff 64bit pref] [ 0.496260] pci 0000:02:00.0: reg 30: [mem 0xd8200000-0xd820ffff pref] [ 0.496312] pci 0000:02:00.0: supports D1 D2 [ 0.496316] pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 0.496323] pci 0000:02:00.0: PME# disabled [ 0.496389] pci 0000:00:0a.0: PCI bridge to [bus 02-02] [ 0.504044] pci 0000:00:0a.0: bridge window [io 0x2000-0x2fff] [ 0.504051] pci 0000:00:0a.0: bridge window [mem 0xd8200000-0xd82fffff] [ 0.504060] pci 0000:00:0a.0: bridge window [mem 0xd0000000-0xd00fffff 64bit pref] [ 0.504115] pci 0000:03:06.0: [168c:0029] type 0 class 0x000280 [ 0.504146] pci 0000:03:06.0: reg 10: [mem 0xd8300000-0xd830ffff] [ 0.504279] pci 0000:03:06.0: PME# supported from D0 D3hot [ 0.504287] pci 0000:03:06.0: PME# disabled [ 0.504355] pci 0000:00:14.4: PCI bridge to [bus 03-03] (subtractive decode) [ 0.512037] pci 0000:00:14.4: bridge window [io 0xf000-0xe000] (disabled) [ 0.512044] pci 0000:00:14.4: bridge window [mem 0xd8300000-0xd83fffff] [ 0.512052] pci 0000:00:14.4: bridge window [mem 0xdff00000-0xdfefffff pref] (disabled) [ 0.512057] pci 0000:00:14.4: bridge window [io 0x0000-0xffff] (subtractive decode) [ 0.512062] pci 0000:00:14.4: bridge window [mem 0xd0100000-0xdfffffff] (subtractive decode) [ 0.512067] pci 0000:00:14.4: bridge window [mem 0x80000000-0xd00fffff] (subtractive decode) [ 0.512072] pci 0000:00:14.4: bridge window [mem 0xf0000000-0xffffffff] (subtractive decode) [ 0.512090] pci_bus 0000:00: on NUMA node 0 [ 0.512095] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 0.512095] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.AGPB._PRT] [ 0.512105] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PBRA._PRT] [ 0.512149] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT] [ 0.512282] pci0000:00: Requesting ACPI _OSC control (0x1d) [ 0.528310] ACPI: PCI Interrupt Link [INTA] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.537025] ACPI: PCI Interrupt Link [INTB] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.545785] ACPI: PCI Interrupt Link [INTC] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.556305] ACPI: PCI Interrupt Link [INTD] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.565026] ACPI: PCI Interrupt Link [INTE] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.573907] ACPI: PCI Interrupt Link [INTF] (IRQs 9) *0, disabled. [ 0.581417] ACPI: PCI Interrupt Link [INTG] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.590178] ACPI: PCI Interrupt Link [INTH] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.600395] vgaarb: device added: PCI:0000:01:05.0,decodes=io+mem,owns=io+mem,locks=none [ 0.608043] vgaarb: loaded [ 0.612323] SCSI subsystem initialized [ 0.617817] Freeing initrd memory: 16436k freed [ 0.617817] libata version 3.00 loaded. [ 0.617817] usbcore: registered new interface driver usbfs [ 0.617817] usbcore: registered new interface driver hub [ 0.617817] usbcore: registered new device driver usb [ 0.617817] wmi: Mapper loaded [ 0.617817] PCI: Using ACPI for IRQ routing [ 0.617817] PCI: pci_cache_line_size set to 64 bytes [ 0.617817] reserve RAM buffer: 000000000009f800 - 000000000009ffff [ 0.617817] reserve RAM buffer: 000000006ffee000 - 000000006fffffff [ 0.617817] NetLabel: Initializing [ 0.617817] NetLabel: domain hash size = 128 [ 0.617817] NetLabel: protocols = UNLABELED CIPSOv4 [ 0.617817] NetLabel: unlabeled traffic allowed by default [ 0.617817] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 [ 0.617817] hpet0: 4 comparators, 32-bit 14.318180 MHz counter [ 0.618190] Switching to clocksource hpet [ 0.626218] Switched to NOHz mode on CPU #0 [ 0.627160] Switched to NOHz mode on CPU #1 [ 0.637951] AppArmor: AppArmor Filesystem Enabled [ 0.643804] pnp: PnP ACPI init [ 0.647038] ACPI: bus type pnp registered [ 0.651436] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.660501] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536) [ 0.672470] pnp 00:00: Plug and Play ACPI device, IDs PNP0a03 (active) [ 0.672640] pnp 00:01: [irq 8] [ 0.672645] pnp 00:01: [io 0x0070-0x0071] [ 0.672698] pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active) [ 0.672714] pnp 00:02: [io 0x0061] [ 0.672767] pnp 00:02: Plug and Play ACPI device, IDs PNP0800 (active) [ 0.672785] pnp 00:03: [dma 4] [ 0.672788] pnp 00:03: [io 0x0000-0x000f] [ 0.672793] pnp 00:03: [io 0x0081-0x0083] [ 0.672797] pnp 00:03: [io 0x0087] [ 0.672800] pnp 00:03: [io 0x0089-0x008b] [ 0.672803] pnp 00:03: [io 0x008f] [ 0.672807] pnp 00:03: [io 0x00c0-0x00df] [ 0.672862] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active) [ 0.672876] pnp 00:04: [io 0x00f0-0x00ff] [ 0.672887] pnp 00:04: [irq 13] [ 0.672941] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active) [ 0.672985] pnp 00:05: [mem 0xfed00000-0xfed003ff] [ 0.673039] pnp 00:05: Plug and Play ACPI device, IDs PNP0103 (active) [ 0.673067] pnp: PnP ACPI: found 6 devices [ 0.677642] ACPI: ACPI bus type pnp unregistered [ 0.682414] PnPBIOS: Disabled by ACPI PNP [ 0.724847] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.730586] pci 0000:00:01.0: bridge window [io 0x1000-0x1fff] [ 0.736784] pci 0000:00:01.0: bridge window [mem 0xd8000000-0xd81fffff] [ 0.743719] pci 0000:00:01.0: bridge window [mem 0xc0000000-0xcfffffff 64bit pref] [ 0.751632] pci 0000:00:0a.0: PCI bridge to [bus 02-02] [ 0.757013] pci 0000:00:0a.0: bridge window [io 0x2000-0x2fff] [ 0.763258] pci 0000:00:0a.0: bridge window [mem 0xd8200000-0xd82fffff] [ 0.770203] pci 0000:00:0a.0: bridge window [mem 0xd0000000-0xd00fffff 64bit pref] [ 0.778120] pci 0000:00:14.4: PCI bridge to [bus 03-03] [ 0.783494] pci 0000:00:14.4: bridge window [io disabled] [ 0.789268] pci 0000:00:14.4: bridge window [mem 0xd8300000-0xd83fffff] [ 0.796213] pci 0000:00:14.4: bridge window [mem pref disabled] [ 0.802489] pci 0000:00:0a.0: setting latency timer to 64 [ 0.802502] pci_bus 0000:00: resource 4 [io 0x0000-0xffff] [ 0.802507] pci_bus 0000:00: resource 5 [mem 0xd0100000-0xdfffffff] [ 0.802512] pci_bus 0000:00: resource 6 [mem 0x80000000-0xd00fffff] [ 0.802517] pci_bus 0000:00: resource 7 [mem 0xf0000000-0xffffffff] [ 0.802521] pci_bus 0000:01: resource 0 [io 0x1000-0x1fff] [ 0.802526] pci_bus 0000:01: resource 1 [mem 0xd8000000-0xd81fffff] [ 0.802530] pci_bus 0000:01: resource 2 [mem 0xc0000000-0xcfffffff 64bit pref] [ 0.802535] pci_bus 0000:02: resource 0 [io 0x2000-0x2fff] [ 0.802540] pci_bus 0000:02: resource 1 [mem 0xd8200000-0xd82fffff] [ 0.802544] pci_bus 0000:02: resource 2 [mem 0xd0000000-0xd00fffff 64bit pref] [ 0.802549] pci_bus 0000:03: resource 1 [mem 0xd8300000-0xd83fffff] [ 0.802554] pci_bus 0000:03: resource 4 [io 0x0000-0xffff] [ 0.802558] pci_bus 0000:03: resource 5 [mem 0xd0100000-0xdfffffff] [ 0.802562] pci_bus 0000:03: resource 6 [mem 0x80000000-0xd00fffff] [ 0.802567] pci_bus 0000:03: resource 7 [mem 0xf0000000-0xffffffff] [ 0.802617] NET: Registered protocol family 2 [ 0.807281] IP route cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.814922] TCP established hash table entries: 131072 (order: 8, 1048576 bytes) [ 0.823416] TCP bind hash table entries: 65536 (order: 7, 524288 bytes) [ 0.830997] TCP: Hash tables configured (established 131072 bind 65536) [ 0.837916] TCP reno registered [ 0.841201] UDP hash table entries: 512 (order: 2, 16384 bytes) [ 0.847274] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) [ 0.853854] NET: Registered protocol family 1 [ 0.858424] pci 0000:00:01.0: MSI quirk detected; subordinate MSI disabled [ 0.865582] pci 0000:01:05.0: Boot video device [ 0.865596] PCI: CLS 64 bytes, default 64 [ 0.865951] cpufreq-nforce2: No nForce2 chipset. [ 0.871126] audit: initializing netlink socket (disabled) [ 0.876776] type=2000 audit(1322453512.876:1): initialized [ 0.907042] highmem bounce pool size: 64 pages [ 0.911623] HugeTLB registered 4 MB page size, pre-allocated 0 pages [ 0.919507] VFS: Disk quotas dquot_6.5.2 [ 0.923670] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 0.931933] fuse init (API version 7.16) [ 0.936066] msgmni has been set to 1709 [ 0.940445] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [ 0.948030] io scheduler noop registered [ 0.952079] io scheduler deadline registered [ 0.956518] io scheduler cfq registered (default) [ 0.961563] pcieport 0000:00:0a.0: setting latency timer to 64 [ 0.961641] pcieport 0000:00:0a.0: irq 40 for MSI/MSI-X [ 0.961780] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 [ 0.967721] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 [ 0.974651] input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0 [ 0.986284] ACPI: Power Button [PWRB] [ 0.990167] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 0.997773] ACPI: Power Button [PWRF] [ 1.001640] ACPI: Fan [FAN0] (on) [ 1.005350] ACPI: acpi_idle registered with cpuidle [ 1.028063] thermal LNXTHERM:00: registered as thermal_zone0 [ 1.033845] ACPI: Thermal Zone [TZ00] (40 C) [ 1.038211] ERST: Table is not found! [ 1.042063] isapnp: Scanning for PnP cards... [ 1.042087] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled [ 1.063191] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A [ 1.436173] isapnp: No Plug & Play device found [ 1.548255] Linux agpgart interface v0.103 [ 1.553492] brd: module loaded [ 1.557070] loop: module loaded [ 1.560414] i2c-core: driver [adp5520] using legacy suspend method [ 1.566723] i2c-core: driver [adp5520] using legacy resume method [ 1.572993] pata_acpi 0000:00:14.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 1.580617] Fixed MDIO Bus: probed [ 1.584124] PPP generic driver version 2.4.2 [ 1.588529] tun: Universal TUN/TAP device driver, 1.6 [ 1.593714] tun: (C) 1999-2004 Max Krasnyansky [ 1.600084] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 1.606700] ehci_hcd 0000:00:12.2: PCI INT B -> GSI 17 (level, low) -> IRQ 17 [ 1.613971] ehci_hcd 0000:00:12.2: EHCI Host Controller [ 1.619306] ehci_hcd 0000:00:12.2: new USB bus registered, assigned bus number 1 [ 1.626899] ehci_hcd 0000:00:12.2: applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround [ 1.635806] ehci_hcd 0000:00:12.2: debug port 1 [ 1.640539] ehci_hcd 0000:00:12.2: irq 17, io mem 0xd8409400 [ 1.656029] ehci_hcd 0000:00:12.2: USB 2.0 started, EHCI 1.00 [ 1.662151] hub 1-0:1.0: USB hub found [ 1.666173] hub 1-0:1.0: 6 ports detected [ 1.670432] ehci_hcd 0000:00:13.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19 [ 1.677812] ehci_hcd 0000:00:13.2: EHCI Host Controller [ 1.683249] ehci_hcd 0000:00:13.2: new USB bus registered, assigned bus number 2 [ 1.690853] ehci_hcd 0000:00:13.2: applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround [ 1.699723] ehci_hcd 0000:00:13.2: debug port 1 [ 1.704388] ehci_hcd 0000:00:13.2: irq 19, io mem 0xd8409500 [ 1.720025] ehci_hcd 0000:00:13.2: USB 2.0 started, EHCI 1.00 [ 1.725985] hub 2-0:1.0: USB hub found [ 1.729868] hub 2-0:1.0: 6 ports detected [ 1.734035] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 1.740326] ohci_hcd 0000:00:12.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 1.747597] ohci_hcd 0000:00:12.0: OHCI Host Controller [ 1.752933] ohci_hcd 0000:00:12.0: new USB bus registered, assigned bus number 3 [ 1.760552] ohci_hcd 0000:00:12.0: irq 16, io mem 0xd8404000 [ 1.824176] hub 3-0:1.0: USB hub found [ 1.828109] hub 3-0:1.0: 3 ports detected [ 1.832314] ohci_hcd 0000:00:12.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 1.839609] ohci_hcd 0000:00:12.1: OHCI Host Controller [ 1.845050] ohci_hcd 0000:00:12.1: new USB bus registered, assigned bus number 4 [ 1.852700] ohci_hcd 0000:00:12.1: irq 16, io mem 0xd8405000 [ 1.916086] hub 4-0:1.0: USB hub found [ 1.919909] hub 4-0:1.0: 3 ports detected [ 1.924150] ohci_hcd 0000:00:13.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 1.931468] ohci_hcd 0000:00:13.0: OHCI Host Controller [ 1.936798] ohci_hcd 0000:00:13.0: new USB bus registered, assigned bus number 5 [ 1.944410] ohci_hcd 0000:00:13.0: irq 18, io mem 0xd8406000 [ 2.008164] hub 5-0:1.0: USB hub found [ 2.012096] hub 5-0:1.0: 3 ports detected [ 2.016308] ohci_hcd 0000:00:13.1: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 2.023615] ohci_hcd 0000:00:13.1: OHCI Host Controller [ 2.029051] ohci_hcd 0000:00:13.1: new USB bus registered, assigned bus number 6 [ 2.036810] ohci_hcd 0000:00:13.1: irq 18, io mem 0xd8407000 [ 2.100076] hub 6-0:1.0: USB hub found [ 2.103886] hub 6-0:1.0: 3 ports detected [ 2.108100] ohci_hcd 0000:00:14.5: PCI INT C -> GSI 18 (level, low) -> IRQ 18 [ 2.115384] ohci_hcd 0000:00:14.5: OHCI Host Controller [ 2.120715] ohci_hcd 0000:00:14.5: new USB bus registered, assigned bus number 7 [ 2.132071] ohci_hcd 0000:00:14.5: irq 18, io mem 0xd8408000 [ 2.196177] hub 7-0:1.0: USB hub found [ 2.200101] hub 7-0:1.0: 2 ports detected [ 2.204306] uhci_hcd: USB Universal Host Controller Interface driver [ 2.210948] i8042: PNP: No PS/2 controller found. Probing ports directly. [ 2.218340] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 2.223674] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 2.229041] mousedev: PS/2 mouse device common for all mice [ 2.235052] rtc_cmos 00:01: RTC can wake from S4 [ 2.240023] rtc_cmos 00:01: rtc core: registered rtc_cmos as rtc0 [ 2.246323] rtc0: alarms up to one day, 114 bytes nvram, hpet irqs [ 2.252648] device-mapper: uevent: version 1.0.3 [ 2.257447] device-mapper: ioctl: 4.19.1-ioctl (2011-01-07) initialised: dm-devel at redhat.com [ 2.266156] device-mapper: multipath: version 1.2.0 loaded [ 2.267928] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input2 [ 2.280470] device-mapper: multipath round-robin: version 1.0.0 loaded [ 2.287144] EISA: Probing bus 0 at eisa.0 [ 2.291296] EISA: Cannot allocate resource for mainboard [ 2.296732] Cannot allocate resource for EISA slot 1 [ 2.301783] Cannot allocate resource for EISA slot 2 [ 2.306883] Cannot allocate resource for EISA slot 3 [ 2.311986] Cannot allocate resource for EISA slot 4 [ 2.317104] Cannot allocate resource for EISA slot 5 [ 2.322191] Cannot allocate resource for EISA slot 6 [ 2.327296] Cannot allocate resource for EISA slot 7 [ 2.332407] Cannot allocate resource for EISA slot 8 [ 2.337460] EISA: Detected 0 cards. [ 2.341224] cpuidle: using governor ladder [ 2.345457] cpuidle: using governor menu [ 2.349696] TCP cubic registered [ 2.353093] NET: Registered protocol family 10 [ 2.358068] NET: Registered protocol family 17 [ 2.362653] Registering the dns_resolver key type [ 2.364046] usb 4-3: new full speed USB device using ohci_hcd and address 2 [ 2.374578] powernow-k8: Found 1 AMD Athlon(tm) II X2 250 Processor (2 cpu cores) (version 2.20.00) [ 2.383791] powernow-k8: 0 : pstate 0 (3000 MHz) [ 2.388831] powernow-k8: 1 : pstate 1 (2300 MHz) [ 2.393841] powernow-k8: 2 : pstate 2 (1800 MHz) [ 2.398849] powernow-k8: 3 : pstate 3 (800 MHz) [ 2.403824] Using IPI No-Shortcut mode [ 2.407850] PM: Hibernation image not present or could not be loaded. [ 2.407865] registered taskstats version 1 [ 2.412545] Magic number: 3:174:162 [ 2.416560] rtc_cmos 00:01: setting system clock to 2011-11-28 04:11:55 UTC (1322453515) [ 2.424784] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found [ 2.430930] EDD information not available. [ 2.435261] Freeing unused kernel memory: 700k freed [ 2.440730] Write protecting the kernel text: 5192k [ 2.445965] Write protecting the kernel read-only data: 2068k [ 2.480242] ramzswap: disk size not provided. You can use disksize_kb module param to specify size. [ 2.480246] Using default: (25% of RAM). [ 2.493428] ramzswap: disk size set to 450412 kB [ 2.503124] <30>udev[72]: starting version 167 [ 2.547042] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded [ 2.554429] ahci 0000:00:11.0: version 3.0 [ 2.554453] ahci 0000:00:11.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22 [ 2.563151] ahci 0000:00:11.0: irq 41 for MSI/MSI-X [ 2.563257] ahci 0000:00:11.0: AHCI 0001.0100 32 slots 4 ports 3 Gbps 0xf impl SATA mode [ 2.571480] ahci 0000:00:11.0: flags: 64bit ncq sntf ilck pm led clo pmp pio slum part ccc [ 2.580907] r8169 0000:02:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 2.587899] scsi0 : ahci [ 2.590696] r8169 0000:02:00.0: setting latency timer to 64 [ 2.590779] r8169 0000:02:00.0: irq 42 for MSI/MSI-X [ 2.591123] r8169 0000:02:00.0: eth0: RTL8168d/8111d at 0xf8006000, ed:0b:00:00:e0:00, XID 083000c0 IRQ 42 [ 2.600931] scsi1 : ahci [ 2.616971] scsi2 : ahci [ 2.622872] scsi3 : ahci [ 2.625879] ata1: SATA max UDMA/133 abar m1024 at 0xd8409000 port 0xd8409100 irq 41 [ 2.633457] ata2: SATA max UDMA/133 abar m1024 at 0xd8409000 port 0xd8409180 irq 41 [ 2.640928] ata3: SATA max UDMA/133 abar m1024 at 0xd8409000 port 0xd8409200 irq 41 [ 2.648461] ata4: SATA max UDMA/133 abar m1024 at 0xd8409000 port 0xd8409280 irq 41 [ 2.659527] scsi4 : pata_atiixp [ 2.663609] scsi5 : pata_atiixp [ 2.667554] ata5: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x3010 irq 14 [ 2.674942] ata6: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x3018 irq 15 [ 2.682108] usb 3-1: new low speed USB device using ohci_hcd and address 2 [ 2.878180] input: HID 0ccd:0077 as /devices/pci0000:00/0000:00:12.1/usb4/4-3/4-3:1.3/input/input3 [ 2.887658] generic-usb 0003:0CCD:0077.0001: input,hidraw0: USB HID v1.00 Device [HID 0ccd:0077] on usb-0000:00:12.1-3/input3 [ 2.909466] input: HID 04d9:1203 as /devices/pci0000:00/0000:00:12.0/usb3/3-1/3-1:1.0/input/input4 [ 2.918653] generic-usb 0003:04D9:1203.0002: input,hidraw1: USB HID v1.11 Keyboard [HID 04d9:1203] on usb-0000:00:12.0-1/input0 [ 2.947205] input: HID 04d9:1203 as /devices/pci0000:00/0000:00:12.0/usb3/3-1/3-1:1.1/input/input5 [ 2.956468] generic-usb 0003:04D9:1203.0003: input,hidraw2: USB HID v1.11 Device [HID 04d9:1203] on usb-0000:00:12.0-1/input1 [ 2.968128] usbcore: registered new interface driver usbhid [ 2.973907] usbhid: USB HID core driver [ 2.980069] ata3: SATA link down (SStatus 0 SControl 300) [ 2.985612] ata2: SATA link down (SStatus 0 SControl 300) [ 2.996029] usb 3-2: new low speed USB device using ohci_hcd and address 3 [ 3.006161] ata4: SATA link down (SStatus 0 SControl 300) [ 3.160050] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [ 3.167349] ata1.00: ATA-8: Hitachi HDP725050GLA360, GM4OA52A, max UDMA/133 [ 3.174467] ata1.00: 976773168 sectors, multi 0: LBA48 NCQ (depth 31/32), AA [ 3.181438] input: B16_b_02 USB-PS/2 Optical Mouse as /devices/pci0000:00/0000:00:12.0/usb3/3-2/3-2:1.0/input/input6 [ 3.181527] generic-usb 0003:046D:C024.0004: input,hidraw3: USB HID v1.10 Mouse [B16_b_02 USB-PS/2 Optical Mouse] on usb-0000:00:12.0-2/input0 [ 3.206421] ata1.00: configured for UDMA/133 [ 3.211028] scsi 0:0:0:0: Direct-Access ATA Hitachi HDP72505 GM4O PQ: 0 ANSI: 5 [ 3.219437] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 3.224942] sd 0:0:0:0: [sda] 976773168 512-byte logical blocks: (500 GB/465 GiB) [ 3.232665] sd 0:0:0:0: [sda] Write Protect is off [ 3.237575] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 3.237607] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 3.259506] sda: sda1 sda2 sda3 [ 3.263262] sd 0:0:0:0: [sda] Attached SCSI disk [ 3.726054] Btrfs loaded [ 3.737570] xor: automatically using best checksumming function: pIII_sse [ 3.764019] pIII_sse : 3201.000 MB/sec [ 3.768509] xor: using function: pIII_sse (3201.000 MB/sec) [ 3.780889] device-mapper: dm-raid45: initialized v0.2594b [ 3.789674] md: linear personality registered for level -1 [ 3.801132] md: multipath personality registered for level -4 [ 3.810274] md: raid0 personality registered for level 0 [ 3.824589] md: raid1 personality registered for level 1 [ 3.832942] async_tx: api initialized (async) [ 3.904032] raid6: int32x1 1345 MB/s [ 3.972021] raid6: int32x2 1402 MB/s [ 4.040070] raid6: int32x4 1043 MB/s [ 4.108014] raid6: int32x8 803 MB/s [ 4.176023] raid6: mmxx1 2483 MB/s [ 4.244015] raid6: mmxx2 4697 MB/s [ 4.312034] raid6: sse1x1 2176 MB/s [ 4.380035] raid6: sse1x2 3592 MB/s [ 4.448024] raid6: sse2x1 4149 MB/s [ 4.520032] raid6: sse2x2 6885 MB/s [ 4.523959] raid6: using algorithm sse2x2 (6885 MB/s) [ 4.545270] md: raid6 personality registered for level 6 [ 4.551624] md: raid5 personality registered for level 5 [ 4.557329] md: raid4 personality registered for level 4 [ 4.572376] md: raid10 personality registered for level 10 [ 16.346420] EXT3-fs (dm-0): recovery required on readonly filesystem [ 16.353258] EXT3-fs (dm-0): write access will be enabled during recovery [ 16.382409] EXT3-fs: barriers not enabled [ 17.920337] kjournald starting. Commit interval 5 seconds [ 17.920476] EXT3-fs (dm-0): orphan cleanup on readonly fs [ 17.920482] ext3_orphan_cleanup: deleting unreferenced inode 26924626 [ 17.920511] EXT3-fs (dm-0): 1 orphan inode deleted [ 17.920512] EXT3-fs (dm-0): recovery complete [ 17.950387] EXT3-fs (dm-0): mounted filesystem with ordered data mode [ 41.807682] <30>udev[423]: starting version 167 [ 41.827903] lp: driver loaded but no devices found [ 41.885666] shpchp 0000:00:01.0: HPC vendor_id 1022 device_id 9602 ss_vid 1022 ss_did 9602 [ 41.885670] shpchp 0000:00:01.0: Cannot reserve MMIO region [ 41.893246] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4 [ 42.028134] ACPI: resource piix4_smbus [io 0x0b00-0x0b07] conflicts with ACPI region SMB0 [io 0xb00-0xb0b] [ 42.028137] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 42.064040] SP5100 TCO timer: SP5100 TCO WatchDog Timer Driver v0.01 [ 42.072226] SP5100 TCO timer: mmio address 0xfec000f0 already in use [ 42.092417] <30>udev[513]: renamed network interface eth0 to eth5 [ 42.187984] type=1400 audit(1322453555.264:2): apparmor="STATUS" operation="profile_load" name="/sbin/dhclient" pid=716 comm="apparmor_parser" [ 42.188312] type=1400 audit(1322453555.268:3): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=716 comm="apparmor_parser" [ 42.188483] type=1400 audit(1322453555.268:4): apparmor="STATUS" operation="profile_load" name="/usr/lib/connman/scripts/dhclient-script" pid=716 comm="apparmor_parser" [ 42.189192] type=1400 audit(1322453555.268:5): apparmor="STATUS" operation="profile_replace" name="/sbin/dhclient" pid=683 comm="apparmor_parser" [ 42.189842] type=1400 audit(1322453555.268:6): apparmor="STATUS" operation="profile_replace" name="/usr/lib/NetworkManager/nm-dhcp- client.action" pid=683 comm="apparmor_parser" [ 42.190262] type=1400 audit(1322453555.268:7): apparmor="STATUS" operation="profile_replace" name="/usr/lib/connman/scripts/dhclient-script" pid=683 comm="apparmor_parser" [ 42.195769] cfg80211: Calling CRDA to update world regulatory domain [ 42.293006] cfg80211: World regulatory domain updated: [ 42.293009] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) [ 42.293011] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) [ 42.293013] cfg80211: (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm) [ 42.293015] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm) [ 42.293017] cfg80211: (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) [ 42.293019] cfg80211: (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) [ 42.385685] ath9k 0000:03:06.0: PCI INT A -> GSI 21 (level, low) -> IRQ 21 [ 42.552877] usbcore: registered new interface driver snd-usb-audio [ 43.959786] ath: EEPROM regdomain: 0x30 [ 43.959788] ath: EEPROM indicates we should expect a direct regpair map [ 43.959790] ath: Country alpha2 being used: AM [ 43.959792] ath: Regpair used: 0x30 [ 43.959906] cfg80211: Updating information on frequency 2412 MHz for a 20 MHz width channel with regulatory rule: [ 43.959908] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959910] cfg80211: Updating information on frequency 2417 MHz for a 20 MHz width channel with regulatory rule: [ 43.959912] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959914] cfg80211: Updating information on frequency 2422 MHz for a 20 MHz width channel with regulatory rule: [ 43.959916] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959917] cfg80211: Updating information on frequency 2427 MHz for a 20 MHz width channel with regulatory rule: [ 43.959919] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959921] cfg80211: Updating information on frequency 2432 MHz for a 20 MHz width channel with regulatory rule: [ 43.959923] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959924] cfg80211: Updating information on frequency 2437 MHz for a 20 MHz width channel with regulatory rule: [ 43.959926] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959928] cfg80211: Updating information on frequency 2442 MHz for a 20 MHz width channel with regulatory rule: [ 43.959930] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959931] cfg80211: Updating information on frequency 2447 MHz for a 20 MHz width channel with regulatory rule: [ 43.959933] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959935] cfg80211: Updating information on frequency 2452 MHz for a 20 MHz width channel with regulatory rule: [ 43.959937] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959938] cfg80211: Updating information on frequency 2457 MHz for a 20 MHz width channel with regulatory rule: [ 43.959940] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959942] cfg80211: Updating information on frequency 2462 MHz for a 20 MHz width channel with regulatory rule: [ 43.959943] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959945] cfg80211: Disabling freq 2467 MHz as custom regd has no rule that fits a 20 MHz wide channel [ 43.959947] cfg80211: Disabling freq 2472 MHz as custom regd has no rule that fits a 20 MHz wide channel [ 43.959949] cfg80211: Disabling freq 2484 MHz as custom regd has no rule that fits a 20 MHz wide channel [ 43.962455] cfg80211: Updating information on frequency 2412 MHz for a 20 MHz width channel with regulatory rule: [ 43.962457] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962459] cfg80211: Updating information on frequency 2417 MHz for a 20 MHz width channel with regulatory rule: [ 43.962461] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962463] cfg80211: Updating information on frequency 2422 MHz for a 20 MHz width channel with regulatory rule: [ 43.962465] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962467] cfg80211: Updating information on frequency 2427 MHz for a 20 MHz width channel with regulatory rule: [ 43.962469] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962470] cfg80211: Updating information on frequency 2432 MHz for a 20 MHz width channel with regulatory rule: [ 43.962472] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962474] cfg80211: Updating information on frequency 2437 MHz for a 20 MHz width channel with regulatory rule: [ 43.962476] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962478] cfg80211: Updating information on frequency 2442 MHz for a 20 MHz width channel with regulatory rule: [ 43.962480] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962482] cfg80211: Updating information on frequency 2447 MHz for a 20 MHz width channel with regulatory rule: [ 43.962484] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962485] cfg80211: Updating information on frequency 2452 MHz for a 20 MHz width channel with regulatory rule: [ 43.962487] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962489] cfg80211: Updating information on frequency 2457 MHz for a 20 MHz width channel with regulatory rule: [ 43.962491] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962493] cfg80211: Updating information on frequency 2462 MHz for a 20 MHz width channel with regulatory rule: [ 43.962495] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962497] cfg80211: Updating information on frequency 2467 MHz for a 20 MHz width channel with regulatory rule: [ 43.962499] cfg80211: 2457000 KHz - 2482000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962500] cfg80211: Updating information on frequency 2472 MHz for a 20 MHz width channel with regulatory rule: [ 43.962502] cfg80211: 2457000 KHz - 2482000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962504] cfg80211: Updating information on frequency 2484 MHz for a 20 MHz width channel with regulatory rule: [ 43.962506] cfg80211: 2474000 KHz - 2494000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.970787] ieee80211 phy0: Selected rate control algorithm 'ath9k_rate_control' [ 43.971254] Registered led device: ath9k-phy0::radio [ 43.971268] Registered led device: ath9k-phy0::assoc [ 43.971281] Registered led device: ath9k-phy0::tx [ 43.971296] Registered led device: ath9k-phy0::rx [ 43.971299] ieee80211 phy0: Atheros AR9280 Rev:2 mem=0xf8440000, irq=21 [ 43.971422] cfg80211: Calling CRDA for country: AM [ 43.985168] cfg80211: Updating information on frequency 2412 MHz for a 20 MHz width channel with regulatory rule: [ 43.985171] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985173] cfg80211: Updating information on frequency 2417 MHz for a 20 MHz width channel with regulatory rule: [ 43.985176] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985177] cfg80211: Updating information on frequency 2422 MHz for a 20 MHz width channel with regulatory rule: [ 43.985179] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985181] cfg80211: Updating information on frequency 2427 MHz for a 20 MHz width channel with regulatory rule: [ 43.985183] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985184] cfg80211: Updating information on frequency 2432 MHz for a 20 MHz width channel with regulatory rule: [ 43.985186] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985188] cfg80211: Updating information on frequency 2437 MHz for a 20 MHz width channel with regulatory rule: [ 43.985189] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985191] cfg80211: Updating information on frequency 2442 MHz for a 20 MHz width channel with regulatory rule: [ 43.985193] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985194] cfg80211: Updating information on frequency 2447 MHz for a 20 MHz width channel with regulatory rule: [ 43.985196] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985198] cfg80211: Updating information on frequency 2452 MHz for a 20 MHz width channel with regulatory rule: [ 43.985200] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985201] cfg80211: Updating information on frequency 2457 MHz for a 20 MHz width channel with regulatory rule: [ 43.985203] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985205] cfg80211: Updating information on frequency 2462 MHz for a 20 MHz width channel with regulatory rule: [ 43.985207] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985208] cfg80211: Updating information on frequency 2467 MHz for a 20 MHz width channel with regulatory rule: [ 43.985210] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985212] cfg80211: Updating information on frequency 2472 MHz for a 20 MHz width channel with regulatory rule: [ 43.985214] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985215] cfg80211: Disabling freq 2484 MHz [ 43.985218] cfg80211: Regulatory domain changed to country: AM [ 43.985219] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) [ 43.985221] cfg80211: (2402000 KHz - 2482000 KHz @ 40000 KHz), (N/A, 2000 mBm) [ 43.985222] cfg80211: (5170000 KHz - 5250000 KHz @ 20000 KHz), (N/A, 1800 mBm) [ 43.985224] cfg80211: (5250000 KHz - 5330000 KHz @ 20000 KHz), (N/A, 1800 mBm) [ 44.068231] ADDRCONF(NETDEV_UP): wlan0: link is not ready [ 44.213372] EXT3-fs (dm-0): using internal journal [ 44.721119] EXT3-fs: barriers not enabled [ 44.721749] kjournald starting. Commit interval 5 seconds [ 44.775506] EXT3-fs (sda2): using internal journal [ 44.775515] EXT3-fs (sda2): mounted filesystem with ordered data mode [ 44.824766] RPC: Registered udp transport module. [ 44.824769] RPC: Registered tcp transport module. [ 44.824770] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 44.834537] FS-Cache: Loaded [ 44.863058] FS-Cache: Netfs 'nfs' registered for caching [ 44.906194] Installing knfsd (copyright (C) 1996 okir at monad.swb.de). [ 44.963589] type=1400 audit(1322453558.040:8): apparmor="STATUS" operation="profile_replace" name="/sbin/dhclient" pid=1047 comm="apparmor_parser" [ 44.963867] type=1400 audit(1322453558.040:9): apparmor="STATUS" operation="profile_replace" name="/usr/lib/NetworkManager/nm-dhcp- client.action" pid=1047 comm="apparmor_parser" [ 44.964245] type=1400 audit(1322453558.044:10): apparmor="STATUS" operation="profile_replace" name="/usr/lib/connman/scripts/dhclient-script" pid=1047 comm="apparmor_parser" [ 44.972367] type=1400 audit(1322453558.052:11): apparmor="STATUS" operation="profile_load" name="/usr/bin/evince" pid=1049 comm="apparmor_parser" [ 45.078531] wlan0: authenticate with 00:24:01:63:89:bd (try 1) [ 45.080800] wlan0: authenticated [ 45.080823] wlan0: associate with 00:24:01:63:89:bd (try 1) [ 45.083291] wlan0: RX AssocResp from 00:24:01:63:89:bd (capab=0x401 status=0 aid=2) [ 45.083294] wlan0: associated [ 45.083608] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready [ 45.097598] ppdev: user-space parallel port driver [ 45.582849] kvm: Nested Virtualization enabled [ 45.809676] pci 0000:01:05.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 45.834999] [drm] Initialized drm 1.1.0 20060810 [ 45.864594] [drm] radeon defaulting to kernel modesetting. [ 45.864597] [drm] radeon kernel modesetting enabled. [ 45.864657] radeon 0000:01:05.0: setting latency timer to 64 [ 45.867133] [drm] initializing kernel modesetting (RS880 0x1002:0x9710). [ 45.867160] [drm] register mmio base: 0xD8100000 [ 45.867162] [drm] register mmio size: 65536 [ 45.867239] ATOM BIOS: B43106 [ 45.867270] radeon 0000:01:05.0: VRAM: 256M 0x00000000C0000000 - 0x00000000CFFFFFFF (256M used) [ 45.867272] radeon 0000:01:05.0: GTT: 512M 0x00000000A0000000 - 0x00000000BFFFFFFF [ 45.867628] [drm] Detected VRAM RAM=256M, BAR=256M [ 45.867631] [drm] RAM width 32bits DDR [ 45.875994] [TTM] Zone kernel: Available graphics memory: 438016 kiB. [ 45.875996] [TTM] Zone highmem: Available graphics memory: 900832 kiB. [ 45.876015] [TTM] Initializing pool allocator. [ 45.876088] [drm] radeon: 256M of VRAM memory ready [ 45.876089] [drm] radeon: 512M of GTT memory ready. [ 45.876105] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010). [ 45.876106] [drm] Driver supports precise vblank timestamp query. [ 45.876140] [drm] radeon: irq initialized. [ 45.876142] [drm] GART: num cpu pages 131072, num gpu pages 131072 [ 45.876988] [drm] Loading RS780 Microcode [ 45.876990] radeon_cp.0: Missing Free firmware [ 45.915550] [drm:r600_startup] *ERROR* Failed to load firmware! [ 45.921989] radeon 0000:01:05.0: disabling GPU acceleration [ 45.928744] radeon 0000:01:05.0: ef428800 unpin not necessary [ 45.928750] radeon 0000:01:05.0: ef428800 unpin not necessary [ 45.928757] [drm] Enabling audio support [ 45.928766] failed to evaluate ATIF got AE_BAD_PARAMETER [ 45.929090] [drm] Radeon Display Connectors [ 45.929094] [drm] Connector 0: [ 45.929097] [drm] VGA [ 45.929101] [drm] DDC: 0x7e40 0x7e40 0x7e44 0x7e44 0x7e48 0x7e48 0x7e4c 0x7e4c [ 45.929104] [drm] Encoders: [ 45.929107] [drm] CRT1: INTERNAL_KLDSCP_DAC1 [ 45.929110] [drm] Connector 1: [ 45.929112] [drm] HDMI-A [ 45.929114] [drm] HPD3 [ 45.929118] [drm] DDC: 0x7e50 0x7e50 0x7e54 0x7e54 0x7e58 0x7e58 0x7e5c 0x7e5c [ 45.929121] [drm] Encoders: [ 45.929124] [drm] DFP3: INTERNAL_KLDSCP_LVTMA [ 45.993047] [drm] radeon: power management initialized [ 46.117232] [drm] fb mappable at 0xC0040000 [ 46.117237] [drm] vram apper at 0xC0000000 [ 46.117240] [drm] size 5324800 [ 46.117243] [drm] fb depth is 24 [ 46.117246] [drm] pitch is 5888 [ 46.119045] fbcon: radeondrmfb (fb0) is primary device [ 46.122246] Console: switching to colour frame buffer device 180x56 [ 46.122257] fb0: radeondrmfb frame buffer device [ 46.122261] drm: registered panic notifier [ 46.122271] [drm] Initialized radeon 2.8.0 20080528 for 0000:01:05.0 on minor 0 [ 55.584060] wlan0: no IPv6 routers present This dmesg was made after booting from coreboot which contained the following commits: 2687844 M4A785T-M: fix ACPI's P-States Table 1eb55d0 Add ASUS M4A785T-M mainboard support e8d0122 RS780: print the vgainfo 0dbfb54 Remove unused code files and cosmetic changes (HEAD from master) Denis. From gerrit at coreboot.org Mon Nov 28 05:34:15 2011 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Mon, 28 Nov 2011 05:34:15 +0100 Subject: [coreboot] Patch set updated for coreboot: 26a17fa M4A785T-M: fix ACPI's P-States Table References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/458 -gerrit commit 26a17fa00218a47c7fa1b2c93f9813218ae0e693 Author: Denis 'GNUtoo' Carikli Date: Sun Nov 27 22:04:02 2011 +0100 M4A785T-M: fix ACPI's P-States Table Without that fix the linux kernel cannot change the frequency of the CPUs with cpufreq. Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/m4a785t-m/acpi/cpstate.asl | 36 +++++++++++++++++++----- 1 files changed, 28 insertions(+), 8 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl index 6a1b002..0ee537d 100644 --- a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl +++ b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl @@ -46,22 +46,42 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) Name(_PSS, Package(){ Package () { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, + 0x00000BB8, + 0x000078D9, + 0x00000004, + 0x00000004, 0x00000000, 0x00000000 }, Package () { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, + 0x000008FC, + 0x0000659A, + 0x00000004, + 0x00000004, 0x00000001, 0x00000001 + }, + + Package () + { + 0x00000708, + 0x000056BF, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package () + { + 0x00000320, + 0x00001FA1, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 } }) From gerrit at coreboot.org Mon Nov 28 05:34:16 2011 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Mon, 28 Nov 2011 05:34:16 +0100 Subject: [coreboot] Patch set updated for coreboot: 00dec5d Add ASUS M4A785T-M mainboard support References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/457 -gerrit commit 00dec5d1fce2fac8f866fc9b5e54ab6f036f3ee6 Author: Denis 'GNUtoo' Carikli Date: Sun Nov 27 15:58:38 2011 +0100 Add ASUS M4A785T-M mainboard support This mainboard is very similar to the M4A785-M, but it has DDR3 instead of DDR2. That's why most of the code was copied or included from the m4a785-m directory Notable changes between the two mainboards include: * the selection of the last microcode (mc_patch_010000b6.h) which made it pass the CPU init. * the selection of DDR3 which made it pass the ram init This change was tested with the Trisquel 5.0 GNU/Linux distribution which uses the linux-libre version 2.6.38-12-generic The mainboard boots fine, however some special care is required for the onboard sound CODEC, and the onboard video chip: * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue is the same than the ASUS M4A785-M mainboard: It causes a flood of interupts which prevents booting * The internal video chip currently requires pci=nocrs, else the graphics are frozen as soon as the radeon module loads, and dmesg would print the following(the card only has 256M, and the mainboard was equiped with 2G of RAM): [ 3.674762] [drm] radeon: 3584M of VRAM memory ready [ 3.679863] [drm] radeon: 512M of GTT memory ready. instead of : [ 45.876088] [drm] radeon: 256M of VRAM memory ready [ 45.876089] [drm] radeon: 512M of GTT memory ready. The following peripherals were tested: * The ath9k PCI wireless card was tested * The SATA hard disk works fine * the USB keyboard and mouse work fine * htop see 2 cores * serial port works under coreboot and GNU/Linux * power off and reboot works CPU frequency cannot be changed yet, this is addressed in a new commit. More detail are available here: http://www.coreboot.org/ASUS_M4A785T-M dmesg is available here: http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html The mailing list thread on the graphic problem is here: http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/m4a785-m/mainboard.c | 4 + src/mainboard/asus/m4a785t-m/Kconfig | 86 ++ src/mainboard/asus/m4a785t-m/acpi/cpstate.asl | 75 + src/mainboard/asus/m4a785t-m/acpi/ide.asl | 244 ++++ src/mainboard/asus/m4a785t-m/acpi/routing.asl | 300 ++++ src/mainboard/asus/m4a785t-m/acpi/sata.asl | 149 ++ src/mainboard/asus/m4a785t-m/acpi/usb.asl | 161 +++ src/mainboard/asus/m4a785t-m/acpi_tables.c | 21 + src/mainboard/asus/m4a785t-m/chip.h | 23 + src/mainboard/asus/m4a785t-m/cmos.layout | 98 ++ src/mainboard/asus/m4a785t-m/devicetree.cb | 106 ++ src/mainboard/asus/m4a785t-m/dsdt.asl | 1850 +++++++++++++++++++++++++ src/mainboard/asus/m4a785t-m/get_bus_conf.c | 21 + src/mainboard/asus/m4a785t-m/irq_tables.c | 21 + src/mainboard/asus/m4a785t-m/mainboard.c | 21 + src/mainboard/asus/m4a785t-m/mptable.c | 21 + src/mainboard/asus/m4a785t-m/romstage.c | 21 + 18 files changed, 3225 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..630e1ec 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -35,6 +35,8 @@ config BOARD_ASUS_M2V_MX_SE bool "M2V-MX SE" config BOARD_ASUS_M4A785M bool "M4A785-M" +config BOARD_ASUS_M4A785TM + bool "M4A785T-M" config BOARD_ASUS_M4A78_EM bool "M4A78-EM" config BOARD_ASUS_M5A88_V @@ -65,6 +67,7 @@ source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" source "src/mainboard/asus/m4a785-m/Kconfig" +source "src/mainboard/asus/m4a785t-m/Kconfig" source "src/mainboard/asus/m4a78-em/Kconfig" source "src/mainboard/asus/m5a88-v/Kconfig" source "src/mainboard/asus/mew-am/Kconfig" diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 8a96476..d152f71 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -242,6 +242,10 @@ static void m4a785m_enable(device_t dev) } struct chip_operations mainboard_ops = { +#ifdef CONFIG_BOARD_ASUS_M4A785TM + CHIP_NAME("ASUS M4A785T-M Mainboard") +#else CHIP_NAME("ASUS M4A785-M Mainboard") +#endif .enable_dev = m4a785m_enable, }; diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig new file mode 100644 index 0000000..e3893b2 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -0,0 +1,86 @@ +if BOARD_ASUS_M4A785TM + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_AM3 + select DIMM_DDR3 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_AMD_RS780 + select SOUTHBRIDGE_AMD_SB700 + select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT + select SUPERIO_ITE_IT8712F + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO + select ENABLE_APIC_EXT_ID + select GFXUMA + select QRANK_DIMM_SUPPORT + +config MAINBOARD_DIR + string + default asus/m4a785t-m + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "M4A785T-M" + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config MEM_TRAIN_SEQ + int + default 2 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config IRQ_SLOT_COUNT + int + default 19 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_010000c4.h" + +config RAMTOP + hex + default 0x2000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config RAMBASE + hex + default 0x200000 + +endif diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl new file mode 100644 index 0000000..6a1b002 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/m4a785t-m/acpi/ide.asl b/src/mainboard/asus/m4a785t-m/acpi/ide.asl new file mode 100644 index 0000000..6ea2b09 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/routing.asl b/src/mainboard/asus/m4a785t-m/acpi/routing.asl new file mode 100644 index 0000000..ad51815 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/routing.asl @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 1, INTA, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + Package(){0x0012FFFF, 0, INTA, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + Package(){0x0013FFFF, 0, INTA, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTA, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Package(){0x0001FFFF, 0, 0, 18 }, */ + /* package(){0x0001FFFF, 1, 0, 19 }, */ + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 22 }, + + /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + Package(){0x0012FFFF, 0, 0, 16 }, + Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 19 }, + Package(){0x0014FFFF, 0, 0, 16 }, + /* Package(){0x00130004, 2, 0, 18 }, */ + /* Package(){0x00130005, 3, 0, 19 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/sata.asl b/src/mainboard/asus/m4a785t-m/acpi/sata.asl new file mode 100644 index 0000000..b5e6fc5 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/usb.asl b/src/mainboard/asus/m4a785t-m/acpi/usb.asl new file mode 100644 index 0000000..203e0ad --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/usb.asl @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/asus/m4a785t-m/acpi_tables.c b/src/mainboard/asus/m4a785t-m/acpi_tables.c new file mode 100644 index 0000000..a7ffc02 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/acpi_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/chip.h b/src/mainboard/asus/m4a785t-m/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m4a785t-m/cmos.layout b/src/mainboard/asus/m4a785t-m/cmos.layout new file mode 100644 index 0000000..53fdef5 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb new file mode 100644 index 0000000..e8764b1 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -0,0 +1,106 @@ +chip northbridge/amd/amdfam10/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR2 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1043 0x83a2 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 off end # + device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "2" + + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8712f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + end + device pnp 2e.9 off # GAME + end + device pnp 2e.a off end # CIR + end #superio + end #LPC + device pci 14.4 on end # PCI to PCI Bridge [1002:4384] + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # chip northbridge + end #pci_domain +end # northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl new file mode 100644 index 0000000..34ddd3a --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -0,0 +1,1850 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "M4A785-M ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x808, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU2, /* name space name */ + 2, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU3, /* name space name */ + 3, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PINA, 0x00000008, /* Index 0 */ + PINB, 0x00000008, /* Index 1 */ + PINC, 0x00000008, /* Index 2 */ + PIND, 0x00000008, /* Index 3 */ + AINT, 0x00000008, /* Index 4 */ + SINT, 0x00000008, /* Index 5 */ + , 0x00000008, /* Index 6 */ + AAUD, 0x00000008, /* Index 7 */ + AMOD, 0x00000008, /* Index 8 */ + PINE, 0x00000008, /* Index 9 */ + PINF, 0x00000008, /* Index A */ + PING, 0x00000008, /* Index B */ + PINH, 0x00000008, /* Index C */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PINA) + Store(0, PINB) + Store(0, PINC) + Store(0, PIND) + Store(0, PINE) + Store(0, PINF) + Store(0, PING) + Store(0, PINH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PINA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PINA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PINB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PINB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PINC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PINC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIND) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIND) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIND, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIND) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PINE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PINE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PINF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PINF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PING) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PING) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PING, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PING) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PINH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PINH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + \_SB.PCI0.SIOS (Arg0) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + \_SB.PCI0.SIOW (Arg0) + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + Notify (\_TZ.TZ00, 0x80) + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00130001) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130003) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00130004) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00130005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + /* ITE8718 Support */ + OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ + Field (IOID, ByteAcc, NoLock, Preserve) + { + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + } + + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + LDN, 8, /* Logical Device Number */ + Offset (0x20), + CID1, 8, /* Chip ID Byte 1, 0x87 */ + CID2, 8, /* Chip ID Byte 2, 0x12 */ + Offset (0x30), + ACTR, 8, /* Function activate */ + Offset (0xF0), + APC0, 8, /* APC/PME Event Enable Register */ + APC1, 8, /* APC/PME Status Register */ + APC2, 8, /* APC/PME Control Register 1 */ + APC3, 8, /* Environment Controller Special Configuration Register */ + APC4, 8 /* APC/PME Control Register 2 */ + } + + /* Enter the 8718 MB PnP Mode */ + Method (EPNP) + { + Store(0x87, SIOI) + Store(0x01, SIOI) + Store(0x55, SIOI) + Store(0x55, SIOI) /* 8718 magic number */ + } + /* Exit the 8718 MB PnP Mode */ + Method (XPNP) + { + Store (0x02, SIOI) + Store (0x02, SIOD) + } + /* + * Keyboard PME is routed to SB700 Gevent3. We can wake + * up the system by pressing the key. + */ + Method (SIOS, 1) + { + /* We only enable KBD PME for S5. */ + If (LLess (Arg0, 0x05)) + { + EPNP() + /* DBGO("8718F\n") */ + + Store (0x4, LDN) + Store (One, ACTR) /* Enable EC */ + /* + Store (0x4, LDN) + Store (0x04, APC4) + */ /* falling edge. which mode? Not sure. */ + + Store (0x4, LDN) + Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ + Store (0x4, LDN) + Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + + XPNP() + } + } + Method (SIOW, 1) + { + EPNP() + Store (0x4, LDN) + Store (Zero, APC0) /* disable keyboard PME */ + Store (0x4, LDN) + Store (0xFF, APC1) /* clear keyboard PME status */ + XPNP() + } + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PEBM + ) + + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ + + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +} +/* End of ASL file */ diff --git a/src/mainboard/asus/m4a785t-m/get_bus_conf.c b/src/mainboard/asus/m4a785t-m/get_bus_conf.c new file mode 100644 index 0000000..577b51c --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/get_bus_conf.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/get_bus_conf.c" diff --git a/src/mainboard/asus/m4a785t-m/irq_tables.c b/src/mainboard/asus/m4a785t-m/irq_tables.c new file mode 100644 index 0000000..b4c030f --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/irq_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/irq_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/mainboard.c b/src/mainboard/asus/m4a785t-m/mainboard.c new file mode 100644 index 0000000..76a2a68 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/mainboard.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/mainboard.c" diff --git a/src/mainboard/asus/m4a785t-m/mptable.c b/src/mainboard/asus/m4a785t-m/mptable.c new file mode 100644 index 0000000..c6e4b88 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/mptable.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/mptable.c" diff --git a/src/mainboard/asus/m4a785t-m/romstage.c b/src/mainboard/asus/m4a785t-m/romstage.c new file mode 100644 index 0000000..43cd523 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/romstage.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/romstage.c" From gerrit at coreboot.org Mon Nov 28 05:34:16 2011 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Mon, 28 Nov 2011 05:34:16 +0100 Subject: [coreboot] Patch set updated for coreboot: 5c8526e RS780: print the vgainfo References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/456 -gerrit commit 5c8526e3d32afb22644a92aa5abeb1b3a54eab1b Author: Denis 'GNUtoo' Carikli Date: Sun Nov 27 13:43:16 2011 +0100 RS780: print the vgainfo With this commit the vgainfo is printed and looks like that on the serial console: vgainfo: ulBootUpEngineClock:50000 ulBootUpUMAClock:66700 ulBootUpSidePortClock:0 ulMinSidePortClock:0 ulSystemConfig:0 ulBootUpReqDisplayVector:0 ulOtherDisplayMisc:0 ulDDISlot1Config:0 ulDDISlot2Config:0 ucMemoryType:0 ucUMAChannelNumber:1 ucDockingPinBit:0 ucDockingPinPolarity:0 ulDockingPinCFGInfo:0 ulCPUCapInfo: 2 usNumberOfCyclesInPeriod:0 usMaxNBVoltage:0 usMinNBVoltage:0 usBootUpNBVoltage:0 ulHTLinkFreq:20000 usMinHTLinkWidth:8 usMaxHTLinkWidth:8 usUMASyncStartDelay:100 usUMADataReturnTime:300 usLinkStatusZeroTime:600 ulHighVoltageHTLinkFreq:20000 ulLowVoltageHTLinkFreq:20000 usMaxUpStreamHTLinkWidth:8 usMaxDownStreamHTLinkWidth:8 usMinUpStreamHTLinkWidth:8 usMinDownStreamHTLinkWidth:8 Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524 Signed-off-by: Denis 'GNUtoo' Carikli --- src/southbridge/amd/rs780/gfx.c | 80 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 80 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 65a5e2b..29a6394 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -575,6 +575,86 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Poweron DDI Lanes */ poweron_ddi_lanes(nb_dev); + printk(BIOS_DEBUG,"vgainfo:\n" + " ulBootUpEngineClock:%lu \n" + " ulBootUpUMAClock:%lu \n" + " ulBootUpSidePortClock:%lu \n" + " ulMinSidePortClock:%lu \n" + " ulSystemConfig:%lu \n" + " ulBootUpReqDisplayVector:%lu \n" + " ulOtherDisplayMisc:%lu \n" + " ulDDISlot1Config:%lu \n" + " ulDDISlot2Config:%lu \n" + + " ucMemoryType:%u \n" + " ucUMAChannelNumber:%u \n" + " ucDockingPinBit:%u \n" + " ucDockingPinPolarity:%u \n" + + " ulDockingPinCFGInfo:%lu \n" + " ulCPUCapInfo: %lu \n" + + " usNumberOfCyclesInPeriod:%hu \n" + " usMaxNBVoltage:%hu \n" + " usMinNBVoltage:%hu \n" + " usBootUpNBVoltage:%hu \n" + + " ulHTLinkFreq:%lu \n" + + " usMinHTLinkWidth:%hu \n" + " usMaxHTLinkWidth:%hu \n" + " usUMASyncStartDelay:%hu \n" + " usUMADataReturnTime:%hu \n" + " usLinkStatusZeroTime:%hu \n" + + " ulHighVoltageHTLinkFreq:%lu \n" + " ulLowVoltageHTLinkFreq:%lu \n" + + " usMaxUpStreamHTLinkWidth:%hu \n" + " usMaxDownStreamHTLinkWidth:%hu \n" + " usMinUpStreamHTLinkWidth:%hu \n" + " usMinDownStreamHTLinkWidth:%hu \n", + + (unsigned long)vgainfo.ulBootUpEngineClock, + (unsigned long)vgainfo.ulBootUpUMAClock, + (unsigned long)vgainfo.ulBootUpSidePortClock, + (unsigned long)vgainfo.ulMinSidePortClock, + (unsigned long)vgainfo.ulSystemConfig, + (unsigned long)vgainfo.ulBootUpReqDisplayVector, + (unsigned long)vgainfo.ulOtherDisplayMisc, + (unsigned long)vgainfo.ulDDISlot1Config, + (unsigned long)vgainfo.ulDDISlot2Config, + + vgainfo.ucMemoryType, + vgainfo.ucUMAChannelNumber, + vgainfo.ucDockingPinBit, + vgainfo.ucDockingPinPolarity, + + (unsigned long)vgainfo.ulDockingPinCFGInfo, + (unsigned long)vgainfo.ulCPUCapInfo, + + vgainfo.usNumberOfCyclesInPeriod, + vgainfo.usMaxNBVoltage, + vgainfo.usMinNBVoltage, + vgainfo.usBootUpNBVoltage, + + (unsigned long)vgainfo.ulHTLinkFreq, + + vgainfo.usMinHTLinkWidth, + vgainfo.usMaxHTLinkWidth, + vgainfo.usUMASyncStartDelay, + vgainfo.usUMADataReturnTime, + vgainfo.usLinkStatusZeroTime, + + (unsigned long)vgainfo.ulHighVoltageHTLinkFreq, + (unsigned long)vgainfo.ulLowVoltageHTLinkFreq, + + vgainfo.usMaxUpStreamHTLinkWidth, + vgainfo.usMaxDownStreamHTLinkWidth, + vgainfo.usMinUpStreamHTLinkWidth, + vgainfo.usMinDownStreamHTLinkWidth); + + /* Transfer the Table to VBIOS. */ pointer = (u32 *)&vgainfo; for(i=0; i Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/458 -gerrit commit 4211f0c5542743e251dbd022b023d0d34d8877c2 Author: Denis 'GNUtoo' Carikli Date: Sun Nov 27 22:04:02 2011 +0100 M4A785T-M: fix ACPI's P-States Table Without that fix the linux kernel cannot change the frequency of the CPUs with cpufreq. Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/m4a785t-m/acpi/cpstate.asl | 36 +++++++++++++++++++----- 1 files changed, 28 insertions(+), 8 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl index 6a1b002..0ee537d 100644 --- a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl +++ b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl @@ -46,22 +46,42 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) Name(_PSS, Package(){ Package () { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, + 0x00000BB8, + 0x000078D9, + 0x00000004, + 0x00000004, 0x00000000, 0x00000000 }, Package () { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, + 0x000008FC, + 0x0000659A, + 0x00000004, + 0x00000004, 0x00000001, 0x00000001 + }, + + Package () + { + 0x00000708, + 0x000056BF, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package () + { + 0x00000320, + 0x00001FA1, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 } }) From gerrit at coreboot.org Mon Nov 28 05:57:23 2011 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Mon, 28 Nov 2011 05:57:23 +0100 Subject: [coreboot] Patch set updated for coreboot: 47e054a Add ASUS M4A785T-M mainboard support References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/457 -gerrit commit 47e054a1c4090e4a5a404de427634b260e4c4d13 Author: Denis 'GNUtoo' Carikli Date: Sun Nov 27 15:58:38 2011 +0100 Add ASUS M4A785T-M mainboard support This mainboard is very similar to the M4A785-M, but it has DDR3 instead of DDR2. That's why most of the code was copied or included from the m4a785-m directory Notable changes between the two mainboards include: * the selection of the last microcode (mc_patch_010000b6.h) which made it pass the CPU init. * the selection of DDR3 which made it pass the ram init This change was tested with the Trisquel 5.0 GNU/Linux distribution which uses the linux-libre version 2.6.38-12-generic The mainboard boots fine, however some special care is required for the onboard sound CODEC, and the onboard video chip: * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue is the same than the ASUS M4A785-M mainboard: It causes a flood of interupts which prevents booting * The internal video chip currently requires pci=nocrs, else the graphics are frozen as soon as the radeon module loads, and dmesg would print the following(the card only has 256M, and the mainboard was equiped with 2G of RAM): [ 3.674762] [drm] radeon: 3584M of VRAM memory ready [ 3.679863] [drm] radeon: 512M of GTT memory ready. instead of : [ 45.876088] [drm] radeon: 256M of VRAM memory ready [ 45.876089] [drm] radeon: 512M of GTT memory ready. * The screen(both VGA and HDMI) flickers at high resolution * Sometimes the computer freeze while changing the resolution (even the serial console stops responding) The following peripherals were tested: * The ath9k PCI wireless card was tested * The SATA hard disk works fine * the USB keyboard and mouse work fine * htop see 2 cores * serial port works under coreboot and GNU/Linux * power off and reboot works CPU frequency cannot be changed yet, this is addressed in a new commit. More detail are available here: http://www.coreboot.org/ASUS_M4A785T-M dmesg is available here: http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html The mailing list thread on the graphic problem is here: http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/m4a785-m/mainboard.c | 4 + src/mainboard/asus/m4a785t-m/Kconfig | 86 ++ src/mainboard/asus/m4a785t-m/acpi/cpstate.asl | 75 + src/mainboard/asus/m4a785t-m/acpi/ide.asl | 244 ++++ src/mainboard/asus/m4a785t-m/acpi/routing.asl | 300 ++++ src/mainboard/asus/m4a785t-m/acpi/sata.asl | 149 ++ src/mainboard/asus/m4a785t-m/acpi/usb.asl | 161 +++ src/mainboard/asus/m4a785t-m/acpi_tables.c | 21 + src/mainboard/asus/m4a785t-m/chip.h | 23 + src/mainboard/asus/m4a785t-m/cmos.layout | 98 ++ src/mainboard/asus/m4a785t-m/devicetree.cb | 106 ++ src/mainboard/asus/m4a785t-m/dsdt.asl | 1850 +++++++++++++++++++++++++ src/mainboard/asus/m4a785t-m/get_bus_conf.c | 21 + src/mainboard/asus/m4a785t-m/irq_tables.c | 21 + src/mainboard/asus/m4a785t-m/mainboard.c | 21 + src/mainboard/asus/m4a785t-m/mptable.c | 21 + src/mainboard/asus/m4a785t-m/romstage.c | 21 + 18 files changed, 3225 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..630e1ec 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -35,6 +35,8 @@ config BOARD_ASUS_M2V_MX_SE bool "M2V-MX SE" config BOARD_ASUS_M4A785M bool "M4A785-M" +config BOARD_ASUS_M4A785TM + bool "M4A785T-M" config BOARD_ASUS_M4A78_EM bool "M4A78-EM" config BOARD_ASUS_M5A88_V @@ -65,6 +67,7 @@ source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" source "src/mainboard/asus/m4a785-m/Kconfig" +source "src/mainboard/asus/m4a785t-m/Kconfig" source "src/mainboard/asus/m4a78-em/Kconfig" source "src/mainboard/asus/m5a88-v/Kconfig" source "src/mainboard/asus/mew-am/Kconfig" diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 8a96476..d152f71 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -242,6 +242,10 @@ static void m4a785m_enable(device_t dev) } struct chip_operations mainboard_ops = { +#ifdef CONFIG_BOARD_ASUS_M4A785TM + CHIP_NAME("ASUS M4A785T-M Mainboard") +#else CHIP_NAME("ASUS M4A785-M Mainboard") +#endif .enable_dev = m4a785m_enable, }; diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig new file mode 100644 index 0000000..e3893b2 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -0,0 +1,86 @@ +if BOARD_ASUS_M4A785TM + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_AM3 + select DIMM_DDR3 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_AMD_RS780 + select SOUTHBRIDGE_AMD_SB700 + select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT + select SUPERIO_ITE_IT8712F + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO + select ENABLE_APIC_EXT_ID + select GFXUMA + select QRANK_DIMM_SUPPORT + +config MAINBOARD_DIR + string + default asus/m4a785t-m + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "M4A785T-M" + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config MEM_TRAIN_SEQ + int + default 2 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config IRQ_SLOT_COUNT + int + default 19 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_010000c4.h" + +config RAMTOP + hex + default 0x2000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config RAMBASE + hex + default 0x200000 + +endif diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl new file mode 100644 index 0000000..6a1b002 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/m4a785t-m/acpi/ide.asl b/src/mainboard/asus/m4a785t-m/acpi/ide.asl new file mode 100644 index 0000000..6ea2b09 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/routing.asl b/src/mainboard/asus/m4a785t-m/acpi/routing.asl new file mode 100644 index 0000000..ad51815 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/routing.asl @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 1, INTA, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + Package(){0x0012FFFF, 0, INTA, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + Package(){0x0013FFFF, 0, INTA, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTA, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Package(){0x0001FFFF, 0, 0, 18 }, */ + /* package(){0x0001FFFF, 1, 0, 19 }, */ + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 22 }, + + /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + Package(){0x0012FFFF, 0, 0, 16 }, + Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 19 }, + Package(){0x0014FFFF, 0, 0, 16 }, + /* Package(){0x00130004, 2, 0, 18 }, */ + /* Package(){0x00130005, 3, 0, 19 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/sata.asl b/src/mainboard/asus/m4a785t-m/acpi/sata.asl new file mode 100644 index 0000000..b5e6fc5 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/usb.asl b/src/mainboard/asus/m4a785t-m/acpi/usb.asl new file mode 100644 index 0000000..203e0ad --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/usb.asl @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/asus/m4a785t-m/acpi_tables.c b/src/mainboard/asus/m4a785t-m/acpi_tables.c new file mode 100644 index 0000000..a7ffc02 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/acpi_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/chip.h b/src/mainboard/asus/m4a785t-m/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m4a785t-m/cmos.layout b/src/mainboard/asus/m4a785t-m/cmos.layout new file mode 100644 index 0000000..53fdef5 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb new file mode 100644 index 0000000..e8764b1 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -0,0 +1,106 @@ +chip northbridge/amd/amdfam10/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR2 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1043 0x83a2 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 off end # + device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "2" + + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8712f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + end + device pnp 2e.9 off # GAME + end + device pnp 2e.a off end # CIR + end #superio + end #LPC + device pci 14.4 on end # PCI to PCI Bridge [1002:4384] + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # chip northbridge + end #pci_domain +end # northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl new file mode 100644 index 0000000..34ddd3a --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -0,0 +1,1850 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "M4A785-M ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x808, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU2, /* name space name */ + 2, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU3, /* name space name */ + 3, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PINA, 0x00000008, /* Index 0 */ + PINB, 0x00000008, /* Index 1 */ + PINC, 0x00000008, /* Index 2 */ + PIND, 0x00000008, /* Index 3 */ + AINT, 0x00000008, /* Index 4 */ + SINT, 0x00000008, /* Index 5 */ + , 0x00000008, /* Index 6 */ + AAUD, 0x00000008, /* Index 7 */ + AMOD, 0x00000008, /* Index 8 */ + PINE, 0x00000008, /* Index 9 */ + PINF, 0x00000008, /* Index A */ + PING, 0x00000008, /* Index B */ + PINH, 0x00000008, /* Index C */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PINA) + Store(0, PINB) + Store(0, PINC) + Store(0, PIND) + Store(0, PINE) + Store(0, PINF) + Store(0, PING) + Store(0, PINH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PINA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PINA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PINB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PINB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PINC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PINC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIND) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIND) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIND, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIND) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PINE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PINE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PINF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PINF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PING) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PING) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PING, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PING) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PINH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PINH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + \_SB.PCI0.SIOS (Arg0) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + \_SB.PCI0.SIOW (Arg0) + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + Notify (\_TZ.TZ00, 0x80) + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00130001) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130003) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00130004) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00130005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + /* ITE8718 Support */ + OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ + Field (IOID, ByteAcc, NoLock, Preserve) + { + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + } + + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + LDN, 8, /* Logical Device Number */ + Offset (0x20), + CID1, 8, /* Chip ID Byte 1, 0x87 */ + CID2, 8, /* Chip ID Byte 2, 0x12 */ + Offset (0x30), + ACTR, 8, /* Function activate */ + Offset (0xF0), + APC0, 8, /* APC/PME Event Enable Register */ + APC1, 8, /* APC/PME Status Register */ + APC2, 8, /* APC/PME Control Register 1 */ + APC3, 8, /* Environment Controller Special Configuration Register */ + APC4, 8 /* APC/PME Control Register 2 */ + } + + /* Enter the 8718 MB PnP Mode */ + Method (EPNP) + { + Store(0x87, SIOI) + Store(0x01, SIOI) + Store(0x55, SIOI) + Store(0x55, SIOI) /* 8718 magic number */ + } + /* Exit the 8718 MB PnP Mode */ + Method (XPNP) + { + Store (0x02, SIOI) + Store (0x02, SIOD) + } + /* + * Keyboard PME is routed to SB700 Gevent3. We can wake + * up the system by pressing the key. + */ + Method (SIOS, 1) + { + /* We only enable KBD PME for S5. */ + If (LLess (Arg0, 0x05)) + { + EPNP() + /* DBGO("8718F\n") */ + + Store (0x4, LDN) + Store (One, ACTR) /* Enable EC */ + /* + Store (0x4, LDN) + Store (0x04, APC4) + */ /* falling edge. which mode? Not sure. */ + + Store (0x4, LDN) + Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ + Store (0x4, LDN) + Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + + XPNP() + } + } + Method (SIOW, 1) + { + EPNP() + Store (0x4, LDN) + Store (Zero, APC0) /* disable keyboard PME */ + Store (0x4, LDN) + Store (0xFF, APC1) /* clear keyboard PME status */ + XPNP() + } + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PEBM + ) + + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ + + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +} +/* End of ASL file */ diff --git a/src/mainboard/asus/m4a785t-m/get_bus_conf.c b/src/mainboard/asus/m4a785t-m/get_bus_conf.c new file mode 100644 index 0000000..577b51c --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/get_bus_conf.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/get_bus_conf.c" diff --git a/src/mainboard/asus/m4a785t-m/irq_tables.c b/src/mainboard/asus/m4a785t-m/irq_tables.c new file mode 100644 index 0000000..b4c030f --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/irq_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/irq_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/mainboard.c b/src/mainboard/asus/m4a785t-m/mainboard.c new file mode 100644 index 0000000..76a2a68 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/mainboard.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/mainboard.c" diff --git a/src/mainboard/asus/m4a785t-m/mptable.c b/src/mainboard/asus/m4a785t-m/mptable.c new file mode 100644 index 0000000..c6e4b88 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/mptable.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/mptable.c" diff --git a/src/mainboard/asus/m4a785t-m/romstage.c b/src/mainboard/asus/m4a785t-m/romstage.c new file mode 100644 index 0000000..43cd523 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/romstage.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/romstage.c" From svn at coreboot.org Mon Nov 28 16:00:02 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 28 Nov 2011 16:00:02 +0100 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Mon Nov 28 21:24:55 2011 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Mon, 28 Nov 2011 21:24:55 +0100 Subject: [coreboot] New patch to review for coreboot: aadf4c5 X60/T60: reset baudrate loglevel to sane values References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/459 -gerrit commit aadf4c5effd7f31579d6105d82a7006d08eeab3e Author: Sven Schnelle Date: Mon Nov 28 21:12:11 2011 +0100 X60/T60: reset baudrate loglevel to sane values Change-Id: Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/mainboard.c | 4 ++++ src/mainboard/lenovo/x60/mainboard.c | 4 ++++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 19ac221..a1de756 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -90,6 +90,10 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Restoring CMOS defaults\n"); set_option("tft_brightness", &(u8[]){ 0xff }); set_option("volume", &(u8[]){ 0x03 }); + /* set baudrate to 115200 baud */ + set_option("baud_rate", &(u8[]){ 0x05 }); + /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */ + set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 }); set_option("cmos_defaults_loaded", &(u8[]){ 0x01 }); } } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 5bc1dca..ee6ac14 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -88,6 +88,10 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Restoring CMOS defaults\n"); set_option("tft_brightness", &(u8[]){ 0xff }); set_option("volume", &(u8[]){ 0x03 }); + /* set baudrate to 115200 baud */ + set_option("baud_rate", &(u8[]){ 0x05 }); + /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */ + set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 }); set_option("cmos_defaults_loaded", &(u8[]){ 0x01 }); } } From wmkamp at datakamp.de Tue Nov 29 11:36:45 2011 From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp) Date: Tue, 29 Nov 2011 11:36:45 +0100 Subject: [coreboot] Persimmon LAN problem with coreboot Message-ID: <4738C8CE0A30FF47AACA9C624746E3E208C2C81636@DATAKAMPONE.datakamp2008.local> Hi Marc, I encountered a problem with the onboard LAN of the Persimmon mainboard in UBUNTU. The cable connection will not be recognized. The problem exists with the actual coreboot version from GIT. If I try the coreboot which comes with sage electronic EDK 1.06 this problem does not exist. What is the difference between this versions? What could be the problem? Thanks Wolfgang -------------- next part -------------- An HTML attachment was scrubbed... URL: From marcj303 at gmail.com Tue Nov 29 18:23:31 2011 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 29 Nov 2011 10:23:31 -0700 Subject: [coreboot] Persimmon LAN problem with coreboot In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E208C2C81636@DATAKAMPONE.datakamp2008.local> References: <4738C8CE0A30FF47AACA9C624746E3E208C2C81636@DATAKAMPONE.datakamp2008.local> Message-ID: Hi Wolfgang, On Tue, Nov 29, 2011 at 3:36 AM, Wolfgang Kamp - datakamp wrote: > > > Hi Marc, > > > > I encountered a problem with the onboard LAN of the Persimmon mainboard in > UBUNTU. > > The cable connection will not be recognized. The problem exists with the > actual coreboot version from GIT. > > If I try the coreboot which comes with sage electronic EDK 1.06 this problem > does not exist. > > What is the difference between this versions? What could be the problem? > > The coreboot in the Sage EDK is several months behind coreboot.org. There shouldn't be any major differences in the coreboot code, just some additions for working in the EDK environment. You can check the history log to see the changes. I don't know what the problem is. You could do a git bisect to figure out which change is causing the problem. I think that AMD made a big change to the fam14 support that isn't in the EDK. That would be where we should start looking. Marc -- http://se-eng.com From wmkamp at datakamp.de Tue Nov 29 20:26:28 2011 From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp) Date: Tue, 29 Nov 2011 20:26:28 +0100 Subject: [coreboot] Persimmon LAN problem with coreboot Message-ID: <4738C8CE0A30FF47AACA9C624746E3E208C2C8163F@DATAKAMPONE.datakamp2008.local> Hi Marc, it looks that the PCI enumeration of the LAN chip works fine, but then the register access fails. So lspci -vvnn lists the Realtec LAN [10ec/8168] correct, but network test fails to access the register. It's not possible to read out the MAC address. 0xFF on all places will be returned. I have attached the coreboot log file. On line 375 PCI: 01:00.0 [10ec/8168] enabled shows the bus. On line 994 down I can see assertion fails on AmdInitLate process. What does this mean? Can you help? Thanks Wolfgang -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Wed Nov 30 01:50:02 2011 From: peter at stuge.se (Peter Stuge) Date: Wed, 30 Nov 2011 01:50:02 +0100 Subject: [coreboot] Persimmon LAN problem with coreboot In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E208C2C8163F@DATAKAMPONE.datakamp2008.local> References: <4738C8CE0A30FF47AACA9C624746E3E208C2C8163F@DATAKAMPONE.datakamp2008.local> Message-ID: <20111130005002.5525.qmail@stuge.se> Wolfgang Kamp - datakamp wrote: > I have attached the coreboot log file. Attached zip file was 0 bytes. It is possible that the mailing list is stripping non-text attachments. Please either save the boot log as a .txt file and attach that uncompressed (text/plain mimetype) or put it somewhere on the web and include a link to the logfile in your email. A plain text attachment is prefered, since it is much simpler to consume. Thanks! //Peter From wmkamp at datakamp.de Wed Nov 30 09:46:18 2011 From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp) Date: Wed, 30 Nov 2011 09:46:18 +0100 Subject: [coreboot] Persimmon LAN problem with coreboot Message-ID: <4738C8CE0A30FF47AACA9C624746E3E208C2C81649@DATAKAMPONE.datakamp2008.local> Hi Marc, it looks that the PCI enumeration of the LAN chip works fine, but then the register access fails. So lspci -vvnn lists the Realtec LAN [10ec/8168] correct, but network test fails to access the register. It's not possible to read out the MAC address. 0xFF on all places will be returned. I have attached the coreboot log file. On line 375 PCI: 01:00.0 [10ec/8168] enabled shows the bus. On line 994 down I can see assertion fails on AmdInitLate process. What does this mean? Can you help? Thanks Wolfgang -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: FT1LOG10.TXT URL: From hagigatali at gmail.com Wed Nov 30 09:55:56 2011 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 30 Nov 2011 12:25:56 +0330 Subject: [coreboot] Intel GMCH 82815 Message-ID: I am working with Pentium III, Intel GMCH, 82815 and Intel ICH2, 82801. I managed to initialize DRAM controller to recognize the first 640 K of the memory correctly in the real mode. When i switch to the protected mode, CPU writes to the first 64K only. Every other read/write from the higher addresses leads to CPU restart. Can anybody say what is going on? From peter at stuge.se Wed Nov 30 10:27:04 2011 From: peter at stuge.se (Peter Stuge) Date: Wed, 30 Nov 2011 10:27:04 +0100 Subject: [coreboot] Intel GMCH 82815 In-Reply-To: References: Message-ID: <20111130092704.13719.qmail@stuge.se> ali hagigat wrote: > I am working with Pentium III, Intel GMCH, 82815 and Intel ICH2, 82801. > > I managed to initialize DRAM controller to recognize the first 640 K > of the memory correctly in the real mode. > > When i switch to the protected mode, CPU writes to the first 64K only. > Every other read/write from the higher addresses leads to CPU restart. > > Can anybody say what is going on? Not unless you show your code. One explanation would be that you haven't done a proper switch into protected mode (setting up a descriptor table and initializing selectors) which would make the CPU triple fault and reset on accesses outside whatever the descriptors happen to be. If this is the case, I think that Intel's IA-32 architecture manuals have good info on what you need to do, and of course you can study both coreboot sources as well as some good old DOS extenders such as Tran's PMODE32, DOS4GW from Watcom or my personal favorite DOS32. //Peter From hagigatali at gmail.com Wed Nov 30 11:26:51 2011 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 30 Nov 2011 13:56:51 +0330 Subject: [coreboot] Intel GMCH 82815 In-Reply-To: <20111130092704.13719.qmail@stuge.se> References: <20111130092704.13719.qmail@stuge.se> Message-ID: Dear Peter, Thank you so much for the reply. I have copied the content of the three files I use for the RAM initialization, ram.S, ram.ld and Makefile. my GCC is: gcc (GCC) 4.6.1 20110908 (Red Hat 4.6.1-9) binutils: Version : 2.21.53.0.2 Vendor: Fedora Project Release : 1.fc17 Build Date: Mon 08 Aug 2011 20:53:40 IRDT It is compiled for Pentium III, 815/ICH2. Regards ram.S ****************************************************** .code16 .section .realmode start: cli mov $0, %ax mov %ax, %ds #-********************************* #/* Configure the RAM command. */ mov $0x0cf8, %dx mov $0x80000050, %eax out %eax, %dx movw $0x0CFC, %dx in %dx, %eax and $0x1fffffff, %eax or $0x05000000, %eax movw $0x0CFC, %dx out %eax, %dx #;-------------------------------------------------- #general initialization #50-53************************** mov $0x0cf8, %dx mov $0x80000050, %eax out %eax, %dx mov $0x0cfc, %dx in %dx, %eax #Res mask and $0x0000F823, %eax #Bios => cas 2clk or $0x2fcc0140, %eax mov $0x0cfc, %dx out %eax, %dx #70,72-73************************** mov $0x0cf8, %dx mov $0x80000070, %eax out %eax, %dx mov $0x0cfc, %dx movb $0xc0, %al out %al, %dx mov $0x0cfe, %dx inw %dx, %ax #Res mask and $0x7704, %ax #Bios or $0x0012, %ax mov $0x0cfe, %dx out %ax, %dx #92-93**************************** mov $0x0cf8, %dx mov $0x80000090, %eax out %eax, %dx mov $0x0cfe, %dx movw $0xff5c, %ax out %ax, %dx #94-95***************************** mov $0x0cf8, %dx mov $0x80000094, %eax out %eax, %dx mov $0x0cfe, %dx inw %dx, %ax #Res mask and $0xffc0, %ax #Bios or $0x001c, %ax mov $0x0cfe, %dx out %ax, %dx #98-9B***************************** mov $0x0cf8, %dx mov $0x80000098, %eax out %eax, %dx movw $0x0cfc, %dx in %dx, %eax #Res mask and $0x7F887F88, %eax #Bios or $0x80238023, %eax movw $0x0cfc, %dx out %eax, %dx #9c-9f*************************** mov $0x0cf8, %dx mov $0x8000009c, %eax out %eax, %dx movw $0x0CFC, %dx in %dx, %eax #Res mask and $0xFFFF7FFF, %eax #Bios or $0x00008000, %eax movw $0x0CFC, %dx out %eax, %dx #2c-2f*************************** mov $0x0cf8, %dx mov $0x8000002c, %eax out %eax, %dx mov $0x0cfc, %dx mov $0x80271043, %eax out %eax, %dx #;-------------------------------------------------- #NOP /* 1. Apply NOP. */ #display 1 mov $1, %al out %al, $0x80 #%%%%%%%%%%%%%%%%%%%% mov $0x0cf8, %dx mov $0x80000050, %eax out %eax, %dx mov $0x0cfc, %dx in %dx, %eax #Res mask and $0x0000F823, %eax #Bios => cas 2clk or $0x8fcc0140, %eax mov $0x0cfc, %dx out %eax, %dx #%%%%%%%%%%%%%%%%%%%%%% mov $0x00000000, %ebx mov (%ebx), %eax /* mov $0x08000000, %ebx mov (%ebx), %eax mov $0x10000000, %ebx mov (%ebx), %eax mov $0x18000000, %ebx mov (%ebx), %eax */ #%%%%%%%%%%%%%%%%%%%%% mov $1, %di delay11r: mov $200000, %ecx delay1r: dec %ecx jnz delay1r dec %di jnz delay11r #;-------------------------------------------------- #precharge /* 2. Precharge all. Wait tRP. */ #display 2 mov $2, %al out %al, $0x80 #%%%%%%%%%%%%%%%%%%%%%% mov $0x0cf8, %dx mov $0x80000050, %eax out %eax, %dx mov $0x0cfc, %dx in %dx, %eax #Res mask and $0x0000F823, %eax #Bios => cas 2clk or $0xafcc0140, %eax mov $0x0cfc, %dx out %eax, %dx #%%%%%%%%%%%%%%%%%%%%%% mov $0x00000000, %ebx mov %ds:(%ebx), %eax /* mov $0x08000000, %ebx mov %ds:(%ebx), %eax mov $0x10000000, %ebx mov %ds:(%ebx), %eax mov $0x18000000, %ebx mov %ds:(%ebx), %eax */ #%%%%%%%%%%%%%%%%%%%%%%% mov $10, %di delay21r: mov $1000, %ecx delay2r: dec %ecx jnz delay2r dec %di jnz delay21r #;-------------------------------------------------- #CBR cycle /* 3. Perform 8 refresh cycles. Wait tRC each time. */ #display 3 mov $3, %al out %al, $0x80 #%%%%%%%%%%%%%%%%%%%%%% mov $8, %esi refreshcycler: mov $0x0cf8, %dx mov $0x80000050, %eax out %eax, %dx mov $0x0cfc, %dx in %dx, %eax #Res mask and $0x0000F823, %eax #Bios => cas 2clk or $0xefcc0140, %eax mov $0x0cfc, %dx out %eax, %dx #%%%%%%%%%%%%%%%%%%%%%%% mov $0x00000000, %ebx mov %ds:(%ebx), %eax /* mov $0x08000000, %ebx mov %ds:(%ebx), %eax mov $0x10000000, %ebx mov %ds:(%ebx), %eax mov $0x18000000, %ebx mov %ds:(%ebx), %eax */ #%%%%%%%%%%%%%%%%%%%%%%% mov $10, %di delay31r: mov $1000, %ecx delay3r: dec %ecx jnz delay3r dec %di jnz delay31r dec %esi jnz refreshcycler #;-------------------------------------------------- #mode register set /* 4. Mode register set. Wait two memory cycles. */ #display 4 mov $4, %al out %al, $0x80 #%%%%%%%%%%%%%%%%%%%%%%%%% mov $0x0cf8, %dx mov $0x80000050, %eax out %eax, %dx mov $0x0cfc, %dx in %dx, %eax #Res mask and $0x0000F823, %eax #Bios => cas 2clk or $0xafcc0140, %eax mov $0x0cfc, %dx out %eax, %dx #%%%%%%%%%%%%%%%%%%%%%%%% #1d0 => 150 mov $0x000001d0, %ebx mov %ds:(%ebx), %eax /* mov $0x08000150, %ebx mov %ds:(%ebx), %eax mov $0x10000650, %ebx mov %ds:(%ebx), %eax mov $0x18000650, %esi mov %ds:(%ebx), %eax */ #%%%%%%%%%%%%%%%%%%%%%%%%%%% mov $10, %di delay41r: mov $1000, %ecx delay4r: dec %ecx jnz delay4r dec %di jnz delay41r #;-------------------------------------------------- #normal operation /* 5. Normal operation (enables refresh at 15.6usec). */ #display 5 mov $5, %al out %al, $0x80 #%%%%%%%%%%%%%%%%%%%%%%%%%% mov $0x0cf8, %dx mov $0x80000050, %eax out %eax, %dx mov $0x0cfc, %dx in %dx, %eax #Res mask and $0x0000F823, %eax #Bios => cas 2clk or $0x2fcc0140, %eax mov $0x0cfc, %dx out %eax, %dx #%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% mov $0x00000000, %ebx mov %ds:(%ebx), %eax /* mov $0x08000000, %ebx mov %ds:(%ebx), %eax mov $0x10000000, %ebx mov %ds:(%ebx), %eax mov $0x18000000, %ebx mov %ds:(%ebx), %eax */ #%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% mov $10, %di delay51r: mov $1000, %ecx delay5r: dec %ecx jnz delay5r dec %di jnz delay51r #;-------------------------------------------------- mov $10, %al out %al, $0x80 #;-------------------------------------------------- mov $0xffff, %cx delayea1r: dec %cx jnz delayea1r #*********************..................************** #;enabling protected mode cli lgdtl %cs:32 mov $0x10, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs mov %ax, %gs mov %ax, %ss mov $0x34, %al out %al, $0x80 mov %cr0, %eax or $1, %eax mov %eax, %cr0 data32 ljmp $0x0008, $0xfffc0000 .section .gdtsection gdt: .byte 0, 0, 0, 0, 0, 0, 0, 0 .byte 0xff, 0xff, 0, 0, 0, 0x9a, 0xdf, 0 .byte 0xff, 0xff, 0, 0, 0, 0x92, 0xdf, 0 .byte 0xff, 0xff, 0, 0, 0, 0x92, 0xdf, 0 .byte 32, 0, 0, 0, 0xff, 0xff .code32 .section .protectedmode protectedmode: mov $0x42, %al out %al, $0x80 #*********************..................*********************** mov $0xffff, %cx delayea1: dec %cx jnz delayea1 #write mov $0x8ffff, %ebx mov $0x59, %al mov %al, (%ebx) #read mov $0x8ffff, %ebx mov (%ebx), %al outb %al, $0x80 #*********************..................************** end: jmp end .code16 .section .reset jmp start ram.ld ***************************************************** SECTIONS { /DISCARD/ : { *(.comment) *(.note.*) *(.note) } } SECTIONS { . = 0xfffc0000; .text : { compstart = .; *(.protectedmode); . = compstart + 0x30000; compstart = .; *(.gdtsection); . = compstart + 0x8200; compstart = .; *(.realmode); . = compstart + 0x7df0; compstart = .; *(.reset); . = compstart + 0x10; } } Makefile **************************************************** all: as -march=pentiumiii -mtune=pentiumiii -o ram.o ram.S ld ram.o -o ram -T ram.ld objcopy -O binary ram ram.img **************************************************** On Wed, Nov 30, 2011 at 12:57 PM, Peter Stuge wrote: > ali hagigat wrote: >> I am working with Pentium III, Intel GMCH, 82815 and Intel ICH2, 82801. >> >> I managed to initialize DRAM controller to recognize the first 640 K >> of the memory correctly in the real mode. >> >> When i switch to the protected mode, CPU writes to the first 64K only. >> Every other read/write from the higher addresses leads to CPU restart. >> >> Can anybody say what is going on? > > Not unless you show your code. > > One explanation would be that you haven't done a proper switch into > protected mode (setting up a descriptor table and initializing > selectors) which would make the CPU triple fault and reset on > accesses outside whatever the descriptors happen to be. If this is > the case, I think that Intel's IA-32 architecture manuals have good > info on what you need to do, and of course you can study both > coreboot sources as well as some good old DOS extenders such as > Tran's PMODE32, DOS4GW from Watcom or my personal favorite DOS32. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From kyosti.malkki at gmail.com Wed Nov 30 12:57:37 2011 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Wed, 30 Nov 2011 13:57:37 +0200 Subject: [coreboot] AMD root_complex usage Message-ID: <1322654257.22522.38.camel@obelix> Hi Could someone explain the need for five (5) different versions of root_complex, which appears to be just a logical container with no real hw to control? northbridge/amd/amdfam10/root_complex northbridge/amd/agesa/family14/root_complex northbridge/amd/agesa/family12/root_complex northbridge/amd/agesa/family10/root_complex northbridge/amd/amdk8/root_complex Could you not have just one drivers/generic/root_complex? In my opinion, the current devicetree.cb practice of placing the "chip northbridge/x/x" line outside the pci_domain is mis-leading on boards without the root_complex. Looking at the amd/persimmon I was also confused about the multiple instances of the "chip northbridge/amd/agesa/family14" line. Thanks, Ky?sti From peter at stuge.se Wed Nov 30 13:32:32 2011 From: peter at stuge.se (Peter Stuge) Date: Wed, 30 Nov 2011 13:32:32 +0100 Subject: [coreboot] AMD root_complex usage In-Reply-To: <1322654257.22522.38.camel@obelix> References: <1322654257.22522.38.camel@obelix> Message-ID: <20111130123232.6539.qmail@stuge.se> Ky?sti M?lkki wrote: > Could someone explain the need for five (5) different versions of > root_complex, which appears to be just a logical container with > no real hw to control? No need. People have copypasted without abstracting. > Could you not have just one drivers/generic/root_complex? Sounds good. Care to make a patch? > Looking at the amd/persimmon I was also confused about the multiple > instances of the "chip northbridge/amd/agesa/family14" line. Some chips have multiple PCI instances, but I believe a devicetree.cb chip always corresponds only to one. //Peter From njacobs8 at adsltotaal.nl Thu Nov 17 23:24:14 2011 From: njacobs8 at adsltotaal.nl (Nils) Date: Thu, 17 Nov 2011 23:24:14 +0100 Subject: [coreboot] Current status of WYSE S50 support Message-ID: <1321568654.2354.32.camel@Debian.lan> Hi JM, Welcome to coreboot. Sorry for the late response, i'm not subscribed. >1. Does the board work after RAMBASE rework (i.e. is ticket #163 really >fixed)? The RAMBASE problems are solved. >2. Is the current support of this board sufficient to boot Linux? More >specifically, I have come across some reports of broken vsa and acpi, >is this still an issue? If so, how does the lack of those features >affect normal Linux operation? You need a working GX2 vsa. As far as i know there is no ready and free available version around. I have a version that works mostly, but i am working on a new version. As i have very little time to spend on it it is evolving slowly. There is no early (bios) vga available yet. ACPI is not implemented. >3. When booting Linux from USB using default manufacturer's BIOS the >ATA port is being disabled. Is this a software or hardware limitation? >In other words, if I boot from USB with coreboot/SeaBIOS would I have >ATA enabled? This is a software limitation of the original bios. I boot from a IDE drive in coreboot. >4. When I boot the Linux kernel with the default BIOS it occasionally >hangs on initializing the PCI subsystem. Is this a result of a bug in >vsa code (virtualized pci) or BIOS? Does the problem persist with >coreboot/SeaBIOS and AMD's vsa? I noticed something called OpenVSA, >does it support Geode GX? I don't see that on coreboot. OpenVSA is never finished and not working. The current state is: I use rev.6433 with some patches for development/testing and stopped updating because of tracing the many regressions took all my time. I don't know if current trunk boots on S50. Probably not as there are a lot of changes such as small bootblock. It boots linux and when you use the in kernel geode GX2 vga driver you can use VGA. Power button doesn't work. No ACPI. (no real problem when you don't use suspend) Beeper doesn't work. Flashrom works. If you want an experimental coreboot rom image send me a mail. Greetings, Nils. From eldmannen at gmail.com Wed Nov 30 19:45:12 2011 From: eldmannen at gmail.com (Fred .) Date: Wed, 30 Nov 2011 19:45:12 +0100 Subject: [coreboot] Fwd: MSI P35 Neo (MS-7360) motherboard In-Reply-To: References: Message-ID: ---------- Forwarded message ---------- From: Fred . Date: 2008/10/28 Subject: MSI P35 Neo (MS-7360) motherboard To: coreboot at coreboot.org Files attached. MSI P35 Neo (MS-7360) Intel P35 chipset. Fintek F71882FG/F71883FG super i/o. ICH9 southbridge. $ dmidecode $ dmidecode --dump $ hardinfo $ lshw $ lspci -n $ lspci -tvnn $ lspci -v $ superiotool -dV Hope it helps. -------------- next part -------------- # dmidecode 2.9 SMBIOS 2.5 present. 27 structures occupying 1379 bytes. Table at 0x000FC070. Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: American Megatrends Inc. Version: V1.8B0 Release Date: 06/26/2008 Address: 0xF0000 Runtime Size: 64 kB ROM Size: 1024 kB Characteristics: ISA is supported PCI is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed ESCD support is available Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 KB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported LS-120 boot is supported ATAPI Zip drive boot is supported BIOS boot specification is supported Targeted content distribution is supported BIOS Revision: 8.14 Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: MICRO-STAR INTERNATIONAL CO.,LTD Product Name: MS-7360 Version: 1.0 Serial Number: To Be Filled By O.E.M. UUID: Not Present Wake-up Type: Power Switch SKU Number: To Be Filled By O.E.M. Family: To Be Filled By O.E.M. Handle 0x0002, DMI type 2, 15 bytes Base Board Information Manufacturer: MICRO-STAR INTERNATIONAL CO.,LTD Product Name: MS-7360 Version: 1.0 Serial Number: To be filled by O.E.M. Asset Tag: To Be Filled By O.E.M. Features: Board is a hosting board Board is replaceable Location In Chassis: To Be Filled By O.E.M. Chassis Handle: 0x0003 Type: Motherboard Contained Object Handles: 0 Handle 0x0003, DMI type 3, 21 bytes Chassis Information Manufacturer: MICRO-STAR INTERNATIONAL CO.,LTD Type: Desktop Lock: Not Present Version: 1.0 Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00000000 Height: Unspecified Number Of Power Cords: 1 Contained Elements: 0 Handle 0x0004, DMI type 4, 40 bytes Processor Information Socket Designation: CPU 1 Type: Central Processor Family: Unknown Manufacturer: Intel ID: F6 06 00 00 FF FB EB BF Version: Intel(R) Core(TM)2 CPU 6420 @ 2.13GHz Voltage: 1.3 V External Clock: 267 MHz Max Speed: 2133 MHz Current Speed: 2136 MHz Status: Populated, Enabled Upgrade: Other L1 Cache Handle: 0x0005 L2 Cache Handle: 0x0006 L3 Cache Handle: 0x0007 Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Part Number: To Be Filled By O.E.M. Core Count: 2 Core Enabled: 2 Thread Count: 2 Characteristics: 64-bit capable Handle 0x0005, DMI type 7, 19 bytes Cache Information Socket Designation: L1-Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 64 KB Maximum Size: 64 KB Supported SRAM Types: Other Installed SRAM Type: Other Speed: Unknown Error Correction Type: Parity System Type: Data Associativity: 8-way Set-associative Handle 0x0006, DMI type 7, 19 bytes Cache Information Socket Designation: L2-Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 4096 KB Maximum Size: 4096 KB Supported SRAM Types: Other Installed SRAM Type: Other Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 16-way Set-associative Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: L3-Cache Configuration: Disabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 0 KB Maximum Size: 0 KB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x0008, DMI type 5, 24 bytes Memory Controller Information Error Detecting Method: 64-bit ECC Error Correcting Capabilities: None Supported Interleave: One-way Interleave Current Interleave: One-way Interleave Maximum Memory Module Size: 4096 MB Maximum Total Memory Size: 16384 MB Supported Speeds: Other Supported Memory Types: DIMM SDRAM Memory Module Voltage: 3.3 V Associated Memory Slots: 4 0x0009 0x000A 0x000B 0x000C Enabled Error Correcting Capabilities: None Handle 0x0009, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM0 Bank Connections: 0 1 Current Speed: Unknown Type: DIMM SDRAM Installed Size: 1024 MB (Double-bank Connection) Enabled Size: 1024 MB (Double-bank Connection) Error Status: OK Handle 0x000A, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM1 Bank Connections: 2 3 Current Speed: Unknown Type: DIMM SDRAM Installed Size: 1024 MB (Double-bank Connection) Enabled Size: 1024 MB (Double-bank Connection) Error Status: OK Handle 0x000B, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM2 Bank Connections: 4 5 Current Speed: Unknown Type: DIMM SDRAM Installed Size: 1024 MB (Double-bank Connection) Enabled Size: 1024 MB (Double-bank Connection) Error Status: OK Handle 0x000C, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM3 Bank Connections: 6 7 Current Speed: Unknown Type: DIMM SDRAM Installed Size: 1024 MB (Double-bank Connection) Enabled Size: 1024 MB (Double-bank Connection) Error Status: OK Handle 0x000D, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 1 en|US|iso8859-1 Currently Installed Language: en|US|iso8859-1 Handle 0x000E, DMI type 15, 35 bytes System Event Log Area Length: 4 bytes Header Start Offset: 0x0000 Header Length: 2 bytes Data Start Offset: 0x0002 Access Method: Indexed I/O, one 16-bit index port, one 8-bit data port Access Address: Index 0x046A, Data 0x046C Status: Invalid, Not Full Change Token: 0x00000000 Header Format: No Header Supported Log Type Descriptors: 6 Descriptor 1: End of log Data Format 1: OEM-specific Descriptor 2: End of log Data Format 2: OEM-specific Descriptor 3: End of log Data Format 3: OEM-specific Descriptor 4: End of log Data Format 4: OEM-specific Descriptor 5: End of log Data Format 5: OEM-specific Descriptor 6: End of log Data Format 6: OEM-specific Handle 0x000F, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 4 GB Error Information Handle: Not Provided Number Of Devices: 4 Handle 0x0010, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Array Handle: 0x000F Partition Width: 0 Handle 0x0011, DMI type 17, 27 bytes Memory Device Array Handle: 0x000F Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: DIMM0 Bank Locator: BANK0 Type: SDRAM Type Detail: Synchronous Speed: Unknown Manufacturer: Manufacturer0 Serial Number: SerNum0 Asset Tag: AssetTagNum0 Part Number: PartNum0 Handle 0x0012, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0003FFFFFFF Range Size: 1 GB Physical Device Handle: 0x0011 Memory Array Mapped Address Handle: 0x0010 Partition Row Position: 1 Interleaved Data Depth: 1 Handle 0x0013, DMI type 17, 27 bytes Memory Device Array Handle: 0x000F Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: DIMM1 Bank Locator: BANK1 Type: SDRAM Type Detail: Synchronous Speed: Unknown Manufacturer: Manufacturer1 Serial Number: SerNum1 Asset Tag: AssetTagNum1 Part Number: PartNum1 Handle 0x0014, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00040000000 Ending Address: 0x0007FFFFFFF Range Size: 1 GB Physical Device Handle: 0x0013 Memory Array Mapped Address Handle: 0x0010 Partition Row Position: 1 Interleaved Data Depth: 1 Handle 0x0015, DMI type 17, 27 bytes Memory Device Array Handle: 0x000F Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: DIMM2 Bank Locator: BANK2 Type: SDRAM Type Detail: Synchronous Speed: Unknown Manufacturer: Manufacturer2 Serial Number: SerNum2 Asset Tag: AssetTagNum2 Part Number: PartNum2 Handle 0x0016, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00080000000 Ending Address: 0x000BFFFFFFF Range Size: 1 GB Physical Device Handle: 0x0015 Memory Array Mapped Address Handle: 0x0010 Partition Row Position: 1 Interleaved Data Depth: 1 Handle 0x0017, DMI type 17, 27 bytes Memory Device Array Handle: 0x000F Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: DIMM3 Bank Locator: BANK3 Type: SDRAM Type Detail: Synchronous Speed: Unknown Manufacturer: Manufacturer3 Serial Number: SerNum3 Asset Tag: AssetTagNum3 Part Number: PartNum3 Handle 0x0018, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x000C0000000 Ending Address: 0x000FFFFFFFF Range Size: 1 GB Physical Device Handle: 0x0017 Memory Array Mapped Address Handle: 0x0010 Partition Row Position: 1 Interleaved Data Depth: 1 Handle 0x0019, DMI type 32, 20 bytes System Boot Information Status: No errors detected Handle 0x001A, DMI type 127, 4 bytes End Of Table -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- # dmidecode 2.9 SMBIOS 2.5 present. 27 structures occupying 1379 bytes. Table at 0x000FC070. Handle 0x0000, DMI type 0, 24 bytes Header and Data: 00 18 00 00 01 02 00 F0 03 0F 90 DE 8B 7F 01 00 00 00 33 05 08 0E FF FF Strings: 41 6D 65 72 69 63 61 6E 20 4D 65 67 61 74 72 65 6E 64 73 20 49 6E 63 2E 00 "American Megatrends Inc." 56 31 2E 38 42 30 00 "V1.8B0" 30 36 2F 32 36 2F 32 30 30 38 00 "06/26/2008" Handle 0x0001, DMI type 1, 27 bytes Header and Data: 01 1B 01 00 01 02 03 04 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 06 05 06 Strings: 4D 49 43 52 4F 2D 53 54 41 52 20 49 4E 54 45 52 4E 41 54 49 4F 4E 41 4C 20 43 4F 2E 2C 4C 54 44 00 "MICRO-STAR INTERNATIONAL CO.,LTD" 4D 53 2D 37 33 36 30 00 "MS-7360" 31 2E 30 00 "1.0" 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." Handle 0x0002, DMI type 2, 15 bytes Header and Data: 02 0F 02 00 01 02 03 04 05 09 06 03 00 0A 00 Strings: 4D 49 43 52 4F 2D 53 54 41 52 20 49 4E 54 45 52 4E 41 54 49 4F 4E 41 4C 20 43 4F 2E 2C 4C 54 44 00 "MICRO-STAR INTERNATIONAL CO.,LTD" 4D 53 2D 37 33 36 30 00 "MS-7360" 31 2E 30 00 "1.0" 54 6F 20 62 65 20 66 69 6C 6C 65 64 20 62 79 20 4F 2E 45 2E 4D 2E 00 "To be filled by O.E.M." 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." Handle 0x0003, DMI type 3, 21 bytes Header and Data: 03 15 03 00 01 03 02 03 04 03 03 03 03 00 00 00 00 00 01 00 00 Strings: 4D 49 43 52 4F 2D 53 54 41 52 20 49 4E 54 45 52 4E 41 54 49 4F 4E 41 4C 20 43 4F 2E 2C 4C 54 44 00 "MICRO-STAR INTERNATIONAL CO.,LTD" 31 2E 30 00 "1.0" 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." Handle 0x0004, DMI type 4, 40 bytes Header and Data: 04 28 04 00 01 03 02 02 F6 06 00 00 FF FB EB BF 03 8D 0B 01 55 08 58 08 41 01 05 00 06 00 07 00 04 05 06 02 02 02 04 00 Strings: 43 50 55 20 31 00 "CPU 1" 49 6E 74 65 6C 20 20 20 20 20 20 20 20 20 20 20 20 00 "Intel " 49 6E 74 65 6C 28 52 29 20 43 6F 72 65 28 54 4D 29 32 20 43 50 55 20 20 20 20 20 20 20 20 20 20 36 34 32 30 20 20 40 20 32 2E 31 33 47 48 7A 20 20 20 20 20 00 "Intel(R) Core(TM)2 CPU 6420 @ 2.13GHz " 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." 54 6F 20 42 65 20 46 69 6C 6C 65 64 20 42 79 20 4F 2E 45 2E 4D 2E 00 "To Be Filled By O.E.M." Handle 0x0005, DMI type 7, 19 bytes Header and Data: 07 13 05 00 01 80 01 40 00 40 00 01 00 01 00 00 04 04 07 Strings: 4C 31 2D 43 61 63 68 65 00 "L1-Cache" Handle 0x0006, DMI type 7, 19 bytes Header and Data: 07 13 06 00 01 81 01 00 10 00 10 01 00 01 00 00 05 05 08 Strings: 4C 32 2D 43 61 63 68 65 00 "L2-Cache" Handle 0x0007, DMI type 7, 19 bytes Header and Data: 07 13 07 00 01 02 03 00 00 00 00 02 00 02 00 00 02 02 02 Strings: 4C 33 2D 43 61 63 68 65 00 "L3-Cache" Handle 0x0008, DMI type 5, 24 bytes Header and Data: 05 18 08 00 06 04 03 03 0C 01 00 00 05 02 04 09 00 0A 00 0B 00 0C 00 04 Handle 0x0009, DMI type 6, 12 bytes Header and Data: 06 0C 09 00 01 01 00 00 05 8A 8A 00 Strings: 44 49 4D 4D 30 00 "DIMM0" Handle 0x000A, DMI type 6, 12 bytes Header and Data: 06 0C 0A 00 01 23 00 00 05 8A 8A 00 Strings: 44 49 4D 4D 31 00 "DIMM1" Handle 0x000B, DMI type 6, 12 bytes Header and Data: 06 0C 0B 00 01 45 00 00 05 8A 8A 00 Strings: 44 49 4D 4D 32 00 "DIMM2" Handle 0x000C, DMI type 6, 12 bytes Header and Data: 06 0C 0C 00 01 67 00 00 05 8A 8A 00 Strings: 44 49 4D 4D 33 00 "DIMM3" Handle 0x000D, DMI type 13, 22 bytes Header and Data: 0D 16 0D 00 01 FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 Strings: 65 6E 7C 55 53 7C 69 73 6F 38 38 35 39 2D 31 00 "en|US|iso8859-1" Handle 0x000E, DMI type 15, 35 bytes Header and Data: 0F 23 0E 00 04 00 00 00 02 00 02 00 00 00 00 00 6A 04 6C 04 00 06 02 FF FF FF FF FF FF FF FF FF FF FF FF Handle 0x000F, DMI type 16, 15 bytes Header and Data: 10 0F 0F 00 03 03 03 00 00 40 00 FE FF 04 00 Handle 0x0010, DMI type 19, 15 bytes Header and Data: 13 0F 10 00 00 00 00 00 FF FF 3F 00 0F 00 04 Handle 0x0011, DMI type 17, 27 bytes Header and Data: 11 1B 11 00 0F 00 FE FF 40 00 40 00 00 04 09 00 01 02 0F 80 00 00 00 03 04 05 06 Strings: 44 49 4D 4D 30 00 "DIMM0" 42 41 4E 4B 30 00 "BANK0" 4D 61 6E 75 66 61 63 74 75 72 65 72 30 00 "Manufacturer0" 53 65 72 4E 75 6D 30 00 "SerNum0" 41 73 73 65 74 54 61 67 4E 75 6D 30 00 "AssetTagNum0" 50 61 72 74 4E 75 6D 30 00 "PartNum0" Handle 0x0012, DMI type 20, 19 bytes Header and Data: 14 13 12 00 00 00 00 00 FF FF 0F 00 11 00 10 00 01 00 01 Handle 0x0013, DMI type 17, 27 bytes Header and Data: 11 1B 13 00 0F 00 FE FF 40 00 40 00 00 04 09 00 01 02 0F 80 00 00 00 03 04 05 06 Strings: 44 49 4D 4D 31 00 "DIMM1" 42 41 4E 4B 31 00 "BANK1" 4D 61 6E 75 66 61 63 74 75 72 65 72 31 00 "Manufacturer1" 53 65 72 4E 75 6D 31 00 "SerNum1" 41 73 73 65 74 54 61 67 4E 75 6D 31 00 "AssetTagNum1" 50 61 72 74 4E 75 6D 31 00 "PartNum1" Handle 0x0014, DMI type 20, 19 bytes Header and Data: 14 13 14 00 00 00 10 00 FF FF 1F 00 13 00 10 00 01 00 01 Handle 0x0015, DMI type 17, 27 bytes Header and Data: 11 1B 15 00 0F 00 FE FF 40 00 40 00 00 04 09 00 01 02 0F 80 00 00 00 03 04 05 06 Strings: 44 49 4D 4D 32 00 "DIMM2" 42 41 4E 4B 32 00 "BANK2" 4D 61 6E 75 66 61 63 74 75 72 65 72 32 00 "Manufacturer2" 53 65 72 4E 75 6D 32 00 "SerNum2" 41 73 73 65 74 54 61 67 4E 75 6D 32 00 "AssetTagNum2" 50 61 72 74 4E 75 6D 32 00 "PartNum2" Handle 0x0016, DMI type 20, 19 bytes Header and Data: 14 13 16 00 00 00 20 00 FF FF 2F 00 15 00 10 00 01 00 01 Handle 0x0017, DMI type 17, 27 bytes Header and Data: 11 1B 17 00 0F 00 FE FF 40 00 40 00 00 04 09 00 01 02 0F 80 00 00 00 03 04 05 06 Strings: 44 49 4D 4D 33 00 "DIMM3" 42 41 4E 4B 33 00 "BANK3" 4D 61 6E 75 66 61 63 74 75 72 65 72 33 00 "Manufacturer3" 53 65 72 4E 75 6D 33 00 "SerNum3" 41 73 73 65 74 54 61 67 4E 75 6D 33 00 "AssetTagNum3" 50 61 72 74 4E 75 6D 33 00 "PartNum3" Handle 0x0018, DMI type 20, 19 bytes Header and Data: 14 13 18 00 00 00 30 00 FF FF 3F 00 17 00 10 00 01 00 01 Handle 0x0019, DMI type 32, 20 bytes Header and Data: 20 14 19 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Handle 0x001A, DMI type 127, 4 bytes Header and Data: 7F 04 1A 00 -------------- next part -------------- darkstar description: Desktop Computer product: MS-7360 vendor: MICRO-STAR INTERNATIONAL CO.,LTD version: 1.0 serial: To Be Filled By O.E.M. width: 32 bits capabilities: smbios-2.5 dmi-2.5 smp-1.4 smp configuration: boot=normal chassis=desktop cpus=2 *-core description: Motherboard product: MS-7360 vendor: MICRO-STAR INTERNATIONAL CO.,LTD physical id: 0 version: 1.0 serial: To be filled by O.E.M. slot: To Be Filled By O.E.M. *-firmware description: BIOS vendor: American Megatrends Inc. physical id: 0 version: V1.8B0 (06/26/2008) size: 64KiB capacity: 960KiB capabilities: isa pci pnp apm upgrade shadowing escd cdboot bootselect socketedrom edd int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb ls120boot zipboot biosbootspecification *-cpu:0 description: CPU product: Intel(R) Core(TM)2 CPU 6420 @ 2.13GHz vendor: Intel Corp. physical id: 4 bus info: cpu at 0 version: 6.15.6 serial: 0000-06F6-0000-0000-0000-0000 slot: CPU 1 size: 2136MHz capacity: 2136MHz width: 64 bits clock: 267MHz capabilities: boot fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx x86-64 constant_tsc arch_perfmon pebs bts pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm cpufreq configuration: id=0 *-cache:0 description: L1 cache physical id: 5 slot: L1-Cache size: 64KiB capacity: 64KiB capabilities: internal write-back data *-cache:1 description: L2 cache physical id: 6 slot: L2-Cache size: 4MiB capacity: 4MiB capabilities: internal write-back unified *-cache:2 DISABLED description: L3 cache physical id: 7 slot: L3-Cache capabilities: internal *-logicalcpu:0 description: Logical CPU physical id: 0.1 width: 64 bits capabilities: logical *-logicalcpu:1 description: Logical CPU physical id: 0.2 width: 64 bits capabilities: logical *-memory description: System Memory physical id: f slot: System board or motherboard size: 4GiB *-bank:0 description: DIMM SDRAM Synchronous product: PartNum0 vendor: Manufacturer0 physical id: 0 serial: SerNum0 slot: DIMM0 size: 1GiB width: 64 bits *-bank:1 description: DIMM SDRAM Synchronous product: PartNum1 vendor: Manufacturer1 physical id: 1 serial: SerNum1 slot: DIMM1 size: 1GiB width: 64 bits *-bank:2 description: DIMM SDRAM Synchronous product: PartNum2 vendor: Manufacturer2 physical id: 2 serial: SerNum2 slot: DIMM2 size: 1GiB width: 64 bits *-bank:3 description: DIMM SDRAM Synchronous product: PartNum3 vendor: Manufacturer3 physical id: 3 serial: SerNum3 slot: DIMM3 size: 1GiB width: 64 bits *-cpu:1 physical id: 1 bus info: cpu at 1 version: 6.15.6 serial: 0000-06F6-0000-0000-0000-0000 size: 2136MHz capacity: 2136MHz capabilities: vmx ht cpufreq configuration: id=0 *-logicalcpu:0 description: Logical CPU physical id: 0.1 capabilities: logical *-logicalcpu:1 description: Logical CPU physical id: 0.2 capabilities: logical *-pci description: Host bridge product: 82G33/G31/P35/P31 Express DRAM Controller vendor: Intel Corporation physical id: 100 bus info: pci at 0000:00:00.0 version: 02 width: 32 bits clock: 33MHz *-pci:0 description: PCI bridge product: 82G33/G31/P35/P31 Express PCI Express Root Port vendor: Intel Corporation physical id: 1 bus info: pci at 0000:00:01.0 version: 02 width: 32 bits clock: 33MHz capabilities: pci pm msi pciexpress bus_master cap_list configuration: driver=pcieport-driver *-display description: VGA compatible controller product: GeForce 8600 GT vendor: nVidia Corporation physical id: 0 bus info: pci at 0000:01:00.0 version: a1 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=nvidia latency=0 module=nvidia *-usb:0 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #4 vendor: Intel Corporation physical id: 1a bus info: pci at 0000:00:1a.0 version: 02 width: 32 bits clock: 33MHz capabilities: bus_master cap_list configuration: driver=uhci_hcd latency=0 module=uhci_hcd *-usb:1 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #5 vendor: Intel Corporation physical id: 1a.1 bus info: pci at 0000:00:1a.1 version: 02 width: 32 bits clock: 33MHz capabilities: bus_master cap_list configuration: driver=uhci_hcd latency=0 module=uhci_hcd *-usb:2 description: USB Controller product: 82801I (ICH9 Family) USB2 EHCI Controller #2 vendor: Intel Corporation physical id: 1a.7 bus info: pci at 0000:00:1a.7 version: 02 width: 32 bits clock: 33MHz capabilities: pm debug bus_master cap_list configuration: driver=ehci_hcd latency=0 module=ehci_hcd *-multimedia description: Audio device product: 82801I (ICH9 Family) HD Audio Controller vendor: Intel Corporation physical id: 1b bus info: pci at 0000:00:1b.0 version: 02 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=HDA Intel latency=0 module=snd_hda_intel *-pci:1 description: PCI bridge product: 82801I (ICH9 Family) PCI Express Port 1 vendor: Intel Corporation physical id: 1c bus info: pci at 0000:00:1c.0 version: 02 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm bus_master cap_list configuration: driver=pcieport-driver *-pci:2 description: PCI bridge product: 82801I (ICH9 Family) PCI Express Port 6 vendor: Intel Corporation physical id: 1c.5 bus info: pci at 0000:00:1c.5 version: 02 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm bus_master cap_list configuration: driver=pcieport-driver *-network description: Ethernet interface product: RTL8111/8168B PCI Express Gigabit Ethernet controller vendor: Realtek Semiconductor Co., Ltd. physical id: 0 bus info: pci at 0000:03:00.0 logical name: eth0 version: 01 serial: 00:19:db:6c:87:59 size: 100MB/s capacity: 1GB/s width: 64 bits clock: 33MHz capabilities: pm vpd msi pciexpress bus_master cap_list ethernet physical tp 10bt 10bt-fd 100bt 100bt-fd 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=2.3LK-NAPI duplex=full ip=213.112.91.144 latency=0 link=yes module=r8169 multicast=yes port=twisted pair speed=100MB/s *-usb:3 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #1 vendor: Intel Corporation physical id: 1d bus info: pci at 0000:00:1d.0 version: 02 width: 32 bits clock: 33MHz capabilities: bus_master cap_list configuration: driver=uhci_hcd latency=0 module=uhci_hcd *-usb:4 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #2 vendor: Intel Corporation physical id: 1d.1 bus info: pci at 0000:00:1d.1 version: 02 width: 32 bits clock: 33MHz capabilities: bus_master cap_list configuration: driver=uhci_hcd latency=0 module=uhci_hcd *-usb:5 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #3 vendor: Intel Corporation physical id: 1d.2 bus info: pci at 0000:00:1d.2 version: 02 width: 32 bits clock: 33MHz capabilities: bus_master cap_list configuration: driver=uhci_hcd latency=0 module=uhci_hcd *-usb:6 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #6 vendor: Intel Corporation physical id: 1d.3 bus info: pci at 0000:00:1d.3 version: 02 width: 32 bits clock: 33MHz capabilities: bus_master cap_list configuration: driver=uhci_hcd latency=0 module=uhci_hcd *-usb:7 description: USB Controller product: 82801I (ICH9 Family) USB2 EHCI Controller #1 vendor: Intel Corporation physical id: 1d.7 bus info: pci at 0000:00:1d.7 version: 02 width: 32 bits clock: 33MHz capabilities: pm debug bus_master cap_list configuration: driver=ehci_hcd latency=0 module=ehci_hcd *-pci:3 description: PCI bridge product: 82801 PCI Bridge vendor: Intel Corporation physical id: 1e bus info: pci at 0000:00:1e.0 version: 92 width: 32 bits clock: 33MHz capabilities: pci bus_master cap_list *-isa description: ISA bridge product: 82801IB (ICH9) LPC Interface Controller vendor: Intel Corporation physical id: 1f bus info: pci at 0000:00:1f.0 version: 02 width: 32 bits clock: 33MHz capabilities: isa bus_master cap_list configuration: latency=0 *-ide:0 description: IDE interface product: 82801IB (ICH9) 2 port SATA IDE Controller vendor: Intel Corporation physical id: 1f.2 bus info: pci at 0000:00:1f.2 logical name: scsi0 logical name: scsi1 version: 02 width: 32 bits clock: 66MHz capabilities: ide pm bus_master cap_list emulated configuration: driver=ata_piix latency=0 module=ata_piix *-disk:0 description: ATA Disk product: SAMSUNG HD501LJ physical id: 0 bus info: scsi at 0:0.0.0 logical name: /dev/sda version: CR10 serial: S0MUJ1DP508269 size: 465GiB (500GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 signature=000ca0a4 *-volume:0 description: Windows NTFS volume physical id: 1 bus info: scsi at 0:0.0.0,1 logical name: /dev/sda1 version: 3.1 serial: 8ab1b534-1dac-fd48-920e-f1b7b98b7ab8 size: 24GiB capacity: 24GiB capabilities: primary bootable ntfs initialized configuration: clustersize=4096 created=2007-06-21 00:37:23 filesystem=ntfs label=windows state=clean *-volume:1 description: Extended partition physical id: 2 bus info: scsi at 0:0.0.0,2 logical name: /dev/sda2 size: 441GiB capacity: 441GiB capabilities: primary extended partitioned partitioned:extended *-logicalvolume:0 description: HPFS/NTFS partition physical id: 5 logical name: /dev/sda5 logical name: /media/Music capacity: 73GiB configuration: mount.fstype=fuseblk mount.options=rw,nosuid,nodev,user_id=0,group_id=0,allow_other,blksize=4096 state=mounted *-logicalvolume:1 description: HPFS/NTFS partition physical id: 6 logical name: /dev/sda6 capacity: 368GiB *-disk:1 description: ATA Disk product: SAMSUNG HD252KJ physical id: 1 bus info: scsi at 1:0.0.0 logical name: /dev/sdb version: CM10 serial: S0NJJDPP900694 size: 232GiB (250GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 signature=0005dff8 *-volume:0 description: EXT3 volume vendor: Linux physical id: 1 bus info: scsi at 1:0.0.0,1 logical name: /dev/sdb1 logical name: / logical name: /dev/.static/dev version: 1.0 serial: 606e20ff-fac7-4f82-8ab4-e36d0b64017c size: 23GiB capacity: 23GiB capabilities: primary bootable journaled extended_attributes large_files huge_files recover ext3 ext2 initialized configuration: created=2008-04-24 21:50:55 filesystem=ext3 modified=2008-10-28 05:07:26 mount.fstype=ext3 mount.options=ro,errors=remount-ro,data=ordered mounted=2008-10-27 17:43:42 state=mounted *-volume:1 description: EXT3 volume vendor: Linux physical id: 2 bus info: scsi at 1:0.0.0,2 logical name: /dev/sdb2 logical name: /media/sdb2 version: 1.0 serial: 5ff034fc-3484-4136-b95f-ce0dc3885db9 size: 209GiB capacity: 209GiB capabilities: primary journaled extended_attributes large_files huge_files recover ext3 ext2 initialized configuration: created=2007-10-19 19:46:08 filesystem=ext3 modified=2008-10-28 13:29:08 mount.fstype=ext3 mount.options=rw,relatime,errors=continue,data=ordered mounted=2008-10-28 13:29:08 state=mounted *-serial UNCLAIMED description: SMBus product: 82801I (ICH9 Family) SMBus Controller vendor: Intel Corporation physical id: 1f.3 bus info: pci at 0000:00:1f.3 version: 02 width: 64 bits clock: 33MHz configuration: latency=0 *-ide:1 description: IDE interface product: 82801I (ICH9 Family) 2 port SATA IDE Controller vendor: Intel Corporation physical id: 1f.5 bus info: pci at 0000:00:1f.5 version: 02 width: 32 bits clock: 66MHz capabilities: ide pm bus_master cap_list configuration: driver=ata_piix latency=0 module=ata_piix *-network DISABLED description: Ethernet interface physical id: 1 logical name: pan0 serial: fa:ea:3a:10:99:b0 capabilities: ethernet physical configuration: broadcast=yes driver=bridge driverversion=2.3 firmware=N/A link=yes multicast=yes -------------- next part -------------- 00:00.0 0600: 8086:29c0 (rev 02) 00:01.0 0604: 8086:29c1 (rev 02) 00:1a.0 0c03: 8086:2937 (rev 02) 00:1a.1 0c03: 8086:2938 (rev 02) 00:1a.7 0c03: 8086:293c (rev 02) 00:1b.0 0403: 8086:293e (rev 02) 00:1c.0 0604: 8086:2940 (rev 02) 00:1c.5 0604: 8086:294a (rev 02) 00:1d.0 0c03: 8086:2934 (rev 02) 00:1d.1 0c03: 8086:2935 (rev 02) 00:1d.2 0c03: 8086:2936 (rev 02) 00:1d.3 0c03: 8086:2939 (rev 02) 00:1d.7 0c03: 8086:293a (rev 02) 00:1e.0 0604: 8086:244e (rev 92) 00:1f.0 0601: 8086:2918 (rev 02) 00:1f.2 0101: 8086:2921 (rev 02) 00:1f.3 0c05: 8086:2930 (rev 02) 00:1f.5 0101: 8086:2926 (rev 02) 01:00.0 0300: 10de:0402 (rev a1) 03:00.0 0200: 10ec:8168 (rev 01) -------------- next part -------------- -[0000:00]-+-00.0 Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller [8086:29c0] +-01.0-[0000:01]----00.0 nVidia Corporation GeForce 8600 GT [10de:0402] +-1a.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937] +-1a.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938] +-1a.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c] +-1b.0 Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e] +-1c.0-[0000:02]-- +-1c.5-[0000:03]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] +-1d.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] +-1d.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935] +-1d.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936] +-1d.3 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939] +-1d.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a] +-1e.0-[0000:04]-- +-1f.0 Intel Corporation 82801IB (ICH9) LPC Interface Controller [8086:2918] +-1f.2 Intel Corporation 82801IB (ICH9) 2 port SATA IDE Controller [8086:2921] +-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller [8086:2930] \-1f.5 Intel Corporation 82801I (ICH9 Family) 2 port SATA IDE Controller [8086:2926] -------------- next part -------------- 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, fast devsel, latency 0 Capabilities: [e0] Vendor Specific Information Kernel modules: intel-agp 00:01.0 PCI bridge: Intel Corporation 82G33/G31/P35/P31 Express PCI Express Root Port (rev 02) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: fa000000-feafffff Prefetchable memory behind bridge: 00000000d0000000-00000000dfffffff Capabilities: [88] Subsystem: Intel Corporation Device 0000 Capabilities: [80] Power Management version 3 Capabilities: [90] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Capabilities: [a0] Express Root Port (Slot+), MSI 00 Capabilities: [100] Virtual Channel Capabilities: [140] Root Complex Link Kernel driver in use: pcieport-driver Kernel modules: shpchp 00:1a.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, medium devsel, latency 0, IRQ 16 I/O ports at cc00 [size=32] Capabilities: [50] Vendor Specific Information Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00:1a.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, medium devsel, latency 0, IRQ 21 I/O ports at c880 [size=32] Capabilities: [50] Vendor Specific Information Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00:1a.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 (rev 02) (prog-if 20) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, medium devsel, latency 0, IRQ 18 Memory at f9fffc00 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Capabilities: [58] Debug port: BAR=1 offset=00a0 Capabilities: [98] Vendor Specific Information Kernel driver in use: ehci_hcd Kernel modules: ehci-hcd 00:1b.0 Audio device: Intel Corporation 82801I (ICH9 Family) HD Audio Controller (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, fast devsel, latency 0, IRQ 22 Memory at f9ff8000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Capabilities: [60] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Capabilities: [70] Express Root Complex Integrated Endpoint, MSI 00 Capabilities: [100] Virtual Channel Capabilities: [130] Root Complex Link Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel 00:1c.0 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 1 (rev 02) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 Capabilities: [40] Express Root Port (Slot+), MSI 00 Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Capabilities: [90] Subsystem: Micro-Star International Co., Ltd. Device 7360 Capabilities: [a0] Power Management version 2 Capabilities: [100] Virtual Channel Capabilities: [180] Root Complex Link Kernel driver in use: pcieport-driver Kernel modules: shpchp 00:1c.5 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 6 (rev 02) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: feb00000-febfffff Capabilities: [40] Express Root Port (Slot+), MSI 00 Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Capabilities: [90] Subsystem: Micro-Star International Co., Ltd. Device 7360 Capabilities: [a0] Power Management version 2 Capabilities: [100] Virtual Channel Capabilities: [180] Root Complex Link Kernel driver in use: pcieport-driver Kernel modules: shpchp 00:1d.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, medium devsel, latency 0, IRQ 23 I/O ports at c800 [size=32] Capabilities: [50] Vendor Specific Information Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00:1d.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, medium devsel, latency 0, IRQ 19 I/O ports at c480 [size=32] Capabilities: [50] Vendor Specific Information Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00:1d.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, medium devsel, latency 0, IRQ 18 I/O ports at c400 [size=32] Capabilities: [50] Vendor Specific Information Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00:1d.3 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, medium devsel, latency 0, IRQ 16 I/O ports at c080 [size=32] Capabilities: [50] Vendor Specific Information Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00:1d.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 (rev 02) (prog-if 20) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, medium devsel, latency 0, IRQ 23 Memory at f9fff800 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Capabilities: [58] Debug port: BAR=1 offset=00a0 Capabilities: [98] Vendor Specific Information Kernel driver in use: ehci_hcd Kernel modules: ehci-hcd 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92) (prog-if 01) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=04, subordinate=04, sec-latency=32 Capabilities: [50] Subsystem: Micro-Star International Co., Ltd. Device 7360 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, medium devsel, latency 0 Capabilities: [e0] Vendor Specific Information Kernel modules: iTCO_wdt 00:1f.2 IDE interface: Intel Corporation 82801IB (ICH9) 2 port SATA IDE Controller (rev 02) (prog-if 8f [Master SecP SecO PriP PriO]) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 19 I/O ports at c000 [size=8] I/O ports at bc00 [size=4] I/O ports at b880 [size=8] I/O ports at b800 [size=4] I/O ports at b480 [size=16] I/O ports at b400 [size=16] Capabilities: [70] Power Management version 3 Capabilities: [b0] Vendor Specific Information Kernel driver in use: ata_piix Kernel modules: ata_piix 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: medium devsel, IRQ 11 Memory at f9fff400 (64-bit, non-prefetchable) [size=256] I/O ports at 0400 [size=32] Kernel modules: i2c-i801 00:1f.5 IDE interface: Intel Corporation 82801I (ICH9 Family) 2 port SATA IDE Controller (rev 02) (prog-if 85 [Master SecO PriO]) Subsystem: Micro-Star International Co., Ltd. Device 7360 Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 19 I/O ports at b000 [size=8] I/O ports at ac00 [size=4] I/O ports at a880 [size=8] I/O ports at a800 [size=4] I/O ports at a480 [size=16] I/O ports at a400 [size=16] Capabilities: [70] Power Management version 3 Capabilities: [b0] Vendor Specific Information Kernel driver in use: ata_piix Kernel modules: ata_piix 01:00.0 VGA compatible controller: nVidia Corporation GeForce 8600 GT (rev a1) Subsystem: CardExpert Technology Device 0401 Flags: bus master, fast devsel, latency 0, IRQ 16 Memory at fd000000 (32-bit, non-prefetchable) [size=16M] Memory at d0000000 (64-bit, prefetchable) [size=256M] Memory at fa000000 (64-bit, non-prefetchable) [size=32M] I/O ports at dc00 [size=128] [virtual] Expansion ROM at feae0000 [disabled] [size=128K] Capabilities: [60] Power Management version 2 Capabilities: [68] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Capabilities: [78] Express Endpoint, MSI 00 Capabilities: [100] Virtual Channel Capabilities: [128] Power Budgeting Capabilities: [600] Vendor Specific Information Kernel driver in use: nvidia Kernel modules: nvidiafb, nvidia 03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01) Subsystem: Micro-Star International Co., Ltd. Device 360c Flags: bus master, fast devsel, latency 0, IRQ 220 I/O ports at e800 [size=256] Memory at febff000 (64-bit, non-prefetchable) [size=4K] Expansion ROM at febc0000 [disabled] [size=128K] Capabilities: [40] Power Management version 2 Capabilities: [48] Vital Product Data Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Capabilities: [60] Express Endpoint, MSI 00 Capabilities: [84] Vendor Specific Information Capabilities: [100] Advanced Error Reporting Capabilities: [12c] Virtual Channel Capabilities: [148] Device Serial Number 68-81-ec-10-00-00-00-6e Capabilities: [154] Power Budgeting Kernel driver in use: r8169 Kernel modules: r8169 -------------- next part -------------- superiotool r3125 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Found Fintek F71882FG/F71883FG (vid=0x3419, id=0x4105) at 0x4e No dump available for this Super I/O Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x0541, rev=0x0 Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0x05/0x0f, rev=0x41 Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff From eldmannen at gmail.com Wed Nov 30 19:48:31 2011 From: eldmannen at gmail.com (Fred .) Date: Wed, 30 Nov 2011 19:48:31 +0100 Subject: [coreboot] Add password protection Message-ID: Add password protection so you need password for boot the system. Add it to SeaBIOS too. From eldmannen at gmail.com Wed Nov 30 19:46:19 2011 From: eldmannen at gmail.com (Fred .) Date: Wed, 30 Nov 2011 19:46:19 +0100 Subject: [coreboot] Fwd: mptable and irq_tables.c for MSI P35 Neo (MS-7360) In-Reply-To: References: Message-ID: ---------- Forwarded message ---------- From: Fred . Date: Tue, Oct 28, 2008 at 9:14 PM Subject: mptable and irq_tables.c for MSI P35 Neo (MS-7360) To: coreboot at coreboot.org I've attached the mptable file, and irq_tables.c file. -------------- next part -------------- /* generated by MPTable, version 2.0.15*/ /* as modified by RGM for coreboot */ #include #include #include #include #include void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); /*Bus: Bus ID Type*/ smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 2, "PCI "); smp_write_bus(mc, 3, "PCI "); smp_write_bus(mc, 4, "PCI "); smp_write_bus(mc, 5, "ISA "); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, 0xfec00000); { device_t dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 3, 0x20, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 4, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 5, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 8, 0x20, res->base); } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x0, 0x2, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x1, 0x2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x0, 0x2, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x4, 0x2, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x6, 0x2, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x8, 0x2, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x9, 0x2, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0xc, 0x2, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0xd, 0x2, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7e, 0x2, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x68, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x69, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6a, 0x2, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x16); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x0, 0x2, 0x11); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); MP Config Extended Table Entries: -- System Address Space bus ID: 0 address type: I/O address address base: 0xa000 address range: 0x5000 -- System Address Space bus ID: 0 address type: I/O address address base: 0x0 address range: 0x100 -- System Address Space bus ID: 0 address type: memory address address base: 0xa0000 address range: 0x20000 -- System Address Space bus ID: 0 address type: memory address address base: 0xf9000000 address range: 0x5c00000 -- System Address Space bus ID: 0 address type: prefetch address address base: 0xd0000000 address range: 0x29000000 -- Bus Heirarchy bus ID: 5 bus info: 0x01 parent bus ID: 0-- Compatibility Bus Address bus ID: 0 address modifier: add predefined range: 0x00000000-- Compatibility Bus Address bus ID: 0 address modifier: add predefined range: 0x00000001 /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } unsigned long write_smp_table(unsigned long addr) { void *v; v = smp_write_floating_table(addr); return (unsigned long)smp_write_config_table(v); } -------------- next part -------------- A non-text attachment was scrubbed... Name: irq_tables.c Type: text/x-csrc Size: 2445 bytes Desc: not available URL: