[coreboot] Trouble with cbfstool when attempting dualboot
patrick at georgi-clan.de
Tue Nov 1 18:27:12 CET 2011
Am 01.11.2011 14:02, schrieb Kyösti Mälkki:
> My Cache-As-Ram boot enters intel/car/cache_as_ram.inc but never reaches
> LogicalAP_SIPINotdone in it. I found a note in this file saying LAPIC ID
> logic works only for processors with two threads, so does a dual Xeon
> P4/HT setup require re-writing this logic?
Possibly. Comparing the code to the datasheets will give you a
> I happen to have normal/romstage that does not cross CONFIG_XIP_ROM_SIZE
> boundary. I think it is a bug in cbfstool that normal/romstage placement
> is unaligned,
It is aligned...
> since early_mtrr_init does not cover cases where
> normal/romstage crosses said boundary.
... which is why this works.
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