[coreboot] How to change clockchip frequency?

Marc Jones marcj303 at gmail.com
Wed Nov 2 20:04:02 CET 2011

On Wed, Nov 2, 2011 at 10:26 AM, Oskar Enoksson <enok at lysator.liu.se> wrote:
> On 11/02/2011 04:31 PM, Marc Jones wrote:
>> On Wed, Nov 2, 2011 at 6:37 AM, Oskar Enoksson<enok at lysator.liu.se>
>>  wrote:
>>> I have a chip called CDC960 on my motherboard. It is responsible for
>>> generating the bus frequency for the cpu, the pci bus etc. I downloaded
>>> the
>>> datasheet and noticed that I can change the base frequency by +/-10% by
>>> sending an smbus command to the cdc960.
>>> When I sent the smbus commands from a running linux the system froze for
>>> a
>>> few seconds and then rebooted. But after reboot the frequency was indeed
>>> changed (overclocked) and everything worked just fine.
>>> I tried to add the smbus command to romstage.c in my coreboot, but that
>>> didn't work. The boot process just hanged immediately after the smbus
>>> command had been sent.
>>> I guess the running CPU (or something else in the system) cannot handle
>>> the
>>> frequency change and needs to be reset immediately after the command is
>>> sent. Perhaps some watchdog under Linux resets the system after a few
>>> seconds of irresponsiveness. But what is the recommended way in coreboot?
>> It would be hard to tell why Linux resets, but you can look in the
>> southbridge for a watchdog. You should also read the CPU spec about
>> changing clock speed etc.
> Thanks. There is a watchdog in the southbridge (amd 8111) and it could be
> set up to reset the system after a specified number of seconds, but it
> requires memory mapped I/O to work and I'm not sure how to do that in
> coreboot.
> Do you (or someone else) think it's a doable way? If so I'll give it a try

Seems doable. You should be able to refer to similar register accesses
in the 8111 code for reference. I assume that there is a way to change
the clocking without needing the watchdog though. The watchdog would
be a failsafe.



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