[coreboot] Patch set updated for coreboot: 3e13da8 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
Florian Zumbiehl
gerrit at coreboot.org
Fri Nov 4 04:48:29 CET 2011
Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/370
-gerrit
commit 3e13da8aa63cd8ec6e4657e7bbc0a23b45a76257
Author: Florian Zumbiehl <florz at florz.de>
Date: Tue Nov 1 20:17:12 2011 +0100
Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
Signed-off-by: Florian Zumbiehl <florz at florz.de>
---
src/northbridge/amd/amdk8/raminit_f.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 319293b..dc3addb 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
18, /* *Supported CAS Latencies */
9, /* *Cycle time at highest CAS Latency CL=X */
23, /* *Cycle time at CAS Latency (CLX - 1) */
- 26, /* *Cycle time at CAS Latency (CLX - 2) */
+ 25, /* *Cycle time at CAS Latency (CLX - 2) */
};
u32 dcl, dcm;
u8 common_cl;
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