[coreboot] Cache-line trouble on Xeon
r.marek at assembler.cz
Tue Nov 8 09:33:02 CET 2011
Just a quick notes. There a peformance MSRs which have L2 fills counters. I did
want to know on AMD how the fills/misses/etc works so I used that counters to
see what is actually going on.
Has a list of events.
> Problem 3: Cache re-allocation policy?
> Cache-lines for the stack must remain in L1 while the XIP ROM lines can
> be thrown out whenever necessary. Generally, do dirty cache-lines remain
> in L1 as long as there are non-dirty cache-lines that require less
> effort to re-allocate?
I think non-dirty stuff which is not modified is just discarded (XIP ROM)or
moved to L2.
The CR.NW mode differs accross Intel CPUs just check documentation what is it
doing in your case (The architecture manuals). To get CAR working I would simply
follow the BIOS with serialICE.
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