From rbyshko at gmail.com  Sun Oct  2 16:10:56 2011
From: rbyshko at gmail.com (Roman B.)
Date: Sun, 2 Oct 2011 16:10:56 +0200
Subject: [coreboot] Support wanted - ASUS P5GD1-VM
Message-ID: <CAMXmWBnxfKqb7PM2To3okMOJOFTqT_5uGecyQOiDD+fJPc4CtQ@mail.gmail.com>

Hi,

I would like to have my motherboad supported. Technical data as asked
on the wiki follows.

1. Motherboad, chipset and CPU
ASUS P5GD1-VM
Northbridge: Intel 915 Graphics Memory Controller Hub (GMCH)
Southbridge: Intel ICH6
Pentium IV 3.0 GHz, Socket LGA 775

2. Please see the output of "lspci -tvnn" attached.

3. Super I/O
On-chip label:
Please see the output of "superiotool -dV" attached.

4: BIOS device
Unfortunately the label of BIOS device cannot be completely read. X -
denotes unreadable text.
BIOS device label:
PMC Flash
XXXXXX
05XXXX
XXXX004T-33JC
Please see the output of "flashrom -V" attached.

5. URL to the mainboard specifications page (optional).
http://dlcdnet.asus.com/pub/ASUS/mb/socket775/P5GD1-VM/e1881_p5gd1-vm.pdf

I am willing to help with development and/or testing. Feel free to contact me.

Best regards
Roman
-------------- next part --------------
flashrom v0.9.4-r1395 on Linux 3.0-ARCH (i686), built with libpci 3.1.7, GCC 4.6.1, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 1 usecs, 1720M loops per second, delay more than 10% too short (got 86% of expected delay), recalculating... 1761M loops per second, delay more than 10% too short (got 88% of expected delay), recalculating... 1725M loops per second, delay more than 10% too short (got 87% of expected delay), recalculating... 1839M loops per second, 10 myus = 9 us, 100 myus = 92 us, 1000 myus = 922 us, 10000 myus = 10903 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "To Be Filled By O.E.M."
DMI string system-product-name: "To Be Filled By O.E.M."
DMI string system-version: "To Be Filled By O.E.M."
DMI string baseboard-manufacturer: "ASUSTeK Computer INC."
DMI string baseboard-product-name: "P5GD1-VM"
DMI string baseboard-version: "Rev 1.xx"
DMI string chassis-type: "<OUT OF SPEC>"
DMI chassis-type is not specific enough.
========================================================================
WARNING! You may be running flashrom on an unsupported laptop. We could
not detect this for sure because your vendor has not setup the SMBIOS
tables correctly. You can enforce execution by adding
'-p internal:laptop=force_I_want_a_brick' to the command line, but
please read the following warning if you are not sure.

Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See http://www.flashrom.org/Laptops for details.

If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Aborting.
-------------- next part --------------
superiotool r6543
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0x4400, id=0x5488
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0x8854, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x164e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for Nuvoton Super I/O at 0x164e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x2e...
  Failed. Returned data: chip_id=0x8854
Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e...
  Failed. Returned data: sid=0xff, id=0x8854, rev=0x00
Probing for Nuvoton Super I/O at 0x4e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x54) at 0x2e
Register dump:
idx 20 21 22 23 24 25 26 27  28 29 2a 2b 2c 2d 2e 2f
val 88 54 ff 00 44 00 00 ff  50 04 00 00 f8 21 00 ff
def 88 MM ff 00 MM 00 MM RR  50 04 00 RR 00 21 00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2  f4 f5
val 00 03 f0 06 02 0e 00 ff  00 00
def 01 03 f0 06 02 8e 00 ff  00 00
LDN 0x01 (Parallel port)
idx 30 60 61 70 74 f0
val 01 03 78 07 03 3a
def 01 03 78 07 04 3f
LDN 0x02 (COM1)
idx 30 60 61 70 f0
val 01 03 f8 04 00
def 01 03 f8 04 00
LDN 0x03 (COM2)
idx 30 60 61 70 f0 f1
val 00 02 f8 03 00 00
def 01 02 f8 03 00 00
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 72 f0
val 01 00 60 00 64 01 0c 83
def 01 00 60 00 64 01 0c 83
LDN 0x06 (Serial flash interface)
idx 30 62 63
val 00 ff ff
def 00 00 00
LDN 0x07 (GPIO 1, GPIO 6, game port, MIDI port)
idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6 f7
val 00 02 01 03 30 00 ff ff  ff ff ff ff ff 00
def 00 02 01 03 30 09 ff 00  00 00 ff 00 00 00
LDN 0x08 (WDTO#, PLED)
idx 30 f5 f6 f7
val 00 ff 00 ff
def 00 00 00 00
LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED)
idx 30 e0 e1 e2 e3 e4 e5 f0  f1 f2 f3 f4 f5 f6 f7
val 08 fe 21 00 ff ff ff ff  ff ff 09 ff ff ff ff
def 00 ff 00 00 ff 00 00 ff  00 00 00 ff 00 00 00
LDN 0x0a (ACPI)
idx 30 70 e0 e1 e2 e3 e4 e5  e6 e7 e8 f2 f3 f4 f6 f7
val 01 00 03 00 ff 01 00 02  00 10 09 7d 00 00 00 00
def 00 00 01 00 ff 08 00 RR  00 00 RR 7c 00 00 00 00
LDN 0x0b (Hardware monitor)
idx 30 60 61 70 f0 f1
val 01 02 90 00 11 1e
def 00 00 00 00 c1 00
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for VIA Super I/O at 0x3f0...
  PCI device 1106:0686 not found.
Probing for Server Engines Super I/O at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xff
-------------- next part --------------
-[0000:00]-+-00.0  Intel Corporation 82915G/P/GV/GL/PL/910GL Memory Controller Hub [8086:2580]
           +-02.0  Intel Corporation 82915G/GV/910GL Integrated Graphics Controller [8086:2582]
           +-02.1  Intel Corporation 82915G Integrated Graphics Controller [8086:2782]
           +-1b.0  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller [8086:2668]
           +-1c.0-[05]--
           +-1c.1-[04]--
           +-1c.2-[03]--
           +-1c.3-[02]--
           +-1d.0  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 [8086:2658]
           +-1d.1  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 [8086:2659]
           +-1d.2  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 [8086:265a]
           +-1d.3  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 [8086:265b]
           +-1d.7  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller [8086:265c]
           +-1e.0-[01]--+-03.0  Integrated Technology Express, Inc. ITE 8211F Single Channel UDMA 133 [1283:8211]
           |            \-08.0  Intel Corporation 82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller [8086:1064]
           +-1f.0  Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge [8086:2640]
           +-1f.1  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller [8086:266f]
           +-1f.2  Intel Corporation 82801FB/FW (ICH6/ICH6W) SATA Controller [8086:2651]
           \-1f.3  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller [8086:266a]

From peter at stuge.se  Sun Oct  2 17:06:38 2011
From: peter at stuge.se (Peter Stuge)
Date: Sun, 2 Oct 2011 17:06:38 +0200
Subject: [coreboot] Support wanted - ASUS P5GD1-VM
In-Reply-To: <CAMXmWBnxfKqb7PM2To3okMOJOFTqT_5uGecyQOiDD+fJPc4CtQ@mail.gmail.com>
References: <CAMXmWBnxfKqb7PM2To3okMOJOFTqT_5uGecyQOiDD+fJPc4CtQ@mail.gmail.com>
Message-ID: <20111002150638.20809.qmail@stuge.se>

Hi Roman,

Roman B. wrote:
> I would like to have my motherboad supported. Technical data as
> asked on the wiki follows.
> 
> 1. Motherboad, chipset and CPU
> ASUS P5GD1-VM
> Northbridge: Intel 915 Graphics Memory Controller Hub (GMCH)

Not exactly supported I think, so adding support for your board will
be a fairly major task. Expect 6-12 months of active work, with lots
of reverse engineering fun.


> I am willing to help with development and/or testing. Feel free to
> contact me.

The way this works is that you do the development and then push
patches into gerrit for review, much like every other open source
project. We are of course happy to help, but you will be the one
doing the work. Feel free to also stop by on IRC to get to know some
developers there. #coreboot on freenode.


Kind regards

//Peter



From r.marek at assembler.cz  Mon Oct  3 08:16:10 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 03 Oct 2011 08:16:10 +0200
Subject: [coreboot] FID/VID change and display flicker
Message-ID: <4E89532A.5060100@assembler.cz>

Hi all,

I finally moved my desktop to the Asrock socket 939 board with 785G/SB700 + 
coreboot. So far even with 6 harddrives and 2GB RAM everything works :)

I only noticed a flicker if CPU freq/voltage changes. I briefly chekced the 
LDTSTOP settings in SB and also in HTIU in NB so far it makes sense. Is it a bug 
or feature? I admit I did not check with original BIOS.

Thanks
Rudolf



From christian.leber at ziti.uni-heidelberg.de  Mon Oct  3 15:19:53 2011
From: christian.leber at ziti.uni-heidelberg.de (christian.leber at ziti.uni-heidelberg.de)
Date: Mon, 03 Oct 2011 15:19:53 +0200
Subject: [coreboot] FID/VID change and display flicker
In-Reply-To: <4E89532A.5060100@assembler.cz>
References: <4E89532A.5060100@assembler.cz>
Message-ID: <20111003151953.x2xq9g1v4s0sco4w@wwwmail.urz.uni-heidelberg.de>

Quoting Rudolf Marek <r.marek at assembler.cz>:

Hello Rudolf

> I only noticed a flicker if CPU freq/voltage changes.

Are you using the on-board video and have you 2 or more screens connected?

Regards
Christian




From svn at coreboot.org  Mon Oct  3 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 03 Oct 2011 16:00:02 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1RAj3q-00084B-DI@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20111003/5a5d3000/attachment.html>

From r.marek at assembler.cz  Mon Oct  3 17:32:12 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 03 Oct 2011 17:32:12 +0200
Subject: [coreboot] FID/VID change and display flicker
In-Reply-To: <20111003151953.x2xq9g1v4s0sco4w@wwwmail.urz.uni-heidelberg.de>
References: <4E89532A.5060100@assembler.cz>
	<20111003151953.x2xq9g1v4s0sco4w@wwwmail.urz.uni-heidelberg.de>
Message-ID: <4E89D57C.2040709@assembler.cz>

 > Are you using the on-board video and have you 2 or more screens 
connected?

Hi,

Yes it is onboard but only one DVI (no dualhead) circa 1920x1200

Thanks
Rudolf




From alperenkose at buyutech.com.tr  Mon Oct  3 18:16:15 2011
From: alperenkose at buyutech.com.tr (=?ISO-8859-1?Q?Alp_Eren_K=F6se?=)
Date: Mon, 3 Oct 2011 19:16:15 +0300
Subject: [coreboot] Coreboot on Axiomtek PICO821
Message-ID: <CAOz08zFfKpUprX76LeO5NCtJUXtgwUG0mxM1FVH_0-5gPv2pEA@mail.gmail.com>

Hello all!

I am new to your list, and I want to install coreboot in a board I own.
I couldn't be sure if it work on it, let me give you the details:

Board Vendor: Axiomtek
Board Name: PICO821
CPU: Intel(R) Atom(TM) CPU Z510   @ 1.10GHz
Chipset: Intel System Controller Hub US15W

The "*lspci -tvnn*" output is attached at the "lspci_output.txt" file.

"*superiotool -dV*" output is attached at "superiotool_output.txt" file.

"*flasrom -V*" output is at "flashrom_output.txt" file.

And this is the URL of the product:
http://axiomtek.com/products/ViewProduct.asp?view=772
also the product manual link is at:
http://www.axiomtek.com/Download/Download/PICO821/PICO821.pdf

Soo that's all, I hope it is possible to flash coreboot on this device, I
would really to have it running, believe it will be much faster to run Linux
on top of it ;)

Thanks,
Regards,
Alp
-------------- next part --------------
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-------------- next part --------------
-[0000:00]-+-00.0  Intel Corporation System Controller Hub (SCH Poulsbo) [8086:8100]
           +-02.0  Intel Corporation System Controller Hub (SCH Poulsbo) Graphics Controller [8086:8108]
           +-1a.0  Intel Corporation System Controller Hub (SCH Poulsbo) USB Client Controller [8086:8118]
           +-1c.0-[01]----00.0  Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168]
           +-1d.0  Intel Corporation System Controller Hub (SCH Poulsbo) USB UHCI #1 [8086:8114]
           +-1d.1  Intel Corporation System Controller Hub (SCH Poulsbo) USB UHCI #2 [8086:8115]
           +-1d.2  Intel Corporation System Controller Hub (SCH Poulsbo) USB UHCI #3 [8086:8116]
           +-1d.7  Intel Corporation System Controller Hub (SCH Poulsbo) USB EHCI #1 [8086:8117]
           +-1f.0  Intel Corporation System Controller Hub (SCH Poulsbo) LPC Bridge [8086:8119]
           \-1f.1  Intel Corporation System Controller Hub (SCH Poulsbo) IDE Controller [8086:811a]
-------------- next part --------------
superiotool r5050
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xc0fe, id=0x4152
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0x5241, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e
Register dump:
idx 02 20 21 22 23 24 25 26  28 29 2a 2b 2c 2e 2f
val ff 52 41 ff fe c0 00 00  00 00 fe c0 ff 00 ff
def 00 52 NA ff 00 MM 00 00  00 00 7c c0 00 00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2  f4 f5
val 00 00 00 00 04 0e 00 ff  00 00
def 01 03 f0 06 02 0e 00 ff  00 00
LDN 0x01 (Parallel port)
idx 30 60 61 70 74 f0
val 00 00 00 00 04 38
def 01 03 78 07 04 3f
LDN 0x02 (COM1)
idx 30 60 61 70 f0
val 01 03 f8 04 00
def 01 03 f8 04 00
LDN 0x03 (COM2)
idx 30 60 61 70 f0 f1
val 00 00 00 00 00 00
def 01 02 f8 03 00 00
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 72 f0
val 01 00 60 00 64 01 00 80
def 01 00 60 00 64 01 0c 80
LDN 0x06 (Consumer IR)
idx 30 60 61 70
val 00 00 00 00
def 00 00 00 00
LDN 0x07 (Game port, MIDI port, GPIO 1)
idx 30 60 61 62 63 70 f0 f1  f2
val 01 00 00 00 00 00 00 ff  00
def 00 02 01 03 30 09 ff 00  00
LDN 0x08 (GPIO 2, watchdog timer)
idx 30 f0 f1 f2 f3 f5 f6 f6  f7
val 00 ff ff ff 00 00 00 00  00
def 00 ff 00 00 00 00 00 00  00
LDN 0x09 (GPIO 3)
idx 30 f0 f1 f2 f3
val 00 ff ff ff 00
def 00 ff 00 00 00
LDN 0x0a (ACPI)
idx 30 70 e0 e1 e2 e3 e4 e5  e6 e7 f0 f1 f3 f4 f6 f7  f9 fe ff
val 00 00 00 00 00 20 00 00  00 00 00 af 32 01 00 00  00 00 00
def 00 00 00 00 NA NA 00 00  00 00 00 00 00 00 00 00  00 00 00
LDN 0x0b (Hardware monitor)
idx 30 60 61 70 f0
val 01 02 90 00 00
def 00 00 00 00 00
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for VIA Super I/O at 0x3f0...
  PCI device 1106:0686 not found.
-------------- next part --------------
flashrom v0.9.2-r1141 on Linux 2.6.38-8-generic-pae (i686), built with libpci 3.1.7, GCC 4.5.1, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 2 usecs, 546M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 997 us, 10000 myus = 10180 us, 8 myus = 9 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: " "
DMI string system-product-name: " "
DMI string system-version: " "
DMI string baseboard-manufacturer: " "
DMI string baseboard-product-name: "POULSBO"
DMI string baseboard-version: " "
DMI string chassis-type: "Desktop"
Found chipset "Intel Poulsbo", enabling flash write... chipset PCI ID is 8086:8119, 
BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0
BIOS Prefetch Enable: enabled, OK.
This chipset supports the following protocols: FWH.
Probing for AMD Am29F010A/B, 128 KB: skipped.
Probing for AMD Am29F002(N)BB, 256 KB: skipped.
Probing for AMD Am29F002(N)BT, 256 KB: skipped.
Probing for AMD Am29F016D, 2048 KB: skipped.
Probing for AMD Am29F040B, 512 KB: skipped.
Probing for AMD Am29F080B, 1024 KB: skipped.
Probing for AMD Am29LV040B, 512 KB: skipped.
Probing for AMD Am29LV081B, 1024 KB: skipped.
Probing for AMIC A25L05PT, 64 KB: skipped.
Probing for AMIC A25L05PU, 64 KB: skipped.
Probing for AMIC A25L10PT, 128 KB: skipped.
Probing for AMIC A25L10PU, 128 KB: skipped.
Probing for AMIC A25L20PT, 256 KB: skipped.
Probing for AMIC A25L20PU, 256 KB: skipped.
Probing for AMIC A25L40PT, 512 KB: skipped.
Probing for AMIC A25L40PU, 512 KB: skipped.
Probing for AMIC A25L80P, 1024 KB: skipped.
Probing for AMIC A25L16PT, 2048 KB: skipped.
Probing for AMIC A25L16PU, 2048 KB: skipped.
Probing for AMIC A25L512, 64 KB: skipped.
Probing for AMIC A25L010, 128 KB: skipped.
Probing for AMIC A25L020, 256 KB: skipped.
Probing for AMIC A25L040, 512 KB: skipped.
Probing for AMIC A25L080, 1024 KB: skipped.
Probing for AMIC A25L016, 2048 KB: skipped.
Probing for AMIC A25L032, 4096 KB: skipped.
Probing for AMIC A25LQ032, 4096 KB: skipped.
Probing for AMIC A29002B, 256 KB: skipped.
Probing for AMIC A29002T, 256 KB: skipped.
Probing for AMIC A29040B, 512 KB: skipped.
Probing for AMIC A49LF040A, 512 KB: skipped.
Probing for ASD AE49F2008, 256 KB: skipped.
Probing for Atmel AT25DF021, 256 KB: skipped.
Probing for Atmel AT25DF041A, 512 KB: skipped.
Probing for Atmel AT25DF081, 1024 KB: skipped.
Probing for Atmel AT25DF081A, 1024 KB: skipped.
Probing for Atmel AT25DF161, 2048 KB: skipped.
Probing for Atmel AT25DF321, 4096 KB: skipped.
Probing for Atmel AT25DF321A, 4096 KB: skipped.
Probing for Atmel AT25DF641, 8192 KB: skipped.
Probing for Atmel AT25DQ161, 2048 KB: skipped.
Probing for Atmel AT25F512B, 64 KB: skipped.
Probing for Atmel AT25FS010, 128 KB: skipped.
Probing for Atmel AT25FS040, 512 KB: skipped.
Probing for Atmel AT26DF041, 512 KB: skipped.
Probing for Atmel AT26DF081A, 1024 KB: skipped.
Probing for Atmel AT26DF161, 2048 KB: skipped.
Probing for Atmel AT26DF161A, 2048 KB: skipped.
Probing for Atmel AT26F004, 512 KB: skipped.
Probing for Atmel AT29C512, 64 KB: skipped.
Probing for Atmel AT29C010A, 128 KB: skipped.
Probing for Atmel AT29C020, 256 KB: skipped.
Probing for Atmel AT29C040A, 512 KB: skipped.
Probing for Atmel AT45CS1282, 16896 KB: skipped.
Probing for Atmel AT45DB011D, 128 KB: skipped.
Probing for Atmel AT45DB021D, 256 KB: skipped.
Probing for Atmel AT45DB041D, 512 KB: skipped.
Probing for Atmel AT45DB081D, 1024 KB: skipped.
Probing for Atmel AT45DB161D, 2048 KB: skipped.
Probing for Atmel AT45DB321C, 4224 KB: skipped.
Probing for Atmel AT45DB321D, 4096 KB: skipped.
Probing for Atmel AT45DB642D, 8192 KB: skipped.
Probing for Atmel AT49BV512, 64 KB: skipped.
Probing for Atmel AT49F020, 256 KB: skipped.
Probing for Atmel AT49F002(N), 256 KB: skipped.
Probing for Atmel AT49F002(N)T, 256 KB: skipped.
Probing for EMST F49B002UA, 256 KB: skipped.
Probing for EMST F25L008A, 1024 KB: skipped.
Probing for Eon EN25B05, 64 KB: skipped.
Probing for Eon EN25B05T, 64 KB: skipped.
Probing for Eon EN25B10, 128 KB: skipped.
Probing for Eon EN25B10T, 128 KB: skipped.
Probing for Eon EN25B20, 256 KB: skipped.
Probing for Eon EN25B20T, 256 KB: skipped.
Probing for Eon EN25B40, 512 KB: skipped.
Probing for Eon EN25B40T, 512 KB: skipped.
Probing for Eon EN25B80, 1024 KB: skipped.
Probing for Eon EN25B80T, 1024 KB: skipped.
Probing for Eon EN25B16, 2048 KB: skipped.
Probing for Eon EN25B16T, 2048 KB: skipped.
Probing for Eon EN25B32, 4096 KB: skipped.
Probing for Eon EN25B32T, 4096 KB: skipped.
Probing for Eon EN25B64, 8192 KB: skipped.
Probing for Eon EN25B64T, 8192 KB: skipped.
Probing for Eon EN25D16, 2048 KB: skipped.
Probing for Eon EN25F05, 64 KB: skipped.
Probing for Eon EN25F10, 128 KB: skipped.
Probing for Eon EN25F20, 256 KB: skipped.
Probing for Eon EN25F40, 512 KB: skipped.
Probing for Eon EN25F80, 1024 KB: skipped.
Probing for Eon EN25F16, 2048 KB: skipped.
Probing for Eon EN25F32, 4096 KB: skipped.
Probing for Eon EN29F010, 128 KB: skipped.
Probing for Eon EN29F002(A)(N)B, 256 KB: skipped.
Probing for Eon EN29F002(A)(N)T, 256 KB: skipped.
Probing for Fujitsu MBM29F004BC, 512 KB: skipped.
Probing for Fujitsu MBM29F004TC, 512 KB: skipped.
Probing for Fujitsu MBM29F400BC, 512 KB: skipped.
Probing for Fujitsu MBM29F400TC, 512 KB: skipped.
Probing for Hyundai HY29F002T, 256 KB: skipped.
Probing for Hyundai HY29F002B, 256 KB: skipped.
Probing for Intel 28F001BX-B, 128 KB: skipped.
Probing for Intel 28F001BX-T, 128 KB: skipped.
Probing for Intel 28F002BC-T, 256 KB: skipped.
Probing for Intel 28F004S5, 512 KB: skipped.
Probing for Intel 28F004BV/BE-B, 512 KB: skipped.
Probing for Intel 28F004BV/BE-T, 512 KB: skipped.
Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped.
Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped.
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x90, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Macronix MX25L512, 64 KB: skipped.
Probing for Macronix MX25L1005, 128 KB: skipped.
Probing for Macronix MX25L2005, 256 KB: skipped.
Probing for Macronix MX25L4005, 512 KB: skipped.
Probing for Macronix MX25L8005, 1024 KB: skipped.
Probing for Macronix MX25L1605, 2048 KB: skipped.
Probing for Macronix MX25L1635D, 2048 KB: skipped.
Probing for Macronix MX25L3205, 4096 KB: skipped.
Probing for Macronix MX25L3235D, 4096 KB: skipped.
Probing for Macronix MX25L6405, 8192 KB: skipped.
Probing for Macronix MX25L12805, 16384 KB: skipped.
Probing for Macronix MX29F001B, 128 KB: skipped.
Probing for Macronix MX29F001T, 128 KB: skipped.
Probing for Macronix MX29F002B, 256 KB: skipped.
Probing for Macronix MX29F002T, 256 KB: skipped.
Probing for Macronix MX29LV040, 512 KB: skipped.
Probing for MoselVitelic V29C51000B, 64 KB: skipped.
Probing for MoselVitelic V29C51000T, 64 KB: skipped.
Probing for MoselVitelic V29C51400B, 512 KB: skipped.
Probing for MoselVitelic V29C51400T, 512 KB: skipped.
Probing for MoselVitelic V29LC51000, 64 KB: skipped.
Probing for MoselVitelic V29LC51001, 128 KB: skipped.
Probing for MoselVitelic V29LC51002, 256 KB: skipped.
Probing for Numonyx M25PE10, 128 KB: skipped.
Probing for Numonyx M25PE20, 256 KB: skipped.
Probing for Numonyx M25PE40, 512 KB: skipped.
Probing for Numonyx M25PE80, 1024 KB: skipped.
Probing for Numonyx M25PE16, 2048 KB: skipped.
Probing for PMC Pm25LV010, 128 KB: skipped.
Probing for PMC Pm25LV016B, 2048 KB: skipped.
Probing for PMC Pm25LV020, 256 KB: skipped.
Probing for PMC Pm25LV040, 512 KB: skipped.
Probing for PMC Pm25LV080B, 1024 KB: skipped.
Probing for PMC Pm25LV512, 64 KB: skipped.
Probing for PMC Pm29F002T, 256 KB: skipped.
Probing for PMC Pm29F002B, 256 KB: skipped.
Probing for PMC Pm39LV010, 128 KB: skipped.
Probing for PMC Pm39LV020, 256 KB: skipped.
Probing for PMC Pm39LV040, 512 KB: skipped.
Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5a
Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5a
Probing for Sanyo LF25FW203A, 2048 KB: skipped.
Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0x90, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Spansion S25FL008A, 1024 KB: skipped.
Probing for Spansion S25FL016A, 2048 KB: skipped.
Probing for SST SST25VF016B, 2048 KB: skipped.
Probing for SST SST25VF032B, 4096 KB: skipped.
Probing for SST SST25VF064C, 8192 KB: skipped.
Probing for SST SST25VF040.REMS, 512 KB: skipped.
Probing for SST SST25VF040B, 512 KB: skipped.
Probing for SST SST25LF040A.RES, 512 KB: skipped.
Probing for SST SST25VF040B.REMS, 512 KB: skipped.
Probing for SST SST25VF080B, 1024 KB: skipped.
Probing for SST SST28SF040A, 512 KB: skipped.
Probing for SST SST29EE010, 128 KB: skipped.
Probing for SST SST29LE010, 128 KB: skipped.
Probing for SST SST29EE020A, 256 KB: skipped.
Probing for SST SST29LE020, 256 KB: skipped.
Probing for SST SST39SF512, 64 KB: skipped.
Probing for SST SST39SF010A, 128 KB: skipped.
Probing for SST SST39SF020A, 256 KB: skipped.
Probing for SST SST39SF040, 512 KB: skipped.
Probing for SST SST39VF512, 64 KB: skipped.
Probing for SST SST39VF010, 128 KB: skipped.
Probing for SST SST39VF020, 256 KB: skipped.
Probing for SST SST39VF040, 512 KB: skipped.
Probing for SST SST39VF080, 1024 KB: skipped.
Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5a
Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xbf, id2 0x5a
Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5a
Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xbf, id2 0x5a
Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address 0xfff00000.
Lock status for 0x000000 (size 0x010000) is 01, write locked
Lock status for 0x010000 (size 0x010000) is 01, write locked
Lock status for 0x020000 (size 0x010000) is 01, write locked
Lock status for 0x030000 (size 0x010000) is 01, write locked
Lock status for 0x040000 (size 0x010000) is 01, write locked
Lock status for 0x050000 (size 0x010000) is 01, write locked
Lock status for 0x060000 (size 0x010000) is 01, write locked
Lock status for 0x070000 (size 0x010000) is 01, write locked
Lock status for 0x080000 (size 0x010000) is 01, write locked
Lock status for 0x090000 (size 0x010000) is 01, write locked
Lock status for 0x0a0000 (size 0x010000) is 01, write locked
Lock status for 0x0b0000 (size 0x010000) is 01, write locked
Lock status for 0x0c0000 (size 0x010000) is 01, write locked
Lock status for 0x0d0000 (size 0x010000) is 01, write locked
Lock status for 0x0e0000 (size 0x010000) is 01, write locked
Lock status for 0x0f0000 (size 0x010000) is 01, write locked
Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0x90, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF020, 256 KB: skipped.
Probing for SST SST49LF020A, 256 KB: skipped.
Probing for SST SST49LF040, 512 KB: skipped.
Probing for SST SST49LF040B, 512 KB: skipped.
Probing for SST SST49LF080A, 1024 KB: skipped.
Probing for SST SST49LF160C, 2048 KB: skipped.
Probing for ST M25P05-A, 64 KB: skipped.
Probing for ST M25P05.RES, 64 KB: skipped.
Probing for ST M25P10-A, 128 KB: skipped.
Probing for ST M25P10.RES, 128 KB: skipped.
Probing for ST M25P20, 256 KB: skipped.
Probing for ST M25P40, 512 KB: skipped.
Probing for ST M25P40-old, 512 KB: skipped.
Probing for ST M25P80, 1024 KB: skipped.
Probing for ST M25P16, 2048 KB: skipped.
Probing for ST M25P32, 4096 KB: skipped.
Probing for ST M25P64, 8192 KB: skipped.
Probing for ST M25P128, 16384 KB: skipped.
Probing for ST M29F002B, 256 KB: skipped.
Probing for ST M29F002T/NT, 256 KB: skipped.
Probing for ST M29F040B, 512 KB: skipped.
Probing for ST M29F400BB, 512 KB: skipped.
Probing for ST M29F400BT, 512 KB: skipped.
Probing for ST M29W010B, 128 KB: skipped.
Probing for ST M29W040B, 512 KB: skipped.
Probing for ST M29W512B, 64 KB: skipped.
Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x90, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x90, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x90, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50LPW116, 2048 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped.
Probing for TI TMS29F002RB, 256 KB: skipped.
Probing for TI TMS29F002RT, 256 KB: skipped.
Probing for Winbond W25Q80, 1024 KB: skipped.
Probing for Winbond W25Q16, 2048 KB: skipped.
Probing for Winbond W25Q32, 4096 KB: skipped.
Probing for Winbond W25Q64, 8192 KB: skipped.
Probing for Winbond W25x10, 128 KB: skipped.
Probing for Winbond W25x20, 256 KB: skipped.
Probing for Winbond W25x40, 512 KB: skipped.
Probing for Winbond W25x80, 1024 KB: skipped.
Probing for Winbond W25x16, 2048 KB: skipped.
Probing for Winbond W25x32, 4096 KB: skipped.
Probing for Winbond W25x64, 8192 KB: skipped.
Probing for Winbond W29C011, 128 KB: skipped.
Probing for Winbond W29C020C, 256 KB: skipped.
Probing for Winbond W29C040P, 512 KB: skipped.
Probing for Winbond W29EE011, 128 KB: skipped.
Probing for Winbond W39V040A, 512 KB: skipped.
Probing for Winbond W39V040B, 512 KB: skipped.
Probing for Winbond W39V040C, 512 KB: skipped.
Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5a
Probing for Winbond W39V080A, 1024 KB: skipped.
Probing for Winbond W49F002U, 256 KB: skipped.
Probing for Winbond W49F020, 256 KB: skipped.
Probing for Winbond W49V002A, 256 KB: skipped.
Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5a
Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5a
Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5a
Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped.
Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped.
Probing for Eon unknown Eon SPI chip, 0 KB: skipped.
Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped.
Probing for PMC unknown PMC SPI chip, 0 KB: skipped.
Probing for SST unknown SST SPI chip, 0 KB: skipped.
Probing for ST unknown ST SPI chip, 0 KB: skipped.
Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped.
Probing for Generic unknown SPI chip (RDID), 0 KB: skipped.
Probing for Generic unknown SPI chip (REMS), 0 KB: skipped.
No operations were specified.

From gerrit at coreboot.org  Mon Oct  3 23:17:34 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 3 Oct 2011 23:17:34 +0200
Subject: [coreboot] Patch merged into coreboot/master: aeaa118
	TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms
References: <I74fb892aa39048e2d0e76c081b713f825d67f2d4+0@gerrit.coreboot.org>
Message-ID: <E1RAptG-00007w-AQ@ra.coresystems.de>

the following patch was just integrated into master:
commit aeaa1183df0952e99232a335524191225d2ecef4
Author: enok71 <enok at lysator.liu.se>
Date:   Wed Sep 28 16:55:59 2011 +0200

    TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms
    
    The hp/dl145_g1 motherboard did not work since commit
    1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That commit added
    TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process
    stopped very early (no console output whatsoever). The same symptom was
    reported on other AMDK8 based boards with amd8111 southbridge chips. This
    commit seems to fix the bug. It adds a bootblock.c under
    src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the
    problem was that enum_ht_chains needs to be called before the southbridge
    bootblock.c function, not after.
    
    Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>

See http://review.coreboot.org/235 for details.

-gerrit



From gerrit at coreboot.org  Mon Oct  3 23:27:28 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 3 Oct 2011 23:27:28 +0200
Subject: [coreboot] Patch merged into coreboot/master: 56d8c3c pci_ids: Add
	sb800 SATA device raid mode device id
References: <If54f7751f531c94ee725309a2a5c255390935ead+0@gerrit.coreboot.org>
Message-ID: <E1RAq2q-0000y4-Rb@ra.coresystems.de>

the following patch was just integrated into master:
commit 56d8c3cff880c65c5c839b56c68fc63891ebec06
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Sep 22 18:52:35 2011 +0800

    pci_ids: Add sb800 SATA device raid mode device id
    
    sb800 SATA device have different device id with different configure
    mode, 4392h for RAID mode, 4393h for RAID5 mode
    
    Change-Id: If54f7751f531c94ee725309a2a5c255390935ead
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>

See http://review.coreboot.org/226 for details.

-gerrit



From mopz0506 at gmail.com  Tue Oct  4 04:21:31 2011
From: mopz0506 at gmail.com (mopz0506 mopz0506)
Date: Tue, 4 Oct 2011 10:21:31 +0800
Subject: [coreboot] patch to display ASRock E350M1 freq correctly
Message-ID: <CADBhXUT1aigKywuBhrnzeF+-xiah1_0G2pVG6Rmgjm-hqXNZ8Q@mail.gmail.com>

Morning All,

I'm not native speaker and sorry for my English.

I heard about Coreboot since it has named LinuxBIOS
but never own a mainboard supported.

I bought a E350M1 after found it listed in supported
mainboard (thank you Scott, thank you AMD)

Once linux up, the cpu freq. is 2800 MHz for P0,
1400 MHz for P1.

In E350M1 status page, "CPU frequency scaling" keep
"CPU might report (or have) wrong frequency. " for
a while and seems no one cares about it.

I run a benchmark and seems CPU runs on correct freq.,
and it just display wrong number (which coreboot sent to
linux kernel).

Finally I think maybe I can fix it myself and start
digging ACPI and source code.

so attached is a trival patch to display the true
freq. of CPU, 1600 MHz for P0, 800 MHz for P1.

the setting runs on my E350M1 for 3 weeks and looks OK.

the persimmon uses the wrong setting too. but it declares
"CPU frequency scaling" is "OK". I don't know why.

Thanks and Regards,

mopz0506
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From r.marek at assembler.cz  Tue Oct  4 09:38:21 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 04 Oct 2011 09:38:21 +0200
Subject: [coreboot] patch to display ASRock E350M1 freq correctly
In-Reply-To: <CADBhXUT1aigKywuBhrnzeF+-xiah1_0G2pVG6Rmgjm-hqXNZ8Q@mail.gmail.com>
References: <CADBhXUT1aigKywuBhrnzeF+-xiah1_0G2pVG6Rmgjm-hqXNZ8Q@mail.gmail.com>
Message-ID: <4E8AB7ED.1070802@assembler.cz>

Hi all,

> I'm not native speaker and sorry for my English.

Yep me too ;) But your doing OK we can understand what you wrote.

> Finally I think maybe I can fix it myself and start
> digging ACPI and source code.

I'm quite surprised that this is hardcoded. We used to have a functions
which place it there runtime depending on CPU model. I don't know
why it is hardcoded here. I think a proper fix would be to provide that runtime 
depending on CPU. Maybe AGESA has some infrastructure for that. Did not check so 
far.

Thanks
Rudolf



From enok at lysator.liu.se  Tue Oct  4 15:14:18 2011
From: enok at lysator.liu.se (Oskar Enoksson)
Date: Tue, 04 Oct 2011 15:14:18 +0200
Subject: [coreboot] "WARNING: BIOS bug: CPU MTRRs don't cover all of memory"
 loosing 2048MB of ram
Message-ID: <4E8B06AA.6080007@lysator.liu.se>

I incidently put 5GB RAM in my hp/dl145_g1 motherboard (2x1g+6x512m) and 
got the following error from Linux when booting:

"WARNING: BIOS bug: CPU MTRRs don't cover all of memory" loosing 2048MB 
of ram

(The dl145_g1 is a dual-socket amdk8 board with four DIMM's per CPU socket).

After digging around in the coreboot code I noticed that if I changed 
the last line in src/amd/amd_mtrr.c the generated MTRR was correct and 
the problem was solved:

     /* Now that I have mapped what is memory and what is not
      * Setup the mtrrs so we can cache the memory.
      */
-    x86_setup_var_mtrrs(address_bits, 0);
+    x86_setup_var_mtrrs(address_bits, 1);

In cpu/x86/mtrr/mtrr.c the comments explains the last parameter in great 
detail:

void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
/* this routine needs to know how many address bits a given processor
  * supports.  CPUs get grumpy when you set too many bits in
  * their mtrr registers :(  I would generically call cpuid here
  * and find out how many physically supported but some cpus are
  * buggy, and report more bits then they actually support.
  * If above4gb flag is set, variable MTRR ranges must be used to
  * set cacheability of DRAM above 4GB. If above4gb flag is clear,
  * some other mechanism is controlling cacheability of DRAM above 4GB.
  */

So - what "some other mechanism" is assumed to work on AMD cpu's and 
what should I do to make it work?

The patch described in 
http://www.coreboot.org/pipermail/coreboot/attachments/20101111/7eff5b02/attachment-0001.txt 
by Scott Duplichan tries to explain something, but I'm still not sure 
what to do.





From marcj303 at gmail.com  Tue Oct  4 18:24:53 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 4 Oct 2011 10:24:53 -0600
Subject: [coreboot] patch to display ASRock E350M1 freq correctly
In-Reply-To: <4E8AB7ED.1070802@assembler.cz>
References: <CADBhXUT1aigKywuBhrnzeF+-xiah1_0G2pVG6Rmgjm-hqXNZ8Q@mail.gmail.com>
	<4E8AB7ED.1070802@assembler.cz>
Message-ID: <CALrs_3jDKpRkiML8At=G-MqY8w98hnBPm9DC0yTxm_mkqtC80w@mail.gmail.com>

On Tue, Oct 4, 2011 at 1:38 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
> Hi all,
>
>> I'm not native speaker and sorry for my English.
>
> Yep me too ;) But your doing OK we can understand what you wrote.
>
>> Finally I think maybe I can fix it myself and start
>> digging ACPI and source code.
>
> I'm quite surprised that this is hardcoded. We used to have a functions
> which place it there runtime depending on CPU model. I don't know
> why it is hardcoded here. I think a proper fix would be to provide that
> runtime depending on CPU. Maybe AGESA has some infrastructure for that. Did
> not check so far.
>
> Thanks
> Rudolf

This should be generated by the AMDInitLate call, which needs some
work in coreboot acpi/agesa wrappers. Feel free to check out the
tables that are generated and look at how they should be integrated.

Marc



-- 
http://se-eng.com



From enok at lysator.liu.se  Tue Oct  4 18:37:22 2011
From: enok at lysator.liu.se (Oskar Enoksson)
Date: Tue, 04 Oct 2011 18:37:22 +0200
Subject: [coreboot] git/gerrit question
In-Reply-To: <4E8B2810.6060307@lysator.liu.se>
References: <gerrit.1317223000146.I74fb892aa39048e2d0e76c081b713f825d67f2d4@review.coreboot.org>
	<20110928155023.45F364002F@mail.lysator.liu.se>
	<4E834487.3060404@lysator.liu.se> <4E8B2520.8040709@lysator.liu.se>
	<4E8B2810.6060307@lysator.liu.se>
Message-ID: <4E8B3642.6080200@lysator.liu.se>

I'm trying to upload a patch. It seems that for some reason "gerrit" 
requires a "signed-off-by" line in every single local commit in order to 
push it to the remote location. I'm able to "amend" such a line to the 
very last commit, but I can't find a way to do it on the previous 
commits. How can I do it? I've googled the web, browsed the manuals, 
scimmed through the tutorials and found no clue. Do I have to start from 
scratch?




From marcj303 at gmail.com  Tue Oct  4 18:45:57 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 4 Oct 2011 10:45:57 -0600
Subject: [coreboot] "WARNING: BIOS bug: CPU MTRRs don't cover all of
 memory" loosing 2048MB of ram
In-Reply-To: <4E8B06AA.6080007@lysator.liu.se>
References: <4E8B06AA.6080007@lysator.liu.se>
Message-ID: <CALrs_3jWuwKh1b_dkj-tEsXf9RPL3WnSFo3MTe074bdxSwSWqQ@mail.gmail.com>

On Tue, Oct 4, 2011 at 7:14 AM, Oskar Enoksson <enok at lysator.liu.se> wrote:
> I incidently put 5GB RAM in my hp/dl145_g1 motherboard (2x1g+6x512m) and got
> the following error from Linux when booting:
>
> "WARNING: BIOS bug: CPU MTRRs don't cover all of memory" loosing 2048MB of
> ram
>
> (The dl145_g1 is a dual-socket amdk8 board with four DIMM's per CPU socket).
>
> After digging around in the coreboot code I noticed that if I changed the
> last line in src/amd/amd_mtrr.c the generated MTRR was correct and the
> problem was solved:
>
> ? ?/* Now that I have mapped what is memory and what is not
> ? ? * Setup the mtrrs so we can cache the memory.
> ? ? */
> - ? ?x86_setup_var_mtrrs(address_bits, 0);
> + ? ?x86_setup_var_mtrrs(address_bits, 1);
>
> In cpu/x86/mtrr/mtrr.c the comments explains the last parameter in great
> detail:
>
> void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
> /* this routine needs to know how many address bits a given processor
> ?* supports. ?CPUs get grumpy when you set too many bits in
> ?* their mtrr registers :( ?I would generically call cpuid here
> ?* and find out how many physically supported but some cpus are
> ?* buggy, and report more bits then they actually support.
> ?* If above4gb flag is set, variable MTRR ranges must be used to
> ?* set cacheability of DRAM above 4GB. If above4gb flag is clear,
> ?* some other mechanism is controlling cacheability of DRAM above 4GB.
> ?*/
>
> So - what "some other mechanism" is assumed to work on AMD cpu's and what
> should I do to make it work?
>
> The patch described in
> http://www.coreboot.org/pipermail/coreboot/attachments/20101111/7eff5b02/attachment-0001.txt
> by Scott Duplichan tries to explain something, but I'm still not sure what
> to do.

The Fam10 and K8 have the AMD Tom2ForceMemTypeWB feature to avoid the
need for  variable MTRR ranges above 4GB. Either that isn't being set
on your platform or your kernel is misreporting because it doesn't
know about the feature.

Marc



-- 
http://se-eng.com



From christophg+cb at grenz-bonn.de  Tue Oct  4 18:51:39 2011
From: christophg+cb at grenz-bonn.de (Christoph Grenz)
Date: Tue, 4 Oct 2011 18:51:39 +0200
Subject: [coreboot] git/gerrit question
In-Reply-To: <4E8B3642.6080200@lysator.liu.se>
References: <gerrit.1317223000146.I74fb892aa39048e2d0e76c081b713f825d67f2d4@review.coreboot.org>
	<4E8B2810.6060307@lysator.liu.se> <4E8B3642.6080200@lysator.liu.se>
Message-ID: <201110041851.39782.christophg+cb@grenz-bonn.de>

Use git rebase -i HEAD~X (with X = the number of commits you want to change)
or git rebase -i master (all commits since last pull/push)

Then you can reorder commits, merge multiple commits into one (fixup, this 
might be what you want), and change every commit message (reword).

See also: http://www.coreboot.org/Git#Evolving_patches

Am Dienstag, 4. Oktober 2011, um 18:37:22 schrieb Oskar Enoksson:
> I'm trying to upload a patch. It seems that for some reason "gerrit"
> requires a "signed-off-by" line in every single local commit in order to
> push it to the remote location. I'm able to "amend" such a line to the
> very last commit, but I can't find a way to do it on the previous
> commits. How can I do it? I've googled the web, browsed the manuals,
> scimmed through the tutorials and found no clue. Do I have to start from
> scratch?



From peter at stuge.se  Tue Oct  4 19:06:07 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 4 Oct 2011 19:06:07 +0200
Subject: [coreboot] git/gerrit question
In-Reply-To: <4E8B3642.6080200@lysator.liu.se>
References: <gerrit.1317223000146.I74fb892aa39048e2d0e76c081b713f825d67f2d4@review.coreboot.org>
	<20110928155023.45F364002F@mail.lysator.liu.se>
	<4E834487.3060404@lysator.liu.se> <4E8B2520.8040709@lysator.liu.se>
	<4E8B2810.6060307@lysator.liu.se> <4E8B3642.6080200@lysator.liu.se>
Message-ID: <20111004170607.6000.qmail@stuge.se>

Hi,

Oskar Enoksson wrote:
> I'm trying to upload a patch. It seems that for some reason
> "gerrit" requires a "signed-off-by" line in every single local
> commit in order to push it to the remote location.

More background at
http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure


> I'm able to "amend" such a line to the very last commit, but I
> can't find a way to do it on the previous commits. How can I do it?
..
> Do I have to start from scratch?

Not at all. You'll use the git feature called interactive rebase, to
rewrite your history. I recommend reading man git-rebase under
"INTERACTIVE MODE" and/or http://progit.org/book/ch6-4.html for good
descriptions of how this works.

You run git rebase -i commithash_before_the_first_you_want_to_change
and get an editor where you first create a script for git telling it
what to do for each commit following the commit you specified.
Default is to pick every commit unchanged. Change pick to edit, or
simply e, for each line, save and exit. git rolls back history,
applies the first commit, and exits to a shell. You can now git
commit --amend -s -C HEAD to amend that commit to include a signoff.

Remember to configure your user name and email address in git first:
git config --global user.name 'Oskar Enoksson'
git config --global user.email your at email.here

If you had not done this before committing the first time, then you
should also add --author='Oskar Enoksson <your at email.here>' to the
git commit --amend -s -C HEAD command, in order to also fix the
authorship information while you are iterating over the patches
anyway. Use git show to review the commit. Then run
git rebase --continue

to have git perform the next command in the rebase script you created
at the beginning. Once you've iterated over all commits git should
report success.


Note that when a branch with multiple commits which gerrit has not
seen is pushed to gerrit, gerrit interprets this to mean that the
commits in this branch all belong together as one unity, there is a
dependence documented for each commit. This is not a hard dependency,
the commits can also be included in the public repo out of order from
gerrit, but for maximum clarity it is better to push independent
patches separately, e.g. by having different branches locally, based
on the current public repo and with just one new commit on each. It's
not a too big deal if this should end up wrong in gerrit, especially
on the first push, but keep it in mind for the future if there are
independent commits. (This is just a note, I don't know if you do
have independent commits or not.)


Hope this helps

//Peter



From gerrit at coreboot.org  Tue Oct  4 19:24:59 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Tue, 4 Oct 2011 19:24:59 +0200
Subject: [coreboot] New patch to review for coreboot: 37e4516 Added
	RAMINIT_SYSINFO. Also re-generated irq_tables.c
References: <Ie90a134a1efc9605b3fe17a5b5008856226984be+0@gerrit.coreboot.org>
Message-ID: <Ie90a134a1efc9605b3fe17a5b5008856226984be+1@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/236

-gerrit

commit 37e4516ea19db743daa0142ea00933586100bea5
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Tue Oct 4 16:31:20 2011 +0200

    Added RAMINIT_SYSINFO. Also re-generated irq_tables.c
    
    Signed-off-by: enok71 <enok at lysator.liu.se>
    Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be
---
 src/mainboard/hp/dl145_g1/Kconfig        |    1 +
 src/mainboard/hp/dl145_g1/get_bus_conf.c |   55 ++++-----
 src/mainboard/hp/dl145_g1/irq_tables.c   |  148 ++++++++-----------------
 src/mainboard/hp/dl145_g1/mb_sysconf.h   |   33 ++++++
 src/mainboard/hp/dl145_g1/mptable.c      |   37 +++----
 src/mainboard/hp/dl145_g1/romstage.c     |  177 +++++++++++++++---------------
 6 files changed, 208 insertions(+), 243 deletions(-)

diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig
index eb90b07..ebd7ffd 100644
--- a/src/mainboard/hp/dl145_g1/Kconfig
+++ b/src/mainboard/hp/dl145_g1/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
+	select RAMINIT_SYSINFO
 #	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select QRANK_DIMM_SUPPORT
 
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
index e4721ce..8fb52bd 100644
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -9,20 +9,12 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 #include <stdlib.h>
-
+#include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_8131_0 = 1;
-unsigned char bus_8131_1 = 2;
-unsigned char bus_8131_2 = 3;
-unsigned char bus_8111_0 = 1;
-unsigned char bus_8111_1 = 4;
-unsigned apicid_8111 ;
-unsigned apicid_8131_1;
-unsigned apicid_8131_2;
-
-unsigned pci1234x[] =
+struct mb_sysconf_t mb_sysconf;
+
+static unsigned pci1234x[] =
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
 	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
@@ -34,7 +26,7 @@ unsigned pci1234x[] =
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] =
+static unsigned hcdnx[] =
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
 	0x20202020,
 //	0x20202020,
@@ -45,8 +37,6 @@ unsigned hcdnx[] =
 //        0x20202020,
 //        0x20202020,
 };
-unsigned sbdn3;
-
 
 
 static unsigned get_bus_conf_done = 0;
@@ -58,11 +48,16 @@ void get_bus_conf(void)
 
         device_t dev;
         int i;
+	struct mb_sysconf_t *m;
 
         if(get_bus_conf_done==1) return; //do it only once
 
         get_bus_conf_done = 1;
 
+	sysconf.mb = &mb_sysconf;
+
+	m = sysconf.mb;
+
         sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
@@ -72,36 +67,36 @@ void get_bus_conf(void)
         get_sblk_pci1234();
 
 	sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
-	sbdn3 = sysconf.hcdn[0] & 0xff;
+	m->sbdn3 = sysconf.hcdn[0] & 0xff;
 
-	bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
-	bus_8111_0 = bus_8131_0;
+	m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
+	m->bus_8111_0 = m->bus_8131_0;
 
                 /* 8111 */
-        dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
+        dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
         if (dev) {
-                bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	        m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
 	else {
-                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0);
         }
 
         /* 8131-1 */
-        dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
+        dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0));
         if (dev) {
-                bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
         else {
-                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0);
         }
 
         /* 8132-2 */
-        dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
+        dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0));
         if (dev) {
-                bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
         else {
-                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0);
         }
 
 
@@ -111,7 +106,7 @@ void get_bus_conf(void)
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
-	apicid_8111 = apicid_base+0;
-	apicid_8131_1 = apicid_base+1;
-	apicid_8131_2 = apicid_base+2;
+	m->apicid_8111 = apicid_base+0;
+	m->apicid_8131_1 = apicid_base+1;
+	m->apicid_8131_2 = apicid_base+2;
 }
diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c
index b53a992..cd5e5a7 100644
--- a/src/mainboard/hp/dl145_g1/irq_tables.c
+++ b/src/mainboard/hp/dl145_g1/irq_tables.c
@@ -1,107 +1,55 @@
-/* This file was generated by getpir.c, do not modify!
-   (but if you do, please run checkpir on it to verify)
-   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Oskar Enoksson <enok at lysator.liu.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
-   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
 #include <arch/pirq_routing.h>
 
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
-		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
-		uint8_t slot, uint8_t rfu)
-{
-        pirq_info->bus = bus;
-        pirq_info->devfn = devfn;
-                pirq_info->irq[0].link = link0;
-                pirq_info->irq[0].bitmap = bitmap0;
-                pirq_info->irq[1].link = link1;
-                pirq_info->irq[1].bitmap = bitmap1;
-                pirq_info->irq[2].link = link2;
-                pirq_info->irq[2].bitmap = bitmap2;
-                pirq_info->irq[3].link = link3;
-                pirq_info->irq[3].bitmap = bitmap3;
-        pirq_info->slot = slot;
-        pirq_info->rfu = rfu;
-}
-
-extern  unsigned char bus_8131_0;
-extern  unsigned char bus_8131_1;
-extern  unsigned char bus_8131_2;
-extern  unsigned char bus_8111_0;
-extern  unsigned char bus_8111_1;
-
-extern  unsigned sbdn3;
-
-
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 9,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x07 << 3) | 0x3,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x1022,			/* Vendor */
+	0x746b,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x2d,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x07 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x0, 0x0},
+		{0x01, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0xdef8}}, 0x0, 0x0},
+		{0x01, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x03, (0x01 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0},
+		{0x03, (0x02 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x4, 0x0},
+		{0x01, (0x04 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0},
+		{0x02, (0x03 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x02, (0x01 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x03, (0x03 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}}, 0x3, 0x0},
+	}
+};
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	unsigned slot_num;
-	uint8_t *v;
-
-        uint8_t sum=0;
-        int i;
-
-	get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-
-        /* Align the table to be 16 byte aligned. */
-        addr += 15;
-        addr &= ~15;
-
-        /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (uint8_t *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version  = PIRQ_VERSION;
-
-	pirq->rtr_bus = bus_8111_0;
-	pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1022;
-	pirq->rtr_device = 0x746b;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *) ( &pirq->checksum + 1);
-	slot_num = 0;
-//pci bridge
-	write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++; slot_num++;
-//pcix bridge
-//        write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-//        pirq_info++; slot_num++;
-
-        pirq_info++; slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-        for (i = 0; i < pirq->size; i++)
-                sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-        if (sum != pirq->checksum) {
-                pirq->checksum = sum;
-        }
-
-	printk(BIOS_INFO, "done.\n");
-
-	return	(unsigned long) pirq_info;
-
+	return copy_pirq_routing_table(addr);
 }
diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h
new file mode 100644
index 0000000..aecd9b6
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h
@@ -0,0 +1,33 @@
+#ifndef MB_SYSCONF_H
+
+#define MB_SYSCONF_H
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+//busnum is default
+/*
+unsigned char bus_8131_0 = 1;
+unsigned char bus_8131_1 = 2;
+unsigned char bus_8131_2 = 3;
+unsigned char bus_8111_0 = 1;
+unsigned char bus_8111_1 = 4;
+unsigned apicid_8111 ;
+unsigned apicid_8131_1;
+unsigned apicid_8131_2;
+unsigned sbdn3;
+*/
+struct mb_sysconf_t {
+	unsigned char bus_8131_0;
+	unsigned char bus_8131_1;
+	unsigned char bus_8131_2;
+	unsigned char bus_8111_0;
+	unsigned char bus_8111_1;
+
+        unsigned apicid_8111;
+        unsigned apicid_8131_1;
+        unsigned apicid_8131_2;
+
+        unsigned sbdn3;
+};
+
+#endif
+
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index 3cd9fd6..d8b1a6a 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -5,22 +5,13 @@
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdk8_sysconf.h>
-
-extern  unsigned char bus_8131_0;
-extern  unsigned char bus_8131_1;
-extern  unsigned char bus_8131_2;
-extern  unsigned char bus_8111_0;
-extern  unsigned char bus_8111_1;
-extern  unsigned apicid_8111;
-extern  unsigned apicid_8131_1;
-extern  unsigned apicid_8131_2;
-
-extern  unsigned sbdn3;
+#include "mb_sysconf.h"
 
 static void *smp_write_config_table(void *v)
 {
         struct mp_config_table *mc;
 	int bus_isa;
+	struct mb_sysconf_t *m;
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
@@ -30,31 +21,33 @@ static void *smp_write_config_table(void *v)
 
 	get_bus_conf();
 
+	m = sysconf.mb;
+
 	mptable_write_buses(mc, NULL, &bus_isa);
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
-	smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR);
+	smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
         {
                 device_t dev;
                 struct resource *res;
-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
+                dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
-                                smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
+                                smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base);
                         }
                 }
-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
+                dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
-                                smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
+                                smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base);
                         }
                 }
 
 	}
 
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
 
 	//
 	// The commented-out lines are auto-detected on my servers.
@@ -66,18 +59,18 @@ static void *smp_write_config_table(void *v)
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111  , 0x11);
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111  , 0x12);
 	// Integrated AMD USB
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111  , 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111  , 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111  , 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111  , 0x13);
 	// On board ATI Rage XL
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111  , 0x14);
 	// On board Broadcom nics
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00);
 	// On board LSI SCSI
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
 
 	// PCIX-133 Slot
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01);
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index f51b4c4..7c34ff9 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -1,17 +1,17 @@
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/amdk8.h"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/early_serial.c"
@@ -23,53 +23,45 @@
 
 static void memreset_setup(void)
 {
-   if (is_cpu_pre_c0()) {
-      /* Set the memreset low. */
-      outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
-      /* Ensure the BIOS has control of the memory lines. */
-      outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-   } else {
-      /* Ensure the CPU has control of the memory lines. */
-      outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
-   }
+	if (is_cpu_pre_c0()) {
+		// Set the memreset low.
+		outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		// Ensure the BIOS has control of the memory lines.
+		outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+	} else {
+		// Ensure the CPU has control of the memory lines.
+		outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+	}
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
-   if (is_cpu_pre_c0()) {
-      udelay(800);
-      /* Set memreset high. */
-      outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
-      udelay(90);
-   }
+	if (is_cpu_pre_c0()) {
+		udelay(800);
+		// Set memreset high.
+		outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		udelay(90);
+	}
 }
 
 #define SMBUS_HUB 0x18
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
+static inline void change_i2c_mux(unsigned device)
 {
-  int ret,i;
-  unsigned device=(ctrl->channel0[0])>>8;
-  /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
-  i=2;
-  do {
-    ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-  } while ((ret!=0) && (i-->0));
-
-  smbus_write_byte(SMBUS_HUB, 0x03, 0);
+	int ret, i;
+	print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
+	i=2;
+	do {
+		ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
+		print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
+	} while ((ret!=0) && (i-->0));
+	ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
+	print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
 }
 
-static inline void change_i2c_mux(unsigned device)
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
-  int ret, i;
-  print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
-  i=2;
-  do {
-    ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-    print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
-  } while ((ret!=0) && (i-->0));
-  ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
-  print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
+	change_i2c_mux(ctrl->channel0[0]>>8);
 }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
@@ -77,6 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
+#include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -86,78 +79,80 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#define RC0 ((1<<1)<<8) // Not sure about these values
-#define RC1 ((1<<2)<<8) // Not sure about these values
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const uint16_t spd_addr [] = {
-		//first node
-		RC0|DIMM0, RC0|DIMM2, 0, 0,
-		RC0|DIMM1, RC0|DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
-		//second node
-		RC1|DIMM0, RC1|DIMM2, 0, 0,
-		RC1|DIMM1, RC1|DIMM3, 0, 0,
-#endif
-	};
-
-        int needs_reset;
-        unsigned bsp_apicid = 0, nodes;
-        struct mem_controller ctrl[8];
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	int needs_reset = 0;
+	unsigned bsp_apicid = 0;
 
-        if (bist == 0)
-                bsp_apicid = init_cpus(cpu_init_detectedx);
+	if (bist == 0)
+		bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo);
 
  	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
+	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+
 	setup_dl145g1_resource_map();
 	//setup_default_resource_map();
 
-	needs_reset = setup_coherent_ht_domain();
-
-        wait_all_core0_started();
+#if CONFIG_MEM_TRAIN_SEQ == 1
+	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+#endif
+	setup_coherent_ht_domain();
+	wait_all_core0_started();
 #if CONFIG_LOGICAL_CPUS==1
-        // It is said that we should start core1 after all core0 launched
-        start_other_cores();
-        wait_all_other_cores_started(bsp_apicid);
+	// It is said that we should start core1 after all core0 launched
+	start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
 #endif
+	ht_setup_chains_x(sysinfo);
 
-        needs_reset |= ht_setup_chains_x();
-
-       	if (needs_reset) {
-               	print_info("ht reset -\n");
-               	soft_reset();
-       	}
-
-	enable_smbus();
-
-	int i;
-	for(i=0;i<2;i++) {
-		activate_spd_rom(&ctrl[i]);
-	}
-	for(i=2;i<8;i<<=1) {
-		change_i2c_mux(i);
+	needs_reset |= optimize_link_coherent_ht();
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	if (needs_reset) {
+		print_info("ht reset -\n");
+		soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 	}
 
-	//dump_spd_registers(&ctrl[0]);
-	//dump_spd_registers(&ctrl[1]);
-	//dump_smbus_registers();
-
-        allow_all_aps_stop(bsp_apicid);
-
-        nodes = get_nodes();
-        //It's the time to set ctrl now;
-        fill_mem_ctrl(nodes, ctrl, spd_addr);
-
-        memreset_setup();
-        sdram_initialize(nodes, ctrl);
+	enable_smbus();
 
-	//dump_pci_devices();
+#define RC0 ((1<<1)<<8)
+#define RC1 ((1<<2)<<8)
+#if 0
+	change_i2c_mux(RC0>>8);
+	dump_smbus_registers();
+	change_i2c_mux(RC1>>8);
+	dump_smbus_registers();
+#endif
+	allow_all_aps_stop(bsp_apicid);
 
+	//It's the time to set ctrl now;
+	static const uint16_t spd_addr [] = {
+		//first node
+		RC0|DIMM0, RC0|DIMM2, 0, 0,
+		RC0|DIMM1, RC0|DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+		//second node
+		RC1|DIMM0, RC1|DIMM2, 0, 0,
+		RC1|DIMM1, RC1|DIMM3, 0, 0,
+#endif
+	};
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+#if 0
+	change_i2c_mux(sysinfo->ctrl[0].channel0[0]>>8);
+	dump_spd_registers(&sysinfo->ctrl[0]);
+	change_i2c_mux(sysinfo->ctrl[1].channel0[0]>>8);
+	dump_spd_registers(&sysinfo->ctrl[1]);
+#endif
+	memreset_setup();
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+#if 0
+	dump_pci_devices();
+#endif
 	post_cache_as_ram();
 }



From enok at lysator.liu.se  Tue Oct  4 20:00:22 2011
From: enok at lysator.liu.se (Oskar Enoksson)
Date: Tue, 04 Oct 2011 20:00:22 +0200
Subject: [coreboot] git/gerrit question
In-Reply-To: <20111004170607.6000.qmail@stuge.se>
References: <gerrit.1317223000146.I74fb892aa39048e2d0e76c081b713f825d67f2d4@review.coreboot.org>	<20110928155023.45F364002F@mail.lysator.liu.se>	<4E834487.3060404@lysator.liu.se>
	<4E8B2520.8040709@lysator.liu.se>	<4E8B2810.6060307@lysator.liu.se>
	<4E8B3642.6080200@lysator.liu.se>
	<20111004170607.6000.qmail@stuge.se>
Message-ID: <4E8B49B6.9060503@lysator.liu.se>

Thanks! This worked fine.

On 10/04/2011 07:06 PM, Peter Stuge wrote:
> Hi,
>
> Oskar Enoksson wrote:
>> I'm trying to upload a patch. It seems that for some reason
>> "gerrit" requires a "signed-off-by" line in every single local
>> commit in order to push it to the remote location.
> More background at
> http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
>
>
>> I'm able to "amend" such a line to the very last commit, but I
>> can't find a way to do it on the previous commits. How can I do it?
> ..
>> Do I have to start from scratch?
> Not at all. You'll use the git feature called interactive rebase, to
> rewrite your history. I recommend reading man git-rebase under
> "INTERACTIVE MODE" and/or http://progit.org/book/ch6-4.html for good
> descriptions of how this works.
>
> You run git rebase -i commithash_before_the_first_you_want_to_change
> and get an editor where you first create a script for git telling it
> what to do for each commit following the commit you specified.
> Default is to pick every commit unchanged. Change pick to edit, or
> simply e, for each line, save and exit. git rolls back history,
> applies the first commit, and exits to a shell. You can now git
> commit --amend -s -C HEAD to amend that commit to include a signoff.
>
> Remember to configure your user name and email address in git first:
> git config --global user.name 'Oskar Enoksson'
> git config --global user.email your at email.here
>
> If you had not done this before committing the first time, then you
> should also add --author='Oskar Enoksson<your at email.here>' to the
> git commit --amend -s -C HEAD command, in order to also fix the
> authorship information while you are iterating over the patches
> anyway. Use git show to review the commit. Then run
> git rebase --continue
>
> to have git perform the next command in the rebase script you created
> at the beginning. Once you've iterated over all commits git should
> report success.
>
>
> Note that when a branch with multiple commits which gerrit has not
> seen is pushed to gerrit, gerrit interprets this to mean that the
> commits in this branch all belong together as one unity, there is a
> dependence documented for each commit. This is not a hard dependency,
> the commits can also be included in the public repo out of order from
> gerrit, but for maximum clarity it is better to push independent
> patches separately, e.g. by having different branches locally, based
> on the current public repo and with just one new commit on each. It's
> not a too big deal if this should end up wrong in gerrit, especially
> on the first push, but keep it in mind for the future if there are
> independent commits. (This is just a note, I don't know if you do
> have independent commits or not.)
>
>
> Hope this helps
>
> //Peter
>




From gerrit at coreboot.org  Tue Oct  4 22:21:22 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Tue, 4 Oct 2011 22:21:22 +0200
Subject: [coreboot] Patch set updated for coreboot: 84a6f2f Added
	RAMINIT_SYSINFO and declared the necessary structs
References: <Ie90a134a1efc9605b3fe17a5b5008856226984be+0@gerrit.coreboot.org>
Message-ID: <Ie90a134a1efc9605b3fe17a5b5008856226984be+2@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/236

-gerrit

commit 84a6f2f02377a6d4e2b6ae4d058255199eaff77a
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Tue Oct 4 22:15:51 2011 +0200

    Added RAMINIT_SYSINFO and declared the necessary structs
    
    Functionality should be as before, but more clean/safe declaration
    through struct mb_sysconf_t. It's more consistent with other MB's
    and I've tested it thoroughly on my DL145. This is a second
    change-attempt, without any style fixes or other unrelated changes.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be
---
 src/mainboard/hp/dl145_g1/Kconfig        |    1 +
 src/mainboard/hp/dl145_g1/get_bus_conf.c |   52 ++++++++++++----------------
 src/mainboard/hp/dl145_g1/irq_tables.c   |   19 +++-------
 src/mainboard/hp/dl145_g1/mb_sysconf.h   |   20 +++++++++++
 src/mainboard/hp/dl145_g1/mptable.c      |   36 +++++++------------
 src/mainboard/hp/dl145_g1/romstage.c     |   55 +++++++++++++++++-------------
 6 files changed, 94 insertions(+), 89 deletions(-)

diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig
index eb90b07..ebd7ffd 100644
--- a/src/mainboard/hp/dl145_g1/Kconfig
+++ b/src/mainboard/hp/dl145_g1/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
+	select RAMINIT_SYSINFO
 #	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select QRANK_DIMM_SUPPORT
 
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
index e4721ce..a951328 100644
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -10,19 +10,12 @@
 #include <cpu/amd/amdk8_sysconf.h>
 #include <stdlib.h>
 
+#include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_8131_0 = 1;
-unsigned char bus_8131_1 = 2;
-unsigned char bus_8131_2 = 3;
-unsigned char bus_8111_0 = 1;
-unsigned char bus_8111_1 = 4;
-unsigned apicid_8111 ;
-unsigned apicid_8131_1;
-unsigned apicid_8131_2;
-
-unsigned pci1234x[] =
+struct mb_sysconf_t mb_sysconf;
+
+static unsigned pci1234x[] =
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
 	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
@@ -34,7 +27,7 @@ unsigned pci1234x[] =
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] =
+static unsigned hcdnx[] =
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
 	0x20202020,
 //	0x20202020,
@@ -45,8 +38,6 @@ unsigned hcdnx[] =
 //        0x20202020,
 //        0x20202020,
 };
-unsigned sbdn3;
-
 
 
 static unsigned get_bus_conf_done = 0;
@@ -63,6 +54,9 @@ void get_bus_conf(void)
 
         get_bus_conf_done = 1;
 
+	sysconf.mb = &mb_sysconf;
+	struct mb_sysconf_t *m = sysconf.mb;
+
         sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
@@ -72,36 +66,36 @@ void get_bus_conf(void)
         get_sblk_pci1234();
 
 	sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
-	sbdn3 = sysconf.hcdn[0] & 0xff;
+	m->sbdn3 = sysconf.hcdn[0] & 0xff;
 
-	bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
-	bus_8111_0 = bus_8131_0;
+	m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
+	m->bus_8111_0 = m->bus_8131_0;
 
                 /* 8111 */
-        dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
+        dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
         if (dev) {
-                bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	        m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
 	else {
-                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0);
         }
 
         /* 8131-1 */
-        dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
+        dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0));
         if (dev) {
-                bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
         else {
-                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0);
         }
 
         /* 8132-2 */
-        dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
+        dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0));
         if (dev) {
-                bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
         else {
-                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0);
         }
 
 
@@ -111,7 +105,7 @@ void get_bus_conf(void)
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
-	apicid_8111 = apicid_base+0;
-	apicid_8131_1 = apicid_base+1;
-	apicid_8131_2 = apicid_base+2;
+	m->apicid_8111 = apicid_base+0;
+	m->apicid_8131_1 = apicid_base+1;
+	m->apicid_8131_2 = apicid_base+2;
 }
diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c
index b53a992..24fc9be 100644
--- a/src/mainboard/hp/dl145_g1/irq_tables.c
+++ b/src/mainboard/hp/dl145_g1/irq_tables.c
@@ -11,6 +11,7 @@
 #include <arch/pirq_routing.h>
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include "mb_sysconf.h"
 
 static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
 		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
@@ -30,23 +31,13 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
         pirq_info->rfu = rfu;
 }
 
-extern  unsigned char bus_8131_0;
-extern  unsigned char bus_8131_1;
-extern  unsigned char bus_8131_2;
-extern  unsigned char bus_8111_0;
-extern  unsigned char bus_8111_1;
-
-extern  unsigned sbdn3;
-
-
-
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-
 	struct irq_routing_table *pirq;
 	struct irq_info *pirq_info;
 	unsigned slot_num;
 	uint8_t *v;
+	struct mb_sysconf_t *m = sysconf.mb;
 
         uint8_t sum=0;
         int i;
@@ -66,7 +57,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version  = PIRQ_VERSION;
 
-	pirq->rtr_bus = bus_8111_0;
+	pirq->rtr_bus = m->bus_8111_0;
 	pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
 
 	pirq->exclusive_irqs = 0;
@@ -81,10 +72,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	pirq_info = (void *) ( &pirq->checksum + 1);
 	slot_num = 0;
 //pci bridge
-	write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 	pirq_info++; slot_num++;
 //pcix bridge
-//        write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+//        write_pirq_info(pirq_info, m->bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 //        pirq_info++; slot_num++;
 
         pirq_info++; slot_num++;
diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h
new file mode 100644
index 0000000..0bceab4
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h
@@ -0,0 +1,20 @@
+#ifndef MB_SYSCONF_H
+
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+	unsigned char bus_8131_0;
+	unsigned char bus_8131_1;
+	unsigned char bus_8131_2;
+	unsigned char bus_8111_0;
+	unsigned char bus_8111_1;
+
+        unsigned apicid_8111;
+        unsigned apicid_8131_1;
+        unsigned apicid_8131_2;
+
+        unsigned sbdn3;
+};
+
+#endif
+
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index 3cd9fd6..20bf30f 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -5,17 +5,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdk8_sysconf.h>
-
-extern  unsigned char bus_8131_0;
-extern  unsigned char bus_8131_1;
-extern  unsigned char bus_8131_2;
-extern  unsigned char bus_8111_0;
-extern  unsigned char bus_8111_1;
-extern  unsigned apicid_8111;
-extern  unsigned apicid_8131_1;
-extern  unsigned apicid_8131_2;
-
-extern  unsigned sbdn3;
+#include "mb_sysconf.h"
 
 static void *smp_write_config_table(void *v)
 {
@@ -30,31 +20,33 @@ static void *smp_write_config_table(void *v)
 
 	get_bus_conf();
 
+	struct mb_sysconf_t *m = sysconf.mb;
+
 	mptable_write_buses(mc, NULL, &bus_isa);
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
-	smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR);
+	smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
         {
                 device_t dev;
                 struct resource *res;
-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
+                dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
-                                smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
+                                smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base);
                         }
                 }
-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
+                dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
-                                smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
+                                smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base);
                         }
                 }
 
 	}
 
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
 
 	//
 	// The commented-out lines are auto-detected on my servers.
@@ -66,18 +58,18 @@ static void *smp_write_config_table(void *v)
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111  , 0x11);
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111  , 0x12);
 	// Integrated AMD USB
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111  , 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111  , 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111  , 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111  , 0x13);
 	// On board ATI Rage XL
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111  , 0x14);
 	// On board Broadcom nics
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00);
 	// On board LSI SCSI
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
 
 	// PCIX-133 Slot
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01);
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index f51b4c4..c0a12d9 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -1,17 +1,17 @@
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/amdk8.h"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/early_serial.c"
@@ -55,7 +55,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
   do {
     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
   } while ((ret!=0) && (i-->0));
-
   smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
 
@@ -77,6 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
+#include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -86,8 +86,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#define RC0 ((1<<1)<<8) // Not sure about these values
-#define RC1 ((1<<2)<<8) // Not sure about these values
+#define RC0 ((1<<1)<<8)
+#define RC1 ((1<<2)<<8)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -101,13 +101,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		RC1|DIMM1, RC1|DIMM3, 0, 0,
 #endif
 	};
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-        int needs_reset;
-        unsigned bsp_apicid = 0, nodes;
-        struct mem_controller ctrl[8];
+	int needs_reset = 0;
+	unsigned bsp_apicid = 0;
 
         if (bist == 0)
-                bsp_apicid = init_cpus(cpu_init_detectedx);
+                bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo);
 
  	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         console_init();
@@ -115,47 +116,53 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
+        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+
 	setup_dl145g1_resource_map();
 	//setup_default_resource_map();
 
-	needs_reset = setup_coherent_ht_domain();
-
-        wait_all_core0_started();
+#if CONFIG_MEM_TRAIN_SEQ == 1
+	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+#endif
+	setup_coherent_ht_domain();
+	wait_all_core0_started();
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
         start_other_cores();
         wait_all_other_cores_started(bsp_apicid);
 #endif
 
-        needs_reset |= ht_setup_chains_x();
+        ht_setup_chains_x(sysinfo);
 
-       	if (needs_reset) {
-               	print_info("ht reset -\n");
-               	soft_reset();
-       	}
+	needs_reset |= optimize_link_coherent_ht();
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+
+	if (needs_reset) {
+		print_info("ht reset -\n");
+		soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
+	}
 
 	enable_smbus();
 
 	int i;
 	for(i=0;i<2;i++) {
-		activate_spd_rom(&ctrl[i]);
+		activate_spd_rom(&sysinfo->ctrl[i]);
 	}
-	for(i=2;i<8;i<<=1) {
+	for(i=RC0;i<=RC1;i<<=1) {
 		change_i2c_mux(i);
 	}
 
-	//dump_spd_registers(&ctrl[0]);
-	//dump_spd_registers(&ctrl[1]);
+	//dump_spd_registers(&sysinfo->ctrl[0]);
+	//dump_spd_registers(&sysinfo->ctrl[1]);
 	//dump_smbus_registers();
 
         allow_all_aps_stop(bsp_apicid);
 
-        nodes = get_nodes();
         //It's the time to set ctrl now;
-        fill_mem_ctrl(nodes, ctrl, spd_addr);
+        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
         memreset_setup();
-        sdram_initialize(nodes, ctrl);
+        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
 	//dump_pci_devices();
 



From gerrit at coreboot.org  Tue Oct  4 22:45:04 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Tue, 4 Oct 2011 22:45:04 +0200
Subject: [coreboot] New patch to review for coreboot: 1448012 Re-worked
	devicetree.cb for DL145 G1
References: <Ibbd97fafad22196b1e18d0b257731490339f113e+0@gerrit.coreboot.org>
Message-ID: <Ibbd97fafad22196b1e18d0b257731490339f113e+1@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/237

-gerrit

commit 144801207d5b1ad494d7b89b8c7156f8ae7ebd22
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Tue Oct 4 22:34:11 2011 +0200

    Re-worked devicetree.cb for DL145 G1
    
    After a lot of experimentation this commit improves some hardware
    features that were not recognized or incorrectly configured before.
    The only thing not tested is SCSI-option board (I dont have one).
    Misleading errors in comments have been corrected.
    (Note BTW that the DL145 G1 mainboard is identical to AMD Serenade
    which was supported in early versions of coreboot but was dropped
    for some reason.)
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e
---
 src/mainboard/hp/dl145_g1/devicetree.cb |  121 +++++++++++++------------------
 1 files changed, 52 insertions(+), 69 deletions(-)

diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb
index 3237723..bd67f23 100644
--- a/src/mainboard/hp/dl145_g1/devicetree.cb
+++ b/src/mainboard/hp/dl145_g1/devicetree.cb
@@ -12,45 +12,46 @@ chip northbridge/amd/amdk8/root_complex
       device pci 18.0 on     # link 2
         chip southbridge/amd/amd8131
           # the on/off keyword is mandatory
-          device pci 0.0 on end
-          device pci 0.1 on end
-          device pci 1.0 on end
-          device pci 1.1 on end
-          device pci 2.0 on end
-          device pci 2.1 on end
-          device pci 3.0 off end
+          device pci 0.0 on # PCIX Bridge A
+            # PCI-X expansion slot cards auto-detected here
+          end
+          device pci 0.1 on end  # IOAPIC A
+          device pci 1.0 on      # PCIX Bridge B
+            # On-board BCM5704 dual port ethernet chip auto-detected here
+            # Optional SCSI board also (?)
+	  end
+          device pci 1.1 on end  # IOAPIC B
+          device pci 2.0 off end
         end
         chip southbridge/amd/amd8111
-          # this "device pci 0.0" is the parent the next one
+          # this "device pci 0.0" is the parent of the next one
           # PCI bridge
           device pci 0.0 on
-            device pci 0.0 on end # LPC
-            device pci 0.1 on end # IDE
-            device pci 0.2 on end # SMbus
-            device pci 0.3 on end # ACPI
-            device pci 1.0 off end
-            #device pci 5.0 on end # SiI
-            #device pci 6.0 on end
+            device pci 0.0 on end  # OHCI-based USB controller 0
+            device pci 0.1 on end  # OCHI-based USB controller 1
+            device pci 0.2 on end  # EHCI-based USB2 controller
+            device pci 1.0 off end # LAN Ethernet controller
+            #device pci 4.0 on end # VGA PCI-card (auto detected)
           end
-          device pci 1.0 on
+          device pci 1.0 on # LPC Bridge
             chip superio/winbond/w83627hf
               device pnp 2e.0 off # Floppy
-                io  0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
+                #io  0x60 = 0x3f0
+                #irq 0x70 = 6
+                #drq 0x74 = 2
               end
               device pnp 2e.1 off # Parallel Port
-                io  0x60 = 0x378
-                irq 0x70 = 7
-                drq 0x74 = 1
+                #io  0x60 = 0x378
+                #irq 0x70 = 7
+                #drq 0x74 = 1
               end
               device pnp 2e.2 on  # Com1
                 io  0x60 = 0x3f8
                 irq 0x70 = 4
               end
-              device pnp 2e.3 on  # Com2
-                io  0x60 = 0x2f8
-                irq 0x70 = 3
+              device pnp 2e.3 off # Com2
+                #io  0x60 = 0x2f8
+                #irq 0x70 = 3
               end
               device pnp 2e.5 on  # Keyboard
                 io  0x60 = 0x60
@@ -60,12 +61,12 @@ chip northbridge/amd/amdk8/root_complex
               end
               device pnp 2e.6 off # CIR
               end
-              device pnp 2e.7 off # GAM_MIDI_GIPO1
-                io  0x60 = 0x201
-                io  0x62 = 0x330
-                irq 0x70 = 9
+              device pnp 2e.7 off  # GAM_MIDI_GPIO1
+                #io  0x60 = 0x201
+                #io  0x62 = 0x330
+                #irq 0x70 = 9
               end
-              device pnp 2e.8 on  # GPIO2
+              device pnp 2e.8 on  # GPIO2 (watchdog timer)
               end
               device pnp 2e.9 on  # GPIO3
               end
@@ -77,28 +78,18 @@ chip northbridge/amd/amdk8/root_complex
               end
             end
           end
-          device pci 1.1 on end
-          device pci 1.2 on end
-          device pci 1.3 on
-            chip drivers/generic/generic # ???
-              device i2c 08 on end
+          device pci 1.1 on end # EIDE controller
+          device pci 1.2 on 
+            chip drivers/generic/generic
+              device i2c 8 on end # Some HW-monitor/sensor?
             end
-            chip drivers/i2c/i2cmux # pca9556 smbus mux
-              device i2c 18 on #0 pca9516 1
-                # I don't know what 30-33 are for,
-                # they seem to have something to do with the DIMM's
-                chip drivers/generic/generic # ???
-                  device i2c 30 on end
-                end
-                chip drivers/generic/generic # ???
-                  device i2c 31 on end
-                end
-                chip drivers/generic/generic # ???
-                  device i2c 32 on end
-                end
-                chip drivers/generic/generic # ???
-                  device i2c 33 on end
-                end
+          end
+          device pci 1.2 on 
+            chip drivers/i2c/i2cmux # Multplexed DIMM spd eeproms.
+              device i2c 18 on #0 pca9516 (?)
+                # Some dimms also listen to address 30-33
+		# It's some kind of write-protect function
+		# The 50-53 addresses are the interesting ones.
                 chip drivers/generic/generic #dimm H0-0
                   device i2c 50 on end
                 end
@@ -112,19 +103,7 @@ chip northbridge/amd/amdk8/root_complex
                   device i2c 53 on end
                 end
               end
-              device i2c 18 on #1 pca9516 2
-                chip drivers/generic/generic # ???
-                  device i2c 30 on end
-                end
-                chip drivers/generic/generic # ???
-                  device i2c 31 on end
-                end
-                chip drivers/generic/generic # ???
-                  device i2c 32 on end
-                end
-                chip drivers/generic/generic # ???
-                  device i2c 33 on end
-                end
+              device i2c 18 on #1 pca9516 (?)
                 chip drivers/generic/generic #dimm H1-0
                   device i2c 50 on end
                 end
@@ -139,13 +118,17 @@ chip northbridge/amd/amdk8/root_complex
                 end
               end
             end
-            chip drivers/generic/generic # ???
-              device i2c 69 on end
+          end
+          device pci 1.2 on 
+            chip drivers/generic/generic
+              device i2c 69 on end  # Texas Instruments cdc960 clock synthesizer
             end
-          end # acpi
-          device pci 1.4 off end
+	  end # SMBus 2.0 controller
+          device pci 1.3 on     # System management registers (ACPI)
+          end # System management
+          #device pci 1.4 off end
           device pci 1.5 off end # AC97 Audio
-          device pci 1.6 off end # MC97 Modem
+          device pci 1.6 off end # AC97 Modem
           register "ide0_enable" = "1"
           register "ide1_enable" = "1"
         end



From enok at lysator.liu.se  Tue Oct  4 23:43:15 2011
From: enok at lysator.liu.se (Oskar Enoksson)
Date: Tue, 04 Oct 2011 23:43:15 +0200
Subject: [coreboot] "WARNING: BIOS bug: CPU MTRRs don't cover all of
 memory" loosing 2048MB of ram
In-Reply-To: <CALrs_3jWuwKh1b_dkj-tEsXf9RPL3WnSFo3MTe074bdxSwSWqQ@mail.gmail.com>
References: <4E8B06AA.6080007@lysator.liu.se>
	<CALrs_3jWuwKh1b_dkj-tEsXf9RPL3WnSFo3MTe074bdxSwSWqQ@mail.gmail.com>
Message-ID: <4E8B7DF3.6080506@lysator.liu.se>

On 10/04/2011 06:45 PM, Marc Jones wrote:
> On Tue, Oct 4, 2011 at 7:14 AM, Oskar Enoksson<enok at lysator.liu.se>  wrote:
>> I incidently put 5GB RAM in my hp/dl145_g1 motherboard (2x1g+6x512m) and got
>> the following error from Linux when booting:
>>
>> "WARNING: BIOS bug: CPU MTRRs don't cover all of memory" loosing 2048MB of
>> ram
>>
>> (The dl145_g1 is a dual-socket amdk8 board with four DIMM's per CPU socket).
>>
>> After digging around in the coreboot code I noticed that if I changed the
>> last line in src/amd/amd_mtrr.c the generated MTRR was correct and the
>> problem was solved:
>>
>>     /* Now that I have mapped what is memory and what is not
>>      * Setup the mtrrs so we can cache the memory.
>>      */
>> -    x86_setup_var_mtrrs(address_bits, 0);
>> +    x86_setup_var_mtrrs(address_bits, 1);
>>
>> In cpu/x86/mtrr/mtrr.c the comments explains the last parameter in great
>> detail:
>>
>> void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
>> /* this routine needs to know how many address bits a given processor
>>   * supports.  CPUs get grumpy when you set too many bits in
>>   * their mtrr registers :(  I would generically call cpuid here
>>   * and find out how many physically supported but some cpus are
>>   * buggy, and report more bits then they actually support.
>>   * If above4gb flag is set, variable MTRR ranges must be used to
>>   * set cacheability of DRAM above 4GB. If above4gb flag is clear,
>>   * some other mechanism is controlling cacheability of DRAM above 4GB.
>>   */
>>
>> So - what "some other mechanism" is assumed to work on AMD cpu's and what
>> should I do to make it work?
>>
>> The patch described in
>> http://www.coreboot.org/pipermail/coreboot/attachments/20101111/7eff5b02/attachment-0001.txt
>> by Scott Duplichan tries to explain something, but I'm still not sure what
>> to do.
> The Fam10 and K8 have the AMD Tom2ForceMemTypeWB feature to avoid the
> need for  variable MTRR ranges above 4GB. Either that isn't being set
> on your platform or your kernel is misreporting because it doesn't
> know about the feature.
>
> Marc
It looks to me like  AMD K8 processors don't have this feature.

On pp 314 of AMD Family 10 BKDG the bit is described 
"Tom2ForceMemTypeWB: top of memory 2 memory type write back. "

On pp 369 of AMD Hammer BKDG bits 22-64 are all Reserved.

So coreboot is wrong assuming there is such mechanism on amdk8.




From marcj303 at gmail.com  Wed Oct  5 00:30:50 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 4 Oct 2011 16:30:50 -0600
Subject: [coreboot] "WARNING: BIOS bug: CPU MTRRs don't cover all of
 memory" loosing 2048MB of ram
In-Reply-To: <4E8B7DF3.6080506@lysator.liu.se>
References: <4E8B06AA.6080007@lysator.liu.se>
	<CALrs_3jWuwKh1b_dkj-tEsXf9RPL3WnSFo3MTe074bdxSwSWqQ@mail.gmail.com>
	<4E8B7DF3.6080506@lysator.liu.se>
Message-ID: <CALrs_3hzSGbnd0Ah3bOwAg24soQrBJytTJcU=_u31mF7dUuRVQ@mail.gmail.com>

On Tue, Oct 4, 2011 at 3:43 PM, Oskar Enoksson <enok at lysator.liu.se> wrote:
> On 10/04/2011 06:45 PM, Marc Jones wrote:
>>
>> On Tue, Oct 4, 2011 at 7:14 AM, Oskar Enoksson<enok at lysator.liu.se>
>> ?wrote:
>>>
>>> I incidently put 5GB RAM in my hp/dl145_g1 motherboard (2x1g+6x512m) and
>>> got
>>> the following error from Linux when booting:
>>>
>>> "WARNING: BIOS bug: CPU MTRRs don't cover all of memory" loosing 2048MB
>>> of
>>> ram
>>>
>>> (The dl145_g1 is a dual-socket amdk8 board with four DIMM's per CPU
>>> socket).
>>>
>>> After digging around in the coreboot code I noticed that if I changed the
>>> last line in src/amd/amd_mtrr.c the generated MTRR was correct and the
>>> problem was solved:
>>>
>>> ? ?/* Now that I have mapped what is memory and what is not
>>> ? ? * Setup the mtrrs so we can cache the memory.
>>> ? ? */
>>> - ? ?x86_setup_var_mtrrs(address_bits, 0);
>>> + ? ?x86_setup_var_mtrrs(address_bits, 1);
>>>
>>> In cpu/x86/mtrr/mtrr.c the comments explains the last parameter in great
>>> detail:
>>>
>>> void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int
>>> above4gb)
>>> /* this routine needs to know how many address bits a given processor
>>> ?* supports. ?CPUs get grumpy when you set too many bits in
>>> ?* their mtrr registers :( ?I would generically call cpuid here
>>> ?* and find out how many physically supported but some cpus are
>>> ?* buggy, and report more bits then they actually support.
>>> ?* If above4gb flag is set, variable MTRR ranges must be used to
>>> ?* set cacheability of DRAM above 4GB. If above4gb flag is clear,
>>> ?* some other mechanism is controlling cacheability of DRAM above 4GB.
>>> ?*/
>>>
>>> So - what "some other mechanism" is assumed to work on AMD cpu's and what
>>> should I do to make it work?
>>>
>>> The patch described in
>>>
>>> http://www.coreboot.org/pipermail/coreboot/attachments/20101111/7eff5b02/attachment-0001.txt
>>> by Scott Duplichan tries to explain something, but I'm still not sure
>>> what
>>> to do.
>>
>> The Fam10 and K8 have the AMD Tom2ForceMemTypeWB feature to avoid the
>> need for ?variable MTRR ranges above 4GB. Either that isn't being set
>> on your platform or your kernel is misreporting because it doesn't
>> know about the feature.
>>
>> Marc
>
> It looks to me like ?AMD K8 processors don't have this feature.
>
> On pp 314 of AMD Family 10 BKDG the bit is described "Tom2ForceMemTypeWB:
> top of memory 2 memory type write back. "
>
> On pp 369 of AMD Hammer BKDG bits 22-64 are all Reserved.
>
> So coreboot is wrong assuming there is such mechanism on amdk8.


The feature was added in the reg F, so without a version check there
it could do the wrong thing. If you have a rev F or later you must
have an old kernel.

http://kerneltrap.org/mailarchive/linux-kernel/2008/1/21/588155


Marc


-- 
http://se-eng.com



From enok at lysator.liu.se  Wed Oct  5 00:38:19 2011
From: enok at lysator.liu.se (Oskar Enoksson)
Date: Wed, 05 Oct 2011 00:38:19 +0200
Subject: [coreboot] "WARNING: BIOS bug: CPU MTRRs don't cover all of
 memory" loosing 2048MB of ram
In-Reply-To: <CALrs_3hzSGbnd0Ah3bOwAg24soQrBJytTJcU=_u31mF7dUuRVQ@mail.gmail.com>
References: <4E8B06AA.6080007@lysator.liu.se>
	<CALrs_3jWuwKh1b_dkj-tEsXf9RPL3WnSFo3MTe074bdxSwSWqQ@mail.gmail.com>
	<4E8B7DF3.6080506@lysator.liu.se>
	<CALrs_3hzSGbnd0Ah3bOwAg24soQrBJytTJcU=_u31mF7dUuRVQ@mail.gmail.com>
Message-ID: <4E8B8ADB.2060500@lysator.liu.se>

On 10/05/2011 12:30 AM, Marc Jones wrote:
> On Tue, Oct 4, 2011 at 3:43 PM, Oskar Enoksson<enok at lysator.liu.se>  wrote:
>> On 10/04/2011 06:45 PM, Marc Jones wrote:
>>> On Tue, Oct 4, 2011 at 7:14 AM, Oskar Enoksson<enok at lysator.liu.se>
>>>   wrote:
>>>> I incidently put 5GB RAM in my hp/dl145_g1 motherboard (2x1g+6x512m) and
>>>> got
>>>> the following error from Linux when booting:
>>>>
>>>> "WARNING: BIOS bug: CPU MTRRs don't cover all of memory" loosing 2048MB
>>>> of
>>>> ram
>>>>
>>>> (The dl145_g1 is a dual-socket amdk8 board with four DIMM's per CPU
>>>> socket).
>>>>
>>>> After digging around in the coreboot code I noticed that if I changed the
>>>> last line in src/amd/amd_mtrr.c the generated MTRR was correct and the
>>>> problem was solved:
>>>>
>>>>     /* Now that I have mapped what is memory and what is not
>>>>      * Setup the mtrrs so we can cache the memory.
>>>>      */
>>>> -    x86_setup_var_mtrrs(address_bits, 0);
>>>> +    x86_setup_var_mtrrs(address_bits, 1);
>>>>
>>>> In cpu/x86/mtrr/mtrr.c the comments explains the last parameter in great
>>>> detail:
>>>>
>>>> void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int
>>>> above4gb)
>>>> /* this routine needs to know how many address bits a given processor
>>>>   * supports.  CPUs get grumpy when you set too many bits in
>>>>   * their mtrr registers :(  I would generically call cpuid here
>>>>   * and find out how many physically supported but some cpus are
>>>>   * buggy, and report more bits then they actually support.
>>>>   * If above4gb flag is set, variable MTRR ranges must be used to
>>>>   * set cacheability of DRAM above 4GB. If above4gb flag is clear,
>>>>   * some other mechanism is controlling cacheability of DRAM above 4GB.
>>>>   */
>>>>
>>>> So - what "some other mechanism" is assumed to work on AMD cpu's and what
>>>> should I do to make it work?
>>>>
>>>> The patch described in
>>>>
>>>> http://www.coreboot.org/pipermail/coreboot/attachments/20101111/7eff5b02/attachment-0001.txt
>>>> by Scott Duplichan tries to explain something, but I'm still not sure
>>>> what
>>>> to do.
>>> The Fam10 and K8 have the AMD Tom2ForceMemTypeWB feature to avoid the
>>> need for  variable MTRR ranges above 4GB. Either that isn't being set
>>> on your platform or your kernel is misreporting because it doesn't
>>> know about the feature.
>>>
>>> Marc
>> It looks to me like  AMD K8 processors don't have this feature.
>>
>> On pp 314 of AMD Family 10 BKDG the bit is described "Tom2ForceMemTypeWB:
>> top of memory 2 memory type write back. "
>>
>> On pp 369 of AMD Hammer BKDG bits 22-64 are all Reserved.
>>
>> So coreboot is wrong assuming there is such mechanism on amdk8.
> The feature was added in the reg F, so without a version check there
> it could do the wrong thing. If you have a rev F or later you must
> have an old kernel.
>
> http://kerneltrap.org/mailarchive/linux-kernel/2008/1/21/588155
Makes sense. My CPU is old (rev E) and my kernel is new (2.6.37). 
Coreboot should make variable MTRRs span memory >4GB if for K8 CPU rev <F.





From yinghailu at gmail.com  Wed Oct  5 00:26:09 2011
From: yinghailu at gmail.com (yhlu)
Date: Tue, 4 Oct 2011 15:26:09 -0700
Subject: [coreboot] "WARNING: BIOS bug: CPU MTRRs don't cover all of
 memory" loosing 2048MB of ram
In-Reply-To: <4E8B7DF3.6080506@lysator.liu.se>
References: <4E8B06AA.6080007@lysator.liu.se>
	<CALrs_3jWuwKh1b_dkj-tEsXf9RPL3WnSFo3MTe074bdxSwSWqQ@mail.gmail.com>
	<4E8B7DF3.6080506@lysator.liu.se>
Message-ID: <CANeVWaPbogn1jF0i_1YiWTuV9Kdp2-pB9QHp9aq-bWB0dU2UQg@mail.gmail.com>

On Tue, Oct 4, 2011 at 2:43 PM, Oskar Enoksson <enok at lysator.liu.se> wrote:
>
> It looks to me like ?AMD K8 processors don't have this feature.
>
> On pp 314 of AMD Family 10 BKDG the bit is described "Tom2ForceMemTypeWB:
> top of memory 2 memory type write back. "
>
> On pp 369 of AMD Hammer BKDG bits 22-64 are all Reserved.
>
> So coreboot is wrong assuming there is such mechanism on amdk8.
>

only cpus after K8 rev F (included), have that feature.

corresponding kernel code:

/*
 * Newer AMD K8s and later CPUs have a special magic MSR way to force WB
 * for memory >4GB. Check for that here.
 * Note this won't check if the MTRRs < 4GB where the magic bit doesn't
 * apply to are wrong, but so far we don't know of any such case in the wild.
 */
#define Tom2Enabled             (1U << 21)
#define Tom2ForceMemTypeWB      (1U << 22)

int __init amd_special_default_mtrr(void)
{
        u32 l, h;

        if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
                return 0;
        if (boot_cpu_data.x86 < 0xf)
                return 0;
        /* In case some hypervisor doesn't pass SYSCFG through: */
        if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0)
                return 0;
        /*
         * Memory between 4GB and top of mem is forced WB by this magic bit.
         * Reserved before K8RevF, but should be zero there.
         */
        if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) ==
                 (Tom2Enabled | Tom2ForceMemTypeWB))
                return 1;
        return 0;
}



From thomas at gstaedtner.net  Wed Oct  5 01:26:42 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Wed, 5 Oct 2011 01:26:42 +0200
Subject: [coreboot] Issues with Supermicro H8SCM
Message-ID: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>

Hi everyone,

I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of
the boards AMD as of recently claims to officially support.
So I decided to try coreboot, but (as expected) it is not really an
out-of-the-box experience.

First of all, flashrom does not support flashing out-of-the-box, but
Frederic Temporelli's patches (
http://patchwork.coreboot.org/patch/3326/ and
http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I tested
multiple reads and multiple writes, always worked), I can report that
to the flashrom list separately if you want.

I built coreboot from the gerrit-branch (also tried a "stable"
revision), coreboot-4.0-1714-gf8adf7a, using the "default"
board-config incl. seabios (stable) as payload.
After powering on nothing happens (apart from the fans running and the
power led flashing) and it stays that way, it is silent on VGA as well
as serial.
After manually triggering a reset I immediately get the following
output on serial:

coreboot-4.0-1714-gf8adf7a Wed Oct  5 00:31:05 CEST 2011 starting...
BSP Family_Model:

Here it hangs, and I don't quite know how to move on and debug the issue.

Can you give me any hints where to go on from here? I have external
flashing equipment at hand (which also works fine btw.), but no fancy
bios-debugging hardware.

Regards,

thomasg

P.S. In case anyone else stumbles upon it: the board has 2 separate
flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W
package on the left of the board) as well as a SST25VF016B, 16 Mbit,
as the SOIC8W on the right. The first one holds the IPMI firmware, the
second one the AMI BIOS.
Flashing requires a testclip or some really serious soldering skills.
Attaching a SO8 socket can only be done with hot air soldering.



From alperenkose at buyutech.com.tr  Wed Oct  5 10:04:22 2011
From: alperenkose at buyutech.com.tr (=?ISO-8859-1?Q?Alp_Eren_K=F6se?=)
Date: Wed, 5 Oct 2011 11:04:22 +0300
Subject: [coreboot] Coreboot on Axiomtek PICO821
In-Reply-To: <CAOz08zFfKpUprX76LeO5NCtJUXtgwUG0mxM1FVH_0-5gPv2pEA@mail.gmail.com>
References: <CAOz08zFfKpUprX76LeO5NCtJUXtgwUG0mxM1FVH_0-5gPv2pEA@mail.gmail.com>
Message-ID: <CAOz08zEMc1EjetFPeAhSOsf5ht=rKLq1Zo3CAqrbyw3C+13QGQ@mail.gmail.com>

Anyone has an idea?

Another question is I can't find my mainboard vendor "Axiomtek" in Mainboard
Vendor selection list in menuconfig as expectedly, but all the chips and
chipset of it seem to be supported as I see them in coreboot website. Is it
still possible to install coreboot, if so how can I do it?
It would be really nice if someone could point a way..

Thanks in advance,
Alp


2011/10/3 Alp Eren K?se <alperenkose at buyutech.com.tr>

> Hello all!
>
> I am new to your list, and I want to install coreboot in a board I own.
> I couldn't be sure if it work on it, let me give you the details:
>
> Board Vendor: Axiomtek
> Board Name: PICO821
> CPU: Intel(R) Atom(TM) CPU Z510   @ 1.10GHz
> Chipset: Intel System Controller Hub US15W
>
> The "*lspci -tvnn*" output is attached at the "lspci_output.txt" file.
>
> "*superiotool -dV*" output is attached at "superiotool_output.txt" file.
>
> "*flasrom -V*" output is at "flashrom_output.txt" file.
>
> And this is the URL of the product:
> http://axiomtek.com/products/ViewProduct.asp?view=772
> also the product manual link is at:
> http://www.axiomtek.com/Download/Download/PICO821/PICO821.pdf
>
> Soo that's all, I hope it is possible to flash coreboot on this device, I
> would really to have it running, believe it will be much faster to run Linux
> on top of it ;)
>
> Thanks,
> Regards,
> Alp
>
-------------- next part --------------
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From vidwer at gmail.com  Wed Oct  5 12:38:04 2011
From: vidwer at gmail.com (Idwer Vollering)
Date: Wed, 5 Oct 2011 12:38:04 +0200
Subject: [coreboot] Coreboot on Axiomtek PICO821
In-Reply-To: <CAOz08zEMc1EjetFPeAhSOsf5ht=rKLq1Zo3CAqrbyw3C+13QGQ@mail.gmail.com>
References: <CAOz08zFfKpUprX76LeO5NCtJUXtgwUG0mxM1FVH_0-5gPv2pEA@mail.gmail.com>
	<CAOz08zEMc1EjetFPeAhSOsf5ht=rKLq1Zo3CAqrbyw3C+13QGQ@mail.gmail.com>
Message-ID: <CAPp9OrmKKSxNvW++OfYR044TWnviti5fnnn76MYUsXfT9S7EKw@mail.gmail.com>

2011/10/5 Alp Eren K?se <alperenkose at buyutech.com.tr>:
> Anyone has an idea?
>
> Another question is I can't find my mainboard vendor "Axiomtek" in Mainboard
> Vendor selection list in menuconfig as expectedly, but all the chips and
> chipset of it seem to be supported as I see them in coreboot website. Is it
> still possible to install coreboot, if so how can I do it?

Yes, it is still possible but you should have a way to restore the
vendor image if this board does not boot. The target that I suggest to
use is iWave iW-RainboW-G6:
http://www.coreboot.org/News#2010.2F12.2F18_Intel_Poulsbo.2FSCH.2FAtom_and_iWave_iW-RainboW-G6_now_supported

> It would be really nice if someone could point a way..
>
> Thanks in advance,
> Alp
>
>
> 2011/10/3 Alp Eren K?se <alperenkose at buyutech.com.tr>
>>
>> Hello all!
>> I am new to your list, and I want to install coreboot in a board I own.
>> I couldn't be sure if it work on it, let me give you the details:
>> Board Vendor: Axiomtek
>> Board Name: PICO821
>> CPU:?Intel(R) Atom(TM) CPU Z510 ? @ 1.10GHz
>> Chipset: Intel System Controller Hub US15W
>> The "lspci -tvnn"?output is attached at the "lspci_output.txt" file.
>> "superiotool -dV" output is attached at "superiotool_output.txt" file.
>> "flasrom -V" output is at "flashrom_output.txt" file.
>> And this is the URL of the
>> product:?http://axiomtek.com/products/ViewProduct.asp?view=772
>> also the product manual link is
>> at:?http://www.axiomtek.com/Download/Download/PICO821/PICO821.pdf
>> Soo that's all, I hope it is possible to flash coreboot on this device, I
>> would really to have it running, believe it will be much faster to run Linux
>> on top of it ;)
>> Thanks,
>> Regards,
>> Alp
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From marcj303 at gmail.com  Wed Oct  5 20:08:27 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 5 Oct 2011 12:08:27 -0600
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
Message-ID: <CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>

On Tue, Oct 4, 2011 at 5:26 PM, Thomas Gst?dtner <thomas at gstaedtner.net> wrote:
> Hi everyone,
>
> I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of
> the boards AMD as of recently claims to officially support.
> So I decided to try coreboot, but (as expected) it is not really an
> out-of-the-box experience.
>
> First of all, flashrom does not support flashing out-of-the-box, but
> Frederic Temporelli's patches (
> http://patchwork.coreboot.org/patch/3326/ and
> http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I tested
> multiple reads and multiple writes, always worked), I can report that
> to the flashrom list separately if you want.
>
> I built coreboot from the gerrit-branch (also tried a "stable"
> revision), coreboot-4.0-1714-gf8adf7a, using the "default"
> board-config incl. seabios (stable) as payload.
> After powering on nothing happens (apart from the fans running and the
> power led flashing) and it stays that way, it is silent on VGA as well
> as serial.
> After manually triggering a reset I immediately get the following
> output on serial:
>
> coreboot-4.0-1714-gf8adf7a Wed Oct ?5 00:31:05 CEST 2011 starting...
> BSP Family_Model:
>
> Here it hangs, and I don't quite know how to move on and debug the issue.
>
> Can you give me any hints where to go on from here? I have external
> flashing equipment at hand (which also works fine btw.), but no fancy
> bios-debugging hardware.
>
> Regards,
>
> thomasg
>
> P.S. In case anyone else stumbles upon it: the board has 2 separate
> flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W
> package on the left of the board) as well as a SST25VF016B, 16 Mbit,
> as the SOIC8W on the right. The first one holds the IPMI firmware, the
> second one the AMI BIOS.
> Flashing requires a testclip or some really serious soldering skills.
> Attaching a SO8 socket can only be done with hot air soldering.

Hi Thomas,

Thanks for the report. While many people overlap with the flashrom
list, please post about those patches on that list. Seems that you
should be able to ack them.

 It looks like maybe the platform build doesn't support your CPU.
There have been a number of recent contributions from AMD, but they
don't all align with the platform contributions. So, the H8SCM should
support all fam10 revD, but may have issue with Fam10 rev E. To get
more information, you can turn the console debug output to SPEW in
menuconfig.

Marc



-- 
http://se-eng.com



From enok at lysator.liu.se  Thu Oct  6 00:05:50 2011
From: enok at lysator.liu.se (Oskar Enoksson)
Date: Thu, 06 Oct 2011 00:05:50 +0200
Subject: [coreboot] amd_model_fxx_generate_powernow with dual-socket
 dual-core K8 system just handles first CPU(?)
Message-ID: <4E8CD4BE.5010009@lysator.liu.se>

I'm trying to make Cool'n'Quiet working on DL145G1 (dual-socket 940-pin 
K8 processors) but I just get FID/VID changes on one of the CPU's (under 
Linux 2.6.37).

Problem seems to be that amd_model_fxx_generate_powernow just generates 
two "Processor" objects in SSDT. I think there should be one for each core.

If I add a factor 2 on row cpu/amd/model_fxx/powernow_acpi.c I get four 
Processor objects in my SSDT and everything works:

-    for (index = 0; index < cmp_cap + 1; index++) {
+    for (index = 0; index < 2*(cmp_cap + 1); index++) {
         len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid

cmp_cap is correctly detected further up as 1 or 0 depending on the 
dual-core-capability (of the first CPU).

Shouldn't there be a loop over all processor sockets around all this?




From marcj303 at gmail.com  Thu Oct  6 01:03:38 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 5 Oct 2011 17:03:38 -0600
Subject: [coreboot] amd_model_fxx_generate_powernow with dual-socket
 dual-core K8 system just handles first CPU(?)
In-Reply-To: <4E8CD4BE.5010009@lysator.liu.se>
References: <4E8CD4BE.5010009@lysator.liu.se>
Message-ID: <CALrs_3hf0x+FNxLDSF8PEqkVoc8NdCUShOHLrMoUOPzE+z3o9A@mail.gmail.com>

On Wed, Oct 5, 2011 at 4:05 PM, Oskar Enoksson <enok at lysator.liu.se> wrote:
> I'm trying to make Cool'n'Quiet working on DL145G1 (dual-socket 940-pin K8
> processors) but I just get FID/VID changes on one of the CPU's (under Linux
> 2.6.37).
>
> Problem seems to be that amd_model_fxx_generate_powernow just generates two
> "Processor" objects in SSDT. I think there should be one for each core.
>
> If I add a factor 2 on row cpu/amd/model_fxx/powernow_acpi.c I get four
> Processor objects in my SSDT and everything works:
>
> - ? ?for (index = 0; index < cmp_cap + 1; index++) {
> + ? ?for (index = 0; index < 2*(cmp_cap + 1); index++) {
> ? ? ? ?len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid
>
> cmp_cap is correctly detected further up as 1 or 0 depending on the
> dual-core-capability (of the first CPU).
>
> Shouldn't there be a loop over all processor sockets around all this?

Seems so.


-- 
http://se-eng.com



From r.marek at assembler.cz  Thu Oct  6 01:07:57 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 06 Oct 2011 01:07:57 +0200
Subject: [coreboot] amd_model_fxx_generate_powernow with dual-socket
 dual-core K8 system just handles first CPU(?)
In-Reply-To: <CALrs_3hf0x+FNxLDSF8PEqkVoc8NdCUShOHLrMoUOPzE+z3o9A@mail.gmail.com>
References: <4E8CD4BE.5010009@lysator.liu.se>
	<CALrs_3hf0x+FNxLDSF8PEqkVoc8NdCUShOHLrMoUOPzE+z3o9A@mail.gmail.com>
Message-ID: <4E8CE34D.1070300@assembler.cz>

Hi all,

Yes there should be a loop for processor sockets. I wrote that for single cpu 
(dual core...)

Please fix it so it works on all cases.

Thanks
Rudolf



From marcj303 at gmail.com  Thu Oct  6 17:15:05 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 6 Oct 2011 09:15:05 -0600
Subject: [coreboot] amd_model_fxx_generate_powernow with dual-socket
 dual-core K8 system just handles first CPU(?)
In-Reply-To: <4E8DB42C.4050004@lysator.liu.se>
References: <4E8CD4BE.5010009@lysator.liu.se>
	<CALrs_3hf0x+FNxLDSF8PEqkVoc8NdCUShOHLrMoUOPzE+z3o9A@mail.gmail.com>
	<4E8CE34D.1070300@assembler.cz> <4E8DB42C.4050004@lysator.liu.se>
Message-ID: <CALrs_3jcXsbkAok_wU6BcrEzHnqaPx1s3t+SsxEOkRuq=NbZ_Q@mail.gmail.com>

On Thu, Oct 6, 2011 at 7:59 AM, Oskar Enoksson <enok at lysator.liu.se> wrote:
> I think I can fix it, or at least improve it.
>
> One question though: is there any easy way to read msr register from a
> particular cpudevice (not from the core on which we currently execute)?
>

No, MSRs can only be read by code running on a given CPU.

Marc



> On 10/06/2011 01:07 AM, Rudolf Marek wrote:
>>
>> Hi all,
>>
>> Yes there should be a loop for processor sockets. I wrote that for single
>> cpu (dual core...)
>>
>> Please fix it so it works on all cases.
>>
>> Thanks
>> Rudolf
>>
>
>



-- 
http://se-eng.com



From marcj303 at gmail.com  Thu Oct  6 16:58:50 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 6 Oct 2011 08:58:50 -0600
Subject: [coreboot] patch to display ASRock E350M1 freq correctly
In-Reply-To: <CADBhXUTdvf5baYWVHRhmJGbjA91Pwqz1O+iCbMAZ5bM+V2PrRQ@mail.gmail.com>
References: <CADBhXUT1aigKywuBhrnzeF+-xiah1_0G2pVG6Rmgjm-hqXNZ8Q@mail.gmail.com>
	<4E8AB7ED.1070802@assembler.cz>
	<CALrs_3jDKpRkiML8At=G-MqY8w98hnBPm9DC0yTxm_mkqtC80w@mail.gmail.com>
	<CADBhXUTdvf5baYWVHRhmJGbjA91Pwqz1O+iCbMAZ5bM+V2PrRQ@mail.gmail.com>
Message-ID: <CALrs_3hwHv2MbUjpe5L4mB4aKYxcMSGU2KTzRfH+RSxwxH2qXg@mail.gmail.com>

Keeping this on the list.

On Wed, Oct 5, 2011 at 7:03 PM, mopz0506 mopz0506 <mopz0506 at gmail.com> wrote:
> I'm very surprised too.
>
> I'm not familiar with coreboot code base, but seems all SB800-based
> ?system are running hardcoded codepath and ignores a lot of Agesa code.
> There are so many indirection and everytime you call the same
> function it may do different thing, depends on "The service desired",
> and the callback.
>
> Don't have serial port/cable so what I can do is guessing.
>
> so below is what happened, I guess.
>
> in agesawrapper_amdinitlate (), AmdLateParams has been filled
> with 0 (And AmdLateParams.StdHeader.HeapBasePtr).
>
> so we must set "AmdLateParams.PlatformConfig.UserOptionPstate"
> to "TRUE", tell Agesa that we want a PState table.
>
> then call AmdInitLate(&AmdLateParams) and let Agesa to build
> ?SSDT for us.
>
> AmdInitLate() call GenerateSsdt () to do the real work.
>
> GenerateSsdt () call HeapLocateBuffer() to get the location of
> PState data, which Agesa prepared for us before.
>
> unlucky, HeapLocateBuffer() requires (NULL != StdHeader->HeapBasePtr),
> here StdHeader is &AmdLateParams.StdHead.
>
> since AmdLateParams has been initialized to 0, aka. the stdheader.HeapBasePtr
> ?is NULL, the HeapLocateBuffer() failed and return AGESA_ERROR.
>
> so, all those pointer, *DmiTable, *AcpiPstate, *AcpiSrat, *AcpiSlit,
> *AcpiWheaMce, *AcpiWheaCmc, *AcpiAlib, always being NULL.
>
> since AcpiPstate is NULL, write_acpi_tables() always skip Agesa and
> fallback to hardcoded data and ACPI setting.
>
> we must set the AmdLateParams.StdHeader to a valid HeapBasePtr to fetch
> Agesa's PState data.
>
> but seems HeapManager is for Agesa internal only. Tried HeapGetBaseAddress()
> the computer frozen. I know nothing about programming on such raw hardware
> and don't know why.
>
> I checked agesawrapper.c from other mainboards and found nothing.
>
> how could I get a valid HeapBasePtr to call HeapLocateBuffer() and
> HeapAllocateBuffer()?
>
> Any hints?
>
> Thanks,
> mopz0506
>
> On Wed, Oct 5, 2011 at 12:24 AM, Marc Jones <marcj303 at gmail.com> wrote:
>> On Tue, Oct 4, 2011 at 1:38 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
>>> Hi all,
>>>
>>>> I'm not native speaker and sorry for my English.
>>>
>>> Yep me too ;) But your doing OK we can understand what you wrote.
>>>
>>>> Finally I think maybe I can fix it myself and start
>>>> digging ACPI and source code.
>>>
>>> I'm quite surprised that this is hardcoded. We used to have a functions
>>> which place it there runtime depending on CPU model. I don't know
>>> why it is hardcoded here. I think a proper fix would be to provide that
>>> runtime depending on CPU. Maybe AGESA has some infrastructure for that. Did
>>> not check so far.
>>>
>>> Thanks
>>> Rudolf
>>
>> This should be generated by the AMDInitLate call, which needs some
>> work in coreboot acpi/agesa wrappers. Feel free to check out the
>> tables that are generated and look at how they should be integrated.
>>
>> Marc
>>
>>
>>
>> --
>> http://se-eng.com
>>
>



-- 
http://se-eng.com



From gerrit at coreboot.org  Thu Oct  6 18:26:32 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Thu, 6 Oct 2011 18:26:32 +0200
Subject: [coreboot] New patch to review for coreboot: 1c4e003 Fixed broken
	MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
References: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+0@gerrit.coreboot.org>
Message-ID: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+1@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/238

-gerrit

commit 1c4e003269ed43e3d46c60f56e62bcb1049a3fc0
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Thu Oct 6 18:21:19 2011 +0200

    Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
    
    AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB in SYSCFG_MSR to
    mark dram memory above 4GB as WB. However, AMD K8
    rev E and earlier don't implement this bit and therefore need
    MTRR spanning dram memory above 4GB. The current implementation
    of amd_setup_mtrrs never generate MTRR above 4GB.
    This caused memory > 4GB not to be recognized in e.g. Linux on those
    rev E or older platforms. This commit should fix that bug.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1
---
 src/cpu/amd/mtrr/amd_mtrr.c |   18 +++++++++++++++---
 1 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 623a344..93a3bba 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -112,7 +112,13 @@ void amd_setup_mtrrs(void)
 	struct mem_state state;
 	unsigned long i;
 	msr_t msr, sys_cfg;
-
+	// Test if this CPU is a Fam 0Fh rev. F or later
+	const int is_revF = 
+		((cpuid_eax(0x80000001)&0x00000f00)>>8 >= 0xf) ||
+		(((cpuid_eax(0x80000001)&0x00000f00)>>8 == 0xf) &&
+		 ((cpuid_eax(0x80000001)&0x000f0000)>>16 >= 0x4));
+	if(is_revF)
+		printk(BIOS_DEBUG, "Detected CPU Fam 0Fh rev.F or later\n");
 
 	/* Enable the access to AMD RdDram and WrDram extension bits */
 	disable_cache();
@@ -168,7 +174,9 @@ void amd_setup_mtrrs(void)
 		msr.hi = state.tomk >> 22;
 		msr.lo = state.tomk << 10;
 		wrmsr(TOP_MEM2, msr);
-		sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB;
+		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
+		if(is_revF)
+			sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
 	}
 
 	/* zero the IORR's before we enable to prevent
@@ -201,5 +209,9 @@ void amd_setup_mtrrs(void)
 	/* Now that I have mapped what is memory and what is not
 	 * Setup the mtrrs so we can cache the memory.
 	 */
-	x86_setup_var_mtrrs(address_bits, 0);
+
+	// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need
+	// variable MTRR to span memory above 4GB
+	// Lower revisions K8 need variable MTRR over 4GB
+	x86_setup_var_mtrrs(address_bits, is_revF ? 0 : 1);
 }



From yinghailu at gmail.com  Thu Oct  6 18:51:56 2011
From: yinghailu at gmail.com (yhlu)
Date: Thu, 6 Oct 2011 09:51:56 -0700
Subject: [coreboot] New patch to review for coreboot: 1c4e003 Fixed
 broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
In-Reply-To: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+1@gerrit.coreboot.org>
References: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+0@gerrit.coreboot.org>
	<Ie568a52a8eb355969c86964d5afc4692e60f69c1+1@gerrit.coreboot.org>
Message-ID: <CANeVWaMKdiccwrG1a-U7BczaV45oks5NVwdQCgq7YBkVneAcrQ@mail.gmail.com>

On Thu, Oct 6, 2011 at 9:26 AM, Oskar Enoksson <gerrit at coreboot.org> wrote:
> Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/238
>
> -gerrit
>
> commit 1c4e003269ed43e3d46c60f56e62bcb1049a3fc0
> Author: Oskar Enoksson <enok at lysator.liu.se>
> Date: ? Thu Oct 6 18:21:19 2011 +0200
>
> ? ?Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
>
> ? ?AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB in SYSCFG_MSR to
> ? ?mark dram memory above 4GB as WB. However, AMD K8
> ? ?rev E and earlier don't implement this bit and therefore need
> ? ?MTRR spanning dram memory above 4GB. The current implementation
> ? ?of amd_setup_mtrrs never generate MTRR above 4GB.
> ? ?This caused memory > 4GB not to be recognized in e.g. Linux on those
> ? ?rev E or older platforms. This commit should fix that bug.
>
> ? ?Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
> ? ?Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1
> ---
> ?src/cpu/amd/mtrr/amd_mtrr.c | ? 18 +++++++++++++++---
> ?1 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
> index 623a344..93a3bba 100644
> --- a/src/cpu/amd/mtrr/amd_mtrr.c
> +++ b/src/cpu/amd/mtrr/amd_mtrr.c
> @@ -112,7 +112,13 @@ void amd_setup_mtrrs(void)
> ? ? ? ?struct mem_state state;
> ? ? ? ?unsigned long i;
> ? ? ? ?msr_t msr, sys_cfg;
> -
> + ? ? ? // Test if this CPU is a Fam 0Fh rev. F or later
> + ? ? ? const int is_revF =
> + ? ? ? ? ? ? ? ((cpuid_eax(0x80000001)&0x00000f00)>>8 >= 0xf) ||
> + ? ? ? ? ? ? ? (((cpuid_eax(0x80000001)&0x00000f00)>>8 == 0xf) &&
> + ? ? ? ? ? ? ? ?((cpuid_eax(0x80000001)&0x000f0000)>>16 >= 0x4));
> + ? ? ? if(is_revF)
> + ? ? ? ? ? ? ? printk(BIOS_DEBUG, "Detected CPU Fam 0Fh rev.F or later\n");

should be configuration option instead of run-time checking.

There is no MB that will support revE and revF at same time. they are
different sockets

Yinghai



From gerrit at coreboot.org  Thu Oct  6 18:58:31 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Thu, 6 Oct 2011 18:58:31 +0200
Subject: [coreboot] New patch to review for coreboot: af6f38b Fixes several
	issues with amd k8 SSDT P-state generation
References: <I61f6e2210b84ccba33a36c5efc866447b7134417+0@gerrit.coreboot.org>
Message-ID: <I61f6e2210b84ccba33a36c5efc866447b7134417+1@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/239

-gerrit

commit af6f38bbfbf7702a5c432a6275e58dd13ce318bd
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Thu Oct 6 18:43:43 2011 +0200

    Fixes several issues with amd k8 SSDT P-state generation
    
    For multi-socket CPU the current implementation emitted
    Processor objects for cores in the first CPU only. This
    commit fixes the bug. One caveat though: the unlikely case
    of CPU's with different FID/VID capabilities mixed in the
    same system is not handled correctly.
    
    Second issue fixed: processors not supporting P-state
    transitions got no Processor objects at all. It's probably
    better to give them a Processor object with one single P-state.
    The old loop also looked wrong in case a processor
    in the table doesn't have any declared P-states at all. The
    rewritten loop is safe. Some possibly dangerous array
    lengths were also fixed.
    
    Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV
    according to the BKDG. The current implementation always set it
    to 25mV. This commit selects 0 or 25mV depending on if the
    number of populated CPU sockets is >1 or not.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417
---
 src/cpu/amd/model_fxx/powernow_acpi.c |  155 ++++++++++++++++++++++-----------
 1 files changed, 103 insertions(+), 52 deletions(-)

diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index bbcf013..65bbd90 100644
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -586,70 +586,121 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	u8 cmp_cap;
 	struct cpuentry *data = NULL;
 	uint32_t control;
-	int i = 0, index, len = 0, Pstate_num = 0;
+	int i = 0, index = 0, len = 0, Pstate_num = 0, isock = 0, nsock = 0;
 	msr_t msr;
-	u8 Pstate_fid[10];
-	u16 Pstate_feq[10];
-	u8 Pstate_vid[10];
-	u32 Pstate_power[10];
+	u8 Pstate_fid[MAXP+1];
+	u16 Pstate_feq[MAXP+1];
+	u8 Pstate_vid[MAXP+1];
+	u32 Pstate_power[MAXP+1];
 	u8 Max_fid, Start_fid, Start_vid, Max_vid;
 	struct cpuid_result cpuid1 = cpuid(0x80000001);
+	unsigned sockets[] = { 0x18, 0x19, 0x1a, 0x1b };
+	struct cpuentry entr_dummy = {.pstates[0].freqMhz = 0 };
 
-	msr = rdmsr(0xc0010042);
-	Max_fid = (msr.lo & 0x3F0000) >> 16;
-	Max_vid = (msr.hi & 0x3F0000) >> 16;
-	Start_fid = (msr.lo & 0x3F00) >> 8;
-	Start_vid = (msr.hi & 0x3F00) >> 8;
-
-	cmp_cap =
-	    (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
-	     0x3000) >> 12;
+	// Count number of populated sockets
+	for (isock = 0,nsock = 0; isock < ARRAY_SIZE(sockets); isock++) {
+		if(dev_find_slot(0, PCI_DEVFN(sockets[isock], 0))!=NULL)
+			nsock++;
+	}
+		
+	for (isock = 0; isock < ARRAY_SIZE(sockets); isock++) {
+		if(dev_find_slot(0, PCI_DEVFN(sockets[isock], 0))==NULL)
+			continue;
+		// TODO: We should read msr from the right CPU here
+		// The following only works if fid/vid values are identical on
+		// all CPU's
+		msr = rdmsr(0xc0010042);
+		Max_fid = (msr.lo & 0x3F0000) >> 16;
+		Max_vid = (msr.hi & 0x3F0000) >> 16;
+		Start_fid = (msr.lo & 0x3F00) >> 8;
+		Start_vid = (msr.hi & 0x3F00) >> 8;
+
+		cmp_cap =
+		    (pci_read_config16(dev_find_slot(0, PCI_DEVFN(sockets[isock], 3)), 0xE8) &
+		     0x3000) >> 12;
+
+		for (i = 0; i < ARRAY_SIZE(entr); i++) {
+			if ((entr[i].cpuid == cpuid1.eax)
+			    && (entr[i].startFID == Start_fid)
+			    && (entr[i].maxFID == Max_fid)
+			    && (entr[i].brandID == ((u8 )((cpuid1.ebx >> 6) & 0xff)))) {
+				data = &entr[i];
+				break;
+			}
+		}
 
-	for (i = 0; i < ARRAY_SIZE(entr); i++) {
-		if ((entr[i].cpuid == cpuid1.eax)
-		    && (entr[i].startFID == Start_fid)
-		    && (entr[i].maxFID == Max_fid)
-		    && (entr[i].brandID == ((u8 )((cpuid1.ebx >> 6) & 0xff)))) {
-			data = &entr[i];
+		if (data == NULL) {
+			printk(BIOS_WARNING, "Unknown CPU in socket %d, please update powernow_acpi.c\n",isock);
+			data = &entr_dummy;
+		}
+		/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
+		cpuid1 = cpuid(0x80000007);
+		switch ((cpuid1.edx & 0x6)) {
+		case 0x6:
+			break;
+		case 0x0:
+			printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
+			data = &entr_dummy;
+			break;
+		default:
+			printk(BIOS_WARNING, "Capability of performing P-state transitions unknown\n");
 			break;
 		}
-	}
-
-	if (data == NULL) {
-		printk(BIOS_WARNING, "Unknown CPU, please update the powernow_acpi.c\n");
-		return 0;
-	}
-
-	/* IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */
-	control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (1 << 29);
-	len = 0;
-	Pstate_num = 0;
 
-	Pstate_fid[Pstate_num] = Max_fid;
-	Pstate_feq[Pstate_num] = fid_to_freq(Max_fid);
-	Pstate_vid[Pstate_num] = Max_vid;
-	Pstate_power[Pstate_num] = data->pwr * 100;
-	Pstate_num++;
-
-	do {
-		Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
-		Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz;
-		Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage);
-		Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100;
+		if(nsock==1)
+			// IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us RVO = 50mV
+			control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (1 << 29);
+		else
+			// MP-systems should default to RVO=0mV (no ramp voltage)
+			// IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us RVO = 0mV
+			control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (0 << 29);
+		// RVO:  00   0mV (default for MP-systems)
+		//       01  25mV
+		//       10  50mV (default)
+		//       11  75mV
+		// IRT:  00  10uS
+		//       01  20uS
+		//       10  40uS
+		//       11  80uS (default)
+		// MVS:  00  25mV (default)
+		//       01  50mV (reserved)
+		//       10 100mV (reserved)
+		//       11 200mV (reserved)
+		// VST:  time is value*20uS  (default value: 5 => 100uS)
+		// PLL_LOCK_TIME: time is value*1uS (often seen value: 2uS)
+		//
+		
+		len = 0;
+		Pstate_num = 0;
+
+		Pstate_fid[Pstate_num] = Max_fid;
+		Pstate_feq[Pstate_num] = fid_to_freq(Max_fid);
+		Pstate_vid[Pstate_num] = Max_vid;
+		Pstate_power[Pstate_num] = data->pwr * 100;
 		Pstate_num++;
-	} while ((Pstate_num < MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0));
 
-	for (i=0;i<Pstate_num;i++)
-		printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,
-		       Pstate_feq[i],
-		       vid_from_reg(Pstate_vid[i]),
-		       Pstate_power[i]);
+		while ((Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0)) {
+			Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
+			Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz;
+			Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage);
+			Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100;
+			Pstate_num++;
+		}
 
-	for (index = 0; index < (cmp_cap + 1); index++) {
-		len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
-				Pstate_fid, Pstate_power, index,
-				pcontrol_blk, plen, onlyBSP, control);
+		for (i=0;i<Pstate_num;i++)
+			printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,
+			       Pstate_feq[i],
+			       vid_from_reg(Pstate_vid[i]),
+			       Pstate_power[i]);
+
+		for (i = 0; i < cmp_cap + 1; i++) {
+			len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
+					Pstate_fid, Pstate_power, index+i,
+					pcontrol_blk, plen, onlyBSP, control);
+		}
+		index += i;
 	}
+	printk(BIOS_DEBUG,"%d Processor objects will be emitted to SSDT\n",index);
 
 	return len;
 }



From gerrit at coreboot.org  Thu Oct  6 19:09:01 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Thu, 6 Oct 2011 19:09:01 +0200
Subject: [coreboot] Patch set updated for coreboot: 4780961 Fixed broken
	MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
References: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+0@gerrit.coreboot.org>
Message-ID: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+2@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/238

-gerrit

commit 478096179cbc7c777641dda7ac1a7f1cce7d400e
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Thu Oct 6 18:21:19 2011 +0200

    Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
    
    AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB in SYSCFG_MSR to
    mark dram memory above 4GB as WB. However, AMD K8
    rev E and earlier don't implement this bit and therefore need
    MTRR spanning dram memory above 4GB. The current implementation
    of amd_setup_mtrrs never generate MTRR above 4GB.
    This caused memory > 4GB not to be recognized in e.g. Linux on those
    rev E or older platforms. This commit should fix that bug.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1
---
 src/cpu/amd/mtrr/amd_mtrr.c |   19 ++++++++++++++++---
 1 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 623a344..7d15b84 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -112,7 +112,14 @@ void amd_setup_mtrrs(void)
 	struct mem_state state;
 	unsigned long i;
 	msr_t msr, sys_cfg;
-
+	// Test if this CPU is a Fam 0Fh rev. F or later
+	const int cpu_id = cpuid_eax(0x80000001);
+	const int is_revF = 
+		 (((cpu_id>>8 )&0xf) >= 0xf) || // Family > 0F
+		((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F
+		 (((cpu_id>>16)&0xf) >= 0x4));  // Rev>=F deduced from rev tables
+	if(is_revF)
+		printk(BIOS_DEBUG, "Detected CPU Fam 0Fh rev.F or later\n");
 
 	/* Enable the access to AMD RdDram and WrDram extension bits */
 	disable_cache();
@@ -168,7 +175,9 @@ void amd_setup_mtrrs(void)
 		msr.hi = state.tomk >> 22;
 		msr.lo = state.tomk << 10;
 		wrmsr(TOP_MEM2, msr);
-		sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB;
+		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
+		if(is_revF)
+			sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
 	}
 
 	/* zero the IORR's before we enable to prevent
@@ -201,5 +210,9 @@ void amd_setup_mtrrs(void)
 	/* Now that I have mapped what is memory and what is not
 	 * Setup the mtrrs so we can cache the memory.
 	 */
-	x86_setup_var_mtrrs(address_bits, 0);
+
+	// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need
+	// variable MTRR to span memory above 4GB
+	// Lower revisions K8 need variable MTRR over 4GB
+	x86_setup_var_mtrrs(address_bits, is_revF ? 0 : 1);
 }



From enok at lysator.liu.se  Thu Oct  6 19:33:36 2011
From: enok at lysator.liu.se (Oskar Enoksson)
Date: Thu, 06 Oct 2011 19:33:36 +0200
Subject: [coreboot] New patch to review for coreboot: 1c4e003 Fixed
 broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
In-Reply-To: <CANeVWaMKdiccwrG1a-U7BczaV45oks5NVwdQCgq7YBkVneAcrQ@mail.gmail.com>
References: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+0@gerrit.coreboot.org>	<Ie568a52a8eb355969c86964d5afc4692e60f69c1+1@gerrit.coreboot.org>
	<CANeVWaMKdiccwrG1a-U7BczaV45oks5NVwdQCgq7YBkVneAcrQ@mail.gmail.com>
Message-ID: <4E8DE670.5000701@lysator.liu.se>

On 10/06/2011 06:51 PM, yhlu wrote:
> On Thu, Oct 6, 2011 at 9:26 AM, Oskar Enoksson<gerrit at coreboot.org>  wrote:
>> -
>> +       // Test if this CPU is a Fam 0Fh rev. F or later
>> +       const int is_revF =
>> +               ((cpuid_eax(0x80000001)&0x00000f00)>>8>= 0xf) ||
>> +               (((cpuid_eax(0x80000001)&0x00000f00)>>8 == 0xf)&&
>> +                ((cpuid_eax(0x80000001)&0x000f0000)>>16>= 0x4));
>> +       if(is_revF)
>> +               printk(BIOS_DEBUG, "Detected CPU Fam 0Fh rev.F or later\n");
> should be configuration option instead of run-time checking.
>
> There is no MB that will support revE and revF at same time. they are
> different sockets
>
> Yinghai
So, is it CONFIG_K8_REV_F_SUPPORT == 1 I should use?




From r.marek at assembler.cz  Thu Oct  6 23:02:39 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 06 Oct 2011 23:02:39 +0200
Subject: [coreboot] FID/VID change and display flicker
In-Reply-To: <4E89532A.5060100@assembler.cz>
References: <4E89532A.5060100@assembler.cz>
Message-ID: <4E8E176F.2060204@assembler.cz>

Hi all,

I still got the flicker. I checked so far:

PMM settings in the CPU.
LDTSTOP length is SB
HTIU settings with regards of FID/VID change and ALLOW_LDTSTOP
Settings fro the VGA BIOS.

I found in RPR 880 guide (46141_rs880_rpr_pub_3.00.pdf)

8.8.3 ATIVumaSysInfoRev3 Programming
       The system BIOS is responsible for filling in the ATIVumaSysInfoRev3 
table when the video BIOS calls GetIntegratedSystemInformation via INT 15h. The 
table parameters are used by the video BIOS and the video driver to support the 
"C1e/C3/Stutter Mode" feature and the "PowerNow!/Cool'nQuiet" feature. This 
section explains how to program the table entries k8SyncStartDly and k8DataRetTime.

This seems wrong to me, I'm not aware of any 15h interface. Everything is 
handled through the ATOM BIOS in gfx.c where those values seems hardcoded.

Does the 15h interface exists? Or the documentation is wrong?

The HTIU settings:

42dfa202 is coreboot HTIU 0x6
071081c9 is coreboot HTIU 0x7

I'm bit confused that HTIU 7 bits 1 and 2 should be 0, but the guide is telling so.

delay_STPCLK_en 1 0x1 Holds off upstream SMC STPCLK for FID message until
                       DISP_ALLOW_LDTSTOP is asserted. During this time,
                       only DISP can issue request.
                         0=Disable
                         1=Enable
delay_FID_en    2 0x1 Holds off upstream SMC FID message until
                       DISP_ALLOW_LDTSTOP is asserted. Note: This bit should
                       always be set to 0.
                         0=Disable

I checked all PMIO settings and PMM settings and still flicker. I checked also 
the PSS object itself, the only difference is is that I use different VID for 
two highest P-states than the asrock bios. Latency settings etc is the same.

I tried even disassembling the ATOM tables and it only differs in 
ulmemoryclock/bootupumaclock which is 0 in orig bios and 16600 in coreboot.

So... Why I still got the flicker? Is there any other HTIU settings I missed? Or 
what else should I check.

Thanks
Rudolf




On 3.10.2011 08:16, Rudolf Marek wrote:
> Hi all,
>
> I finally moved my desktop to the Asrock socket 939 board with 785G/SB700 +
> coreboot. So far even with 6 harddrives and 2GB RAM everything works :)
>
> I only noticed a flicker if CPU freq/voltage changes. I briefly chekced the
> LDTSTOP settings in SB and also in HTIU in NB so far it makes sense. Is it a bug
> or feature? I admit I did not check with original BIOS.
>
> Thanks
> Rudolf




From gerrit at coreboot.org  Fri Oct  7 00:52:19 2011
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Fri, 7 Oct 2011 00:52:19 +0200
Subject: [coreboot] New patch to review for coreboot: f58d203 Don't do a
	call as the first instruction in libpayload.
References: <Ie6f6748a471324b29ebad045c807dfc9f4b92034+0@gerrit.coreboot.org>
Message-ID: <Ie6f6748a471324b29ebad045c807dfc9f4b92034+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/240

-gerrit

commit f58d203a35b5a75feb3a17319a83d41385852a9f
Author: Marc Jones <marcj303 at gmail.com>
Date:   Thu Oct 6 16:38:35 2011 -0600

    Don't do a call as the first instruction in libpayload.
    
    Doing a call before the payload has set up its stack is risky. The stack may not be in a favorable location. Normally this is not an issue with coreboot or other well behaved callers.
    
    Change-Id: Ie6f6748a471324b29ebad045c807dfc9f4b92034
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 payloads/libpayload/arch/i386/head.S |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/payloads/libpayload/arch/i386/head.S b/payloads/libpayload/arch/i386/head.S
index 88db412..3dd6133 100644
--- a/payloads/libpayload/arch/i386/head.S
+++ b/payloads/libpayload/arch/i386/head.S
@@ -38,10 +38,7 @@
  * change anything.
  */
 _entry:
-	call _init
-
-	/* We're back - go back to the bootloader. */
-	ret
+	jmp _init
 
 	.align 4
 
@@ -66,6 +63,9 @@ _init:
 	/* No interrupts, please. */
 	cli
 
+	/* There is a bunch of stuff missing here to take arguments on the stack
+	 * See http://www.coreboot.org/Payload_API and exec.S.
+	 */
 	/* Store current stack pointer. */
 	movl %esp, %esi
 



From gerrit at coreboot.org  Fri Oct  7 00:58:38 2011
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Fri, 7 Oct 2011 00:58:38 +0200
Subject: [coreboot] Patch set updated for coreboot: 9a43592 Don't do a call
	as the first instruction in libpayload.
References: <Ie6f6748a471324b29ebad045c807dfc9f4b92034+0@gerrit.coreboot.org>
Message-ID: <Ie6f6748a471324b29ebad045c807dfc9f4b92034+2@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/240

-gerrit

commit 9a4359203d961e591e8f3dfe32045608117c918a
Author: Marc Jones <marcj303 at gmail.com>
Date:   Thu Oct 6 16:38:35 2011 -0600

    Don't do a call as the first instruction in libpayload.
    
    Doing a call before the payload has set up its stack is risky. The stack may
    not be in a favorable location. Normally this is not an issue with coreboot
    or other well behaved callers.
    
    Change-Id: Ie6f6748a471324b29ebad045c807dfc9f4b92034
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 payloads/libpayload/arch/i386/head.S |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/payloads/libpayload/arch/i386/head.S b/payloads/libpayload/arch/i386/head.S
index 88db412..3dd6133 100644
--- a/payloads/libpayload/arch/i386/head.S
+++ b/payloads/libpayload/arch/i386/head.S
@@ -38,10 +38,7 @@
  * change anything.
  */
 _entry:
-	call _init
-
-	/* We're back - go back to the bootloader. */
-	ret
+	jmp _init
 
 	.align 4
 
@@ -66,6 +63,9 @@ _init:
 	/* No interrupts, please. */
 	cli
 
+	/* There is a bunch of stuff missing here to take arguments on the stack
+	 * See http://www.coreboot.org/Payload_API and exec.S.
+	 */
 	/* Store current stack pointer. */
 	movl %esp, %esi
 



From gerrit at coreboot.org  Fri Oct  7 01:38:50 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Fri, 7 Oct 2011 01:38:50 +0200
Subject: [coreboot] Patch set updated for coreboot: b92ae6b Fixed broken
	MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
References: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+0@gerrit.coreboot.org>
Message-ID: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+3@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/238

-gerrit

commit b92ae6b8fd0dba5ac8472ce91c7a0a2b5f6e774c
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Thu Oct 6 18:21:19 2011 +0200

    Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
    
    AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB in SYSCFG_MSR to
    mark dram memory above 4GB as WB. However, AMD K8
    rev E and earlier don't implement this bit and therefore need
    MTRR spanning dram memory above 4GB. The current implementation
    of amd_setup_mtrrs never generate MTRR above 4GB.
    This caused memory > 4GB not to be recognized in e.g. Linux on those
    rev E or older platforms. This commit should fix that bug.
    I use the value of CONFIG_K8_REV_F_SUPPORT (I hope I've
    understood it's meaning correctly).
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1
---
 src/cpu/amd/mtrr/amd_mtrr.c |   14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 623a344..6066284 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -113,7 +113,6 @@ void amd_setup_mtrrs(void)
 	unsigned long i;
 	msr_t msr, sys_cfg;
 
-
 	/* Enable the access to AMD RdDram and WrDram extension bits */
 	disable_cache();
 	sys_cfg = rdmsr(SYSCFG_MSR);
@@ -168,7 +167,10 @@ void amd_setup_mtrrs(void)
 		msr.hi = state.tomk >> 22;
 		msr.lo = state.tomk << 10;
 		wrmsr(TOP_MEM2, msr);
-		sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB;
+		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
+#if CONFIG_K8_REV_F_SUPPORT == 1
+		sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
+#endif
 	}
 
 	/* zero the IORR's before we enable to prevent
@@ -201,5 +203,13 @@ void amd_setup_mtrrs(void)
 	/* Now that I have mapped what is memory and what is not
 	 * Setup the mtrrs so we can cache the memory.
 	 */
+
+	// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need
+	// variable MTRR to span memory above 4GB
+	// Lower revisions K8 need variable MTRR over 4GB
+#if CONFIG_K8_REV_F_SUPPORT == 1
 	x86_setup_var_mtrrs(address_bits, 0);
+#else
+	x86_setup_var_mtrrs(address_bits, 1);
+#endif
 }



From alperenkose at buyutech.com.tr  Fri Oct  7 10:07:18 2011
From: alperenkose at buyutech.com.tr (=?ISO-8859-1?Q?Alp_Eren_K=F6se?=)
Date: Fri, 7 Oct 2011 11:07:18 +0300
Subject: [coreboot] Coreboot on Axiomtek PICO821
In-Reply-To: <CAOXdWGvmtDHBePi+SxiKOsyJpFD2DO-H+RgSEO+VrrLhtnsD-g@mail.gmail.com>
References: <CAOz08zFfKpUprX76LeO5NCtJUXtgwUG0mxM1FVH_0-5gPv2pEA@mail.gmail.com>
	<CAOz08zEMc1EjetFPeAhSOsf5ht=rKLq1Zo3CAqrbyw3C+13QGQ@mail.gmail.com>
	<CAOXdWGvmtDHBePi+SxiKOsyJpFD2DO-H+RgSEO+VrrLhtnsD-g@mail.gmail.com>
Message-ID: <CAOz08zHUvpiUzZVJ4vsAAZ8MDpzrpXKP598ozfuOBL7K8EAKfw@mail.gmail.com>

> 1. Make sure you can recover from a bad image (extra flash chip with
> the original BIOS)

Ok, I have got a spare rom which is a "SST SST49LF008A" (1024 KB, FWH) with
the original bios, but i don't have an external programmer to flash if the
first one is bricked..

> 2. Make sure you can get serial output

I believe I can do it, the board has an RS232 port, so I guess i need a null
modem cable to connect it to the computer..

> 3. Choose the most similar supported motherboard

I guess it is the iWave iW-RainboW-G6 as Idwer Vollering suggested..

> 4. Change the code to support your board

Well this is a little problem, I don't know exactly where and what to change
in the code,
I believe i need to make a copy of src/mainboard/iwave/iWRainbowG6 and
modify files to fit it my mainboard..
I have some C knowledge, but I would really need help, and some people to
show me the way what and where to change in the code at least to make it
work?

> 5. Try it
> 6. Iterate on 4&5 until you're happy with it
> 7. Send a patch

I would for sure send a patch if I can make it work :)
Btw the CPU and the southbridge/northbridge matches with the Rainbow-G6, but
I don't know about the SuperIO of it, there is just a "-" in the list of
supported motherboards for superIO of Rainbow-G6..

Thanks in advance,
Alp

2011/10/5 Myles Watson <mylesgw at gmail.com>

> 2011/10/5 Alp Eren K?se <alperenkose at buyutech.com.tr>:
> > Anyone has an idea?
> >
> > Another question is I can't find my mainboard vendor "Axiomtek" in
> Mainboard
> > Vendor selection list in menuconfig as expectedly, but all the chips and
> > chipset of it seem to be supported as I see them in coreboot website. Is
> it
> > still possible to install coreboot, if so how can I do it?
> > It would be really nice if someone could point a way..
>
> Generally the steps are:
> 1. Make sure you can recover from a bad image (extra flash chip with
> the original BIOS)
> 2. Make sure you can get serial output
> 3. Choose the most similar supported motherboard
> 4. Change the code to support your board
> 5. Try it
> 6. Iterate on 4&5 until you're happy with it
> 7. Send a patch
>
> If you don't have 1 & 2 you shouldn't try at all.
>
> Good luck!
> Myles
>
-------------- next part --------------
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From vidwer at gmail.com  Fri Oct  7 12:41:10 2011
From: vidwer at gmail.com (Idwer Vollering)
Date: Fri, 7 Oct 2011 12:41:10 +0200
Subject: [coreboot] Coreboot on Axiomtek PICO821
In-Reply-To: <CAOz08zHUvpiUzZVJ4vsAAZ8MDpzrpXKP598ozfuOBL7K8EAKfw@mail.gmail.com>
References: <CAOz08zFfKpUprX76LeO5NCtJUXtgwUG0mxM1FVH_0-5gPv2pEA@mail.gmail.com>
	<CAOz08zEMc1EjetFPeAhSOsf5ht=rKLq1Zo3CAqrbyw3C+13QGQ@mail.gmail.com>
	<CAOXdWGvmtDHBePi+SxiKOsyJpFD2DO-H+RgSEO+VrrLhtnsD-g@mail.gmail.com>
	<CAOz08zHUvpiUzZVJ4vsAAZ8MDpzrpXKP598ozfuOBL7K8EAKfw@mail.gmail.com>
Message-ID: <CAPp9OrnPXASNvtxMQFGz6VtktR1U7o2m8G7yNU7_6PTMzqHh3g@mail.gmail.com>

2011/10/7 Alp Eren K?se <alperenkose at buyutech.com.tr>:
>
>> 1. Make sure you can recover from a bad image (extra flash chip with
>> the original BIOS)
>
> Ok, I have got a spare rom which is a "SST SST49LF008A" (1024 KB, FWH) with
> the original bios, but i don't have an external programmer to flash if the
> first one is bricked..

If you store that spare rom in a safe place and only use it to boot
from, you don't need an external programmer. A often used trick to
ease removal is to glue a handle to the chip:
http://www.settoplinux.org/images/thumb/5/56/Push_pin2.jpg/500px-Push_pin2.jpg

>
>> 2. Make sure you can get serial output
>
> I believe I can do it, the board has an RS232 port, so I guess i need a null
> modem cable to connect it to the computer..
>
>> 3. Choose the most similar supported motherboard
>
> I guess it is the iWave iW-RainboW-G6 as Idwer Vollering suggested..
>
>> 4. Change the code to support your board
>
> Well this is a little problem, I don't know exactly where and what to change
> in the code,
> I believe i need to make a copy of src/mainboard/iwave/iWRainbowG6 and
> modify files to fit it my mainboard..

0) Compile crossgcc: run "make crossgcc" in the top source directory
1) Edit src/mainboard/Kconfig
2) Make a directory named axiomtek/pico821 in src/mainboard/ (run this
in the top source code directory: mkdir -p src/mainboard
/axiomtek/pico821 )
3) Add the file src/mainboard/axiomtek/Kconfig and edit that file,
you'll want to take src/mainboard/iwave/iWRainbowG6/Kconfig as an
example.
4) Copy the files from the iwave board (cd
src/mainboard/iwave/iWRainbowG6/ ; cp -r * ../../axiomtek/pico821/ ),
edit at least devicetree.cb, Kconfig and mainboard.c. Then replace the
names but keep the (C) copyright headers.
5) "cd" back into the top source dir and run "make menuconfig ; make"
(or make xconfig/gconfig) where you select the axiomtek mainboard.
Exit the menu, save the configuration and run "make"; after a minute
or so you should have the file build/coreboot.rom which you'll have to
program into the first chip.
6) Make sure that you have stored the spare rom in a safe place, then
download, compile and install flashrom:
http://www.flashrom.org/Downloads#Installation_from_source

http://www.coreboot.org/Developer_Manual#How_to_support_a_new_board

> I have some C knowledge, but I would really need help, and some people to
> show me the way what and where to change in the code at least to make it
> work?
>
>> 5. Try it
>> 6. Iterate on 4&5 until you're happy with it
>> 7. Send a patch
>
> I would for sure send a patch if I can make it work :)
> Btw the CPU and the southbridge/northbridge matches with the Rainbow-G6, but
> I don't know about the SuperIO of it, there is just a "-" in the list of
> supported motherboards for superIO of Rainbow-G6..

Compile and run superiotool, it's in util/superiotool/

>
> Thanks in advance,
> Alp
>
> 2011/10/5 Myles Watson <mylesgw at gmail.com>
>>
>> 2011/10/5 Alp Eren K?se <alperenkose at buyutech.com.tr>:
>> > Anyone has an idea?
>> >
>> > Another question is I can't find my mainboard vendor "Axiomtek" in
>> > Mainboard
>> > Vendor selection list in menuconfig as expectedly, but all the chips and
>> > chipset of it seem to be supported as I see them in coreboot website. Is
>> > it
>> > still possible to install coreboot, if so how can I do it?
>> > It would be really nice if someone could point a way..
>>
>> Generally the steps are:
>> 1. Make sure you can recover from a bad image (extra flash chip with
>> the original BIOS)
>> 2. Make sure you can get serial output
>> 3. Choose the most similar supported motherboard
>> 4. Change the code to support your board
>> 5. Try it
>> 6. Iterate on 4&5 until you're happy with it
>> 7. Send a patch
>>
>> If you don't have 1 & 2 you shouldn't try at all.
>>
>> Good luck!
>> Myles
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From alperenkose at buyutech.com.tr  Fri Oct  7 15:19:21 2011
From: alperenkose at buyutech.com.tr (=?ISO-8859-1?Q?Alp_Eren_K=F6se?=)
Date: Fri, 7 Oct 2011 16:19:21 +0300
Subject: [coreboot] Coreboot on Axiomtek PICO821
In-Reply-To: <CAPp9OrnPXASNvtxMQFGz6VtktR1U7o2m8G7yNU7_6PTMzqHh3g@mail.gmail.com>
References: <CAOz08zFfKpUprX76LeO5NCtJUXtgwUG0mxM1FVH_0-5gPv2pEA@mail.gmail.com>
	<CAOz08zEMc1EjetFPeAhSOsf5ht=rKLq1Zo3CAqrbyw3C+13QGQ@mail.gmail.com>
	<CAOXdWGvmtDHBePi+SxiKOsyJpFD2DO-H+RgSEO+VrrLhtnsD-g@mail.gmail.com>
	<CAOz08zHUvpiUzZVJ4vsAAZ8MDpzrpXKP598ozfuOBL7K8EAKfw@mail.gmail.com>
	<CAPp9OrnPXASNvtxMQFGz6VtktR1U7o2m8G7yNU7_6PTMzqHh3g@mail.gmail.com>
Message-ID: <CAOz08zGPT3YaMwa0ZuOQ5nzjWA=GhvDo3Wc3D1PskD9r_Td0uA@mail.gmail.com>

> If you store that spare rom in a safe place and only use it to boot
> from, you don't need an external programmer. A often used trick to
> ease removal is to glue a handle to the chip:
>
http://www.settoplinux.org/images/thumb/5/56/Push_pin2.jpg/500px-Push_pin2.jpg

Ok, if I understand it right, when I brick the first rom, I can boot using
the second one into a freedos, remove the rom while the system is running
and put the bricked rom in and flash the original BIOS, is that correct??
The pin trick is very nice btw:)

> 4) Copy the files from the iwave board (cd
src/mainboard/iwave/iWRainbowG6/ ; cp -r * ../../axiomtek/pico821/ ),
> edit at least devicetree.cb, Kconfig and mainboard.c. Then replace the
names but keep the (C) copyright headers.

I suppose I will edit devicetree.cb file according to my lspci output, but I
didn't get how to modify the lines similar to following:
chip southbridge/intel/sch
            register "pirqa_routing" = "0xa"
            register "pirqb_routing" = "0xb"
Are those something about IRQ routing? my board also have Intel SCH so I
hope they are the same..

And there is not much in mainboard.c file, I couldn't see much to change
apart from the CHIP_NAME?

> Compile and run superiotool, it's in util/superiotool/

I have run it on my board, i have an " Winbond W83627HF/F/HG/G (id=0x52,
rev=0x41)", but I don't know what iWRainbowG6 has on it? I looked at the
code, but couldn't figure what it's SuperIO chip is? Anyone know, or own
this board, could tell me?

Sorry it's been lots of questions, thank you very much for guiding,
Thanks in advance,
Alp

2011/10/7 Idwer Vollering <vidwer at gmail.com>

> 2011/10/7 Alp Eren K?se <alperenkose at buyutech.com.tr>:
> >
> >> 1. Make sure you can recover from a bad image (extra flash chip with
> >> the original BIOS)
> >
> > Ok, I have got a spare rom which is a "SST SST49LF008A" (1024 KB, FWH)
> with
> > the original bios, but i don't have an external programmer to flash if
> the
> > first one is bricked..
>
> If you store that spare rom in a safe place and only use it to boot
> from, you don't need an external programmer. A often used trick to
> ease removal is to glue a handle to the chip:
>
> http://www.settoplinux.org/images/thumb/5/56/Push_pin2.jpg/500px-Push_pin2.jpg
>
> >
> >> 2. Make sure you can get serial output
> >
> > I believe I can do it, the board has an RS232 port, so I guess i need a
> null
> > modem cable to connect it to the computer..
> >
> >> 3. Choose the most similar supported motherboard
> >
> > I guess it is the iWave iW-RainboW-G6 as Idwer Vollering suggested..
> >
> >> 4. Change the code to support your board
> >
> > Well this is a little problem, I don't know exactly where and what to
> change
> > in the code,
> > I believe i need to make a copy of src/mainboard/iwave/iWRainbowG6 and
> > modify files to fit it my mainboard..
>
> 0) Compile crossgcc: run "make crossgcc" in the top source directory
> 1) Edit src/mainboard/Kconfig
> 2) Make a directory named axiomtek/pico821 in src/mainboard/ (run this
> in the top source code directory: mkdir -p src/mainboard
> /axiomtek/pico821 )
> 3) Add the file src/mainboard/axiomtek/Kconfig and edit that file,
> you'll want to take src/mainboard/iwave/iWRainbowG6/Kconfig as an
> example.
> 4) Copy the files from the iwave board (cd
> src/mainboard/iwave/iWRainbowG6/ ; cp -r * ../../axiomtek/pico821/ ),
> edit at least devicetree.cb, Kconfig and mainboard.c. Then replace the
> names but keep the (C) copyright headers.
> 5) "cd" back into the top source dir and run "make menuconfig ; make"
> (or make xconfig/gconfig) where you select the axiomtek mainboard.
> Exit the menu, save the configuration and run "make"; after a minute
> or so you should have the file build/coreboot.rom which you'll have to
> program into the first chip.
> 6) Make sure that you have stored the spare rom in a safe place, then
> download, compile and install flashrom:
> http://www.flashrom.org/Downloads#Installation_from_source
>
> http://www.coreboot.org/Developer_Manual#How_to_support_a_new_board
>
> > I have some C knowledge, but I would really need help, and some people to
> > show me the way what and where to change in the code at least to make it
> > work?
> >
> >> 5. Try it
> >> 6. Iterate on 4&5 until you're happy with it
> >> 7. Send a patch
> >
> > I would for sure send a patch if I can make it work :)
> > Btw the CPU and the southbridge/northbridge matches with the Rainbow-G6,
> but
> > I don't know about the SuperIO of it, there is just a "-" in the list of
> > supported motherboards for superIO of Rainbow-G6..
>
> Compile and run superiotool, it's in util/superiotool/
>
> >
> > Thanks in advance,
> > Alp
> >
> > 2011/10/5 Myles Watson <mylesgw at gmail.com>
> >>
> >> 2011/10/5 Alp Eren K?se <alperenkose at buyutech.com.tr>:
> >> > Anyone has an idea?
> >> >
> >> > Another question is I can't find my mainboard vendor "Axiomtek" in
> >> > Mainboard
> >> > Vendor selection list in menuconfig as expectedly, but all the chips
> and
> >> > chipset of it seem to be supported as I see them in coreboot website.
> Is
> >> > it
> >> > still possible to install coreboot, if so how can I do it?
> >> > It would be really nice if someone could point a way..
> >>
> >> Generally the steps are:
> >> 1. Make sure you can recover from a bad image (extra flash chip with
> >> the original BIOS)
> >> 2. Make sure you can get serial output
> >> 3. Choose the most similar supported motherboard
> >> 4. Change the code to support your board
> >> 5. Try it
> >> 6. Iterate on 4&5 until you're happy with it
> >> 7. Send a patch
> >>
> >> If you don't have 1 & 2 you shouldn't try at all.
> >>
> >> Good luck!
> >> Myles
> >
> >
> > --
> > coreboot mailing list: coreboot at coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
> >
>
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From gerrit at coreboot.org  Fri Oct  7 15:47:10 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 7 Oct 2011 15:47:10 +0200
Subject: [coreboot] New patch to review for coreboot: ae3a08a amd/sb600:
	Enable COM2 at all times in early setup
References: <I886f98b715c1f384c8693f2977671ff15897b5a5+0@gerrit.coreboot.org>
Message-ID: <I886f98b715c1f384c8693f2977671ff15897b5a5+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/241

-gerrit

commit ae3a08acb2fb105e35f218f810619b48f4501f76
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Fri Oct 7 14:43:27 2011 +0200

    amd/sb600: Enable COM2 at all times in early setup
    
    Otherwise with a coreboot log on COM2 (which doesn't work) the boot
    process takes eons.
    
    Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/southbridge/amd/sb600/early_setup.c |    9 ++++-----
 1 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index 838ea31..5ffd3d8 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -53,11 +53,11 @@ static u8 get_sb600_revision(void)
 
 /***************************************
 * Legacy devices are mapped to LPC space.
-*	Serial port 0
+*	Serial port 0, 1
 *	KBC Port
 *	ACPI Micro-controller port
 *	This function does not change port 0x80 decoding.
-*	Console output through any port besides 0x3f8 is unsupported.
+*	Console output through any port besides 0x2f8/0x3f8 is unsupported.
 *	If you use FWH ROMs, you have to setup IDSEL.
 * Reviewed-by: Carl-Daniel Hailfinger
 * Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1
@@ -84,10 +84,9 @@ static void sb600_lpc_init(void)
 	pci_write_config32(dev, 0x64, reg32);
 
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);	/* LPC Controller */
-	/* Decode port 0x3f8-0x3ff (Serial 0) */
-	// XXX Serial port decode on LPC is hardcoded to 0x3f8
+	/* Decode port 0x3f8-0x3ff (Serial 0), 0x2f8-0x2ff (Serial 1) */
 	reg8 = pci_read_config8(dev, 0x44);
-	reg8 |= 1 << 6;
+	reg8 |= (1 << 6) | (1 << 7);
 	pci_write_config8(dev, 0x44, reg8);
 
 	/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/



From gerrit at coreboot.org  Fri Oct  7 15:47:10 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 7 Oct 2011 15:47:10 +0200
Subject: [coreboot] New patch to review for coreboot: 84628e8
	siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
References: <I4d2a10c9b45306ac6e6026a31765d3b912fd855c+0@gerrit.coreboot.org>
Message-ID: <I4d2a10c9b45306ac6e6026a31765d3b912fd855c+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/242

-gerrit

commit 84628e8a3e0f67d638d62af7910ebaab8f85e855
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Oct 6 14:34:22 2011 +0200

    siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
    
    Each variable is essentially unused or incorrect.
    
    Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c |   23 +---------------------
 src/mainboard/siemens/sitemp_g1p1/irq_tables.c   |    1 -
 src/mainboard/siemens/sitemp_g1p1/mptable.c      |   14 ++++--------
 3 files changed, 6 insertions(+), 32 deletions(-)

diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
index 24b9f28..2b0fca7 100644
--- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
+++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
@@ -32,7 +32,6 @@
 /* Global variables for MB layouts and these will be shared by irqtable mptable
 * and acpi_tables busnum is default.
 */
-u8 bus_isa;
 u8 bus_rs690[8];
 u8 bus_sb600[2];
 u32 apicid_sb600;
@@ -54,8 +53,6 @@ u32 hcdnx[] = {
 	0x20202020,
 };
 
-u32 bus_type[256];
-
 u32 sbdn_rs690;
 u32 sbdn_sb600;
 
@@ -67,7 +64,7 @@ void get_bus_conf(void)
 {
 	u32 apicid_base;
 	device_t dev;
-	int i, j;
+	int i;
 
 	if (get_bus_conf_done == 1)
 		return;		/* do it only once */
@@ -92,25 +89,13 @@ void get_bus_conf(void)
 		bus_rs690[i] = 0;
 	}
 
-	for (i = 0; i < 256; i++) {
-		bus_type[i] = 0; /* default ISA bus. */
-	}
-
-	bus_type[0] = 1;	/* pci */
-
 	bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 	bus_sb600[0] = bus_rs690[0];
 
-	bus_type[bus_rs690[0]] = 1;
-
 	/* sb600 */
 	dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
 	if (dev) {
 		bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-		bus_isa++;
-		for (j = bus_sb600[1]; j < bus_isa; j++)
-			bus_type[j] = 1;
 	}
 
 	/* rs690 */
@@ -118,16 +103,10 @@ void get_bus_conf(void)
 		dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
 		if (dev) {
 			bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-			if(255 != bus_rs690[i]) {
-				bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-				bus_isa++;
-				bus_type[bus_rs690[i]] = 1; /* PCI bus. */
-			}
 		}
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-	bus_isa = 10;
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(1);
 #else
diff --git a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
index 63b532d..b2a9668 100644
--- a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
+++ b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
@@ -68,7 +68,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 	pirq_info->slot = slot;
 	pirq_info->rfu = rfu;
 }
-extern u8 bus_isa;
 extern u8 bus_rs690[8];
 extern u8 bus_sb600[2];
 extern unsigned long sbdn_sb600;
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index df2f77b..d5b18ec 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -26,13 +26,11 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern u8 bus_isa;
 extern u8 bus_rs690[8];
 extern u8 bus_sb600[2];
 
 extern u32 apicid_sb600;
 
-extern u32 bus_type[256];
 extern u32 sbdn_rs690;
 extern u32 sbdn_sb600;
 
@@ -46,12 +44,9 @@ static void *smp_write_config_table(void *v)
 	smp_write_processors(mc);
 
 	get_bus_conf();
-	printk(BIOS_DEBUG, "%s: bus_isa=%d, apic_id=0x%x\n", __func__, bus_isa, apicid_sb600);
+	printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600);
 
 	mptable_write_buses(mc, NULL, &isa_bus);
-	if (isa_bus != bus_isa) {
-		printk(BIOS_ERR, "ISA bus numbering schemes differ! Please fix mptable.c\n");
-	}
 	/* I/O APICs:   APIC ID Version State   Address */
 	{
 		device_t dev;
@@ -63,10 +58,11 @@ static void *smp_write_config_table(void *v)
 			smp_write_ioapic(mc, apicid_sb600, 0x20, res->base);
 		}
 	}
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
+	mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0);
+
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
 
 	/* Compute the checksums */
 	mc->mpe_checksum =



From gerrit at coreboot.org  Fri Oct  7 15:47:10 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 7 Oct 2011 15:47:10 +0200
Subject: [coreboot] New patch to review for coreboot: b768713
	siemens/sitemp_g1p1: Don't mess with virtual wire settings
References: <I4ddd25fef57bed64877959ca96cca68170042bca+0@gerrit.coreboot.org>
Message-ID: <I4ddd25fef57bed64877959ca96cca68170042bca+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/243

-gerrit

commit b7687135f3d1f17fcaa3c47c9856319ac7ab7645
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Oct 6 15:24:08 2011 +0200

    siemens/sitemp_g1p1: Don't mess with virtual wire settings
    
    That function broke SMP on Linux 2.4, now it works.
    
    Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/mainboard/siemens/sitemp_g1p1/mptable.c |   10 ----------
 1 files changed, 0 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index d5b18ec..f1f96d2 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -73,19 +73,9 @@ static void *smp_write_config_table(void *v)
 	return smp_next_mpe_entry(mc);
 }
 
-static void fixup_virtual_wire(void *v)
-{
-        struct intel_mp_floating *mf = v;
-
-        mf->mpf_checksum = 0;
-        mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
-        mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
-}
-
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
 	v = smp_write_floating_table(addr);
-	fixup_virtual_wire(v);
 	return (unsigned long)smp_write_config_table(v);
 }



From alperenkose at buyutech.com.tr  Fri Oct  7 15:57:22 2011
From: alperenkose at buyutech.com.tr (=?ISO-8859-1?Q?Alp_Eren_K=F6se?=)
Date: Fri, 7 Oct 2011 16:57:22 +0300
Subject: [coreboot] crossgcc/buildgcc gdb7.2 version name change
Message-ID: <CAOz08zH-AaCZvXmy3Tm2bLbDu045WEhGUvZPzceGYWZBnK49bg@mail.gmail.com>

gdb7.2 is renamed to gdb7.2a in
http://ftp.gnu.org/gnu/gdb/

so 'make crosgcc' fails with:
Failed to download gdb-7.2.tar.bz2.
make[1]: *** [build] Error 1
make: *** [crossgcc] Error 2

It seems, the gdb version in util/crossgcc/buildgcc needs to be updated?
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From marcj303 at gmail.com  Fri Oct  7 17:54:40 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 7 Oct 2011 09:54:40 -0600
Subject: [coreboot] crossgcc/buildgcc gdb7.2 version name change
In-Reply-To: <CAOz08zH-AaCZvXmy3Tm2bLbDu045WEhGUvZPzceGYWZBnK49bg@mail.gmail.com>
References: <CAOz08zH-AaCZvXmy3Tm2bLbDu045WEhGUvZPzceGYWZBnK49bg@mail.gmail.com>
Message-ID: <CALrs_3gCMkqpL4uD8GCZtJMi8iS=jadH+nD2-phZvj8T4djR2A@mail.gmail.com>

2011/10/7 Alp Eren K?se <alperenkose at buyutech.com.tr>:
> gdb7.2 is renamed to gdb7.2a in
> http://ftp.gnu.org/gnu/gdb/
>
> so 'make crosgcc' fails with:
> Failed to download gdb-7.2.tar.bz2.
> make[1]: *** [build] Error 1
> make: *** [crossgcc] Error 2
>
> It seems, the gdb version in util/crossgcc/buildgcc needs to be updated?

That has been overcome by events. Please update your tree.
http://review.coreboot.org/#change,214



-- 
http://se-eng.com



From thomas at gstaedtner.net  Fri Oct  7 21:10:14 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Fri, 7 Oct 2011 21:10:14 +0200
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
	<CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>
Message-ID: <CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>

On Wed, Oct 5, 2011 at 20:08, Marc Jones <marcj303 at gmail.com> wrote:
> On Tue, Oct 4, 2011 at 5:26 PM, Thomas Gst?dtner <thomas at gstaedtner.net> wrote:
>> Hi everyone,
>>
>> I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of
>> the boards AMD as of recently claims to officially support.
>> So I decided to try coreboot, but (as expected) it is not really an
>> out-of-the-box experience.
>>
>> First of all, flashrom does not support flashing out-of-the-box, but
>> Frederic Temporelli's patches (
>> http://patchwork.coreboot.org/patch/3326/ and
>> http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I tested
>> multiple reads and multiple writes, always worked), I can report that
>> to the flashrom list separately if you want.
>>
>> I built coreboot from the gerrit-branch (also tried a "stable"
>> revision), coreboot-4.0-1714-gf8adf7a, using the "default"
>> board-config incl. seabios (stable) as payload.
>> After powering on nothing happens (apart from the fans running and the
>> power led flashing) and it stays that way, it is silent on VGA as well
>> as serial.
>> After manually triggering a reset I immediately get the following
>> output on serial:
>>
>> coreboot-4.0-1714-gf8adf7a Wed Oct ?5 00:31:05 CEST 2011 starting...
>> BSP Family_Model:
>>
>> Here it hangs, and I don't quite know how to move on and debug the issue.
>>
>> Can you give me any hints where to go on from here? I have external
>> flashing equipment at hand (which also works fine btw.), but no fancy
>> bios-debugging hardware.
>>
>> Regards,
>>
>> thomasg
>>
>> P.S. In case anyone else stumbles upon it: the board has 2 separate
>> flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W
>> package on the left of the board) as well as a SST25VF016B, 16 Mbit,
>> as the SOIC8W on the right. The first one holds the IPMI firmware, the
>> second one the AMI BIOS.
>> Flashing requires a testclip or some really serious soldering skills.
>> Attaching a SO8 socket can only be done with hot air soldering.
>
> Hi Thomas,
>
> Thanks for the report. While many people overlap with the flashrom
> list, please post about those patches on that list. Seems that you
> should be able to ack them.
>
> ?It looks like maybe the platform build doesn't support your CPU.
> There have been a number of recent contributions from AMD, but they
> don't all align with the platform contributions. So, the H8SCM should
> support all fam10 revD, but may have issue with Fam10 rev E. To get
> more information, you can turn the console debug output to SPEW in
> menuconfig.
>
> Marc
>
>
>
> --
> http://se-eng.com
>

Thanks for the advice Marc,

I already had the loglevel set to spew (8). I additionally tried the
other "Verbose output" debugging options, unfortunately I don't get
any output at all when they are built in.
Also, while it is hard to find and AMD doesn't have any official
document confirming this, according to some google hits the processor
should be revision D1 not rev E (AMD model number: OS4170OFU6DGOWOF ).

(Sry for sending the mail twice, hit the wrong button)



From gerrit at coreboot.org  Fri Oct  7 21:28:44 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Fri, 7 Oct 2011 21:28:44 +0200
Subject: [coreboot] Patch set updated for coreboot: 00bff57 Fixes several
	issues with amd k8 SSDT P-state generation
References: <I61f6e2210b84ccba33a36c5efc866447b7134417+0@gerrit.coreboot.org>
Message-ID: <I61f6e2210b84ccba33a36c5efc866447b7134417+2@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/239

-gerrit

commit 00bff5758e8104153ff9668fe739026ab977ab9a
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Thu Oct 6 18:43:43 2011 +0200

    Fixes several issues with amd k8 SSDT P-state generation
    
    For multi-socket CPU the current implementation emitted
    Processor objects for cores in the first CPU only. This
    commit fixes the bug. One caveat though: the unlikely case
    of mixed CPU models is still not handled correctly.
    
    Second issue fixed:
    One loop was wrong in case a processor in the table declares
    no P-states at all. The rewritten loop is safe. Some possibly
    dangerous array lengths were also fixed.
    
    Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV
    according to the BKDG. The current implementation always set it
    to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417
---
 src/cpu/amd/model_fxx/powernow_acpi.c |   81 +++++++++++++++++++++++++--------
 1 files changed, 61 insertions(+), 20 deletions(-)

diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index bbcf013..c49322f 100644
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -586,15 +586,17 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	u8 cmp_cap;
 	struct cpuentry *data = NULL;
 	uint32_t control;
-	int i = 0, index, len = 0, Pstate_num = 0;
+	int i = 0, index = 0, len = 0, Pstate_num = 0, dev = 0;
 	msr_t msr;
-	u8 Pstate_fid[10];
-	u16 Pstate_feq[10];
-	u8 Pstate_vid[10];
-	u32 Pstate_power[10];
+	u8 Pstate_fid[MAXP+1];
+	u16 Pstate_feq[MAXP+1];
+	u8 Pstate_vid[MAXP+1];
+	u32 Pstate_power[MAXP+1];
 	u8 Max_fid, Start_fid, Start_vid, Max_vid;
 	struct cpuid_result cpuid1 = cpuid(0x80000001);
 
+	// Because I don't know how to read msr registers from
+	// other CPU's I assume they all have the same SYSCONF values
 	msr = rdmsr(0xc0010042);
 	Max_fid = (msr.lo & 0x3F0000) >> 16;
 	Max_vid = (msr.hi & 0x3F0000) >> 16;
@@ -619,25 +621,57 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 		printk(BIOS_WARNING, "Unknown CPU, please update the powernow_acpi.c\n");
 		return 0;
 	}
+	/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
+	cpuid1 = cpuid(0x80000007);
+	if((cpuid1.edx & 0x6)!=0x6) {
+		printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
+		return 0;
+	}
+
+#if CONFIG_MAX_PHYSICAL_CPUS==1
+	// IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us
+	control = (3 << 30) | (2 << 28) | (2 << 20) | (0 << 18) | (5 << 11);
+#else
+	// MP-systems should default to RVO=0mV (no ramp voltage)
+	// IRT 80us RVO = 0mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us
+	control = (3 << 30) | (0 << 28) | (2 << 20) | (0 << 18) | (5 << 11);
+#endif
+	// RVO (Ramp Voltage Offset)
+	//   00   0mV (default for MP-systems)
+	//   01  25mV
+	//   10  50mV (default)
+	//   11  75mV
+	// IRT (Isochronous Release Time)
+	//   00  10uS
+	//   01  20uS
+	//   10  40uS
+	//   11  80uS (default)
+	// MVS (Maximum Voltage Step)
+	//   00  25mV (default)
+	//   01  50mV (reserved)
+	//   10 100mV (reserved)
+	//   11 200mV (reserved)
+	// VST (Voltage Stabilization Time)
+	//   time = value*20uS  (default value: 5 => 100uS)
+	// PLL_LOCK_TIME
+	//   time is value*1uS (often seen value: 2uS)
+	//
 
-	/* IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */
-	control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (1 << 29);
 	len = 0;
-	Pstate_num = 0;
 
-	Pstate_fid[Pstate_num] = Max_fid;
-	Pstate_feq[Pstate_num] = fid_to_freq(Max_fid);
-	Pstate_vid[Pstate_num] = Max_vid;
-	Pstate_power[Pstate_num] = data->pwr * 100;
-	Pstate_num++;
+	Pstate_fid[0] = Max_fid;
+	Pstate_feq[0] = fid_to_freq(Max_fid);
+	Pstate_vid[0] = Max_vid;
+	Pstate_power[0] = data->pwr * 100;
 
-	do {
+	for(Pstate_num = 1;
+	    (Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0);
+	    Pstate_num++) {
 		Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
 		Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz;
 		Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage);
 		Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100;
-		Pstate_num++;
-	} while ((Pstate_num < MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0));
+	}
 
 	for (i=0;i<Pstate_num;i++)
 		printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,
@@ -645,11 +679,18 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 		       vid_from_reg(Pstate_vid[i]),
 		       Pstate_power[i]);
 
-	for (index = 0; index < (cmp_cap + 1); index++) {
-		len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
-				Pstate_fid, Pstate_power, index,
-				pcontrol_blk, plen, onlyBSP, control);
+	for (dev = 0x18; dev < 0x1c; dev++) {
+		if(dev_find_slot(0, PCI_DEVFN(dev, 0))==NULL)
+			continue;
+
+		for (i = 0; i < (cmp_cap + 1); i++) {
+			len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
+					Pstate_fid, Pstate_power, index+i,
+					pcontrol_blk, plen, onlyBSP, control);
+		}
+		index += i;
 	}
+	printk(BIOS_DEBUG,"%d Processor objects emitted to SSDT\n",index);
 
 	return len;
 }



From marcj303 at gmail.com  Fri Oct  7 21:44:48 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 7 Oct 2011 13:44:48 -0600
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
	<CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>
	<CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
Message-ID: <CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>

On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gst?dtner <thomas at gstaedtner.net> wrote:
> On Wed, Oct 5, 2011 at 20:08, Marc Jones <marcj303 at gmail.com> wrote:
>> On Tue, Oct 4, 2011 at 5:26 PM, Thomas Gst?dtner <thomas at gstaedtner.net> wrote:
>>> Hi everyone,
>>>
>>> I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of
>>> the boards AMD as of recently claims to officially support.
>>> So I decided to try coreboot, but (as expected) it is not really an
>>> out-of-the-box experience.
>>>
>>> First of all, flashrom does not support flashing out-of-the-box, but
>>> Frederic Temporelli's patches (
>>> http://patchwork.coreboot.org/patch/3326/ and
>>> http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I tested
>>> multiple reads and multiple writes, always worked), I can report that
>>> to the flashrom list separately if you want.
>>>
>>> I built coreboot from the gerrit-branch (also tried a "stable"
>>> revision), coreboot-4.0-1714-gf8adf7a, using the "default"
>>> board-config incl. seabios (stable) as payload.
>>> After powering on nothing happens (apart from the fans running and the
>>> power led flashing) and it stays that way, it is silent on VGA as well
>>> as serial.
>>> After manually triggering a reset I immediately get the following
>>> output on serial:
>>>
>>> coreboot-4.0-1714-gf8adf7a Wed Oct ?5 00:31:05 CEST 2011 starting...
>>> BSP Family_Model:
>>>
>>> Here it hangs, and I don't quite know how to move on and debug the issue.
>>>
>>> Can you give me any hints where to go on from here? I have external
>>> flashing equipment at hand (which also works fine btw.), but no fancy
>>> bios-debugging hardware.
>>>
>>> Regards,
>>>
>>> thomasg
>>>
>>> P.S. In case anyone else stumbles upon it: the board has 2 separate
>>> flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W
>>> package on the left of the board) as well as a SST25VF016B, 16 Mbit,
>>> as the SOIC8W on the right. The first one holds the IPMI firmware, the
>>> second one the AMI BIOS.
>>> Flashing requires a testclip or some really serious soldering skills.
>>> Attaching a SO8 socket can only be done with hot air soldering.
>>
>> Hi Thomas,
>>
>> Thanks for the report. While many people overlap with the flashrom
>> list, please post about those patches on that list. Seems that you
>> should be able to ack them.
>>
>> ?It looks like maybe the platform build doesn't support your CPU.
>> There have been a number of recent contributions from AMD, but they
>> don't all align with the platform contributions. So, the H8SCM should
>> support all fam10 revD, but may have issue with Fam10 rev E. To get
>> more information, you can turn the console debug output to SPEW in
>> menuconfig.
>>
>> Marc
>>
>>
>>
>> --
>> http://se-eng.com
>>
>
> Thanks for the advice Marc,
>
> I already had the loglevel set to spew (8). I additionally tried the
> other "Verbose output" debugging options, unfortunately I don't get
> any output at all when they are built in.
> Also, while it is hard to find and AMD doesn't have any official
> document confirming this, according to some google hits the processor
> should be revision D1 not rev E (AMD model number: OS4170OFU6DGOWOF ).
>
> (Sry for sending the mail twice, hit the wrong button)
>

Oh, I just recalled something about the H8SCM. There is jumper to
disable the bmc which might have a watchdog that coreboot can't deal
with. Did you disable that?

Marc


-- 
http://se-eng.com



From gerrit at coreboot.org  Fri Oct  7 21:48:04 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 7 Oct 2011 21:48:04 +0200
Subject: [coreboot] New patch to review for coreboot: 51caef5 mptable:
	Refactor lintsrc generation
References: <I97421f820cd039f5fd753cb0da5c1cca68819bb4+0@gerrit.coreboot.org>
Message-ID: <I97421f820cd039f5fd753cb0da5c1cca68819bb4+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/244

-gerrit

commit 51caef5bb69445b65f4d7e468abe06bdb95de7b9
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Oct 7 21:42:52 2011 +0200

    mptable: Refactor lintsrc generation
    
    We copied pretty much the same code for generating mptable entries for
    local interrupts (with some notable exceptions).
    This change moves these lines into a generic function "mptable_lintsrc"
    and makes use of it in many places.
    
    The remaining uses of smp_write_lintsrc should be reviewed and replaced
    by mptable_lintsrc calls where possible, and smp_write_lintsrc made static.
    
    This patch was generated using Coccinelle:
      @@
      expression mc;
      expression isa_bus;
      @@
      -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
      -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
      +mptable_lintsrc(mc, isa_bus);
    
      @@
      expression mc;
      expression isa_bus;
      @@
      -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
      -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
      +mptable_lintsrc(mc, isa_bus);
    
      @m@
      identifier mc;
      expression BUS;
      @@
      -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin));
      ...
      -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
      -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
      +mptable_lintsrc(mc, BUS);
    
    Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/mpspec.c                         |    6 ++++++
 src/arch/x86/include/arch/smp/mpspec.h             |    1 +
 src/mainboard/amd/serengeti_cheetah/mptable.c      |    3 +--
 .../amd/serengeti_cheetah_fam10/mptable.c          |    3 +--
 src/mainboard/arima/hdama/mptable.c                |    5 +----
 src/mainboard/asus/a8n_e/mptable.c                 |    7 +------
 src/mainboard/asus/a8v-e_deluxe/mptable.c          |    3 +--
 src/mainboard/asus/a8v-e_se/mptable.c              |    3 +--
 src/mainboard/asus/m2n-e/mptable.c                 |    3 +--
 src/mainboard/asus/m2v/mptable.c                   |    3 +--
 src/mainboard/asus/p2b-d/mptable.c                 |    3 +--
 src/mainboard/asus/p2b-ds/mptable.c                |    3 +--
 src/mainboard/broadcom/blast/mptable.c             |    3 +--
 src/mainboard/getac/p470/mptable.c                 |    3 +--
 src/mainboard/gigabyte/ga_2761gxdk/mptable.c       |    3 +--
 src/mainboard/gigabyte/m57sli/mptable.c            |    3 +--
 src/mainboard/hp/dl145_g1/mptable.c                |    3 +--
 src/mainboard/hp/dl145_g3/mptable.c                |    3 +--
 src/mainboard/hp/dl165_g6_fam10/mptable.c          |    3 +--
 src/mainboard/ibase/mb899/mptable.c                |    3 +--
 src/mainboard/ibm/e325/mptable.c                   |    3 +--
 src/mainboard/ibm/e326/mptable.c                   |    3 +--
 src/mainboard/intel/d945gclf/mptable.c             |    3 +--
 src/mainboard/intel/eagleheights/mptable.c         |    3 +--
 src/mainboard/intel/jarrell/mptable.c              |    5 +----
 src/mainboard/intel/mtarvon/mptable.c              |    5 +----
 src/mainboard/intel/truxton/mptable.c              |    5 +----
 src/mainboard/intel/xe7501devkit/mptable.c         |    3 +--
 src/mainboard/iwave/iWRainbowG6/mptable.c          |    3 +--
 src/mainboard/iwill/dk8_htx/mptable.c              |    3 +--
 src/mainboard/iwill/dk8s2/mptable.c                |    5 +----
 src/mainboard/iwill/dk8x/mptable.c                 |    5 +----
 src/mainboard/kontron/986lcd-m/mptable.c           |    3 +--
 src/mainboard/msi/ms7135/mptable.c                 |    7 +------
 src/mainboard/msi/ms7260/mptable.c                 |    3 +--
 src/mainboard/msi/ms9185/mptable.c                 |    3 +--
 src/mainboard/msi/ms9282/mptable.c                 |    3 +--
 src/mainboard/msi/ms9652_fam10/mptable.c           |    3 +--
 src/mainboard/newisys/khepri/mptable.c             |    5 +----
 src/mainboard/nvidia/l1_2pvv/mptable.c             |    3 +--
 src/mainboard/roda/rk886ex/mptable.c               |    3 +--
 src/mainboard/siemens/sitemp_g1p1/mptable.c        |    3 +--
 src/mainboard/sunw/ultra40/mptable.c               |    3 +--
 src/mainboard/supermicro/h8dme/mptable.c           |    3 +--
 src/mainboard/supermicro/h8dmr/mptable.c           |    3 +--
 src/mainboard/supermicro/h8dmr_fam10/mptable.c     |    3 +--
 src/mainboard/supermicro/h8qme_fam10/mptable.c     |    3 +--
 src/mainboard/supermicro/x6dhe_g/mptable.c         |    5 +----
 src/mainboard/supermicro/x6dhe_g2/mptable.c        |    5 +----
 src/mainboard/supermicro/x6dhr_ig/mptable.c        |    5 +----
 src/mainboard/tyan/s2735/mptable.c                 |    3 +--
 src/mainboard/tyan/s2850/mptable.c                 |    3 +--
 src/mainboard/tyan/s2875/mptable.c                 |    3 +--
 src/mainboard/tyan/s2880/mptable.c                 |    3 +--
 src/mainboard/tyan/s2881/mptable.c                 |    3 +--
 src/mainboard/tyan/s2882/mptable.c                 |    3 +--
 src/mainboard/tyan/s2885/mptable.c                 |    3 +--
 src/mainboard/tyan/s2891/mptable.c                 |    3 +--
 src/mainboard/tyan/s2892/mptable.c                 |    3 +--
 src/mainboard/tyan/s2895/mptable.c                 |    3 +--
 src/mainboard/tyan/s2912/mptable.c                 |    3 +--
 src/mainboard/tyan/s2912_fam10/mptable.c           |    3 +--
 src/mainboard/tyan/s4880/mptable.c                 |    3 +--
 src/mainboard/tyan/s4882/mptable.c                 |    3 +--
 src/mainboard/via/epia-n/mptable.c                 |    3 +--
 src/mainboard/via/pc2500e/mptable.c                |    7 +------
 src/mainboard/via/vt8454c/mptable.c                |    3 +--
 67 files changed, 72 insertions(+), 162 deletions(-)

diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c
index 72a6d28..6c81430 100644
--- a/src/arch/x86/boot/mpspec.c
+++ b/src/arch/x86/boot/mpspec.c
@@ -335,6 +335,12 @@ void smp_write_compatibility_address_space(struct mp_config_table *mc,
 	smp_add_mpe_entry(mc, (mpe_t)mpe);
 }
 
+void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa)
+{
+	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+}
+
 void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external_int2)
 {
 /*I/O Ints:                   Type         Trigger            Polarity         Bus ID   IRQ  APIC ID   PIN# */
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 57fda34..1f194cd 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -273,6 +273,7 @@ void *smp_write_floating_table_physaddr(unsigned long addr,
 		unsigned long mpf_physptr);
 unsigned long write_smp_table(unsigned long addr);
 
+void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa);
 void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external);
 void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, int *isa_bus);
 
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 6af71e8..6478704 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -155,8 +155,7 @@ static void *smp_write_config_table(void *v)
 
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index f333bef..7a65c9f 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -179,8 +179,7 @@ static void *smp_write_config_table(void *v)
 
 
 	/* Local Ints:	Type	Polarity	Trigger		Bus ID		IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 3dc01e4..93959df 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -198,10 +198,7 @@ static void *smp_write_config_table(void *v)
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* PCI Ints:	     Type    Trigger                Polarity                 Bus ID      PCIDEVNUM|IRQ  APIC ID PIN# */
 	/* On board nics */
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index 05f74da..2191fef 100644
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -108,12 +108,7 @@ static void *smp_write_config_table(void *v)
 			 0x17);
 
 	/* Local Ints: Type Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT,
-			 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
-			 bus_ck804[0], 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,
-			 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
-			 bus_ck804[0], 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_ck804[0]);
 
 	/* There is no extension information... */
 
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
index 02e3f46..8d8059f 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c
@@ -101,8 +101,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
 
 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index 02e3f46..8d8059f 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -101,8 +101,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
 
 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
index 86b6670..66c4ee9 100644
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -91,8 +91,7 @@ static void *smp_write_config_table(void *v)
 	}
 
 	/* Local Ints:        Type       Trigger               Polarity              Bus ID   IRQ  APIC ID      PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* Compute the checksums. */
 	mc->mpe_checksum =
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
index 48c6d6f..0f84ad6 100644
--- a/src/mainboard/asus/m2v/mptable.c
+++ b/src/mainboard/asus/m2v/mptable.c
@@ -132,8 +132,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12);
 
 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, 0);
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c
index a3f06fd..c8e32c0 100644
--- a/src/mainboard/asus/p2b-d/mptable.c
+++ b/src/mainboard/asus/p2b-d/mptable.c
@@ -49,8 +49,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,  0x0,     0x13, ioapic_id,   0x13); /* UHCI */
 
 	/* Local Ints:       Type       Trigger                Polarity              Bus ID   IRQ   APIC ID      PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE  | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0,  MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_EDGE  | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0,  MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums. */
 	mc->mpe_checksum =
diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c
index 5374066..88028b7 100644
--- a/src/mainboard/asus/p2b-ds/mptable.c
+++ b/src/mainboard/asus/p2b-ds/mptable.c
@@ -50,8 +50,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc,  mp_INT,    MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,  0x0,     0x18, ioapic_id,   0x13);
 
 	/* Local Ints:        Type       Trigger                Polarity              Bus ID   IRQ   APIC ID      PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |  MP_IRQ_POLARITY_HIGH, 0x1,     0x0,  MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_EDGE |  MP_IRQ_POLARITY_HIGH, 0x1,     0x0,  MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, 0x1);
 
 	/* Compute the checksums. */
 	mc->mpe_checksum =
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index ae0c003..9debc04 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -130,8 +130,7 @@ static void *smp_write_config_table(void *v)
         }
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index ea7db07..989c892 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -71,8 +71,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
 
 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index c38d7f6..a4b15af 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -104,8 +104,7 @@ static void *smp_write_config_table(void *v)
 	        }
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 28b2858..8cb3cd2 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -110,8 +110,7 @@ static void *smp_write_config_table(void *v)
         }
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index 3cd9fd6..c45e1f4 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -83,8 +83,7 @@ static void *smp_write_config_table(void *v)
 	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index f23121e..1f75dad 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -164,8 +164,7 @@ static void *smp_write_config_table(void *v)
 
 /*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
 	printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa);
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa , 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 
 	//extended table entries
 	smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index c76ca6c..97b0c0e 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -142,8 +142,7 @@ static void *smp_write_config_table(void *v)
 	}
 
 	/* Local Ints:		Type	Polarity/Trigger				Bus ID		IRQ	APIC ID		PIN#  */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus,	0x0,	MP_APIC_ALL,	0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus,		0x0,	MP_APIC_ALL,	0x1);
+	mptable_lintsrc(mc, isa_bus);
 
 	//extended table entries
 	smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index 53156a3..18af2a1 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -119,8 +119,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
 
 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index d7ea08e..1128f0f 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -115,8 +115,7 @@ static void *smp_write_config_table(void *v)
 
 	/* Standard local interrupt assignments:
 	 * 		      Type	 Polarity		Trigger			 Bus ID   IRQ	APIC ID	     PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* There is no extension information... */
 
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
index 4934456..f7a41cc 100644
--- a/src/mainboard/ibm/e326/mptable.c
+++ b/src/mainboard/ibm/e326/mptable.c
@@ -114,8 +114,7 @@ static void *smp_write_config_table(void *v)
 
 	/* Standard local interrupt assignments:
 	 * 		      Type	 Polarity		Trigger			 Bus ID   IRQ	APIC ID	     PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* There is no extension information... */
 
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 641a7ef..3e26beb 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -76,8 +76,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
 
 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 02744c7..be89bf8 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -126,8 +126,7 @@ static void *smp_write_config_table(void *v)
 	mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
 
 	/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);
-	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* Internal PCI device for i3100 */
 
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index 748eb93..a68aaaf 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -167,10 +167,7 @@ static void *smp_write_config_table(void *v)
 		bus_isa, 0x0a, 0x08, 0x10);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* FIXME verify I have the irqs handled for all of the risers */
 
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index 638d669..6e211f9 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -47,10 +47,7 @@ static void *smp_write_config_table(void *v)
 	mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* Internal PCI devices */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index 67a7333..d8f9787 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -75,10 +75,7 @@ static void *smp_write_config_table(void *v)
 	mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* IMCH/IICH PCI devices */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index acd7621..f1be1d7 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -61,8 +61,7 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
 {
 	// Chipset PCI bus
 	//					 Type		Trigger | Polarity							Bus ID				IRQ					APIC ID					PIN#
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	PCI_BUS_CHIPSET,	0,					MP_APIC_ALL,			 0);
-	smp_write_lintsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	PCI_BUS_CHIPSET,	0,					MP_APIC_ALL,			 1);
+	mptable_lintsrc(mc, PCI_BUS_CHIPSET);
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_CHIPSET, 	PCI_IRQ(29, INT_A), IOAPIC_ICH3, 			16);	// USB 1.1 Controller #1
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_CHIPSET,	PCI_IRQ(31, INT_B),	IOAPIC_ICH3,			17);	// SMBus
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_CHIPSET, 	PCI_IRQ(29, INT_C), IOAPIC_ICH3, 			18);	// USB 1.1 Controller #3
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index 19bd835..a79b70b 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -90,8 +90,7 @@ void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x79, 0x1, 0x11);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7a, 0x1, 0x12);
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, isa_bus);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index 1964463..3b4578a 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -167,8 +167,7 @@ static void *smp_write_config_table(void *v)
 
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
index 4f262f2..3108c3c 100644
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ b/src/mainboard/iwill/dk8s2/mptable.c
@@ -79,10 +79,7 @@ static void *smp_write_config_table(void *v)
 	mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 
 	/* PCI Slot 1 */
diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c
index 4f262f2..3108c3c 100644
--- a/src/mainboard/iwill/dk8x/mptable.c
+++ b/src/mainboard/iwill/dk8x/mptable.c
@@ -79,10 +79,7 @@ static void *smp_write_config_table(void *v)
 	mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 
 	/* PCI Slot 1 */
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 9aa074e..84c3b2a 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -102,8 +102,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
 
 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
index 3412145..b30182c 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -144,12 +144,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(3, 0, 3, 17);
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT,
-			 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
-			 bus_ck804[0], 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,
-			 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
-			 bus_ck804[0], 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_ck804[0]);
 
 	/* There is no extension information... */
 
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
index e6a9e4d..b6142d6 100644
--- a/src/mainboard/msi/ms7260/mptable.c
+++ b/src/mainboard/msi/ms7260/mptable.c
@@ -94,8 +94,7 @@ static void *smp_write_config_table(void *v)
 	}
 
 	/* Local Ints:       Type       Trigger               Polarity              Bus ID   IRQ  APIC ID      PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* There is no extension information... */
 
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index 4cced6d..a754390 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -146,8 +146,7 @@ static void *smp_write_config_table(void *v)
         }
 
 /*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
-       smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-       smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+       mptable_lintsrc(mc, bus_isa);
        /* There is no extension information... */
 
        /* Compute the checksums */
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index f6b2d69..4c7774a 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -115,8 +115,7 @@ static void *smp_write_config_table(void *v)
                }
 
 /*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
-       smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-       smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+       mptable_lintsrc(mc, bus_isa);
        /* There is no extension information... */
 
        /* Compute the checksums */
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index f74acbf..87afa99 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -104,8 +104,7 @@ static void *smp_write_config_table(void *v)
 		}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index 37ed636..b11718b 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -80,10 +80,7 @@ static void *smp_write_config_table(void *v)
 	mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 
 	/* PCI Slot 1 */
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index db96584..043e473 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -161,8 +161,7 @@ static void *smp_write_config_table(void *v)
 	}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index ea7db07..989c892 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -71,8 +71,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
 
 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index df2f77b..889810f 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -65,8 +65,7 @@ static void *smp_write_config_table(void *v)
 	}
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* Compute the checksums */
 	mc->mpe_checksum =
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index 02a7024..9dbcf97 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -182,8 +182,7 @@ static void *smp_write_config_table(void *v)
         }
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index 16ff72a..dafa92a 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -117,8 +117,7 @@ static void *smp_write_config_table(void *v)
 	}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 8a00275..041aef8 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -118,8 +118,7 @@ static void *smp_write_config_table(void *v)
 	}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index a8cbc4b..54264e5 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -104,8 +104,7 @@ static void *smp_write_config_table(void *v)
 		}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index af44614..5a0ba63 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -102,8 +102,7 @@ static void *smp_write_config_table(void *v)
 		}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c
index 9b182a2..ba07bc7 100644
--- a/src/mainboard/supermicro/x6dhe_g/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g/mptable.c
@@ -116,10 +116,7 @@ static void *smp_write_config_table(void *v)
 		bus_esb6300_2, 0x08, 0x02, 0x14);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* FIXME verify I have the irqs handled for all of the risers */
 
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c
index 4ea62ce..35da882 100644
--- a/src/mainboard/supermicro/x6dhe_g2/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c
@@ -117,10 +117,7 @@ static void *smp_write_config_table(void *v)
 		bus_esb6300_2, 0x08, 0x02, 0x14);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* FIXME verify I have the irqs handled for all of the risers */
 
diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c
index eb0c307..7b182c8 100644
--- a/src/mainboard/supermicro/x6dhr_ig/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c
@@ -164,10 +164,7 @@ static void *smp_write_config_table(void *v)
 		(bus_isa - 1), 0x04, 0x02, 0x10);
 
 	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
+	mptable_lintsrc(mc, bus_isa);
 
 	/* There is no extension information... */
 
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index d17cd41..8f5a6b8 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -79,8 +79,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7);
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, 0x0);
 /*
 MP Config Extended Table Entries:
 
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 103dd3d..4267baf 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -148,8 +148,7 @@ static void *smp_write_config_table(void *v)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, apicid_8111, 0x10);
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-        smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-        smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+        mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index 80c1b84..4f9e50a 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -165,8 +165,7 @@ static void *smp_write_config_table(void *v)
 
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 8e11762..559f768 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -191,8 +191,7 @@ static void *smp_write_config_table(void *v)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, apicid_8131_2, 0x0);//
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c
index 2a6fcdc..bad4ae6 100644
--- a/src/mainboard/tyan/s2881/mptable.c
+++ b/src/mainboard/tyan/s2881/mptable.c
@@ -94,8 +94,7 @@ static void *smp_write_config_table(void *v)
 
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 49ec61f..b380dc1 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -203,8 +203,7 @@ static void *smp_write_config_table(void *v)
 
 #endif
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-        smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-        smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+        mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index a901cd7..e41e750 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -106,8 +106,7 @@ static void *smp_write_config_table(void *v)
         }
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index f3014e7..aec325e 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -131,8 +131,7 @@ static void *smp_write_config_table(void *v)
 	}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c
index fa5d0a1..0fc260c 100644
--- a/src/mainboard/tyan/s2892/mptable.c
+++ b/src/mainboard/tyan/s2892/mptable.c
@@ -153,8 +153,7 @@ static void *smp_write_config_table(void *v)
 	}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index a051b93..67fa39f 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -181,8 +181,7 @@ static void *smp_write_config_table(void *v)
 	}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index 26770bf..10c132c 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -102,8 +102,7 @@ static void *smp_write_config_table(void *v)
 		}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 58d6abb..7efccd0 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -102,8 +102,7 @@ static void *smp_write_config_table(void *v)
 		}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index 5f59c7a..71c7ff0 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -197,8 +197,7 @@ static void *smp_write_config_table(void *v)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index aa39882..668c880 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -196,8 +196,7 @@ static void *smp_write_config_table(void *v)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, bus_isa);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c
index 2102bf6..3be2f0a 100644
--- a/src/mainboard/via/epia-n/mptable.c
+++ b/src/mainboard/via/epia-n/mptable.c
@@ -35,8 +35,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14);
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, 0x0);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
index 125db37..e62c576 100644
--- a/src/mainboard/via/pc2500e/mptable.c
+++ b/src/mainboard/via/pc2500e/mptable.c
@@ -83,12 +83,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(1, 0, 0, 16);
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_lintsrc(mc, mp_ExtINT,
-			 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
-			 0, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI,
-			 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
-			 0, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, 0);
 
 	/* There is no extension information... */
 
diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c
index c2c844e..f196c15 100644
--- a/src/mainboard/via/vt8454c/mptable.c
+++ b/src/mainboard/via/vt8454c/mptable.c
@@ -55,8 +55,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x2, 0x10, 0x2, 0x11);
 
 	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+	mptable_lintsrc(mc, 0x0);
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);



From gerrit at coreboot.org  Fri Oct  7 22:42:51 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 7 Oct 2011 22:42:51 +0200
Subject: [coreboot] New patch to review for coreboot: 258ab20 mptable: Get
	rid of fixup_virtual_wire
References: <Icad8a063380bf4726be7cebb414d13b574112b14+0@gerrit.coreboot.org>
Message-ID: <Icad8a063380bf4726be7cebb414d13b574112b14+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/245

-gerrit

commit 258ab2084569a7f720c6b3aac1e9d0afba597d6a
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Oct 7 22:41:07 2011 +0200

    mptable: Get rid of fixup_virtual_wire
    
    As stated in some code files, fixup_virtual_wire was established
    to avoid touching 200 invocations of the mptable code.
    
    Let Coccinelle do it:
      @@
      type T;
      identifier v;
      @@
      -void fixup_virtual_wire(T v)
      -{ ... }
    
      @@
      expression A;
      identifier v;
      @@
      -v = smp_write_floating_table(A);
      +v = smp_write_floating_table(A, 0);
    
      @@
      expression A;
      identifier v;
      @@
      -v = smp_write_floating_table(A, 0);
      -fixup_virtual_wire(v);
      +v = smp_write_floating_table(A, 1);
    
    Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/mpspec.c                         |   18 +++++++++---------
 src/arch/x86/include/arch/smp/mpspec.h             |    4 +---
 src/mainboard/advansus/a785e-i/mptable.c           |    2 +-
 src/mainboard/amd/bimini_fam10/mptable.c           |    2 +-
 src/mainboard/amd/dbm690t/mptable.c                |    2 +-
 src/mainboard/amd/inagua/mptable.c                 |    2 +-
 src/mainboard/amd/mahogany/mptable.c               |    2 +-
 src/mainboard/amd/mahogany_fam10/mptable.c         |    2 +-
 src/mainboard/amd/persimmon/mptable.c              |    2 +-
 src/mainboard/amd/pistachio/mptable.c              |    2 +-
 src/mainboard/amd/serengeti_cheetah/mptable.c      |    2 +-
 .../amd/serengeti_cheetah_fam10/mptable.c          |    2 +-
 src/mainboard/amd/tilapia_fam10/mptable.c          |    2 +-
 src/mainboard/amd/torpedo/mptable.c                |    2 +-
 src/mainboard/arima/hdama/mptable.c                |    2 +-
 src/mainboard/asrock/939a785gmh/mptable.c          |    2 +-
 src/mainboard/asrock/e350m1/mptable.c              |    2 +-
 src/mainboard/asus/a8v-e_deluxe/mptable.c          |    2 +-
 src/mainboard/asus/a8v-e_se/mptable.c              |    2 +-
 src/mainboard/asus/m2n-e/mptable.c                 |    2 +-
 src/mainboard/asus/m2v/mptable.c                   |    2 +-
 src/mainboard/asus/m4a78-em/mptable.c              |    2 +-
 src/mainboard/asus/m4a785-m/mptable.c              |    2 +-
 src/mainboard/asus/p2b-d/mptable.c                 |    2 +-
 src/mainboard/asus/p2b-ds/mptable.c                |    2 +-
 src/mainboard/avalue/eax-785e/mptable.c            |    2 +-
 src/mainboard/broadcom/blast/mptable.c             |    2 +-
 src/mainboard/dell/s1850/mptable.c                 |    2 +-
 src/mainboard/getac/p470/mptable.c                 |    2 +-
 src/mainboard/gigabyte/ga_2761gxdk/mptable.c       |    2 +-
 src/mainboard/gigabyte/m57sli/mptable.c            |    2 +-
 src/mainboard/gigabyte/ma785gmt/mptable.c          |    2 +-
 src/mainboard/gigabyte/ma78gm/mptable.c            |    2 +-
 src/mainboard/hp/dl145_g1/mptable.c                |    2 +-
 src/mainboard/hp/dl145_g3/mptable.c                |    2 +-
 src/mainboard/hp/dl165_g6_fam10/mptable.c          |    2 +-
 src/mainboard/ibase/mb899/mptable.c                |   19 +------------------
 src/mainboard/ibm/e325/mptable.c                   |    2 +-
 src/mainboard/ibm/e326/mptable.c                   |    2 +-
 src/mainboard/iei/kino-780am2-fam10/mptable.c      |    2 +-
 src/mainboard/intel/d945gclf/mptable.c             |    2 +-
 src/mainboard/intel/eagleheights/mptable.c         |    2 +-
 src/mainboard/intel/jarrell/mptable.c              |    2 +-
 src/mainboard/intel/mtarvon/mptable.c              |    2 +-
 src/mainboard/intel/truxton/mptable.c              |    2 +-
 src/mainboard/intel/xe7501devkit/mptable.c         |    2 +-
 src/mainboard/iwave/iWRainbowG6/mptable.c          |    2 +-
 src/mainboard/iwill/dk8_htx/mptable.c              |    2 +-
 src/mainboard/iwill/dk8s2/mptable.c                |    2 +-
 src/mainboard/iwill/dk8x/mptable.c                 |    2 +-
 src/mainboard/jetway/pa78vm5/mptable.c             |    2 +-
 src/mainboard/kontron/986lcd-m/mptable.c           |   19 +------------------
 src/mainboard/kontron/kt690/mptable.c              |    2 +-
 src/mainboard/lenovo/t60/mptable.c                 |    2 +-
 src/mainboard/lenovo/x60/mptable.c                 |    2 +-
 src/mainboard/msi/ms7135/mptable.c                 |    2 +-
 src/mainboard/msi/ms7260/mptable.c                 |    2 +-
 src/mainboard/msi/ms9185/mptable.c                 |    2 +-
 src/mainboard/msi/ms9282/mptable.c                 |    2 +-
 src/mainboard/msi/ms9652_fam10/mptable.c           |    2 +-
 src/mainboard/newisys/khepri/mptable.c             |    2 +-
 src/mainboard/nvidia/l1_2pvv/mptable.c             |    2 +-
 src/mainboard/roda/rk886ex/mptable.c               |    2 +-
 src/mainboard/siemens/sitemp_g1p1/mptable.c        |   12 +-----------
 src/mainboard/sunw/ultra40/mptable.c               |    2 +-
 src/mainboard/supermicro/h8dme/mptable.c           |    2 +-
 src/mainboard/supermicro/h8dmr/mptable.c           |    2 +-
 src/mainboard/supermicro/h8dmr_fam10/mptable.c     |    2 +-
 src/mainboard/supermicro/h8qgi/mptable.c           |    2 +-
 src/mainboard/supermicro/h8qme_fam10/mptable.c     |    2 +-
 src/mainboard/supermicro/h8scm_fam10/mptable.c     |    2 +-
 src/mainboard/supermicro/x6dai_g/mptable.c         |    2 +-
 src/mainboard/supermicro/x6dhe_g/mptable.c         |    2 +-
 src/mainboard/supermicro/x6dhe_g2/mptable.c        |    2 +-
 src/mainboard/supermicro/x6dhr_ig/mptable.c        |    2 +-
 src/mainboard/supermicro/x6dhr_ig2/mptable.c       |    2 +-
 src/mainboard/technexion/tim5690/mptable.c         |    2 +-
 src/mainboard/technexion/tim8690/mptable.c         |    2 +-
 src/mainboard/tyan/s2735/mptable.c                 |    2 +-
 src/mainboard/tyan/s2850/mptable.c                 |    2 +-
 src/mainboard/tyan/s2875/mptable.c                 |    2 +-
 src/mainboard/tyan/s2880/mptable.c                 |    2 +-
 src/mainboard/tyan/s2881/mptable.c                 |    2 +-
 src/mainboard/tyan/s2882/mptable.c                 |    2 +-
 src/mainboard/tyan/s2885/mptable.c                 |    2 +-
 src/mainboard/tyan/s2891/mptable.c                 |    2 +-
 src/mainboard/tyan/s2892/mptable.c                 |    2 +-
 src/mainboard/tyan/s2895/mptable.c                 |    2 +-
 src/mainboard/tyan/s2912/mptable.c                 |    2 +-
 src/mainboard/tyan/s2912_fam10/mptable.c           |    2 +-
 src/mainboard/tyan/s4880/mptable.c                 |    2 +-
 src/mainboard/tyan/s4882/mptable.c                 |    2 +-
 src/mainboard/via/epia-n/mptable.c                 |    2 +-
 src/mainboard/via/pc2500e/mptable.c                |    2 +-
 src/mainboard/via/vt8454c/mptable.c                |    2 +-
 95 files changed, 103 insertions(+), 149 deletions(-)

diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c
index 6c81430..604f191 100644
--- a/src/arch/x86/boot/mpspec.c
+++ b/src/arch/x86/boot/mpspec.c
@@ -53,14 +53,7 @@ unsigned char smp_compute_checksum(void *v, int len)
 	return checksum;
 }
 
-void *smp_write_floating_table(unsigned long addr)
-{
-	/* 16 byte align the table address */
-	addr = (addr + 0xf) & (~0xf);
-	return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN);
-}
-
-void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr)
+static void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr, unsigned int virtualwire)
 {
         struct intel_mp_floating *mf;
         void *v;
@@ -76,7 +69,7 @@ void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_ph
         mf->mpf_specification = 4;
         mf->mpf_checksum = 0;
         mf->mpf_feature1 = 0;
-        mf->mpf_feature2 = 0;
+        mf->mpf_feature2 = virtualwire?MP_FEATURE_VIRTUALWIRE:0;
         mf->mpf_feature3 = 0;
         mf->mpf_feature4 = 0;
         mf->mpf_feature5 = 0;
@@ -84,6 +77,13 @@ void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_ph
         return v;
 }
 
+void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire)
+{
+	/* 16 byte align the table address */
+	addr = (addr + 0xf) & (~0xf);
+	return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN, virtualwire);
+}
+
 void *smp_next_mpc_entry(struct mp_config_table *mc)
 {
 	void *v;
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 1f194cd..e9a20c3 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -268,9 +268,7 @@ void smp_write_compatibility_address_space(struct mp_config_table *mc,
 	unsigned char busid, unsigned char address_modifier,
 	unsigned int range_list);
 unsigned char smp_compute_checksum(void *v, int len);
-void *smp_write_floating_table(unsigned long addr);
-void *smp_write_floating_table_physaddr(unsigned long addr,
-		unsigned long mpf_physptr);
+void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire);
 unsigned long write_smp_table(unsigned long addr);
 
 void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa);
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c
index 72733c6..d331929 100644
--- a/src/mainboard/advansus/a785e-i/mptable.c
+++ b/src/mainboard/advansus/a785e-i/mptable.c
@@ -151,6 +151,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
index a39c9ba..65852af 100644
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ b/src/mainboard/amd/bimini_fam10/mptable.c
@@ -155,6 +155,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index cb731a7..6d2c535 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -165,6 +165,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index e3cd5d0..1fc69cb 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -240,6 +240,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
   void *v;
-  v = smp_write_floating_table(addr);
+  v = smp_write_floating_table(addr, 0);
   return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index f07877b..e31bce7 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -172,6 +172,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index ec74b92..3e57ea0 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -158,6 +158,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
   void *v;
-  v = smp_write_floating_table(addr);
+  v = smp_write_floating_table(addr, 0);
   return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index cb731a7..6d2c535 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -165,6 +165,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 6478704..71e2d0e 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -169,6 +169,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index 7a65c9f..d3ebafb 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -193,6 +193,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 755b4a3..91213d8 100755
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -247,6 +247,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
   void *v;
-  v = smp_write_floating_table(addr);
+  v = smp_write_floating_table(addr, 0);
   return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 93959df..648a313 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -309,7 +309,7 @@ unsigned long write_smp_table(unsigned long addr)
 	void *v;
 	reboot_if_hotswap();
 
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
index 94002ff..f1f4a46 100644
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ b/src/mainboard/asrock/939a785gmh/mptable.c
@@ -170,6 +170,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 05c2275..712419a 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -158,6 +158,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
   void *v;
-  v = smp_write_floating_table(addr);
+  v = smp_write_floating_table(addr, 0);
   return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
index 8d8059f..6c67533 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c
@@ -115,6 +115,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index 8d8059f..6c67533 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -115,6 +115,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
index 66c4ee9..716c754 100644
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -105,6 +105,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
index 0f84ad6..9dd57f5 100644
--- a/src/mainboard/asus/m2v/mptable.c
+++ b/src/mainboard/asus/m2v/mptable.c
@@ -146,6 +146,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c
index c8e32c0..7030023 100644
--- a/src/mainboard/asus/p2b-d/mptable.c
+++ b/src/mainboard/asus/p2b-d/mptable.c
@@ -63,6 +63,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c
index 88028b7..31d360d 100644
--- a/src/mainboard/asus/p2b-ds/mptable.c
+++ b/src/mainboard/asus/p2b-ds/mptable.c
@@ -64,6 +64,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
index e4fc23b..5182ee7 100644
--- a/src/mainboard/avalue/eax-785e/mptable.c
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -153,6 +153,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index 9debc04..dc09fad 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -144,6 +144,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c
index 11a4a61..334e6ff 100644
--- a/src/mainboard/dell/s1850/mptable.c
+++ b/src/mainboard/dell/s1850/mptable.c
@@ -159,7 +159,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index 989c892..33b256f 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -85,6 +85,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index a4b15af..b79ddfb 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -118,6 +118,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 8cb3cd2..57fea2c 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -124,6 +124,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index c45e1f4..1d63af8 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -97,6 +97,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 1f75dad..f0786a0 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -189,6 +189,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 97b0c0e..860b86b 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -167,6 +167,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index 18af2a1..7ee2ed8 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -130,26 +130,9 @@ static void *smp_write_config_table(void *v)
 	return smp_next_mpe_entry(mc);
 }
 
-/* MP table generation in coreboot is not very well designed;
- * One of the issues is that it knows nothing about Virtual
- * Wire mode, which everyone uses since a decade or so. This
- * function fixes up our floating table. This spares us doing
- * a half-baked fix of adding a new parameter to 200+ calls
- * to smp_write_floating_table()
- */
-static void fixup_virtual_wire(void *v)
-{
-        struct intel_mp_floating *mf = v;
-
-        mf->mpf_checksum = 0;
-        mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
-        mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
-}
-
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
-	fixup_virtual_wire(v);
+	v = smp_write_floating_table(addr, 1);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index 1128f0f..2a4c7f3 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -130,7 +130,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
index f7a41cc..0b66b44 100644
--- a/src/mainboard/ibm/e326/mptable.c
+++ b/src/mainboard/ibm/e326/mptable.c
@@ -129,7 +129,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 3e26beb..6dcdf72 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -90,6 +90,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index be89bf8..1717b36 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -229,6 +229,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index a68aaaf..5b28642 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -238,7 +238,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index 6e211f9..b578ce8 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index d8f9787..c602fa8 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -139,7 +139,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index f1be1d7..9b28db1 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -141,6 +141,6 @@ static void *smp_write_config_table(void* v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index a79b70b..45a3c14 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -104,6 +104,6 @@ void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index 3b4578a..8aad009 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -181,6 +181,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
index 3108c3c..7fd370f 100644
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ b/src/mainboard/iwill/dk8s2/mptable.c
@@ -163,7 +163,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c
index 3108c3c..7fd370f 100644
--- a/src/mainboard/iwill/dk8x/mptable.c
+++ b/src/mainboard/iwill/dk8x/mptable.c
@@ -163,7 +163,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index f465b97..e8afa39 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -172,6 +172,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 84c3b2a..8280203 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -113,26 +113,9 @@ static void *smp_write_config_table(void *v)
 	return smp_next_mpe_entry(mc);
 }
 
-/* MP table generation in coreboot is not very well designed;
- * One of the issues is that it knows nothing about Virtual
- * Wire mode, which everyone uses since a decade or so. This
- * function fixes up our floating table. This spares us doing
- * a half-baked fix of adding a new parameter to 200+ calls
- * to smp_write_floating_table()
- */
-static void fixup_virtual_wire(void *v)
-{
-        struct intel_mp_floating *mf = v;
-
-        mf->mpf_checksum = 0;
-        mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
-        mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
-}
-
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
-	fixup_virtual_wire(v);
+	v = smp_write_floating_table(addr, 1);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 05dc951..1b32543 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -164,6 +164,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
index 3181e28..5d8ce23 100644
--- a/src/mainboard/lenovo/t60/mptable.c
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -78,6 +78,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
index 5bf9775..a366860 100644
--- a/src/mainboard/lenovo/x60/mptable.c
+++ b/src/mainboard/lenovo/x60/mptable.c
@@ -80,6 +80,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
index b30182c..3b19141 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -160,6 +160,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
index b6142d6..d14dd72 100644
--- a/src/mainboard/msi/ms7260/mptable.c
+++ b/src/mainboard/msi/ms7260/mptable.c
@@ -110,6 +110,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index a754390..314acf0 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -160,6 +160,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
        void *v;
-       v = smp_write_floating_table(addr);
+       v = smp_write_floating_table(addr, 0);
        return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index 4c7774a..5a6ec69 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -129,6 +129,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
        void *v;
-       v = smp_write_floating_table(addr);
+       v = smp_write_floating_table(addr, 0);
        return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index 87afa99..279f1a7 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -118,6 +118,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index b11718b..dca1cff 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index 043e473..50b1849 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -175,6 +175,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index 989c892..33b256f 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -85,6 +85,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index 889810f..3abadcf 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -76,19 +76,9 @@ static void *smp_write_config_table(void *v)
 	return smp_next_mpe_entry(mc);
 }
 
-static void fixup_virtual_wire(void *v)
-{
-        struct intel_mp_floating *mf = v;
-
-        mf->mpf_checksum = 0;
-        mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
-        mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
-}
-
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
-	fixup_virtual_wire(v);
+	v = smp_write_floating_table(addr, 1);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index 9dbcf97..7e6c018 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -196,6 +196,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index dafa92a..f16c4b2 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -131,6 +131,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 041aef8..96ba983 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -132,6 +132,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index 54264e5..50697d7 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -118,6 +118,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 4d32f39..6956027 100755
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -195,6 +195,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index 5a0ba63..b59c2ad 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -116,6 +116,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index f271402..eb6e6a4 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -185,6 +185,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c
index 62751e3..4b86f3d 100644
--- a/src/mainboard/supermicro/x6dai_g/mptable.c
+++ b/src/mainboard/supermicro/x6dai_g/mptable.c
@@ -88,7 +88,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c
index ba07bc7..07fbe9d 100644
--- a/src/mainboard/supermicro/x6dhe_g/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g/mptable.c
@@ -132,7 +132,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c
index 35da882..2fae456 100644
--- a/src/mainboard/supermicro/x6dhe_g2/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c
@@ -133,7 +133,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c
index 7b182c8..1782726 100644
--- a/src/mainboard/supermicro/x6dhr_ig/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c
@@ -180,7 +180,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
index 33ed3bb..a6ee5a6 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
@@ -168,7 +168,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 05dc951..1b32543 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -164,6 +164,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 05dc951..1b32543 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -164,6 +164,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index 8f5a6b8..91fca62 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -129,6 +129,6 @@ Compatibility Bus Address
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 4267baf..cd772b9 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -162,6 +162,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index 4f9e50a..f29f4cf 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -179,6 +179,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 559f768..7566de3 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -205,6 +205,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c
index bad4ae6..e303bfb 100644
--- a/src/mainboard/tyan/s2881/mptable.c
+++ b/src/mainboard/tyan/s2881/mptable.c
@@ -108,6 +108,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index b380dc1..8ec323c 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -217,6 +217,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index e41e750..a33f7c5 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -120,6 +120,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index aec325e..85248cc 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -145,6 +145,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c
index 0fc260c..aafe043 100644
--- a/src/mainboard/tyan/s2892/mptable.c
+++ b/src/mainboard/tyan/s2892/mptable.c
@@ -167,6 +167,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index 67fa39f..ef4f4ef 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -195,6 +195,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index 10c132c..e105442 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -116,6 +116,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 7efccd0..6778565 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -116,6 +116,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index 71c7ff0..dde7f88 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -211,6 +211,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index 668c880..ee78b11 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -210,6 +210,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c
index 3be2f0a..3b217ae 100644
--- a/src/mainboard/via/epia-n/mptable.c
+++ b/src/mainboard/via/epia-n/mptable.c
@@ -49,6 +49,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
index e62c576..82cbad6 100644
--- a/src/mainboard/via/pc2500e/mptable.c
+++ b/src/mainboard/via/pc2500e/mptable.c
@@ -99,6 +99,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c
index f196c15..d254fb1 100644
--- a/src/mainboard/via/vt8454c/mptable.c
+++ b/src/mainboard/via/vt8454c/mptable.c
@@ -67,6 +67,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }



From marcel.lucius at hccnet.nl  Fri Oct  7 22:17:07 2011
From: marcel.lucius at hccnet.nl (Marcel Lucius)
Date: Fri, 07 Oct 2011 22:17:07 +0200
Subject: [coreboot] Coreboot on ASUS A8N-E
Message-ID: <4E8F5E43.10501@hccnet.nl>

can I use coreboot safely on this board?
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From gerrit at coreboot.org  Fri Oct  7 23:03:37 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 7 Oct 2011 23:03:37 +0200
Subject: [coreboot] New patch to review for coreboot: 4a5e019 mptable:
	Refactor mptable generation some more
References: <Ib2270d800bdd486c5eb49b328544d36bd2298c9e+0@gerrit.coreboot.org>
Message-ID: <Ib2270d800bdd486c5eb49b328544d36bd2298c9e+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/246

-gerrit

commit 4a5e0191dce174f85f356b7c103d16b6cdbf8030
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Oct 7 23:01:55 2011 +0200

    mptable: Refactor mptable generation some more
    
    The last couple of lines of every mptable function were mostly
    identical. Refactor into common code, a new function mptable_finalize.
    
    Coccinelle script:
      @@
      identifier mc;
      @@
      (
      -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
      -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
      -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
      -return smp_next_mpe_entry(mc);
      +return mptable_finalize(mc);
      |
      -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
      -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
      -return smp_next_mpe_entry(mc);
      +return mptable_finalize(mc);
      )
    
    Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/mpspec.c                         |    9 ++++++++-
 src/arch/x86/include/arch/smp/mpspec.h             |    2 +-
 src/mainboard/advansus/a785e-i/mptable.c           |    7 +------
 src/mainboard/amd/bimini_fam10/mptable.c           |    7 +------
 src/mainboard/amd/dbm690t/mptable.c                |    7 +------
 src/mainboard/amd/inagua/mptable.c                 |    7 +------
 src/mainboard/amd/mahogany/mptable.c               |    7 +------
 src/mainboard/amd/mahogany_fam10/mptable.c         |    7 +------
 src/mainboard/amd/persimmon/mptable.c              |    7 +------
 src/mainboard/amd/pistachio/mptable.c              |    7 +------
 src/mainboard/amd/serengeti_cheetah/mptable.c      |    6 +-----
 .../amd/serengeti_cheetah_fam10/mptable.c          |    6 +-----
 src/mainboard/amd/tilapia_fam10/mptable.c          |    7 +------
 src/mainboard/amd/torpedo/mptable.c                |    7 +------
 src/mainboard/arima/hdama/mptable.c                |    6 +-----
 src/mainboard/asrock/939a785gmh/mptable.c          |    7 +------
 src/mainboard/asrock/e350m1/mptable.c              |    7 +------
 src/mainboard/asus/a8n_e/mptable.c                 |    7 +------
 src/mainboard/asus/a8v-e_deluxe/mptable.c          |    6 +-----
 src/mainboard/asus/a8v-e_se/mptable.c              |    6 +-----
 src/mainboard/asus/m2n-e/mptable.c                 |    7 +------
 src/mainboard/asus/m2v/mptable.c                   |    6 +-----
 src/mainboard/asus/m4a78-em/mptable.c              |    7 +------
 src/mainboard/asus/m4a785-m/mptable.c              |    7 +------
 src/mainboard/asus/p2b-d/mptable.c                 |    7 +------
 src/mainboard/asus/p2b-ds/mptable.c                |    7 +------
 src/mainboard/avalue/eax-785e/mptable.c            |    7 +------
 src/mainboard/broadcom/blast/mptable.c             |    6 +-----
 src/mainboard/dell/s1850/mptable.c                 |    7 +------
 src/mainboard/getac/p470/mptable.c                 |    7 +------
 src/mainboard/gigabyte/ga_2761gxdk/mptable.c       |    6 +-----
 src/mainboard/gigabyte/m57sli/mptable.c            |    6 +-----
 src/mainboard/gigabyte/ma785gmt/mptable.c          |    7 +------
 src/mainboard/gigabyte/ma78gm/mptable.c            |    7 +------
 src/mainboard/hp/dl145_g1/mptable.c                |    6 +-----
 src/mainboard/hp/dl145_g3/mptable.c                |    6 +-----
 src/mainboard/hp/dl165_g6_fam10/mptable.c          |    6 +-----
 src/mainboard/ibase/mb899/mptable.c                |    7 +------
 src/mainboard/ibm/e325/mptable.c                   |    6 +-----
 src/mainboard/ibm/e326/mptable.c                   |    6 +-----
 src/mainboard/iei/kino-780am2-fam10/mptable.c      |    7 +------
 src/mainboard/intel/d945gclf/mptable.c             |    7 +------
 src/mainboard/intel/eagleheights/mptable.c         |    6 +-----
 src/mainboard/intel/jarrell/mptable.c              |    7 +------
 src/mainboard/intel/mtarvon/mptable.c              |    7 +------
 src/mainboard/intel/truxton/mptable.c              |    7 +------
 src/mainboard/intel/xe7501devkit/mptable.c         |    6 +-----
 src/mainboard/iwave/iWRainbowG6/mptable.c          |    6 +-----
 src/mainboard/iwill/dk8_htx/mptable.c              |    6 +-----
 src/mainboard/iwill/dk8s2/mptable.c                |    6 +-----
 src/mainboard/iwill/dk8x/mptable.c                 |    6 +-----
 src/mainboard/jetway/pa78vm5/mptable.c             |    7 +------
 src/mainboard/kontron/986lcd-m/mptable.c           |    7 +------
 src/mainboard/kontron/kt690/mptable.c              |    7 +------
 src/mainboard/lenovo/t60/mptable.c                 |    7 +------
 src/mainboard/lenovo/x60/mptable.c                 |    7 +------
 src/mainboard/msi/ms7135/mptable.c                 |    7 +------
 src/mainboard/msi/ms7260/mptable.c                 |    7 +------
 src/mainboard/msi/ms9185/mptable.c                 |    6 +-----
 src/mainboard/msi/ms9282/mptable.c                 |    6 +-----
 src/mainboard/msi/ms9652_fam10/mptable.c           |    6 +-----
 src/mainboard/newisys/khepri/mptable.c             |    6 +-----
 src/mainboard/nvidia/l1_2pvv/mptable.c             |    6 +-----
 src/mainboard/roda/rk886ex/mptable.c               |    7 +------
 src/mainboard/siemens/sitemp_g1p1/mptable.c        |    7 +------
 src/mainboard/sunw/ultra40/mptable.c               |    6 +-----
 src/mainboard/supermicro/h8dme/mptable.c           |    6 +-----
 src/mainboard/supermicro/h8dmr/mptable.c           |    6 +-----
 src/mainboard/supermicro/h8dmr_fam10/mptable.c     |    6 +-----
 src/mainboard/supermicro/h8qgi/mptable.c           |    7 +------
 src/mainboard/supermicro/h8qme_fam10/mptable.c     |    6 +-----
 src/mainboard/supermicro/h8scm_fam10/mptable.c     |    7 +------
 src/mainboard/supermicro/x6dai_g/mptable.c         |    7 +------
 src/mainboard/supermicro/x6dhe_g/mptable.c         |    7 +------
 src/mainboard/supermicro/x6dhe_g2/mptable.c        |    7 +------
 src/mainboard/supermicro/x6dhr_ig/mptable.c        |    7 +------
 src/mainboard/supermicro/x6dhr_ig2/mptable.c       |    7 +------
 src/mainboard/technexion/tim5690/mptable.c         |    7 +------
 src/mainboard/technexion/tim8690/mptable.c         |    7 +------
 src/mainboard/tyan/s2735/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2850/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2875/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2880/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2881/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2882/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2885/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2891/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2892/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2895/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2912/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2912_fam10/mptable.c           |    6 +-----
 src/mainboard/tyan/s4880/mptable.c                 |    6 +-----
 src/mainboard/tyan/s4882/mptable.c                 |    6 +-----
 src/mainboard/via/epia-n/mptable.c                 |    6 +-----
 src/mainboard/via/pc2500e/mptable.c                |    7 +------
 src/mainboard/via/vt8454c/mptable.c                |    5 +----
 96 files changed, 103 insertions(+), 519 deletions(-)

diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c
index 604f191..209e0bb 100644
--- a/src/arch/x86/boot/mpspec.c
+++ b/src/arch/x86/boot/mpspec.c
@@ -40,7 +40,7 @@ void mptable_init(struct mp_config_table *mc, u32 lapic_addr)
 		mc->mpc_productid[i] = ' ';
 }
 
-unsigned char smp_compute_checksum(void *v, int len)
+static unsigned char smp_compute_checksum(void *v, int len)
 {
 	unsigned char *bytes;
 	unsigned char checksum;
@@ -396,3 +396,10 @@ void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, int *isa_
 	smp_write_bus(mc, *isa_bus, "ISA   ");
 }
 
+void *mptable_finalize(struct mp_config_table *mc)
+{
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index e9a20c3..2eb1813 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -267,13 +267,13 @@ void smp_write_bus_hierarchy(struct mp_config_table *mc,
 void smp_write_compatibility_address_space(struct mp_config_table *mc,
 	unsigned char busid, unsigned char address_modifier,
 	unsigned int range_list);
-unsigned char smp_compute_checksum(void *v, int len);
 void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire);
 unsigned long write_smp_table(unsigned long addr);
 
 void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa);
 void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external);
 void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, int *isa_bus);
+void *mptable_finalize(struct mp_config_table *mc);
 
 #endif
 
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c
index d331929..6504049 100644
--- a/src/mainboard/advansus/a785e-i/mptable.c
+++ b/src/mainboard/advansus/a785e-i/mptable.c
@@ -140,12 +140,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
index 65852af..2ab3f24 100644
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ b/src/mainboard/amd/bimini_fam10/mptable.c
@@ -144,12 +144,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index 6d2c535..901591a 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -154,12 +154,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 1fc69cb..fa7de7d 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -229,12 +229,7 @@ static void *smp_write_config_table(void *v)
   /* There is no extension information... */
 
   /* Compute the checksums */
-  mc->mpe_checksum =
-      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-         mc, smp_next_mpe_entry(mc));
-  return smp_next_mpe_entry(mc);
+  return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index e31bce7..f79a579 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -161,12 +161,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 3e57ea0..a3b4b5c 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -147,12 +147,7 @@ static void *smp_write_config_table(void *v)
   /* There is no extension information... */
 
   /* Compute the checksums */
-  mc->mpe_checksum =
-      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-         mc, smp_next_mpe_entry(mc));
-  return smp_next_mpe_entry(mc);
+  return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index 6d2c535..901591a 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -154,12 +154,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 71e2d0e..ebd4cbc 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -159,11 +159,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index d3ebafb..d527f9c 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -183,11 +183,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 91213d8..0381206 100755
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -236,12 +236,7 @@ static void *smp_write_config_table(void *v)
   /* There is no extension information... */
 
   /* Compute the checksums */
-  mc->mpe_checksum =
-      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-         mc, smp_next_mpe_entry(mc));
-  return smp_next_mpe_entry(mc);
+  return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 648a313..19bbf25 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -248,11 +248,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 static void reboot_if_hotswap(void)
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
index f1f4a46..95b1271 100644
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ b/src/mainboard/asrock/939a785gmh/mptable.c
@@ -159,12 +159,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 712419a..397e829 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -147,12 +147,7 @@ static void *smp_write_config_table(void *v)
   /* There is no extension information... */
 
   /* Compute the checksums */
-  mc->mpe_checksum =
-      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-         mc, smp_next_mpe_entry(mc));
-  return smp_next_mpe_entry(mc);
+  return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index 2191fef..09d6c55 100644
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -113,12 +113,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
index 6c67533..999dd6c 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c
@@ -105,11 +105,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
-						mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index 6c67533..999dd6c 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -105,11 +105,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
-						mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
index 716c754..29b9d07 100644
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -94,12 +94,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, bus_isa);
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
index 9dd57f5..5dc340a 100644
--- a/src/mainboard/asus/m2v/mptable.c
+++ b/src/mainboard/asus/m2v/mptable.c
@@ -136,11 +136,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
-						mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c
index 7030023..43f3a85 100644
--- a/src/mainboard/asus/p2b-d/mptable.c
+++ b/src/mainboard/asus/p2b-d/mptable.c
@@ -52,12 +52,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c
index 31d360d..153c62c 100644
--- a/src/mainboard/asus/p2b-ds/mptable.c
+++ b/src/mainboard/asus/p2b-ds/mptable.c
@@ -53,12 +53,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, 0x1);
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
index 5182ee7..021f635 100644
--- a/src/mainboard/avalue/eax-785e/mptable.c
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -142,12 +142,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index dc09fad..b747d2e 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -134,11 +134,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c
index 334e6ff..a71dab0 100644
--- a/src/mainboard/dell/s1850/mptable.c
+++ b/src/mainboard/dell/s1850/mptable.c
@@ -148,12 +148,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index 33b256f..5954c97 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -74,12 +74,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index b79ddfb..b52cda9 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -108,11 +108,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 57fea2c..5aa7e61 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -114,11 +114,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index 1d63af8..010f986 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -87,11 +87,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index f0786a0..466b7fc 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -179,11 +179,7 @@ static void *smp_write_config_table(void *v)
 
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 860b86b..c246721 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -157,11 +157,7 @@ static void *smp_write_config_table(void *v)
 
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index 7ee2ed8..0ff1896 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -122,12 +122,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index 2a4c7f3..6431f32 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -120,11 +120,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
index 0b66b44..e81bf8f 100644
--- a/src/mainboard/ibm/e326/mptable.c
+++ b/src/mainboard/ibm/e326/mptable.c
@@ -119,11 +119,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 6dcdf72..ab537cb 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -79,12 +79,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 1717b36..8571864 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -219,11 +219,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index 5b28642..b665703 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -227,12 +227,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index b578ce8..0c025f0 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -100,12 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index c602fa8..506a1d0 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -128,12 +128,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index 9b28db1..99fd5af 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -131,11 +131,7 @@ static void *smp_write_config_table(void* v)
 	xe7501devkit_register_interrupts(mc);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index 45a3c14..bf94b8c 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -94,11 +94,7 @@ void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index 8aad009..fd53bd7 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -171,11 +171,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
index 7fd370f..d78ce20 100644
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ b/src/mainboard/iwill/dk8s2/mptable.c
@@ -153,11 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c
index 7fd370f..d78ce20 100644
--- a/src/mainboard/iwill/dk8x/mptable.c
+++ b/src/mainboard/iwill/dk8x/mptable.c
@@ -153,11 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index e8afa39..11b4357 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -161,12 +161,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 8280203..ab63b45 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -105,12 +105,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 1b32543..21a0d05 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -153,12 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
index 5d8ce23..a74aca8 100644
--- a/src/mainboard/lenovo/t60/mptable.c
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -67,12 +67,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0);
 	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1);
 
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
index a366860..0ce10ed 100644
--- a/src/mainboard/lenovo/x60/mptable.c
+++ b/src/mainboard/lenovo/x60/mptable.c
@@ -69,12 +69,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0);
 	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1);
 
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
index 3b19141..4262af1 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -149,12 +149,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
index d14dd72..bef81ef 100644
--- a/src/mainboard/msi/ms7260/mptable.c
+++ b/src/mainboard/msi/ms7260/mptable.c
@@ -99,12 +99,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index 314acf0..0f97dca 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -150,11 +150,7 @@ static void *smp_write_config_table(void *v)
        /* There is no extension information... */
 
        /* Compute the checksums */
-       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-       printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-               mc, smp_next_mpe_entry(mc));
-       return smp_next_mpe_entry(mc);
+       return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index 5a6ec69..baba6b5 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -119,11 +119,7 @@ static void *smp_write_config_table(void *v)
        /* There is no extension information... */
 
        /* Compute the checksums */
-       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-       printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-               mc, smp_next_mpe_entry(mc));
-       return smp_next_mpe_entry(mc);
+       return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index 279f1a7..5e45380 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -108,11 +108,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index dca1cff..4017fce 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -154,11 +154,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index 50b1849..5d13701 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -165,11 +165,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index 33b256f..5954c97 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -74,12 +74,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index 3abadcf..4180c36 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -68,12 +68,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, bus_isa);
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index 7e6c018..c00c4b8 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -186,11 +186,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index f16c4b2..cdbe7d6 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -121,11 +121,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 96ba983..734fac9 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -122,11 +122,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index 50697d7..f2ee7a8 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -108,11 +108,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 6956027..7373cb8 100755
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -184,12 +184,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-		smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-			mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index b59c2ad..2e7c4af 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -106,11 +106,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index eb6e6a4..b2c1c92 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -174,12 +174,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c
index 4b86f3d..acd719d 100644
--- a/src/mainboard/supermicro/x6dai_g/mptable.c
+++ b/src/mainboard/supermicro/x6dai_g/mptable.c
@@ -77,12 +77,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c
index 07fbe9d..f5f4100 100644
--- a/src/mainboard/supermicro/x6dhe_g/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g/mptable.c
@@ -121,12 +121,7 @@ static void *smp_write_config_table(void *v)
 	/* FIXME verify I have the irqs handled for all of the risers */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c
index 2fae456..e39a700 100644
--- a/src/mainboard/supermicro/x6dhe_g2/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c
@@ -122,12 +122,7 @@ static void *smp_write_config_table(void *v)
 	/* FIXME verify I have the irqs handled for all of the risers */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c
index 1782726..143138d 100644
--- a/src/mainboard/supermicro/x6dhr_ig/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c
@@ -169,12 +169,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
index a6ee5a6..a374f5c 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
@@ -157,12 +157,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 1b32543..21a0d05 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -153,12 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 1b32543..21a0d05 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -153,12 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index 91fca62..9612a4c 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -119,11 +119,7 @@ Compatibility Bus Address
  predefined range: 0x00000001	// There is no extension information...
 */
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index cd772b9..5144cec 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -152,11 +152,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index f29f4cf..67de027 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -169,11 +169,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 7566de3..e0058fa 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -195,11 +195,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c
index e303bfb..80b35bc 100644
--- a/src/mainboard/tyan/s2881/mptable.c
+++ b/src/mainboard/tyan/s2881/mptable.c
@@ -98,11 +98,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 8ec323c..b028abb 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -207,11 +207,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index a33f7c5..fc5109f 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -110,11 +110,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index 85248cc..12d6e78 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -135,11 +135,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c
index aafe043..7af319a 100644
--- a/src/mainboard/tyan/s2892/mptable.c
+++ b/src/mainboard/tyan/s2892/mptable.c
@@ -157,11 +157,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index ef4f4ef..a383cb2 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -185,11 +185,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index e105442..49720dc 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -106,11 +106,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 6778565..393362b 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -106,11 +106,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index dde7f88..6646718 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -201,11 +201,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index ee78b11..c1da3e5 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -200,11 +200,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c
index 3b217ae..c7c554a 100644
--- a/src/mainboard/via/epia-n/mptable.c
+++ b/src/mainboard/via/epia-n/mptable.c
@@ -39,11 +39,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
index 82cbad6..939f21d 100644
--- a/src/mainboard/via/pc2500e/mptable.c
+++ b/src/mainboard/via/pc2500e/mptable.c
@@ -88,12 +88,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c
index d254fb1..575237f 100644
--- a/src/mainboard/via/vt8454c/mptable.c
+++ b/src/mainboard/via/vt8454c/mptable.c
@@ -58,10 +58,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, 0x0);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)



From gerrit at coreboot.org  Fri Oct  7 23:08:36 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 7 Oct 2011 23:08:36 +0200
Subject: [coreboot] Patch set updated for coreboot: eae1696 mptable: Get rid
	of fixup_virtual_wire
References: <Icad8a063380bf4726be7cebb414d13b574112b14+0@gerrit.coreboot.org>
Message-ID: <Icad8a063380bf4726be7cebb414d13b574112b14+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/245

-gerrit

commit eae1696809d6e6834d08ef22aa08c8f200870c59
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Oct 7 22:41:07 2011 +0200

    mptable: Get rid of fixup_virtual_wire
    
    As stated in some code files, fixup_virtual_wire was established
    to avoid touching 200 invocations of the mptable code.
    
    Let Coccinelle do it:
      @@
      type T;
      identifier v;
      @@
      -void fixup_virtual_wire(T v)
      -{ ... }
    
      @@
      expression A;
      identifier v;
      @@
      -v = smp_write_floating_table(A);
      +v = smp_write_floating_table(A, 0);
    
      @@
      expression A;
      identifier v;
      @@
      -v = smp_write_floating_table(A, 0);
      -fixup_virtual_wire(v);
      +v = smp_write_floating_table(A, 1);
    
    Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/mpspec.c                         |   18 +++++++++---------
 src/arch/x86/include/arch/smp/mpspec.h             |    4 +---
 src/mainboard/advansus/a785e-i/mptable.c           |    2 +-
 src/mainboard/amd/bimini_fam10/mptable.c           |    2 +-
 src/mainboard/amd/dbm690t/mptable.c                |    2 +-
 src/mainboard/amd/inagua/mptable.c                 |    2 +-
 src/mainboard/amd/mahogany/mptable.c               |    2 +-
 src/mainboard/amd/mahogany_fam10/mptable.c         |    2 +-
 src/mainboard/amd/persimmon/mptable.c              |    2 +-
 src/mainboard/amd/pistachio/mptable.c              |    2 +-
 src/mainboard/amd/serengeti_cheetah/mptable.c      |    2 +-
 .../amd/serengeti_cheetah_fam10/mptable.c          |    2 +-
 src/mainboard/amd/tilapia_fam10/mptable.c          |    2 +-
 src/mainboard/amd/torpedo/mptable.c                |    2 +-
 src/mainboard/arima/hdama/mptable.c                |    2 +-
 src/mainboard/asrock/939a785gmh/mptable.c          |    2 +-
 src/mainboard/asrock/e350m1/mptable.c              |    2 +-
 src/mainboard/asus/a8n_e/mptable.c                 |    2 +-
 src/mainboard/asus/a8v-e_deluxe/mptable.c          |    2 +-
 src/mainboard/asus/a8v-e_se/mptable.c              |    2 +-
 src/mainboard/asus/m2n-e/mptable.c                 |    2 +-
 src/mainboard/asus/m2v/mptable.c                   |    2 +-
 src/mainboard/asus/m4a78-em/mptable.c              |    2 +-
 src/mainboard/asus/m4a785-m/mptable.c              |    2 +-
 src/mainboard/asus/p2b-d/mptable.c                 |    2 +-
 src/mainboard/asus/p2b-ds/mptable.c                |    2 +-
 src/mainboard/avalue/eax-785e/mptable.c            |    2 +-
 src/mainboard/broadcom/blast/mptable.c             |    2 +-
 src/mainboard/dell/s1850/mptable.c                 |    2 +-
 src/mainboard/getac/p470/mptable.c                 |    2 +-
 src/mainboard/gigabyte/ga_2761gxdk/mptable.c       |    2 +-
 src/mainboard/gigabyte/m57sli/mptable.c            |    2 +-
 src/mainboard/gigabyte/ma785gmt/mptable.c          |    2 +-
 src/mainboard/gigabyte/ma78gm/mptable.c            |    2 +-
 src/mainboard/hp/dl145_g1/mptable.c                |    2 +-
 src/mainboard/hp/dl145_g3/mptable.c                |    2 +-
 src/mainboard/hp/dl165_g6_fam10/mptable.c          |    2 +-
 src/mainboard/ibase/mb899/mptable.c                |   19 +------------------
 src/mainboard/ibm/e325/mptable.c                   |    2 +-
 src/mainboard/ibm/e326/mptable.c                   |    2 +-
 src/mainboard/iei/kino-780am2-fam10/mptable.c      |    2 +-
 src/mainboard/intel/d945gclf/mptable.c             |    2 +-
 src/mainboard/intel/eagleheights/mptable.c         |    2 +-
 src/mainboard/intel/jarrell/mptable.c              |    2 +-
 src/mainboard/intel/mtarvon/mptable.c              |    2 +-
 src/mainboard/intel/truxton/mptable.c              |    2 +-
 src/mainboard/intel/xe7501devkit/mptable.c         |    2 +-
 src/mainboard/iwave/iWRainbowG6/mptable.c          |    2 +-
 src/mainboard/iwill/dk8_htx/mptable.c              |    2 +-
 src/mainboard/iwill/dk8s2/mptable.c                |    2 +-
 src/mainboard/iwill/dk8x/mptable.c                 |    2 +-
 src/mainboard/jetway/pa78vm5/mptable.c             |    2 +-
 src/mainboard/kontron/986lcd-m/mptable.c           |   19 +------------------
 src/mainboard/kontron/kt690/mptable.c              |    2 +-
 src/mainboard/lenovo/t60/mptable.c                 |    2 +-
 src/mainboard/lenovo/x60/mptable.c                 |    2 +-
 src/mainboard/msi/ms7135/mptable.c                 |    2 +-
 src/mainboard/msi/ms7260/mptable.c                 |    2 +-
 src/mainboard/msi/ms9185/mptable.c                 |    2 +-
 src/mainboard/msi/ms9282/mptable.c                 |    2 +-
 src/mainboard/msi/ms9652_fam10/mptable.c           |    2 +-
 src/mainboard/newisys/khepri/mptable.c             |    2 +-
 src/mainboard/nvidia/l1_2pvv/mptable.c             |    2 +-
 src/mainboard/roda/rk886ex/mptable.c               |    2 +-
 src/mainboard/siemens/sitemp_g1p1/mptable.c        |   12 +-----------
 src/mainboard/sunw/ultra40/mptable.c               |    2 +-
 src/mainboard/supermicro/h8dme/mptable.c           |    2 +-
 src/mainboard/supermicro/h8dmr/mptable.c           |    2 +-
 src/mainboard/supermicro/h8dmr_fam10/mptable.c     |    2 +-
 src/mainboard/supermicro/h8qgi/mptable.c           |    2 +-
 src/mainboard/supermicro/h8qme_fam10/mptable.c     |    2 +-
 src/mainboard/supermicro/h8scm_fam10/mptable.c     |    2 +-
 src/mainboard/supermicro/x6dai_g/mptable.c         |    2 +-
 src/mainboard/supermicro/x6dhe_g/mptable.c         |    2 +-
 src/mainboard/supermicro/x6dhe_g2/mptable.c        |    2 +-
 src/mainboard/supermicro/x6dhr_ig/mptable.c        |    2 +-
 src/mainboard/supermicro/x6dhr_ig2/mptable.c       |    2 +-
 src/mainboard/technexion/tim5690/mptable.c         |    2 +-
 src/mainboard/technexion/tim8690/mptable.c         |    2 +-
 src/mainboard/tyan/s2735/mptable.c                 |    2 +-
 src/mainboard/tyan/s2850/mptable.c                 |    2 +-
 src/mainboard/tyan/s2875/mptable.c                 |    2 +-
 src/mainboard/tyan/s2880/mptable.c                 |    2 +-
 src/mainboard/tyan/s2881/mptable.c                 |    2 +-
 src/mainboard/tyan/s2882/mptable.c                 |    2 +-
 src/mainboard/tyan/s2885/mptable.c                 |    2 +-
 src/mainboard/tyan/s2891/mptable.c                 |    2 +-
 src/mainboard/tyan/s2892/mptable.c                 |    2 +-
 src/mainboard/tyan/s2895/mptable.c                 |    2 +-
 src/mainboard/tyan/s2912/mptable.c                 |    2 +-
 src/mainboard/tyan/s2912_fam10/mptable.c           |    2 +-
 src/mainboard/tyan/s4880/mptable.c                 |    2 +-
 src/mainboard/tyan/s4882/mptable.c                 |    2 +-
 src/mainboard/via/epia-n/mptable.c                 |    2 +-
 src/mainboard/via/pc2500e/mptable.c                |    2 +-
 src/mainboard/via/vt8454c/mptable.c                |    2 +-
 96 files changed, 104 insertions(+), 150 deletions(-)

diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c
index 6c81430..604f191 100644
--- a/src/arch/x86/boot/mpspec.c
+++ b/src/arch/x86/boot/mpspec.c
@@ -53,14 +53,7 @@ unsigned char smp_compute_checksum(void *v, int len)
 	return checksum;
 }
 
-void *smp_write_floating_table(unsigned long addr)
-{
-	/* 16 byte align the table address */
-	addr = (addr + 0xf) & (~0xf);
-	return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN);
-}
-
-void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr)
+static void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr, unsigned int virtualwire)
 {
         struct intel_mp_floating *mf;
         void *v;
@@ -76,7 +69,7 @@ void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_ph
         mf->mpf_specification = 4;
         mf->mpf_checksum = 0;
         mf->mpf_feature1 = 0;
-        mf->mpf_feature2 = 0;
+        mf->mpf_feature2 = virtualwire?MP_FEATURE_VIRTUALWIRE:0;
         mf->mpf_feature3 = 0;
         mf->mpf_feature4 = 0;
         mf->mpf_feature5 = 0;
@@ -84,6 +77,13 @@ void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_ph
         return v;
 }
 
+void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire)
+{
+	/* 16 byte align the table address */
+	addr = (addr + 0xf) & (~0xf);
+	return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN, virtualwire);
+}
+
 void *smp_next_mpc_entry(struct mp_config_table *mc)
 {
 	void *v;
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 1f194cd..e9a20c3 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -268,9 +268,7 @@ void smp_write_compatibility_address_space(struct mp_config_table *mc,
 	unsigned char busid, unsigned char address_modifier,
 	unsigned int range_list);
 unsigned char smp_compute_checksum(void *v, int len);
-void *smp_write_floating_table(unsigned long addr);
-void *smp_write_floating_table_physaddr(unsigned long addr,
-		unsigned long mpf_physptr);
+void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire);
 unsigned long write_smp_table(unsigned long addr);
 
 void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa);
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c
index 72733c6..d331929 100644
--- a/src/mainboard/advansus/a785e-i/mptable.c
+++ b/src/mainboard/advansus/a785e-i/mptable.c
@@ -151,6 +151,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
index a39c9ba..65852af 100644
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ b/src/mainboard/amd/bimini_fam10/mptable.c
@@ -155,6 +155,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index cb731a7..6d2c535 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -165,6 +165,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index e3cd5d0..1fc69cb 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -240,6 +240,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
   void *v;
-  v = smp_write_floating_table(addr);
+  v = smp_write_floating_table(addr, 0);
   return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index f07877b..e31bce7 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -172,6 +172,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index ec74b92..3e57ea0 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -158,6 +158,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
   void *v;
-  v = smp_write_floating_table(addr);
+  v = smp_write_floating_table(addr, 0);
   return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index cb731a7..6d2c535 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -165,6 +165,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 6478704..71e2d0e 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -169,6 +169,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index 7a65c9f..d3ebafb 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -193,6 +193,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 755b4a3..91213d8 100755
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -247,6 +247,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
   void *v;
-  v = smp_write_floating_table(addr);
+  v = smp_write_floating_table(addr, 0);
   return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 93959df..648a313 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -309,7 +309,7 @@ unsigned long write_smp_table(unsigned long addr)
 	void *v;
 	reboot_if_hotswap();
 
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
index 94002ff..f1f4a46 100644
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ b/src/mainboard/asrock/939a785gmh/mptable.c
@@ -170,6 +170,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 05c2275..712419a 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -158,6 +158,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
   void *v;
-  v = smp_write_floating_table(addr);
+  v = smp_write_floating_table(addr, 0);
   return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index 2191fef..d790c76 100644
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -123,6 +123,6 @@ static void *smp_write_config_table(void *v)
 
 unsigned long write_smp_table(unsigned long addr)
 {
-	void *v = smp_write_floating_table(addr);
+	void *v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
index 8d8059f..6c67533 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c
@@ -115,6 +115,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index 8d8059f..6c67533 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -115,6 +115,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
index 66c4ee9..716c754 100644
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -105,6 +105,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
index 0f84ad6..9dd57f5 100644
--- a/src/mainboard/asus/m2v/mptable.c
+++ b/src/mainboard/asus/m2v/mptable.c
@@ -146,6 +146,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c
index c8e32c0..7030023 100644
--- a/src/mainboard/asus/p2b-d/mptable.c
+++ b/src/mainboard/asus/p2b-d/mptable.c
@@ -63,6 +63,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c
index 88028b7..31d360d 100644
--- a/src/mainboard/asus/p2b-ds/mptable.c
+++ b/src/mainboard/asus/p2b-ds/mptable.c
@@ -64,6 +64,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
index e4fc23b..5182ee7 100644
--- a/src/mainboard/avalue/eax-785e/mptable.c
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -153,6 +153,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index 9debc04..dc09fad 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -144,6 +144,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c
index 11a4a61..334e6ff 100644
--- a/src/mainboard/dell/s1850/mptable.c
+++ b/src/mainboard/dell/s1850/mptable.c
@@ -159,7 +159,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index 989c892..33b256f 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -85,6 +85,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index a4b15af..b79ddfb 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -118,6 +118,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 8cb3cd2..57fea2c 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -124,6 +124,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index c45e1f4..1d63af8 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -97,6 +97,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 1f75dad..f0786a0 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -189,6 +189,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 97b0c0e..860b86b 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -167,6 +167,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index 18af2a1..7ee2ed8 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -130,26 +130,9 @@ static void *smp_write_config_table(void *v)
 	return smp_next_mpe_entry(mc);
 }
 
-/* MP table generation in coreboot is not very well designed;
- * One of the issues is that it knows nothing about Virtual
- * Wire mode, which everyone uses since a decade or so. This
- * function fixes up our floating table. This spares us doing
- * a half-baked fix of adding a new parameter to 200+ calls
- * to smp_write_floating_table()
- */
-static void fixup_virtual_wire(void *v)
-{
-        struct intel_mp_floating *mf = v;
-
-        mf->mpf_checksum = 0;
-        mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
-        mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
-}
-
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
-	fixup_virtual_wire(v);
+	v = smp_write_floating_table(addr, 1);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index 1128f0f..2a4c7f3 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -130,7 +130,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
index f7a41cc..0b66b44 100644
--- a/src/mainboard/ibm/e326/mptable.c
+++ b/src/mainboard/ibm/e326/mptable.c
@@ -129,7 +129,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index dabda5b..024e87a 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -171,6 +171,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 3e26beb..6dcdf72 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -90,6 +90,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index be89bf8..1717b36 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -229,6 +229,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index a68aaaf..5b28642 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -238,7 +238,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index 6e211f9..b578ce8 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index d8f9787..c602fa8 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -139,7 +139,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index f1be1d7..9b28db1 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -141,6 +141,6 @@ static void *smp_write_config_table(void* v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index a79b70b..45a3c14 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -104,6 +104,6 @@ void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index 3b4578a..8aad009 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -181,6 +181,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
index 3108c3c..7fd370f 100644
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ b/src/mainboard/iwill/dk8s2/mptable.c
@@ -163,7 +163,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c
index 3108c3c..7fd370f 100644
--- a/src/mainboard/iwill/dk8x/mptable.c
+++ b/src/mainboard/iwill/dk8x/mptable.c
@@ -163,7 +163,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index f465b97..e8afa39 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -172,6 +172,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 84c3b2a..8280203 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -113,26 +113,9 @@ static void *smp_write_config_table(void *v)
 	return smp_next_mpe_entry(mc);
 }
 
-/* MP table generation in coreboot is not very well designed;
- * One of the issues is that it knows nothing about Virtual
- * Wire mode, which everyone uses since a decade or so. This
- * function fixes up our floating table. This spares us doing
- * a half-baked fix of adding a new parameter to 200+ calls
- * to smp_write_floating_table()
- */
-static void fixup_virtual_wire(void *v)
-{
-        struct intel_mp_floating *mf = v;
-
-        mf->mpf_checksum = 0;
-        mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
-        mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
-}
-
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
-	fixup_virtual_wire(v);
+	v = smp_write_floating_table(addr, 1);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 05dc951..1b32543 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -164,6 +164,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
index 3181e28..5d8ce23 100644
--- a/src/mainboard/lenovo/t60/mptable.c
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -78,6 +78,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
index 5bf9775..a366860 100644
--- a/src/mainboard/lenovo/x60/mptable.c
+++ b/src/mainboard/lenovo/x60/mptable.c
@@ -80,6 +80,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
index b30182c..3b19141 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -160,6 +160,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
index b6142d6..d14dd72 100644
--- a/src/mainboard/msi/ms7260/mptable.c
+++ b/src/mainboard/msi/ms7260/mptable.c
@@ -110,6 +110,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index a754390..314acf0 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -160,6 +160,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
        void *v;
-       v = smp_write_floating_table(addr);
+       v = smp_write_floating_table(addr, 0);
        return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index 4c7774a..5a6ec69 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -129,6 +129,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
        void *v;
-       v = smp_write_floating_table(addr);
+       v = smp_write_floating_table(addr, 0);
        return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index 87afa99..279f1a7 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -118,6 +118,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index b11718b..dca1cff 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index 043e473..50b1849 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -175,6 +175,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index 989c892..33b256f 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -85,6 +85,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index 889810f..3abadcf 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -76,19 +76,9 @@ static void *smp_write_config_table(void *v)
 	return smp_next_mpe_entry(mc);
 }
 
-static void fixup_virtual_wire(void *v)
-{
-        struct intel_mp_floating *mf = v;
-
-        mf->mpf_checksum = 0;
-        mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
-        mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
-}
-
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
-	fixup_virtual_wire(v);
+	v = smp_write_floating_table(addr, 1);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index 9dbcf97..7e6c018 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -196,6 +196,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index dafa92a..f16c4b2 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -131,6 +131,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 041aef8..96ba983 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -132,6 +132,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index 54264e5..50697d7 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -118,6 +118,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 4d32f39..6956027 100755
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -195,6 +195,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index 5a0ba63..b59c2ad 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -116,6 +116,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index f271402..eb6e6a4 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -185,6 +185,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c
index 62751e3..4b86f3d 100644
--- a/src/mainboard/supermicro/x6dai_g/mptable.c
+++ b/src/mainboard/supermicro/x6dai_g/mptable.c
@@ -88,7 +88,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c
index ba07bc7..07fbe9d 100644
--- a/src/mainboard/supermicro/x6dhe_g/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g/mptable.c
@@ -132,7 +132,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c
index 35da882..2fae456 100644
--- a/src/mainboard/supermicro/x6dhe_g2/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c
@@ -133,7 +133,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c
index 7b182c8..1782726 100644
--- a/src/mainboard/supermicro/x6dhr_ig/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c
@@ -180,7 +180,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
index 33ed3bb..a6ee5a6 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
@@ -168,7 +168,7 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
 
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 05dc951..1b32543 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -164,6 +164,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 05dc951..1b32543 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -164,6 +164,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index 8f5a6b8..91fca62 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -129,6 +129,6 @@ Compatibility Bus Address
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 4267baf..cd772b9 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -162,6 +162,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index 4f9e50a..f29f4cf 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -179,6 +179,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 559f768..7566de3 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -205,6 +205,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c
index bad4ae6..e303bfb 100644
--- a/src/mainboard/tyan/s2881/mptable.c
+++ b/src/mainboard/tyan/s2881/mptable.c
@@ -108,6 +108,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index b380dc1..8ec323c 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -217,6 +217,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index e41e750..a33f7c5 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -120,6 +120,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index aec325e..85248cc 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -145,6 +145,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c
index 0fc260c..aafe043 100644
--- a/src/mainboard/tyan/s2892/mptable.c
+++ b/src/mainboard/tyan/s2892/mptable.c
@@ -167,6 +167,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index 67fa39f..ef4f4ef 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -195,6 +195,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index 10c132c..e105442 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -116,6 +116,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 7efccd0..6778565 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -116,6 +116,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index 71c7ff0..dde7f88 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -211,6 +211,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index 668c880..ee78b11 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -210,6 +210,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c
index 3be2f0a..3b217ae 100644
--- a/src/mainboard/via/epia-n/mptable.c
+++ b/src/mainboard/via/epia-n/mptable.c
@@ -49,6 +49,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
index e62c576..82cbad6 100644
--- a/src/mainboard/via/pc2500e/mptable.c
+++ b/src/mainboard/via/pc2500e/mptable.c
@@ -99,6 +99,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c
index f196c15..d254fb1 100644
--- a/src/mainboard/via/vt8454c/mptable.c
+++ b/src/mainboard/via/vt8454c/mptable.c
@@ -67,6 +67,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }



From gerrit at coreboot.org  Fri Oct  7 23:08:36 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 7 Oct 2011 23:08:36 +0200
Subject: [coreboot] Patch set updated for coreboot: 3322f8f mptable:
	Refactor mptable generation some more
References: <Ib2270d800bdd486c5eb49b328544d36bd2298c9e+0@gerrit.coreboot.org>
Message-ID: <Ib2270d800bdd486c5eb49b328544d36bd2298c9e+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/246

-gerrit

commit 3322f8f5a5ce35ecc5f03ca56f587f1b85b04e78
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Oct 7 23:01:55 2011 +0200

    mptable: Refactor mptable generation some more
    
    The last couple of lines of every mptable function were mostly
    identical. Refactor into common code, a new function mptable_finalize.
    
    Coccinelle script:
      @@
      identifier mc;
      @@
      (
      -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
      -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
      -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
      -return smp_next_mpe_entry(mc);
      +return mptable_finalize(mc);
      |
      -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
      -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
      -return smp_next_mpe_entry(mc);
      +return mptable_finalize(mc);
      )
    
    Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/mpspec.c                         |    9 ++++++++-
 src/arch/x86/include/arch/smp/mpspec.h             |    2 +-
 src/mainboard/advansus/a785e-i/mptable.c           |    7 +------
 src/mainboard/amd/bimini_fam10/mptable.c           |    7 +------
 src/mainboard/amd/dbm690t/mptable.c                |    7 +------
 src/mainboard/amd/inagua/mptable.c                 |    7 +------
 src/mainboard/amd/mahogany/mptable.c               |    7 +------
 src/mainboard/amd/mahogany_fam10/mptable.c         |    7 +------
 src/mainboard/amd/persimmon/mptable.c              |    7 +------
 src/mainboard/amd/pistachio/mptable.c              |    7 +------
 src/mainboard/amd/serengeti_cheetah/mptable.c      |    6 +-----
 .../amd/serengeti_cheetah_fam10/mptable.c          |    6 +-----
 src/mainboard/amd/tilapia_fam10/mptable.c          |    7 +------
 src/mainboard/amd/torpedo/mptable.c                |    7 +------
 src/mainboard/arima/hdama/mptable.c                |    6 +-----
 src/mainboard/asrock/939a785gmh/mptable.c          |    7 +------
 src/mainboard/asrock/e350m1/mptable.c              |    7 +------
 src/mainboard/asus/a8n_e/mptable.c                 |    7 +------
 src/mainboard/asus/a8v-e_deluxe/mptable.c          |    6 +-----
 src/mainboard/asus/a8v-e_se/mptable.c              |    6 +-----
 src/mainboard/asus/m2n-e/mptable.c                 |    7 +------
 src/mainboard/asus/m2v/mptable.c                   |    6 +-----
 src/mainboard/asus/m4a78-em/mptable.c              |    7 +------
 src/mainboard/asus/m4a785-m/mptable.c              |    7 +------
 src/mainboard/asus/p2b-d/mptable.c                 |    7 +------
 src/mainboard/asus/p2b-ds/mptable.c                |    7 +------
 src/mainboard/avalue/eax-785e/mptable.c            |    7 +------
 src/mainboard/broadcom/blast/mptable.c             |    6 +-----
 src/mainboard/dell/s1850/mptable.c                 |    7 +------
 src/mainboard/getac/p470/mptable.c                 |    7 +------
 src/mainboard/gigabyte/ga_2761gxdk/mptable.c       |    6 +-----
 src/mainboard/gigabyte/m57sli/mptable.c            |    6 +-----
 src/mainboard/gigabyte/ma785gmt/mptable.c          |    7 +------
 src/mainboard/gigabyte/ma78gm/mptable.c            |    7 +------
 src/mainboard/hp/dl145_g1/mptable.c                |    6 +-----
 src/mainboard/hp/dl145_g3/mptable.c                |    6 +-----
 src/mainboard/hp/dl165_g6_fam10/mptable.c          |    6 +-----
 src/mainboard/ibase/mb899/mptable.c                |    7 +------
 src/mainboard/ibm/e325/mptable.c                   |    6 +-----
 src/mainboard/ibm/e326/mptable.c                   |    6 +-----
 src/mainboard/iei/kino-780am2-fam10/mptable.c      |    7 +------
 src/mainboard/intel/d945gclf/mptable.c             |    7 +------
 src/mainboard/intel/eagleheights/mptable.c         |    6 +-----
 src/mainboard/intel/jarrell/mptable.c              |    7 +------
 src/mainboard/intel/mtarvon/mptable.c              |    7 +------
 src/mainboard/intel/truxton/mptable.c              |    7 +------
 src/mainboard/intel/xe7501devkit/mptable.c         |    6 +-----
 src/mainboard/iwave/iWRainbowG6/mptable.c          |    6 +-----
 src/mainboard/iwill/dk8_htx/mptable.c              |    6 +-----
 src/mainboard/iwill/dk8s2/mptable.c                |    6 +-----
 src/mainboard/iwill/dk8x/mptable.c                 |    6 +-----
 src/mainboard/jetway/pa78vm5/mptable.c             |    7 +------
 src/mainboard/kontron/986lcd-m/mptable.c           |    7 +------
 src/mainboard/kontron/kt690/mptable.c              |    7 +------
 src/mainboard/lenovo/t60/mptable.c                 |    7 +------
 src/mainboard/lenovo/x60/mptable.c                 |    7 +------
 src/mainboard/msi/ms7135/mptable.c                 |    7 +------
 src/mainboard/msi/ms7260/mptable.c                 |    7 +------
 src/mainboard/msi/ms9185/mptable.c                 |    6 +-----
 src/mainboard/msi/ms9282/mptable.c                 |    6 +-----
 src/mainboard/msi/ms9652_fam10/mptable.c           |    6 +-----
 src/mainboard/newisys/khepri/mptable.c             |    6 +-----
 src/mainboard/nvidia/l1_2pvv/mptable.c             |    6 +-----
 src/mainboard/roda/rk886ex/mptable.c               |    7 +------
 src/mainboard/siemens/sitemp_g1p1/mptable.c        |    7 +------
 src/mainboard/sunw/ultra40/mptable.c               |    6 +-----
 src/mainboard/supermicro/h8dme/mptable.c           |    6 +-----
 src/mainboard/supermicro/h8dmr/mptable.c           |    6 +-----
 src/mainboard/supermicro/h8dmr_fam10/mptable.c     |    6 +-----
 src/mainboard/supermicro/h8qgi/mptable.c           |    7 +------
 src/mainboard/supermicro/h8qme_fam10/mptable.c     |    6 +-----
 src/mainboard/supermicro/h8scm_fam10/mptable.c     |    7 +------
 src/mainboard/supermicro/x6dai_g/mptable.c         |    7 +------
 src/mainboard/supermicro/x6dhe_g/mptable.c         |    7 +------
 src/mainboard/supermicro/x6dhe_g2/mptable.c        |    7 +------
 src/mainboard/supermicro/x6dhr_ig/mptable.c        |    7 +------
 src/mainboard/supermicro/x6dhr_ig2/mptable.c       |    7 +------
 src/mainboard/technexion/tim5690/mptable.c         |    7 +------
 src/mainboard/technexion/tim8690/mptable.c         |    7 +------
 src/mainboard/tyan/s2735/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2850/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2875/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2880/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2881/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2882/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2885/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2891/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2892/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2895/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2912/mptable.c                 |    6 +-----
 src/mainboard/tyan/s2912_fam10/mptable.c           |    6 +-----
 src/mainboard/tyan/s4880/mptable.c                 |    6 +-----
 src/mainboard/tyan/s4882/mptable.c                 |    6 +-----
 src/mainboard/via/epia-n/mptable.c                 |    6 +-----
 src/mainboard/via/pc2500e/mptable.c                |    7 +------
 src/mainboard/via/vt8454c/mptable.c                |    5 +----
 96 files changed, 103 insertions(+), 519 deletions(-)

diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c
index 604f191..209e0bb 100644
--- a/src/arch/x86/boot/mpspec.c
+++ b/src/arch/x86/boot/mpspec.c
@@ -40,7 +40,7 @@ void mptable_init(struct mp_config_table *mc, u32 lapic_addr)
 		mc->mpc_productid[i] = ' ';
 }
 
-unsigned char smp_compute_checksum(void *v, int len)
+static unsigned char smp_compute_checksum(void *v, int len)
 {
 	unsigned char *bytes;
 	unsigned char checksum;
@@ -396,3 +396,10 @@ void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, int *isa_
 	smp_write_bus(mc, *isa_bus, "ISA   ");
 }
 
+void *mptable_finalize(struct mp_config_table *mc)
+{
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index e9a20c3..2eb1813 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -267,13 +267,13 @@ void smp_write_bus_hierarchy(struct mp_config_table *mc,
 void smp_write_compatibility_address_space(struct mp_config_table *mc,
 	unsigned char busid, unsigned char address_modifier,
 	unsigned int range_list);
-unsigned char smp_compute_checksum(void *v, int len);
 void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire);
 unsigned long write_smp_table(unsigned long addr);
 
 void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa);
 void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external);
 void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, int *isa_bus);
+void *mptable_finalize(struct mp_config_table *mc);
 
 #endif
 
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c
index d331929..6504049 100644
--- a/src/mainboard/advansus/a785e-i/mptable.c
+++ b/src/mainboard/advansus/a785e-i/mptable.c
@@ -140,12 +140,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
index 65852af..2ab3f24 100644
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ b/src/mainboard/amd/bimini_fam10/mptable.c
@@ -144,12 +144,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index 6d2c535..901591a 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -154,12 +154,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 1fc69cb..fa7de7d 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -229,12 +229,7 @@ static void *smp_write_config_table(void *v)
   /* There is no extension information... */
 
   /* Compute the checksums */
-  mc->mpe_checksum =
-      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-         mc, smp_next_mpe_entry(mc));
-  return smp_next_mpe_entry(mc);
+  return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index e31bce7..f79a579 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -161,12 +161,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 3e57ea0..a3b4b5c 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -147,12 +147,7 @@ static void *smp_write_config_table(void *v)
   /* There is no extension information... */
 
   /* Compute the checksums */
-  mc->mpe_checksum =
-      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-         mc, smp_next_mpe_entry(mc));
-  return smp_next_mpe_entry(mc);
+  return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index 6d2c535..901591a 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -154,12 +154,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 71e2d0e..ebd4cbc 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -159,11 +159,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index d3ebafb..d527f9c 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -183,11 +183,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 91213d8..0381206 100755
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -236,12 +236,7 @@ static void *smp_write_config_table(void *v)
   /* There is no extension information... */
 
   /* Compute the checksums */
-  mc->mpe_checksum =
-      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-         mc, smp_next_mpe_entry(mc));
-  return smp_next_mpe_entry(mc);
+  return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 648a313..19bbf25 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -248,11 +248,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 static void reboot_if_hotswap(void)
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
index f1f4a46..95b1271 100644
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ b/src/mainboard/asrock/939a785gmh/mptable.c
@@ -159,12 +159,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 712419a..397e829 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -147,12 +147,7 @@ static void *smp_write_config_table(void *v)
   /* There is no extension information... */
 
   /* Compute the checksums */
-  mc->mpe_checksum =
-      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-         mc, smp_next_mpe_entry(mc));
-  return smp_next_mpe_entry(mc);
+  return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index d790c76..349ae74 100644
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -113,12 +113,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
index 6c67533..999dd6c 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c
@@ -105,11 +105,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
-						mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index 6c67533..999dd6c 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -105,11 +105,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
-						mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
index 716c754..29b9d07 100644
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -94,12 +94,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, bus_isa);
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
index 9dd57f5..5dc340a 100644
--- a/src/mainboard/asus/m2v/mptable.c
+++ b/src/mainboard/asus/m2v/mptable.c
@@ -136,11 +136,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
-						mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c
index 7030023..43f3a85 100644
--- a/src/mainboard/asus/p2b-d/mptable.c
+++ b/src/mainboard/asus/p2b-d/mptable.c
@@ -52,12 +52,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c
index 31d360d..153c62c 100644
--- a/src/mainboard/asus/p2b-ds/mptable.c
+++ b/src/mainboard/asus/p2b-ds/mptable.c
@@ -53,12 +53,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, 0x1);
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
index 5182ee7..021f635 100644
--- a/src/mainboard/avalue/eax-785e/mptable.c
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -142,12 +142,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index dc09fad..b747d2e 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -134,11 +134,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c
index 334e6ff..a71dab0 100644
--- a/src/mainboard/dell/s1850/mptable.c
+++ b/src/mainboard/dell/s1850/mptable.c
@@ -148,12 +148,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index 33b256f..5954c97 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -74,12 +74,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index b79ddfb..b52cda9 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -108,11 +108,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 57fea2c..5aa7e61 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -114,11 +114,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index 1d63af8..010f986 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -87,11 +87,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index f0786a0..466b7fc 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -179,11 +179,7 @@ static void *smp_write_config_table(void *v)
 
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 860b86b..c246721 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -157,11 +157,7 @@ static void *smp_write_config_table(void *v)
 
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index 7ee2ed8..0ff1896 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -122,12 +122,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index 2a4c7f3..6431f32 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -120,11 +120,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
index 0b66b44..e81bf8f 100644
--- a/src/mainboard/ibm/e326/mptable.c
+++ b/src/mainboard/ibm/e326/mptable.c
@@ -119,11 +119,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index 024e87a..4bf3480 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -160,12 +160,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 6dcdf72..ab537cb 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -79,12 +79,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 1717b36..8571864 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -219,11 +219,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index 5b28642..b665703 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -227,12 +227,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index b578ce8..0c025f0 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -100,12 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index c602fa8..506a1d0 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -128,12 +128,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index 9b28db1..99fd5af 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -131,11 +131,7 @@ static void *smp_write_config_table(void* v)
 	xe7501devkit_register_interrupts(mc);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index 45a3c14..bf94b8c 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -94,11 +94,7 @@ void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index 8aad009..fd53bd7 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -171,11 +171,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
index 7fd370f..d78ce20 100644
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ b/src/mainboard/iwill/dk8s2/mptable.c
@@ -153,11 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c
index 7fd370f..d78ce20 100644
--- a/src/mainboard/iwill/dk8x/mptable.c
+++ b/src/mainboard/iwill/dk8x/mptable.c
@@ -153,11 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index e8afa39..11b4357 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -161,12 +161,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 8280203..ab63b45 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -105,12 +105,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 1b32543..21a0d05 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -153,12 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
index 5d8ce23..a74aca8 100644
--- a/src/mainboard/lenovo/t60/mptable.c
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -67,12 +67,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0);
 	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1);
 
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
index a366860..0ce10ed 100644
--- a/src/mainboard/lenovo/x60/mptable.c
+++ b/src/mainboard/lenovo/x60/mptable.c
@@ -69,12 +69,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0);
 	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1);
 
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
index 3b19141..4262af1 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -149,12 +149,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
index d14dd72..bef81ef 100644
--- a/src/mainboard/msi/ms7260/mptable.c
+++ b/src/mainboard/msi/ms7260/mptable.c
@@ -99,12 +99,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums. */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index 314acf0..0f97dca 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -150,11 +150,7 @@ static void *smp_write_config_table(void *v)
        /* There is no extension information... */
 
        /* Compute the checksums */
-       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-       printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-               mc, smp_next_mpe_entry(mc));
-       return smp_next_mpe_entry(mc);
+       return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index 5a6ec69..baba6b5 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -119,11 +119,7 @@ static void *smp_write_config_table(void *v)
        /* There is no extension information... */
 
        /* Compute the checksums */
-       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-       printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-               mc, smp_next_mpe_entry(mc));
-       return smp_next_mpe_entry(mc);
+       return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index 279f1a7..5e45380 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -108,11 +108,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index dca1cff..4017fce 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -154,11 +154,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index 50b1849..5d13701 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -165,11 +165,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index 33b256f..5954c97 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -74,12 +74,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index 3abadcf..4180c36 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -68,12 +68,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, bus_isa);
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index 7e6c018..c00c4b8 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -186,11 +186,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index f16c4b2..cdbe7d6 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -121,11 +121,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 96ba983..734fac9 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -122,11 +122,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index 50697d7..f2ee7a8 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -108,11 +108,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 6956027..7373cb8 100755
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -184,12 +184,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-		smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-			mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index b59c2ad..2e7c4af 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -106,11 +106,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index eb6e6a4..b2c1c92 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -174,12 +174,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c
index 4b86f3d..acd719d 100644
--- a/src/mainboard/supermicro/x6dai_g/mptable.c
+++ b/src/mainboard/supermicro/x6dai_g/mptable.c
@@ -77,12 +77,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c
index 07fbe9d..f5f4100 100644
--- a/src/mainboard/supermicro/x6dhe_g/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g/mptable.c
@@ -121,12 +121,7 @@ static void *smp_write_config_table(void *v)
 	/* FIXME verify I have the irqs handled for all of the risers */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c
index 2fae456..e39a700 100644
--- a/src/mainboard/supermicro/x6dhe_g2/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c
@@ -122,12 +122,7 @@ static void *smp_write_config_table(void *v)
 	/* FIXME verify I have the irqs handled for all of the risers */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c
index 1782726..143138d 100644
--- a/src/mainboard/supermicro/x6dhr_ig/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c
@@ -169,12 +169,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
index a6ee5a6..a374f5c 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
@@ -157,12 +157,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 1b32543..21a0d05 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -153,12 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 1b32543..21a0d05 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -153,12 +153,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index 91fca62..9612a4c 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -119,11 +119,7 @@ Compatibility Bus Address
  predefined range: 0x00000001	// There is no extension information...
 */
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index cd772b9..5144cec 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -152,11 +152,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index f29f4cf..67de027 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -169,11 +169,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 7566de3..e0058fa 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -195,11 +195,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c
index e303bfb..80b35bc 100644
--- a/src/mainboard/tyan/s2881/mptable.c
+++ b/src/mainboard/tyan/s2881/mptable.c
@@ -98,11 +98,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 8ec323c..b028abb 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -207,11 +207,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index a33f7c5..fc5109f 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -110,11 +110,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index 85248cc..12d6e78 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -135,11 +135,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c
index aafe043..7af319a 100644
--- a/src/mainboard/tyan/s2892/mptable.c
+++ b/src/mainboard/tyan/s2892/mptable.c
@@ -157,11 +157,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index ef4f4ef..a383cb2 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -185,11 +185,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index e105442..49720dc 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -106,11 +106,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 6778565..393362b 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -106,11 +106,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index dde7f88..6646718 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -201,11 +201,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index ee78b11..c1da3e5 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -200,11 +200,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c
index 3b217ae..c7c554a 100644
--- a/src/mainboard/via/epia-n/mptable.c
+++ b/src/mainboard/via/epia-n/mptable.c
@@ -39,11 +39,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
index 82cbad6..939f21d 100644
--- a/src/mainboard/via/pc2500e/mptable.c
+++ b/src/mainboard/via/pc2500e/mptable.c
@@ -88,12 +88,7 @@ static void *smp_write_config_table(void *v)
 	/* There is no extension information... */
 
 	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c
index d254fb1..575237f 100644
--- a/src/mainboard/via/vt8454c/mptable.c
+++ b/src/mainboard/via/vt8454c/mptable.c
@@ -58,10 +58,7 @@ static void *smp_write_config_table(void *v)
 	mptable_lintsrc(mc, 0x0);
 
 	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)



From paulepanter at users.sourceforge.net  Sat Oct  8 10:50:55 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sat, 08 Oct 2011 10:50:55 +0200
Subject: [coreboot] [RFC] Tracking run tested coreboot revisions for boards
Message-ID: <1318063855.3932.36.camel@mattotaupa>

Dear coreboot folks,


on IRC Rudolf mentioned that the A8V SE [1] works with the latest
revision of coreboot and he asked if there is a way to tag that in the
repository.

There are several ways to accomplish that but all seem to have down
sides.

1. Git tags. We could use `git tag <board name> <commit>` and interested
folks could then do `git tag | grep <board name>` to find tested
revisions. Peter wrote, that Git tags could slow down the repository and
that only finitely many tags can be used. Would the last point be a
problem for us?

2. Git notes. Peter suggested also to use Git notes. But Rudolf wrote he
finds it difficult to handle.

3. Wiki. We could use the Wiki by either adding tested revisions to the
corresponding board pages or by creating a new page with a table. The
first solution is not feasible because not all boards have their own
page. Patrick wrote that using the Wiki often it gets out of date pretty
quickly. Although in this case I think that would not be a huge problem
considering that the noted revision actually was tested. Additionally
not a lot of developers are comfortable using the Wiki. OpenEmbedded
once did something like that [2].

4. Provide tested images. In addition to specifying the revision such
tested images could be uploaded somewhere so users would not have to
build it themselves. This would not work though, since the
infrastructure is not in place and we have to be careful with images
containing option roms(?).

5. ROM-o-matic.net [3]. Idwer suggested a service similar to
ROM-o-matic.net where know revisions get build by this server and users
can configure an image to be built. That is an interesting idea although
it is probably the most difficult to realize. Could this be a GSoC
project?

6. File in repository. An other suggestion by Patrick and myself is to
put a file in for example `Documentation/working-revisions.mdtext` and
note the tested revision and board there or to put a file in each board
directory and note tested revisions there. The downside is that people
would have to register with Gerrit to submit changes.

If we would manage our Wiki in our repository [4] options 3 and 6 could
be combined.

7. Messages to the list. Thinking about it the easiest solution would be
to create something like the script `alsa-info.sh`. This script collects
the necessary information ? in our case for example revision, boards,
cbfs output, used build tools. Even better would be to run that script
on the tested machine so also something like the tested distribution
could be tested.

Then a mbox or text file with an appropriate name/subject line is
created

        [Tested] ASUS M2V-MX SE works with revision <commit>

which gets send to the list by the user or automatically.

People then can search the archive. The only downside is that a nice
table is missing.

All in all I am quite surprised that no nice solutions seem to exist
especially since I would imagine quality assurance (QA) folks in
companies need to maintain similar data.

Please comment and add your ideas.


Thanks,

Paul


[1] http://www.coreboot.org/Supported_Motherboards
[2] http://www.openembedded.org/wiki/Testing
[3] http://rom-o-matic.net/
[4] http://www.coreboot.org/pipermail/coreboot/2011-June/065706.html
[5] http://alsa-project.org/main/index.php/Help_To_Debug
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From wangqingpei at gmail.com  Sat Oct  8 10:56:35 2011
From: wangqingpei at gmail.com (QingPei Wang)
Date: Sat, 8 Oct 2011 16:56:35 +0800
Subject: [coreboot] Coreboot on ASUS A8N-E
In-Reply-To: <4E8F5E43.10501@hccnet.nl>
References: <4E8F5E43.10501@hccnet.nl>
Message-ID: <CADuV8k4LchEzjFwOu35z1qujBQ2WH7eBaMEK8bPBys88Qi2yng@mail.gmail.com>

as what the page http://www.coreboot.org/Supported_Motherboards said, this
mainboard is supported.




Best wishes
QingPei Wang
Phone: 86+018930528086


On Sat, Oct 8, 2011 at 4:17 AM, Marcel Lucius <marcel.lucius at hccnet.nl>wrote:

> can I use coreboot safely on this board?
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From gerrit at coreboot.org  Sun Oct  9 09:08:39 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Sun, 9 Oct 2011 09:08:39 +0200
Subject: [coreboot] Patch set updated for coreboot: 6060f76 sb800: Add
	Kconfig option ENABLE_IDE_COMBINED_MODE
References: <I1ab8acd27947a71baf954f44d0741f81f48e5541+0@gerrit.coreboot.org>
Message-ID: <I1ab8acd27947a71baf954f44d0741f81f48e5541+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/231

-gerrit

commit 6060f7630470c14ad60ac885a2103c7286034779
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Sun Oct 9 14:26:21 2011 +0800

    sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
    
    Add this option to enable/disable SATA IDE Combined Mode feature
    
    Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/southbridge/amd/cimx/sb800/Kconfig |   16 ++++++++++++++++
 src/southbridge/amd/cimx/sb800/cfg.c   |    2 +-
 src/southbridge/amd/cimx/sb800/late.c  |    5 -----
 3 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index dc4dd7a..1370e7e 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -28,6 +28,22 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
         string
         default "southbridge/amd/cimx/sb800/bootblock.c"
 
+config ENABLE_IDE_COMBINED_MODE
+	bool "Enable SATA IDE combined mode"
+	default n
+	help
+	  If Combined Mode is enabled. IDE controller is exposed and
+	  SATA controller has control over Port0 through Port3,
+	  IDE controller has control over Port4 and Port5.
+
+	  If Combined Mode is disabled, IDE controller is hidden and
+	  SATA controller has full control of all 6 Ports when operating in non-IDE mode.
+
+config IDE_COMBINED_MODE
+	hex
+	default "0x0" if ENABLE_IDE_COMBINED_MODE
+	default "0x1" if !ENABLE_IDE_COMBINED_MODE
+
 choice
 	prompt "SATA Mode"
 	default SB800_SATA_IDE
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index a7801a8..a34dd14 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
   	sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
 	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
 								//TODO: set to secondary not take effect.
-	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
+	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE;
 	sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
 
   	/* Azalia HDA */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index d0e752f..74f952a 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -343,11 +343,6 @@ static void sb800_enable(device_t dev)
 		break;
 
 	case (0x14 << 3) | 1: /* 0:14:1 IDE */
-		if (dev->enabled) {
-			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED;
-		} else {
-  			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED;
-		}
 		break;
 
 	case (0x14 << 3) | 2: /* 0:14:2 HDA */



From gerrit at coreboot.org  Sun Oct  9 09:08:39 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Sun, 9 Oct 2011 09:08:39 +0200
Subject: [coreboot] Patch set updated for coreboot: 35d6eac sb800: Update
	entry point of sb_Before_Pci_Init
References: <I76ebad842e90b0f740abbec031165d7c39a80abf+0@gerrit.coreboot.org>
Message-ID: <I76ebad842e90b0f740abbec031165d7c39a80abf+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/230

-gerrit

commit 35d6eac5744aee2aab1b1b9f35667e67446707c2
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Sun Oct 9 14:25:56 2011 +0800

    sb800: Update entry point of sb_Before_Pci_Init
    
    Formally sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
    enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init
    will not get called.
    
    Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/northbridge/amd/agesa/family10/northbridge.c |    6 ++++++
 src/northbridge/amd/agesa/family14/northbridge.c |    3 +++
 src/northbridge/amd/amdfam10/northbridge.c       |    3 +++
 src/southbridge/amd/cimx/sb800/late.c            |    3 ---
 4 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index b3e4c63..b347469 100755
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -38,6 +38,9 @@
 #include <Porting.h>
 #include <AGESA.h>
 #include <Options.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
 #include "root_complex/chip.h"
 #include "northbridge.h"
 #include "amdfam10.h"
@@ -775,6 +778,9 @@ static void amdfam10_domain_read_resources(device_t dev)
 {
 	unsigned reg;
 
+#if CONFIG_AMD_SB_CIMX
+	sb_Before_Pci_Init();
+#endif
 	/* Find the already assigned resource pairs */
 	get_fx_devs();
 	for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index b2ca256..712145b 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -488,6 +488,9 @@ static void domain_read_resources(device_t dev)
     unsigned reg;
 
     printk(BIOS_DEBUG, "\nFam14h - domain_read_resources.\n");
+#if CONFIG_AMD_SB_CIMX
+    sb_Before_Pci_Init();
+#endif
 
     /* Find the already assigned resource pairs */
     get_fx_devs();
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 89bd673..33843b8 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -634,6 +634,9 @@ static void amdfam10_domain_read_resources(device_t dev)
 {
 	unsigned reg;
 
+#if CONFIG_AMD_SB_CIMX
+	sb_Before_Pci_Init();
+#endif
 	/* Find the already assigned resource pairs */
 	get_fx_devs();
 	for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b581212..d0e752f 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -418,9 +418,6 @@ static void sb800_enable(device_t dev)
 		break;
 	case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
 		sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
-
-		/* the last sb800 device */
-		sb_Before_Pci_Init();
 		break;
 
 	default:



From gerrit at coreboot.org  Sun Oct  9 09:08:40 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Sun, 9 Oct 2011 09:08:40 +0200
Subject: [coreboot] Patch set updated for coreboot: 84b249e sb800: sata
	combine mode configure fix
References: <I32e7101737f1dbfff49daa58670e6820b476b250+0@gerrit.coreboot.org>
Message-ID: <I32e7101737f1dbfff49daa58670e6820b476b250+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/229

-gerrit

commit 84b249e7750d850f524c68788708be7c9b7942e4
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Sun Oct 9 14:25:54 2011 +0800

    sb800: sata combine mode configure fix
    
    Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to
    configure SataIdeCombinedMode is wrong.
    
    sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller
      0: IDE controller is exposed and Combined Mode is enabled.
         SATA controller has control over Port0 through Port3,
         IDE controller has control over Port4 and Port5
      1: IDE controller is hidden and Combined Mode is disabled,
         SATA controller has full control of all 6 Ports when operating in non-IDE mode
    
    Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/vendorcode/amd/cimx/sb800/SATA.c   |    4 ++--
 src/vendorcode/amd/cimx/sb800/SBTYPE.h |   10 ++++++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index 1c0e7e6..b7bbacd 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -470,7 +470,7 @@ sataInitAfterPciEnum (
 
   if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
     // RIAD or AHCI
-    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
       // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
@@ -631,7 +631,7 @@ sataInitLatePost (
   //Enable write access to pci header, pm capabilities
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
 
-//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
 //  }
   sataBar5setting (pConfig, &ddBar5);
diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
index b8278cf..f8e825e 100644
--- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h
+++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
@@ -1106,6 +1106,16 @@ typedef unsigned int    CIM_STATUS;
  */
 #define CIMX_OPTION_ENABLED    1
 
+/**
+ * SATA_IDE_COMBINE_ENABLE  -Define  Enable Combined Mode
+ */
+#define SATA_IDE_COMBINE_ENABLE   0
+
+/**
+ * SATA_IDE_COMBINE_DISABLE  -Define  Disable Combined Mode
+ */
+#define SATA_IDE_COMBINE_DISABLE  1
+
 // mov al, code
 // out 80h, al
 // jmp $



From gerrit at coreboot.org  Sun Oct  9 09:08:40 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Sun, 9 Oct 2011 09:08:40 +0200
Subject: [coreboot] Patch set updated for coreboot: 16b2ad3 persimmon: sb800
	sata mode configure update
References: <I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+0@gerrit.coreboot.org>
Message-ID: <I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/227

-gerrit

commit 16b2ad39712307be5235bb0a00e501339f0afef1
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Sun Oct 9 14:24:44 2011 +0800

    persimmon: sb800 sata mode configure update
    
    persimmon configure sb800 sata mode according to the
    southbridge kconfig selection.
    
    Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/amd/persimmon/platform_cfg.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index 5e3c3f4..e4fedd9 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -103,7 +103,7 @@
  * @breif INCHIP Sata Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
-#define SATA_MODE			AHCI_MODE
+#define SATA_MODE			CONFIG_SB800_SATA_MODE
 
 /**
  * @breif INCHIP Sata IDE Controller Mode



From gerrit at coreboot.org  Sun Oct  9 09:08:41 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Sun, 9 Oct 2011 09:08:41 +0200
Subject: [coreboot] Patch set updated for coreboot: 1a3976e sb800: Add sata
	ahci/raid mode kconfig option
References: <I87a7814930ce3a7c38cde1e235d151223eea2107+0@gerrit.coreboot.org>
Message-ID: <I87a7814930ce3a7c38cde1e235d151223eea2107+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/225

-gerrit

commit 1a3976e5ab189193ece8114ac533b00af6f9a293
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Sun Oct 9 14:18:28 2011 +0800

    sb800: Add sata ahci/raid mode kconfig option
    
    If sb800 sata was configured as ahci or raid mode,
    locate the corresponding option rom at site-local directory by default.
    
    Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/southbridge/amd/cimx/sb800/Kconfig |   59 ++++++++++++++++++++++++++++++++
 1 files changed, 59 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 681c881..dc4dd7a 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -28,8 +28,67 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
         string
         default "southbridge/amd/cimx/sb800/bootblock.c"
 
+choice
+	prompt "SATA Mode"
+	default SB800_SATA_IDE
+	help
+	  Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
+	  The default is NATIVE.
+
+config SB800_SATA_IDE
+	bool "NATIVE"
+
+config SB800_SATA_AHCI
+	bool "AHCI"
+
+config SB800_SATA_RAID
+	bool "RAID"
+endchoice
+
+config SB800_SATA_MODE
+        hex
+	depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI)
+	default "0x0" if SB800_SATA_IDE
+	default "0x1" if SB800_SATA_RAID
+	default "0x2" if SB800_SATA_AHCI
+
 config SB_SUPERIO_HWM
         bool
         default n
+
+if SB800_SATA_AHCI
+config AHCI_ROM_ID
+	string "AHCI device PCI IDs"
+	default "1002,4391"
+
+config AHCI_ROM_FILE
+	string "AHCI ROM path and filename"
+	default "site-local/sb800/ahci.bin"
+endif
+
+if SB800_SATA_RAID
+config RAID_ROM_ID
+	string "RAID device PCI IDs"
+	default "1002,4393"
+        help
+          1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
+
+config RAID_ROM_FILE
+	string "RAID ROM path and filename"
+	default "site-local/sb800/raid.bin"
+
+config RAID_MISC_ROM
+        bool
+        default y
+        help
+          SB800 Promisc RAID Option ROM misc binary
+
+config RAID_MISC_ROM_FILE
+        string "RAID Misc ROM path and filename"
+        default "site-local/sb800/misc.bin"
+        depends on RAID_MISC_ROM
+
+endif
+
 endif #SOUTHBRIDGE_AMD_CIMX_SB800
 



From Kerry.She at amd.com  Sun Oct  9 09:06:52 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Sun, 9 Oct 2011 15:06:52 +0800
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com><CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com><CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
	<CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4107ABF637@sbjgexmb1.amd.com>

Hello, Thomas

> -----Original Message-----
> From: coreboot-bounces+kerry.she=amd.com at coreboot.org [mailto:coreboot-
> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Marc Jones
> Sent: Saturday, October 08, 2011 3:45 AM
> To: Thomas Gst?dtner
> Cc: coreboot
> Subject: Re: [coreboot] Issues with Supermicro H8SCM
> 
> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gst?dtner <thomas at gstaedtner.net>
> wrote:
> > On Wed, Oct 5, 2011 at 20:08, Marc Jones <marcj303 at gmail.com> wrote:
> >> On Tue, Oct 4, 2011 at 5:26 PM, Thomas Gst?dtner
> <thomas at gstaedtner.net> wrote:
> >>> Hi everyone,
> >>>
> >>> I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of
> >>> the boards AMD as of recently claims to officially support.
> >>> So I decided to try coreboot, but (as expected) it is not really an
> >>> out-of-the-box experience.
> >>>
> >>> First of all, flashrom does not support flashing out-of-the-box, but
> >>> Frederic Temporelli's patches (
> >>> http://patchwork.coreboot.org/patch/3326/ and
> >>> http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I
> tested
> >>> multiple reads and multiple writes, always worked), I can report that
> >>> to the flashrom list separately if you want.
> >>>
> >>> I built coreboot from the gerrit-branch (also tried a "stable"
> >>> revision), coreboot-4.0-1714-gf8adf7a, using the "default"
> >>> board-config incl. seabios (stable) as payload.
> >>> After powering on nothing happens (apart from the fans running and
> the
> >>> power led flashing) and it stays that way, it is silent on VGA as
> well
> >>> as serial.
> >>> After manually triggering a reset I immediately get the following
> >>> output on serial:
> >>>
> >>> coreboot-4.0-1714-gf8adf7a Wed Oct ?5 00:31:05 CEST 2011 starting...
> >>> BSP Family_Model:
> >>>
> >>> Here it hangs, and I don't quite know how to move on and debug the
> issue.
> >>>
> >>> Can you give me any hints where to go on from here? I have external
> >>> flashing equipment at hand (which also works fine btw.), but no fancy
> >>> bios-debugging hardware.
> >>>
> >>> Regards,
> >>>
> >>> thomasg
> >>>
> >>> P.S. In case anyone else stumbles upon it: the board has 2 separate
> >>> flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W
> >>> package on the left of the board) as well as a SST25VF016B, 16 Mbit,
> >>> as the SOIC8W on the right. The first one holds the IPMI firmware,
> the
> >>> second one the AMI BIOS.
> >>> Flashing requires a testclip or some really serious soldering skills.
> >>> Attaching a SO8 socket can only be done with hot air soldering.
> >>
> >> Hi Thomas,
> >>
> >> Thanks for the report. While many people overlap with the flashrom
> >> list, please post about those patches on that list. Seems that you
> >> should be able to ack them.
> >>
> >> ?It looks like maybe the platform build doesn't support your CPU.
> >> There have been a number of recent contributions from AMD, but they
> >> don't all align with the platform contributions. So, the H8SCM should
> >> support all fam10 revD, but may have issue with Fam10 rev E. To get
> >> more information, you can turn the console debug output to SPEW in
> >> menuconfig.
> >>
> >> Marc
> >>
> >>
> >>
> >> --
> >> http://se-eng.com
> >>
> >
> > Thanks for the advice Marc,
> >
> > I already had the loglevel set to spew (8). I additionally tried the
> > other "Verbose output" debugging options, unfortunately I don't get
> > any output at all when they are built in.
> > Also, while it is hard to find and AMD doesn't have any official
> > document confirming this, according to some google hits the processor
> > should be revision D1 not rev E (AMD model number: OS4170OFU6DGOWOF ).

I also found the latest code not boot on my H8SCM-F mainboard with Rev D1 processor.
So I have made some update to using the AGESA wrapper framework, the attachment is some of my update, with this series of patches applied, we can boot to Debian Linux Destop or Windows Server 2008 R2 standard edition.
Thanks
Kerry

> > (Sry for sending the mail twice, hit the wrong button)
> >
> 
> Oh, I just recalled something about the H8SCM. There is jumper to
> disable the bmc which might have a watchdog that coreboot can't deal
> with. Did you disable that?
> 
> Marc
> 
> 
> --
> http://se-eng.com
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

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From thomas at gstaedtner.net  Sun Oct  9 17:53:08 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Sun, 9 Oct 2011 17:53:08 +0200
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <F53A09371FB723428826B442A4B20A4107ABF56C@sbjgexmb1.amd.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
	<CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>
	<CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
	<CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107ABF56C@sbjgexmb1.amd.com>
Message-ID: <CABgBRiJP-xh74+h5QCQkoaOU6QMj0Ajre6dxwxuJKWSuLY=HHQ@mail.gmail.com>

On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She at amd.com> wrote:
> Hello, Thomas
>
>> -----Original Message-----
>> From: coreboot-bounces+kerry.she=amd.com at coreboot.org [mailto:coreboot-
>> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Marc Jones
>> Sent: Saturday, October 08, 2011 3:45 AM
>> To: Thomas Gst?dtner
>> Cc: coreboot
>> Subject: Re: [coreboot] Issues with Supermicro H8SCM
>>
>> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gst?dtner <thomas at gstaedtner.net>
>> wrote:
>> >
>> > Thanks for the advice Marc,
>> >
>> > I already had the loglevel set to spew (8). I additionally tried the
>> > other "Verbose output" debugging options, unfortunately I don't get
>> > any output at all when they are built in.
>> > Also, while it is hard to find and AMD doesn't have any official
>> > document confirming this, according to some google hits the processor
>> > should be revision D1 not rev E (AMD model number: OS4170OFU6DGOWOF ).
>
> I also found the latest code not boot on my H8SCM-F mainboard with Rev D1 processor.
> So I have made some update to using the AGESA wrapper framework,
> the attachment is some of my update,
> with this series of patches applied, we can boot to Debian Linux Destop or
> Windows Server 2008 R2 standard edition.
> Thanks
>

Hi Kerry,

first of all: thanks for your effort!
While I had no success at first, I now can get to the boot prompt
(haven't tried any further yet).

Anyway, I currently have 2 DIMMs, each 4 GiB.
A dual-channel configuration does not seem to work, the DIMMs are
detected, but coreboot throws an "ASSERTION FAILED" error (see
attached log cb_h8scm_01.log).
It seems to fail because it somehow seems to think no DIMM is found
(despite both DIMMs being detected). I tried disabling this check, but
this only leads to a reset.
The same problem exists with a single-DIMM configuration.

However, when I switch to a dual-DIMM, single-channel config, it at
first does not start at all (i.e. no output on serial and no heartbeat
from the BMC) - but when I trigger a manual reset it immediately
starts up (see attached log cb_h8scm_dimma1a2_success.log).

I'll report back when I find out more.
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From gerrit at coreboot.org  Mon Oct 10 08:18:11 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 10 Oct 2011 08:18:11 +0200
Subject: [coreboot] Patch set updated for coreboot: dc8722c persimmon: Add
	usb3 dev in devicetree
References: <If060ccb43df7fbe88bafc61e9e600a9120575437+0@gerrit.coreboot.org>
Message-ID: <If060ccb43df7fbe88bafc61e9e600a9120575437+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/232

-gerrit

commit dc8722c6d48a18ad82e8a4b2cc9afb8d6cfc25ec
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Oct 10 14:36:25 2011 +0800

    persimmon: Add usb3 dev in devicetree
    
    The sb800 southbridge requires the usb3 devices in the devicetree,
    Persimmon doesn't have the connector, so they are off.
    
    Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/amd/persimmon/devicetree.cb |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index 7da2169..fe87bca 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -87,6 +87,8 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 15.1 off end # PCIe PortB
 					device pci 15.2 off end # PCIe PortC
 					device pci 15.3 off end # PCIe PortD
+					device pci 16.0 off end # OHCI-USB3
+					device pci 16.2 off end # UHCI-USB3
 					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb800



From gerrit at coreboot.org  Mon Oct 10 08:18:12 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 10 Oct 2011 08:18:12 +0200
Subject: [coreboot] Patch set updated for coreboot: 6944d47 sb800: Add
	Kconfig option ENABLE_IDE_COMBINED_MODE
References: <I1ab8acd27947a71baf954f44d0741f81f48e5541+0@gerrit.coreboot.org>
Message-ID: <I1ab8acd27947a71baf954f44d0741f81f48e5541+3@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/231

-gerrit

commit 6944d473008bd12414d18b171240703346133653
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Sun Oct 9 14:26:21 2011 +0800

    sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
    
    Add this option to enable/disable SATA IDE Combined Mode feature
    
    Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/southbridge/amd/cimx/sb800/Kconfig |   16 ++++++++++++++++
 src/southbridge/amd/cimx/sb800/cfg.c   |    2 +-
 src/southbridge/amd/cimx/sb800/late.c  |    5 -----
 3 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index dc4dd7a..1370e7e 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -28,6 +28,22 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
         string
         default "southbridge/amd/cimx/sb800/bootblock.c"
 
+config ENABLE_IDE_COMBINED_MODE
+	bool "Enable SATA IDE combined mode"
+	default n
+	help
+	  If Combined Mode is enabled. IDE controller is exposed and
+	  SATA controller has control over Port0 through Port3,
+	  IDE controller has control over Port4 and Port5.
+
+	  If Combined Mode is disabled, IDE controller is hidden and
+	  SATA controller has full control of all 6 Ports when operating in non-IDE mode.
+
+config IDE_COMBINED_MODE
+	hex
+	default "0x0" if ENABLE_IDE_COMBINED_MODE
+	default "0x1" if !ENABLE_IDE_COMBINED_MODE
+
 choice
 	prompt "SATA Mode"
 	default SB800_SATA_IDE
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index a7801a8..a34dd14 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
   	sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
 	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
 								//TODO: set to secondary not take effect.
-	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
+	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE;
 	sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
 
   	/* Azalia HDA */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index d0e752f..74f952a 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -343,11 +343,6 @@ static void sb800_enable(device_t dev)
 		break;
 
 	case (0x14 << 3) | 1: /* 0:14:1 IDE */
-		if (dev->enabled) {
-			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED;
-		} else {
-  			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED;
-		}
 		break;
 
 	case (0x14 << 3) | 2: /* 0:14:2 HDA */



From gerrit at coreboot.org  Mon Oct 10 08:18:12 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 10 Oct 2011 08:18:12 +0200
Subject: [coreboot] Patch set updated for coreboot: f14ebb9 sb800: Update
	entry point of sb_Before_Pci_Init
References: <I76ebad842e90b0f740abbec031165d7c39a80abf+0@gerrit.coreboot.org>
Message-ID: <I76ebad842e90b0f740abbec031165d7c39a80abf+3@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/230

-gerrit

commit f14ebb9af7d47bae97b37158664c64448db442c9
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Sun Oct 9 14:25:56 2011 +0800

    sb800: Update entry point of sb_Before_Pci_Init
    
    Formally sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
    enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init
    will not get called.
    
    Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/northbridge/amd/agesa/family10/northbridge.c |    6 ++++++
 src/northbridge/amd/agesa/family14/northbridge.c |    3 +++
 src/northbridge/amd/amdfam10/northbridge.c       |    3 +++
 src/southbridge/amd/cimx/sb800/late.c            |    3 ---
 4 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index b3e4c63..b347469 100755
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -38,6 +38,9 @@
 #include <Porting.h>
 #include <AGESA.h>
 #include <Options.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
 #include "root_complex/chip.h"
 #include "northbridge.h"
 #include "amdfam10.h"
@@ -775,6 +778,9 @@ static void amdfam10_domain_read_resources(device_t dev)
 {
 	unsigned reg;
 
+#if CONFIG_AMD_SB_CIMX
+	sb_Before_Pci_Init();
+#endif
 	/* Find the already assigned resource pairs */
 	get_fx_devs();
 	for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index b2ca256..712145b 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -488,6 +488,9 @@ static void domain_read_resources(device_t dev)
     unsigned reg;
 
     printk(BIOS_DEBUG, "\nFam14h - domain_read_resources.\n");
+#if CONFIG_AMD_SB_CIMX
+    sb_Before_Pci_Init();
+#endif
 
     /* Find the already assigned resource pairs */
     get_fx_devs();
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 89bd673..33843b8 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -634,6 +634,9 @@ static void amdfam10_domain_read_resources(device_t dev)
 {
 	unsigned reg;
 
+#if CONFIG_AMD_SB_CIMX
+	sb_Before_Pci_Init();
+#endif
 	/* Find the already assigned resource pairs */
 	get_fx_devs();
 	for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b581212..d0e752f 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -418,9 +418,6 @@ static void sb800_enable(device_t dev)
 		break;
 	case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
 		sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
-
-		/* the last sb800 device */
-		sb_Before_Pci_Init();
 		break;
 
 	default:



From gerrit at coreboot.org  Mon Oct 10 08:18:13 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 10 Oct 2011 08:18:13 +0200
Subject: [coreboot] Patch set updated for coreboot: dd211b4 sb800: sata
	combine mode configure fix
References: <I32e7101737f1dbfff49daa58670e6820b476b250+0@gerrit.coreboot.org>
Message-ID: <I32e7101737f1dbfff49daa58670e6820b476b250+3@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/229

-gerrit

commit dd211b4537f4122403b20a9e8cf568a81e617cd8
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Sun Oct 9 14:25:54 2011 +0800

    sb800: sata combine mode configure fix
    
    Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to
    configure SataIdeCombinedMode is wrong.
    
    sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller
      0: IDE controller is exposed and Combined Mode is enabled.
         SATA controller has control over Port0 through Port3,
         IDE controller has control over Port4 and Port5
      1: IDE controller is hidden and Combined Mode is disabled,
         SATA controller has full control of all 6 Ports when operating in non-IDE mode
    
    Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/vendorcode/amd/cimx/sb800/SATA.c   |    4 ++--
 src/vendorcode/amd/cimx/sb800/SBTYPE.h |   10 ++++++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index 1c0e7e6..b7bbacd 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -470,7 +470,7 @@ sataInitAfterPciEnum (
 
   if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
     // RIAD or AHCI
-    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
       // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
@@ -631,7 +631,7 @@ sataInitLatePost (
   //Enable write access to pci header, pm capabilities
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
 
-//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
 //  }
   sataBar5setting (pConfig, &ddBar5);
diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
index b8278cf..f8e825e 100644
--- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h
+++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
@@ -1106,6 +1106,16 @@ typedef unsigned int    CIM_STATUS;
  */
 #define CIMX_OPTION_ENABLED    1
 
+/**
+ * SATA_IDE_COMBINE_ENABLE  -Define  Enable Combined Mode
+ */
+#define SATA_IDE_COMBINE_ENABLE   0
+
+/**
+ * SATA_IDE_COMBINE_DISABLE  -Define  Disable Combined Mode
+ */
+#define SATA_IDE_COMBINE_DISABLE  1
+
 // mov al, code
 // out 80h, al
 // jmp $



From gerrit at coreboot.org  Mon Oct 10 08:18:13 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 10 Oct 2011 08:18:13 +0200
Subject: [coreboot] Patch set updated for coreboot: 701e1e7 persimmon: sb800
	sata mode configure update
References: <I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+0@gerrit.coreboot.org>
Message-ID: <I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+3@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/227

-gerrit

commit 701e1e7d68150ce9d31bca103501aea50b300e65
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Sun Oct 9 14:24:44 2011 +0800

    persimmon: sb800 sata mode configure update
    
    persimmon configure sb800 sata mode according to the
    southbridge kconfig selection.
    
    Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/amd/persimmon/platform_cfg.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index 5e3c3f4..e4fedd9 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -103,7 +103,7 @@
  * @breif INCHIP Sata Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
-#define SATA_MODE			AHCI_MODE
+#define SATA_MODE			CONFIG_SB800_SATA_MODE
 
 /**
  * @breif INCHIP Sata IDE Controller Mode



From gerrit at coreboot.org  Mon Oct 10 10:53:13 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 10 Oct 2011 10:53:13 +0200
Subject: [coreboot] Patch set updated for coreboot: eb837a7 sb800: Add sata
	ahci/raid mode kconfig option
References: <I87a7814930ce3a7c38cde1e235d151223eea2107+0@gerrit.coreboot.org>
Message-ID: <I87a7814930ce3a7c38cde1e235d151223eea2107+3@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/225

-gerrit

commit eb837a74ad78ed6d98ba0799f7ed2ed8475b1fd5
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Oct 10 17:17:39 2011 +0800

    sb800: Add sata ahci/raid mode kconfig option
    
    If sb800 sata was configured as ahci or raid mode,
    give the option to add ROM files.
    
    Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/southbridge/amd/cimx/sb800/Kconfig      |   66 +++++++++++++++++++++++++++
 src/southbridge/amd/cimx/sb800/Makefile.inc |   18 +++++++
 2 files changed, 84 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 681c881..b7ac0db 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -28,8 +28,74 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
         string
         default "southbridge/amd/cimx/sb800/bootblock.c"
 
+choice
+	prompt "SATA Mode"
+	default SB800_SATA_IDE
+	help
+	  Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
+	  The default is NATIVE.
+
+config SB800_SATA_IDE
+	bool "NATIVE"
+	help
+	  NATIVE is the default mode and does not require a ROM.
+
+config SB800_SATA_AHCI
+	bool "AHCI"
+	help
+	  AHCI may work with or without AHCI ROM. It depends on the payload support.
+	  For example, seabios does not require the AHCI ROM.
+
+config SB800_SATA_RAID
+	bool "RAID"
+	help
+	  sb800 RAID mode must have the two required ROM files.
+
+endchoice
+
+config SB800_SATA_MODE
+        hex
+	depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI)
+	default "0x0" if SB800_SATA_IDE
+	default "0x1" if SB800_SATA_RAID
+	default "0x2" if SB800_SATA_AHCI
+
 config SB_SUPERIO_HWM
         bool
         default n
+
+if SB800_SATA_AHCI
+config AHCI_ROM_ID
+	string "AHCI device PCI IDs"
+	default "1002,4391"
+
+config SB800_AHCI_ROM
+	bool "Add a AHCI ROM"
+
+config AHCI_ROM_FILE
+	string "AHCI ROM path and filename"
+	depends on SB800_AHCI_ROM
+	default "site-local/sb800/ahci.bin"
+endif
+
+if SB800_SATA_RAID
+config RAID_ROM_ID
+	string "RAID device PCI IDs"
+	default "1002,4393"
+        help
+          1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
+
+config RAID_ROM_FILE
+	string "RAID ROM path and filename"
+	depends on SB800_SATA_RAID
+	default "site-local/sb800/raid.bin"
+
+config RAID_MISC_ROM_FILE
+        string "RAID Misc ROM path and filename"
+        default "site-local/sb800/misc.bin"
+	depends on SB800_SATA_RAID
+
+endif
+
 endif #SOUTHBRIDGE_AMD_CIMX_SB800
 
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index acc5fdf..30c0d39 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -31,4 +31,22 @@ ramstage-y += late.c
 driver-y   += smbus.c
 driver-y   += lpc.c
 
+ifeq ($(CONFIG_SB800_SATA_AHCI), y)
+ifdef CONFIG_SB800_AHCI_ROM
+	stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID))
+	cbfs-files-y += pci$(stripped_ahci_rom_id).rom
+	pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE))
+	pci$(stripped_ahci_rom_id).rom-type := optionrom
+endif
+endif
 
+ifeq ($(CONFIG_SB800_SATA_RAID), y)
+	stripped_raid_rom_id = $(call strip_quotes,$(CONFIG_RAID_ROM_ID))
+	cbfs-files-y += pci$(stripped_raid_rom_id).rom
+	pci$(stripped_raid_rom_id).rom-file := $(call strip_quotes,$(CONFIG_RAID_ROM_FILE))
+	pci$(stripped_raid_rom_id).rom-type := optionrom
+
+	cbfs-files-y += raid/misc.bin
+	raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE))
+	raid/misc.bin-type := raw
+endif



From Kerry.She at amd.com  Mon Oct 10 11:47:24 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Mon, 10 Oct 2011 17:47:24 +0800
Subject: [coreboot] kconfig question
Message-ID: <F53A09371FB723428826B442A4B20A4107B6B251@sbjgexmb1.amd.com>

Hello All,

 

I add a choice kconfig option to the southbridge chipset kconfig.

I want to override the default choice in the mainboard kconfig, but I
can't figure out how to do it.

The choice is below. Can anyone offer a solution? 

 

+choice

+     prompt "SATA Mode"

+     default SB800_SATA_IDE

+     help

+       Select the mode in which SATA should be driven. NATIVE AHCI, or
RAID.

+       The default is NATIVE.

+

+config SB800_SATA_IDE

+     bool "NATIVE"

+     help

+       NATIVE is the default mode and does not require a ROM.

+

+config SB800_SATA_AHCI

+     bool "AHCI"

+     help

+       AHCI may work with or without AHCI ROM. It depends on the
payload support.

+       For example, seabios does not require the AHCI ROM.

+

+config SB800_SATA_RAID

+     bool "RAID"

+     help

+       sb800 RAID mode must have the two required ROM files.

+

+endchoice

 

 

Regards, 
Kerry Sheh < kerry.she at amd.com>
Tel:  86-10-6280-1415 
Mobile:  86 - 152 1018 2083 

 

 

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From gerrit at coreboot.org  Mon Oct 10 12:55:34 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 10 Oct 2011 12:55:34 +0200
Subject: [coreboot] Patch set updated for coreboot: 42acf3c mainboard:
	complete the sb800 devicetree even device is off
References: <I76ebad842e90b0f740abbec031165d7c39a80abf+0@gerrit.coreboot.org>
Message-ID: <I76ebad842e90b0f740abbec031165d7c39a80abf+4@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/230

-gerrit

commit 42acf3ccf042ecf596df8d149ad66512e81a8fc8
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Oct 10 19:19:46 2011 +0800

    mainboard: complete the sb800 devicetree even device is off
    
    sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
    enable_dev() function. If the devicetree don't have this device,
    then sb_Before_Pci_Init will not get called.
    
    Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/amd/inagua/devicetree.cb    |    2 ++
 src/mainboard/asrock/e350m1/devicetree.cb |    2 ++
 src/southbridge/amd/cimx/sb800/late.c     |    4 +++-
 3 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 82658cf..32d9a26 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -71,6 +71,8 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 15.1 on end # PCIe PortB
 					device pci 15.2 on end # PCIe PortC
 					device pci 15.3 on end # PCIe PortD
+					device pci 16.0 off end # OHCI USB3
+					device pci 16.2 off end # EHCI USB3
 					register "gpp_configuration" = "4" #1:1:1:1
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb800
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index bff8151..ca5cf2b 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -103,6 +103,8 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 15.1 on  end # PCIe PortB: NIC
 					device pci 15.2 on  end # PCIe PortC: USB3
 					device pci 15.3 off end # PCIe PortD
+					device pci 16.0 off end # OHCI USB3
+					device pci 16.2 off end # EHCI USB3
 
 					# gpp_configuration options
 					#0000: PortA lanes[3:0]
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b581212..c36ee03 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -419,7 +419,9 @@ static void sb800_enable(device_t dev)
 	case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
 		sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
 
-		/* the last sb800 device */
+		/* call the CIMX entry at the last sb800 device,
+		 * so make sure the mainboard devicetree is complete
+		 */
 		sb_Before_Pci_Init();
 		break;
 



From gerrit at coreboot.org  Mon Oct 10 12:55:34 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 10 Oct 2011 12:55:34 +0200
Subject: [coreboot] Patch set updated for coreboot: eb0e452 sb800: sata
	combine mode configure fix
References: <I32e7101737f1dbfff49daa58670e6820b476b250+0@gerrit.coreboot.org>
Message-ID: <I32e7101737f1dbfff49daa58670e6820b476b250+4@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/229

-gerrit

commit eb0e4526ffeb1330d9c2b9f2c69cac6a4f3a41ec
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Oct 10 18:23:49 2011 +0800

    sb800: sata combine mode configure fix
    
    Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to
    configure SataIdeCombinedMode is wrong.
    
    sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller
      0: IDE controller is exposed and Combined Mode is enabled.
         SATA controller has control over Port0 through Port3,
         IDE controller has control over Port4 and Port5
      1: IDE controller is hidden and Combined Mode is disabled,
         SATA controller has full control of all 6 Ports when operating in non-IDE mode
    
    Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/vendorcode/amd/cimx/sb800/SATA.c   |    4 ++--
 src/vendorcode/amd/cimx/sb800/SBTYPE.h |   10 ++++++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index 1c0e7e6..b7bbacd 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -470,7 +470,7 @@ sataInitAfterPciEnum (
 
   if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
     // RIAD or AHCI
-    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
       // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
@@ -631,7 +631,7 @@ sataInitLatePost (
   //Enable write access to pci header, pm capabilities
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
 
-//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
 //  }
   sataBar5setting (pConfig, &ddBar5);
diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
index b8278cf..f8e825e 100644
--- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h
+++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
@@ -1106,6 +1106,16 @@ typedef unsigned int    CIM_STATUS;
  */
 #define CIMX_OPTION_ENABLED    1
 
+/**
+ * SATA_IDE_COMBINE_ENABLE  -Define  Enable Combined Mode
+ */
+#define SATA_IDE_COMBINE_ENABLE   0
+
+/**
+ * SATA_IDE_COMBINE_DISABLE  -Define  Disable Combined Mode
+ */
+#define SATA_IDE_COMBINE_DISABLE  1
+
 // mov al, code
 // out 80h, al
 // jmp $



From gerrit at coreboot.org  Mon Oct 10 12:55:35 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 10 Oct 2011 12:55:35 +0200
Subject: [coreboot] Patch set updated for coreboot: 429729d persimmon: sb800
	sata mode configure update
References: <I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+0@gerrit.coreboot.org>
Message-ID: <I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+4@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/227

-gerrit

commit 429729d93d3562ccca5f2f13f407ae7a8a971212
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Oct 10 18:13:51 2011 +0800

    persimmon: sb800 sata mode configure update
    
    persimmon configure sb800 sata mode according to the
    southbridge kconfig selection.
    
    Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/amd/persimmon/Kconfig        |   13 ++-----------
 src/mainboard/amd/persimmon/platform_cfg.h |    2 +-
 2 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index 5f85688..72b7947 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -124,20 +124,11 @@ config VGA_BIOS_ID
         string
         default "1002,9802"
 
-config AHCI_BIOS
+
+config SB800_AHCI_ROM
         bool
         default n
 
-#config AHCI_BIOS_FILE
-#        string "AHCI ROM path and filename"
-#        depends on AHCI_BIOS
-#        default "rom/ahci/sb900.bin"
-
-config AHCI_BIOS_ID
-        string "AHCI device PCI IDs"
-        depends on AHCI_BIOS
-        default "1002,4391"
-
 config DRIVERS_PS2_KEYBOARD
         bool
         default n
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index 5e3c3f4..e4fedd9 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -103,7 +103,7 @@
  * @breif INCHIP Sata Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
-#define SATA_MODE			AHCI_MODE
+#define SATA_MODE			CONFIG_SB800_SATA_MODE
 
 /**
  * @breif INCHIP Sata IDE Controller Mode



From paulepanter at users.sourceforge.net  Mon Oct 10 13:57:17 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Mon, 10 Oct 2011 13:57:17 +0200
Subject: [coreboot] Patch set updated for coreboot: 429729d persimmon:
 sb800 sata mode configure update
In-Reply-To: <I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+4@gerrit.coreboot.org>
References: <I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+0@gerrit.coreboot.org>
	<I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+4@gerrit.coreboot.org>
Message-ID: <1318247837.4394.49.camel@mattotaupa>

Dear Kerry,


Am Montag, den 10.10.2011, 12:55 +0200 schrieb Kerry Sheh:

[?]

> commit 429729d93d3562ccca5f2f13f407ae7a8a971212
> Author: Kerry Sheh <shekairui at gmail.com>
> Date:   Mon Oct 10 18:13:51 2011 +0800
> 
>     persimmon: sb800 sata mode configure update
>     
>     persimmon configure sb800 sata mode according to the
>     southbridge kconfig selection.

you could use the following commit message to make the commit summary
more specific.

        persimmon: Configure sb800 sata mode using kconfig selection
        
        Use the kconfig selection CONFIG_SB800_SATA_MODE to configure
        the sb800 sata mode of persimmon.

Using `git commit --amend` it is easy to update the commit message.
    
>     Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca
>     Signed-off-by: Kerry Sheh <kerry.she at amd.com>
>     Signed-off-by: Kerry Sheh <shekairui at gmail.com>
> ---
>  src/mainboard/amd/persimmon/Kconfig        |   13 ++-----------
>  src/mainboard/amd/persimmon/platform_cfg.h |    2 +-
>  2 files changed, 3 insertions(+), 12 deletions(-)

[?]


Thanks,

Paul
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From gerrit at coreboot.org  Mon Oct 10 14:13:26 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Mon, 10 Oct 2011 14:13:26 +0200
Subject: [coreboot] New patch to review for coreboot: 0ea79df Fixed hangup
	problem with processors that lack PowerNow!
References: <Id1b739ec5ae8fbe65bbae1dbde7d41db5f18212f+0@gerrit.coreboot.org>
Message-ID: <Id1b739ec5ae8fbe65bbae1dbde7d41db5f18212f+1@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/247

-gerrit

commit 0ea79dfc52268d1d519c36d1d5290a37bf57f57f
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Mon Oct 10 13:59:53 2011 +0200

    Fixed hangup problem with processors that lack PowerNow!
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: Id1b739ec5ae8fbe65bbae1dbde7d41db5f18212f
---
 src/cpu/amd/model_fxx/fidvid.c        |    4 ++++
 src/cpu/amd/model_fxx/powernow_acpi.c |   13 +++++++------
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c
index bbafde6..62a25d6 100644
--- a/src/cpu/amd/model_fxx/fidvid.c
+++ b/src/cpu/amd/model_fxx/fidvid.c
@@ -347,6 +347,10 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
 	u32 fid_max;
 	int loop;
 
+	if((cpuid_edx(0x80000007)&0x06)!=0x06) {
+		return; // FID/VID change not supported
+	}
+
 	msr = rdmsr(0xc0010042);
 	fid_max = ((msr.lo >> 16) & 0x3f);	/* max fid */
 #if FX_SUPPORT
diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index c49322f..dd7038d 100644
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -595,6 +595,13 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	u8 Max_fid, Start_fid, Start_vid, Max_vid;
 	struct cpuid_result cpuid1 = cpuid(0x80000001);
 
+	/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
+	cpuid1 = cpuid(0x80000007);
+	if((cpuid1.edx & 0x6)!=0x6) {
+		printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
+		return 0;
+	}
+
 	// Because I don't know how to read msr registers from
 	// other CPU's I assume they all have the same SYSCONF values
 	msr = rdmsr(0xc0010042);
@@ -621,12 +628,6 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 		printk(BIOS_WARNING, "Unknown CPU, please update the powernow_acpi.c\n");
 		return 0;
 	}
-	/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
-	cpuid1 = cpuid(0x80000007);
-	if((cpuid1.edx & 0x6)!=0x6) {
-		printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
-		return 0;
-	}
 
 #if CONFIG_MAX_PHYSICAL_CPUS==1
 	// IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us



From gerrit at coreboot.org  Mon Oct 10 14:52:30 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Mon, 10 Oct 2011 14:52:30 +0200
Subject: [coreboot] Patch set updated for coreboot: c626561 Fixes several
	issues with amd k8 SSDT P-state generation
References: <I61f6e2210b84ccba33a36c5efc866447b7134417+0@gerrit.coreboot.org>
Message-ID: <I61f6e2210b84ccba33a36c5efc866447b7134417+3@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/239

-gerrit

commit c626561a2308efad8b07920932248d15f819e314
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Thu Oct 6 18:43:43 2011 +0200

    Fixes several issues with amd k8 SSDT P-state generation
    
    First issue fixed:
    For multi-socket CPU the current implementation emitted
    Processor objects for cores in the first CPU only. This
    commit fixes the bug by really emitting one Processor
    object for each core. However, the unlikely case of mixed
    CPU models is still not handled correctly.
    
    Second issue fixed:
    One loop was wrong in case a processor in the table declares
    no P-states at all. The rewritten loop is safe. Some possibly
    dangerous array lengths were also fixed.
    
    Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV
    according to the BKDG. The current implementation always set it
    to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS.
    
    Fourth issue: If a processor without PowerNow! support was inserted in a
    system with coreboot configured with SET_FIDVID then the boot process hanged
    mysteriously and very early. Apparently because init_fidvid_ap tampers with
    non-existing registers. This commit fixes the bug by bailing out
    from init_fidvid_ap if PowerNow! capability is missing.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417
---
 src/cpu/amd/model_fxx/fidvid.c        |    4 ++
 src/cpu/amd/model_fxx/powernow_acpi.c |   86 +++++++++++++++++++++++++--------
 2 files changed, 69 insertions(+), 21 deletions(-)

diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c
index bbafde6..62a25d6 100644
--- a/src/cpu/amd/model_fxx/fidvid.c
+++ b/src/cpu/amd/model_fxx/fidvid.c
@@ -347,6 +347,10 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
 	u32 fid_max;
 	int loop;
 
+	if((cpuid_edx(0x80000007)&0x06)!=0x06) {
+		return; // FID/VID change not supported
+	}
+
 	msr = rdmsr(0xc0010042);
 	fid_max = ((msr.lo >> 16) & 0x3f);	/* max fid */
 #if FX_SUPPORT
diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index bbcf013..b39eee1 100644
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -586,15 +586,26 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	u8 cmp_cap;
 	struct cpuentry *data = NULL;
 	uint32_t control;
-	int i = 0, index, len = 0, Pstate_num = 0;
+	int i = 0, index = 0, len = 0, Pstate_num = 0, dev = 0;
 	msr_t msr;
-	u8 Pstate_fid[10];
-	u16 Pstate_feq[10];
-	u8 Pstate_vid[10];
-	u32 Pstate_power[10];
+	u8 Pstate_fid[MAXP+1];
+	u16 Pstate_feq[MAXP+1];
+	u8 Pstate_vid[MAXP+1];
+	u32 Pstate_power[MAXP+1];
 	u8 Max_fid, Start_fid, Start_vid, Max_vid;
-	struct cpuid_result cpuid1 = cpuid(0x80000001);
+	struct cpuid_result cpuid1;
+
+	/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
+	cpuid1 = cpuid(0x80000007);
+	if((cpuid1.edx & 0x6)!=0x6) {
+		printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
+		return 0;
+	}
+
+	cpuid1 = cpuid(0x80000001);
 
+	// Because I don't know how to read msr registers from
+	// other CPU's I assume they all have the same SYSCONF values
 	msr = rdmsr(0xc0010042);
 	Max_fid = (msr.lo & 0x3F0000) >> 16;
 	Max_vid = (msr.hi & 0x3F0000) >> 16;
@@ -620,24 +631,50 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 		return 0;
 	}
 
-	/* IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */
-	control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (1 << 29);
+#if CONFIG_MAX_PHYSICAL_CPUS==1
+	// IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us
+	control = (3 << 30) | (2 << 28) | (2 << 20) | (0 << 18) | (5 << 11);
+#else
+	// MP-systems should default to RVO=0mV (no ramp voltage)
+	// IRT 80us RVO = 0mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us
+	control = (3 << 30) | (0 << 28) | (2 << 20) | (0 << 18) | (5 << 11);
+#endif
+	// RVO (Ramp Voltage Offset)
+	//   00   0mV (default for MP-systems)
+	//   01  25mV
+	//   10  50mV (default)
+	//   11  75mV
+	// IRT (Isochronous Release Time)
+	//   00  10uS
+	//   01  20uS
+	//   10  40uS
+	//   11  80uS (default)
+	// MVS (Maximum Voltage Step)
+	//   00  25mV (default)
+	//   01  50mV (reserved)
+	//   10 100mV (reserved)
+	//   11 200mV (reserved)
+	// VST (Voltage Stabilization Time)
+	//   time = value*20uS  (default value: 5 => 100uS)
+	// PLL_LOCK_TIME
+	//   time is value*1uS (often seen value: 2uS)
+	//
+
 	len = 0;
-	Pstate_num = 0;
 
-	Pstate_fid[Pstate_num] = Max_fid;
-	Pstate_feq[Pstate_num] = fid_to_freq(Max_fid);
-	Pstate_vid[Pstate_num] = Max_vid;
-	Pstate_power[Pstate_num] = data->pwr * 100;
-	Pstate_num++;
+	Pstate_fid[0] = Max_fid;
+	Pstate_feq[0] = fid_to_freq(Max_fid);
+	Pstate_vid[0] = Max_vid;
+	Pstate_power[0] = data->pwr * 100;
 
-	do {
+	for(Pstate_num = 1;
+	    (Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0);
+	    Pstate_num++) {
 		Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
 		Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz;
 		Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage);
 		Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100;
-		Pstate_num++;
-	} while ((Pstate_num < MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0));
+	}
 
 	for (i=0;i<Pstate_num;i++)
 		printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,
@@ -645,11 +682,18 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 		       vid_from_reg(Pstate_vid[i]),
 		       Pstate_power[i]);
 
-	for (index = 0; index < (cmp_cap + 1); index++) {
-		len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
-				Pstate_fid, Pstate_power, index,
-				pcontrol_blk, plen, onlyBSP, control);
+	for (dev = 0x18; dev < 0x1c; dev++) {
+		if(dev_find_slot(0, PCI_DEVFN(dev, 0))==NULL)
+			continue;
+
+		for (i = 0; i < (cmp_cap + 1); i++) {
+			len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
+					Pstate_fid, Pstate_power, index+i,
+					pcontrol_blk, plen, onlyBSP, control);
+		}
+		index += i;
 	}
+	printk(BIOS_DEBUG,"%d Processor objects emitted to SSDT\n",index);
 
 	return len;
 }



From svn at coreboot.org  Mon Oct 10 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 10 Oct 2011 16:00:02 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1RDGOg-0002zC-1S@ra.coresystems.de>

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From alperenkose at buyutech.com.tr  Mon Oct 10 18:02:23 2011
From: alperenkose at buyutech.com.tr (=?ISO-8859-1?Q?Alp_Eren_K=F6se?=)
Date: Mon, 10 Oct 2011 19:02:23 +0300
Subject: [coreboot] make crossgcc fails with 'Building IASL 20110623 ...
	failed'
Message-ID: <CAOz08zEcS0yp6K5SYH7OkxQNg_whFVJZEFouYRpwKGw-Cv6yMg@mail.gmail.com>

As written on the subject 'make crossgcc' fails as following:
Skipping GDB as requested by command line
Building IASL 20110623 ... failed
make[1]: *** [build-without-gdb] Error 1
make: *** [crossgcc] Error 2

Anyone knows why?
and the "util/crossgcc/acpica-unix-20110623/compiler/crossgcc-build.log"
file is at the attachment.

complete output below:

Welcome to the coresystems cross toolchain builder v1.04 (August 8th, 2011)

Will skip GDB ... ok
Downloading tar balls ...
 * gmp-5.0.1.tar.bz2 (downloading)
 * mpfr-3.0.0.tar.bz2 (downloading)
 * mpc-0.8.2.tar.gz (downloading)
 * libelf-0.8.13.tar.gz (downloading)
 * gcc-core-4.5.2.tar.bz2 (downloading)
 * binutils-2.20.1.tar.bz2 (downloading)
 * acpica-unix-20110623.tar.gz (downloading)
Downloaded tar balls ... ok
Unpacking and patching ...
 * gmp-5.0.1.tar.bz2
 * mpfr-3.0.0.tar.bz2
   o mpfr-3.0.0_allpatches_20101216.patch
 * mpc-0.8.2.tar.gz
 * libelf-0.8.13.tar.gz
 * gcc-core-4.5.2.tar.bz2
   o gcc-4.5.2_pragma.patch
 * binutils-2.20.1.tar.bz2
   o binutils-2.20.1_no-bfd-doc.patch
 * acpica-unix-20110623.tar.gz
Unpacked and patched ... ok
Building GMP 5.0.1 ... ok
Building MPFR 3.0.0 ... ok
Building MPC 0.8.2 ... ok
Building libelf 0.8.13 ... ok
Building binutils 2.20.1 ... ok
Building GCC 4.5.2 ... ok
Skipping GDB as requested by command line
Building IASL 20110623 ... failed
make[1]: *** [build-without-gdb] Error 1
make: *** [crossgcc] Error 2
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From vidwer at gmail.com  Mon Oct 10 18:13:17 2011
From: vidwer at gmail.com (Idwer Vollering)
Date: Mon, 10 Oct 2011 18:13:17 +0200
Subject: [coreboot] make crossgcc fails with 'Building IASL 20110623 ...
	failed'
In-Reply-To: <CAOz08zEcS0yp6K5SYH7OkxQNg_whFVJZEFouYRpwKGw-Cv6yMg@mail.gmail.com>
References: <CAOz08zEcS0yp6K5SYH7OkxQNg_whFVJZEFouYRpwKGw-Cv6yMg@mail.gmail.com>
Message-ID: <CAPp9Orn_rQ04mp4LxSA5FpaFxz3DGttsdzOaVHzpBv6JsdrN0g@mail.gmail.com>

2011/10/10 Alp Eren K?se <alperenkose at buyutech.com.tr>:
> As written on the subject 'make crossgcc' fails as following:
> Skipping GDB as requested by command line
> Building IASL 20110623 ... failed
> make[1]: *** [build-without-gdb] Error 1
> make: *** [crossgcc] Error 2
>
> Anyone knows why?
> and the "util/crossgcc/acpica-unix-20110623/compiler/crossgcc-build.log"
> file is at the attachment.
>
> complete output below:
>
> Welcome to the coresystems cross toolchain builder v1.04 (August 8th, 2011)
>
> Will skip GDB ... ok
> Downloading tar balls ...
> ?* gmp-5.0.1.tar.bz2 (downloading)
> ?* mpfr-3.0.0.tar.bz2 (downloading)
> ?* mpc-0.8.2.tar.gz (downloading)
> ?* libelf-0.8.13.tar.gz (downloading)
> ?* gcc-core-4.5.2.tar.bz2 (downloading)
> ?* binutils-2.20.1.tar.bz2 (downloading)
> ?* acpica-unix-20110623.tar.gz (downloading)
> Downloaded tar balls ... ok
> Unpacking and patching ...
> ?* gmp-5.0.1.tar.bz2
> ?* mpfr-3.0.0.tar.bz2
> ?? o mpfr-3.0.0_allpatches_20101216.patch
> ?* mpc-0.8.2.tar.gz
> ?* libelf-0.8.13.tar.gz
> ?* gcc-core-4.5.2.tar.bz2
> ?? o gcc-4.5.2_pragma.patch
> ?* binutils-2.20.1.tar.bz2
> ?? o binutils-2.20.1_no-bfd-doc.patch
> ?* acpica-unix-20110623.tar.gz
> Unpacked and patched ... ok
> Building GMP 5.0.1 ... ok
> Building MPFR 3.0.0 ... ok
> Building MPC 0.8.2 ... ok
> Building libelf 0.8.13 ... ok
> Building binutils 2.20.1 ... ok
> Building GCC 4.5.2 ... ok
> Skipping GDB as requested by command line
> Building IASL 20110623 ... failed
> make[1]: *** [build-without-gdb] Error 1
> make: *** [crossgcc] Error 2
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Can you try this patch?

--- acpica-unix-20110623.orig/compiler/Makefile 2011-06-23
18:34:09.000000000 +0200
+++ acpica-unix-20110623/compiler/Makefile      2011-09-30
13:40:22.700774117 +0200
@@ -43,7 +43,6 @@
     -Wall \
     -Wbad-function-cast \
     -Wdeclaration-after-statement \
-    -Werror \
     -Wformat=2 \
     -Wmissing-declarations \
     -Wmissing-prototypes \
@@ -243,16 +242,16 @@
 # by the utilities above and they are not necessarily ANSI C, etc.
 #
 aslcompilerlex.o :   aslcompilerlex.c
-       $(CC) -c $(CFLAGS) -Wall -Werror -Wstrict-aliasing=0 -o$@ $?
+       $(CC) -c $(CFLAGS) -Wall -Wstrict-aliasing=0 -o$@ $?

 aslcompilerparse.o : aslcompilerparse.c
-       $(CC) -c $(CFLAGS) -Wall -Werror -Wstrict-aliasing=0 -o$@ $?
+       $(CC) -c $(CFLAGS) -Wall -Wstrict-aliasing=0 -o$@ $?

 dtparserlex.o :      dtparserlex.c
-       $(CC) -c $(CFLAGS) -Wall -Werror -Wstrict-aliasing=0 -o$@ $?
+       $(CC) -c $(CFLAGS) -Wall -Wstrict-aliasing=0 -o$@ $?

 dtparserparse.o :    dtparserparse.c
-       $(CC) -c $(CFLAGS) -Wall -Werror -Wstrict-aliasing=0 -o$@ $?
+       $(CC) -c $(CFLAGS) -Wall -Wstrict-aliasing=0 -o$@ $?


 #



From gerrit at coreboot.org  Mon Oct 10 23:28:13 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Mon, 10 Oct 2011 23:28:13 +0200
Subject: [coreboot] Patch set updated for coreboot: feb5cbb Fixed broken
	MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
References: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+0@gerrit.coreboot.org>
Message-ID: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+4@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/238

-gerrit

commit feb5cbb72fc0424f9aecf0db122d2344b4fb9512
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Thu Oct 6 18:21:19 2011 +0200

    Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
    
    AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB to
    mark dram memory above 4GB as WB. However, AMD K8
    rev E and earlier don't implement this bit and therefore need
    MTRR spanning dram memory above 4GB. The current implementation
    of amd_setup_mtrrs never generate MTRR above 4GB.
    This caused memory > 4GB not to be recognized in e.g. Linux on those
    rev E or older platforms. This commit should fix that bug.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1
---
 src/cpu/amd/mtrr/amd_mtrr.c |   19 ++++++++++++++++---
 1 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 623a344..c5e01b1 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -112,7 +112,14 @@ void amd_setup_mtrrs(void)
 	struct mem_state state;
 	unsigned long i;
 	msr_t msr, sys_cfg;
-
+	// Test if this CPU is a Fam 0Fh rev. F or later
+	const int cpu_id = cpuid_eax(0x80000001);
+	const int has_tom2wb =
+		 (((cpu_id>>8 )&0xf)  > 0xf) || // Family > 0F
+		((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F
+		 (((cpu_id>>16)&0xf) >= 0x4));  // Rev>=F deduced from rev tables
+	if(has_tom2wb)
+		printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB\n");
 
 	/* Enable the access to AMD RdDram and WrDram extension bits */
 	disable_cache();
@@ -168,7 +175,9 @@ void amd_setup_mtrrs(void)
 		msr.hi = state.tomk >> 22;
 		msr.lo = state.tomk << 10;
 		wrmsr(TOP_MEM2, msr);
-		sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB;
+		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
+		if(has_tom2wb)
+			sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
 	}
 
 	/* zero the IORR's before we enable to prevent
@@ -201,5 +210,9 @@ void amd_setup_mtrrs(void)
 	/* Now that I have mapped what is memory and what is not
 	 * Setup the mtrrs so we can cache the memory.
 	 */
-	x86_setup_var_mtrrs(address_bits, 0);
+
+	// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need
+	// variable MTRR to span memory above 4GB
+	// Lower revisions K8 need variable MTRR over 4GB
+	x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1);
 }



From raxtum at gmail.com  Mon Oct 10 17:53:32 2011
From: raxtum at gmail.com (=?UTF-8?B?0J3QuNC60L7Qu9Cw0Lkg0J/QvtC90L7QvNCw0YDQtdCy?=)
Date: Mon, 10 Oct 2011 19:53:32 +0400
Subject: [coreboot] Problem with coreboot and flashrom
Message-ID: <CA+Q3tg4-NqazbpY9hkcEtv3D=znKr3iXPKgr5U6F+GcfwVCMxA@mail.gmail.com>

I was flashed bios with coreboot and after that network card, usb,
video card not working. flashrom not working too, it start flash bios
and stop at probing chip. Can anybody help me?
Mother board: http://www.gigabyte.ru/products/page/mb/ga-ma78gm-s2h_11
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From Kerry.She at amd.com  Sun Oct  9 07:17:19 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Sun, 9 Oct 2011 13:17:19 +0800
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com><CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com><CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
	<CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4107ABF56C@sbjgexmb1.amd.com>

Hello, Thomas

> -----Original Message-----
> From: coreboot-bounces+kerry.she=amd.com at coreboot.org [mailto:coreboot-
> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Marc Jones
> Sent: Saturday, October 08, 2011 3:45 AM
> To: Thomas Gst?dtner
> Cc: coreboot
> Subject: Re: [coreboot] Issues with Supermicro H8SCM
> 
> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gst?dtner <thomas at gstaedtner.net>
> wrote:
> > On Wed, Oct 5, 2011 at 20:08, Marc Jones <marcj303 at gmail.com> wrote:
> >> On Tue, Oct 4, 2011 at 5:26 PM, Thomas Gst?dtner
> <thomas at gstaedtner.net> wrote:
> >>> Hi everyone,
> >>>
> >>> I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of
> >>> the boards AMD as of recently claims to officially support.
> >>> So I decided to try coreboot, but (as expected) it is not really an
> >>> out-of-the-box experience.
> >>>
> >>> First of all, flashrom does not support flashing out-of-the-box, but
> >>> Frederic Temporelli's patches (
> >>> http://patchwork.coreboot.org/patch/3326/ and
> >>> http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I
> tested
> >>> multiple reads and multiple writes, always worked), I can report that
> >>> to the flashrom list separately if you want.
> >>>
> >>> I built coreboot from the gerrit-branch (also tried a "stable"
> >>> revision), coreboot-4.0-1714-gf8adf7a, using the "default"
> >>> board-config incl. seabios (stable) as payload.
> >>> After powering on nothing happens (apart from the fans running and
> the
> >>> power led flashing) and it stays that way, it is silent on VGA as
> well
> >>> as serial.
> >>> After manually triggering a reset I immediately get the following
> >>> output on serial:
> >>>
> >>> coreboot-4.0-1714-gf8adf7a Wed Oct ?5 00:31:05 CEST 2011 starting...
> >>> BSP Family_Model:
> >>>
> >>> Here it hangs, and I don't quite know how to move on and debug the
> issue.
> >>>
> >>> Can you give me any hints where to go on from here? I have external
> >>> flashing equipment at hand (which also works fine btw.), but no fancy
> >>> bios-debugging hardware.
> >>>
> >>> Regards,
> >>>
> >>> thomasg
> >>>
> >>> P.S. In case anyone else stumbles upon it: the board has 2 separate
> >>> flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W
> >>> package on the left of the board) as well as a SST25VF016B, 16 Mbit,
> >>> as the SOIC8W on the right. The first one holds the IPMI firmware,
> the
> >>> second one the AMI BIOS.
> >>> Flashing requires a testclip or some really serious soldering skills.
> >>> Attaching a SO8 socket can only be done with hot air soldering.
> >>
> >> Hi Thomas,
> >>
> >> Thanks for the report. While many people overlap with the flashrom
> >> list, please post about those patches on that list. Seems that you
> >> should be able to ack them.
> >>
> >> ?It looks like maybe the platform build doesn't support your CPU.
> >> There have been a number of recent contributions from AMD, but they
> >> don't all align with the platform contributions. So, the H8SCM should
> >> support all fam10 revD, but may have issue with Fam10 rev E. To get
> >> more information, you can turn the console debug output to SPEW in
> >> menuconfig.
> >>
> >> Marc
> >>
> >>
> >>
> >> --
> >> http://se-eng.com
> >>
> >
> > Thanks for the advice Marc,
> >
> > I already had the loglevel set to spew (8). I additionally tried the
> > other "Verbose output" debugging options, unfortunately I don't get
> > any output at all when they are built in.
> > Also, while it is hard to find and AMD doesn't have any official
> > document confirming this, according to some google hits the processor
> > should be revision D1 not rev E (AMD model number: OS4170OFU6DGOWOF ).

I also found the latest code not boot on my H8SCM-F mainboard with Rev D1 processor.
So I have made some update to using the AGESA wrapper framework,
the attachment is some of my update,
with this series of patches applied, we can boot to Debian Linux Destop or 
Windows Server 2008 R2 standard edition.
Thanks
  
> >
> > (Sry for sending the mail twice, hit the wrong button)
> >
> 
> Oh, I just recalled something about the H8SCM. There is jumper to
> disable the bmc which might have a watchdog that coreboot can't deal
> with. Did you disable that?
> 
> Marc
> 
> 
> --
> http://se-eng.com
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

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From stefan.reinauer at coreboot.org  Tue Oct 11 05:50:32 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 10 Oct 2011 20:50:32 -0700
Subject: [coreboot] make crossgcc fails with 'Building IASL 20110623 ...
 failed'
In-Reply-To: <CAOz08zEcS0yp6K5SYH7OkxQNg_whFVJZEFouYRpwKGw-Cv6yMg@mail.gmail.com>
References: <CAOz08zEcS0yp6K5SYH7OkxQNg_whFVJZEFouYRpwKGw-Cv6yMg@mail.gmail.com>
Message-ID: <4E93BD08.2040005@coreboot.org>

On 10/10/11 9:02 AM, Alp Eren K?se wrote:
> As written on the subject 'make crossgcc' fails as following:
> Skipping GDB as requested by command line
> Building IASL 20110623 ... failed
> make[1]: *** [build-without-gdb] Error 1
> make: *** [crossgcc] Error 2
>
> Anyone knows why?
> and the 
> "util/crossgcc/acpica-unix-20110623/compiler/crossgcc-build.log" file 
> is at the attachment.
>
> complete output below:
>
> Welcome to the coresystems cross toolchain builder v1.04 (August 8th, 
> 2011)
>
> Will skip GDB ... ok
> Downloading tar balls ...
>  * gmp-5.0.1.tar.bz2 (downloading)
>  * mpfr-3.0.0.tar.bz2 (downloading)
>  * mpc-0.8.2.tar.gz (downloading)
>  * libelf-0.8.13.tar.gz (downloading)
>  * gcc-core-4.5.2.tar.bz2 (downloading)
>  * binutils-2.20.1.tar.bz2 (downloading)
>  * acpica-unix-20110623.tar.gz (downloading)
> Downloaded tar balls ... ok
> Unpacking and patching ...
>  * gmp-5.0.1.tar.bz2
>  * mpfr-3.0.0.tar.bz2
>    o mpfr-3.0.0_allpatches_20101216.patch
>  * mpc-0.8.2.tar.gz
>  * libelf-0.8.13.tar.gz
>  * gcc-core-4.5.2.tar.bz2
>    o gcc-4.5.2_pragma.patch
>  * binutils-2.20.1.tar.bz2
>    o binutils-2.20.1_no-bfd-doc.patch
>  * acpica-unix-20110623.tar.gz
> Unpacked and patched ... ok
> Building GMP 5.0.1 ... ok
> Building MPFR 3.0.0 ... ok
> Building MPC 0.8.2 ... ok
> Building libelf 0.8.13 ... ok
> Building binutils 2.20.1 ... ok
> Building GCC 4.5.2 ... ok
> Skipping GDB as requested by command line
> Building IASL 20110623 ... failed
> make[1]: *** [build-without-gdb] Error 1
> make: *** [crossgcc] Error 2
>
Sounds like $(CC) is not set for some reason?



From peter at stuge.se  Tue Oct 11 06:29:46 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 11 Oct 2011 06:29:46 +0200
Subject: [coreboot] make crossgcc fails with 'Building IASL 20110623	...
	failed'
In-Reply-To: <4E93BD08.2040005@coreboot.org>
References: <CAOz08zEcS0yp6K5SYH7OkxQNg_whFVJZEFouYRpwKGw-Cv6yMg@mail.gmail.com>
	<4E93BD08.2040005@coreboot.org>
Message-ID: <20111011042946.18255.qmail@stuge.se>

Stefan Reinauer wrote:
>> Building IASL 20110623 ... failed
>> make[1]: *** [build-without-gdb] Error 1
>> make: *** [crossgcc] Error 2
>
> Sounds like $(CC) is not set for some reason?

I spent some time debugging this when I first encountered it but I
don't know how simple the solution is. CC indeed ends up blank, but
I didn't see an obvious solution. iasl makes ugly.


//Peter



From gerrit at coreboot.org  Tue Oct 11 07:59:13 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 11 Oct 2011 07:59:13 +0200
Subject: [coreboot] Patch merged into coreboot/master: eb837a7 sb800: Add
	sata ahci/raid mode kconfig option
References: <I87a7814930ce3a7c38cde1e235d151223eea2107+0@gerrit.coreboot.org>
Message-ID: <E1RDVMv-0005ch-7v@ra.coresystems.de>

the following patch was just integrated into master:
commit eb837a74ad78ed6d98ba0799f7ed2ed8475b1fd5
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Oct 10 17:17:39 2011 +0800

    sb800: Add sata ahci/raid mode kconfig option
    
    If sb800 sata was configured as ahci or raid mode,
    give the option to add ROM files.
    
    Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>

See http://review.coreboot.org/225 for details.

-gerrit



From gerrit at coreboot.org  Tue Oct 11 07:59:43 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 11 Oct 2011 07:59:43 +0200
Subject: [coreboot] Patch merged into coreboot/master: 429729d persimmon:
	sb800 sata mode configure update
References: <I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca+0@gerrit.coreboot.org>
Message-ID: <E1RDVNQ-0005ma-0b@ra.coresystems.de>

the following patch was just integrated into master:
commit 429729d93d3562ccca5f2f13f407ae7a8a971212
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Oct 10 18:13:51 2011 +0800

    persimmon: sb800 sata mode configure update
    
    persimmon configure sb800 sata mode according to the
    southbridge kconfig selection.
    
    Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>

See http://review.coreboot.org/227 for details.

-gerrit



From gerrit at coreboot.org  Tue Oct 11 08:07:23 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 11 Oct 2011 08:07:23 +0200
Subject: [coreboot] Patch merged into coreboot/master: eb0e452 sb800: sata
	combine mode configure fix
References: <I32e7101737f1dbfff49daa58670e6820b476b250+0@gerrit.coreboot.org>
Message-ID: <E1RDVUp-00011s-3j@ra.coresystems.de>

the following patch was just integrated into master:
commit eb0e4526ffeb1330d9c2b9f2c69cac6a4f3a41ec
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Oct 10 18:23:49 2011 +0800

    sb800: sata combine mode configure fix
    
    Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to
    configure SataIdeCombinedMode is wrong.
    
    sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller
      0: IDE controller is exposed and Combined Mode is enabled.
         SATA controller has control over Port0 through Port3,
         IDE controller has control over Port4 and Port5
      1: IDE controller is hidden and Combined Mode is disabled,
         SATA controller has full control of all 6 Ports when operating in non-IDE mode
    
    Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>

See http://review.coreboot.org/229 for details.

-gerrit



From gerrit at coreboot.org  Tue Oct 11 08:12:01 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 11 Oct 2011 08:12:01 +0200
Subject: [coreboot] Patch merged into coreboot/master: 42acf3c mainboard:
	complete the sb800 devicetree even device is off
References: <I76ebad842e90b0f740abbec031165d7c39a80abf+0@gerrit.coreboot.org>
Message-ID: <E1RDVZJ-0002EW-2s@ra.coresystems.de>

the following patch was just integrated into master:
commit 42acf3ccf042ecf596df8d149ad66512e81a8fc8
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Oct 10 19:19:46 2011 +0800

    mainboard: complete the sb800 devicetree even device is off
    
    sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
    enable_dev() function. If the devicetree don't have this device,
    then sb_Before_Pci_Init will not get called.
    
    Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>

See http://review.coreboot.org/230 for details.

-gerrit



From marcj303 at gmail.com  Tue Oct 11 08:27:20 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 11 Oct 2011 00:27:20 -0600
Subject: [coreboot] [RFC] Tracking run tested coreboot revisions for
	boards
In-Reply-To: <1318063855.3932.36.camel@mattotaupa>
References: <1318063855.3932.36.camel@mattotaupa>
Message-ID: <CALrs_3iiejT5q9JqPrNjeiNrYrAtq+AezGHyxm3-k5WsPD4L1g@mail.gmail.com>

On Sat, Oct 8, 2011 at 2:50 AM, Paul Menzel
<paulepanter at users.sourceforge.net> wrote:
> Dear coreboot folks,
>
>
> on IRC Rudolf mentioned that the A8V SE [1] works with the latest
> revision of coreboot and he asked if there is a way to tag that in the
> repository.
>
> There are several ways to accomplish that but all seem to have down
> sides.
>
> 1. Git tags. We could use `git tag <board name> <commit>` and interested
> folks could then do `git tag | grep <board name>` to find tested
> revisions. Peter wrote, that Git tags could slow down the repository and
> that only finitely many tags can be used. Would the last point be a
> problem for us?
>
> 2. Git notes. Peter suggested also to use Git notes. But Rudolf wrote he
> finds it difficult to handle.
>
> 3. Wiki. We could use the Wiki by either adding tested revisions to the
> corresponding board pages or by creating a new page with a table. The
> first solution is not feasible because not all boards have their own
> page. Patrick wrote that using the Wiki often it gets out of date pretty
> quickly. Although in this case I think that would not be a huge problem
> considering that the noted revision actually was tested. Additionally
> not a lot of developers are comfortable using the Wiki. OpenEmbedded
> once did something like that [2].
>
> 4. Provide tested images. In addition to specifying the revision such
> tested images could be uploaded somewhere so users would not have to
> build it themselves. This would not work though, since the
> infrastructure is not in place and we have to be careful with images
> containing option roms(?).
>
> 5. ROM-o-matic.net [3]. Idwer suggested a service similar to
> ROM-o-matic.net where know revisions get build by this server and users
> can configure an image to be built. That is an interesting idea although
> it is probably the most difficult to realize. Could this be a GSoC
> project?
>
> 6. File in repository. An other suggestion by Patrick and myself is to
> put a file in for example `Documentation/working-revisions.mdtext` and
> note the tested revision and board there or to put a file in each board
> directory and note tested revisions there. The downside is that people
> would have to register with Gerrit to submit changes.
>
> If we would manage our Wiki in our repository [4] options 3 and 6 could
> be combined.
>
> 7. Messages to the list. Thinking about it the easiest solution would be
> to create something like the script `alsa-info.sh`. This script collects
> the necessary information ? in our case for example revision, boards,
> cbfs output, used build tools. Even better would be to run that script
> on the tested machine so also something like the tested distribution
> could be tested.
>
> Then a mbox or text file with an appropriate name/subject line is
> created
>
> ? ? ? ?[Tested] ASUS M2V-MX SE works with revision <commit>
>
> which gets send to the list by the user or automatically.
>
> People then can search the archive. The only downside is that a nice
> table is missing.
>
> All in all I am quite surprised that no nice solutions seem to exist
> especially since I would imagine quality assurance (QA) folks in
> companies need to maintain similar data.
>
> Please comment and add your ideas.
>
>
> Thanks,
>
> Paul
>
>
> [1] http://www.coreboot.org/Supported_Motherboards
> [2] http://www.openembedded.org/wiki/Testing
> [3] http://rom-o-matic.net/
> [4] http://www.coreboot.org/pipermail/coreboot/2011-June/065706.html
> [5] http://alsa-project.org/main/index.php/Help_To_Debug
>

Hi Paul,

Thanks for the writeup. I prefer option #3 and that this was
information kept in the wiki somehow. It is searchable by the public
at large. I would like to see us do a better job at the wiki as it is
the public face of the project and the best place for new developers
and users to get information. I like the idea of the maillist script.
I think that would be great. With that, a wiki page or other html page
could be easily generated. New users may not join the maillist but it
is searchable by the public.  Personally, I really don't like
non-source files in the source repository. It is the most difficult
place to find information and has a high bar to enter to get some
simple information.

Regards,
Marc




-- 
http://se-eng.com



From peter at stuge.se  Tue Oct 11 08:41:57 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 11 Oct 2011 08:41:57 +0200
Subject: [coreboot] Patch set updated for coreboot: 42acf3c
	mainboard:	complete the sb800 devicetree even device is off
In-Reply-To: <I76ebad842e90b0f740abbec031165d7c39a80abf+4@gerrit.coreboot.org>
References: <I76ebad842e90b0f740abbec031165d7c39a80abf+0@gerrit.coreboot.org>
	<I76ebad842e90b0f740abbec031165d7c39a80abf+4@gerrit.coreboot.org>
Message-ID: <20111011064157.4200.qmail@stuge.se>

Kerry Sheh wrote:
> commit 42acf3ccf042ecf596df8d149ad66512e81a8fc8
> Author: Kerry Sheh <shekairui at gmail.com>
> Date:   Mon Oct 10 19:19:46 2011 +0800
> 
>     mainboard: complete the sb800 devicetree even device is off
>     
>     sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
>     enable_dev() function.

Using "was" indicates that this patch changes how that works, which
is not the case. In any case, the good solution to this problem is
Patrick's idea to fix coreboot so that there is a convenient method
to run chipset specific code at strategic points during
initialization.

Please mention if you know of places in coreboot where it would be
particularly useful to make calls into chipset code.


//Peter



From gerrit at coreboot.org  Tue Oct 11 08:50:01 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 11 Oct 2011 08:50:01 +0200
Subject: [coreboot] Patch merged into coreboot/master: feb5cbb Fixed broken
	MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
References: <Ie568a52a8eb355969c86964d5afc4692e60f69c1+0@gerrit.coreboot.org>
Message-ID: <E1RDWA5-0003cg-2z@ra.coresystems.de>

the following patch was just integrated into master:
commit feb5cbb72fc0424f9aecf0db122d2344b4fb9512
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Thu Oct 6 18:21:19 2011 +0200

    Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
    
    AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB to
    mark dram memory above 4GB as WB. However, AMD K8
    rev E and earlier don't implement this bit and therefore need
    MTRR spanning dram memory above 4GB. The current implementation
    of amd_setup_mtrrs never generate MTRR above 4GB.
    This caused memory > 4GB not to be recognized in e.g. Linux on those
    rev E or older platforms. This commit should fix that bug.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1

See http://review.coreboot.org/238 for details.

-gerrit



From cristi.magherusan at gmail.com  Tue Oct 11 10:47:49 2011
From: cristi.magherusan at gmail.com (=?UTF-8?Q?Cristian_M=C4=83gheru=C8=99an=2DStanciu?=)
Date: Tue, 11 Oct 2011 10:47:49 +0200
Subject: [coreboot] [RFC] Tracking run tested coreboot revisions for
	boards
In-Reply-To: <CALrs_3iiejT5q9JqPrNjeiNrYrAtq+AezGHyxm3-k5WsPD4L1g@mail.gmail.com>
References: <1318063855.3932.36.camel@mattotaupa>
	<CALrs_3iiejT5q9JqPrNjeiNrYrAtq+AezGHyxm3-k5WsPD4L1g@mail.gmail.com>
Message-ID: <CAPOa5OnJLaHjEog1e06SHP=Pq+iMkc3aCJ6-khXhO2ArFKxTbw@mail.gmail.com>

Hi,

I also advocate a wiki but created automatically, like by a new script
from utils. I think flashrom's supported hardware wiki page is a good
example on how that could be done.

This script could open up a file in a text editor where one could
check everything that works or not for this particular build, then the
script would generate a table similar to those we have in most
motherboard wikis, also including further details such as current Git
tag, upload the current content of the config file, and so on. The
text file would be stored in the current motherboard's directory, so
it would be persistent.

Further on, the script could be enhanced to use mediawiki APIs to
upload/update the wiki page of that motherboard and maybe even to add
it to the mainboard support wiki.

What do you guys think?

Cristi


On Tue, Oct 11, 2011 at 8:27 AM, Marc Jones <marcj303 at gmail.com> wrote:
> On Sat, Oct 8, 2011 at 2:50 AM, Paul Menzel
> <paulepanter at users.sourceforge.net> wrote:
>> Dear coreboot folks,
>>
>>
>> on IRC Rudolf mentioned that the A8V SE [1] works with the latest
>> revision of coreboot and he asked if there is a way to tag that in the
>> repository.
>>
>> There are several ways to accomplish that but all seem to have down
>> sides.
>>
>> 1. Git tags. We could use `git tag <board name> <commit>` and interested
>> folks could then do `git tag | grep <board name>` to find tested
>> revisions. Peter wrote, that Git tags could slow down the repository and
>> that only finitely many tags can be used. Would the last point be a
>> problem for us?
>>
>> 2. Git notes. Peter suggested also to use Git notes. But Rudolf wrote he
>> finds it difficult to handle.
>>
>> 3. Wiki. We could use the Wiki by either adding tested revisions to the
>> corresponding board pages or by creating a new page with a table. The
>> first solution is not feasible because not all boards have their own
>> page. Patrick wrote that using the Wiki often it gets out of date pretty
>> quickly. Although in this case I think that would not be a huge problem
>> considering that the noted revision actually was tested. Additionally
>> not a lot of developers are comfortable using the Wiki. OpenEmbedded
>> once did something like that [2].
>>
>> 4. Provide tested images. In addition to specifying the revision such
>> tested images could be uploaded somewhere so users would not have to
>> build it themselves. This would not work though, since the
>> infrastructure is not in place and we have to be careful with images
>> containing option roms(?).
>>
>> 5. ROM-o-matic.net [3]. Idwer suggested a service similar to
>> ROM-o-matic.net where know revisions get build by this server and users
>> can configure an image to be built. That is an interesting idea although
>> it is probably the most difficult to realize. Could this be a GSoC
>> project?
>>
>> 6. File in repository. An other suggestion by Patrick and myself is to
>> put a file in for example `Documentation/working-revisions.mdtext` and
>> note the tested revision and board there or to put a file in each board
>> directory and note tested revisions there. The downside is that people
>> would have to register with Gerrit to submit changes.
>>
>> If we would manage our Wiki in our repository [4] options 3 and 6 could
>> be combined.
>>
>> 7. Messages to the list. Thinking about it the easiest solution would be
>> to create something like the script `alsa-info.sh`. This script collects
>> the necessary information ? in our case for example revision, boards,
>> cbfs output, used build tools. Even better would be to run that script
>> on the tested machine so also something like the tested distribution
>> could be tested.
>>
>> Then a mbox or text file with an appropriate name/subject line is
>> created
>>
>> ? ? ? ?[Tested] ASUS M2V-MX SE works with revision <commit>
>>
>> which gets send to the list by the user or automatically.
>>
>> People then can search the archive. The only downside is that a nice
>> table is missing.
>>
>> All in all I am quite surprised that no nice solutions seem to exist
>> especially since I would imagine quality assurance (QA) folks in
>> companies need to maintain similar data.
>>
>> Please comment and add your ideas.
>>
>>
>> Thanks,
>>
>> Paul
>>
>>
>> [1] http://www.coreboot.org/Supported_Motherboards
>> [2] http://www.openembedded.org/wiki/Testing
>> [3] http://rom-o-matic.net/
>> [4] http://www.coreboot.org/pipermail/coreboot/2011-June/065706.html
>> [5] http://alsa-project.org/main/index.php/Help_To_Debug
>>
>
> Hi Paul,
>
> Thanks for the writeup. I prefer option #3 and that this was
> information kept in the wiki somehow. It is searchable by the public
> at large. I would like to see us do a better job at the wiki as it is
> the public face of the project and the best place for new developers
> and users to get information. I like the idea of the maillist script.
> I think that would be great. With that, a wiki page or other html page
> could be easily generated. New users may not join the maillist but it
> is searchable by the public. ?Personally, I really don't like
> non-source files in the source repository. It is the most difficult
> place to find information and has a high bar to enter to get some
> simple information.
>
> Regards,
> Marc
>
>
>
>
> --
> http://se-eng.com
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From gerrit at coreboot.org  Tue Oct 11 11:47:07 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 11 Oct 2011 11:47:07 +0200
Subject: [coreboot] Patch merged into coreboot/master: 9a43592 Don't do a
	call as the first instruction in libpayload.
References: <Ie6f6748a471324b29ebad045c807dfc9f4b92034+0@gerrit.coreboot.org>
Message-ID: <E1RDYvT-0002mf-T4@ra.coresystems.de>

the following patch was just integrated into master:
commit 9a4359203d961e591e8f3dfe32045608117c918a
Author: Marc Jones <marcj303 at gmail.com>
Date:   Thu Oct 6 16:38:35 2011 -0600

    Don't do a call as the first instruction in libpayload.
    
    Doing a call before the payload has set up its stack is risky. The stack may
    not be in a favorable location. Normally this is not an issue with coreboot
    or other well behaved callers.
    
    Change-Id: Ie6f6748a471324b29ebad045c807dfc9f4b92034
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

See http://review.coreboot.org/240 for details.

-gerrit



From gerrit at coreboot.org  Tue Oct 11 12:00:44 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Tue, 11 Oct 2011 12:00:44 +0200
Subject: [coreboot] New patch to review for coreboot: 96e55ec SB800: Sata
	Enable bus master and enable ahci for AHCI/RAID mode
References: <I9d9c557816d364d8373fe343860ad5fe45988200+0@gerrit.coreboot.org>
Message-ID: <I9d9c557816d364d8373fe343860ad5fe45988200+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/248

-gerrit

commit 96e55eccb38c6e70a5543a4b7610fa3588168655
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 18:20:33 2011 +0800

    SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
    
    In order to make sure AHCI/RAID ROM works correctly
    For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should
    enable bus master and the ahci also should be enabled.
    
    Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/include/device/pci_ids.h          |    1 +
 src/southbridge/amd/cimx/sb800/late.c |   56 +++++++++++++++++++++++++++++++-
 2 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 390a42a..d16f85e 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -15,6 +15,7 @@
 #define PCI_CLASS_STORAGE_FLOPPY	0x0102
 #define PCI_CLASS_STORAGE_IPI		0x0103
 #define PCI_CLASS_STORAGE_RAID		0x0104
+#define PCI_CLASS_STORAGE_SATA		0x0106
 #define PCI_CLASS_STORAGE_OTHER		0x0180
 
 #define PCI_BASE_CLASS_NETWORK		0x02
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b78f1ce..7811c25 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -74,6 +74,47 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config)
 	return ret;
 }
 
+#define HOST_CAP                  0x00 /* host capabilities */
+#define HOST_CTL                  0x04 /* global host control */
+#define HOST_IRQ_STAT             0x08 /* interrupt status */
+#define HOST_PORTS_IMPL           0x0c /* bitmap of implemented ports */
+
+#define HOST_CTL_AHCI_EN          (1 << 31) /* AHCI enabled */
+void ahci_raid_init(struct device *dev)
+{
+	u8 irq = 0;
+	u32 bar5, caps, ports, val;
+
+	val = pci_read_config16(dev, PCI_CLASS_DEVICE);
+	if (val == PCI_CLASS_STORAGE_SATA) {
+		printk(BIOS_DEBUG, "AHCI controller ");
+	} else if (val == PCI_CLASS_STORAGE_RAID) {
+		printk(BIOS_DEBUG, "RAID controller ");
+	} else {
+		printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val);
+		return;
+	}
+
+	irq = pci_read_config8(dev, PCI_INTERRUPT_LINE);
+	bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+	printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq);
+
+	caps = *(volatile u32 *)(bar5 + HOST_CAP);
+	caps = (caps & 0x1F) + 1;
+	ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL);
+	printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
+
+	//dev->command = pci_read_config8(dev, PCI_COMMAND);
+	dev->command |= PCI_COMMAND_MASTER;
+	pci_write_config8(dev, PCI_COMMAND, dev->command);
+
+	/* make sure ahci is enabled */
+	val = *(volatile u32 *)(bar5 + HOST_CTL);
+	if (!(val & HOST_CTL_AHCI_EN)) {
+		*(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN;
+	}
+	printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
+}
 
 static struct pci_operations lops_pci = {
 	.set_subsystem = pci_dev_set_subsystem,
@@ -98,17 +139,28 @@ static struct device_operations sata_ops = {
 	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init = 0,
+	.init = ahci_raid_init,
 	.scan_bus = 0,
 	.ops_pci = &lops_pci,
 };
 
-static const struct pci_driver sata_driver __pci_driver = {
+static const struct pci_driver ahci_driver __pci_driver = {
 	.ops = &sata_ops,
 	.vendor = PCI_VENDOR_ID_ATI,
 	.device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
 };
 
+static const struct pci_driver raid_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID,
+};
+static const struct pci_driver raid5_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5,
+};
+
 #if CONFIG_USBDEBUG == 1
 static void usb_set_resources(struct device *dev)
 {



From gerrit at coreboot.org  Tue Oct 11 12:00:45 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Tue, 11 Oct 2011 12:00:45 +0200
Subject: [coreboot] New patch to review for coreboot: f8c69e7 SB800 RAID:
	add kconfig option RAID_MISC_ROM_POSITION
References: <I4fc64df8e091fb0cccd063826ab31a4f198942d1+0@gerrit.coreboot.org>
Message-ID: <I4fc64df8e091fb0cccd063826ab31a4f198942d1+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/249

-gerrit

commit f8c69e73c88ac79b88c204d19544e08fef3fd80f
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 18:20:35 2011 +0800

    SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
    
    SB800 RAID ROM require to put the misc ROM to specific position,
    this patch enable user to put the RAID misc ROM to the right place
    in the coreboot image.
    
    Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/southbridge/amd/cimx/sb800/Kconfig      |    9 +++++++++
 src/southbridge/amd/cimx/sb800/Makefile.inc |    1 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 17ff3f9..41a167a 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -111,6 +111,15 @@ config RAID_MISC_ROM_FILE
         default "site-local/sb800/misc.bin"
 	depends on SB800_SATA_RAID
 
+config RAID_MISC_ROM_POSITION
+	hex "RAID Misc ROM Position"
+	default 0xFFF00000
+	depends on SB800_SATA_RAID
+	help
+	  RAID ROM require to put the misc ROM at range from 0xFFF0_0000 to
+	  0xFFF0_FFFF, and must 1K bytes aligned.
+	  So CONFIG_ROM_SIZE must larger than 0x100000.
+
 endif
 
 endif #SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 30c0d39..48b198d 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -48,5 +48,6 @@ ifeq ($(CONFIG_SB800_SATA_RAID), y)
 
 	cbfs-files-y += raid/misc.bin
 	raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE))
+	raid/misc.bin-position := $(CONFIG_RAID_MISC_ROM_POSITION)
 	raid/misc.bin-type := raw
 endif



From gerrit at coreboot.org  Tue Oct 11 12:00:45 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Tue, 11 Oct 2011 12:00:45 +0200
Subject: [coreboot] Patch set updated for coreboot: 6607c70 avalue/eax-785e:
	Get SATA Mode from Kconfig option
References: <I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd+0@gerrit.coreboot.org>
Message-ID: <I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/233

-gerrit

commit 6607c70b9e63e53ba1657118b5808a7c3c76ca28
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 17:27:26 2011 +0800

    avalue/eax-785e: Get SATA Mode from Kconfig option
    
    Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/avalue/eax-785e/platform_cfg.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h
index 24dcae0..e503585 100644
--- a/src/mainboard/avalue/eax-785e/platform_cfg.h
+++ b/src/mainboard/avalue/eax-785e/platform_cfg.h
@@ -103,7 +103,7 @@
  * @breif INCHIP Sata Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
-#define SATA_MODE			NATIVE_IDE_MODE
+#define SATA_MODE			CONFIG_SB800_SATA_MODE
 
 /**
  * @breif INCHIP Sata IDE Controller Mode



From gerrit at coreboot.org  Tue Oct 11 12:00:47 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Tue, 11 Oct 2011 12:00:47 +0200
Subject: [coreboot] Patch set updated for coreboot: 2e6a214 persimmon:
	complete the sb800 devicetree
References: <If060ccb43df7fbe88bafc61e9e600a9120575437+0@gerrit.coreboot.org>
Message-ID: <If060ccb43df7fbe88bafc61e9e600a9120575437+3@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/232

-gerrit

commit 2e6a214fe93272b99f7bbb0c6786d8392653f412
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 17:27:00 2011 +0800

    persimmon: complete the sb800 devicetree
    
    sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
    enable_dev() function. If the devicetree don't have this device,
    then sb_Before_Pci_Init will not get called.
    So the missing sb800 USB3 devicees was add to the mainboard devicetree.
    Because of no physical usb connector connected to USB3, the USB3 device setting was off.
    
    Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/amd/persimmon/devicetree.cb |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index 7da2169..b47e6b9 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -87,6 +87,8 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 15.1 off end # PCIe PortB
 					device pci 15.2 off end # PCIe PortC
 					device pci 15.3 off end # PCIe PortD
+					device pci 16.0 off end # OHCI USB3
+					device pci 16.2 off end # EHCI USB3
 					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb800



From gerrit at coreboot.org  Tue Oct 11 12:00:48 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Tue, 11 Oct 2011 12:00:48 +0200
Subject: [coreboot] Patch set updated for coreboot: c098e66 sb800: Add
	Kconfig option ENABLE_IDE_COMBINED_MODE
References: <I1ab8acd27947a71baf954f44d0741f81f48e5541+0@gerrit.coreboot.org>
Message-ID: <I1ab8acd27947a71baf954f44d0741f81f48e5541+4@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/231

-gerrit

commit c098e66cd2aff9089afde58fc37226a3dff220fe
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 17:27:06 2011 +0800

    sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
    
    Add this option to enable/disable SATA IDE Combined Mode feature
    
    Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/southbridge/amd/cimx/sb800/Kconfig |   16 ++++++++++++++++
 src/southbridge/amd/cimx/sb800/cfg.c   |    2 +-
 src/southbridge/amd/cimx/sb800/late.c  |    5 -----
 3 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index b7ac0db..17ff3f9 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -28,6 +28,22 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
         string
         default "southbridge/amd/cimx/sb800/bootblock.c"
 
+config ENABLE_IDE_COMBINED_MODE
+	bool "Enable SATA IDE combined mode"
+	default n
+	help
+	  If Combined Mode is enabled. IDE controller is exposed and
+	  SATA controller has control over Port0 through Port3,
+	  IDE controller has control over Port4 and Port5.
+
+	  If Combined Mode is disabled, IDE controller is hidden and
+	  SATA controller has full control of all 6 Ports when operating in non-IDE mode.
+
+config IDE_COMBINED_MODE
+	hex
+	default "0x0" if ENABLE_IDE_COMBINED_MODE
+	default "0x1" if !ENABLE_IDE_COMBINED_MODE
+
 choice
 	prompt "SATA Mode"
 	default SB800_SATA_IDE
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index a7801a8..a34dd14 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
   	sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
 	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
 								//TODO: set to secondary not take effect.
-	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
+	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE;
 	sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
 
   	/* Azalia HDA */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index c36ee03..b78f1ce 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -343,11 +343,6 @@ static void sb800_enable(device_t dev)
 		break;
 
 	case (0x14 << 3) | 1: /* 0:14:1 IDE */
-		if (dev->enabled) {
-			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED;
-		} else {
-  			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED;
-		}
 		break;
 
 	case (0x14 << 3) | 2: /* 0:14:2 HDA */



From gerrit at coreboot.org  Tue Oct 11 12:30:35 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Tue, 11 Oct 2011 12:30:35 +0200
Subject: [coreboot] Patch set updated for coreboot: c20defe SB800: Sata
	Enable bus master and enable ahci for AHCI/RAID mode
References: <I9d9c557816d364d8373fe343860ad5fe45988200+0@gerrit.coreboot.org>
Message-ID: <I9d9c557816d364d8373fe343860ad5fe45988200+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/248

-gerrit

commit c20defe1c19d01f86ee53d013b00c352ec445eca
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 18:54:48 2011 +0800

    SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
    
    In order to make sure AHCI/RAID ROM works correctly
    For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should
    enable bus master and the ahci also should be enabled.
    
    Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/include/device/pci_ids.h          |    1 +
 src/southbridge/amd/cimx/sb800/late.c |   56 +++++++++++++++++++++++++++++++-
 2 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 390a42a..d16f85e 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -15,6 +15,7 @@
 #define PCI_CLASS_STORAGE_FLOPPY	0x0102
 #define PCI_CLASS_STORAGE_IPI		0x0103
 #define PCI_CLASS_STORAGE_RAID		0x0104
+#define PCI_CLASS_STORAGE_SATA		0x0106
 #define PCI_CLASS_STORAGE_OTHER		0x0180
 
 #define PCI_BASE_CLASS_NETWORK		0x02
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b78f1ce..6fa3dcf 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -74,6 +74,47 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config)
 	return ret;
 }
 
+#define HOST_CAP                  0x00 /* host capabilities */
+#define HOST_CTL                  0x04 /* global host control */
+#define HOST_IRQ_STAT             0x08 /* interrupt status */
+#define HOST_PORTS_IMPL           0x0c /* bitmap of implemented ports */
+
+#define HOST_CTL_AHCI_EN          (1 << 31) /* AHCI enabled */
+static void ahci_raid_init(struct device *dev)
+{
+	u8 irq = 0;
+	u32 bar5, caps, ports, val;
+
+	val = pci_read_config16(dev, PCI_CLASS_DEVICE);
+	if (val == PCI_CLASS_STORAGE_SATA) {
+		printk(BIOS_DEBUG, "AHCI controller ");
+	} else if (val == PCI_CLASS_STORAGE_RAID) {
+		printk(BIOS_DEBUG, "RAID controller ");
+	} else {
+		printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val);
+		return;
+	}
+
+	irq = pci_read_config8(dev, PCI_INTERRUPT_LINE);
+	bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+	printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq);
+
+	caps = *(volatile u32 *)(bar5 + HOST_CAP);
+	caps = (caps & 0x1F) + 1;
+	ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL);
+	printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
+
+	//dev->command = pci_read_config8(dev, PCI_COMMAND);
+	dev->command |= PCI_COMMAND_MASTER;
+	pci_write_config8(dev, PCI_COMMAND, dev->command);
+
+	/* make sure ahci is enabled */
+	val = *(volatile u32 *)(bar5 + HOST_CTL);
+	if (!(val & HOST_CTL_AHCI_EN)) {
+		*(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN;
+	}
+	printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
+}
 
 static struct pci_operations lops_pci = {
 	.set_subsystem = pci_dev_set_subsystem,
@@ -98,17 +139,28 @@ static struct device_operations sata_ops = {
 	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init = 0,
+	.init = ahci_raid_init,
 	.scan_bus = 0,
 	.ops_pci = &lops_pci,
 };
 
-static const struct pci_driver sata_driver __pci_driver = {
+static const struct pci_driver ahci_driver __pci_driver = {
 	.ops = &sata_ops,
 	.vendor = PCI_VENDOR_ID_ATI,
 	.device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
 };
 
+static const struct pci_driver raid_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID,
+};
+static const struct pci_driver raid5_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5,
+};
+
 #if CONFIG_USBDEBUG == 1
 static void usb_set_resources(struct device *dev)
 {



From gerrit at coreboot.org  Tue Oct 11 12:30:38 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Tue, 11 Oct 2011 12:30:38 +0200
Subject: [coreboot] Patch set updated for coreboot: b4b90b6 SB800 RAID: add
	kconfig option RAID_MISC_ROM_POSITION
References: <I4fc64df8e091fb0cccd063826ab31a4f198942d1+0@gerrit.coreboot.org>
Message-ID: <I4fc64df8e091fb0cccd063826ab31a4f198942d1+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/249

-gerrit

commit b4b90b6a6feece0ff9a911ca2e41653d2ba94092
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 18:54:54 2011 +0800

    SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
    
    SB800 RAID ROM require to put the misc ROM to specific position,
    this patch enable user to put the RAID misc ROM to the right place
    in the coreboot image.
    
    Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/southbridge/amd/cimx/sb800/Kconfig      |    9 +++++++++
 src/southbridge/amd/cimx/sb800/Makefile.inc |    1 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 17ff3f9..41a167a 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -111,6 +111,15 @@ config RAID_MISC_ROM_FILE
         default "site-local/sb800/misc.bin"
 	depends on SB800_SATA_RAID
 
+config RAID_MISC_ROM_POSITION
+	hex "RAID Misc ROM Position"
+	default 0xFFF00000
+	depends on SB800_SATA_RAID
+	help
+	  RAID ROM require to put the misc ROM at range from 0xFFF0_0000 to
+	  0xFFF0_FFFF, and must 1K bytes aligned.
+	  So CONFIG_ROM_SIZE must larger than 0x100000.
+
 endif
 
 endif #SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 30c0d39..48b198d 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -48,5 +48,6 @@ ifeq ($(CONFIG_SB800_SATA_RAID), y)
 
 	cbfs-files-y += raid/misc.bin
 	raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE))
+	raid/misc.bin-position := $(CONFIG_RAID_MISC_ROM_POSITION)
 	raid/misc.bin-type := raw
 endif



From alperenkose at buyutech.com.tr  Tue Oct 11 12:32:02 2011
From: alperenkose at buyutech.com.tr (=?ISO-8859-1?Q?Alp_Eren_K=F6se?=)
Date: Tue, 11 Oct 2011 13:32:02 +0300
Subject: [coreboot] make crossgcc fails with 'Building IASL 20110623 ...
	failed'
In-Reply-To: <20111011042946.18255.qmail@stuge.se>
References: <CAOz08zEcS0yp6K5SYH7OkxQNg_whFVJZEFouYRpwKGw-Cv6yMg@mail.gmail.com>
	<4E93BD08.2040005@coreboot.org>
	<20111011042946.18255.qmail@stuge.se>
Message-ID: <CAOz08zH0OivemRBUy2x+bciSyBkBv5QqWE4-8DRGPoRa=GyABg@mail.gmail.com>

The script doesn't help. What do I need to do? set the CC variable to gcc in
the environment?

2011/10/11 Peter Stuge <peter at stuge.se>

> Stefan Reinauer wrote:
> >> Building IASL 20110623 ... failed
> >> make[1]: *** [build-without-gdb] Error 1
> >> make: *** [crossgcc] Error 2
> >
> > Sounds like $(CC) is not set for some reason?
>
> I spent some time debugging this when I first encountered it but I
> don't know how simple the solution is. CC indeed ends up blank, but
> I didn't see an obvious solution. iasl makes ugly.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From Kerry.She at amd.com  Tue Oct 11 12:41:58 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Tue, 11 Oct 2011 18:41:58 +0800
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <CABgBRiJP-xh74+h5QCQkoaOU6QMj0Ajre6dxwxuJKWSuLY=HHQ@mail.gmail.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
	<CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>
	<CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
	<CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107ABF56C@sbjgexmb1.amd.com>
	<CABgBRiJP-xh74+h5QCQkoaOU6QMj0Ajre6dxwxuJKWSuLY=HHQ@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4107B6BAFD@sbjgexmb1.amd.com>

Hello, Thomas

> -----Original Message-----
> From: Thomas Gst?dtner [mailto:thomas at gstaedtner.net]
> Sent: Sunday, October 09, 2011 11:53 PM
> To: She, Kerry
> Cc: Marc Jones; coreboot
> Subject: Re: [coreboot] Issues with Supermicro H8SCM
> 
> On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She at amd.com> wrote:
> > Hello, Thomas
> >
> >> -----Original Message-----
> >> From: coreboot-bounces+kerry.she=amd.com at coreboot.org
> >> [mailto:coreboot-
> >> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Marc Jones
> >> Sent: Saturday, October 08, 2011 3:45 AM
> >> To: Thomas Gst?dtner
> >> Cc: coreboot
> >> Subject: Re: [coreboot] Issues with Supermicro H8SCM
> >>
> >> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gst?dtner
> >> <thomas at gstaedtner.net>
> >> wrote:
> >> >
> >> > Thanks for the advice Marc,
> >> >
> >> > I already had the loglevel set to spew (8). I additionally tried
> >> > the other "Verbose output" debugging options, unfortunately I don't
> >> > get any output at all when they are built in.
> >> > Also, while it is hard to find and AMD doesn't have any official
> >> > document confirming this, according to some google hits the
> >> > processor should be revision D1 not rev E (AMD model number:
> OS4170OFU6DGOWOF ).
> >
> > I also found the latest code not boot on my H8SCM-F mainboard with Rev
> D1 processor.
> > So I have made some update to using the AGESA wrapper framework, the
> > attachment is some of my update, with this series of patches applied,
> > we can boot to Debian Linux Destop or Windows Server 2008 R2 standard
> > edition.
> > Thanks
> >
> 
> Hi Kerry,
> 
> first of all: thanks for your effort!
> While I had no success at first, I now can get to the boot prompt
> (haven't tried any further yet).
> 
> Anyway, I currently have 2 DIMMs, each 4 GiB.
> A dual-channel configuration does not seem to work, the DIMMs are
> detected, but coreboot throws an "ASSERTION FAILED" error (see attached
> log cb_h8scm_01.log).
> It seems to fail because it somehow seems to think no DIMM is found
> (despite both DIMMs being detected). I tried disabling this check, but
> this only leads to a reset.
> The same problem exists with a single-DIMM configuration.
> 
> However, when I switch to a dual-DIMM, single-channel config, it at first
> does not start at all (i.e. no output on serial and no heartbeat from the
> BMC) - but when I trigger a manual reset it immediately starts up (see
> attached log cb_h8scm_dimma1a2_success.log).
> 
> I'll report back when I find out more.


I have only test with 4 Registered ECC DIMMs, so I can confirm dual DIMMs in one channel should works,
It seems that the DRAM training has some problem for single DIMM on one channel situation.
Thanks
Kerry




From thomas at gstaedtner.net  Tue Oct 11 14:17:14 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Tue, 11 Oct 2011 14:17:14 +0200
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <F53A09371FB723428826B442A4B20A4107B6BAFD@sbjgexmb1.amd.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
	<CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>
	<CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
	<CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107ABF56C@sbjgexmb1.amd.com>
	<CABgBRiJP-xh74+h5QCQkoaOU6QMj0Ajre6dxwxuJKWSuLY=HHQ@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107B6BAFD@sbjgexmb1.amd.com>
Message-ID: <CABgBRiK8kg69h_CFG+QGE2md6teB8E49JHd4XDmOWTX8ZHDN0g@mail.gmail.com>

On Tue, Oct 11, 2011 at 12:41, She, Kerry <Kerry.She at amd.com> wrote:
> Hello, Thomas
>
>> -----Original Message-----
>> From: Thomas Gst?dtner [mailto:thomas at gstaedtner.net]
>> Sent: Sunday, October 09, 2011 11:53 PM
>> To: She, Kerry
>> Cc: Marc Jones; coreboot
>> Subject: Re: [coreboot] Issues with Supermicro H8SCM
>>
>> On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She at amd.com> wrote:
>> > Hello, Thomas
>> >
>> >> -----Original Message-----
>> >> From: coreboot-bounces+kerry.she=amd.com at coreboot.org
>> >> [mailto:coreboot-
>> >> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Marc Jones
>> >> Sent: Saturday, October 08, 2011 3:45 AM
>> >> To: Thomas Gst?dtner
>> >> Cc: coreboot
>> >> Subject: Re: [coreboot] Issues with Supermicro H8SCM
>> >>
>> >> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gst?dtner
>> >> <thomas at gstaedtner.net>
>> >> wrote:
>> >> >
>> >> > Thanks for the advice Marc,
>> >> >
>> >> > I already had the loglevel set to spew (8). I additionally tried
>> >> > the other "Verbose output" debugging options, unfortunately I don't
>> >> > get any output at all when they are built in.
>> >> > Also, while it is hard to find and AMD doesn't have any official
>> >> > document confirming this, according to some google hits the
>> >> > processor should be revision D1 not rev E (AMD model number:
>> OS4170OFU6DGOWOF ).
>> >
>> > I also found the latest code not boot on my H8SCM-F mainboard with Rev
>> D1 processor.
>> > So I have made some update to using the AGESA wrapper framework, the
>> > attachment is some of my update, with this series of patches applied,
>> > we can boot to Debian Linux Destop or Windows Server 2008 R2 standard
>> > edition.
>> > Thanks
>> >
>>
>> Hi Kerry,
>>
>> first of all: thanks for your effort!
>> While I had no success at first, I now can get to the boot prompt
>> (haven't tried any further yet).
>>
>> Anyway, I currently have 2 DIMMs, each 4 GiB.
>> A dual-channel configuration does not seem to work, the DIMMs are
>> detected, but coreboot throws an "ASSERTION FAILED" error (see attached
>> log cb_h8scm_01.log).
>> It seems to fail because it somehow seems to think no DIMM is found
>> (despite both DIMMs being detected). I tried disabling this check, but
>> this only leads to a reset.
>> The same problem exists with a single-DIMM configuration.
>>
>> However, when I switch to a dual-DIMM, single-channel config, it at first
>> does not start at all (i.e. no output on serial and no heartbeat from the
>> BMC) - but when I trigger a manual reset it immediately starts up (see
>> attached log cb_h8scm_dimma1a2_success.log).
>>
>> I'll report back when I find out more.
>
>
> I have only test with 4 Registered ECC DIMMs, so I can confirm dual DIMMs in one channel should works,
> It seems that the DRAM training has some problem for single DIMM on one channel situation.
> Thanks
> Kerry
>

I unfortunately only have 2 registered DIMMs, so I can't test a dual
channel configuration, but yes, seems 1 DIMM per Channel does not work
at all.

Anyway, I built a rom with vga bios included and can boot to FILO
prompt or SeaBIOS. So far USB is not working, neither the attached USB
keybord, nor the USB flashdrive I wanted to boot from.
A related warning seems to be: "WARNING - Timeout at
ehci_wait_qh:319!", might try to disable ehci to see if ohci works.

Also, it seems it now starts up most of the time immediately,
approximately 1 out of 5 times it needs a manual reset after powering
up.
Time from power-on to FILO prompt is about 2 seconds with loglevel 3
(over serial, via VGA I can't tell, it's ready long before the display
makes it from wake-up to active).

So in short,
What Works: All 6 CPU cores are detected, clock is correct, VGA,
Serial, SeaBIOS and FILO
What Doesn't: USB/EHCI, Single-DIMM per Channel, reliable bootup



From thomas at gstaedtner.net  Tue Oct 11 16:28:47 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Tue, 11 Oct 2011 16:28:47 +0200
Subject: [coreboot] FILO fails to build via coreboot
Message-ID: <CABgBRiLmEbHESSJyxc-037KZrALOHmLuj-wdrQoBZGi8uQGXtQ@mail.gmail.com>

Hi everyone,

FILO (0.6 and SVN tested) fails to build as a coreboot payload with
the following error:

    MAKE       FILO HEAD
Found Libpayload
/home/thomasg/sources/coreboot/payloads/external/FILO/filo/build/libpayload/lib/libpayload.a.
  CC      build/i386/context.o
  CC      build/i386/segment.o
  CC      build/i386/timer.o
  CC      build/i386/sys_info.o
  CC      build/i386/linux_load.o
  CC      build/main/filo.o
  CC      build/main/strtox.o
  CC      build/main/elfload.o
  CC      build/main/ipchecksum.o
  CC      build/main/grub/grub.o
  CC      build/main/grub/builtins.o
/home/thomasg/sources/coreboot/payloads/external/FILO/filo/main/grub/builtins.c:456:2:
warning: #warning "FIND not implemented yet."
  CC      build/main/grub/cmdline.o
  CC      build/main/grub/char_io.o
  CC      build/main/grub/completions.o
  CC      build/main/grub/md5.o
  CC      build/fs/blockdev.o
  CC      build/fs/vfs.o
  CC      build/fs/eltorito.o
  CC      build/fs/fsys_ext2fs.o
  CC      build/fs/fsys_fat.o
  CC      build/fs/fsys_reiserfs.o
  CC      build/fs/fsys_iso9660.o
  CC      build/fs/fsys_cbfs.o
  CC      build/fs/cbfs.o
/home/thomasg/sources/coreboot/payloads/external/FILO/filo/fs/cbfs.c:113:20:
error: conflicting types for ?cbfs_find_file?
/home/thomasg/sources/coreboot/payloads/external/FILO/filo/build/libpayload/include/cbfs_core.h:175:7:
note: previous declaration of ?cbfs_find_file? was here
make[2]: *** [/home/thomasg/sources/coreboot/payloads/external/FILO/filo/build/fs/cbfs.o]
Error 1
make[1]: *** [filo] Error 2
make: *** [filo] Error 2


The reason is, that cbfs_find_file is defined in coreboot as "void
*cbfs_find_file(const char *name, int type)"
while FILO defines it as "struct cbfs_stage *cbfs_find_file(const char
*name, int type)".
As far as I can tell it works either way as the void is cast to the
right type where used, but I assume it got changed somewhere for a
reason, I just don't know which way it should be.

I could provide a patch, but I suggest that someone who actually knows
the code take a look.

If you need any more information, let me know.

thomasg



From enok at lysator.liu.se  Tue Oct 11 22:13:38 2011
From: enok at lysator.liu.se (Oskar Enoksson)
Date: Tue, 11 Oct 2011 22:13:38 +0200
Subject: [coreboot] missing read resources
Message-ID: <4E94A372.3010806@lysator.liu.se>

I get the following warnings:

APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC: 02 missing read_resources
APIC: 03 missing read_resources
I2C: 01:08 missing read_resources
I2C: 04:50 missing read_resources
I2C: 04:51 missing read_resources
I2C: 04:52 missing read_resources
I2C: 04:53 missing read_resources
I2C: 05:50 missing read_resources
I2C: 05:51 missing read_resources
I2C: 05:52 missing read_resources
I2C: 05:53 missing read_resources
I2C: 03:69 missing read_resources

What does it mean? Should I do something about it in devicetree.cb?




From marcj303 at gmail.com  Wed Oct 12 02:46:40 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 11 Oct 2011 18:46:40 -0600
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <CABgBRiK8kg69h_CFG+QGE2md6teB8E49JHd4XDmOWTX8ZHDN0g@mail.gmail.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
	<CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>
	<CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
	<CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107ABF56C@sbjgexmb1.amd.com>
	<CABgBRiJP-xh74+h5QCQkoaOU6QMj0Ajre6dxwxuJKWSuLY=HHQ@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107B6BAFD@sbjgexmb1.amd.com>
	<CABgBRiK8kg69h_CFG+QGE2md6teB8E49JHd4XDmOWTX8ZHDN0g@mail.gmail.com>
Message-ID: <CALrs_3iyVwqG09oTCCG+x3UhixJE+XwiY-FTQcrrEEeEzgcRNQ@mail.gmail.com>

On Tue, Oct 11, 2011 at 6:17 AM, Thomas Gst?dtner <thomas at gstaedtner.net> wrote:
> On Tue, Oct 11, 2011 at 12:41, She, Kerry <Kerry.She at amd.com> wrote:
>> Hello, Thomas
>>
>>> -----Original Message-----
>>> From: Thomas Gst?dtner [mailto:thomas at gstaedtner.net]
>>> Sent: Sunday, October 09, 2011 11:53 PM
>>> To: She, Kerry
>>> Cc: Marc Jones; coreboot
>>> Subject: Re: [coreboot] Issues with Supermicro H8SCM
>>>
>>> On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She at amd.com> wrote:
>>> > Hello, Thomas
>>> >
>>> >> -----Original Message-----
>>> >> From: coreboot-bounces+kerry.she=amd.com at coreboot.org
>>> >> [mailto:coreboot-
>>> >> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Marc Jones
>>> >> Sent: Saturday, October 08, 2011 3:45 AM
>>> >> To: Thomas Gst?dtner
>>> >> Cc: coreboot
>>> >> Subject: Re: [coreboot] Issues with Supermicro H8SCM
>>> >>
>>> >> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gst?dtner
>>> >> <thomas at gstaedtner.net>
>>> >> wrote:
>>> >> >
>>> >> > Thanks for the advice Marc,
>>> >> >
>>> >> > I already had the loglevel set to spew (8). I additionally tried
>>> >> > the other "Verbose output" debugging options, unfortunately I don't
>>> >> > get any output at all when they are built in.
>>> >> > Also, while it is hard to find and AMD doesn't have any official
>>> >> > document confirming this, according to some google hits the
>>> >> > processor should be revision D1 not rev E (AMD model number:
>>> OS4170OFU6DGOWOF ).
>>> >
>>> > I also found the latest code not boot on my H8SCM-F mainboard with Rev
>>> D1 processor.
>>> > So I have made some update to using the AGESA wrapper framework, the
>>> > attachment is some of my update, with this series of patches applied,
>>> > we can boot to Debian Linux Destop or Windows Server 2008 R2 standard
>>> > edition.
>>> > Thanks
>>> >
>>>
>>> Hi Kerry,
>>>
>>> first of all: thanks for your effort!
>>> While I had no success at first, I now can get to the boot prompt
>>> (haven't tried any further yet).
>>>
>>> Anyway, I currently have 2 DIMMs, each 4 GiB.
>>> A dual-channel configuration does not seem to work, the DIMMs are
>>> detected, but coreboot throws an "ASSERTION FAILED" error (see attached
>>> log cb_h8scm_01.log).
>>> It seems to fail because it somehow seems to think no DIMM is found
>>> (despite both DIMMs being detected). I tried disabling this check, but
>>> this only leads to a reset.
>>> The same problem exists with a single-DIMM configuration.
>>>
>>> However, when I switch to a dual-DIMM, single-channel config, it at first
>>> does not start at all (i.e. no output on serial and no heartbeat from the
>>> BMC) - but when I trigger a manual reset it immediately starts up (see
>>> attached log cb_h8scm_dimma1a2_success.log).
>>>
>>> I'll report back when I find out more.
>>
>>
>> I have only test with 4 Registered ECC DIMMs, so I can confirm dual DIMMs in one channel should works,
>> It seems that the DRAM training has some problem for single DIMM on one channel situation.
>> Thanks
>> Kerry
>>
>
> I unfortunately only have 2 registered DIMMs, so I can't test a dual
> channel configuration, but yes, seems 1 DIMM per Channel does not work
> at all.
>
> Anyway, I built a rom with vga bios included and can boot to FILO
> prompt or SeaBIOS. So far USB is not working, neither the attached USB
> keybord, nor the USB flashdrive I wanted to boot from.
> A related warning seems to be: "WARNING - Timeout at
> ehci_wait_qh:319!", might try to disable ehci to see if ohci works.
>
> Also, it seems it now starts up most of the time immediately,
> approximately 1 out of 5 times it needs a manual reset after powering
> up.
> Time from power-on to FILO prompt is about 2 seconds with loglevel 3
> (over serial, via VGA I can't tell, it's ready long before the display
> makes it from wake-up to active).
>
> So in short,
> What Works: All 6 CPU cores are detected, clock is correct, VGA,
> Serial, SeaBIOS and FILO
> What Doesn't: USB/EHCI, Single-DIMM per Channel, reliable bootup
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

Hi Tomas

This is great feedback. Maybe you can narrow down the boot failure. Is
it in coreboot, payload, or Linux when it fails?



Kerry,

Please add this info to the wiki for this board.

Thanks,
Marc

-- 
http://se-eng.com



From gerrit at coreboot.org  Wed Oct 12 03:40:19 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 12 Oct 2011 03:40:19 +0200
Subject: [coreboot] Patch merged into coreboot/master: 2e6a214 persimmon:
	complete the sb800 devicetree
References: <If060ccb43df7fbe88bafc61e9e600a9120575437+0@gerrit.coreboot.org>
Message-ID: <E1RDnnv-0000ud-Pf@ra.coresystems.de>

the following patch was just integrated into master:
commit 2e6a214fe93272b99f7bbb0c6786d8392653f412
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 17:27:00 2011 +0800

    persimmon: complete the sb800 devicetree
    
    sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
    enable_dev() function. If the devicetree don't have this device,
    then sb_Before_Pci_Init will not get called.
    So the missing sb800 USB3 devicees was add to the mainboard devicetree.
    Because of no physical usb connector connected to USB3, the USB3 device setting was off.
    
    Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>

See http://review.coreboot.org/232 for details.

-gerrit



From gerrit at coreboot.org  Wed Oct 12 03:41:39 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 12 Oct 2011 03:41:39 +0200
Subject: [coreboot] Patch merged into coreboot/master: c098e66 sb800: Add
	Kconfig option ENABLE_IDE_COMBINED_MODE
References: <I1ab8acd27947a71baf954f44d0741f81f48e5541+0@gerrit.coreboot.org>
Message-ID: <E1RDnpD-0001CZ-MD@ra.coresystems.de>

the following patch was just integrated into master:
commit c098e66cd2aff9089afde58fc37226a3dff220fe
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 17:27:06 2011 +0800

    sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
    
    Add this option to enable/disable SATA IDE Combined Mode feature
    
    Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>

See http://review.coreboot.org/231 for details.

-gerrit



From gerrit at coreboot.org  Wed Oct 12 03:42:52 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 12 Oct 2011 03:42:52 +0200
Subject: [coreboot] Patch merged into coreboot/master: 6607c70
	avalue/eax-785e: Get SATA Mode from Kconfig option
References: <I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd+0@gerrit.coreboot.org>
Message-ID: <E1RDnqO-0001Xp-Vp@ra.coresystems.de>

the following patch was just integrated into master:
commit 6607c70b9e63e53ba1657118b5808a7c3c76ca28
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 17:27:26 2011 +0800

    avalue/eax-785e: Get SATA Mode from Kconfig option
    
    Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>

See http://review.coreboot.org/233 for details.

-gerrit



From gerrit at coreboot.org  Wed Oct 12 05:17:48 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 12 Oct 2011 05:17:48 +0200
Subject: [coreboot] Patch set updated for coreboot: a9f89fe SB800: Sata
	Enable bus master and enable ahci for AHCI/RAID mode
References: <I9d9c557816d364d8373fe343860ad5fe45988200+0@gerrit.coreboot.org>
Message-ID: <I9d9c557816d364d8373fe343860ad5fe45988200+3@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/248

-gerrit

commit a9f89fe8ff733c2aeb2c6629ede625c4374e2181
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Oct 12 11:42:59 2011 +0800

    SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
    
    In order to make sure AHCI/RAID ROM works correctly
    For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should
    enable bus master and the ahci also should be enabled.
    
    Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/include/device/pci_ids.h          |    1 +
 src/southbridge/amd/cimx/sb800/late.c |   55 +++++++++++++++++++++++++++++++-
 2 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 390a42a..d16f85e 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -15,6 +15,7 @@
 #define PCI_CLASS_STORAGE_FLOPPY	0x0102
 #define PCI_CLASS_STORAGE_IPI		0x0103
 #define PCI_CLASS_STORAGE_RAID		0x0104
+#define PCI_CLASS_STORAGE_SATA		0x0106
 #define PCI_CLASS_STORAGE_OTHER		0x0180
 
 #define PCI_BASE_CLASS_NETWORK		0x02
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b78f1ce..8c7abdb 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -74,6 +74,46 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config)
 	return ret;
 }
 
+#define HOST_CAP                  0x00 /* host capabilities */
+#define HOST_CTL                  0x04 /* global host control */
+#define HOST_IRQ_STAT             0x08 /* interrupt status */
+#define HOST_PORTS_IMPL           0x0c /* bitmap of implemented ports */
+
+#define HOST_CTL_AHCI_EN          (1 << 31) /* AHCI enabled */
+static void ahci_raid_init(struct device *dev)
+{
+	u8 irq = 0;
+	u32 bar5, caps, ports, val;
+
+	val = pci_read_config16(dev, PCI_CLASS_DEVICE);
+	if (val == PCI_CLASS_STORAGE_SATA) {
+		printk(BIOS_DEBUG, "AHCI controller ");
+	} else if (val == PCI_CLASS_STORAGE_RAID) {
+		printk(BIOS_DEBUG, "RAID controller ");
+	} else {
+		printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val);
+		return;
+	}
+
+	irq = pci_read_config8(dev, PCI_INTERRUPT_LINE);
+	bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+	printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq);
+
+	caps = *(volatile u32 *)(bar5 + HOST_CAP);
+	caps = (caps & 0x1F) + 1;
+	ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL);
+	printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
+
+	/* make sure ahci is enabled */
+	val = *(volatile u32 *)(bar5 + HOST_CTL);
+	if (!(val & HOST_CTL_AHCI_EN)) {
+		*(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN;
+	}
+
+	dev->command |= PCI_COMMAND_MASTER;
+	pci_write_config8(dev, PCI_COMMAND, dev->command);
+	printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
+}
 
 static struct pci_operations lops_pci = {
 	.set_subsystem = pci_dev_set_subsystem,
@@ -98,17 +138,28 @@ static struct device_operations sata_ops = {
 	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init = 0,
+	.init = ahci_raid_init,
 	.scan_bus = 0,
 	.ops_pci = &lops_pci,
 };
 
-static const struct pci_driver sata_driver __pci_driver = {
+static const struct pci_driver ahci_driver __pci_driver = {
 	.ops = &sata_ops,
 	.vendor = PCI_VENDOR_ID_ATI,
 	.device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
 };
 
+static const struct pci_driver raid_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID,
+};
+static const struct pci_driver raid5_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5,
+};
+
 #if CONFIG_USBDEBUG == 1
 static void usb_set_resources(struct device *dev)
 {



From gerrit at coreboot.org  Wed Oct 12 05:17:49 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 12 Oct 2011 05:17:49 +0200
Subject: [coreboot] Patch set updated for coreboot: cf271c1 SB800 RAID: add
	kconfig option RAID_MISC_ROM_POSITION
References: <I4fc64df8e091fb0cccd063826ab31a4f198942d1+0@gerrit.coreboot.org>
Message-ID: <I4fc64df8e091fb0cccd063826ab31a4f198942d1+3@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/249

-gerrit

commit cf271c1a7851527c035e3f2061abfba7ade6d475
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Oct 12 11:42:59 2011 +0800

    SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
    
    SB800 RAID ROM require to put the misc ROM to specific position,
    this patch enable user to put the RAID misc ROM to the right place
    in the coreboot image.
    
    Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/southbridge/amd/cimx/sb800/Kconfig      |    9 +++++++++
 src/southbridge/amd/cimx/sb800/Makefile.inc |    1 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 17ff3f9..79624e0 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -111,6 +111,15 @@ config RAID_MISC_ROM_FILE
         default "site-local/sb800/misc.bin"
 	depends on SB800_SATA_RAID
 
+config RAID_MISC_ROM_POSITION
+	hex "RAID Misc ROM Position"
+	default 0xFFF00000
+	depends on SB800_SATA_RAID
+	help
+	  The RAID ROM requires that the MISC ROM is located between the range
+	  0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
+	  The CONFIG_ROM_SIZE must larger than 0x100000.
+
 endif
 
 endif #SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 30c0d39..48b198d 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -48,5 +48,6 @@ ifeq ($(CONFIG_SB800_SATA_RAID), y)
 
 	cbfs-files-y += raid/misc.bin
 	raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE))
+	raid/misc.bin-position := $(CONFIG_RAID_MISC_ROM_POSITION)
 	raid/misc.bin-type := raw
 endif



From gerrit at coreboot.org  Wed Oct 12 05:48:06 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 12 Oct 2011 05:48:06 +0200
Subject: [coreboot] Patch set updated for coreboot: 84aaa51 SB800: Hide
	unused gpp ports
References: <I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0+0@gerrit.coreboot.org>
Message-ID: <I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0+4@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/207

-gerrit

commit 84aaa51051020920f5f42b7ea4c2410693cba36a
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Oct 12 12:06:23 2011 +0800

    SB800: Hide unused gpp ports
    
    Add configure option SB_GPP_UNHIDE_PORTS for mainboard
    to hide/unhide the unused sb800 gpp ports.
    Certain gpp port should be hidden, if no device was detected and
    hotplug feature is disabled for such port.
    Hidden unused ports makes lspci -vvv get more accurate information under Linux.
    Test on avalue/eax-785e mainboard.
    
    Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/advansus/a785e-i/platform_cfg.h |    6 ++++++
 src/mainboard/amd/inagua/platform_cfg.h       |    6 ++++++
 src/mainboard/amd/persimmon/platform_cfg.h    |    6 ++++++
 src/mainboard/asrock/e350m1/platform_cfg.h    |    6 ++++++
 src/southbridge/amd/cimx/sb800/cfg.c          |    2 +-
 5 files changed, 25 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h
index ee68386..5fd49d6 100644
--- a/src/mainboard/advansus/a785e-i/platform_cfg.h
+++ b/src/mainboard/advansus/a785e-i/platform_cfg.h
@@ -211,6 +211,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index 4a3f080..aa7cb5c 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -213,6 +213,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index e4fedd9..66aab8b 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -213,6 +213,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
index a0cbd11..6aa31d2 100644
--- a/src/mainboard/asrock/e350m1/platform_cfg.h
+++ b/src/mainboard/asrock/e350m1/platform_cfg.h
@@ -213,6 +213,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index a34dd14..2998fa2 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -108,7 +108,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
 	sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 	sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 	sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
-	sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
+	sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS;
 	sb_config->NbSbGen2 = NB_SB_GEN2;
 	sb_config->GppGen2 = SB_GPP_GEN2;
 



From gerrit at coreboot.org  Wed Oct 12 07:43:49 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 12 Oct 2011 07:43:49 +0200
Subject: [coreboot] Patch merged into coreboot/master: a9f89fe SB800: Sata
	Enable bus master and enable ahci for AHCI/RAID mode
References: <I9d9c557816d364d8373fe343860ad5fe45988200+0@gerrit.coreboot.org>
Message-ID: <E1RDrbZ-0001MN-F6@ra.coresystems.de>

the following patch was just integrated into master:
commit a9f89fe8ff733c2aeb2c6629ede625c4374e2181
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Oct 12 11:42:59 2011 +0800

    SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
    
    In order to make sure AHCI/RAID ROM works correctly
    For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should
    enable bus master and the ahci also should be enabled.
    
    Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>

See http://review.coreboot.org/248 for details.

-gerrit



From gerrit at coreboot.org  Wed Oct 12 07:45:11 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 12 Oct 2011 07:45:11 +0200
Subject: [coreboot] Patch merged into coreboot/master: cf271c1 SB800 RAID:
	add kconfig option RAID_MISC_ROM_POSITION
References: <I4fc64df8e091fb0cccd063826ab31a4f198942d1+0@gerrit.coreboot.org>
Message-ID: <E1RDrct-0001xY-0r@ra.coresystems.de>

the following patch was just integrated into master:
commit cf271c1a7851527c035e3f2061abfba7ade6d475
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Oct 12 11:42:59 2011 +0800

    SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
    
    SB800 RAID ROM require to put the misc ROM to specific position,
    this patch enable user to put the RAID misc ROM to the right place
    in the coreboot image.
    
    Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>

See http://review.coreboot.org/249 for details.

-gerrit



From gerrit at coreboot.org  Wed Oct 12 07:54:27 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 12 Oct 2011 07:54:27 +0200
Subject: [coreboot] Patch merged into coreboot/master: 6803e54 amdk8: ASL
	include for K8 temperature sensor support in ACPI
References: <I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339+0@gerrit.coreboot.org>
Message-ID: <E1RDrlr-00034Q-PZ@ra.coresystems.de>

the following patch was just integrated into master:
commit 6803e546d97b07d01845e3be2708e99d09591378
Author: Christoph Grenz <christophg+cb at grenz-bonn.de>
Date:   Sun Sep 18 23:20:55 2011 +0200

    amdk8: ASL include for K8 temperature sensor support in ACPI
    
    Add a ACPI Source Language snippet which if included as
    shown in the comments in the file, exposes the 4 possible
    temperature sensors in the CPU as ACPI thermal zones.
    
    Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339
    Signed-off-by: Christoph Grenz <christophg+cb at grenz-bonn.de>

See http://review.coreboot.org/222 for details.

-gerrit



From gerrit at coreboot.org  Wed Oct 12 07:56:30 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 12 Oct 2011 07:56:30 +0200
Subject: [coreboot] Patch merged into coreboot/master: 94e9f37 w83627hf: ASL
	include containing virtual device tree of the SuperIO
References: <I1108d29b341ef78fe7f1e574f98b680aada39daf+0@gerrit.coreboot.org>
Message-ID: <E1RDrnq-0007FH-Ke@ra.coresystems.de>

the following patch was just integrated into master:
commit 94e9f377664dbb9b49aa80ff47aa7ae3b7d78c34
Author: Christoph Grenz <christophg+cb at grenz-bonn.de>
Date:   Sun Sep 18 22:53:18 2011 +0200

    w83627hf: ASL include containing virtual device tree of the SuperIO
    
    Add a ACPI Source Language snippet to superio/w83627hf which maps the
    SuperIO and most of the logical devices to PnP devices, exposing
    configuration options and chip power management to the OS.
    Written using the Winbond W83627HF/F datasheet.
    
    Change-Id: I1108d29b341ef78fe7f1e574f98b680aada39daf
    Signed-off-by: Christoph Grenz <christophg+cb at grenz-bonn.de>

See http://review.coreboot.org/223 for details.

-gerrit



From gerrit at coreboot.org  Wed Oct 12 08:56:02 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 12 Oct 2011 08:56:02 +0200
Subject: [coreboot] New patch to review for coreboot: 5308dd7 Update
	coreboot cross toolchain to gcc 4.6.1
References: <I132c01293fc0cff0cfb84556a93c0b8de8e57230+0@gerrit.coreboot.org>
Message-ID: <I132c01293fc0cff0cfb84556a93c0b8de8e57230+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/250

-gerrit

commit 5308dd7bafe6981863bf817efdea8432c00c58cf
Author: Stefan Reinauer <reinauer at google.com>
Date:   Tue Oct 11 22:37:59 2011 -0700

    Update coreboot cross toolchain to gcc 4.6.1
    
    - tested on Mac OS X 10.7.1
    
    Please test on Windows and Linux
    
    Change-Id: I132c01293fc0cff0cfb84556a93c0b8de8e57230
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/crossgcc/buildgcc                             |   76 ++++--
 .../acpica-unix-20110922_unknown_warnings.patch    |   19 ++
 .../binutils-2.20_no-i386-svr4-asm-comments.patch  |   10 -
 .../patches/binutils-2.21.1_no-bfd-doc.patch       |   11 +
 .../patches/gcc-4.4.2_less-junk-in-crtbegin.patch  |   50 ----
 util/crossgcc/patches/gcc-4.5.1_pragma.patch       |   10 -
 .../patches/mpfr-2.4.2_allpatches_20100308.patch   |  266 --------------------
 7 files changed, 80 insertions(+), 362 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 6061f26..40444a5 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -20,8 +20,8 @@
 # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA
 #
 
-CROSSGCC_DATE="August 8th, 2011"
-CROSSGCC_VERSION="1.04"
+CROSSGCC_DATE="October 10th, 2011"
+CROSSGCC_VERSION="1.05"
 
 # default settings
 TARGETDIR=`pwd`/xgcc
@@ -29,17 +29,18 @@ TARGETARCH=i386-elf
 DESTDIR=
 
 # version numbers
-GMP_VERSION=5.0.1
-MPFR_VERSION=3.0.0
-MPC_VERSION=0.8.2
+GMP_VERSION=5.0.2
+MPFR_VERSION=3.1.0
+MPC_VERSION=0.9
 LIBELF_VERSION=0.8.13
-GCC_VERSION=4.5.2
-BINUTILS_VERSION=2.20.1
+GCC_VERSION=4.6.1
+GCC_AUTOCONF_VERSION=2.64
+BINUTILS_VERSION=2.21.1
 GDB_VERSION=7.3.1
 W32API_VERSION=3.17-2
 W32API_VERSION_SHORT=3.17
 MINGWRT_VERSION=3.18
-IASL_VERSION=20110623
+IASL_VERSION=20110922
 
 # archive locations
 GMP_ARCHIVE="ftp://ftp.gmplib.org/pub/gmp-${GMP_VERSION}/gmp-${GMP_VERSION}.tar.bz2"
@@ -146,7 +147,7 @@ GNU General Public License for more details.
 EOF
 }
 
-printf "${blue}Welcome to the ${red}coresystems${blue} cross toolchain builder v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n"
+printf "${blue}Welcome to the ${red}coreboot${blue} cross toolchain builder v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n"
 
 # Look if we have getopt. If not, build it.
 export PATH=$PATH:.
@@ -198,14 +199,12 @@ if [ "$TARGETARCH" = "i386-mingw32" ]; then
 	MINGW_ARCHIVES="$W32API_ARCHIVE $MINGWRT_ARCHIVE"
 fi
 
-if [ ${GCC_VERSION} = "4.5.0" -o ${GCC_VERSION} = "4.6.0" ]; then
-  # coreboot does not like the GOLD linker
-  # USE_GOLD="--enable-gold"
-  USE_GOLD=""
-  GCC_OPTIONS="--enable-lto"
-fi
+# coreboot does not like the GOLD linker
+# USE_GOLD="--enable-gold"
+USE_GOLD=""
+GCC_OPTIONS="--enable-lto"
 
-if [ ${GCC_VERSION} = "4.6.0" ]; then
+if [ ${GCC_VERSION} = "4.6.2" ]; then
   if [ ! -r tarballs/gcc-core-${GCC_VERSION}.tar.bz2 ]; then
     printf "Pre-Release GCC ${GCC_VERSION}, checking out subversion trunk\n"
     mkdir -p tarballs/.tmp
@@ -273,6 +272,7 @@ if [ "$TARGETARCH" = "i386-mingw32" ]; then
 	mv $MINGWRT_DIR/include/* $W32API_DIR/include/* $TARGETDIR/i386-mingw32/sys-include
 fi
 
+CC=cc
 if [ `uname` = "Darwin" ]; then
 	#GCC_OPTIONS="$GCC_OPTIONS --enable-threads=posix"
 
@@ -286,13 +286,14 @@ if [ `uname` = "Darwin" ]; then
 	else
 		OPTIONS="ABI=32"
 	fi
-	# old check:
-	#OPTIONS="ABI=32"
-	#touch .architecture_check.c
-	#gcc .architecture_check.c -c -o .architecture_check.o
-	#ARCH=`file .architecture_check.o |cut -f5 -d\ `
-	#test  "$ARCH" = "x86_64" && OPTIONS="ABI=64"
-	#rm .architecture_check.c .architecture_check.o
+
+	# In Xcode 4 the default compiler was switched to gcc-llvm.
+	# However, this compiler fails to compile gcc 4.6.x. As a
+	# workaround it's possible to compile gcc with gcc-4.2 or
+	# clang.
+	if $CC -v 2>&1 | grep -q LLVM; then
+		CC=clang
+	fi
 fi
 
 mkdir -p build-gmp build-mpfr build-mpc build-libelf build-binutils build-gcc
@@ -321,8 +322,10 @@ fi
 #	ln -s $DESTDIR$TARGETDIR $TARGETDIR
 #fi
 
-# Now set CFLAGS to match GMP CFLAGS.
-HOSTCFLAGS=`grep __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h |cut -d\" -f2`
+# Now set CFLAGS to match GMP CFLAGS but strip out -pedantic
+# as GCC 4.6.x fails if it's there.
+HOSTCFLAGS=`grep __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h |cut -d\" -f2 |\
+	    sed s,-pedantic,,`
 
 if [ -f build-mpfr/.success ]; then
 	printf "Skipping MPFR as it is already built\n"
@@ -393,6 +396,12 @@ if [ -f build-binutils/.success ]; then
 else
 printf "Building binutils ${BINUTILS_VERSION} ... "
 (
+	# What a pain: binutils don't come with configure
+	# script anymore. Create it:
+	cd binutils-${BINUTILS_VERSION}/
+	autoconf
+	cd ..
+	# Now build binutils
 	cd build-binutils
 	rm -f .failed
 	../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR --target=${TARGETARCH} \
@@ -411,6 +420,19 @@ if [ -f build-gcc/.success ]; then
 else
 printf "Building GCC ${GCC_VERSION} ... "
 (
+	# Even worse than binutils: GCC does not come with configure
+	# script anymore, but also enforces an obsolete autoconf version
+	# to create it. This is a poster child of how autotools help make
+	# software portable.
+	cd gcc-${GCC_VERSION}
+	sed '/dnl Ensure exactly this Autoconf version is used/d' \
+		config/override.m4 > config/override.m4.new
+	autoconf_version=`autoconf -V | grep "autoconf" | tr ' ' '\n' | tail -1`
+	sed "s/${GCC_AUTOCONF_VERSION}/${autoconf_version}/g" \
+		config/override.m4.new > config/override.m4
+	autoconf
+	cd ..
+	# Now, finally, we can build gcc:
 	cd build-gcc
 	export PATH=$PATH:$DESTDIR$TARGETDIR/bin
 	rm -f .failed
@@ -419,10 +441,12 @@ printf "Building GCC ${GCC_VERSION} ... "
 	# There's a work-around called CFLAGS_FOR_BUILD and CFLAGS_FOR_TARGET
 	# but it does not seem to work properly. At least the host library
 	# libiberty is not compiled with CFLAGS_FOR_BUILD.
-	CFLAGS_FOR_TARGET="-O2" CFLAGS="$HOSTCFLAGS" CFLAGS_FOR_BUILD="$HOSTCFLAGS" `readlink -f ../gcc-${GCC_VERSION}/configure` \
+	CC="$CC" CFLAGS_FOR_TARGET="-O2" CFLAGS="$HOSTCFLAGS" \
+		CFLAGS_FOR_BUILD="$HOSTCFLAGS" ../gcc-${GCC_VERSION}/configure \
 		--prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \
 		--target=${TARGETARCH} --disable-werror --disable-shared \
 		--disable-libssp --disable-bootstrap --disable-nls \
+		--disable-libquadmath \
 		$GCC_OPTIONS --enable-languages="c" $USE_GOLD \
 		--with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \
 		--with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \
diff --git a/util/crossgcc/patches/acpica-unix-20110922_unknown_warnings.patch b/util/crossgcc/patches/acpica-unix-20110922_unknown_warnings.patch
new file mode 100644
index 0000000..f53be92
--- /dev/null
+++ b/util/crossgcc/patches/acpica-unix-20110922_unknown_warnings.patch
@@ -0,0 +1,19 @@
+--- acpica-unix-20110922/compiler/Makefile	2011-09-22 08:59:34.000000000 -0700
++++ acpica-unix-20110922/compiler/Makefile	2011-10-11 23:47:29.000000000 -0700
+@@ -245,15 +245,11 @@
+     -Waggregate-return \
+     -Wchar-subscripts \
+     -Wempty-body \
+-    -Wlogical-op \
+     -Wmissing-declarations \
+     -Wmissing-field-initializers \
+-    -Wmissing-parameter-type \
+     -Wnested-externs \
+-    -Wold-style-declaration \
+     -Wold-style-definition \
+-    -Wredundant-decls \
+-    -Wtype-limits
++    -Wredundant-decls
+ 
+ #
+ # Bison/Flex configuration
diff --git a/util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch b/util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch
deleted file mode 100644
index 3c0cef9..0000000
--- a/util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- binutils-2.20/gas/config/tc-i386.c~	2009-01-20 14:19:04.000000000 +0100
-+++ binutils-2.20/gas/config/tc-i386.c	2009-01-20 14:20:47.000000000 +0100
-@@ -318,6 +318,7 @@
- 	 && !defined (TE_GNU)				\
- 	 && !defined (TE_LINUX)				\
-  	 && !defined (TE_NETWARE)			\
-+	 && 0						\
- 	 && !defined (TE_FreeBSD)			\
- 	 && !defined (TE_NetBSD)))
- /* This array holds the chars that always start a comment.  If the
diff --git a/util/crossgcc/patches/binutils-2.21.1_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.21.1_no-bfd-doc.patch
new file mode 100644
index 0000000..4fb9e21
--- /dev/null
+++ b/util/crossgcc/patches/binutils-2.21.1_no-bfd-doc.patch
@@ -0,0 +1,11 @@
+--- binutils-2.21.1/bfd/Makefile.in	2011-06-27 01:57:12.000000000 -0700
++++ binutils-2.21.1/bfd/Makefile.in	2011-10-11 21:59:15.000000000 -0700
+@@ -323,7 +323,7 @@
+ RELEASE = y
+ INCDIR = $(srcdir)/../include
+ CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
+-SUBDIRS = doc po
++SUBDIRS = po
+ bfddocdir = doc
+ libbfd_la_LDFLAGS = $(am__append_1) -release `cat libtool-soversion` \
+ 	@SHARED_LDFLAGS@ $(am__empty)
diff --git a/util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch b/util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch
deleted file mode 100644
index a1c2480..0000000
--- a/util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch
+++ /dev/null
@@ -1,50 +0,0 @@
---- t/gcc-4.4.2/gcc/crtstuff.c	Fr. Apr 10 01:23:07 2009
-+++ gcc-4.4.2/gcc/crtstuff.c	Di. Jul 28 16:43:28 2009
-@@ -204,6 +204,7 @@
-   = { (func_ptr) (-1) };
- #endif /* __DTOR_LIST__ alternatives */
-
-+#if 0
- #ifdef USE_EH_FRAME_REGISTRY
- /* Stick a label at the beginning of the frame unwind info so we can register
-    and deregister it with the exception handling library code.  */
-@@ -219,6 +220,7 @@
-   __attribute__ ((unused, section(JCR_SECTION_NAME), aligned(sizeof(void*))))
-   = { };
- #endif /* JCR_SECTION_NAME */
-+#endif
-
- #if defined(INIT_SECTION_ASM_OP) || defined(INIT_ARRAY_SECTION_ASM_OP)
-
-@@ -309,6 +311,7 @@
-   }
- #endif /* !defined(FINI_ARRAY_SECTION_ASM_OP) */
-
-+#if 0
- #ifdef USE_EH_FRAME_REGISTRY
- #ifdef CRT_GET_RFIB_DATA
-   /* If we used the new __register_frame_info_bases interface,
-@@ -320,6 +323,7 @@
-     __deregister_frame_info (__EH_FRAME_BEGIN__);
- #endif
- #endif
-+#endif
-
-   completed = 1;
- }
-@@ -333,6 +337,7 @@
-   = { __do_global_dtors_aux };
- #endif /* !defined(FINI_SECTION_ASM_OP) */
-
-+#if 0
- #if defined(USE_EH_FRAME_REGISTRY) || defined(JCR_SECTION_NAME)
- /* Stick a call to __register_frame_info into the .init section.  For some
-    reason calls with no arguments work more reliably in .init, so stick the
-@@ -364,6 +369,7 @@
-     }
- #endif /* JCR_SECTION_NAME */
- }
-+#endif
-
- #ifdef INIT_SECTION_ASM_OP
- CRT_CALL_STATIC_FUNCTION (INIT_SECTION_ASM_OP, frame_dummy)
diff --git a/util/crossgcc/patches/gcc-4.5.1_pragma.patch b/util/crossgcc/patches/gcc-4.5.1_pragma.patch
deleted file mode 100644
index 36ac8f4..0000000
--- a/util/crossgcc/patches/gcc-4.5.1_pragma.patch
+++ /dev/null
@@ -1,10 +0,0 @@
-diff -ur gcc-4.5.1.orig/gcc/config/i386/i386elf.h gcc-4.5.1/gcc/config/i386/i386elf.h
---- gcc-4.5.1.orig/gcc/config/i386/i386elf.h	2010-11-17 19:48:16.184401200 -0700
-+++ gcc-4.5.1/gcc/config/i386/i386elf.h	2010-11-17 20:52:54.443969900 -0700
-@@ -123,3 +123,6 @@
- #undef ASM_OUTPUT_ALIGNED_BSS
- #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-   asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-+
-+/* Enable parsing of #pragma pack(push,<n>) and #pragma pack(pop).  */
-+#define HANDLE_PRAGMA_PACK_PUSH_POP 1
diff --git a/util/crossgcc/patches/mpfr-2.4.2_allpatches_20100308.patch b/util/crossgcc/patches/mpfr-2.4.2_allpatches_20100308.patch
deleted file mode 100644
index 6603337..0000000
--- a/util/crossgcc/patches/mpfr-2.4.2_allpatches_20100308.patch
+++ /dev/null
@@ -1,266 +0,0 @@
-diff -ur mpfr-2.4.2.orig/PATCHES mpfr-2.4.2/PATCHES
---- mpfr-2.4.2.orig/PATCHES	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/PATCHES	2010-03-08 22:28:53.000000000 +0100
-@@ -0,0 +1,3 @@
-+gmp5
-+longlong.h
-+sin_cos_underflow
-diff -ur mpfr-2.4.2.orig/VERSION mpfr-2.4.2/VERSION
---- mpfr-2.4.2.orig/VERSION	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/VERSION	2010-03-08 22:28:53.000000000 +0100
-@@ -1 +1 @@
--2.4.2
-+2.4.2-p3
-diff -ur mpfr-2.4.2.orig/configure mpfr-2.4.2/configure
---- mpfr-2.4.2.orig/configure	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/configure	2010-03-08 22:28:53.000000000 +0100
-@@ -20449,6 +20449,9 @@
- main ()
- {
- 
-+#ifndef BITS_PER_MP_LIMB
-+#define BITS_PER_MP_LIMB GMP_LIMB_BITS
-+#endif
-   return BITS_PER_MP_LIMB == BYTES_PER_MP_LIMB * CHAR_BIT
-          && sizeof(mp_limb_t) == BYTES_PER_MP_LIMB ? 0 : 1;
- 
-diff -ur mpfr-2.4.2.orig/configure.in mpfr-2.4.2/configure.in
---- mpfr-2.4.2.orig/configure.in	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/configure.in	2010-03-08 22:28:53.000000000 +0100
-@@ -424,6 +424,9 @@
- #include "gmp.h"
- #include "gmp-impl.h"
- ]], [[
-+#ifndef BITS_PER_MP_LIMB
-+#define BITS_PER_MP_LIMB GMP_LIMB_BITS
-+#endif
-   return BITS_PER_MP_LIMB == BYTES_PER_MP_LIMB * CHAR_BIT
-          && sizeof(mp_limb_t) == BYTES_PER_MP_LIMB ? 0 : 1;
- ]])], [AC_MSG_RESULT(yes)], [
-diff -ur mpfr-2.4.2.orig/mpfr-impl.h mpfr-2.4.2/mpfr-impl.h
---- mpfr-2.4.2.orig/mpfr-impl.h	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/mpfr-impl.h	2010-03-08 22:28:53.000000000 +0100
-@@ -65,6 +65,12 @@
- # ifndef __GMP_IMPL_H__
- #  include "gmp-impl.h"
- # endif
-+# ifndef BITS_PER_MP_LIMB
-+#  define BITS_PER_MP_LIMB GMP_LIMB_BITS
-+# endif
-+#ifndef mpn_sqr_n
-+# define mpn_sqr_n mpn_sqr
-+#endif
- # ifdef MPFR_NEED_LONGLONG_H
- #  include "longlong.h"
- # endif
-diff -ur mpfr-2.4.2.orig/mpfr-longlong.h mpfr-2.4.2/mpfr-longlong.h
---- mpfr-2.4.2.orig/mpfr-longlong.h	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/mpfr-longlong.h	2010-03-08 22:28:53.000000000 +0100
-@@ -1011,7 +1011,15 @@
- #endif /* __m88000__ */
- 
- #if defined (__mips) && W_TYPE_SIZE == 32
--#if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
-+#if (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4)
-+#define umul_ppmm(w1, w0, u, v) \
-+  do {									\
-+    UDItype _r;							\
-+    _r = (UDItype) u * v;						\
-+    (w1) = _r >> 32;							\
-+    (w0) = (USItype) _r;						\
-+  } while (0)
-+#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7
- #define umul_ppmm(w1, w0, u, v) \
-   __asm__ ("multu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v))
- #else
-@@ -1024,7 +1032,16 @@
- #endif /* __mips */
- 
- #if (defined (__mips) && __mips >= 3) && W_TYPE_SIZE == 64
--#if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
-+#if (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4)
-+typedef unsigned int UTItype __attribute__ ((mode (TI)));
-+#define umul_ppmm(w1, w0, u, v) \
-+  do {									\
-+    UTItype _r;							\
-+    _r = (UTItype) u * v;						\
-+    (w1) = _r >> 64;							\
-+    (w0) = (UDItype) _r;						\
-+  } while (0)
-+#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7
- #define umul_ppmm(w1, w0, u, v) \
-   __asm__ ("dmultu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v))
- #else
-diff -ur mpfr-2.4.2.orig/mpfr.h mpfr-2.4.2/mpfr.h
---- mpfr-2.4.2.orig/mpfr.h	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/mpfr.h	2010-03-08 22:28:53.000000000 +0100
-@@ -27,7 +27,7 @@
- #define MPFR_VERSION_MAJOR 2
- #define MPFR_VERSION_MINOR 4
- #define MPFR_VERSION_PATCHLEVEL 2
--#define MPFR_VERSION_STRING "2.4.2"
-+#define MPFR_VERSION_STRING "2.4.2-p3"
- 
- /* Macros dealing with MPFR VERSION */
- #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c))
-diff -ur mpfr-2.4.2.orig/sin_cos.c mpfr-2.4.2/sin_cos.c
---- mpfr-2.4.2.orig/sin_cos.c	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/sin_cos.c	2010-03-08 22:28:53.000000000 +0100
-@@ -82,17 +82,19 @@
-       if (y != x)
-         /* y and x differ, thus we can safely try to compute y first */
-         {
--          MPFR_FAST_COMPUTE_IF_SMALL_INPUT (y, x, -2 * expx, 2, 0, rnd_mode,
--                                            { inexy = _inexact;
--                                              goto small_input; });
-+          MPFR_FAST_COMPUTE_IF_SMALL_INPUT (
-+            y, x, -2 * expx, 2, 0, rnd_mode,
-+            { inexy = _inexact;
-+              goto small_input; });
-           if (0)
-             {
-             small_input:
-               /* we can go here only if we can round sin(x) */
--              MPFR_FAST_COMPUTE_IF_SMALL_INPUT (z, __gmpfr_one, -2 * expx,
--                                                1, 0, rnd_mode,
--                                                { inexz = _inexact;
--                                                  goto end; });
-+              MPFR_FAST_COMPUTE_IF_SMALL_INPUT (
-+                z, __gmpfr_one, -2 * expx, 1, 0, rnd_mode,
-+                { inexz = _inexact;
-+                  MPFR_SAVE_EXPO_UPDATE_FLAGS (expo, __gmpfr_flags);
-+                  goto end; });
-             }
- 
-           /* if we go here, one of the two MPFR_FAST_COMPUTE_IF_SMALL_INPUT
-@@ -101,18 +103,19 @@
-       else /* y and x are the same variable: try to compute z first, which
-               necessarily differs */
-         {
--          MPFR_FAST_COMPUTE_IF_SMALL_INPUT (z, __gmpfr_one, -2 * expx,
--                                            1, 0, rnd_mode,
--                                            { inexz = _inexact;
--                                              goto small_input2; });
-+          MPFR_FAST_COMPUTE_IF_SMALL_INPUT (
-+            z, __gmpfr_one, -2 * expx, 1, 0, rnd_mode,
-+            { inexz = _inexact;
-+              goto small_input2; });
-           if (0)
-             {
-             small_input2:
-               /* we can go here only if we can round cos(x) */
--              MPFR_FAST_COMPUTE_IF_SMALL_INPUT (y, x, -2 * expx, 2, 0,
--                                                rnd_mode,
--                                                { inexy = _inexact;
--                                                  goto end; });
-+              MPFR_FAST_COMPUTE_IF_SMALL_INPUT (
-+                y, x, -2 * expx, 2, 0, rnd_mode,
-+                { inexy = _inexact;
-+                  MPFR_SAVE_EXPO_UPDATE_FLAGS (expo, __gmpfr_flags);
-+                  goto end; });
-             }
-         }
-       m += 2 * (-expx);
-@@ -207,7 +210,6 @@
-   mpfr_clear (xr);
- 
-  end:
--  /* FIXME: update the underflow flag if need be. */
-   MPFR_SAVE_EXPO_FREE (expo);
-   mpfr_check_range (y, inexy, rnd_mode);
-   mpfr_check_range (z, inexz, rnd_mode);
-diff -ur mpfr-2.4.2.orig/tests/tsin_cos.c mpfr-2.4.2/tests/tsin_cos.c
---- mpfr-2.4.2.orig/tests/tsin_cos.c	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/tests/tsin_cos.c	2010-03-08 22:28:53.000000000 +0100
-@@ -382,23 +382,56 @@
- consistency (void)
- {
-   mpfr_t x, s1, s2, c1, c2;
-+  mp_exp_t emin, emax;
-   mp_rnd_t rnd;
-+  unsigned int flags_sin, flags_cos, flags, flags_before, flags_ref;
-+  int inex_sin, inex_cos, inex, inex_ref;
-   int i;
- 
-+  emin = mpfr_get_emin ();
-+  emax = mpfr_get_emax ();
-+
-   for (i = 0; i <= 10000; i++)
-     {
-       mpfr_init2 (x, MPFR_PREC_MIN + (randlimb () % 8));
-       mpfr_inits2 (MPFR_PREC_MIN + (randlimb () % 8), s1, s2, c1, c2,
-                    (mpfr_ptr) 0);
--      tests_default_random (x, 256, -5, 50);
--      rnd = RND_RAND ();
--      mpfr_sin (s1, x, rnd);
--      mpfr_cos (c1, x, rnd);
--      mpfr_sin_cos (s2, c2, x, rnd);
--      if (!(mpfr_equal_p (s1, s2) && mpfr_equal_p (c1, c2)))
-+      if (i < 8 * GMP_RND_MAX)
-+        {
-+          int j = i / GMP_RND_MAX;
-+          if (j & 1)
-+            mpfr_set_emin (MPFR_EMIN_MIN);
-+          mpfr_set_si (x, (j & 2) ? 1 : -1, GMP_RNDN);
-+          mpfr_set_exp (x, mpfr_get_emin ());
-+          rnd = (mpfr_rnd_t) (i % GMP_RND_MAX);
-+          flags_before = 0;
-+          if (j & 4)
-+            mpfr_set_emax (-17);
-+        }
-+      else
-+        {
-+          tests_default_random (x, 256, -5, 50);
-+          rnd = RND_RAND ();
-+          flags_before = (randlimb () & 1) ?
-+            (unsigned int) (MPFR_FLAGS_ALL ^ MPFR_FLAGS_ERANGE) :
-+            (unsigned int) 0;
-+        }
-+      __gmpfr_flags = flags_before;
-+      inex_sin = mpfr_sin (s1, x, rnd);
-+      flags_sin = __gmpfr_flags;
-+      __gmpfr_flags = flags_before;
-+      inex_cos = mpfr_cos (c1, x, rnd);
-+      flags_cos = __gmpfr_flags;
-+      __gmpfr_flags = flags_before;
-+      inex = !!mpfr_sin_cos (s2, c2, x, rnd);
-+      flags = __gmpfr_flags;
-+      inex_ref = inex_sin || inex_cos;
-+      flags_ref = flags_sin | flags_cos;
-+      if (!(mpfr_equal_p (s1, s2) && mpfr_equal_p (c1, c2)) ||
-+          inex != inex_ref || flags != flags_ref)
-         {
--          printf ("mpfr_sin_cos and mpfr_sin/mpfr_cos disagree on %s,\nx = ",
--                  mpfr_print_rnd_mode (rnd));
-+          printf ("mpfr_sin_cos and mpfr_sin/mpfr_cos disagree on %s,"
-+                  " i = %d\nx = ", mpfr_print_rnd_mode (rnd), i);
-           mpfr_dump (x);
-           printf ("s1 = ");
-           mpfr_dump (s1);
-@@ -408,9 +441,16 @@
-           mpfr_dump (c1);
-           printf ("c2 = ");
-           mpfr_dump (c2);
-+          printf ("inex_sin = %d, inex_cos = %d, inex = %d (expected %d)\n",
-+                  inex_sin, inex_cos, inex, inex_ref);
-+          printf ("flags_sin = 0x%x, flags_cos = 0x%x, "
-+                  "flags = 0x%x (expected 0x%x)\n",
-+                  flags_sin, flags_cos, flags, flags_ref);
-           exit (1);
-         }
-       mpfr_clears (x, s1, s2, c1, c2, (mpfr_ptr) 0);
-+      mpfr_set_emin (emin);
-+      mpfr_set_emax (emax);
-     }
- }
- 
-diff -ur mpfr-2.4.2.orig/version.c mpfr-2.4.2/version.c
---- mpfr-2.4.2.orig/version.c	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/version.c	2010-03-08 22:28:53.000000000 +0100
-@@ -25,5 +25,5 @@
- const char *
- mpfr_get_version (void)
- {
--  return "2.4.2";
-+  return "2.4.2-p3";
- }



From mylesgw at gmail.com  Wed Oct 12 08:19:09 2011
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 12 Oct 2011 08:19:09 +0200
Subject: [coreboot] missing read resources
In-Reply-To: <4E94A372.3010806@lysator.liu.se>
References: <4E94A372.3010806@lysator.liu.se>
Message-ID: <CAOXdWGvommz7x-HnMhHA0M+ULaTEpTYKh32od8Bk9WBDte8RNw@mail.gmail.com>

On Tue, Oct 11, 2011 at 10:13 PM, Oskar Enoksson <enok at lysator.liu.se> wrote:
> I get the following warnings:
>
> APIC: 00 missing read_resources
> APIC: 01 missing read_resources
> APIC: 02 missing read_resources
> APIC: 03 missing read_resources
> I2C: 01:08 missing read_resources
> I2C: 04:50 missing read_resources
> I2C: 04:51 missing read_resources
> I2C: 04:52 missing read_resources
> I2C: 04:53 missing read_resources
> I2C: 05:50 missing read_resources
> I2C: 05:51 missing read_resources
> I2C: 05:52 missing read_resources
> I2C: 05:53 missing read_resources
> I2C: 03:69 missing read_resources
>
> What does it mean? Should I do something about it in devicetree.cb?

It just means that I2C and APIC devices don't have resources to read,
and the warning message was less annoying than implementing empty
functions that might get copied to a device that had resources.

It can be safely ignored for those two classes of devices.

Thanks,
Myles



From thomas at gstaedtner.net  Wed Oct 12 10:10:25 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Wed, 12 Oct 2011 10:10:25 +0200
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <CALrs_3iyVwqG09oTCCG+x3UhixJE+XwiY-FTQcrrEEeEzgcRNQ@mail.gmail.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
	<CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>
	<CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
	<CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107ABF56C@sbjgexmb1.amd.com>
	<CABgBRiJP-xh74+h5QCQkoaOU6QMj0Ajre6dxwxuJKWSuLY=HHQ@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107B6BAFD@sbjgexmb1.amd.com>
	<CABgBRiK8kg69h_CFG+QGE2md6teB8E49JHd4XDmOWTX8ZHDN0g@mail.gmail.com>
	<CALrs_3iyVwqG09oTCCG+x3UhixJE+XwiY-FTQcrrEEeEzgcRNQ@mail.gmail.com>
Message-ID: <CABgBRi+KjqDLZmqk+kbdEDgjgzQqFs4ck1Qg88dcf4yOhMS75A@mail.gmail.com>

On Wed, Oct 12, 2011 at 02:46, Marc Jones <marcj303 at gmail.com> wrote:
> On Tue, Oct 11, 2011 at 6:17 AM, Thomas Gst?dtner <thomas at gstaedtner.net> wrote:
>> On Tue, Oct 11, 2011 at 12:41, She, Kerry <Kerry.She at amd.com> wrote:
>>> Hello, Thomas
>>>
>>>> -----Original Message-----
>>>> From: Thomas Gst?dtner [mailto:thomas at gstaedtner.net]
>>>> Sent: Sunday, October 09, 2011 11:53 PM
>>>> To: She, Kerry
>>>> Cc: Marc Jones; coreboot
>>>> Subject: Re: [coreboot] Issues with Supermicro H8SCM
>>>>
>>>> On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She at amd.com> wrote:
>>>> > Hello, Thomas
>>>> >
>>>> >> -----Original Message-----
>>>> >> From: coreboot-bounces+kerry.she=amd.com at coreboot.org
>>>> >> [mailto:coreboot-
>>>> >> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Marc Jones
>>>> >> Sent: Saturday, October 08, 2011 3:45 AM
>>>> >> To: Thomas Gst?dtner
>>>> >> Cc: coreboot
>>>> >> Subject: Re: [coreboot] Issues with Supermicro H8SCM
>>>> >>
>>>> >> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gst?dtner
>>>> >> <thomas at gstaedtner.net>
>>>> >> wrote:
>>>> >> >
>>>> >> > Thanks for the advice Marc,
>>>> >> >
>>>> >> > I already had the loglevel set to spew (8). I additionally tried
>>>> >> > the other "Verbose output" debugging options, unfortunately I don't
>>>> >> > get any output at all when they are built in.
>>>> >> > Also, while it is hard to find and AMD doesn't have any official
>>>> >> > document confirming this, according to some google hits the
>>>> >> > processor should be revision D1 not rev E (AMD model number:
>>>> OS4170OFU6DGOWOF ).
>>>> >
>>>> > I also found the latest code not boot on my H8SCM-F mainboard with Rev
>>>> D1 processor.
>>>> > So I have made some update to using the AGESA wrapper framework, the
>>>> > attachment is some of my update, with this series of patches applied,
>>>> > we can boot to Debian Linux Destop or Windows Server 2008 R2 standard
>>>> > edition.
>>>> > Thanks
>>>> >
>>>>
>>>> Hi Kerry,
>>>>
>>>> first of all: thanks for your effort!
>>>> While I had no success at first, I now can get to the boot prompt
>>>> (haven't tried any further yet).
>>>>
>>>> Anyway, I currently have 2 DIMMs, each 4 GiB.
>>>> A dual-channel configuration does not seem to work, the DIMMs are
>>>> detected, but coreboot throws an "ASSERTION FAILED" error (see attached
>>>> log cb_h8scm_01.log).
>>>> It seems to fail because it somehow seems to think no DIMM is found
>>>> (despite both DIMMs being detected). I tried disabling this check, but
>>>> this only leads to a reset.
>>>> The same problem exists with a single-DIMM configuration.
>>>>
>>>> However, when I switch to a dual-DIMM, single-channel config, it at first
>>>> does not start at all (i.e. no output on serial and no heartbeat from the
>>>> BMC) - but when I trigger a manual reset it immediately starts up (see
>>>> attached log cb_h8scm_dimma1a2_success.log).
>>>>
>>>> I'll report back when I find out more.
>>>
>>>
>>> I have only test with 4 Registered ECC DIMMs, so I can confirm dual DIMMs in one channel should works,
>>> It seems that the DRAM training has some problem for single DIMM on one channel situation.
>>> Thanks
>>> Kerry
>>>
>>
>> I unfortunately only have 2 registered DIMMs, so I can't test a dual
>> channel configuration, but yes, seems 1 DIMM per Channel does not work
>> at all.
>>
>> Anyway, I built a rom with vga bios included and can boot to FILO
>> prompt or SeaBIOS. So far USB is not working, neither the attached USB
>> keybord, nor the USB flashdrive I wanted to boot from.
>> A related warning seems to be: "WARNING - Timeout at
>> ehci_wait_qh:319!", might try to disable ehci to see if ohci works.
>>
>> Also, it seems it now starts up most of the time immediately,
>> approximately 1 out of 5 times it needs a manual reset after powering
>> up.
>> Time from power-on to FILO prompt is about 2 seconds with loglevel 3
>> (over serial, via VGA I can't tell, it's ready long before the display
>> makes it from wake-up to active).
>>
>> So in short,
>> What Works: All 6 CPU cores are detected, clock is correct, VGA,
>> Serial, SeaBIOS and FILO
>> What Doesn't: USB/EHCI, Single-DIMM per Channel, reliable bootup
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>
> Hi Tomas
>
> This is great feedback. Maybe you can narrow down the boot failure. Is
> it in coreboot, payload, or Linux when it fails?
>
>
>
> Kerry,
>
> Please add this info to the wiki for this board.
>
> Thanks,
> Marc
>
> --
> http://se-eng.com
>

This is really hard to figure out so far, because I can get zero
output that would help me debug this problem.
I don't know how the hardware works exactly, but the board has a neat
watchdog in the BMC that seems to give a hint.
There's a heartbeat-LED that flashes when coreboot seems to run (when
it flashes I usually get output on serial and VGA), and when it
doesn't come up, the heartbeat-LED is off. So I _assume_ it is failing
early on, no clue how the BMC is powered on or what it looks for.
I'm pretty sure the payload is not the problem and as I have not tried
to load linux yet we can rule that out :)

I'm happy to help with the wiki btw.



From thomas at gstaedtner.net  Wed Oct 12 10:27:23 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Wed, 12 Oct 2011 10:27:23 +0200
Subject: [coreboot] [RFC] Tracking run tested coreboot revisions for
	boards
In-Reply-To: <1318063855.3932.36.camel@mattotaupa>
References: <1318063855.3932.36.camel@mattotaupa>
Message-ID: <CABgBRiKow4iP9V8P9RfW93Acqjt-wj_MDhNp0+epyRrSQLBTMw@mail.gmail.com>

On Sat, Oct 8, 2011 at 10:50, Paul Menzel
<paulepanter at users.sourceforge.net> wrote:
> Dear coreboot folks,
>
>
> on IRC Rudolf mentioned that the A8V SE [1] works with the latest
> revision of coreboot and he asked if there is a way to tag that in the
> repository.
>
> There are several ways to accomplish that but all seem to have down
> sides.
>
> 1. Git tags. We could use `git tag <board name> <commit>` and interested
> folks could then do `git tag | grep <board name>` to find tested
> revisions. Peter wrote, that Git tags could slow down the repository and
> that only finitely many tags can be used. Would the last point be a
> problem for us?
>
> 2. Git notes. Peter suggested also to use Git notes. But Rudolf wrote he
> finds it difficult to handle.
>
> 3. Wiki. We could use the Wiki by either adding tested revisions to the
> corresponding board pages or by creating a new page with a table. The
> first solution is not feasible because not all boards have their own
> page. Patrick wrote that using the Wiki often it gets out of date pretty
> quickly. Although in this case I think that would not be a huge problem
> considering that the noted revision actually was tested. Additionally
> not a lot of developers are comfortable using the Wiki. OpenEmbedded
> once did something like that [2].
>
> 4. Provide tested images. In addition to specifying the revision such
> tested images could be uploaded somewhere so users would not have to
> build it themselves. This would not work though, since the
> infrastructure is not in place and we have to be careful with images
> containing option roms(?).
>
> 5. ROM-o-matic.net [3]. Idwer suggested a service similar to
> ROM-o-matic.net where know revisions get build by this server and users
> can configure an image to be built. That is an interesting idea although
> it is probably the most difficult to realize. Could this be a GSoC
> project?
>
> 6. File in repository. An other suggestion by Patrick and myself is to
> put a file in for example `Documentation/working-revisions.mdtext` and
> note the tested revision and board there or to put a file in each board
> directory and note tested revisions there. The downside is that people
> would have to register with Gerrit to submit changes.
>
> If we would manage our Wiki in our repository [4] options 3 and 6 could
> be combined.
>
> 7. Messages to the list. Thinking about it the easiest solution would be
> to create something like the script `alsa-info.sh`. This script collects
> the necessary information ? in our case for example revision, boards,
> cbfs output, used build tools. Even better would be to run that script
> on the tested machine so also something like the tested distribution
> could be tested.
>
> Then a mbox or text file with an appropriate name/subject line is
> created
>
> ? ? ? ?[Tested] ASUS M2V-MX SE works with revision <commit>
>
> which gets send to the list by the user or automatically.
>
> People then can search the archive. The only downside is that a nice
> table is missing.
>
> All in all I am quite surprised that no nice solutions seem to exist
> especially since I would imagine quality assurance (QA) folks in
> companies need to maintain similar data.
>
> Please comment and add your ideas.
>
>
> Thanks,
>
> Paul
>
>
> [1] http://www.coreboot.org/Supported_Motherboards
> [2] http://www.openembedded.org/wiki/Testing
> [3] http://rom-o-matic.net/
> [4] http://www.coreboot.org/pipermail/coreboot/2011-June/065706.html
> [5] http://alsa-project.org/main/index.php/Help_To_Debug
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

As a "end-user" I'd really prefer a possibility to participate in this
issue; I think it is not possible for the few active devs to maintain
every mainboard all the time and make sure to note it in git. Also, I
don't think the coreboot git repo itself is the best place to keep
this information, nor is it the best tool for the job.

I think WINEs appdb (http://appdb.winehq.org) is a good example on how
it could be done. They have a overview site per application (for
coreboot this would be per board) where users can note a) with what
wine version (i.e. coreboot revision) they tested, b) how well it
works (gold, silver, ... rating e.g.) and c) what works and what not.
To not write a new web application, I'm sure something comparable can
be done in most wiki engines.

Another possibility might be using gerrit for such contributions. Many
Wiki engines have a git interface (though I think mediawiki has none)
that would allow commits, and using gerrit and a boilerplate it would
be easy for 3rd parties to send a new wiki-entry for review.
Choice 7 would also work instead.

thomasg



From Kerry.She at amd.com  Wed Oct 12 11:21:01 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Wed, 12 Oct 2011 17:21:01 +0800
Subject: [coreboot] Issues with Supermicro H8SCM
In-Reply-To: <CABgBRi+KjqDLZmqk+kbdEDgjgzQqFs4ck1Qg88dcf4yOhMS75A@mail.gmail.com>
References: <CABgBRiKUrh4kjOa7M4cPfBeARqsrmL=ht6npTjE+0-jf5Pf_ig@mail.gmail.com>
	<CALrs_3hG0SUNpG8i-KR0R-si4U4O5n0yQqpMQk+PV0LnEwRS8g@mail.gmail.com>
	<CABgBRiLTcX+63dJLtnL6248zLNej+4mhh8Kp35-KA7RFCCv2Hw@mail.gmail.com>
	<CALrs_3gnD3CtBhVbke+1Y-YCztHU0y7S14ADA8aspvuEYyeKxA@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107ABF56C@sbjgexmb1.amd.com>
	<CABgBRiJP-xh74+h5QCQkoaOU6QMj0Ajre6dxwxuJKWSuLY=HHQ@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4107B6BAFD@sbjgexmb1.amd.com>
	<CABgBRiK8kg69h_CFG+QGE2md6teB8E49JHd4XDmOWTX8ZHDN0g@mail.gmail.com>
	<CALrs_3iyVwqG09oTCCG+x3UhixJE+XwiY-FTQcrrEEeEzgcRNQ@mail.gmail.com>
	<CABgBRi+KjqDLZmqk+kbdEDgjgzQqFs4ck1Qg88dcf4yOhMS75A@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4107BCB63D@sbjgexmb1.amd.com>



> -----Original Message-----
> From: Thomas Gst?dtner [mailto:thomas at gstaedtner.net]
> Sent: Wednesday, October 12, 2011 4:10 PM
> To: Marc Jones
> Cc: She, Kerry; coreboot
> Subject: Re: [coreboot] Issues with Supermicro H8SCM
> 
> On Wed, Oct 12, 2011 at 02:46, Marc Jones <marcj303 at gmail.com> wrote:
> > On Tue, Oct 11, 2011 at 6:17 AM, Thomas Gst?dtner
> <thomas at gstaedtner.net> wrote:
> >> On Tue, Oct 11, 2011 at 12:41, She, Kerry <Kerry.She at amd.com> wrote:
> >>> Hello, Thomas
> >>>
> >>>> -----Original Message-----
> >>>> From: Thomas Gst?dtner [mailto:thomas at gstaedtner.net]
> >>>> Sent: Sunday, October 09, 2011 11:53 PM
> >>>> To: She, Kerry
> >>>> Cc: Marc Jones; coreboot
> >>>> Subject: Re: [coreboot] Issues with Supermicro H8SCM
> >>>>
> >>>> On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She at amd.com> wrote:
> >>>> > Hello, Thomas
> >>>> >
> >>>> >> -----Original Message-----
> >>>> >> From: coreboot-bounces+kerry.she=amd.com at coreboot.org
> >>>> >> [mailto:coreboot-
> >>>> >> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Marc Jones
> >>>> >> Sent: Saturday, October 08, 2011 3:45 AM
> >>>> >> To: Thomas Gst?dtner
> >>>> >> Cc: coreboot
> >>>> >> Subject: Re: [coreboot] Issues with Supermicro H8SCM
> >>>> >>
> >>>> >> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gst?dtner
> >>>> >> <thomas at gstaedtner.net>
> >>>> >> wrote:
> >>>> >> >
> >>>> >> > Thanks for the advice Marc,
> >>>> >> >
> >>>> >> > I already had the loglevel set to spew (8). I additionally
> tried
> >>>> >> > the other "Verbose output" debugging options, unfortunately I
> don't
> >>>> >> > get any output at all when they are built in.
> >>>> >> > Also, while it is hard to find and AMD doesn't have any
> official
> >>>> >> > document confirming this, according to some google hits the
> >>>> >> > processor should be revision D1 not rev E (AMD model number:
> >>>> OS4170OFU6DGOWOF ).
> >>>> >
> >>>> > I also found the latest code not boot on my H8SCM-F mainboard with
> Rev
> >>>> D1 processor.
> >>>> > So I have made some update to using the AGESA wrapper framework,
> the
> >>>> > attachment is some of my update, with this series of patches
> applied,
> >>>> > we can boot to Debian Linux Destop or Windows Server 2008 R2
> standard
> >>>> > edition.
> >>>> > Thanks
> >>>> >
> >>>>
> >>>> Hi Kerry,
> >>>>
> >>>> first of all: thanks for your effort!
> >>>> While I had no success at first, I now can get to the boot prompt
> >>>> (haven't tried any further yet).
> >>>>
> >>>> Anyway, I currently have 2 DIMMs, each 4 GiB.
> >>>> A dual-channel configuration does not seem to work, the DIMMs are
> >>>> detected, but coreboot throws an "ASSERTION FAILED" error (see
> attached
> >>>> log cb_h8scm_01.log).
> >>>> It seems to fail because it somehow seems to think no DIMM is found
> >>>> (despite both DIMMs being detected). I tried disabling this check,
> but
> >>>> this only leads to a reset.
> >>>> The same problem exists with a single-DIMM configuration.
> >>>>
> >>>> However, when I switch to a dual-DIMM, single-channel config, it at
> first
> >>>> does not start at all (i.e. no output on serial and no heartbeat
> from the
> >>>> BMC) - but when I trigger a manual reset it immediately starts up
> (see
> >>>> attached log cb_h8scm_dimma1a2_success.log).
> >>>>
> >>>> I'll report back when I find out more.
> >>>
> >>>
> >>> I have only test with 4 Registered ECC DIMMs, so I can confirm dual
> DIMMs in one channel should works,
> >>> It seems that the DRAM training has some problem for single DIMM on
> one channel situation.
> >>> Thanks
> >>> Kerry
> >>>
> >>
> >> I unfortunately only have 2 registered DIMMs, so I can't test a dual
> >> channel configuration, but yes, seems 1 DIMM per Channel does not work
> >> at all.
> >>
> >> Anyway, I built a rom with vga bios included and can boot to FILO
> >> prompt or SeaBIOS. So far USB is not working, neither the attached USB
> >> keybord, nor the USB flashdrive I wanted to boot from.
> >> A related warning seems to be: "WARNING - Timeout at
> >> ehci_wait_qh:319!", might try to disable ehci to see if ohci works.
> >>
> >> Also, it seems it now starts up most of the time immediately,
> >> approximately 1 out of 5 times it needs a manual reset after powering
> >> up.
> >> Time from power-on to FILO prompt is about 2 seconds with loglevel 3
> >> (over serial, via VGA I can't tell, it's ready long before the display
> >> makes it from wake-up to active).
> >>
> >> So in short,
> >> What Works: All 6 CPU cores are detected, clock is correct, VGA,
> >> Serial, SeaBIOS and FILO
> >> What Doesn't: USB/EHCI, Single-DIMM per Channel, reliable bootup
> >>
> >> --
> >> coreboot mailing list: coreboot at coreboot.org
> >> http://www.coreboot.org/mailman/listinfo/coreboot
> >
> > Hi Tomas
> >
> > This is great feedback. Maybe you can narrow down the boot failure. Is
> > it in coreboot, payload, or Linux when it fails?
> >
> >
> >
> > Kerry,
> >
> > Please add this info to the wiki for this board.
> >
> > Thanks,
> > Marc
> >
> > --
> > http://se-eng.com
> >
> 
> This is really hard to figure out so far, because I can get zero
> output that would help me debug this problem.
> I don't know how the hardware works exactly, but the board has a neat
> watchdog in the BMC that seems to give a hint.
> There's a heartbeat-LED that flashes when coreboot seems to run (when
> it flashes I usually get output on serial and VGA), and when it
> doesn't come up, the heartbeat-LED is off. So I _assume_ it is failing
> early on, no clue how the BMC is powered on or what it looks for.
The H8SCM Serial port connection is dependent on the BMC,
Some older BMC implementation require the system BIOS to waiting for the BMC initialization,
The serial console log printed by coreboot was dropped away during BMC initialize stage.

The mainbaord manual says after the BMC init was finished, the LED will blanking.
So you can power on the board after the BMC LED is blanking.  
Otherwise you need the BMC datasheet to figure out a solution to waiting for the BMC initialization.

> I'm pretty sure the payload is not the problem and as I have not tried
> to load linux yet we can rule that out :)
The EHCI ports works well under Linux/windows OS, 
But I get some problem with seabios payload to using the EHCI CDROM and FlashDrive.
EHCI cdrom boot sometimes, fail to boot some other time, it's quite not stable.
Thanks

> I'm happy to help with the wiki btw.


From peter at stuge.se  Wed Oct 12 13:33:59 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 12 Oct 2011 13:33:59 +0200
Subject: [coreboot] [RFC] Tracking run tested coreboot revisions
	for	boards
In-Reply-To: <CABgBRiKow4iP9V8P9RfW93Acqjt-wj_MDhNp0+epyRrSQLBTMw@mail.gmail.com>
References: <1318063855.3932.36.camel@mattotaupa>
	<CABgBRiKow4iP9V8P9RfW93Acqjt-wj_MDhNp0+epyRrSQLBTMw@mail.gmail.com>
Message-ID: <20111012113359.2268.qmail@stuge.se>

Thomas Gst?dtner wrote:
> As a "end-user" I'd really prefer a possibility to participate in this
> issue;

You would send a patch.


> I think it is not possible for the few active devs to maintain
> every mainboard all the time and make sure to note it in git.

This was never the idea. It is obvious that it will fail.


> don't think the coreboot git repo itself is the best place to keep
> this information, nor is it the best tool for the job.

Hm.


> I think WINEs appdb (http://appdb.winehq.org) is a good example on how
> it could be done. They have a overview site per application (for
> coreboot this would be per board)

The big difference is that coreboot will never really work on any
mainboard which does not also have explicit support in the repo. So
the repo seems like a natural place to track testing.


> Another possibility might be using gerrit for such contributions.

Yes of course. Test results would also go through gerrit.


//Peter



From gerrit at coreboot.org  Wed Oct 12 22:20:17 2011
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Wed, 12 Oct 2011 22:20:17 +0200
Subject: [coreboot] New patch to review for coreboot: 8125150 Make Asus
	A8V-E SE better ACPI citizen.
References: <Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3+0@gerrit.coreboot.org>
Message-ID: <Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/251

-gerrit

commit 8125150119b0bcbf4ce588dc5c731365bbd362e4
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Wed Oct 12 22:11:40 2011 +0200

    Make Asus A8V-E SE better ACPI citizen.
    
    Use the SSDT autogen infrastructure to support the automatic reserved resources,
    automatic P-state generation and automatic _CRS PCI0 method.
    
    Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/mainboard/asus/a8v-e_se/acpi_tables.c |   19 ++++++++++
 src/mainboard/asus/a8v-e_se/dsdt.asl      |   52 +++++++++++++++++++++++++----
 2 files changed, 64 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c
index fe8d475..e08b305 100644
--- a/src/mainboard/asus/a8v-e_se/acpi_tables.c
+++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c
@@ -31,6 +31,8 @@
 #include <device/pci_ids.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
 #include "southbridge/via/k8t890/k8t890.h"
+#include "northbridge/amd/amdk8/acpi.h"
+#include <cpu/amd/model_fxx_powernow.h>
 
 extern const unsigned char AmlCode[];
 
@@ -81,6 +83,14 @@ unsigned long acpi_fill_madt(unsigned long current)
 	return current;
 }
 
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	k8acpi_write_vars();
+	amd_model_fxx_generate_powernow(0, 0, 0);
+	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
+	return (unsigned long) (acpigen_get_current());
+}
+
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
@@ -91,6 +101,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_mcfg_t *mcfg;
 	acpi_fadt_t *fadt;
 	acpi_facs_t *facs;
+	acpi_header_t *ssdt;
 	acpi_header_t *dsdt;
 
 	/* Align ACPI tables to 16 byte. */
@@ -151,6 +162,14 @@ unsigned long write_acpi_tables(unsigned long start)
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
+	/* SSDT */
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+
+	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+
 	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl
index 6a46102..16ad92c 100644
--- a/src/mainboard/asus/a8v-e_se/dsdt.asl
+++ b/src/mainboard/asus/a8v-e_se/dsdt.asl
@@ -24,12 +24,7 @@
 
 DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
 {
-	/* Define the main processor.*/
-	Scope (\_PR)
-	{
-		Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
-		Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
-	}
+	 #include "northbridge/amd/amdk8/util.asl"
 
 	/* For now only define 2 power states:
 	 *  - S0 which is fully on
@@ -50,8 +45,44 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
 			Name (_UID, 0x00)
 			Name (_BBN, 0x00)
 
+		    External (BUSN)
+		    External (MMIO)
+		    External (PCIO)
+		    External (SBLK)
+		    External (TOM1)
+		    External (HCLK)
+		    External (SBDN)
+		    External (HCDN)
+
+		    Method (_CRS, 0, NotSerialized)
+			{
+			    Name (BUF0, ResourceTemplate ()
+			    {
+				IO (Decode16,
+				0x0CF8,             // Address Range Minimum
+				0x0CF8,             // Address Range Maximum
+				0x01,               // Address Alignment
+				0x08,               // Address Length
+				)
+				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000,             // Address Space Granularity
+				0x0000,             // Address Range Minimum
+				0x0CF7,             // Address Range Maximum
+				0x0000,             // Address Translation Offset
+				0x0CF8,             // Address Length
+				,, , TypeStatic)
+			    })
+				/* Methods bellow use SSDT to get actual MMIO regs
+				   The IO ports are from 0xd00, optionally an VGA,
+				   otherwise the info from MMIO is used.
+				 */
+				Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+				Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+				Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+				Return (Local3)
+			}
+
 			/* PCI Routing Table */
-			/* aaa */
 			Name (_PRT, Package () {
 				Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
 				Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
@@ -206,6 +237,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
 					}
 				}
 			}
+			/* Dummy device to hold auto generated reserved resources */
+			Device(MBRS) {
+				Name (_HID, EisaId ("PNP0C02"))
+				Name (_UID, 0x01)
+				External(_CRS) /* Resource Template in SSDT */
+			}
+
 		}
 	}
 }



From gerrit at coreboot.org  Thu Oct 13 00:48:55 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:48:55 +0200
Subject: [coreboot] New patch to review for coreboot: b130550 Fix romstage
	creation with gcc 4.6 and CAR targets
References: <I7f24c987433cc5886dde2af27498d3331cbda303+0@gerrit.coreboot.org>
Message-ID: <I7f24c987433cc5886dde2af27498d3331cbda303+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/252

-gerrit

commit b1305505c57e4a4c34cf7f11b7028bf52dc8fd2a
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 12:54:08 2011 -0700

    Fix romstage creation with gcc 4.6 and CAR targets
    
    newer gcc versions generate ".section .text" instead of just ".text"
    in their assembler output. This patch makes sure that we don't end up
    with a superfluous ".section" that makes the build fail.
    
    Add -Wno-unused-but-set-variable to CFLAGS if the flag exists.
    
    Change-Id: I7f24c987433cc5886dde2af27498d3331cbda303
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Makefile.inc |    3 ++-
 util/xcompile/xcompile    |    4 ++++
 2 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index e9c00de..65c2a92 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -247,7 +247,8 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDD
 
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
 	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $^ > $@.tmp
+	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
+		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
 	mv $@.tmp $@
 endif
 
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index fd4dbeb..b68e1b3 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -79,6 +79,10 @@ CC="${GCCPREFIX}gcc"
 testcc "$CC" "$CFLAGS-Wa,--divide " && CFLAGS="$CFLAGS-Wa,--divide "
 testcc "$CC" "$CFLAGS-fno-stack-protector " && CFLAGS="$CFLAGS-fno-stack-protector "
 testcc "$CC" "$CFLAGS-Wl,--build-id=none " && CFLAGS="$CFLAGS-Wl,--build-id=none "
+# GCC 4.6 is much more picky about unused variables. Turn off it's warnings for
+# now:
+testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \
+	       CFLAGS="$CFLAGS-Wno-unused-but-set-variable "
 
 if which gcc 2>/dev/null >/dev/null; then
 	HOSTCC=gcc



From gerrit at coreboot.org  Thu Oct 13 00:48:55 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:48:55 +0200
Subject: [coreboot] New patch to review for coreboot: 7c934a0 Update
	"STABLE" SeaBIOS selection to release 1.6.3
References: <Ie3a4d8f2624e0aa85e48ca09da53474c085838db+0@gerrit.coreboot.org>
Message-ID: <Ie3a4d8f2624e0aa85e48ca09da53474c085838db+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/253

-gerrit

commit 7c934a0665195ffb523cdc05366492e7acfb0ff0
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 14:05:49 2011 -0700

    Update "STABLE" SeaBIOS selection to release 1.6.3
    
    1.6.3 has a lot of benefits over the previous version, the two
    most important being:
     - working AHCI support
     - compiles with gcc 4.6.x
    
    Change-Id: Ie3a4d8f2624e0aa85e48ca09da53474c085838db
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 payloads/external/SeaBIOS/Makefile.inc |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc
index e04ffea..99d402c 100644
--- a/payloads/external/SeaBIOS/Makefile.inc
+++ b/payloads/external/SeaBIOS/Makefile.inc
@@ -1,7 +1,7 @@
 
 
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=1efb10b9ea30c45a8c9c6230234fefa10d2886ed
+TAG-$(CONFIG_SEABIOS_STABLE)=e66fb31eac3e6be6aaab548c229af9bb1ba55c33
 
 unexport KCONFIG_AUTOCONFIG
 
@@ -24,6 +24,7 @@ config: checkout
 	$(MAKE) -C seabios defconfig
 	echo "CONFIG_COREBOOT=y" >> seabios/.config
 	echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config
+	echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> seabios/.config
 	echo "CONFIG_COREBOOT_FLASH=y" >> seabios/.config
 	echo "CONFIG_LZMA=y" >> seabios/.config
 	echo "CONFIG_FLASH_FLOPPY=y" >> seabios/.config



From gerrit at coreboot.org  Thu Oct 13 00:48:56 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:48:56 +0200
Subject: [coreboot] New patch to review for coreboot: b49e5b5 Enable/fix
	compilation of i8254 code in ram stage.
References: <I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd+0@gerrit.coreboot.org>
Message-ID: <I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/254

-gerrit

commit b49e5b5bb66a9194728471ed7c04badf5897fb46
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Sep 27 16:26:05 2011 -0700

    Enable/fix compilation of i8254 code in ram stage.
    
    Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/include/pc80/i8254.h |    5 +++--
 src/pc80/Makefile.inc    |    1 +
 src/pc80/i8254.c         |    2 +-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h
index 82f31e6..4c5e703 100644
--- a/src/include/pc80/i8254.h
+++ b/src/include/pc80/i8254.h
@@ -20,8 +20,6 @@
 #ifndef PC80_I8254_H
 #define PC80_I8254_H
 
-void setup_i8254(void);
-
 /* Ports for the 8254 timer chip */
 #define TIMER0_PORT	0x40
 #define TIMER1_PORT	0x41
@@ -60,4 +58,7 @@ void setup_i8254(void);
 #define PPCB_SPKR       0x02    /* Bit 1 */
 #define PPCB_T2GATE     0x01    /* Bit 0 */
 
+#ifndef __ROMCC__
+void setup_i8254(void);
+#endif
 #endif
diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
index 4f126f6..2c8a80e 100644
--- a/src/pc80/Makefile.inc
+++ b/src/pc80/Makefile.inc
@@ -1,5 +1,6 @@
 ramstage-y += mc146818rtc.c
 ramstage-y += isa-dma.c
+ramstage-y += i8254.c
 ramstage-y += i8259.c
 ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c
 ramstage-y += keyboard.c
diff --git a/src/pc80/i8254.c b/src/pc80/i8254.c
index ca993f4..f75216d 100644
--- a/src/pc80/i8254.c
+++ b/src/pc80/i8254.c
@@ -35,7 +35,7 @@ void setup_i8254(void)
 	outb(0x12, TIMER1_PORT);
 }
 
-#if CONFIG_UDELAY_TIMER2
+#if defined(CONFIG_UDELAY_TIMER2) &&  CONFIG_UDELAY_TIMER2
 static void load_timer2(unsigned int ticks)
 {
         /* Set up the timer gate, turn off the speaker */



From gerrit at coreboot.org  Thu Oct 13 00:48:56 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:48:56 +0200
Subject: [coreboot] New patch to review for coreboot: 38860f7 Refactor
	option rom initialization code in coreboot.
References: <Idfff5e804ea328f7b5feebac72497c97329320ee+0@gerrit.coreboot.org>
Message-ID: <Idfff5e804ea328f7b5feebac72497c97329320ee+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/255

-gerrit

commit 38860f7f936d58ca777a55dfc3c458feccfc0137
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 14:25:07 2011 -0700

    Refactor option rom initialization code in coreboot.
    
    - move int15 handler out of the generic code into the mainboard directories
      of those mainboards that actually use it.
    - move vbe headers to vbe.h
    - move function prototypes used in native oprom code to x86.h
    
    Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/oprom/include/vbe.h            |  112 +++++++++++++++++++++
 src/devices/oprom/x86.c                    |   93 +-----------------
 src/devices/oprom/x86.h                    |   48 +++++++++
 src/devices/oprom/x86_interrupts.c         |  150 +++++++++++++++------------
 src/devices/oprom/yabel/vbe.c              |   94 +-----------------
 src/mainboard/kontron/986lcd-m/mainboard.c |   50 +++++++++-
 src/mainboard/roda/rk886ex/mainboard.c     |   49 +++++++++-
 7 files changed, 343 insertions(+), 253 deletions(-)

diff --git a/src/devices/oprom/include/vbe.h b/src/devices/oprom/include/vbe.h
new file mode 100644
index 0000000..b87b0d5
--- /dev/null
+++ b/src/devices/oprom/include/vbe.h
@@ -0,0 +1,112 @@
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * Copyright (c) 2009 Pattrick Hueper <phueper at hueper.net>
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     IBM Corporation - initial implementation
+ *****************************************************************************/
+
+// these structs are for input from and output to OF
+typedef struct {
+	u8 display_type;	// 0=NONE, 1= analog, 2=digital
+	u16 screen_width;
+	u16 screen_height;
+	u16 screen_linebytes;	// bytes per line in framebuffer, may be more than screen_width
+	u8 color_depth;	// color depth in bpp
+	u32 framebuffer_address;
+	u8 edid_block_zero[128];
+} __attribute__ ((__packed__)) screen_info_t;
+
+typedef struct {
+	u8 signature[4];
+	u16 size_reserved;
+	u8 monitor_number;
+	u16 max_screen_width;
+	u8 color_depth;
+} __attribute__ ((__packed__)) screen_info_input_t;
+
+// these structs only store a subset of the VBE defined fields
+// only those needed.
+typedef struct {
+	char signature[4];
+	u16 version;
+	u8 *oem_string_ptr;
+	u32 capabilities;
+	u16 video_mode_list[256];	// lets hope we never have more than 256 video modes...
+	u16 total_memory;
+} vbe_info_t;
+
+typedef struct {
+	u16 mode_attributes; // 00
+	u8 win_a_attributes; // 02
+	u8 win_b_attributes; // 03
+	u16 win_granularity; // 04
+	u16 win_size;        // 06
+	u16 win_a_segment;   // 08
+	u16 win_b_segment;   // 0a
+	u32 win_func_ptr;    // 0c
+	u16 bytes_per_scanline; // 10
+	u16 x_resolution;    // 12
+	u16 y_resolution;    // 14
+	u8 x_charsize;       // 16
+	u8 y_charsize;       // 17
+	u8 number_of_planes; // 18
+	u8 bits_per_pixel;   // 19
+	u8 number_of_banks;  // 20
+	u8 memory_model;     // 21
+	u8 bank_size;        // 22
+	u8 number_of_image_pages; // 23
+	u8 reserved_page;
+	u8 red_mask_size;
+	u8 red_mask_pos;
+	u8 green_mask_size;
+	u8 green_mask_pos;
+	u8 blue_mask_size;
+	u8 blue_mask_pos;
+	u8 reserved_mask_size;
+	u8 reserved_mask_pos;
+	u8 direct_color_mode_info;
+	u32 phys_base_ptr;
+	u32 offscreen_mem_offset;
+	u16 offscreen_mem_size;
+	u8 reserved[206];
+} __attribute__ ((__packed__)) vesa_mode_info_t;
+
+typedef struct {
+	u16 video_mode;
+	union {
+		vesa_mode_info_t vesa;
+		u8 mode_info_block[256];
+	};
+	// our crap
+	//u16 attributes;
+	//u16 linebytes;
+	//u16 x_resolution;
+	//u16 y_resolution;
+	//u8 x_charsize;
+	//u8 y_charsize;
+	//u8 bits_per_pixel;
+	//u8 memory_model;
+	//u32 framebuffer_address;
+} vbe_mode_info_t;
+
+typedef struct {
+	u8 port_number;	// i.e. monitor number
+	u8 edid_transfer_time;
+	u8 ddc_level;
+	u8 edid_block_zero[128];
+} vbe_ddc_info_t;
+
+struct lb_framebuffer;
+
+void vbe_set_graphics(void); // yabel only
+
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+void vbe_textmode_console(void);
+
+
diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index 37b45e6..9a6ce41 100644
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -26,18 +26,7 @@
 #include <console/console.h>
 #include <arch/interrupt.h>
 
-#define REALMODE_BASE ((void *)0x600)
-
-struct realmode_idt {
-	u16 offset, cs;
-};
-
-void x86_exception(struct eregs *info);
-
-/* From x86_asm.S */
-extern unsigned char __idt_handler, __idt_handler_size;
-extern unsigned char __realmode_code, __realmode_code_size;
-extern unsigned char __realmode_call, __realmode_interrupt;
+#include "x86.h"
 
 void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_call;
@@ -45,10 +34,6 @@ void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
 void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
 		u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt;
 
-#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB
-#define INITIAL_EBDA_SEGMENT 0xF600
-#define INITIAL_EBDA_SIZE 0x400
-
 static void setup_bda(void)
 {
 	/* clear BIOS DATA AREA */
@@ -104,79 +89,6 @@ void mainboard_interrupt_handlers(int intXX, void *intXX_func)
 	intXX_handler[intXX] = intXX_func;
 }
 
-static int int10_handler(struct eregs *regs)
-{
-	int res=-1;
-	static u8 cursor_row=0, cursor_col=0;
-	switch((regs->eax & 0xff00)>>8) {
-	case 0x01: // Set cursor shape
-		res = 0;
-		break;
-	case 0x02: // Set cursor position
-		if (cursor_row != ((regs->edx >> 8) & 0xff) ||
-		    cursor_col >= (regs->edx & 0xff)) {
-			printk(BIOS_INFO, "\n");
-		}
-		cursor_row = (regs->edx >> 8) & 0xff;
-		cursor_col = regs->edx & 0xff;
-		res = 0;
-		break;
-	case 0x03: // Get cursor position
-		regs->eax &= 0x00ff;
-		regs->ecx = 0x0607;
-		regs->edx = (cursor_row << 8) | cursor_col;
-		res = 0;
-		break;
-	case 0x06: // Scroll up
-		printk(BIOS_INFO, "\n");
-		res = 0;
-		break;
-	case 0x08: // Get Character and Mode at Cursor Position
-		regs->eax = 0x0f00 | 'A'; // White on black 'A'
-		res = 0;
-		break;
-	case 0x09: // Write Character and attribute
-	case 0x10: // Write Character
-		printk(BIOS_INFO, "%c", regs->eax & 0xff);
-		res = 0;
-		break;
-	case 0x0f: // Get video mode
-		regs->eax = 0x5002; //80x25
-		regs->ebx &= 0x00ff;
-		res = 0;
-		break;
-        default:
-		printk(BIOS_WARNING, "Unknown INT10 function %04x!\n",
-				regs->eax & 0xffff);
-		break;
-	}
-	return res;
-}
-
-static int int16_handler(struct eregs *regs)
-{
-	int res=-1;
-	switch((regs->eax & 0xff00)>>8) {
-	case 0x00: // Check for Keystroke
-		regs->eax = 0x6120; // Space Bar, Space
-		res = 0;
-		break;
-	case 0x01: // Check for Keystroke
-		regs->eflags |= 1<<6; // Zero Flag set (no key available)
-		res = 0;
-		break;
-        default:
-		printk(BIOS_WARNING, "Unknown INT16 function %04x!\n",
-				regs->eax & 0xffff);
-		break;
-	}
-	return res;
-}
-
-int int12_handler(struct eregs *regs);
-int int15_handler(struct eregs *regs);
-int int1a_handler(struct eregs *regs);
-
 static void setup_interrupt_handlers(void)
 {
 	int i;
@@ -206,9 +118,6 @@ static void setup_interrupt_handlers(void)
 			case 0x12:
 				intXX_handler[0x12] = &int12_handler;
 				break;
-			case 0x15:
-				intXX_handler[0x15] = &int15_handler;
-				break;
 			case 0x16:
 				intXX_handler[0x16] = &int16_handler;
 				break;
diff --git a/src/devices/oprom/x86.h b/src/devices/oprom/x86.h
new file mode 100644
index 0000000..0bc2412
--- /dev/null
+++ b/src/devices/oprom/x86.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#define REALMODE_BASE ((void *)0x600)
+
+struct realmode_idt {
+	u16 offset, cs;
+};
+
+void x86_exception(struct eregs *info);
+
+/* From x86_asm.S */
+extern unsigned char __idt_handler, __idt_handler_size;
+extern unsigned char __realmode_code, __realmode_code_size;
+extern unsigned char __realmode_call, __realmode_interrupt;
+
+extern void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
+		u32 esi, u32 edi) __attribute__((regparm(0)));
+
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
+		u32 esi, u32 edi) __attribute__((regparm(0)));
+
+#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB
+#define INITIAL_EBDA_SEGMENT 0xF600
+#define INITIAL_EBDA_SIZE 0x400
+
+int int10_handler(struct eregs *regs);
+int int12_handler(struct eregs *regs);
+int int16_handler(struct eregs *regs);
+int int1a_handler(struct eregs *regs);
+
diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c
index 1dd645b..86d20d7 100644
--- a/src/devices/oprom/x86_interrupts.c
+++ b/src/devices/oprom/x86_interrupts.c
@@ -26,17 +26,7 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <arch/registers.h>
-
-enum {
-	PCIBIOS_CHECK = 0xb101,
-	PCIBIOS_FINDDEV = 0xb102,
-	PCIBIOS_READCONFBYTE = 0xb108,
-	PCIBIOS_READCONFWORD = 0xb109,
-	PCIBIOS_READCONFDWORD = 0xb10a,
-	PCIBIOS_WRITECONFBYTE = 0xb10b,
-	PCIBIOS_WRITECONFWORD = 0xb10c,
-	PCIBIOS_WRITECONFDWORD = 0xb10d
-};
+#include "x86.h"
 
 // errors go in AH. Just set these up so that word assigns
 // will work. KISS.
@@ -48,9 +38,54 @@ enum {
 	PCIBIOS_BADREG = 0x8700
 };
 
-int int12_handler(struct eregs *regs);
-int int1a_handler(struct eregs *regs);
-int int15_handler(struct eregs *regs);
+int int10_handler(struct eregs *regs)
+{
+	int res=-1;
+	static u8 cursor_row=0, cursor_col=0;
+	switch((regs->eax & 0xff00)>>8) {
+	case 0x01: // Set cursor shape
+		res = 0;
+		break;
+	case 0x02: // Set cursor position
+		if (cursor_row != ((regs->edx >> 8) & 0xff) ||
+		    cursor_col >= (regs->edx & 0xff)) {
+			printk(BIOS_INFO, "\n");
+		}
+		cursor_row = (regs->edx >> 8) & 0xff;
+		cursor_col = regs->edx & 0xff;
+		res = 0;
+		break;
+	case 0x03: // Get cursor position
+		regs->eax &= 0x00ff;
+		regs->ecx = 0x0607;
+		regs->edx = (cursor_row << 8) | cursor_col;
+		res = 0;
+		break;
+	case 0x06: // Scroll up
+		printk(BIOS_INFO, "\n");
+		res = 0;
+		break;
+	case 0x08: // Get Character and Mode at Cursor Position
+		regs->eax = 0x0f00 | 'A'; // White on black 'A'
+		res = 0;
+		break;
+	case 0x09: // Write Character and attribute
+	case 0x10: // Write Character
+		printk(BIOS_INFO, "%c", regs->eax & 0xff);
+		res = 0;
+		break;
+	case 0x0f: // Get video mode
+		regs->eax = 0x5002; //80x25
+		regs->ebx &= 0x00ff;
+		res = 0;
+		break;
+        default:
+		printk(BIOS_WARNING, "Unknown INT10 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
 
 int int12_handler(struct eregs *regs)
 {
@@ -58,6 +93,26 @@ int int12_handler(struct eregs *regs)
 	return 0;
 }
 
+int int16_handler(struct eregs *regs)
+{
+	int res=-1;
+	switch((regs->eax & 0xff00)>>8) {
+	case 0x00: // Check for Keystroke
+		regs->eax = 0x6120; // Space Bar, Space
+		res = 0;
+		break;
+	case 0x01: // Check for Keystroke
+		regs->eflags |= 1<<6; // Zero Flag set (no key available)
+		res = 0;
+		break;
+        default:
+		printk(BIOS_WARNING, "Unknown INT16 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
+
 #define PCI_CONFIG_SPACE_TYPE1	(1 << 0)
 #define PCI_CONFIG_SPACE_TYPE2	(1 << 1)
 #define PCI_SPECIAL_CYCLE_TYPE1	(1 << 4)
@@ -77,7 +132,7 @@ int int1a_handler(struct eregs *regs)
 	u8 byte, reg;
 
 	switch (func) {
-	case PCIBIOS_CHECK:
+	case 0xb101: /* PCIBIOS Check */
 		regs->edx = 0x20494350;	/* ' ICP' */
 		regs->eax &= 0xffff0000; /* Clear AH / AL */
 		regs->eax |= PCI_CONFIG_SPACE_TYPE1 | PCI_SPECIAL_CYCLE_TYPE1;
@@ -87,7 +142,7 @@ int int1a_handler(struct eregs *regs)
 		regs->edi = 0x00000000;	/* protected mode entry */
 		retval = 0;
 		break;
-	case PCIBIOS_FINDDEV:
+	case 0xb102: /* Find Device */
 		devid = regs->ecx;
 		vendorid = regs->edx;
 		devindex = regs->esi;
@@ -114,12 +169,12 @@ int int1a_handler(struct eregs *regs)
 			retval = -1;
 		}
 		break;
-	case PCIBIOS_READCONFDWORD:
-	case PCIBIOS_READCONFWORD:
-	case PCIBIOS_READCONFBYTE:
-	case PCIBIOS_WRITECONFDWORD:
-	case PCIBIOS_WRITECONFWORD:
-	case PCIBIOS_WRITECONFBYTE:
+	case 0xb10a: /* Read Config Dword */
+	case 0xb109: /* Read Config Word */
+	case 0xb108: /* Read Config Byte */
+	case 0xb10d: /* Write Config Dword */
+	case 0xb10c: /* Write Config Word */
+	case 0xb10b: /* Write Config Byte */
 		devfn = regs->ebx & 0xff;
 		bus = regs->ebx >> 8;
 		reg = regs->edi;
@@ -133,27 +188,27 @@ int int1a_handler(struct eregs *regs)
 			return retval;
 		}
 		switch (func) {
-		case PCIBIOS_READCONFBYTE:
+		case 0xb108: /* Read Config Byte */
 			byte = pci_read_config8(dev, reg);
 			regs->ecx = byte;
 			break;
-		case PCIBIOS_READCONFWORD:
+		case 0xb109: /* Read Config Word */
 			word = pci_read_config16(dev, reg);
 			regs->ecx = word;
 			break;
-		case PCIBIOS_READCONFDWORD:
+		case 0xb10a: /* Read Config Dword */
 			dword = pci_read_config32(dev, reg);
 			regs->ecx = dword;
 			break;
-		case PCIBIOS_WRITECONFBYTE:
+		case 0xb10b: /* Write Config Byte */
 			byte = regs->ecx;
 			pci_write_config8(dev, reg, byte);
 			break;
-		case PCIBIOS_WRITECONFWORD:
+		case 0xb10c: /* Write Config Word */
 			word = regs->ecx;
 			pci_write_config16(dev, reg, word);
 			break;
-		case PCIBIOS_WRITECONFDWORD:
+		case 0xb10d: /* Write Config Dword */
 			dword = regs->ecx;
 			pci_write_config32(dev, reg, dword);
 			break;
@@ -178,42 +233,3 @@ int int1a_handler(struct eregs *regs)
 	return retval;
 }
 
-int int15_handler(struct eregs *regs)
-{
-	int res = -1;
-
-	/* This int15 handler is Intel IGD. specific. Other chipsets need other
-	 * handlers. The right way to do this is to move this handler code into
-	 * the mainboard or northbridge code.
-	 * TODO: completely move to mainboards / chipsets.
-	 */
-	switch (regs->eax & 0xffff) {
-	/* And now Intel IGD code */
-#define BOOT_DISPLAY_DEFAULT    0
-#define BOOT_DISPLAY_CRT        (1 << 0)
-#define BOOT_DISPLAY_TV         (1 << 1)
-#define BOOT_DISPLAY_EFP        (1 << 2)
-#define BOOT_DISPLAY_LCD        (1 << 3)
-#define BOOT_DISPLAY_CRT2       (1 << 4)
-#define BOOT_DISPLAY_TV2        (1 << 5)
-#define BOOT_DISPLAY_EFP2       (1 << 6)
-#define BOOT_DISPLAY_LCD2       (1 << 7)
-	case 0x5f35:
-		regs->eax = 0x5f;
-		regs->ecx = BOOT_DISPLAY_DEFAULT;
-		res = 0;
-		break;
-	case 0x5f40:
-		regs->eax = 0x5f;
-		regs->ecx = 3; // This is mainboard specific
-		printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
-		res = 0;
-		break;
-	default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
-				regs->eax & 0xffff);
-	}
-
-	return res;
-}
-
diff --git a/src/devices/oprom/yabel/vbe.c b/src/devices/oprom/yabel/vbe.c
index 75e8f3e..27bf5e6 100644
--- a/src/devices/oprom/yabel/vbe.c
+++ b/src/devices/oprom/yabel/vbe.c
@@ -31,13 +31,14 @@
 #include "mem.h"
 #include "interrupt.h"
 #include "device.h"
-#include "vbe.h"
 
 #include <cbfs.h>
 
 #include <delay.h>
 #include "../../src/lib/jpeg.h"
 
+#include <vbe.h>
+
 // pointer to VBEInfoBuffer, set by vbe_prepare
 u8 *vbe_info_buffer = 0;
 
@@ -45,97 +46,6 @@ u8 *vbe_info_buffer = 0;
 u8 *biosmem;
 u32 biosmem_size;
 
-// these structs are for input from and output to OF
-typedef struct {
-	u8 display_type;	// 0=NONE, 1= analog, 2=digital
-	u16 screen_width;
-	u16 screen_height;
-	u16 screen_linebytes;	// bytes per line in framebuffer, may be more than screen_width
-	u8 color_depth;	// color depth in bpp
-	u32 framebuffer_address;
-	u8 edid_block_zero[128];
-} __attribute__ ((__packed__)) screen_info_t;
-
-typedef struct {
-	u8 signature[4];
-	u16 size_reserved;
-	u8 monitor_number;
-	u16 max_screen_width;
-	u8 color_depth;
-} __attribute__ ((__packed__)) screen_info_input_t;
-
-// these structs only store a subset of the VBE defined fields
-// only those needed.
-typedef struct {
-	char signature[4];
-	u16 version;
-	u8 *oem_string_ptr;
-	u32 capabilities;
-	u16 video_mode_list[256];	// lets hope we never have more than 256 video modes...
-	u16 total_memory;
-} vbe_info_t;
-
-typedef struct {
-	u16 mode_attributes; // 00
-	u8 win_a_attributes; // 02
-	u8 win_b_attributes; // 03
-	u16 win_granularity; // 04
-	u16 win_size;        // 06
-	u16 win_a_segment;   // 08
-	u16 win_b_segment;   // 0a
-	u32 win_func_ptr;    // 0c
-	u16 bytes_per_scanline; // 10
-	u16 x_resolution;    // 12
-	u16 y_resolution;    // 14
-	u8 x_charsize;       // 16
-	u8 y_charsize;       // 17
-	u8 number_of_planes; // 18
-	u8 bits_per_pixel;   // 19
-	u8 number_of_banks;  // 20
-	u8 memory_model;     // 21
-	u8 bank_size;        // 22
-	u8 number_of_image_pages; // 23
-	u8 reserved_page;
-	u8 red_mask_size;
-	u8 red_mask_pos;
-	u8 green_mask_size;
-	u8 green_mask_pos;
-	u8 blue_mask_size;
-	u8 blue_mask_pos;
-	u8 reserved_mask_size;
-	u8 reserved_mask_pos;
-	u8 direct_color_mode_info;
-	u32 phys_base_ptr;
-	u32 offscreen_mem_offset;
-	u16 offscreen_mem_size;
-	u8 reserved[206];
-} __attribute__ ((__packed__)) vesa_mode_info_t;
-
-typedef struct {
-	u16 video_mode;
-	union {
-		vesa_mode_info_t vesa;
-		u8 mode_info_block[256];
-	};
-	// our crap
-	//u16 attributes;
-	//u16 linebytes;
-	//u16 x_resolution;
-	//u16 y_resolution;
-	//u8 x_charsize;
-	//u8 y_charsize;
-	//u8 bits_per_pixel;
-	//u8 memory_model;
-	//u32 framebuffer_address;
-} vbe_mode_info_t;
-
-typedef struct {
-	u8 port_number;	// i.e. monitor number
-	u8 edid_transfer_time;
-	u8 ddc_level;
-	u8 edid_block_zero[128];
-} vbe_ddc_info_t;
-
 static inline u8
 vbe_prepare(void)
 {
diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c
index 1d0c494..d7b1f13 100644
--- a/src/mainboard/kontron/986lcd-m/mainboard.c
+++ b/src/mainboard/kontron/986lcd-m/mainboard.c
@@ -25,6 +25,7 @@
 #endif
 #include <pc80/mc146818rtc.h>
 #include <arch/io.h>
+#include <arch/interrupt.h>
 #include "chip.h"
 
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
@@ -70,6 +71,53 @@ static void int15_install(void)
 }
 #endif
 
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+	int res = -1;
+
+	/* This int15 handler is Intel IGD. specific. Other chipsets need other
+	 * handlers. The right way to do this is to move this handler code into
+	 * the mainboard or northbridge code.
+	 * TODO: completely move to mainboards / chipsets.
+	 */
+	switch (regs->eax & 0xffff) {
+	/* And now Intel IGD code */
+#define BOOT_DISPLAY_DEFAULT    0
+#define BOOT_DISPLAY_CRT        (1 << 0)
+#define BOOT_DISPLAY_TV         (1 << 1)
+#define BOOT_DISPLAY_EFP        (1 << 2)
+#define BOOT_DISPLAY_LCD        (1 << 3)
+#define BOOT_DISPLAY_CRT2       (1 << 4)
+#define BOOT_DISPLAY_TV2        (1 << 5)
+#define BOOT_DISPLAY_EFP2       (1 << 6)
+#define BOOT_DISPLAY_LCD2       (1 << 7)
+	case 0x5f35:
+		regs->eax = 0x5f;
+		regs->ecx = BOOT_DISPLAY_DEFAULT;
+		res = 0;
+		break;
+	case 0x5f40:
+		regs->eax = 0x5f;
+		regs->ecx = 3; // This is mainboard specific
+		printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
+		res = 0;
+		break;
+	default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+	}
+
+	return res;
+}
+
+static void int15_install(void)
+{
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+}
+#endif
+
+
 /* Hardware Monitor */
 
 static u16 hwm_base = 0xa00;
@@ -221,7 +269,7 @@ static void verb_setup(void)
 
 static void mainboard_enable(device_t dev)
 {
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
 	/* Install custom int15 handler for VGA OPROM */
 	int15_install();
 #endif
diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c
index 2c5b5e3..d87d712 100644
--- a/src/mainboard/roda/rk886ex/mainboard.c
+++ b/src/mainboard/roda/rk886ex/mainboard.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <arch/io.h>
+#include <arch/interrupt.h>
 #include <boot/tables.h>
 #include <delay.h>
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
@@ -99,6 +100,52 @@ static void int15_install(void)
 }
 #endif
 
+#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+	int res = -1;
+
+	/* This int15 handler is Intel IGD. specific. Other chipsets need other
+	 * handlers. The right way to do this is to move this handler code into
+	 * the mainboard or northbridge code.
+	 * TODO: completely move to mainboards / chipsets.
+	 */
+	switch (regs->eax & 0xffff) {
+	/* And now Intel IGD code */
+#define BOOT_DISPLAY_DEFAULT    0
+#define BOOT_DISPLAY_CRT        (1 << 0)
+#define BOOT_DISPLAY_TV         (1 << 1)
+#define BOOT_DISPLAY_EFP        (1 << 2)
+#define BOOT_DISPLAY_LCD        (1 << 3)
+#define BOOT_DISPLAY_CRT2       (1 << 4)
+#define BOOT_DISPLAY_TV2        (1 << 5)
+#define BOOT_DISPLAY_EFP2       (1 << 6)
+#define BOOT_DISPLAY_LCD2       (1 << 7)
+	case 0x5f35:
+		regs->eax = 0x5f;
+		regs->ecx = BOOT_DISPLAY_DEFAULT;
+		res = 0;
+		break;
+	case 0x5f40:
+		regs->eax = 0x5f;
+		regs->ecx = 3; // This is mainboard specific
+		printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
+		res = 0;
+		break;
+	default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+	}
+
+	return res;
+}
+
+static void int15_install(void)
+{
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+}
+#endif
+
 #if DUMP_RUNTIME_REGISTERS
 static void dump_runtime_registers(void)
 {
@@ -125,7 +172,7 @@ static void mainboard_enable(device_t dev)
 	/* Disable Dummy DCC -> GP45 = 1 */
 	outb(inb(0x60f) | (1 << 5), 0x60f);
 
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
 	/* Install custom int15 handler for VGA OPROM */
 	int15_install();
 #endif



From gerrit at coreboot.org  Thu Oct 13 00:48:57 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:48:57 +0200
Subject: [coreboot] New patch to review for coreboot: b296563 refactor vesa
	mode setting code and bootsplash code
References: <I0045c9d75757657f4ce531889593102ea1e39ce5+0@gerrit.coreboot.org>
Message-ID: <I0045c9d75757657f4ce531889593102ea1e39ce5+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/256

-gerrit

commit b296563878a245bc138fb213f1fb60e04ae1751a
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 14:30:59 2011 -0700

    refactor vesa mode setting code and bootsplash code
    
    - adds possibility to set a vesa mode without showing a bootsplash
    - make bootsplash / mode setting code available in real mode.
    
    Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/Kconfig                                |   46 +++++++------
 src/arch/x86/boot/coreboot_table.c         |    2 +-
 src/devices/oprom/include/vbe.h            |    8 ++-
 src/devices/oprom/x86.c                    |  103 ++++++++++++++++++++++++++--
 src/devices/oprom/x86.h                    |    1 +
 src/devices/oprom/x86_asm.S                |    5 ++
 src/devices/oprom/yabel/compat/functions.c |    2 +-
 src/devices/oprom/yabel/device.c           |    2 +
 src/devices/oprom/yabel/vbe.c              |    9 ++-
 src/lib/fallback_boot.c                    |    2 +-
 10 files changed, 145 insertions(+), 35 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index e9ceed5..525d452 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -516,40 +516,31 @@ config MBI_FILE
 
 endmenu
 
-menu "Bootsplash"
-	depends on PCI_OPTION_ROM_RUN_YABEL
+menu "Display"
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
 
-config BOOTSPLASH
-	prompt "Show graphical bootsplash"
+config FRAMEBUFFER_SET_VESA_MODE
+	prompt "Set VESA framebuffer mode"
 	bool
-	depends on PCI_OPTION_ROM_RUN_YABEL
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
 	help
-	  This option shows a graphical bootsplash screen. The grapics are
-	  loaded from the CBFS file bootsplash.jpg.
-
-config BOOTSPLASH_FILE
-	string "Bootsplash path and filename"
-	depends on BOOTSPLASH
-	default "bootsplash.jpg"
-	help
-	  The path and filename of the file to use as graphical bootsplash
-	  screen. The file format has to be jpg.
+	  Set VESA framebuffer mode (needed for bootsplash)
 
 # TODO: Turn this into a "choice".
 config FRAMEBUFFER_VESA_MODE
 	prompt "VESA framebuffer video mode"
 	hex
 	default 0x117
-	depends on BOOTSPLASH
+	depends on FRAMEBUFFER_SET_VESA_MODE
 	help
-	  This option sets the resolution used for the coreboot framebuffer and
-	  bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
+	  This option sets the resolution used for the coreboot framebuffer (and
+	  bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
 	  some day make this a "choice".
 
-config COREBOOT_KEEP_FRAMEBUFFER
+config FRAMEBUFFER_KEEP_VESA_MODE
 	prompt "Keep VESA framebuffer"
 	bool
-	depends on BOOTSPLASH
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
 	help
 	  This option keeps the framebuffer mode set after coreboot finishes
 	  execution. If this option is enabled, coreboot will pass a
@@ -557,6 +548,21 @@ config COREBOOT_KEEP_FRAMEBUFFER
 	  framebuffer driver. If this option is disabled, coreboot will switch
 	  back to text mode before handing control to a payload.
 
+config BOOTSPLASH
+	prompt "Show graphical bootsplash"
+	bool
+	depends on FRAMEBUFFER_SET_VESA_MODE
+	help
+	  This option shows a graphical bootsplash screen. The grapics are
+	  loaded from the CBFS file bootsplash.jpg.
+
+config BOOTSPLASH_FILE
+	string "Bootsplash path and filename"
+	depends on BOOTSPLASH
+	default "bootsplash.jpg"
+	help
+	  The path and filename of the file to use as graphical bootsplash
+	  screen. The file format has to be jpg.
 endmenu
 
 menu "Debugging"
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index db3a8a9..d53a23a 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -148,7 +148,7 @@ static void lb_console(struct lb_header *header)
 
 static void lb_framebuffer(struct lb_header *header)
 {
-#if CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER
+#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
 	void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
 
 	struct lb_framebuffer *framebuffer;
diff --git a/src/devices/oprom/include/vbe.h b/src/devices/oprom/include/vbe.h
index b87b0d5..f857b67 100644
--- a/src/devices/oprom/include/vbe.h
+++ b/src/devices/oprom/include/vbe.h
@@ -104,9 +104,11 @@ typedef struct {
 
 struct lb_framebuffer;
 
-void vbe_set_graphics(void); // yabel only
-
-void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+void vbe_set_graphics(void);
 void vbe_textmode_console(void);
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
 
+#define VESA_GET_INFO		0x4f00
+#define VESA_GET_MODE_INFO	0x4f01
+#define VESA_SET_MODE		0x4f02
 
diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index 9a6ce41..22fc2c5 100644
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -25,14 +25,19 @@
 #include <arch/registers.h>
 #include <console/console.h>
 #include <arch/interrupt.h>
-
+#include <cbfs.h>
+#include <delay.h>
 #include "x86.h"
+#include "vbe.h"
+#include "../../src/lib/jpeg.h"
 
 void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
-		u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_call;
+		u32 esi, u32 edi) __attribute__((regparm(0))) =
+						(void *)&__realmode_call;
 
 void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
-		u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt;
+		u32 esi, u32 edi) __attribute__((regparm(0))) =
+						(void *)&__realmode_interrupt;
 
 static void setup_bda(void)
 {
@@ -107,9 +112,9 @@ static void setup_interrupt_handlers(void)
 		if(!intXX_handler[i])
 		{
 			/* Now set the default functions that are actually
-			 * needed to initialize the option roms. This is very
-			 * slick, as it allows us to implement mainboard specific
-			 * interrupt handlers, such as the int15
+			 * needed to initialize the option roms. This is
+			 * very slick, as it allows us to implement mainboard
+			 * specific interrupt handlers, such as the int15.
 			 */
 			switch (i) {
 			case 0x10:
@@ -178,6 +183,88 @@ static void setup_realmode_idt(void)
 	write_idt_stub((void *)0xffe6e, 0x1a);
 }
 
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
+static u8 vbe_get_mode_info(vbe_mode_info_t * mode_info)
+{
+	char *buffer = (char *)&__buffer;
+	u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00;
+	u16 buffer_adr = ((unsigned long)buffer) & 0xffff;
+	realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000,
+			mode_info->video_mode, 0x0000, buffer_seg, buffer_adr);
+	memcpy(mode_info, buffer, sizeof(vbe_mode_info_t));
+	return 0;
+}
+
+static u8 vbe_set_mode(vbe_mode_info_t * mode_info)
+{
+	// request linear framebuffer mode
+	mode_info->video_mode |= (1 << 14);
+	// request clearing of framebuffer
+	mode_info->video_mode &= ~(1 << 15);
+	realmode_interrupt(0x10, VESA_SET_MODE, mode_info->video_mode,
+			0x0000, 0x0000, 0x0000, 0x0000);
+	return 0;
+}
+
+vbe_mode_info_t mode_info;
+
+/* These two functions could probably even be generic between
+ * yabel and x86 native. TBD later.
+ */
+void vbe_set_graphics(void)
+{
+	mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
+	vbe_get_mode_info(&mode_info);
+	unsigned char *framebuffer =
+		(unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr);
+	printk(BIOS_DEBUG, "framebuffer: %p\n", framebuffer);
+	printk(BIOS_DEBUG, "framebuffer: %x\n", mode_info.vesa.phys_base_ptr);
+	vbe_set_mode(&mode_info);
+#if CONFIG_BOOTSPLASH
+	struct jpeg_decdata *decdata;
+	decdata = malloc(sizeof(*decdata));
+	unsigned char *jpeg = cbfs_find_file("bootsplash.jpg",
+						CBFS_TYPE_BOOTSPLASH);
+	if (!jpeg) {
+		return;
+	}
+	int ret = 0;
+	ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata);
+#endif
+}
+
+void vbe_textmode_console(void)
+{
+	delay(2);
+	realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000,
+				0x0000, 0x0000, 0x0000);
+}
+
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+{
+	framebuffer->physical_address =
+				le32_to_cpu(mode_info.vesa.phys_base_ptr);
+
+	framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution);
+	framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution);
+	framebuffer->bytes_per_line =
+				le16_to_cpu(mode_info.vesa.bytes_per_scanline);
+	framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel;
+
+	framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos;
+	framebuffer->red_mask_size = mode_info.vesa.red_mask_size;
+
+	framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos;
+	framebuffer->green_mask_size = mode_info.vesa.green_mask_size;
+
+	framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos;
+	framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size;
+
+	framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos;
+	framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size;
+}
+#endif
+
 void run_bios(struct device *dev, unsigned long addr)
 {
 	u32 num_dev = (dev->bus->secondary << 8) | dev->path.pci.devfn;
@@ -203,6 +290,10 @@ void run_bios(struct device *dev, unsigned long addr)
 	/* Option ROM entry point is at OPROM start + 3 */
 	realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0);
 	printk(BIOS_DEBUG, "... Option ROM returned.\n");
+
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
+	vbe_set_graphics();
+#endif
 }
 
 #if CONFIG_GEODE_VSA
diff --git a/src/devices/oprom/x86.h b/src/devices/oprom/x86.h
index 0bc2412..40c5778 100644
--- a/src/devices/oprom/x86.h
+++ b/src/devices/oprom/x86.h
@@ -30,6 +30,7 @@ void x86_exception(struct eregs *info);
 extern unsigned char __idt_handler, __idt_handler_size;
 extern unsigned char __realmode_code, __realmode_code_size;
 extern unsigned char __realmode_call, __realmode_interrupt;
+extern unsigned char __buffer;
 
 extern void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0)));
diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S
index d5b5e18..57c5338 100644
--- a/src/devices/oprom/x86_asm.S
+++ b/src/devices/oprom/x86_asm.S
@@ -66,6 +66,11 @@ __registers = RELOCATED(.)
 	.long 0 /* 16 - ESI */
 	.long 0 /* 20 - EDI */
 
+/* 256 byte buffer, used by int10 */
+	.globl __buffer
+__buffer = RELOCATED(.)
+	.skip 256
+
 	.code32
 	.globl __realmode_call
 __realmode_call = RELOCATED(.)
diff --git a/src/devices/oprom/yabel/compat/functions.c b/src/devices/oprom/yabel/compat/functions.c
index db37fbc..542c81f 100644
--- a/src/devices/oprom/yabel/compat/functions.c
+++ b/src/devices/oprom/yabel/compat/functions.c
@@ -38,7 +38,7 @@ void run_bios(struct device * dev, unsigned long addr)
 
 	biosemu(vmem, VMEM_SIZE, dev, addr);
 
-#if CONFIG_BOOTSPLASH
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 	vbe_set_graphics();
 #endif
 }
diff --git a/src/devices/oprom/yabel/device.c b/src/devices/oprom/yabel/device.c
index 8259594..b09f50e 100644
--- a/src/devices/oprom/yabel/device.c
+++ b/src/devices/oprom/yabel/device.c
@@ -364,6 +364,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr)
 		pci_ds.device_id = in16le(&pci_ds.device_id);
 		pci_ds.img_length = in16le(&pci_ds.img_length);
 		pci_ds.pci_ds_length = in16le(&pci_ds.pci_ds_length);
+#ifdef DO_THIS_TEST_TWICE
 		if (pci_ds.vendor_id != bios_device.pci_vendor_id) {
 			printf
 			    ("Image has invalid Vendor ID: %04x, expected: %04x\n",
@@ -376,6 +377,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr)
 			     pci_ds.device_id, bios_device.pci_device_id);
 			break;
 		}
+#endif
 		DEBUG_PRINTF("Image Length: %d\n", pci_ds.img_length * 512);
 		DEBUG_PRINTF("Image Code Type: %d\n", pci_ds.code_type);
 		if (pci_ds.code_type == 0) {
diff --git a/src/devices/oprom/yabel/vbe.c b/src/devices/oprom/yabel/vbe.c
index 27bf5e6..b1d6984 100644
--- a/src/devices/oprom/yabel/vbe.c
+++ b/src/devices/oprom/yabel/vbe.c
@@ -13,7 +13,7 @@
 
 #include <string.h>
 #include <types.h>
-#if CONFIG_BOOTSPLASH
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 #include <boot/coreboot_tables.h>
 #endif
 
@@ -64,7 +64,7 @@ vbe_prepare(void)
 	return 0;		// successfull init
 }
 
-#if CONFIG_BOOTSPLASH
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 // VBE Function 00h
 static u8
 vbe_info(vbe_info_t * info)
@@ -704,10 +704,12 @@ void vbe_set_graphics(void)
 
 	mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
 	vbe_get_mode_info(&mode_info);
+	vbe_set_mode(&mode_info);
+
+#if CONFIG_BOOTSPLASH
 	unsigned char *framebuffer =
 		(unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr);
 	DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%p\n", framebuffer);
-	vbe_set_mode(&mode_info);
 
 	struct jpeg_decdata *decdata;
 	decdata = malloc(sizeof(*decdata));
@@ -728,6 +730,7 @@ void vbe_set_graphics(void)
 	DEBUG_PRINTF_VBE("Decompressing boot splash screen...\n");
 	ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata);
 	DEBUG_PRINTF_VBE("returns %x\n", ret);
+#endif
 }
 
 void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c
index a8fe377..b5ec6c3 100644
--- a/src/lib/fallback_boot.c
+++ b/src/lib/fallback_boot.c
@@ -28,7 +28,7 @@ void set_boot_successful(void)
 
 void boot_successful(void)
 {
-#if CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
 	void vbe_textmode_console(void);
 
 	vbe_textmode_console();



From gerrit at coreboot.org  Thu Oct 13 00:48:57 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:48:57 +0200
Subject: [coreboot] New patch to review for coreboot: 6faf97c Fix native x86
	option rom initialization
References: <Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c+0@gerrit.coreboot.org>
Message-ID: <Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/257

-gerrit

commit 6faf97c0c1a10c44fbfebcd25d8b93967263fdfd
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 14:35:54 2011 -0700

    Fix native x86 option rom initialization
    
    - Intel option roms want an initialized i8259 or they will
      throw an exception 6. This should be done in the southbridge
      code, but that is executed much later than the VGA init, so
      initialize the i8259 in src/devices/oprom/x86.c.
      In the long run this will allow getting rid of some of the
      ugly hacks in some AMD boards' romstage.c
    - Don't overwrite the mode when copying mode info information back
      from 0x600.
    
    Change-Id: Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/oprom/x86.c |   25 ++++++++++++++-----------
 1 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index 22fc2c5..4d7357c 100644
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -27,6 +27,7 @@
 #include <arch/interrupt.h>
 #include <cbfs.h>
 #include <delay.h>
+#include <pc80/i8259.h>
 #include "x86.h"
 #include "vbe.h"
 #include "../../src/lib/jpeg.h"
@@ -70,14 +71,9 @@ static int intXX_exception_handler(struct eregs *regs)
 {
 	printk(BIOS_INFO, "Oops, exception %d while executing option rom\n",
 			regs->vector);
-#if 0
-	// Odd: The i945GM VGA oprom chokes on a pushl %eax and will
-	// die with an exception #6 if we run the coreboot exception 
-	// handler. Just continue, as it executes fine.
 	x86_exception(regs);	// Call coreboot exception handler
-#endif
 
-	return 0;		// Never returns?
+	return 0;		// Never really returns
 }
 
 static int intXX_unknown_handler(struct eregs *regs)
@@ -186,17 +182,20 @@ static void setup_realmode_idt(void)
 #if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 static u8 vbe_get_mode_info(vbe_mode_info_t * mode_info)
 {
+	printk(BIOS_DEBUG, "Getting information about VESA mode %04x\n",
+		mode_info->video_mode);
 	char *buffer = (char *)&__buffer;
 	u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00;
 	u16 buffer_adr = ((unsigned long)buffer) & 0xffff;
 	realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000,
 			mode_info->video_mode, 0x0000, buffer_seg, buffer_adr);
-	memcpy(mode_info, buffer, sizeof(vbe_mode_info_t));
+	memcpy(mode_info->mode_info_block, buffer, sizeof(vbe_mode_info_t));
 	return 0;
 }
 
 static u8 vbe_set_mode(vbe_mode_info_t * mode_info)
 {
+	printk(BIOS_DEBUG, "Setting VESA mode %04x\n", mode_info->video_mode);
 	// request linear framebuffer mode
 	mode_info->video_mode |= (1 << 14);
 	// request clearing of framebuffer
@@ -216,9 +215,8 @@ void vbe_set_graphics(void)
 	mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
 	vbe_get_mode_info(&mode_info);
 	unsigned char *framebuffer =
-		(unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr);
+		(unsigned char *)mode_info.vesa.phys_base_ptr;
 	printk(BIOS_DEBUG, "framebuffer: %p\n", framebuffer);
-	printk(BIOS_DEBUG, "framebuffer: %x\n", mode_info.vesa.phys_base_ptr);
 	vbe_set_mode(&mode_info);
 #if CONFIG_BOOTSPLASH
 	struct jpeg_decdata *decdata;
@@ -242,8 +240,7 @@ void vbe_textmode_console(void)
 
 void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
 {
-	framebuffer->physical_address =
-				le32_to_cpu(mode_info.vesa.phys_base_ptr);
+	framebuffer->physical_address = mode_info.vesa.phys_base_ptr;
 
 	framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution);
 	framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution);
@@ -269,6 +266,12 @@ void run_bios(struct device *dev, unsigned long addr)
 {
 	u32 num_dev = (dev->bus->secondary << 8) | dev->path.pci.devfn;
 
+	/* Setting up required hardware.
+	 * Removing this will cause random illegal instruction exceptions
+	 * in some option roms.
+	 */
+	setup_i8259();
+
 	/* Set up BIOS Data Area */
 	setup_bda();
 



From gerrit at coreboot.org  Thu Oct 13 00:48:58 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:48:58 +0200
Subject: [coreboot] New patch to review for coreboot: b043841 Fix
	compilation of x86emu with gcc 4.6.x
References: <Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e+0@gerrit.coreboot.org>
Message-ID: <Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/258

-gerrit

commit b0438411e379d3fa1e3e7f43963138eb2d46a2fd
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 4 10:34:37 2011 -0700

    Fix compilation of x86emu with gcc 4.6.x
    
    gcc 4.6 complains about unused but set variables in x86emu.
    Particularly some variables are always set but only used in
    debug mode, or when FPU support is enabled.
    
    Change-Id: Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/oprom/x86emu/debug.h |    6 ++++++
 src/devices/oprom/x86emu/fpu.c   |   32 +++++++++++++++++++-------------
 src/devices/oprom/x86emu/ops.c   |    8 ++++----
 src/devices/oprom/x86emu/ops2.c  |    2 +-
 4 files changed, 30 insertions(+), 18 deletions(-)

diff --git a/src/devices/oprom/x86emu/debug.h b/src/devices/oprom/x86emu/debug.h
index ba180ba..1b2c3a3 100644
--- a/src/devices/oprom/x86emu/debug.h
+++ b/src/devices/oprom/x86emu/debug.h
@@ -198,6 +198,12 @@
 #define	DB(x)
 #endif
 
+#ifdef DEBUG
+#define X86EMU_DEBUG_ONLY(x) x
+#else
+#define X86EMU_DEBUG_ONLY(x) X86EMU_UNUSED(x)
+#endif
+
 /*-------------------------- Function Prototypes --------------------------*/
 
 #ifdef  __cplusplus
diff --git a/src/devices/oprom/x86emu/fpu.c b/src/devices/oprom/x86emu/fpu.c
index daa2ffa..7edebd4 100644
--- a/src/devices/oprom/x86emu/fpu.c
+++ b/src/devices/oprom/x86emu/fpu.c
@@ -50,6 +50,12 @@ void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1))
     END_OF_INSTR_NO_TRACE();
 }
 
+#ifdef X86EMU_FPU_PRESENT
+#define X86EMU_FPU_ONLY(x) x
+#else
+#define X86EMU_FPU_ONLY(x) X86EMU_UNUSED(x)
+#endif
+
 #ifdef DEBUG
 
 static const char *x86emu_fpu_op_d9_tab[] = {
@@ -95,8 +101,8 @@ static const char *x86emu_fpu_op_d9_tab1[] = {
 void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -322,8 +328,8 @@ static const char *x86emu_fpu_op_da_tab[] = {
 void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -403,7 +409,7 @@ static const char *x86emu_fpu_op_db_tab[] = {
 void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
+    uint X86EMU_FPU_ONLY(destoffset);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -530,8 +536,8 @@ static const char *x86emu_fpu_op_dc_tab[] = {
 void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -640,8 +646,8 @@ static const char *x86emu_fpu_op_dd_tab[] = {
 void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -747,8 +753,8 @@ static const char *x86emu_fpu_op_de_tab[] =
 void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -866,8 +872,8 @@ static const char *x86emu_fpu_op_df_tab[] = {
 void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
diff --git a/src/devices/oprom/x86emu/ops.c b/src/devices/oprom/x86emu/ops.c
index c66da95..70e048d 100644
--- a/src/devices/oprom/x86emu/ops.c
+++ b/src/devices/oprom/x86emu/ops.c
@@ -3562,7 +3562,7 @@ Handles opcode 0xcc
 ****************************************************************************/
 static void x86emuOp_int3(u8 X86EMU_UNUSED(op1))
 {
-    u16 tmp;
+    u16 X86EMU_UNUSED(tmp);
 
     START_OF_INSTR();
     DECODE_PRINTF("INT 3\n");
@@ -3590,7 +3590,7 @@ Handles opcode 0xcd
 ****************************************************************************/
 static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1))
 {
-    u16 tmp;
+    u16 X86EMU_UNUSED(tmp);
     u8 intnum;
 
     START_OF_INSTR();
@@ -3620,7 +3620,7 @@ Handles opcode 0xce
 ****************************************************************************/
 static void x86emuOp_into(u8 X86EMU_UNUSED(op1))
 {
-    u16 tmp;
+    u16 X86EMU_UNUSED(tmp);
 
     START_OF_INSTR();
     DECODE_PRINTF("INTO\n");
@@ -4034,7 +4034,7 @@ Handles opcode 0xd5
 ****************************************************************************/
 static void x86emuOp_aad(u8 X86EMU_UNUSED(op1))
 {
-    u8 a;
+    u8 X86EMU_UNUSED(a);
 
     START_OF_INSTR();
     DECODE_PRINTF("AAD\n");
diff --git a/src/devices/oprom/x86emu/ops2.c b/src/devices/oprom/x86emu/ops2.c
index 349a664..f559874 100644
--- a/src/devices/oprom/x86emu/ops2.c
+++ b/src/devices/oprom/x86emu/ops2.c
@@ -336,7 +336,7 @@ static void x86emuOp2_set_byte(u8 op2)
     int mod, rl, rh;
     uint destoffset;
     u8  *destreg;
-    const char *name = 0;
+    const char *X86EMU_DEBUG_ONLY(name) = 0;
     int cond = 0;
 
     START_OF_INSTR();



From gerrit at coreboot.org  Thu Oct 13 00:48:59 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:48:59 +0200
Subject: [coreboot] New patch to review for coreboot: 7f8e685 Load an IDT
	with NULL limit
References: <I8d048c894c863ac4971fcef8f065be6b899e1d3e+0@gerrit.coreboot.org>
Message-ID: <I8d048c894c863ac4971fcef8f065be6b899e1d3e+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/259

-gerrit

commit 7f8e685996f65f2c67d1113fcfaab33ccc385da7
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jun 1 14:01:46 2011 -0700

    Load an IDT with NULL limit
    
    Load an IDT with NULL limit to prevent the 16bit IDT being used
    in protected mode before c_start.S sets up a 32bit IDT when entering
    ram stage.
    
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e
---
 src/cpu/x86/16bit/entry16.inc |   15 ++++++++++++++-
 src/cpu/x86/16bit/entry16.lds |    1 +
 2 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 1eb92c8..9f4c0e3 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -45,7 +45,6 @@ _start:
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
 
-
 	/* Invalidating the cache here seems to be a bad idea on
 	 * modern processors.  Don't.
 	 * If we are hyperthreaded or we have multiple cores it is bad,
@@ -55,6 +54,13 @@ _start:
 	 * entry16.inc.
 	 */
 
+	/* Load an IDT with NULL limit to prevent the 16bit IDT being used
+	 * in protected mode before c_start.S sets up a 32bit IDT when entering
+	 * ram stage.
+	 */
+	movw $nullidt_offset, %bx
+	lidt %cs:(%bx)
+
 	/* Note: gas handles memory addresses in 16 bit code very poorly.
 	 * In particular it doesn't appear to have a directive allowing you
 	 * associate a section or even an absolute offset with a segment register.
@@ -118,6 +124,13 @@ gdtptr16:
 	.word	gdt_end - gdt -1 /* compute the table limit */
 	.long	gdt		 /* we know the offset */
 
+.align	4
+.globl nullidt
+nullidt:
+	.word	0	/* limit */
+	.long	0
+	.word	0
+
 .globl _estart
 _estart:
 	.code32
diff --git a/src/cpu/x86/16bit/entry16.lds b/src/cpu/x86/16bit/entry16.lds
index 0580f0e..112d429 100644
--- a/src/cpu/x86/16bit/entry16.lds
+++ b/src/cpu/x86/16bit/entry16.lds
@@ -1 +1,2 @@
 	gdtptr16_offset = gdtptr16 & 0xffff;
+	nullidt_offset = nullidt & 0xffff;



From gerrit at coreboot.org  Thu Oct 13 00:49:00 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:49:00 +0200
Subject: [coreboot] New patch to review for coreboot: 9570367 Prevent build
	breakage without consoles enabled
References: <Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2+0@gerrit.coreboot.org>
Message-ID: <Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/260

-gerrit

commit 957036708c6ce1396fc1ebbf33e3e3a01af09bc7
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jun 1 14:04:50 2011 -0700

    Prevent build breakage without consoles enabled
    
    If all console types are disabled, coreboot will fail to compile because
    static code is unused. This patch fixes the issue.
    
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2
---
 src/arch/x86/boot/coreboot_table.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index d53a23a..cdfc0c1 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -120,6 +120,8 @@ static struct lb_serial *lb_serial(struct lb_header *header)
 #endif
 }
 
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \
+    CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG
 static void add_console(struct lb_header *header, u16 consoletype)
 {
 	struct lb_console *console;
@@ -130,6 +132,8 @@ static void add_console(struct lb_header *header, u16 consoletype)
 	console->type = consoletype;
 }
 
+#endif
+
 static void lb_console(struct lb_header *header)
 {
 #if CONFIG_CONSOLE_SERIAL8250



From gerrit at coreboot.org  Thu Oct 13 00:49:00 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:49:00 +0200
Subject: [coreboot] New patch to review for coreboot: 6b15b74 Extend
	coreboot table entry for serial ports
References: <I5f7b5eda6063261b9acb7a46310172d4a5471dfb+0@gerrit.coreboot.org>
Message-ID: <I5f7b5eda6063261b9acb7a46310172d4a5471dfb+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/261

-gerrit

commit 6b15b744b316b88f2affec952aaa8e5732007fa1
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jun 22 16:39:19 2011 -0700

    Extend coreboot table entry for serial ports
    
    Add information about memory mapped/io mapped base addresses.
    
    and fix up libpayload to use the same structures
    
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    
    Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb
---
 payloads/libpayload/arch/i386/coreboot.c      |    4 +++-
 payloads/libpayload/arch/powerpc/coreboot.c   |    4 +++-
 payloads/libpayload/include/coreboot_tables.h |   16 ++++++++++++----
 src/arch/x86/boot/coreboot_table.c            |   15 +++++++++++++--
 src/console/uart8250mem_console.c             |    5 +++++
 src/include/boot/coreboot_tables.h            |    5 ++++-
 src/include/uart8250.h                        |    1 +
 7 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index e3c944d..bdef4e8 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -77,7 +77,9 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct cb_serial *ser = (struct cb_serial *)ptr;
-	info->ser_ioport = ser->ioport;
+	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
+		return;
+	info->ser_ioport = ser->baseaddr;
 }
 
 #ifdef CONFIG_NVRAM
diff --git a/payloads/libpayload/arch/powerpc/coreboot.c b/payloads/libpayload/arch/powerpc/coreboot.c
index ee1842c..7da87ed 100644
--- a/payloads/libpayload/arch/powerpc/coreboot.c
+++ b/payloads/libpayload/arch/powerpc/coreboot.c
@@ -77,7 +77,9 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct cb_serial *ser = (struct cb_serial *)ptr;
-	info->ser_ioport = ser->ioport;
+	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
+		return;
+	info->ser_ioport = ser->baseaddr;
 }
 
 #ifdef CONFIG_NVRAM
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index c4dc115..d342c99 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -60,9 +60,13 @@ struct cb_memory_range {
 	u32 type;
 };
 
-#define CB_MEM_RAM      1
-#define CB_MEM_RESERVED 2
-#define CB_MEM_TABLE    16
+#define CB_MEM_RAM          1
+#define CB_MEM_RESERVED     2
+#define CB_MEM_ACPI         3
+#define CB_MEM_NVS          4
+#define CB_MEM_UNUSABLE     5
+#define CB_MEM_VENDOR_RSVD  6
+#define CB_MEM_TABLE       16
 
 struct cb_memory {
 	u32 tag;
@@ -110,7 +114,11 @@ struct cb_string {
 struct cb_serial {
 	u32 tag;
 	u32 size;
-	u16 ioport;
+#define CB_SERIAL_TYPE_IO_MAPPED     1
+#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
+	u32 type;
+	u32 baseaddr;
+	u32 baud;
 };
 
 #define CB_TAG_CONSOLE       0x00010
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index cdfc0c1..78ff97d 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -112,7 +112,19 @@ static struct lb_serial *lb_serial(struct lb_header *header)
 	serial = (struct lb_serial *)rec;
 	serial->tag = LB_TAG_SERIAL;
 	serial->size = sizeof(*serial);
-	serial->ioport = CONFIG_TTYS0_BASE;
+	serial->type = LB_SERIAL_TYPE_IO_MAPPED;
+	serial->baseaddr = CONFIG_TTYS0_BASE;
+	serial->baud = CONFIG_TTYS0_BAUD;
+	return serial;
+#elif CONFIG_CONSOLE_SERIAL8250MEM
+	struct lb_record *rec;
+	struct lb_serial *serial;
+	rec = lb_new_record(header);
+	serial = (struct lb_serial *)rec;
+	serial->tag = LB_TAG_SERIAL;
+	serial->size = sizeof(*serial);
+	serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+	serial->baseaddr = uartmem_getbaseaddr();
 	serial->baud = CONFIG_TTYS0_BAUD;
 	return serial;
 #else
@@ -131,7 +143,6 @@ static void add_console(struct lb_header *header, u16 consoletype)
 	console->size = sizeof(*console);
 	console->type = consoletype;
 }
-
 #endif
 
 static void lb_console(struct lb_header *header)
diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c
index e622ad0..923df99 100644
--- a/src/console/uart8250mem_console.c
+++ b/src/console/uart8250mem_console.c
@@ -28,6 +28,11 @@ static void uartmem_init(void)
 	uart_bar = uart_mem_init();
 }
 
+u32 uartmem_getbaseaddr(void)
+{
+	return uart_bar;
+}
+
 static void uartmem_tx_byte(unsigned char data)
 {
 	if (!uart_bar)
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 983b03f..45ba3af 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -146,7 +146,10 @@ struct lb_string {
 struct lb_serial {
 	uint32_t tag;
 	uint32_t size;
-	uint16_t ioport;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
 	uint32_t baud;
 };
 
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index 4a02179..3c8ea09 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -146,6 +146,7 @@ void uart8250_mem_tx_byte(unsigned base_port, unsigned char data);
 void uart8250_mem_tx_flush(unsigned base_port);
 void uart8250_mem_init(unsigned base_port, unsigned divisor);
 u32 uart_mem_init(void);
+u32 uartmem_getbaseaddr(void);
 
 /* and special init for OXPCIe based cards */
 void oxford_init(void);



From gerrit at coreboot.org  Thu Oct 13 00:49:01 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 00:49:01 +0200
Subject: [coreboot] Patch set updated for coreboot: 7b68d61 Update coreboot
	cross toolchain to gcc 4.6.1
References: <I132c01293fc0cff0cfb84556a93c0b8de8e57230+0@gerrit.coreboot.org>
Message-ID: <I132c01293fc0cff0cfb84556a93c0b8de8e57230+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/250

-gerrit

commit 7b68d61bfff591f5fdec7c63fc9af66cf7dd0c13
Author: Stefan Reinauer <reinauer at google.com>
Date:   Tue Oct 11 22:37:59 2011 -0700

    Update coreboot cross toolchain to gcc 4.6.1
    
    - Tested on Mac OS X 10.7.1
    - Tested on Ubuntu 10.04 LTS (Lucid Lynx)
    
    Please test on Windows and other Linux distributions
    
    Change-Id: I132c01293fc0cff0cfb84556a93c0b8de8e57230
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/crossgcc/buildgcc                             |   76 ++++--
 .../acpica-unix-20110922_unknown_warnings.patch    |   19 ++
 .../binutils-2.20_no-i386-svr4-asm-comments.patch  |   10 -
 .../patches/binutils-2.21.1_no-bfd-doc.patch       |   11 +
 .../patches/gcc-4.4.2_less-junk-in-crtbegin.patch  |   50 ----
 util/crossgcc/patches/gcc-4.5.1_pragma.patch       |   10 -
 .../patches/mpfr-2.4.2_allpatches_20100308.patch   |  266 --------------------
 7 files changed, 80 insertions(+), 362 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 6061f26..40444a5 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -20,8 +20,8 @@
 # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA
 #
 
-CROSSGCC_DATE="August 8th, 2011"
-CROSSGCC_VERSION="1.04"
+CROSSGCC_DATE="October 10th, 2011"
+CROSSGCC_VERSION="1.05"
 
 # default settings
 TARGETDIR=`pwd`/xgcc
@@ -29,17 +29,18 @@ TARGETARCH=i386-elf
 DESTDIR=
 
 # version numbers
-GMP_VERSION=5.0.1
-MPFR_VERSION=3.0.0
-MPC_VERSION=0.8.2
+GMP_VERSION=5.0.2
+MPFR_VERSION=3.1.0
+MPC_VERSION=0.9
 LIBELF_VERSION=0.8.13
-GCC_VERSION=4.5.2
-BINUTILS_VERSION=2.20.1
+GCC_VERSION=4.6.1
+GCC_AUTOCONF_VERSION=2.64
+BINUTILS_VERSION=2.21.1
 GDB_VERSION=7.3.1
 W32API_VERSION=3.17-2
 W32API_VERSION_SHORT=3.17
 MINGWRT_VERSION=3.18
-IASL_VERSION=20110623
+IASL_VERSION=20110922
 
 # archive locations
 GMP_ARCHIVE="ftp://ftp.gmplib.org/pub/gmp-${GMP_VERSION}/gmp-${GMP_VERSION}.tar.bz2"
@@ -146,7 +147,7 @@ GNU General Public License for more details.
 EOF
 }
 
-printf "${blue}Welcome to the ${red}coresystems${blue} cross toolchain builder v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n"
+printf "${blue}Welcome to the ${red}coreboot${blue} cross toolchain builder v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n"
 
 # Look if we have getopt. If not, build it.
 export PATH=$PATH:.
@@ -198,14 +199,12 @@ if [ "$TARGETARCH" = "i386-mingw32" ]; then
 	MINGW_ARCHIVES="$W32API_ARCHIVE $MINGWRT_ARCHIVE"
 fi
 
-if [ ${GCC_VERSION} = "4.5.0" -o ${GCC_VERSION} = "4.6.0" ]; then
-  # coreboot does not like the GOLD linker
-  # USE_GOLD="--enable-gold"
-  USE_GOLD=""
-  GCC_OPTIONS="--enable-lto"
-fi
+# coreboot does not like the GOLD linker
+# USE_GOLD="--enable-gold"
+USE_GOLD=""
+GCC_OPTIONS="--enable-lto"
 
-if [ ${GCC_VERSION} = "4.6.0" ]; then
+if [ ${GCC_VERSION} = "4.6.2" ]; then
   if [ ! -r tarballs/gcc-core-${GCC_VERSION}.tar.bz2 ]; then
     printf "Pre-Release GCC ${GCC_VERSION}, checking out subversion trunk\n"
     mkdir -p tarballs/.tmp
@@ -273,6 +272,7 @@ if [ "$TARGETARCH" = "i386-mingw32" ]; then
 	mv $MINGWRT_DIR/include/* $W32API_DIR/include/* $TARGETDIR/i386-mingw32/sys-include
 fi
 
+CC=cc
 if [ `uname` = "Darwin" ]; then
 	#GCC_OPTIONS="$GCC_OPTIONS --enable-threads=posix"
 
@@ -286,13 +286,14 @@ if [ `uname` = "Darwin" ]; then
 	else
 		OPTIONS="ABI=32"
 	fi
-	# old check:
-	#OPTIONS="ABI=32"
-	#touch .architecture_check.c
-	#gcc .architecture_check.c -c -o .architecture_check.o
-	#ARCH=`file .architecture_check.o |cut -f5 -d\ `
-	#test  "$ARCH" = "x86_64" && OPTIONS="ABI=64"
-	#rm .architecture_check.c .architecture_check.o
+
+	# In Xcode 4 the default compiler was switched to gcc-llvm.
+	# However, this compiler fails to compile gcc 4.6.x. As a
+	# workaround it's possible to compile gcc with gcc-4.2 or
+	# clang.
+	if $CC -v 2>&1 | grep -q LLVM; then
+		CC=clang
+	fi
 fi
 
 mkdir -p build-gmp build-mpfr build-mpc build-libelf build-binutils build-gcc
@@ -321,8 +322,10 @@ fi
 #	ln -s $DESTDIR$TARGETDIR $TARGETDIR
 #fi
 
-# Now set CFLAGS to match GMP CFLAGS.
-HOSTCFLAGS=`grep __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h |cut -d\" -f2`
+# Now set CFLAGS to match GMP CFLAGS but strip out -pedantic
+# as GCC 4.6.x fails if it's there.
+HOSTCFLAGS=`grep __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h |cut -d\" -f2 |\
+	    sed s,-pedantic,,`
 
 if [ -f build-mpfr/.success ]; then
 	printf "Skipping MPFR as it is already built\n"
@@ -393,6 +396,12 @@ if [ -f build-binutils/.success ]; then
 else
 printf "Building binutils ${BINUTILS_VERSION} ... "
 (
+	# What a pain: binutils don't come with configure
+	# script anymore. Create it:
+	cd binutils-${BINUTILS_VERSION}/
+	autoconf
+	cd ..
+	# Now build binutils
 	cd build-binutils
 	rm -f .failed
 	../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR --target=${TARGETARCH} \
@@ -411,6 +420,19 @@ if [ -f build-gcc/.success ]; then
 else
 printf "Building GCC ${GCC_VERSION} ... "
 (
+	# Even worse than binutils: GCC does not come with configure
+	# script anymore, but also enforces an obsolete autoconf version
+	# to create it. This is a poster child of how autotools help make
+	# software portable.
+	cd gcc-${GCC_VERSION}
+	sed '/dnl Ensure exactly this Autoconf version is used/d' \
+		config/override.m4 > config/override.m4.new
+	autoconf_version=`autoconf -V | grep "autoconf" | tr ' ' '\n' | tail -1`
+	sed "s/${GCC_AUTOCONF_VERSION}/${autoconf_version}/g" \
+		config/override.m4.new > config/override.m4
+	autoconf
+	cd ..
+	# Now, finally, we can build gcc:
 	cd build-gcc
 	export PATH=$PATH:$DESTDIR$TARGETDIR/bin
 	rm -f .failed
@@ -419,10 +441,12 @@ printf "Building GCC ${GCC_VERSION} ... "
 	# There's a work-around called CFLAGS_FOR_BUILD and CFLAGS_FOR_TARGET
 	# but it does not seem to work properly. At least the host library
 	# libiberty is not compiled with CFLAGS_FOR_BUILD.
-	CFLAGS_FOR_TARGET="-O2" CFLAGS="$HOSTCFLAGS" CFLAGS_FOR_BUILD="$HOSTCFLAGS" `readlink -f ../gcc-${GCC_VERSION}/configure` \
+	CC="$CC" CFLAGS_FOR_TARGET="-O2" CFLAGS="$HOSTCFLAGS" \
+		CFLAGS_FOR_BUILD="$HOSTCFLAGS" ../gcc-${GCC_VERSION}/configure \
 		--prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \
 		--target=${TARGETARCH} --disable-werror --disable-shared \
 		--disable-libssp --disable-bootstrap --disable-nls \
+		--disable-libquadmath \
 		$GCC_OPTIONS --enable-languages="c" $USE_GOLD \
 		--with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \
 		--with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \
diff --git a/util/crossgcc/patches/acpica-unix-20110922_unknown_warnings.patch b/util/crossgcc/patches/acpica-unix-20110922_unknown_warnings.patch
new file mode 100644
index 0000000..f53be92
--- /dev/null
+++ b/util/crossgcc/patches/acpica-unix-20110922_unknown_warnings.patch
@@ -0,0 +1,19 @@
+--- acpica-unix-20110922/compiler/Makefile	2011-09-22 08:59:34.000000000 -0700
++++ acpica-unix-20110922/compiler/Makefile	2011-10-11 23:47:29.000000000 -0700
+@@ -245,15 +245,11 @@
+     -Waggregate-return \
+     -Wchar-subscripts \
+     -Wempty-body \
+-    -Wlogical-op \
+     -Wmissing-declarations \
+     -Wmissing-field-initializers \
+-    -Wmissing-parameter-type \
+     -Wnested-externs \
+-    -Wold-style-declaration \
+     -Wold-style-definition \
+-    -Wredundant-decls \
+-    -Wtype-limits
++    -Wredundant-decls
+ 
+ #
+ # Bison/Flex configuration
diff --git a/util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch b/util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch
deleted file mode 100644
index 3c0cef9..0000000
--- a/util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- binutils-2.20/gas/config/tc-i386.c~	2009-01-20 14:19:04.000000000 +0100
-+++ binutils-2.20/gas/config/tc-i386.c	2009-01-20 14:20:47.000000000 +0100
-@@ -318,6 +318,7 @@
- 	 && !defined (TE_GNU)				\
- 	 && !defined (TE_LINUX)				\
-  	 && !defined (TE_NETWARE)			\
-+	 && 0						\
- 	 && !defined (TE_FreeBSD)			\
- 	 && !defined (TE_NetBSD)))
- /* This array holds the chars that always start a comment.  If the
diff --git a/util/crossgcc/patches/binutils-2.21.1_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.21.1_no-bfd-doc.patch
new file mode 100644
index 0000000..4fb9e21
--- /dev/null
+++ b/util/crossgcc/patches/binutils-2.21.1_no-bfd-doc.patch
@@ -0,0 +1,11 @@
+--- binutils-2.21.1/bfd/Makefile.in	2011-06-27 01:57:12.000000000 -0700
++++ binutils-2.21.1/bfd/Makefile.in	2011-10-11 21:59:15.000000000 -0700
+@@ -323,7 +323,7 @@
+ RELEASE = y
+ INCDIR = $(srcdir)/../include
+ CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
+-SUBDIRS = doc po
++SUBDIRS = po
+ bfddocdir = doc
+ libbfd_la_LDFLAGS = $(am__append_1) -release `cat libtool-soversion` \
+ 	@SHARED_LDFLAGS@ $(am__empty)
diff --git a/util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch b/util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch
deleted file mode 100644
index a1c2480..0000000
--- a/util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch
+++ /dev/null
@@ -1,50 +0,0 @@
---- t/gcc-4.4.2/gcc/crtstuff.c	Fr. Apr 10 01:23:07 2009
-+++ gcc-4.4.2/gcc/crtstuff.c	Di. Jul 28 16:43:28 2009
-@@ -204,6 +204,7 @@
-   = { (func_ptr) (-1) };
- #endif /* __DTOR_LIST__ alternatives */
-
-+#if 0
- #ifdef USE_EH_FRAME_REGISTRY
- /* Stick a label at the beginning of the frame unwind info so we can register
-    and deregister it with the exception handling library code.  */
-@@ -219,6 +220,7 @@
-   __attribute__ ((unused, section(JCR_SECTION_NAME), aligned(sizeof(void*))))
-   = { };
- #endif /* JCR_SECTION_NAME */
-+#endif
-
- #if defined(INIT_SECTION_ASM_OP) || defined(INIT_ARRAY_SECTION_ASM_OP)
-
-@@ -309,6 +311,7 @@
-   }
- #endif /* !defined(FINI_ARRAY_SECTION_ASM_OP) */
-
-+#if 0
- #ifdef USE_EH_FRAME_REGISTRY
- #ifdef CRT_GET_RFIB_DATA
-   /* If we used the new __register_frame_info_bases interface,
-@@ -320,6 +323,7 @@
-     __deregister_frame_info (__EH_FRAME_BEGIN__);
- #endif
- #endif
-+#endif
-
-   completed = 1;
- }
-@@ -333,6 +337,7 @@
-   = { __do_global_dtors_aux };
- #endif /* !defined(FINI_SECTION_ASM_OP) */
-
-+#if 0
- #if defined(USE_EH_FRAME_REGISTRY) || defined(JCR_SECTION_NAME)
- /* Stick a call to __register_frame_info into the .init section.  For some
-    reason calls with no arguments work more reliably in .init, so stick the
-@@ -364,6 +369,7 @@
-     }
- #endif /* JCR_SECTION_NAME */
- }
-+#endif
-
- #ifdef INIT_SECTION_ASM_OP
- CRT_CALL_STATIC_FUNCTION (INIT_SECTION_ASM_OP, frame_dummy)
diff --git a/util/crossgcc/patches/gcc-4.5.1_pragma.patch b/util/crossgcc/patches/gcc-4.5.1_pragma.patch
deleted file mode 100644
index 36ac8f4..0000000
--- a/util/crossgcc/patches/gcc-4.5.1_pragma.patch
+++ /dev/null
@@ -1,10 +0,0 @@
-diff -ur gcc-4.5.1.orig/gcc/config/i386/i386elf.h gcc-4.5.1/gcc/config/i386/i386elf.h
---- gcc-4.5.1.orig/gcc/config/i386/i386elf.h	2010-11-17 19:48:16.184401200 -0700
-+++ gcc-4.5.1/gcc/config/i386/i386elf.h	2010-11-17 20:52:54.443969900 -0700
-@@ -123,3 +123,6 @@
- #undef ASM_OUTPUT_ALIGNED_BSS
- #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-   asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-+
-+/* Enable parsing of #pragma pack(push,<n>) and #pragma pack(pop).  */
-+#define HANDLE_PRAGMA_PACK_PUSH_POP 1
diff --git a/util/crossgcc/patches/mpfr-2.4.2_allpatches_20100308.patch b/util/crossgcc/patches/mpfr-2.4.2_allpatches_20100308.patch
deleted file mode 100644
index 6603337..0000000
--- a/util/crossgcc/patches/mpfr-2.4.2_allpatches_20100308.patch
+++ /dev/null
@@ -1,266 +0,0 @@
-diff -ur mpfr-2.4.2.orig/PATCHES mpfr-2.4.2/PATCHES
---- mpfr-2.4.2.orig/PATCHES	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/PATCHES	2010-03-08 22:28:53.000000000 +0100
-@@ -0,0 +1,3 @@
-+gmp5
-+longlong.h
-+sin_cos_underflow
-diff -ur mpfr-2.4.2.orig/VERSION mpfr-2.4.2/VERSION
---- mpfr-2.4.2.orig/VERSION	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/VERSION	2010-03-08 22:28:53.000000000 +0100
-@@ -1 +1 @@
--2.4.2
-+2.4.2-p3
-diff -ur mpfr-2.4.2.orig/configure mpfr-2.4.2/configure
---- mpfr-2.4.2.orig/configure	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/configure	2010-03-08 22:28:53.000000000 +0100
-@@ -20449,6 +20449,9 @@
- main ()
- {
- 
-+#ifndef BITS_PER_MP_LIMB
-+#define BITS_PER_MP_LIMB GMP_LIMB_BITS
-+#endif
-   return BITS_PER_MP_LIMB == BYTES_PER_MP_LIMB * CHAR_BIT
-          && sizeof(mp_limb_t) == BYTES_PER_MP_LIMB ? 0 : 1;
- 
-diff -ur mpfr-2.4.2.orig/configure.in mpfr-2.4.2/configure.in
---- mpfr-2.4.2.orig/configure.in	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/configure.in	2010-03-08 22:28:53.000000000 +0100
-@@ -424,6 +424,9 @@
- #include "gmp.h"
- #include "gmp-impl.h"
- ]], [[
-+#ifndef BITS_PER_MP_LIMB
-+#define BITS_PER_MP_LIMB GMP_LIMB_BITS
-+#endif
-   return BITS_PER_MP_LIMB == BYTES_PER_MP_LIMB * CHAR_BIT
-          && sizeof(mp_limb_t) == BYTES_PER_MP_LIMB ? 0 : 1;
- ]])], [AC_MSG_RESULT(yes)], [
-diff -ur mpfr-2.4.2.orig/mpfr-impl.h mpfr-2.4.2/mpfr-impl.h
---- mpfr-2.4.2.orig/mpfr-impl.h	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/mpfr-impl.h	2010-03-08 22:28:53.000000000 +0100
-@@ -65,6 +65,12 @@
- # ifndef __GMP_IMPL_H__
- #  include "gmp-impl.h"
- # endif
-+# ifndef BITS_PER_MP_LIMB
-+#  define BITS_PER_MP_LIMB GMP_LIMB_BITS
-+# endif
-+#ifndef mpn_sqr_n
-+# define mpn_sqr_n mpn_sqr
-+#endif
- # ifdef MPFR_NEED_LONGLONG_H
- #  include "longlong.h"
- # endif
-diff -ur mpfr-2.4.2.orig/mpfr-longlong.h mpfr-2.4.2/mpfr-longlong.h
---- mpfr-2.4.2.orig/mpfr-longlong.h	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/mpfr-longlong.h	2010-03-08 22:28:53.000000000 +0100
-@@ -1011,7 +1011,15 @@
- #endif /* __m88000__ */
- 
- #if defined (__mips) && W_TYPE_SIZE == 32
--#if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
-+#if (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4)
-+#define umul_ppmm(w1, w0, u, v) \
-+  do {									\
-+    UDItype _r;							\
-+    _r = (UDItype) u * v;						\
-+    (w1) = _r >> 32;							\
-+    (w0) = (USItype) _r;						\
-+  } while (0)
-+#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7
- #define umul_ppmm(w1, w0, u, v) \
-   __asm__ ("multu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v))
- #else
-@@ -1024,7 +1032,16 @@
- #endif /* __mips */
- 
- #if (defined (__mips) && __mips >= 3) && W_TYPE_SIZE == 64
--#if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
-+#if (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4)
-+typedef unsigned int UTItype __attribute__ ((mode (TI)));
-+#define umul_ppmm(w1, w0, u, v) \
-+  do {									\
-+    UTItype _r;							\
-+    _r = (UTItype) u * v;						\
-+    (w1) = _r >> 64;							\
-+    (w0) = (UDItype) _r;						\
-+  } while (0)
-+#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7
- #define umul_ppmm(w1, w0, u, v) \
-   __asm__ ("dmultu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v))
- #else
-diff -ur mpfr-2.4.2.orig/mpfr.h mpfr-2.4.2/mpfr.h
---- mpfr-2.4.2.orig/mpfr.h	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/mpfr.h	2010-03-08 22:28:53.000000000 +0100
-@@ -27,7 +27,7 @@
- #define MPFR_VERSION_MAJOR 2
- #define MPFR_VERSION_MINOR 4
- #define MPFR_VERSION_PATCHLEVEL 2
--#define MPFR_VERSION_STRING "2.4.2"
-+#define MPFR_VERSION_STRING "2.4.2-p3"
- 
- /* Macros dealing with MPFR VERSION */
- #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c))
-diff -ur mpfr-2.4.2.orig/sin_cos.c mpfr-2.4.2/sin_cos.c
---- mpfr-2.4.2.orig/sin_cos.c	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/sin_cos.c	2010-03-08 22:28:53.000000000 +0100
-@@ -82,17 +82,19 @@
-       if (y != x)
-         /* y and x differ, thus we can safely try to compute y first */
-         {
--          MPFR_FAST_COMPUTE_IF_SMALL_INPUT (y, x, -2 * expx, 2, 0, rnd_mode,
--                                            { inexy = _inexact;
--                                              goto small_input; });
-+          MPFR_FAST_COMPUTE_IF_SMALL_INPUT (
-+            y, x, -2 * expx, 2, 0, rnd_mode,
-+            { inexy = _inexact;
-+              goto small_input; });
-           if (0)
-             {
-             small_input:
-               /* we can go here only if we can round sin(x) */
--              MPFR_FAST_COMPUTE_IF_SMALL_INPUT (z, __gmpfr_one, -2 * expx,
--                                                1, 0, rnd_mode,
--                                                { inexz = _inexact;
--                                                  goto end; });
-+              MPFR_FAST_COMPUTE_IF_SMALL_INPUT (
-+                z, __gmpfr_one, -2 * expx, 1, 0, rnd_mode,
-+                { inexz = _inexact;
-+                  MPFR_SAVE_EXPO_UPDATE_FLAGS (expo, __gmpfr_flags);
-+                  goto end; });
-             }
- 
-           /* if we go here, one of the two MPFR_FAST_COMPUTE_IF_SMALL_INPUT
-@@ -101,18 +103,19 @@
-       else /* y and x are the same variable: try to compute z first, which
-               necessarily differs */
-         {
--          MPFR_FAST_COMPUTE_IF_SMALL_INPUT (z, __gmpfr_one, -2 * expx,
--                                            1, 0, rnd_mode,
--                                            { inexz = _inexact;
--                                              goto small_input2; });
-+          MPFR_FAST_COMPUTE_IF_SMALL_INPUT (
-+            z, __gmpfr_one, -2 * expx, 1, 0, rnd_mode,
-+            { inexz = _inexact;
-+              goto small_input2; });
-           if (0)
-             {
-             small_input2:
-               /* we can go here only if we can round cos(x) */
--              MPFR_FAST_COMPUTE_IF_SMALL_INPUT (y, x, -2 * expx, 2, 0,
--                                                rnd_mode,
--                                                { inexy = _inexact;
--                                                  goto end; });
-+              MPFR_FAST_COMPUTE_IF_SMALL_INPUT (
-+                y, x, -2 * expx, 2, 0, rnd_mode,
-+                { inexy = _inexact;
-+                  MPFR_SAVE_EXPO_UPDATE_FLAGS (expo, __gmpfr_flags);
-+                  goto end; });
-             }
-         }
-       m += 2 * (-expx);
-@@ -207,7 +210,6 @@
-   mpfr_clear (xr);
- 
-  end:
--  /* FIXME: update the underflow flag if need be. */
-   MPFR_SAVE_EXPO_FREE (expo);
-   mpfr_check_range (y, inexy, rnd_mode);
-   mpfr_check_range (z, inexz, rnd_mode);
-diff -ur mpfr-2.4.2.orig/tests/tsin_cos.c mpfr-2.4.2/tests/tsin_cos.c
---- mpfr-2.4.2.orig/tests/tsin_cos.c	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/tests/tsin_cos.c	2010-03-08 22:28:53.000000000 +0100
-@@ -382,23 +382,56 @@
- consistency (void)
- {
-   mpfr_t x, s1, s2, c1, c2;
-+  mp_exp_t emin, emax;
-   mp_rnd_t rnd;
-+  unsigned int flags_sin, flags_cos, flags, flags_before, flags_ref;
-+  int inex_sin, inex_cos, inex, inex_ref;
-   int i;
- 
-+  emin = mpfr_get_emin ();
-+  emax = mpfr_get_emax ();
-+
-   for (i = 0; i <= 10000; i++)
-     {
-       mpfr_init2 (x, MPFR_PREC_MIN + (randlimb () % 8));
-       mpfr_inits2 (MPFR_PREC_MIN + (randlimb () % 8), s1, s2, c1, c2,
-                    (mpfr_ptr) 0);
--      tests_default_random (x, 256, -5, 50);
--      rnd = RND_RAND ();
--      mpfr_sin (s1, x, rnd);
--      mpfr_cos (c1, x, rnd);
--      mpfr_sin_cos (s2, c2, x, rnd);
--      if (!(mpfr_equal_p (s1, s2) && mpfr_equal_p (c1, c2)))
-+      if (i < 8 * GMP_RND_MAX)
-+        {
-+          int j = i / GMP_RND_MAX;
-+          if (j & 1)
-+            mpfr_set_emin (MPFR_EMIN_MIN);
-+          mpfr_set_si (x, (j & 2) ? 1 : -1, GMP_RNDN);
-+          mpfr_set_exp (x, mpfr_get_emin ());
-+          rnd = (mpfr_rnd_t) (i % GMP_RND_MAX);
-+          flags_before = 0;
-+          if (j & 4)
-+            mpfr_set_emax (-17);
-+        }
-+      else
-+        {
-+          tests_default_random (x, 256, -5, 50);
-+          rnd = RND_RAND ();
-+          flags_before = (randlimb () & 1) ?
-+            (unsigned int) (MPFR_FLAGS_ALL ^ MPFR_FLAGS_ERANGE) :
-+            (unsigned int) 0;
-+        }
-+      __gmpfr_flags = flags_before;
-+      inex_sin = mpfr_sin (s1, x, rnd);
-+      flags_sin = __gmpfr_flags;
-+      __gmpfr_flags = flags_before;
-+      inex_cos = mpfr_cos (c1, x, rnd);
-+      flags_cos = __gmpfr_flags;
-+      __gmpfr_flags = flags_before;
-+      inex = !!mpfr_sin_cos (s2, c2, x, rnd);
-+      flags = __gmpfr_flags;
-+      inex_ref = inex_sin || inex_cos;
-+      flags_ref = flags_sin | flags_cos;
-+      if (!(mpfr_equal_p (s1, s2) && mpfr_equal_p (c1, c2)) ||
-+          inex != inex_ref || flags != flags_ref)
-         {
--          printf ("mpfr_sin_cos and mpfr_sin/mpfr_cos disagree on %s,\nx = ",
--                  mpfr_print_rnd_mode (rnd));
-+          printf ("mpfr_sin_cos and mpfr_sin/mpfr_cos disagree on %s,"
-+                  " i = %d\nx = ", mpfr_print_rnd_mode (rnd), i);
-           mpfr_dump (x);
-           printf ("s1 = ");
-           mpfr_dump (s1);
-@@ -408,9 +441,16 @@
-           mpfr_dump (c1);
-           printf ("c2 = ");
-           mpfr_dump (c2);
-+          printf ("inex_sin = %d, inex_cos = %d, inex = %d (expected %d)\n",
-+                  inex_sin, inex_cos, inex, inex_ref);
-+          printf ("flags_sin = 0x%x, flags_cos = 0x%x, "
-+                  "flags = 0x%x (expected 0x%x)\n",
-+                  flags_sin, flags_cos, flags, flags_ref);
-           exit (1);
-         }
-       mpfr_clears (x, s1, s2, c1, c2, (mpfr_ptr) 0);
-+      mpfr_set_emin (emin);
-+      mpfr_set_emax (emax);
-     }
- }
- 
-diff -ur mpfr-2.4.2.orig/version.c mpfr-2.4.2/version.c
---- mpfr-2.4.2.orig/version.c	2010-03-08 22:28:46.000000000 +0100
-+++ mpfr-2.4.2/version.c	2010-03-08 22:28:53.000000000 +0100
-@@ -25,5 +25,5 @@
- const char *
- mpfr_get_version (void)
- {
--  return "2.4.2";
-+  return "2.4.2-p3";
- }



From gerrit at coreboot.org  Thu Oct 13 01:10:48 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 01:10:48 +0200
Subject: [coreboot] Patch merged into coreboot/master: eae1696 mptable: Get
	rid of fixup_virtual_wire
References: <Icad8a063380bf4726be7cebb414d13b574112b14+0@gerrit.coreboot.org>
Message-ID: <E1RE7wn-0000xi-0p@ra.coresystems.de>

the following patch was just integrated into master:
commit eae1696809d6e6834d08ef22aa08c8f200870c59
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Oct 7 22:41:07 2011 +0200

    mptable: Get rid of fixup_virtual_wire
    
    As stated in some code files, fixup_virtual_wire was established
    to avoid touching 200 invocations of the mptable code.
    
    Let Coccinelle do it:
      @@
      type T;
      identifier v;
      @@
      -void fixup_virtual_wire(T v)
      -{ ... }
    
      @@
      expression A;
      identifier v;
      @@
      -v = smp_write_floating_table(A);
      +v = smp_write_floating_table(A, 0);
    
      @@
      expression A;
      identifier v;
      @@
      -v = smp_write_floating_table(A, 0);
      -fixup_virtual_wire(v);
      +v = smp_write_floating_table(A, 1);
    
    Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/245 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 01:11:12 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 01:11:12 +0200
Subject: [coreboot] Patch merged into coreboot/master: 3322f8f mptable:
	Refactor mptable generation some more
References: <Ib2270d800bdd486c5eb49b328544d36bd2298c9e+0@gerrit.coreboot.org>
Message-ID: <E1RE7xA-0001cC-99@ra.coresystems.de>

the following patch was just integrated into master:
commit 3322f8f5a5ce35ecc5f03ca56f587f1b85b04e78
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Oct 7 23:01:55 2011 +0200

    mptable: Refactor mptable generation some more
    
    The last couple of lines of every mptable function were mostly
    identical. Refactor into common code, a new function mptable_finalize.
    
    Coccinelle script:
      @@
      identifier mc;
      @@
      (
      -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
      -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
      -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
      -return smp_next_mpe_entry(mc);
      +return mptable_finalize(mc);
      |
      -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
      -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
      -return smp_next_mpe_entry(mc);
      +return mptable_finalize(mc);
      )
    
    Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/246 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 01:20:20 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Thu, 13 Oct 2011 01:20:20 +0200
Subject: [coreboot] New patch to review for coreboot: 2a52406 Use default
	table creator macro for all SSDTs
References: <I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e+0@gerrit.coreboot.org>
Message-ID: <I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/262

-gerrit

commit 2a5240633d7e9b768f959b24afb2ab199ed2632f
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 01:18:29 2011 +0200

    Use default table creator macro for all SSDTs
    
    Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/mainboard/amd/dbm690t/acpi_tables.c           |    2 +-
 src/mainboard/amd/mahogany/acpi_tables.c          |    2 +-
 src/mainboard/amd/pistachio/acpi_tables.c         |    2 +-
 src/mainboard/amd/serengeti_cheetah/acpi_tables.c |    2 +-
 src/mainboard/asrock/939a785gmh/acpi_tables.c     |    2 +-
 src/mainboard/asus/a8v-e_se/acpi_tables.c         |    2 +-
 src/mainboard/asus/m2v-mx_se/acpi_tables.c        |    2 +-
 src/mainboard/asus/m2v/acpi_tables.c              |    2 +-
 src/mainboard/gigabyte/m57sli/acpi_tables.c       |    2 +-
 src/mainboard/ibase/mb899/acpi_tables.c           |    4 ++--
 src/mainboard/intel/d945gclf/acpi_tables.c        |    4 ++--
 src/mainboard/iwave/iWRainbowG6/acpi_tables.c     |    4 ++--
 src/mainboard/iwill/dk8_htx/acpi_tables.c         |    2 +-
 src/mainboard/kontron/986lcd-m/acpi_tables.c      |    4 ++--
 src/mainboard/kontron/kt690/acpi_tables.c         |    2 +-
 src/mainboard/lenovo/t60/acpi_tables.c            |    4 ++--
 src/mainboard/lenovo/x60/acpi_tables.c            |    4 ++--
 src/mainboard/msi/ms7135/acpi_tables.c            |    2 +-
 src/mainboard/msi/ms9652_fam10/acpi_tables.c      |    2 +-
 src/mainboard/roda/rk886ex/acpi_tables.c          |    4 ++--
 src/mainboard/siemens/sitemp_g1p1/acpi_tables.c   |    2 +-
 src/mainboard/technexion/tim5690/acpi_tables.c    |    2 +-
 src/mainboard/technexion/tim8690/acpi_tables.c    |    2 +-
 src/mainboard/tyan/s2891/acpi_tables.c            |    2 +-
 src/mainboard/tyan/s2892/acpi_tables.c            |    2 +-
 src/mainboard/tyan/s2895/acpi_tables.c            |    2 +-
 src/mainboard/via/vt8454c/acpi_tables.c           |    2 +-
 src/southbridge/intel/i82371eb/acpi_tables.c      |    2 +-
 28 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/src/mainboard/amd/dbm690t/acpi_tables.c b/src/mainboard/amd/dbm690t/acpi_tables.c
index f9fb416..9f91ee8 100644
--- a/src/mainboard/amd/dbm690t/acpi_tables.c
+++ b/src/mainboard/amd/dbm690t/acpi_tables.c
@@ -170,7 +170,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/amd/mahogany/acpi_tables.c b/src/mainboard/amd/mahogany/acpi_tables.c
index ebd2546..df7a48b 100644
--- a/src/mainboard/amd/mahogany/acpi_tables.c
+++ b/src/mainboard/amd/mahogany/acpi_tables.c
@@ -181,7 +181,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c
index 55db923..3f44b9d 100644
--- a/src/mainboard/amd/pistachio/acpi_tables.c
+++ b/src/mainboard/amd/pistachio/acpi_tables.c
@@ -171,7 +171,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
index 7a0478d..193f6c6 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
@@ -247,7 +247,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/asrock/939a785gmh/acpi_tables.c b/src/mainboard/asrock/939a785gmh/acpi_tables.c
index da6571d..c0d8691 100644
--- a/src/mainboard/asrock/939a785gmh/acpi_tables.c
+++ b/src/mainboard/asrock/939a785gmh/acpi_tables.c
@@ -160,7 +160,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c
index e08b305..218f3bb 100644
--- a/src/mainboard/asus/a8v-e_se/acpi_tables.c
+++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c
@@ -166,7 +166,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
index 73e3768..3cdde41 100644
--- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c
+++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
@@ -187,7 +187,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/asus/m2v/acpi_tables.c b/src/mainboard/asus/m2v/acpi_tables.c
index d8a5258..73f82d8 100644
--- a/src/mainboard/asus/m2v/acpi_tables.c
+++ b/src/mainboard/asus/m2v/acpi_tables.c
@@ -188,7 +188,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c
index 2e2e6a0..513e478 100644
--- a/src/mainboard/gigabyte/m57sli/acpi_tables.c
+++ b/src/mainboard/gigabyte/m57sli/acpi_tables.c
@@ -194,7 +194,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c
index dbe1e91..16ee302 100644
--- a/src/mainboard/ibase/mb899/acpi_tables.c
+++ b/src/mainboard/ibase/mb899/acpi_tables.c
@@ -65,7 +65,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 	/* fill out header fields */
 	memcpy(header->signature, "HPET", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
@@ -251,7 +251,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 	ALIGN_CURRENT;
diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c
index f7e13e9..0435bdd 100644
--- a/src/mainboard/intel/d945gclf/acpi_tables.c
+++ b/src/mainboard/intel/d945gclf/acpi_tables.c
@@ -54,7 +54,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 	/* fill out header fields */
 	memcpy(header->signature, "HPET", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
@@ -239,7 +239,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
index 8c8e788..a30479b 100644
--- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
+++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
@@ -66,7 +66,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t *hpet)
 	/* Fill out header fields. */
 	memcpy(header->signature, "HPET", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
@@ -257,7 +257,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *) current;
-	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 	ALIGN_CURRENT;
diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c
index 400dc0e..599327e 100644
--- a/src/mainboard/iwill/dk8_htx/acpi_tables.c
+++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c
@@ -233,7 +233,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c
index dbe1e91..16ee302 100644
--- a/src/mainboard/kontron/986lcd-m/acpi_tables.c
+++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c
@@ -65,7 +65,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 	/* fill out header fields */
 	memcpy(header->signature, "HPET", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
@@ -251,7 +251,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 	ALIGN_CURRENT;
diff --git a/src/mainboard/kontron/kt690/acpi_tables.c b/src/mainboard/kontron/kt690/acpi_tables.c
index b3db6aa..787a3e5 100644
--- a/src/mainboard/kontron/kt690/acpi_tables.c
+++ b/src/mainboard/kontron/kt690/acpi_tables.c
@@ -149,7 +149,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c
index fa135a6..412ec47 100644
--- a/src/mainboard/lenovo/t60/acpi_tables.c
+++ b/src/mainboard/lenovo/t60/acpi_tables.c
@@ -66,7 +66,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 	/* fill out header fields */
 	memcpy(header->signature, "HPET", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
@@ -287,7 +287,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 	ALIGN_CURRENT;
diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c
index fa135a6..412ec47 100644
--- a/src/mainboard/lenovo/x60/acpi_tables.c
+++ b/src/mainboard/lenovo/x60/acpi_tables.c
@@ -66,7 +66,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 	/* fill out header fields */
 	memcpy(header->signature, "HPET", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
@@ -287,7 +287,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 	ALIGN_CURRENT;
diff --git a/src/mainboard/msi/ms7135/acpi_tables.c b/src/mainboard/msi/ms7135/acpi_tables.c
index 5d5b288..0f81cc6 100644
--- a/src/mainboard/msi/ms7135/acpi_tables.c
+++ b/src/mainboard/msi/ms7135/acpi_tables.c
@@ -269,7 +269,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	current = ALIGN(current, 16);
 	ssdt = (acpi_header_t *)current;
 	printk(BIOS_DEBUG, "ACPI:    * SSDT @ %p\n", ssdt);
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/msi/ms9652_fam10/acpi_tables.c b/src/mainboard/msi/ms9652_fam10/acpi_tables.c
index 08a5a25..25be32a 100644
--- a/src/mainboard/msi/ms9652_fam10/acpi_tables.c
+++ b/src/mainboard/msi/ms9652_fam10/acpi_tables.c
@@ -198,7 +198,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c
index fa135a6..412ec47 100644
--- a/src/mainboard/roda/rk886ex/acpi_tables.c
+++ b/src/mainboard/roda/rk886ex/acpi_tables.c
@@ -66,7 +66,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 	/* fill out header fields */
 	memcpy(header->signature, "HPET", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
@@ -287,7 +287,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 	ALIGN_CURRENT;
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
index 518fb7f..fd731f9 100644
--- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
+++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
@@ -252,7 +252,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* SSDT */
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);	
 	
diff --git a/src/mainboard/technexion/tim5690/acpi_tables.c b/src/mainboard/technexion/tim5690/acpi_tables.c
index b3db6aa..787a3e5 100644
--- a/src/mainboard/technexion/tim5690/acpi_tables.c
+++ b/src/mainboard/technexion/tim5690/acpi_tables.c
@@ -149,7 +149,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/technexion/tim8690/acpi_tables.c b/src/mainboard/technexion/tim8690/acpi_tables.c
index b3db6aa..787a3e5 100644
--- a/src/mainboard/technexion/tim8690/acpi_tables.c
+++ b/src/mainboard/technexion/tim8690/acpi_tables.c
@@ -149,7 +149,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/tyan/s2891/acpi_tables.c b/src/mainboard/tyan/s2891/acpi_tables.c
index 62c2b54..403cca5 100644
--- a/src/mainboard/tyan/s2891/acpi_tables.c
+++ b/src/mainboard/tyan/s2891/acpi_tables.c
@@ -186,7 +186,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	current = ALIGN(current, 16);
 	ssdt = (acpi_header_t *)current;
 	printk(BIOS_DEBUG, "ACPI:    * SSDT @ %p\n", ssdt);
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/tyan/s2892/acpi_tables.c b/src/mainboard/tyan/s2892/acpi_tables.c
index 62c2b54..403cca5 100644
--- a/src/mainboard/tyan/s2892/acpi_tables.c
+++ b/src/mainboard/tyan/s2892/acpi_tables.c
@@ -186,7 +186,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	current = ALIGN(current, 16);
 	ssdt = (acpi_header_t *)current;
 	printk(BIOS_DEBUG, "ACPI:    * SSDT @ %p\n", ssdt);
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c
index 04fa55c..1f2f5b1 100644
--- a/src/mainboard/tyan/s2895/acpi_tables.c
+++ b/src/mainboard/tyan/s2895/acpi_tables.c
@@ -211,7 +211,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	current = ALIGN(current, 16);
 	ssdt = (acpi_header_t *)current;
 	printk(BIOS_DEBUG, "ACPI:    * SSDT @ %p\n", ssdt);
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
diff --git a/src/mainboard/via/vt8454c/acpi_tables.c b/src/mainboard/via/vt8454c/acpi_tables.c
index 03bacc3..4b18b69 100644
--- a/src/mainboard/via/vt8454c/acpi_tables.c
+++ b/src/mainboard/via/vt8454c/acpi_tables.c
@@ -63,7 +63,7 @@ static void acpi_create_via_hpet(acpi_hpet_t * hpet)
 	/* fill out header fields */
 	memcpy(header->signature, "HPET", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 2173a3d..84bb5b7 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -169,7 +169,7 @@ unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start)
 
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 



From gerrit at coreboot.org  Thu Oct 13 01:09:52 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 01:09:52 +0200
Subject: [coreboot] Patch merged into coreboot/master: 8125150 Make Asus
	A8V-E SE better ACPI citizen.
References: <Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3+0@gerrit.coreboot.org>
Message-ID: <E1RE7vs-0006uq-3b@ra.coresystems.de>

the following patch was just integrated into master:
commit 8125150119b0bcbf4ce588dc5c731365bbd362e4
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Wed Oct 12 22:11:40 2011 +0200

    Make Asus A8V-E SE better ACPI citizen.
    
    Use the SSDT autogen infrastructure to support the automatic reserved resources,
    automatic P-state generation and automatic _CRS PCI0 method.
    
    Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

See http://review.coreboot.org/251 for details.

-gerrit



From stefan.reinauer at coreboot.org  Thu Oct 13 01:47:07 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Thu, 13 Oct 2011 01:47:07 +0200
Subject: [coreboot] missing read resources
In-Reply-To: <CAOXdWGvommz7x-HnMhHA0M+ULaTEpTYKh32od8Bk9WBDte8RNw@mail.gmail.com>
References: <4E94A372.3010806@lysator.liu.se>
	<CAOXdWGvommz7x-HnMhHA0M+ULaTEpTYKh32od8Bk9WBDte8RNw@mail.gmail.com>
Message-ID: <20111012234706.GA28251@coreboot.org>

* Myles Watson <mylesgw at gmail.com> [111012 08:19]:
> On Tue, Oct 11, 2011 at 10:13 PM, Oskar Enoksson <enok at lysator.liu.se> wrote:
> > I get the following warnings:
> >
> > APIC: 00 missing read_resources
> > APIC: 01 missing read_resources
> > APIC: 02 missing read_resources
> > APIC: 03 missing read_resources
> > I2C: 01:08 missing read_resources
> > I2C: 04:50 missing read_resources
> > I2C: 04:51 missing read_resources
> > I2C: 04:52 missing read_resources
> > I2C: 04:53 missing read_resources
> > I2C: 05:50 missing read_resources
> > I2C: 05:51 missing read_resources
> > I2C: 05:52 missing read_resources
> > I2C: 05:53 missing read_resources
> > I2C: 03:69 missing read_resources
> >
> > What does it mean? Should I do something about it in devicetree.cb?
> 
> It just means that I2C and APIC devices don't have resources to read,
> and the warning message was less annoying than implementing empty
> functions that might get copied to a device that had resources.
> 
> It can be safely ignored for those two classes of devices.

Should it be BIOS_SPEW than instead of BIOS_ERR?




From gerrit at coreboot.org  Thu Oct 13 01:10:34 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 01:10:34 +0200
Subject: [coreboot] Patch merged into coreboot/master: 51caef5 mptable:
	Refactor lintsrc generation
References: <I97421f820cd039f5fd753cb0da5c1cca68819bb4+0@gerrit.coreboot.org>
Message-ID: <E1RE7wY-0000Ka-4W@ra.coresystems.de>

the following patch was just integrated into master:
commit 51caef5bb69445b65f4d7e468abe06bdb95de7b9
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Oct 7 21:42:52 2011 +0200

    mptable: Refactor lintsrc generation
    
    We copied pretty much the same code for generating mptable entries for
    local interrupts (with some notable exceptions).
    This change moves these lines into a generic function "mptable_lintsrc"
    and makes use of it in many places.
    
    The remaining uses of smp_write_lintsrc should be reviewed and replaced
    by mptable_lintsrc calls where possible, and smp_write_lintsrc made static.
    
    This patch was generated using Coccinelle:
      @@
      expression mc;
      expression isa_bus;
      @@
      -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
      -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
      +mptable_lintsrc(mc, isa_bus);
    
      @@
      expression mc;
      expression isa_bus;
      @@
      -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
      -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
      +mptable_lintsrc(mc, isa_bus);
    
      @m@
      identifier mc;
      expression BUS;
      @@
      -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin));
      ...
      -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
      -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
      +mptable_lintsrc(mc, BUS);
    
    Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/244 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 10:16:04 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Thu, 13 Oct 2011 10:16:04 +0200
Subject: [coreboot] Patch set updated for coreboot: 160ab12
	siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
References: <I4d2a10c9b45306ac6e6026a31765d3b912fd855c+0@gerrit.coreboot.org>
Message-ID: <I4d2a10c9b45306ac6e6026a31765d3b912fd855c+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/242

-gerrit

commit 160ab128f8ea5ca700a4f8ec868e2bbeadbb09b5
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Oct 6 14:34:22 2011 +0200

    siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
    
    Each variable is essentially unused or incorrect.
    
    Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c |   23 +---------------------
 src/mainboard/siemens/sitemp_g1p1/irq_tables.c   |    1 -
 src/mainboard/siemens/sitemp_g1p1/mptable.c      |   12 +++-------
 3 files changed, 5 insertions(+), 31 deletions(-)

diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
index 24b9f28..2b0fca7 100644
--- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
+++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
@@ -32,7 +32,6 @@
 /* Global variables for MB layouts and these will be shared by irqtable mptable
 * and acpi_tables busnum is default.
 */
-u8 bus_isa;
 u8 bus_rs690[8];
 u8 bus_sb600[2];
 u32 apicid_sb600;
@@ -54,8 +53,6 @@ u32 hcdnx[] = {
 	0x20202020,
 };
 
-u32 bus_type[256];
-
 u32 sbdn_rs690;
 u32 sbdn_sb600;
 
@@ -67,7 +64,7 @@ void get_bus_conf(void)
 {
 	u32 apicid_base;
 	device_t dev;
-	int i, j;
+	int i;
 
 	if (get_bus_conf_done == 1)
 		return;		/* do it only once */
@@ -92,25 +89,13 @@ void get_bus_conf(void)
 		bus_rs690[i] = 0;
 	}
 
-	for (i = 0; i < 256; i++) {
-		bus_type[i] = 0; /* default ISA bus. */
-	}
-
-	bus_type[0] = 1;	/* pci */
-
 	bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 	bus_sb600[0] = bus_rs690[0];
 
-	bus_type[bus_rs690[0]] = 1;
-
 	/* sb600 */
 	dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
 	if (dev) {
 		bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-		bus_isa++;
-		for (j = bus_sb600[1]; j < bus_isa; j++)
-			bus_type[j] = 1;
 	}
 
 	/* rs690 */
@@ -118,16 +103,10 @@ void get_bus_conf(void)
 		dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
 		if (dev) {
 			bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-			if(255 != bus_rs690[i]) {
-				bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-				bus_isa++;
-				bus_type[bus_rs690[i]] = 1; /* PCI bus. */
-			}
 		}
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-	bus_isa = 10;
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(1);
 #else
diff --git a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
index 63b532d..b2a9668 100644
--- a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
+++ b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c
@@ -68,7 +68,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 	pirq_info->slot = slot;
 	pirq_info->rfu = rfu;
 }
-extern u8 bus_isa;
 extern u8 bus_rs690[8];
 extern u8 bus_sb600[2];
 extern unsigned long sbdn_sb600;
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index 4180c36..958bfc1 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -26,13 +26,11 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern u8 bus_isa;
 extern u8 bus_rs690[8];
 extern u8 bus_sb600[2];
 
 extern u32 apicid_sb600;
 
-extern u32 bus_type[256];
 extern u32 sbdn_rs690;
 extern u32 sbdn_sb600;
 
@@ -46,12 +44,9 @@ static void *smp_write_config_table(void *v)
 	smp_write_processors(mc);
 
 	get_bus_conf();
-	printk(BIOS_DEBUG, "%s: bus_isa=%d, apic_id=0x%x\n", __func__, bus_isa, apicid_sb600);
+	printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600);
 
 	mptable_write_buses(mc, NULL, &isa_bus);
-	if (isa_bus != bus_isa) {
-		printk(BIOS_ERR, "ISA bus numbering schemes differ! Please fix mptable.c\n");
-	}
 	/* I/O APICs:   APIC ID Version State   Address */
 	{
 		device_t dev;
@@ -63,9 +58,10 @@ static void *smp_write_config_table(void *v)
 			smp_write_ioapic(mc, apicid_sb600, 0x20, res->base);
 		}
 	}
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
+	mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0);
+
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	mptable_lintsrc(mc, bus_isa);
+	mptable_lintsrc(mc, isa_bus);
 
 	/* Compute the checksums */
 	return mptable_finalize(mc);



From gerrit at coreboot.org  Thu Oct 13 10:16:05 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Thu, 13 Oct 2011 10:16:05 +0200
Subject: [coreboot] Patch set updated for coreboot: 5bcd9a7
	siemens/sitemp_g1p1: Don't mess with virtual wire settings
References: <I4ddd25fef57bed64877959ca96cca68170042bca+0@gerrit.coreboot.org>
Message-ID: <I4ddd25fef57bed64877959ca96cca68170042bca+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/243

-gerrit

commit 5bcd9a7d036de9942eddbe0dde3b5bf939a0bc95
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Oct 6 15:24:08 2011 +0200

    siemens/sitemp_g1p1: Don't mess with virtual wire settings
    
    That function broke SMP on Linux 2.4, now it works.
    
    Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/mainboard/siemens/sitemp_g1p1/mptable.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index 958bfc1..0e18fb3 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -70,6 +70,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr, 1);
+	v = smp_write_floating_table(addr, 0);
 	return (unsigned long)smp_write_config_table(v);
 }



From gerrit at coreboot.org  Thu Oct 13 10:16:05 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Thu, 13 Oct 2011 10:16:05 +0200
Subject: [coreboot] Patch set updated for coreboot: 762b7b6 amd/sb600:
	Enable COM2 at all times in early setup
References: <I886f98b715c1f384c8693f2977671ff15897b5a5+0@gerrit.coreboot.org>
Message-ID: <I886f98b715c1f384c8693f2977671ff15897b5a5+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/241

-gerrit

commit 762b7b6c00cdee44eebdd7a8ffeea38404c903a6
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Fri Oct 7 14:43:27 2011 +0200

    amd/sb600: Enable COM2 at all times in early setup
    
    Otherwise with a coreboot log on COM2 (which doesn't work) the boot
    process takes eons.
    
    Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/southbridge/amd/sb600/early_setup.c |    9 ++++-----
 1 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index 838ea31..5ffd3d8 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -53,11 +53,11 @@ static u8 get_sb600_revision(void)
 
 /***************************************
 * Legacy devices are mapped to LPC space.
-*	Serial port 0
+*	Serial port 0, 1
 *	KBC Port
 *	ACPI Micro-controller port
 *	This function does not change port 0x80 decoding.
-*	Console output through any port besides 0x3f8 is unsupported.
+*	Console output through any port besides 0x2f8/0x3f8 is unsupported.
 *	If you use FWH ROMs, you have to setup IDSEL.
 * Reviewed-by: Carl-Daniel Hailfinger
 * Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1
@@ -84,10 +84,9 @@ static void sb600_lpc_init(void)
 	pci_write_config32(dev, 0x64, reg32);
 
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);	/* LPC Controller */
-	/* Decode port 0x3f8-0x3ff (Serial 0) */
-	// XXX Serial port decode on LPC is hardcoded to 0x3f8
+	/* Decode port 0x3f8-0x3ff (Serial 0), 0x2f8-0x2ff (Serial 1) */
 	reg8 = pci_read_config8(dev, 0x44);
-	reg8 |= 1 << 6;
+	reg8 |= (1 << 6) | (1 << 7);
 	pci_write_config8(dev, 0x44, reg8);
 
 	/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/



From mylesgw at gmail.com  Thu Oct 13 09:41:11 2011
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 13 Oct 2011 09:41:11 +0200
Subject: [coreboot] missing read resources
In-Reply-To: <20111012234706.GA28251@coreboot.org>
References: <4E94A372.3010806@lysator.liu.se>
	<CAOXdWGvommz7x-HnMhHA0M+ULaTEpTYKh32od8Bk9WBDte8RNw@mail.gmail.com>
	<20111012234706.GA28251@coreboot.org>
Message-ID: <CAOXdWGv8HaFCcaGUnKo8AZ3pGhyiwyHZg5B69263Asf50=6TqA@mail.gmail.com>

On Thu, Oct 13, 2011 at 1:47 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Myles Watson <mylesgw at gmail.com> [111012 08:19]:
>> On Tue, Oct 11, 2011 at 10:13 PM, Oskar Enoksson <enok at lysator.liu.se> wrote:
>> > I get the following warnings:
>> >
>> > APIC: 00 missing read_resources
>> > APIC: 01 missing read_resources
>> > APIC: 02 missing read_resources
>> > APIC: 03 missing read_resources
>> > I2C: 01:08 missing read_resources
>> > I2C: 04:50 missing read_resources
>> > I2C: 04:51 missing read_resources
>> > I2C: 04:52 missing read_resources
>> > I2C: 04:53 missing read_resources
>> > I2C: 05:50 missing read_resources
>> > I2C: 05:51 missing read_resources
>> > I2C: 05:52 missing read_resources
>> > I2C: 05:53 missing read_resources
>> > I2C: 03:69 missing read_resources
>> >
>> > What does it mean? Should I do something about it in devicetree.cb?
>>
>> It just means that I2C and APIC devices don't have resources to read,
>> and the warning message was less annoying than implementing empty
>> functions that might get copied to a device that had resources.
>>
>> It can be safely ignored for those two classes of devices.
>
> Should it be BIOS_SPEW than instead of BIOS_ERR?

It should be for those devices, but it is an error for devices that
should have the function.  That was the reason we left it.  I think
putting in a read_no_resources() function for those devices would be
the cleanest solution.  The downside was that people implementing a
new device might put in a dummy function to silence the error and
never figure out why their device didn't work.  I don't think we can
protect against things like that, though.

Thanks,
Myles



From gerrit at coreboot.org  Thu Oct 13 11:04:37 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 11:04:37 +0200
Subject: [coreboot] Patch merged into coreboot/master: 762b7b6 amd/sb600:
	Enable COM2 at all times in early setup
References: <I886f98b715c1f384c8693f2977671ff15897b5a5+0@gerrit.coreboot.org>
Message-ID: <E1REHDR-0001CZ-MG@ra.coresystems.de>

the following patch was just integrated into master:
commit 762b7b6c00cdee44eebdd7a8ffeea38404c903a6
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Fri Oct 7 14:43:27 2011 +0200

    amd/sb600: Enable COM2 at all times in early setup
    
    Otherwise with a coreboot log on COM2 (which doesn't work) the boot
    process takes eons.
    
    Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/241 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 11:07:24 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 11:07:24 +0200
Subject: [coreboot] Patch merged into coreboot/master: 160ab12
	siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
References: <I4d2a10c9b45306ac6e6026a31765d3b912fd855c+0@gerrit.coreboot.org>
Message-ID: <E1REHG9-0002ux-04@ra.coresystems.de>

the following patch was just integrated into master:
commit 160ab128f8ea5ca700a4f8ec868e2bbeadbb09b5
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Oct 6 14:34:22 2011 +0200

    siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
    
    Each variable is essentially unused or incorrect.
    
    Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/242 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 11:07:37 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 11:07:37 +0200
Subject: [coreboot] Patch merged into coreboot/master: 5bcd9a7
	siemens/sitemp_g1p1: Don't mess with virtual wire settings
References: <I4ddd25fef57bed64877959ca96cca68170042bca+0@gerrit.coreboot.org>
Message-ID: <E1REHGL-0003WL-JT@ra.coresystems.de>

the following patch was just integrated into master:
commit 5bcd9a7d036de9942eddbe0dde3b5bf939a0bc95
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Oct 6 15:24:08 2011 +0200

    siemens/sitemp_g1p1: Don't mess with virtual wire settings
    
    That function broke SMP on Linux 2.4, now it works.
    
    Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/243 for details.

-gerrit



From Kerry.She at amd.com  Thu Oct 13 11:19:46 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Thu, 13 Oct 2011 17:19:46 +0800
Subject: [coreboot] how to delete symbol link created at compile time
Message-ID: <F53A09371FB723428826B442A4B20A4107BCBF12@sbjgexmb1.amd.com>

Hello,

 

Some mainboard support more than one family of CPUs with same socket
type,

Such as SuperMicro/h8scm:

http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.c
fm

 

My implementation is the mainboard CPU type can be configured as
family10 or family15 CPU.

In order to eliminate the duplicated code, both configuration shares
most of the platform code,

but some code can't be shared between different family of CPUs.

Take devicetree.cb as an example, 

I have created 2 devicetree file :

devicetree_f15.cb for platform with family 15 CPU 

devicetree_f10.cb  for platform with family 10 CPU

 

I changed the makefile to create a symbol link "devicetree.cb" link to
devicetree_f10.cb or devicetree_f15.cb at compile time.

The problem is that I can't delete the symbol link when make
clean/distclean.

 

I found that make clean/distclean will not traverse the src/ directory.

How can I get this symbol link removed when doing a make clean.

Any other suggestion is welcome.

Regards, 
Kerry Sheh < kerry.she at amd.com>
Tel:  86-10-6280-1415 
Mobile:  86 - 152 1018 2083 

 

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From gerrit at coreboot.org  Thu Oct 13 14:20:13 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 14:20:13 +0200
Subject: [coreboot] Patch merged into coreboot/master: b130550 Fix romstage
	creation with gcc 4.6 and CAR targets
References: <I7f24c987433cc5886dde2af27498d3331cbda303+0@gerrit.coreboot.org>
Message-ID: <E1REKGj-0003Tm-R3@ra.coresystems.de>

the following patch was just integrated into master:
commit b1305505c57e4a4c34cf7f11b7028bf52dc8fd2a
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 12:54:08 2011 -0700

    Fix romstage creation with gcc 4.6 and CAR targets
    
    newer gcc versions generate ".section .text" instead of just ".text"
    in their assembler output. This patch makes sure that we don't end up
    with a superfluous ".section" that makes the build fail.
    
    Add -Wno-unused-but-set-variable to CFLAGS if the flag exists.
    
    Change-Id: I7f24c987433cc5886dde2af27498d3331cbda303
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/252 for details.

-gerrit



From wmkamp at datakamp.de  Thu Oct 13 15:56:48 2011
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Thu, 13 Oct 2011 15:56:48 +0200
Subject: [coreboot] usb boot issue
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E208AB0C7849@DATAKAMPONE.datakamp2008.local>



Hi,

is there any solution for the usb boot issue of the AMD SB800 Persimmon platform
with SeaBIOS 1.6.3 and actual Coreboot version?

Wolfgang


Email: wmkamp at datakamp.de<mailto:wmkamp at datakamp.de>
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From gerrit at coreboot.org  Thu Oct 13 19:59:45 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 19:59:45 +0200
Subject: [coreboot] Patch merged into coreboot/master: 2a52406 Use default
	table creator macro for all SSDTs
References: <I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e+0@gerrit.coreboot.org>
Message-ID: <E1REPZJ-0000Ce-Ux@ra.coresystems.de>

the following patch was just integrated into master:
commit 2a5240633d7e9b768f959b24afb2ab199ed2632f
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 01:18:29 2011 +0200

    Use default table creator macro for all SSDTs
    
    Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/262 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 20:00:00 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 20:00:00 +0200
Subject: [coreboot] Patch merged into coreboot/master: 7c934a0 Update
	"STABLE" SeaBIOS selection to release 1.6.3
References: <Ie3a4d8f2624e0aa85e48ca09da53474c085838db+0@gerrit.coreboot.org>
Message-ID: <E1REPZZ-0000J9-0X@ra.coresystems.de>

the following patch was just integrated into master:
commit 7c934a0665195ffb523cdc05366492e7acfb0ff0
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 14:05:49 2011 -0700

    Update "STABLE" SeaBIOS selection to release 1.6.3
    
    1.6.3 has a lot of benefits over the previous version, the two
    most important being:
     - working AHCI support
     - compiles with gcc 4.6.x
    
    Change-Id: Ie3a4d8f2624e0aa85e48ca09da53474c085838db
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/253 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 20:00:24 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 20:00:24 +0200
Subject: [coreboot] Patch merged into coreboot/master: b49e5b5 Enable/fix
	compilation of i8254 code in ram stage.
References: <I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd+0@gerrit.coreboot.org>
Message-ID: <E1REPZw-0000e7-8v@ra.coresystems.de>

the following patch was just integrated into master:
commit b49e5b5bb66a9194728471ed7c04badf5897fb46
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Sep 27 16:26:05 2011 -0700

    Enable/fix compilation of i8254 code in ram stage.
    
    Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/254 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 20:00:39 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 20:00:39 +0200
Subject: [coreboot] Patch merged into coreboot/master: 38860f7 Refactor
	option rom initialization code in coreboot.
References: <Idfff5e804ea328f7b5feebac72497c97329320ee+0@gerrit.coreboot.org>
Message-ID: <E1REPaB-0000k7-SX@ra.coresystems.de>

the following patch was just integrated into master:
commit 38860f7f936d58ca777a55dfc3c458feccfc0137
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 14:25:07 2011 -0700

    Refactor option rom initialization code in coreboot.
    
    - move int15 handler out of the generic code into the mainboard directories
      of those mainboards that actually use it.
    - move vbe headers to vbe.h
    - move function prototypes used in native oprom code to x86.h
    
    Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/255 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 20:01:01 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 20:01:01 +0200
Subject: [coreboot] Patch merged into coreboot/master: b296563 refactor vesa
	mode setting code and bootsplash code
References: <I0045c9d75757657f4ce531889593102ea1e39ce5+0@gerrit.coreboot.org>
Message-ID: <E1REPaX-0000n2-PB@ra.coresystems.de>

the following patch was just integrated into master:
commit b296563878a245bc138fb213f1fb60e04ae1751a
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 14:30:59 2011 -0700

    refactor vesa mode setting code and bootsplash code
    
    - adds possibility to set a vesa mode without showing a bootsplash
    - make bootsplash / mode setting code available in real mode.
    
    Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/256 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 20:01:41 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 20:01:41 +0200
Subject: [coreboot] Patch merged into coreboot/master: 6faf97c Fix native
	x86 option rom initialization
References: <Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c+0@gerrit.coreboot.org>
Message-ID: <E1REPbB-0000uD-9d@ra.coresystems.de>

the following patch was just integrated into master:
commit 6faf97c0c1a10c44fbfebcd25d8b93967263fdfd
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 12 14:35:54 2011 -0700

    Fix native x86 option rom initialization
    
    - Intel option roms want an initialized i8259 or they will
      throw an exception 6. This should be done in the southbridge
      code, but that is executed much later than the VGA init, so
      initialize the i8259 in src/devices/oprom/x86.c.
      In the long run this will allow getting rid of some of the
      ugly hacks in some AMD boards' romstage.c
    - Don't overwrite the mode when copying mode info information back
      from 0x600.
    
    Change-Id: Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/257 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 20:11:52 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 20:11:52 +0200
Subject: [coreboot] Patch merged into coreboot/master: 9570367 Prevent build
	breakage without consoles enabled
References: <Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2+0@gerrit.coreboot.org>
Message-ID: <E1REPl2-0002Eb-5l@ra.coresystems.de>

the following patch was just integrated into master:
commit 957036708c6ce1396fc1ebbf33e3e3a01af09bc7
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jun 1 14:04:50 2011 -0700

    Prevent build breakage without consoles enabled
    
    If all console types are disabled, coreboot will fail to compile because
    static code is unused. This patch fixes the issue.
    
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2

See http://review.coreboot.org/260 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 20:03:14 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 20:03:14 +0200
Subject: [coreboot] Patch merged into coreboot/master: b043841 Fix
	compilation of x86emu with gcc 4.6.x
References: <Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e+0@gerrit.coreboot.org>
Message-ID: <E1REPcg-00040Z-T7@ra.coresystems.de>

the following patch was just integrated into master:
commit b0438411e379d3fa1e3e7f43963138eb2d46a2fd
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 4 10:34:37 2011 -0700

    Fix compilation of x86emu with gcc 4.6.x
    
    gcc 4.6 complains about unused but set variables in x86emu.
    Particularly some variables are always set but only used in
    debug mode, or when FPU support is enabled.
    
    Change-Id: Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/258 for details.

-gerrit



From gerrit at coreboot.org  Thu Oct 13 20:04:27 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 13 Oct 2011 20:04:27 +0200
Subject: [coreboot] Patch merged into coreboot/master: 7f8e685 Load an IDT
	with NULL limit
References: <I8d048c894c863ac4971fcef8f065be6b899e1d3e+0@gerrit.coreboot.org>
Message-ID: <E1REPdr-0005o0-PA@ra.coresystems.de>

the following patch was just integrated into master:
commit 7f8e685996f65f2c67d1113fcfaab33ccc385da7
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jun 1 14:01:46 2011 -0700

    Load an IDT with NULL limit
    
    Load an IDT with NULL limit to prevent the 16bit IDT being used
    in protected mode before c_start.S sets up a 32bit IDT when entering
    ram stage.
    
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e

See http://review.coreboot.org/259 for details.

-gerrit



From uwe at hermann-uwe.de  Fri Oct 14 01:32:43 2011
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 14 Oct 2011 01:32:43 +0200
Subject: [coreboot] Gerrit config (was: Re: Patch merged into
 coreboot/master: 7f8e685 Load an IDT with NULL limit)
In-Reply-To: <E1REPdr-0005o0-PA@ra.coresystems.de>
References: <I8d048c894c863ac4971fcef8f065be6b899e1d3e+0@gerrit.coreboot.org>
	<E1REPdr-0005o0-PA@ra.coresystems.de>
Message-ID: <20111013233243.GA24993@greenwood>

On Thu, Oct 13, 2011 at 08:04:27PM +0200, gerrit at coreboot.org wrote:
> the following patch was just integrated into master:
> commit 7f8e685996f65f2c67d1113fcfaab33ccc385da7
> Author: Stefan Reinauer <reinauer at chromium.org>
> Date:   Wed Jun 1 14:01:46 2011 -0700
> 
>     Load an IDT with NULL limit
>     
>     Load an IDT with NULL limit to prevent the 16bit IDT being used
>     in protected mode before c_start.S sets up a 32bit IDT when entering
>     ram stage.
>     
>     Signed-off-by: Stefan Reinauer <reinauer at google.com>
>     Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e
> 
> See http://review.coreboot.org/259 for details.

Can gerrit be configured to show

 - who approved a patch and when
 - the comment(s) (if any) left by the reviewer?

Having to open the URL in a browser instead of that info being in the
"Patch merged into coreboot/master" mail is really annoying, IMHO.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From gerrit at coreboot.org  Fri Oct 14 02:09:21 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 14 Oct 2011 02:09:21 +0200
Subject: [coreboot] New patch to review for coreboot: 06fb731 Add eh_frame
	to rom section to fix compilation of coreboot with gcc 4.6
References: <I347dd84a61244eed145c02a080309d5a34c5394a+0@gerrit.coreboot.org>
Message-ID: <I347dd84a61244eed145c02a080309d5a34c5394a+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/263

-gerrit

commit 06fb7317666ca52a7d88292c2a6d890005488e91
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 16:52:27 2011 -0700

    Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6
    
    Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/init/bootblock.ld |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index eab64cf..dae17bd 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -39,6 +39,7 @@ SECTIONS
 		*(.rodata);
 		*(.rodata.*);
 		*(.rom.data.*);
+		*(.eh_frame);
 		. = ALIGN(16);
 		_erom = .;
 	}



From gerrit at coreboot.org  Fri Oct 14 02:09:21 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 14 Oct 2011 02:09:21 +0200
Subject: [coreboot] New patch to review for coreboot: 9f88de6 fix
	compilation of intel/sch northbridge code with gcc 4.6
References: <I57804dff9e37f0127900ebb7a67118382944eb89+0@gerrit.coreboot.org>
Message-ID: <I57804dff9e37f0127900ebb7a67118382944eb89+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/264

-gerrit

commit 9f88de6eea53205fac34158c9c71f258a159a364
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 16:53:11 2011 -0700

    fix compilation of intel/sch northbridge code with gcc 4.6
    
    Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/northbridge/intel/sch/raminit.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/intel/sch/raminit.c b/src/northbridge/intel/sch/raminit.c
index 5e49682..ae308ee 100644
--- a/src/northbridge/intel/sch/raminit.c
+++ b/src/northbridge/intel/sch/raminit.c
@@ -70,6 +70,9 @@ static u32 detect_softstrap_base(void)
 	case 4:
 		base_addr = 0xFFFE0000;
 		break;
+	default:
+		base_addr = 0;
+		die("No valid softstrap base found.\n");
 	}
 	return base_addr;
 }



From gerrit at coreboot.org  Fri Oct 14 02:09:21 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 14 Oct 2011 02:09:21 +0200
Subject: [coreboot] New patch to review for coreboot: 59f4c2c Fix
	compilation of VIA CN700 northbridge code with gcc 4.6
References: <Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b+0@gerrit.coreboot.org>
Message-ID: <Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/265

-gerrit

commit 59f4c2c0d334d96a6045ba12782c318cbda01997
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 17:03:04 2011 -0700

    Fix compilation of VIA CN700 northbridge code with gcc 4.6
    
    Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/northbridge/via/cn700/raminit.c |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index df4010e..2c387bb 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -179,12 +179,20 @@ static void sdram_set_size(const struct mem_controller *ctrl)
 	case 0x01:
 		result = 0x10;	/* 1GB */
 		break;
+	default:
+		result = 0;
 	}
 
-	if (result == 0xff)
+	switch (result) {
+	case 0xff:
 		die("DRAM module size too big, not supported by CN700\n");
-	else
+		break;
+	case 0:
+		die("DRAM module has unknown density\n");
+		break;
+	default:
 		printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64);
+	}
 
 	pci_write_config8(ctrl->d0f3, 0x40, result);
 	pci_write_config8(ctrl->d0f3, 0x48, 0x00);



From gerrit at coreboot.org  Fri Oct 14 02:09:22 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 14 Oct 2011 02:09:22 +0200
Subject: [coreboot] New patch to review for coreboot: 4876404 AMD CPU and
	chipset fixes for compilation with gcc 4.6
References: <I05b08765b38d8d6cc9b7cbdaf87c127b33408c81+0@gerrit.coreboot.org>
Message-ID: <I05b08765b38d8d6cc9b7cbdaf87c127b33408c81+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/266

-gerrit

commit 48764047d8720e3e6f9ae9119f8ae16b9d875cd7
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 17:04:02 2011 -0700

    AMD CPU and chipset fixes for compilation with gcc 4.6
    
    Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/northbridge/amd/amdk8/early_ht.c           |    4 ++--
 src/northbridge/amd/amdk8/incoherent_ht.c      |    4 ++--
 src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    |    4 ++--
 src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |    2 +-
 src/southbridge/amd/rs780/rs780.c              |    2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index bf80ef8..2ecc0d0 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -16,8 +16,8 @@ static void enumerate_ht_chain(void)
 	device_t dev;
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 	//let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
-	unsigned real_last_unitid;
-	uint8_t real_last_pos;
+	unsigned real_last_unitid = 0;
+	uint8_t real_last_pos = 0;
 	int ht_dev_num = 0; // except host_bridge
 	uint8_t end_used = 0;
 #endif
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 4d0d025..a14adac 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -305,8 +305,8 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 	//let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
-	unsigned real_last_unitid;
-	uint8_t real_last_pos;
+	unsigned real_last_unitid = 0;
+	uint8_t real_last_pos = 0;
 	int ht_dev_num = 0;
 	uint8_t end_used = 0;
 #endif
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 1191536..1faed5a 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -1353,7 +1353,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
 	u16 tCKproposed16x;
 	u8 CLactual, CLdesired, CLT_Fail;
 
-	u8 smbaddr, byte, bytex;
+	u8 smbaddr, byte = 0, bytex = 0;
 
 	CASLatLow = 0xFF;
 	CASLatHigh = 0xFF;
@@ -2768,7 +2768,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
 static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat,
 					u8 dct, u32 dev, u32 index_reg)
 {
-	u8 Smallest, Largest;
+	u8 Smallest = 0, Largest = 0;
 	u32 val;
 	u8 byte, bytex;
 
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 54fdedf..3e1b13d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -849,7 +849,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
 	u32 value;
 	u8 j;
 	u32 value_test;
-	u32 value_r, value_r_test;
+	u32 value_r = 0, value_r_test = 0;
 	u8 pattern, channel, BeatCnt;
 	struct DCTStatStruc *ptrAddr;
 
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index b8c7d04..cf6d2df 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -190,7 +190,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 {
 	/* NB_InitGFXStraps */
 	u32 MMIOBase, apc04, apc18, apc24, romstrap2;
-	msr_t pcie_mmio_save;
+	msr_t pcie_mmio_save = { 0, 0 };
 	volatile u32 * strap;
 
 	// disable processor pcie mmio, if enabled



From kevin at koconnor.net  Fri Oct 14 01:15:16 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Thu, 13 Oct 2011 19:15:16 -0400
Subject: [coreboot] [SeaBIOS] usb boot issue
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E208AB0C7849@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E208AB0C7849@DATAKAMPONE.datakamp2008.local>
Message-ID: <20111013231516.GA19387@morn.localdomain>

On Thu, Oct 13, 2011 at 03:56:48PM +0200, Wolfgang Kamp - datakamp wrote:
> 
> Hi,
> 
> is there any solution for the usb boot issue of the AMD SB800 Persimmon platform
> with SeaBIOS 1.6.3 and actual Coreboot version?

I'm unfamiliar with the issue.  Can you post the SeaBIOS debug output
along with a description of the issue you are seeing?

-Kevin



From gerrit at coreboot.org  Fri Oct 14 02:27:59 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 14 Oct 2011 02:27:59 +0200
Subject: [coreboot] New patch to review for coreboot: 8b99e13 Fix
	compilation of AMD GX2 northbridge code with gcc 4.6
References: <I71d96b7cd36dd99a3590ec311c11f67f13012e68+0@gerrit.coreboot.org>
Message-ID: <I71d96b7cd36dd99a3590ec311c11f67f13012e68+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/267

-gerrit

commit 8b99e131dab9680feb84d4a1e126b58ea12aa8d0
Author: Stefan Reinauer <reinauer at google.com>
Date:   Thu Oct 13 17:26:10 2011 -0700

    Fix compilation of AMD GX2 northbridge code with gcc 4.6
    
    Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/northbridge/amd/gx2/northbridgeinit.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index fd8d3f9..e4aaa8b 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -485,7 +485,7 @@ performance:
 
 static void GeodeLinkPriority(void)
 {
-	msr_t msr;
+	msr_t msr = { 0, 0 };
 	struct msrinit *prio = GeodeLinkPriorityTable;
 	int i;
 
@@ -526,7 +526,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
 	/* ok this is whacky bit translation time. */
 	int bit;
 	uint8_t shadowByte;
-	msr_t msr;
+	msr_t msr = { 0, 0 };
 	shadowByte = (uint8_t) (shadowLo >> 16);
 
 	/* load up D000 settings in edx. */



From gerrit at coreboot.org  Fri Oct 14 02:28:00 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 14 Oct 2011 02:28:00 +0200
Subject: [coreboot] New patch to review for coreboot: 634373f Fix AMD SB800
	(cimx) southbridge code to compile with gcc 4.6
References: <I672135a9b6e3b641ceb655cb00d40ee760c17edc+0@gerrit.coreboot.org>
Message-ID: <I672135a9b6e3b641ceb655cb00d40ee760c17edc+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/268

-gerrit

commit 634373f4296d80fb0cb6f7df669351f83788d4ee
Author: Stefan Reinauer <reinauer at google.com>
Date:   Thu Oct 13 17:26:43 2011 -0700

    Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6
    
    Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/southbridge/amd/cimx/sb800/SBPLATFORM.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 164a651..d7317a2 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -155,4 +155,7 @@ typedef union _PCI_ADDR {
 #define cimEhciTrafficHandingDefault    FALSE
 #define cimFusionMsgCMultiCoreDefault   FALSE
 #define cimFusionMsgCStageDefault       FALSE
+
+#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
+
 #endif // _AMD_SBPLATFORM_H_



From scott at notabs.org  Fri Oct 14 06:19:54 2011
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 13 Oct 2011 23:19:54 -0500
Subject: [coreboot] [SeaBIOS] usb boot issue
In-Reply-To: <20111013231516.GA19387@morn.localdomain>
References: <4738C8CE0A30FF47AACA9C624746E3E208AB0C7849@DATAKAMPONE.datakamp2008.local>
	<20111013231516.GA19387@morn.localdomain>
Message-ID: <B2DB406FCEB94CD9A1BDC55DE4219231@asusp67>

Kevin O'Connor wrote:

]On Thu, Oct 13, 2011 at 03:56:48PM +0200, Wolfgang Kamp - datakamp wrote:
]> 
]> Hi,
]> 
]> is there any solution for the usb boot issue of the AMD SB800 Persimmon
]platform
]> with SeaBIOS 1.6.3 and actual Coreboot version?
]
]I'm unfamiliar with the issue.  Can you post the SeaBIOS debug output
]along with a description of the issue you are seeing?

This might be a coreboot problem and not a SeaBIOS problem. See:
http://www.mail-archive.com/coreboot at coreboot.org/msg31922.html

Wolfgang could try reverting the suspect coreboot patch and see
if it solves the problem. The change was a NIC fix I believe.
I think Marc had proposed an alternative NIC fix that could be
tried if the existing one really is causing the usb problem.

]-Kevin




From marcj303 at gmail.com  Fri Oct 14 06:22:03 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 13 Oct 2011 22:22:03 -0600
Subject: [coreboot] how to delete symbol link created at compile time
In-Reply-To: <F53A09371FB723428826B442A4B20A4107BCBF12@sbjgexmb1.amd.com>
References: <AcyJiUA8lO474U0LSD2H/TjMkvC6Cw==>
	<F53A09371FB723428826B442A4B20A4107BCBF12@sbjgexmb1.amd.com>
Message-ID: <CALrs_3gL3W3F9LjwxSx=LjB9yNMZA7nTRz58e5diuxTodLa11g@mail.gmail.com>

On Thu, Oct 13, 2011 at 3:19 AM, She, Kerry <Kerry.She at amd.com> wrote:
> Hello,
>
>
>
> Some mainboard support more than one family of CPUs with same socket type,
>
> Such as SuperMicro/h8scm:
>
> http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm
>
>
>
> My implementation is the mainboard CPU type can be configured as family10 or
> family15 CPU.
>
> In order to eliminate the duplicated code, both configuration shares most of
> the platform code,
>
> but some code can?t be shared between different family of CPUs.
>
> Take devicetree.cb as an example,
>
> I have created 2 devicetree file :
>
> devicetree_f15.cb for platform with family 15 CPU
>
> devicetree_f10.cb ?for platform with family 10 CPU
>
>
>
> I changed the makefile to create a symbol link ?devicetree.cb? link to
> devicetree_f10.cb or devicetree_f15.cb at compile time.
>
> The problem is that I can?t delete the symbol link when make
> clean/distclean.
>
>
>
> I found that make clean/distclean will not traverse the src/ directory.
>
> How can I get this symbol link removed when doing a make clean.
>
> Any other suggestion is welcome.
>
> Regards,
> Kerry Sheh < kerry.she at amd.com>
> Tel:? 86-10-6280-1415
> Mobile:? 86 - 152 1018 2083

Kerry,

I thought about a recursive call through the subdirs to do a make
clean, but that would make a lot of errors for most Makefiles.inc
because they don't have a clean target. I wonder if there is a better
way.

Marc

-- 
http://se-eng.com



From Kerry.She at amd.com  Fri Oct 14 06:25:45 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Fri, 14 Oct 2011 12:25:45 +0800
Subject: [coreboot] [SeaBIOS] usb boot issue
In-Reply-To: <20111013231516.GA19387@morn.localdomain>
References: <4738C8CE0A30FF47AACA9C624746E3E208AB0C7849@DATAKAMPONE.datakamp2008.local>
	<20111013231516.GA19387@morn.localdomain>
Message-ID: <F53A09371FB723428826B442A4B20A4107BCC394@sbjgexmb1.amd.com>



> -----Original Message-----
> From: seabios-bounces+kerry.she=amd.com at seabios.org [mailto:seabios-
> bounces+kerry.she=amd.com at seabios.org] On Behalf Of Kevin O'Connor
> Sent: Friday, October 14, 2011 7:15 AM
> To: Wolfgang Kamp - datakamp
> Cc: seabios at seabios.org; coreboot at coreboot.org
> Subject: Re: [SeaBIOS] usb boot issue
> 
> On Thu, Oct 13, 2011 at 03:56:48PM +0200, Wolfgang Kamp - datakamp
wrote:
> >
> > Hi,
> >
> > is there any solution for the usb boot issue of the AMD SB800
Persimmon
> platform
> > with SeaBIOS 1.6.3 and actual Coreboot version?
> 
> I'm unfamiliar with the issue.  Can you post the SeaBIOS debug output
> along with a description of the issue you are seeing?

I got the similar problem with seabios commit 8a161c9f5
I'm using a EHCI CDROM drive, I have a simple test on sb700 and sb800
platform.
After boot to Linux OS, the Ehci CDROM drive can works fine.
I suspect whether the seabios ehci driver is full support EHCI device?

Following text is the seabios log with log level 3.
Thanks

SeaBIOS (version pre-0.6.3-20111014_111147-Debian-vg0)

init usb
EHCI init on dev 00:12.2 (regs=0xfe105420)
/7ffd2000\ Start thread
/7ffd1000\ Start thread
/7ffd0000\ Start thread
/7ffcf000\ Start thread
/7ffce000\ Start thread
/7ffcd000\ Start thread
/7ffcc000\ Start thread
EHCI init on dev 00:13.2 (regs=0xfe105520)
/7ffca000\ Start thread
/7ffc9000\ Start thread
/7ffc8000\ Start thread
/7ffc7000\ Start thread
/7ffc6000\ Start thread
/7ffc5000\ Start thread
/7ffc4000\ Start thread
OHCI init on dev 00:14.5 (regs=0xfe104000)
/7ffc3000\ Start thread
init ps2port
/7ffc2000\ Start thread
|7ffc2000| Searching CBFS for prefix etc/ps2-keyboard-spinup
init lpt
Found 0 lpt ports
init serial
Found 1 serial ports
init floppy drives
init hard drives
ATA controller 1 at 1020/1040/0 (irq 0 dev 88)
/7ffc1000\ Start thread
\7ffc1000/ End thread
ATA controller 2 at 1028/1044/0 (irq 0 dev 88)
/7ffc1000\ Start thread
\7ffc1000/ End thread
ATA controller 3 at 1f0/3f4/0 (irq 14 dev a1)
/7ffc1000\ Start thread
\7ffc1000/ End thread
ATA controller 4 at 170/374/0 (irq 15 dev a1)
/7ffc1000\ Start thread
\7ffc1000/ End thread
init ahci
Searching CBFS for prefix img/
Searching CBFS for prefix floppyimg/
\7ffd1000/ End thread
\7ffcf000/ End thread
\7ffce000/ End thread
\7ffcd000/ End thread
\7ffcc000/ End thread
\7ffc9000/ End thread
\7ffc8000/ End thread
\7ffc7000/ End thread
\7ffc6000/ End thread
\7ffc4000/ End thread
/7ffd1000\ Start thread
\7ffd1000/ End thread
/7ffd1000\ Start thread
\7ffd1000/ End thread
\7ffc3000/ End thread
|7ffc2000| Got ps2 nak (status=51)
|7ffc2000| ps2 command 2ff failed (aux=0)
\7ffc2000/ End thread
|7ffd0000| set_address 0x7ffd37a0
|7ffd0000| config_usb: 0x7ffd343c
|7ffc5000| OHCI init on dev 00:13.0 (regs=0xfe102000)
/7ffd1000\ Start thread
|7ffc5000| OHCI init on dev 00:13.1 (regs=0xfe103000)
/7ffcf000\ Start thread
\7ffc5000/ End thread
\7ffca000/ End thread
/7ffce000\ Start thread
\7ffce000/ End thread
/7ffce000\ Start thread
\7ffce000/ End thread
/7ffce000\ Start thread
\7ffce000/ End thread
\7ffd1000/ End thread
/7ffd1000\ Start thread
\7ffd1000/ End thread
/7ffd1000\ Start thread
/7ffce000\ Start thread
\7ffce000/ End thread
|7ffd1000| set_address 0x7ffd33c0
|7ffd1000| config_usb: 0x7ffd34f0
|7ffd1000| device rev=0110 cls=00 sub=00 proto=00 size=40
|7ffd1000| usb_hid_init 0x7ffd34f0
|7ffd1000| ebda moved from 9fc00 to 9f800
|7ffd1000| USB mouse initialized
\7ffd1000/ End thread
\7ffcf000/ End thread
|7ffd0000| WARNING - Timeout at ehci_wait_qh:316!
\7ffd0000/ End thread
\7ffd2000/ End thread
All threads complete.

> -Kevin
> 
> _______________________________________________
> SeaBIOS mailing list
> SeaBIOS at seabios.org
> http://www.seabios.org/mailman/listinfo/seabios





From Kerry.She at amd.com  Fri Oct 14 07:16:50 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Fri, 14 Oct 2011 13:16:50 +0800
Subject: [coreboot] how to delete symbol link created at compile time
In-Reply-To: <CALrs_3gL3W3F9LjwxSx=LjB9yNMZA7nTRz58e5diuxTodLa11g@mail.gmail.com>
References: <AcyJiUA8lO474U0LSD2H/TjMkvC6Cw==>
	<F53A09371FB723428826B442A4B20A4107BCBF12@sbjgexmb1.amd.com>
	<CALrs_3gL3W3F9LjwxSx=LjB9yNMZA7nTRz58e5diuxTodLa11g@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4107BCC3E8@sbjgexmb1.amd.com>

Hello, Marc

> -----Original Message-----
> From: Marc Jones [mailto:marcj303 at gmail.com]
> Sent: Friday, October 14, 2011 12:22 PM
> To: She, Kerry
> Cc: coreboot
> Subject: Re: [coreboot] how to delete symbol link created at compile time
> 
> On Thu, Oct 13, 2011 at 3:19 AM, She, Kerry <Kerry.She at amd.com> wrote:
> > Hello,
> >
> >
> >
> > Some mainboard support more than one family of CPUs with same socket
> type,
> >
> > Such as SuperMicro/h8scm:
> >
> > http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-
> F.cfm
> >
> >
> >
> > My implementation is the mainboard CPU type can be configured as
> family10 or
> > family15 CPU.
> >
> > In order to eliminate the duplicated code, both configuration shares
> most of
> > the platform code,
> >
> > but some code can't be shared between different family of CPUs.
> >
> > Take devicetree.cb as an example,
> >
> > I have created 2 devicetree file :
> >
> > devicetree_f15.cb for platform with family 15 CPU
> >
> > devicetree_f10.cb ?for platform with family 10 CPU
> >
> >
> >
> > I changed the makefile to create a symbol link "devicetree.cb" link to
> > devicetree_f10.cb or devicetree_f15.cb at compile time.
> >
> > The problem is that I can't delete the symbol link when make
> > clean/distclean.
> >
> >
> >
> > I found that make clean/distclean will not traverse the src/ directory.
> >
> > How can I get this symbol link removed when doing a make clean.
> >
> > Any other suggestion is welcome.
> >
> > Regards,
> > Kerry Sheh < kerry.she at amd.com>
> > Tel:? 86-10-6280-1415
> > Mobile:? 86 - 152 1018 2083
> 
> Kerry,
> 
> I thought about a recursive call through the subdirs to do a make
> clean, but that would make a lot of errors for most Makefiles.inc
> because they don't have a clean target. I wonder if there is a better
> way.

Yes, you are right!
My temporary solution is adding a target in the mainboard Makefile,
not modify any of the top level Makefile. 
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -50,3 +50,5 @@ endif
 
 subdirs-y += ../../../../$(AGESA_ROOT)
 
+clean-mainboard:
+	$(RM) $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb

But I think a better and more generic solution should be considered.
thanks




From gerrit at coreboot.org  Fri Oct 14 08:12:07 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 14 Oct 2011 08:12:07 +0200
Subject: [coreboot] Patch merged into coreboot/master: 06fb731 Add eh_frame
	to rom section to fix compilation of coreboot with gcc 4.6
References: <I347dd84a61244eed145c02a080309d5a34c5394a+0@gerrit.coreboot.org>
Message-ID: <E1REb03-0004kv-Pi@ra.coresystems.de>

the following patch was just integrated into master:
commit 06fb7317666ca52a7d88292c2a6d890005488e91
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 16:52:27 2011 -0700

    Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6
    
    Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/263 for details.

-gerrit



From gerrit at coreboot.org  Fri Oct 14 08:12:26 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 14 Oct 2011 08:12:26 +0200
Subject: [coreboot] Patch merged into coreboot/master: 9f88de6 fix
	compilation of intel/sch northbridge code with gcc 4.6
References: <I57804dff9e37f0127900ebb7a67118382944eb89+0@gerrit.coreboot.org>
Message-ID: <E1REb0M-0004st-Gk@ra.coresystems.de>

the following patch was just integrated into master:
commit 9f88de6eea53205fac34158c9c71f258a159a364
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 16:53:11 2011 -0700

    fix compilation of intel/sch northbridge code with gcc 4.6
    
    Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/264 for details.

-gerrit



From gerrit at coreboot.org  Fri Oct 14 11:42:07 2011
From: gerrit at coreboot.org (Christoph Grenz (christophg+cb@grenz-bonn.de))
Date: Fri, 14 Oct 2011 11:42:07 +0200
Subject: [coreboot] Patch set updated for coreboot: d2e2c79 console: support
	integrated 7-segment displays for POST codes
References: <I8f8e820f8c75641b35e7249bf622b63a3604b9f3+0@gerrit.coreboot.org>
Message-ID: <I8f8e820f8c75641b35e7249bf622b63a3604b9f3+2@gerrit.coreboot.org>

Christoph Grenz (christophg+cb at grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/221

-gerrit

commit d2e2c796580078a568d66e59db805ceb69a1e774
Author: Christoph Grenz <christophg+cb at grenz-bonn.de>
Date:   Sun Sep 18 22:54:51 2011 +0200

    console: support integrated 7-segment displays for POST codes
    
    Add a configuration option POST_PORT which defaults to 0x80 and
    can be redefined by boards which have integrated POST displays
    on another I/O port. Change post.c to output POST codes to this
    port instead of 0x80 hardcoded.
    
    Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3
    Signed-off-by: Christoph Grenz <christophg+cb at grenz-bonn.de>
---
 src/console/Kconfig |    4 ++++
 src/console/post.c  |    2 +-
 2 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/src/console/Kconfig b/src/console/Kconfig
index 02244d7..8382695 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -333,6 +333,10 @@ config NO_POST
 	bool "Don't show any POST codes"
 	default n
 
+config POST_PORT
+	int
+	default 0x80
+
 config CONSOLE_POST
 	bool "Show POST codes on the debug console"
 	depends on !NO_POST
diff --git a/src/console/post.c b/src/console/post.c
index 3872c2d..7fc9d6f 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -32,6 +32,6 @@ void post_code(uint8_t value)
 	print_emerg_hex8(value);
 	print_emerg("\n");
 #endif
-	outb(value, 0x80);
+	outb(value, CONFIG_POST_PORT);
 #endif
 }



From wmkamp at datakamp.de  Fri Oct 14 17:49:39 2011
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Fri, 14 Oct 2011 17:49:39 +0200
Subject: [coreboot] [SeaBIOS] usb boot issue
In-Reply-To: <20111013231516.GA19387@morn.localdomain>
References: <4738C8CE0A30FF47AACA9C624746E3E208AB0C7849@DATAKAMPONE.datakamp2008.local>
	<20111013231516.GA19387@morn.localdomain>
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E208AB0C785C@DATAKAMPONE.datakamp2008.local>

Hi Kevin,

the problem occurs when I try to boot from USB Stick on AMD DBFT1 Persimmon board.
I have tried a couple of sticks in different USB slots but it is always the same issue.
If Ubuntu has booted from HD the stick will be recognized correctly.
The log is attached. Tell me if you need more information.

Regards

Wolfgang


-----Urspr?ngliche Nachricht-----
Von: Kevin O'Connor [mailto:kevin at koconnor.net] 
Gesendet: Freitag, 14. Oktober 2011 01:15
An: Wolfgang Kamp - datakamp
Cc: coreboot at coreboot.org; seabios at seabios.org
Betreff: Re: [SeaBIOS] usb boot issue

On Thu, Oct 13, 2011 at 03:56:48PM +0200, Wolfgang Kamp - datakamp wrote:
> 
> Hi,
> 
> is there any solution for the usb boot issue of the AMD SB800 Persimmon platform
> with SeaBIOS 1.6.3 and actual Coreboot version?

I'm unfamiliar with the issue.  Can you post the SeaBIOS debug output
along with a description of the issue you are seeing?

-Kevin



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From mbuschman at lucidmachines.com  Fri Oct 14 18:00:39 2011
From: mbuschman at lucidmachines.com (Marshall Buschman)
Date: Fri, 14 Oct 2011 11:00:39 -0500
Subject: [coreboot] [SeaBIOS] usb boot issue
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E208AB0C785C@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E208AB0C7849@DATAKAMPONE.datakamp2008.local>	<20111013231516.GA19387@morn.localdomain>
	<4738C8CE0A30FF47AACA9C624746E3E208AB0C785C@DATAKAMPONE.datakamp2008.local>
Message-ID: <4E985CA7.4060009@lucidmachines.com>

On 10/14/2011 10:49 AM, Wolfgang Kamp - datakamp wrote:
> Hi Kevin,
>
> the problem occurs when I try to boot from USB Stick on AMD DBFT1 Persimmon board.
> I have tried a couple of sticks in different USB slots but it is always the same issue.
> If Ubuntu has booted from HD the stick will be recognized correctly.
> The log is attached. Tell me if you need more information.
>
In testing on the ASRock E350M1 (also SB800-based), I am not able to 
correctly access USB disks under linux.
Reads fail and the USB disk device disappears and reappears. The time 
before failure appears to be random, although the most data I've been 
able to read from the device (using a simple file copy) is 500MB. I do 
not believe failure will occur unless you attempt to read data from the 
USB disk.

You said you're able to boot from the hard drive, and then read from the 
USB disk correctly.
It would be interesting to know if once booted, you can read significant 
quantities of data reliably.

I am guessing you will not be able to, and that whatever bug causes this 
is also responsible for the USB boot issue.
> Regards
>
> Wolfgang
>
>
> -----Urspr?ngliche Nachricht-----
> Von: Kevin O'Connor [mailto:kevin at koconnor.net]
> Gesendet: Freitag, 14. Oktober 2011 01:15
> An: Wolfgang Kamp - datakamp
> Cc: coreboot at coreboot.org; seabios at seabios.org
> Betreff: Re: [SeaBIOS] usb boot issue
>
> On Thu, Oct 13, 2011 at 03:56:48PM +0200, Wolfgang Kamp - datakamp wrote:
>> Hi,
>>
>> is there any solution for the usb boot issue of the AMD SB800 Persimmon platform
>> with SeaBIOS 1.6.3 and actual Coreboot version?
> I'm unfamiliar with the issue.  Can you post the SeaBIOS debug output
> along with a description of the issue you are seeing?
>
> -Kevin
>
>
>




From patrick at georgi-clan.de  Fri Oct 14 18:40:28 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 14 Oct 2011 18:40:28 +0200
Subject: [coreboot] how to delete symbol link created at compile time
In-Reply-To: <F53A09371FB723428826B442A4B20A4107BCBF12@sbjgexmb1.amd.com>
References: <F53A09371FB723428826B442A4B20A4107BCBF12@sbjgexmb1.amd.com>
Message-ID: <1318610428.5378.1.camel@ubuntu>

Am Donnerstag, den 13.10.2011, 17:19 +0800 schrieb She, Kerry:
> I have created 2 devicetree file :
> 
> devicetree_f15.cb for platform with family 15 CPU 
> devicetree_f10.cb  for platform with family 10 CPU
What are the differences exactly?

If possible, I'd like to look for a solution that allows a single image
to work with both families.

> The problem is that I can?t delete the symbol link when make
> clean/distclean.
symlinks won't work on Win32 (except in cygwin, which doesn't count).


Patrick





From gerrit at coreboot.org  Fri Oct 14 19:12:11 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 14 Oct 2011 19:12:11 +0200
Subject: [coreboot] Patch merged into coreboot/master: 59f4c2c Fix
	compilation of VIA CN700 northbridge code with gcc 4.6
References: <Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b+0@gerrit.coreboot.org>
Message-ID: <E1RElIp-0004wo-Rm@ra.coresystems.de>

the following patch was just integrated into master:
commit 59f4c2c0d334d96a6045ba12782c318cbda01997
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 17:03:04 2011 -0700

    Fix compilation of VIA CN700 northbridge code with gcc 4.6
    
    Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

See http://review.coreboot.org/265 for details.

-gerrit



From gerrit at coreboot.org  Fri Oct 14 19:25:28 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 14 Oct 2011 19:25:28 +0200
Subject: [coreboot] Patch set updated for coreboot: af7e4d4 Fix AMD SB800
	(cimx) southbridge code to compile with gcc 4.6
References: <I672135a9b6e3b641ceb655cb00d40ee760c17edc+0@gerrit.coreboot.org>
Message-ID: <I672135a9b6e3b641ceb655cb00d40ee760c17edc+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/268

-gerrit

commit af7e4d4a5ac58ca80344ef01810387bd8271207a
Author: Stefan Reinauer <reinauer at google.com>
Date:   Thu Oct 13 17:26:43 2011 -0700

    Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6
    
    Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/southbridge/amd/cimx/sb800/SBPLATFORM.h |    3 +++
 src/vendorcode/amd/cimx/sb800/AMDSBLIB.h    |    4 ++++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 164a651..d7317a2 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -155,4 +155,7 @@ typedef union _PCI_ADDR {
 #define cimEhciTrafficHandingDefault    FALSE
 #define cimFusionMsgCMultiCoreDefault   FALSE
 #define cimFusionMsgCStageDefault       FALSE
+
+#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
+
 #endif // _AMD_SBPLATFORM_H_
diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
index 6c92227..b2a0a1b 100644
--- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
+++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
@@ -43,6 +43,8 @@
  *
  */
 
+#ifndef __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__
+#define __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__
 
 //AMDSBLIB Routines
 
@@ -116,3 +118,5 @@ void WriteIo32(IN unsigned short Address, IN unsigned int Data);
 //void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
 void CpuidRead(unsigned int CpuidFcnAddress, CPUID_DATA *Value);
 unsigned char ReadNumberOfCpuCores(void);
+
+#endif



From patrick at georgi-clan.de  Fri Oct 14 19:26:03 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 14 Oct 2011 19:26:03 +0200
Subject: [coreboot] Gerrit config (was: Re: Patch merged into
 coreboot/master: 7f8e685 Load an IDT with NULL limit)
In-Reply-To: <20111013233243.GA24993@greenwood>
References: <I8d048c894c863ac4971fcef8f065be6b899e1d3e+0@gerrit.coreboot.org>
	<E1REPdr-0005o0-PA@ra.coresystems.de>
	<20111013233243.GA24993@greenwood>
Message-ID: <1318613163.5378.4.camel@ubuntu>

Am Freitag, den 14.10.2011, 01:32 +0200 schrieb Uwe Hermann:
> On Thu, Oct 13, 2011 at 08:04:27PM +0200, gerrit at coreboot.org wrote:
> > the following patch was just integrated into master:
> > commit 7f8e685996f65f2c67d1113fcfaab33ccc385da7
> > Author: Stefan Reinauer <reinauer at chromium.org>
> > Date:   Wed Jun 1 14:01:46 2011 -0700
> > 
> >     Load an IDT with NULL limit
> >     
> >     Load an IDT with NULL limit to prevent the 16bit IDT being used
> >     in protected mode before c_start.S sets up a 32bit IDT when entering
> >     ram stage.
> >     
> >     Signed-off-by: Stefan Reinauer <reinauer at google.com>
> >     Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e
> > 
> > See http://review.coreboot.org/259 for details.
> 
> Can gerrit be configured to show
> 
>  - who approved a patch and when
I implemented this (but didn't add it to the hook yet):
>  - the comment(s) (if any) left by the reviewer?
> 
> Having to open the URL in a browser instead of that info being in the
> "Patch merged into coreboot/master" mail is really annoying, IMHO.
> 
> 
> Uwe.
> -- 
> http://hermann-uwe.de     | http://sigrok.org
> http://randomprojects.org | http://unmaintained-free-software.org
> 





From patrick at georgi-clan.de  Fri Oct 14 19:28:09 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 14 Oct 2011 19:28:09 +0200
Subject: [coreboot] Gerrit config (was: Re: Patch merged into
 coreboot/master: 7f8e685 Load an IDT with NULL limit)
In-Reply-To: <20111013233243.GA24993@greenwood>
References: <I8d048c894c863ac4971fcef8f065be6b899e1d3e+0@gerrit.coreboot.org>
	<E1REPdr-0005o0-PA@ra.coresystems.de>
	<20111013233243.GA24993@greenwood>
Message-ID: <1318613289.5378.6.camel@ubuntu>

Am Freitag, den 14.10.2011, 01:32 +0200 schrieb Uwe Hermann:
> Can gerrit be configured to show
> 
>  - who approved a patch and when
I implemented this (but didn't add it to the hook yet):

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Oct 14
08:11:24 2011, giving +2
Build-Tested: build bot (Jenkins) at Fri Oct 14 02:56:45 2011, giving +1

Any proposal on how to structure it (I have access to each component:
TYPE NAME [<EMAIL>] at DATETIME, giving VOTE)?

>  - the comment(s) (if any) left by the reviewer?
Those are harder to fetch, and to represent...


Patrick




From gerrit at coreboot.org  Fri Oct 14 19:31:24 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 14 Oct 2011 19:31:24 +0200
Subject: [coreboot] New patch to review for coreboot: 5bc892f Drop eh_frame
	instead of moving it into the image.
References: <I3e17c15848aca86f775fc86f4ad906c820625887+0@gerrit.coreboot.org>
Message-ID: <I3e17c15848aca86f775fc86f4ad906c820625887+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/269

-gerrit

commit 5bc892f62a4c5909aa080aaad5ea351b869d1abb
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 10:29:21 2011 -0700

    Drop eh_frame instead of moving it into the image.
    
    That's what SeaBIOS does, too, and it works just fine.
    
    Change-Id: I3e17c15848aca86f775fc86f4ad906c820625887
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/init/bootblock.ld |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index dae17bd..bde0430 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -39,7 +39,6 @@ SECTIONS
 		*(.rodata);
 		*(.rodata.*);
 		*(.rom.data.*);
-		*(.eh_frame);
 		. = ALIGN(16);
 		_erom = .;
 	}
@@ -49,6 +48,7 @@ SECTIONS
 		*(.note)
 		*(.comment.*)
 		*(.note.*)
+		*(.eh_frame);
 	}
 
 	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage");



From gerrit at coreboot.org  Fri Oct 14 22:54:07 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 14 Oct 2011 22:54:07 +0200
Subject: [coreboot] Patch merged into coreboot/master: 8b99e13 Fix
	compilation of AMD GX2 northbridge code with gcc 4.6
References: <I71d96b7cd36dd99a3590ec311c11f67f13012e68+0@gerrit.coreboot.org>
Message-ID: <E1REolb-0004tE-JZ@ra.coresystems.de>

the following patch was just integrated into master:
commit 8b99e131dab9680feb84d4a1e126b58ea12aa8d0
Author: Stefan Reinauer <reinauer at google.com>
Date:   Thu Oct 13 17:26:10 2011 -0700

    Fix compilation of AMD GX2 northbridge code with gcc 4.6
    
    Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68
    Signed-off-by: Stefan Reinauer <reinauer at google.com>


See http://review.coreboot.org/267 for details.

-gerrit



From gerrit at coreboot.org  Fri Oct 14 22:57:13 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 14 Oct 2011 22:57:13 +0200
Subject: [coreboot] Patch merged into coreboot/master: af7e4d4 Fix AMD SB800
	(cimx) southbridge code to compile with gcc 4.6
References: <I672135a9b6e3b641ceb655cb00d40ee760c17edc+0@gerrit.coreboot.org>
Message-ID: <E1REoob-0005qf-DN@ra.coresystems.de>

the following patch was just integrated into master:
commit af7e4d4a5ac58ca80344ef01810387bd8271207a
Author: Stefan Reinauer <reinauer at google.com>
Date:   Thu Oct 13 17:26:43 2011 -0700

    Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6
    
    Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc
    Signed-off-by: Stefan Reinauer <reinauer at google.com>


See http://review.coreboot.org/268 for details.

-gerrit



From stefan.reinauer at coreboot.org  Fri Oct 14 23:26:46 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Fri, 14 Oct 2011 23:26:46 +0200
Subject: [coreboot] how to delete symbol link created at compile time
In-Reply-To: <CALrs_3gL3W3F9LjwxSx=LjB9yNMZA7nTRz58e5diuxTodLa11g@mail.gmail.com>
References: <AcyJiUA8lO474U0LSD2H/TjMkvC6Cw==>
	<F53A09371FB723428826B442A4B20A4107BCBF12@sbjgexmb1.amd.com>
	<CALrs_3gL3W3F9LjwxSx=LjB9yNMZA7nTRz58e5diuxTodLa11g@mail.gmail.com>
Message-ID: <20111014212645.GA29984@coreboot.org>

* Marc Jones <marcj303 at gmail.com> [111014 06:22]:
> On Thu, Oct 13, 2011 at 3:19 AM, She, Kerry <Kerry.She at amd.com> wrote:
> > Hello,
> >
> >
> >
> > Some mainboard support more than one family of CPUs with same socket type,
> >
> > Such as SuperMicro/h8scm:
> >
> > http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm
> >
> >
> >
> > My implementation is the mainboard CPU type can be configured as family10 or
> > family15 CPU.
> >
> > In order to eliminate the duplicated code, both configuration shares most of
> > the platform code,
> >
> > but some code can?t be shared between different family of CPUs.
> >
> > Take devicetree.cb as an example,
> >
> > I have created 2 devicetree file :
> >
> > devicetree_f15.cb for platform with family 15 CPU
> >
> > devicetree_f10.cb ?for platform with family 10 CPU
> >
> >
> >
> > I changed the makefile to create a symbol link ?devicetree.cb? link to
> > devicetree_f10.cb or devicetree_f15.cb at compile time.
> >
> > The problem is that I can?t delete the symbol link when make
> > clean/distclean.

Please fix the problem by using one device tree for both platforms.






From gerrit at coreboot.org  Sat Oct 15 00:26:59 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:26:59 +0200
Subject: [coreboot] New patch to review for coreboot: a9dd41a sconfig: check
	whether component directory actually exists
References: <I3cfca2725816f0cd7d72139ae53af815009e8ab4+0@gerrit.coreboot.org>
Message-ID: <I3cfca2725816f0cd7d72139ae53af815009e8ab4+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/270

-gerrit

commit a9dd41a1c5f3f00ef790fb071c135900598acab5
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 12:41:46 2011 -0700

    sconfig: check whether component directory actually exists
    
    and add drivers/generic/generic back (empty), since it is used by many
    devicetree.cb files.
    
    Without this patch typos in component names in devicetree.cb cause
    the component to be silently ignored.
    
    Change-Id: I3cfca2725816f0cd7d72139ae53af815009e8ab4
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/drivers/generic/Kconfig              |    1 +
 src/drivers/generic/Makefile.inc         |    1 +
 src/drivers/generic/generic/Kconfig      |    2 ++
 src/drivers/generic/generic/Makefile.inc |    1 +
 util/sconfig/main.c                      |    7 +++++++
 5 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/src/drivers/generic/Kconfig b/src/drivers/generic/Kconfig
index fac6ee5..fbbfeb1 100644
--- a/src/drivers/generic/Kconfig
+++ b/src/drivers/generic/Kconfig
@@ -1,2 +1,3 @@
 source src/drivers/generic/debug/Kconfig
+source src/drivers/generic/generic/Kconfig
 
diff --git a/src/drivers/generic/Makefile.inc b/src/drivers/generic/Makefile.inc
index 0700a0c..08e6cc5 100644
--- a/src/drivers/generic/Makefile.inc
+++ b/src/drivers/generic/Makefile.inc
@@ -1 +1,2 @@
 subdirs-y += debug
+subdirs-y += generic
diff --git a/src/drivers/generic/generic/Kconfig b/src/drivers/generic/generic/Kconfig
new file mode 100644
index 0000000..864b878
--- /dev/null
+++ b/src/drivers/generic/generic/Kconfig
@@ -0,0 +1,2 @@
+config DRIVERS_GENERIC_GENERIC
+	bool
diff --git a/src/drivers/generic/generic/Makefile.inc b/src/drivers/generic/generic/Makefile.inc
new file mode 100644
index 0000000..b7db254
--- /dev/null
+++ b/src/drivers/generic/generic/Makefile.inc
@@ -0,0 +1 @@
+# Empty
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index c3448f3..dab04db 100755
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -131,6 +131,13 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) {
 
 	struct stat st;
 	char *chip_h = malloc(strlen(path)+12);
+	sprintf(chip_h, "src/%s", path);
+	if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) {
+		fprintf(stderr, "ERROR: Chip component %s does not exist.\n",
+				path);
+		exit(1);
+	}
+
 	sprintf(chip_h, "src/%s/chip.h", path);
 	if ((stat(chip_h, &st) == -1) && (errno == ENOENT))
 		new_chip->chiph_exists = 0;



From gerrit at coreboot.org  Sat Oct 15 00:27:00 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:27:00 +0200
Subject: [coreboot] New patch to review for coreboot: b11deb8 cbfstool:
	improve error messages
References: <I369d6f5be09ec53ee5beea2cfea65a80407f0ba3+0@gerrit.coreboot.org>
Message-ID: <I369d6f5be09ec53ee5beea2cfea65a80407f0ba3+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/271

-gerrit

commit b11deb89f181728f75071778f22580408e74c3fd
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 12:44:14 2011 -0700

    cbfstool: improve error messages
    
    If a file can't be added by cbfstool, print the type and name of the file
    in the error message.
    
    Change-Id: I369d6f5be09ec53ee5beea2cfea65a80407f0ba3
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/cbfstool/cbfstool.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 4c28c29..f017b2e 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -81,8 +81,10 @@ static int cbfs_add(int argc, char **argv)
 		base = strtoul(argv[6], NULL, 0);
 	}
 	cbfsfile = create_cbfs_file(cbfsname, filedata, &filesize, type, &base);
-	if (add_file_to_cbfs(cbfsfile, filesize, base))
+	if (add_file_to_cbfs(cbfsfile, filesize, base)) {
+		printf("Adding file '%s' failed.\n", filename);
 		return 1;
+	}
 	if (writerom(romname, rom, romsize))
 		return 1;
 	return 0;
@@ -130,8 +132,10 @@ static int cbfs_add_payload(int argc, char **argv)
 	cbfsfile =
 	    create_cbfs_file(cbfsname, payload, &filesize,
 			     CBFS_COMPONENT_PAYLOAD, &base);
-	if (add_file_to_cbfs(cbfsfile, filesize, base))
+	if (add_file_to_cbfs(cbfsfile, filesize, base)) {
+		printf("Adding payload '%s' failed.\n", filename);
 		return 1;
+	}
 	if (writerom(romname, rom, romsize))
 		return 1;
 	return 0;
@@ -180,8 +184,10 @@ static int cbfs_add_stage(int argc, char **argv)
 	    create_cbfs_file(cbfsname, stage, &filesize,
 			     CBFS_COMPONENT_STAGE, &base);
 
-	if (add_file_to_cbfs(cbfsfile, filesize, base))
+	if (add_file_to_cbfs(cbfsfile, filesize, base)) {
+		printf("Adding stage '%s' failed.\n", filename);
 		return 1;
+	}
 	if (writerom(romname, rom, romsize))
 		return 1;
 	return 0;



From gerrit at coreboot.org  Sat Oct 15 00:27:00 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:27:00 +0200
Subject: [coreboot] New patch to review for coreboot: 6b198e3 Add ifdtool,
	utility to read / modify Intel Firmware Descriptor images
References: <Ie78b97bf573d238d0dff9a663e774deb1b7dea44+0@gerrit.coreboot.org>
Message-ID: <Ie78b97bf573d238d0dff9a663e774deb1b7dea44+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/272

-gerrit

commit 6b198e35154a58720348c3f1fb962f77f7f0550b
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 12:49:41 2011 -0700

    Add ifdtool, utility to read / modify Intel Firmware Descriptor images
    
    Change-Id: Ie78b97bf573d238d0dff9a663e774deb1b7dea44
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/ifdtool/Makefile  |   53 +++++
 util/ifdtool/ifdtool.c |  551 ++++++++++++++++++++++++++++++++++++++++++++++++
 util/ifdtool/ifdtool.h |   87 ++++++++
 3 files changed, 691 insertions(+), 0 deletions(-)

diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
new file mode 100644
index 0000000..fc8581f
--- /dev/null
+++ b/util/ifdtool/Makefile
@@ -0,0 +1,53 @@
+#
+# ifdtool - dump Intel Firmware Descriptor information
+#
+# Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+#
+
+PROGRAM = ifdtool
+
+CC      = gcc
+INSTALL = /usr/bin/install
+PREFIX  = /usr/local
+CFLAGS  = -O2 -g -Wall -W
+LDFLAGS = 
+
+OBJS = ifdtool.o
+
+all: dep $(PROGRAM)
+
+$(PROGRAM): $(OBJS)
+	$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)
+
+clean:
+	rm -f $(PROGRAM) *.o *~
+
+distclean: clean
+	rm -f .dependencies
+
+dep:
+	@$(CC) $(CFLAGS) -MM *.c > .dependencies
+
+install: $(PROGRAM)
+	mkdir -p $(DESTDIR)$(PREFIX)/bin
+	$(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin
+	mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8
+	$(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8
+
+.PHONY: all clean distclean dep 
+
+-include .dependencies
+
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
new file mode 100644
index 0000000..204c449
--- /dev/null
+++ b/util/ifdtool/ifdtool.c
@@ -0,0 +1,551 @@
+/*
+ * ifdtool - dump Intel Firmware Descriptor information
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <getopt.h>
+#include <fcntl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include "ifdtool.h"
+
+static fdbar_t *find_fd(char *image, int size)
+{
+	int i, found = 0;
+
+	/* Scan for FD signature */
+	for (i = 0; i < (size - 4); i += 4) {
+		if (*(uint32_t *) (image + i) == 0x0FF0A55A) {
+			found = 1;
+			break;	// signature found.
+		}
+	}
+
+	if (!found) {
+		printf("No Flash Descriptor found in this image\n");
+		return NULL;
+	}
+
+	printf("Found Flash Descriptor signature at 0x%08x\n", i);
+
+	return (fdbar_t *) (image + i);
+}
+
+typedef struct {
+	int base, limit, size;
+} region_t;
+
+static region_t get_region(frba_t *frba, int region_type)
+{
+	region_t region;
+	region.base = 0, region.limit = 0, region.size = 0;
+
+	switch (region_type) {
+	case 0:
+		region.base = (frba->flreg0 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg0 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	case 1:
+		region.base = (frba->flreg1 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg1 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	case 2:
+		region.base = (frba->flreg2 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg2 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	case 3:
+		region.base = (frba->flreg3 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg3 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	case 4:
+		region.base = (frba->flreg4 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg4 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	default:
+		fprintf(stderr, "Invalid region type.\n");
+		exit (EXIT_FAILURE);
+	}
+
+	region.size = region.limit - region.base + 1;
+
+	return region;
+}
+
+static const char *region_name(int region_type)
+{
+	static const char *regions[5] = {
+		"Flash Descriptor",
+		"BIOS",
+		"Intel ME",
+		"GbE",
+		"Platform Data"
+	};
+
+	if (region_type < 0 || region_type > 4) {
+		fprintf(stderr, "Invalid region type.\n");
+		exit (EXIT_FAILURE);
+	}
+
+	return regions[region_type];
+}
+
+static const char *region_filename(int region_type)
+{
+	static const char *region_filenames[5] = {
+		"flashregion_0_flashdescriptor.bin",
+		"flashregion_1_bios.bin",
+		"flashregion_2_intel_me.bin",
+		"flashregion_3_gbe.bin",
+		"flashregion_4_platform_data.bin"
+	};
+
+	if (region_type < 0 || region_type > 4) {
+		fprintf(stderr, "Invalid region type.\n");
+		exit (EXIT_FAILURE);
+	}
+
+	return region_filenames[region_type];
+}
+
+static void dump_frba(frba_t * frba)
+{
+	printf("\nFound Region Section\n");
+	printf("FLREG0:    0x%08x\n", frba->flreg0);
+	printf("FLREG1:    0x%08x\n", frba->flreg1);
+	printf("FLREG2:    0x%08x\n", frba->flreg2);
+	printf("FLREG3:    0x%08x\n", frba->flreg3);
+	printf("FLREG4:    0x%08x\n", frba->flreg4);
+}
+
+static void decode_spi_frequency(unsigned int freq)
+{
+	switch (freq) {
+	case SPI_FREQUENCY_20MHZ:
+		printf("20MHz");
+		break;
+	case SPI_FREQUENCY_33MHZ:
+		printf("33MHz");
+		break;
+	case SPI_FREQUENCY_50MHZ:
+		printf("50MHz");
+		break;
+	default:
+		printf("unknown<%x>MHz", freq);
+	}
+}
+
+static void dump_fcba(fcba_t * fcba)
+{
+	printf("\nFound Component Section\n");
+	printf("FLCOMP     0x%08x\n", fcba->flcomp);
+	printf("  Read ID/Read Status Clock Frequency: ");
+	decode_spi_frequency((fcba->flcomp >> 27) & 7);
+	printf("\n  Write/Erase Clock Frequency:         ");
+	decode_spi_frequency((fcba->flcomp >> 24) & 7);
+	printf("\n  Fast Read Clock Frequency:           ");
+	decode_spi_frequency((fcba->flcomp >> 21) & 7);
+	printf("\n");
+	printf("FLILL      0x%08x\n", fcba->flill);
+	printf("FLPB       0x%08x\n", fcba->flpb);
+}
+
+static void dump_fpsba(fpsba_t * fpsba)
+{
+	printf("\nFound PCH Strap Section\n");
+	printf("PCHSTRP0:  0x%08x\n", fpsba->pchstrp0);
+	printf("PCHSTRP1:  0x%08x\n", fpsba->pchstrp1);
+	printf("PCHSTRP2:  0x%08x\n", fpsba->pchstrp2);
+	printf("PCHSTRP3:  0x%08x\n", fpsba->pchstrp3);
+	printf("PCHSTRP4:  0x%08x\n", fpsba->pchstrp4);
+	printf("PCHSTRP5:  0x%08x\n", fpsba->pchstrp5);
+	printf("PCHSTRP6:  0x%08x\n", fpsba->pchstrp6);
+	printf("PCHSTRP7:  0x%08x\n", fpsba->pchstrp7);
+	printf("PCHSTRP8:  0x%08x\n", fpsba->pchstrp8);
+	printf("PCHSTRP9:  0x%08x\n", fpsba->pchstrp9);
+	printf("PCHSTRP10: 0x%08x\n", fpsba->pchstrp10);
+	printf("PCHSTRP11: 0x%08x\n", fpsba->pchstrp11);
+	printf("PCHSTRP12: 0x%08x\n", fpsba->pchstrp12);
+	printf("PCHSTRP13: 0x%08x\n", fpsba->pchstrp13);
+	printf("PCHSTRP14: 0x%08x\n", fpsba->pchstrp14);
+	printf("PCHSTRP15: 0x%08x\n", fpsba->pchstrp15);
+}
+
+static void dump_fmba(fmba_t * fmba)
+{
+	printf("\nFound Master Section\n");
+	printf("FLMSTR1:   0x%08x\n", fmba->flmstr1);
+	printf("FLMSTR2:   0x%08x\n", fmba->flmstr2);
+	printf("FLMSTR3:   0x%08x\n", fmba->flmstr3);
+}
+
+static void dump_fmsba(fmsba_t * fmsba)
+{
+	printf("\nFound Processor Strap Section\n");
+	printf("????:      0x%08x\n", fmsba->data[0]);
+	printf("????:      0x%08x\n", fmsba->data[1]);
+	printf("????:      0x%08x\n", fmsba->data[2]);
+	printf("????:      0x%08x\n", fmsba->data[3]);
+}
+
+static void dump_fd(char *image, int size)
+{
+	fdbar_t *fdb = find_fd(image, size);
+	if (!fdb)
+		exit(EXIT_FAILURE);
+
+	printf("FLMAP0:    0x%08x\n", fdb->flmap0);
+	printf("  NR:      %d\n", (fdb->flmap0 >> 24) & 7);
+	printf("  FRBA:    0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4);
+	printf("  NC:      %d\n", ((fdb->flmap0 >> 8) & 3) + 1);
+	printf("  FCBA:    0x%x\n", ((fdb->flmap0) & 0xff) << 4);
+
+	printf("FLMAP1:    0x%08x\n", fdb->flmap1);
+	printf("  ISL:     0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
+	printf("  FPSBA:   0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4);
+	printf("  NM:      %d\n", (fdb->flmap1 >> 8) & 3);
+	printf("  FMBA:    0x%x\n", ((fdb->flmap1) & 0xff) << 4);
+
+	printf("FLMAP2:    0x%08x\n", fdb->flmap2);
+	printf("  PSL:     0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
+	printf("  FMSBA:   0x%x\n", ((fdb->flmap2) & 0xff) << 4);
+
+	printf("FLUMAP1:   0x%08x\n", fdb->flumap1);
+
+	dump_frba((frba_t *)
+			(image + (((fdb->flmap0 >> 16) & 0xff) << 4)));
+	dump_fcba((fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4)));
+	dump_fpsba((fpsba_t *)
+			(image + (((fdb->flmap1 >> 16) & 0xff) << 4)));
+	dump_fmba((fmba_t *) (image + (((fdb->flmap1) & 0xff) << 4)));
+	dump_fmsba((fmsba_t *) (image + (((fdb->flmap2) & 0xff) << 4)));
+}
+
+static void write_regions(char *image, int size)
+{
+	int i;
+
+	fdbar_t *fdb = find_fd(image, size);
+	if (!fdb)
+		exit(EXIT_FAILURE);
+
+	frba_t *frba =
+	    (frba_t *) (image + (((fdb->flmap0 >> 16) & 0xff) << 4));
+
+	for (i = 0; i<5; i++) {
+		region_t region = get_region(frba, i);
+		printf("Flash Region %d (%s): %08x - %08x %s\n",
+		       i, region_name(i), region.base, region.limit,
+		       region.size < 1 ? "(unused)" : "");
+		if (region.size > 0) {
+			int region_fd;
+			region_fd = open(region_filename(i),
+					 O_WRONLY | O_CREAT | O_TRUNC,
+					 S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
+			if (write(region_fd, image + region.base, region.size) != region.size)
+				printf("Error while writing.");
+			close(region_fd);
+		}
+	}
+}
+
+static void write_image(char *filename, char *image, int size)
+{
+	char new_filename[FILENAME_MAX]; // allow long file names
+	int new_fd;
+
+	strncpy(new_filename, filename, FILENAME_MAX);
+	strncat(new_filename, ".new", FILENAME_MAX - strlen(filename));
+
+	printf("Writing new image to %s\n", new_filename);
+
+	// Now write out new image
+	new_fd = open(new_filename,
+			 O_WRONLY | O_CREAT | O_TRUNC,
+			 S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
+	if (write(new_fd, image, size) != size)
+		printf("Error while writing.");
+	close(new_fd);
+}
+
+static void set_spi_frequency(char *filename, char *image, int size,
+			      enum spi_frequency freq)
+{
+	fdbar_t *fdb = find_fd(image, size);
+	fcba_t *fcba = (fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4));
+
+	/* clear bits 21-29 */
+	fcba->flcomp &= ~0x3fe00000;
+	/* Read ID and Read Status Clock Frequency */
+	fcba->flcomp |= freq << 27;
+	/* Write and Erase Clock Frequency */
+	fcba->flcomp |= freq << 24;
+	/* Fast Read Clock Frequency */
+	fcba->flcomp |= freq << 21;
+
+	write_image(filename, image, size);
+}
+
+void inject_region(char *filename, char *image, int size, int region_type,
+		   char *region_fname)
+{
+	fdbar_t *fdb = find_fd(image, size);
+	if (!fdb)
+		exit(EXIT_FAILURE);
+	frba_t *frba =
+	    (frba_t *) (image + (((fdb->flmap0 >> 16) & 0xff) << 4));
+	
+	region_t region = get_region(frba, region_type);
+	if (region.size <= 0xfff) {
+		fprintf(stderr, "Region %s is disabled in target. Not injecting.\n",
+				region_name(region_type));
+		exit(EXIT_FAILURE);
+	}
+
+	int region_fd = open(region_fname, O_RDONLY);
+	if (region_fd == -1) {
+		perror("Could not open file");
+		exit(EXIT_FAILURE);
+	}
+	struct stat buf;
+	if (fstat(region_fd, &buf) == -1) {
+		perror("Could not stat file");
+		exit(EXIT_FAILURE);
+	}
+	int region_size = buf.st_size;
+
+	printf("File %s is %d bytes\n", region_fname, region_size);
+
+	if ( (region_size > region.size) || ((region_type != 1) &&
+		(region_size != region.size))) {
+		fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)"
+				" bytes. Not injecting.\n",
+				region_name(region_type), region.size,
+				region.size, region_size, region_size);
+		exit(EXIT_FAILURE);
+	}
+
+	int offset = 0;
+	if ((region_type == 1) && (region_size < region.size)) {
+		fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)"
+				" bytes. Padding before injecting.\n",
+				region_name(region_type), region.size,
+				region.size, region_size, region_size);
+		offset = region.size - region_size;
+		memset(image + region.base, 0xff, offset);
+	}
+
+	if (read(region_fd, image + region.base + offset, region_size)
+							!= region_size) {
+		perror("Could not read file");
+		exit(EXIT_FAILURE);
+	}
+
+	close(region_fd);
+
+	printf("Adding %s as the %s section of %s\n",
+	       region_fname, region_name(region_type), filename);
+	write_image(filename, image, size);
+}
+
+static void print_version(void)
+{
+	printf("ifdtool v%s -- ", IFDTOOL_VERSION);
+	printf("Copyright (C) 2011 Google Inc.\n\n");
+	printf
+	    ("This program is free software: you can redistribute it and/or modify\n"
+	     "it under the terms of the GNU General Public License as published by\n"
+	     "the Free Software Foundation, version 2 of the License.\n\n"
+	     "This program is distributed in the hope that it will be useful,\n"
+	     "but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
+	     "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n"
+	     "GNU General Public License for more details.\n\n"
+	     "You should have received a copy of the GNU General Public License\n"
+	     "along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\n");
+}
+
+static void print_usage(const char *name)
+{
+	printf("usage: %s [-vhdix?] <filename>\n", name);
+	printf("\n"
+	       "   -d | --dump:                      dump intel firmware descriptor\n"
+	       "   -x | --extract:                   extract intel fd modules\n"
+	       "   -i | --inject <region>:<module>   inject file <module> into region <region>\n"
+	       "   -s | --spifreq <20|33|50>         set the SPI frequency\n"
+	       "   -v | --version:                   print the version\n"
+	       "   -h | --help:                      print this help\n\n"
+	       "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n"
+	       "\n");
+}
+
+int main(int argc, char *argv[])
+{
+	int opt, option_index = 0;
+	int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0;
+	char *region_type_string = NULL, *region_fname = NULL;
+	int region_type = -1, inputfreq = 0;
+	enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ;
+
+	static struct option long_options[] = {
+		{"dump", 0, NULL, 'd'},
+		{"extract", 0, NULL, 'x'},
+		{"inject", 1, NULL, 'i'},
+		{"spifreq", 1, NULL, 's'},
+		{"version", 0, NULL, 'v'},
+		{"help", 0, NULL, 'h'},
+		{0, 0, 0, 0}
+	};
+
+	while ((opt = getopt_long(argc, argv, "dxi:s:vh?",
+				  long_options, &option_index)) != EOF) {
+		switch (opt) {
+		case 'd':
+			mode_dump = 1;
+			break;
+		case 'x':
+			mode_extract = 1;
+			break;
+		case 'i':
+			// separate type and file name
+			region_type_string = strdup(optarg);
+			region_fname = strchr(region_type_string, ':');
+			if (!region_fname) {
+				print_usage(argv[0]);
+				exit(EXIT_FAILURE);
+			}
+			region_fname[0] = '\0';
+			region_fname++;
+			// Descriptor, BIOS, ME, GbE, Platform
+			// valid type?
+			if (!strcasecmp("Descriptor", region_type_string))
+				region_type = 0;
+			else if (!strcasecmp("BIOS", region_type_string))
+				region_type = 1;
+			else if (!strcasecmp("ME", region_type_string))
+				region_type = 2;
+			else if (!strcasecmp("GbE", region_type_string))
+				region_type = 3;
+			else if (!strcasecmp("Platform", region_type_string))
+				region_type = 4;
+			if (region_type == -1) {
+				fprintf(stderr, "No such region type: '%s'\n\n",
+					region_type_string);
+				print_usage(argv[0]);
+				exit(EXIT_FAILURE);
+			}
+			mode_inject = 1;
+			break;
+		case 's':
+			// Parse the requested SPI frequency
+			inputfreq = strtol(optarg, NULL, 0);
+			switch (inputfreq) {
+			case 20:
+				spifreq = SPI_FREQUENCY_20MHZ;
+				break;
+			case 33:
+				spifreq = SPI_FREQUENCY_33MHZ;
+				break;
+			case 50:
+				spifreq = SPI_FREQUENCY_50MHZ;
+				break;
+			default:
+				fprintf(stderr, "Invalid SPI Frequency: %d\n",
+					inputfreq);
+				print_usage(argv[0]);
+				exit(EXIT_FAILURE);
+			}
+			mode_spifreq = 1;
+			break;
+		case 'v':
+			print_version();
+			exit(EXIT_SUCCESS);
+			break;
+		case 'h':
+		case '?':
+		default:
+			print_usage(argv[0]);
+			exit(EXIT_SUCCESS);
+			break;
+		}
+	}
+
+	if ((mode_dump + mode_extract + mode_inject + mode_spifreq) > 1) {
+		fprintf(stderr, "Only one mode allowed.\n\n");
+		print_usage(argv[0]);
+		exit(EXIT_FAILURE);
+	}
+
+	if ((mode_dump + mode_extract + mode_inject + mode_spifreq) == 0) {
+		fprintf(stderr, "You need to specify a mode.\n\n");
+		print_usage(argv[0]);
+		exit(EXIT_FAILURE);
+	}
+
+	if (optind + 1 != argc) {
+		fprintf(stderr, "You need to specify a file.\n\n");
+		print_usage(argv[0]);
+		exit(EXIT_FAILURE);
+	}
+
+	char *filename = argv[optind];
+	int bios_fd = open(filename, O_RDONLY);
+	if (bios_fd == -1) {
+		perror("Could not open file");
+		exit(EXIT_FAILURE);
+	}
+	struct stat buf;
+	if (fstat(bios_fd, &buf) == -1) {
+		perror("Could not stat file");
+		exit(EXIT_FAILURE);
+	}
+	int size = buf.st_size;
+
+	printf("File %s is %d bytes\n", filename, size);
+
+	char *image = malloc(size);
+	if (!image) {
+		printf("Out of memory.\n");
+		exit(EXIT_FAILURE);
+	}
+
+	if (read(bios_fd, image, size) != size) {
+		perror("Could not read file");
+		exit(EXIT_FAILURE);
+	}
+
+	close(bios_fd);
+
+	if (mode_dump)
+		dump_fd(image, size);
+
+	if (mode_extract)
+		write_regions(image, size);
+
+	if (mode_inject)
+		inject_region(filename, image, size, region_type,
+				region_fname);
+
+	if (mode_spifreq)
+		set_spi_frequency(filename, image, size, spifreq);
+
+	free(image);
+
+	return 0;
+}
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
new file mode 100644
index 0000000..0571534
--- /dev/null
+++ b/util/ifdtool/ifdtool.h
@@ -0,0 +1,87 @@
+/*
+ * ifdtool - dump Intel Firmware Descriptor information
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stdint.h>
+#define IFDTOOL_VERSION "1.0"
+
+enum spi_frequency {
+	SPI_FREQUENCY_20MHZ = 0,
+	SPI_FREQUENCY_33MHZ = 1,
+	SPI_FREQUENCY_50MHZ = 4,
+};
+
+// flash descriptor
+typedef struct {
+	uint32_t flvalsig;
+	uint32_t flmap0;
+	uint32_t flmap1;
+	uint32_t flmap2;
+	uint8_t  reserved[0xefc - 0x20];
+	uint32_t flumap1;
+} __attribute__((packed)) fdbar_t;
+
+// regions
+typedef struct {
+	uint32_t flreg0;
+	uint32_t flreg1;
+	uint32_t flreg2;
+	uint32_t flreg3;
+	uint32_t flreg4;
+} __attribute__((packed)) frba_t;
+
+// component section
+typedef struct {
+	uint32_t flcomp;
+	uint32_t flill;
+	uint32_t flpb;
+} __attribute__((packed)) fcba_t;
+
+// pch strap
+typedef struct {
+	uint32_t pchstrp0;
+	uint32_t pchstrp1;
+	uint32_t pchstrp2;
+	uint32_t pchstrp3;
+	uint32_t pchstrp4;
+	uint32_t pchstrp5;
+	uint32_t pchstrp6;
+	uint32_t pchstrp7;
+	uint32_t pchstrp8;
+	uint32_t pchstrp9;
+	uint32_t pchstrp10;
+	uint32_t pchstrp11;
+	uint32_t pchstrp12;
+	uint32_t pchstrp13;
+	uint32_t pchstrp14;
+	uint32_t pchstrp15;
+} __attribute__((packed)) fpsba_t;
+
+// master
+typedef struct {
+	uint32_t flmstr1;
+	uint32_t flmstr2;
+	uint32_t flmstr3;
+} __attribute__((packed)) fmba_t;
+
+// processor strap
+typedef struct {
+	uint32_t data[8];
+} __attribute__((packed)) fmsba_t;
+
+



From gerrit at coreboot.org  Sat Oct 15 00:27:01 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:27:01 +0200
Subject: [coreboot] New patch to review for coreboot: 6a8e422
	cbfs_and_run_core() is not part of the API, make it static.
References: <Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6+0@gerrit.coreboot.org>
Message-ID: <Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/273

-gerrit

commit 6a8e4225befd6f6a6e035e628cb5e12b2b23bffc
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 14:50:19 2011 -0700

    cbfs_and_run_core() is not part of the API, make it static.
    
    It's only used in cbfs_and_run.c
    
    Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/include/arch/stages.h |    1 -
 src/arch/x86/lib/cbfs_and_run.c    |    2 +-
 2 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h
index 00d2a93..3ddba51 100644
--- a/src/arch/x86/include/arch/stages.h
+++ b/src/arch/x86/include/arch/stages.h
@@ -19,7 +19,6 @@
 
 #ifndef __ARCH_STAGES_H
 #define __ARCH_STAGES_H
-void cbfs_and_run_core(const char *filename, unsigned int ebp);
 void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset);
 void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr);
 #endif
diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index 5e3d8fe..ad36ddc 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -21,7 +21,7 @@
 #include <cbfs.h>
 #include <arch/stages.h>
 
-void cbfs_and_run_core(const char *filename, unsigned ebp)
+static void cbfs_and_run_core(const char *filename, unsigned ebp)
 {
 	u8 *dst;
 



From gerrit at coreboot.org  Sat Oct 15 00:27:01 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:27:01 +0200
Subject: [coreboot] New patch to review for coreboot: 43c4af9 reformat
	Makefile.bootblock.inc (>80 lines per char)
References: <I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4+0@gerrit.coreboot.org>
Message-ID: <I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/274

-gerrit

commit 43c4af942273a396bda883d7f4f92c17f3a9c408
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 15:09:25 2011 -0700

    reformat Makefile.bootblock.inc (>80 lines per char)
    
    Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Makefile.bootblock.inc |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/Makefile.bootblock.inc b/src/arch/x86/Makefile.bootblock.inc
index f076238..806afea 100644
--- a/src/arch/x86/Makefile.bootblock.inc
+++ b/src/arch/x86/Makefile.bootblock.inc
@@ -5,7 +5,8 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	cp $(obj)/coreboot.pre1 $@
-	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \
+            $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
 #FIXME: location.txt might require an offset of header size
 
 #######################################################################



From gerrit at coreboot.org  Sat Oct 15 00:27:02 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:27:02 +0200
Subject: [coreboot] New patch to review for coreboot: 20a75ca Add macros for
	64bit byte order swapping
References: <Ic31ccd41ba3e0af7046eafc29221810d4cd196c8+0@gerrit.coreboot.org>
Message-ID: <Ic31ccd41ba3e0af7046eafc29221810d4cd196c8+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/275

-gerrit

commit 20a75ca9c0a326ab4113311f6a56dd668be4e283
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 15:11:16 2011 -0700

    Add macros for 64bit byte order swapping
    
    Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/include/arch/byteorder.h |    4 ++++
 src/include/swab.h                    |   11 +++++++++++
 2 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/include/arch/byteorder.h b/src/arch/x86/include/arch/byteorder.h
index ab344e6..7ba6290 100644
--- a/src/arch/x86/include/arch/byteorder.h
+++ b/src/arch/x86/include/arch/byteorder.h
@@ -5,10 +5,14 @@
 
 #include <swab.h>
 
+#define cpu_to_le64(x) ((unsigned long)(x))
+#define le64_to_cpu(x) ((unsigned long)(x))
 #define cpu_to_le32(x) ((unsigned int)(x))
 #define le32_to_cpu(x) ((unsigned int)(x))
 #define cpu_to_le16(x) ((unsigned short)(x))
 #define le16_to_cpu(x) ((unsigned short)(x))
+#define cpu_to_be64(x) swab64(x)
+#define be64_to_cpu(x) swab64(x)
 #define cpu_to_be32(x) swab32((x))
 #define be32_to_cpu(x) swab32((x))
 #define cpu_to_be16(x) swab16((x))
diff --git a/src/include/swab.h b/src/include/swab.h
index 3a16686..c5e4370 100644
--- a/src/include/swab.h
+++ b/src/include/swab.h
@@ -30,4 +30,15 @@
 		(((unsigned int)(x) & (unsigned int)0x00ff0000UL) >>  8) | \
 		(((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
 
+#define swab64(x) \
+	((uint64_t)( \
+		(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \
+		(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \
+		(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \
+		(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) | \
+		(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) | \
+		(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \
+		(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \
+		(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56) ))
+
 #endif /* _SWAB_H */



From gerrit at coreboot.org  Sat Oct 15 00:27:03 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:27:03 +0200
Subject: [coreboot] New patch to review for coreboot: 4c00556 use acpi.h
	include instead of manually adding acpi_slp_type.
References: <I2a3aaf10e453fa6cce8a993356f2a0587178209a+0@gerrit.coreboot.org>
Message-ID: <I2a3aaf10e453fa6cce8a993356f2a0587178209a+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/276

-gerrit

commit 4c00556c2f3a2a814c3a484f4ee924c5678037b0
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 15:18:29 2011 -0700

    use acpi.h include instead of manually adding acpi_slp_type.
    
    Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/northbridge/intel/i945/northbridge.c |    3 +--
 src/northbridge/intel/sch/northbridge.c  |    3 +--
 src/southbridge/intel/i82801gx/lpc.c     |    3 +--
 src/southbridge/via/vt8237r/lpc.c        |    4 +---
 4 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index dfe4fe7..a10bb4a 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -29,6 +29,7 @@
 #include <bitops.h>
 #include <cpu/cpu.h>
 #include <boot/tables.h>
+#include <arch/acpi.h>
 #include "chip.h"
 #include "i945.h"
 
@@ -252,8 +253,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 }
 
 #if CONFIG_HAVE_ACPI_RESUME
-extern u8 acpi_slp_type;
-
 static void northbridge_init(struct device *dev)
 {
 	switch (pci_read_config32(dev, SKPAD)) {
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index ccd0d33..7b7c67b 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -29,6 +29,7 @@
 #include <bitops.h>
 #include <cpu/cpu.h>
 #include <boot/tables.h>
+#include <arch/acpi.h>
 #include "chip.h"
 #include "sch.h"
 
@@ -267,8 +268,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 }
 
 #if CONFIG_HAVE_ACPI_RESUME
-extern u8 acpi_slp_type;
-
 static void northbridge_init(struct device *dev)
 {
 	switch (pci_read_config32(dev, SKPAD)) {
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index b4b2f41..ab3c915 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -27,6 +27,7 @@
 #include <pc80/i8259.h>
 #include <arch/io.h>
 #include <arch/ioapic.h>
+#include <arch/acpi.h>
 #include <cpu/cpu.h>
 #include "i82801gx.h"
 #include <cpu/x86/smm.h>
@@ -170,8 +171,6 @@ static void i82801gx_gpi_routing(device_t dev)
 	pci_write_config32(dev, 0xb8, reg32);
 }
 
-extern u8 acpi_slp_type;
-
 static void i82801gx_power_options(device_t dev)
 {
 	u8 reg8;
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 61f4989..3e2f215 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -32,6 +32,7 @@
 #include <pc80/keyboard.h>
 #include <pc80/i8259.h>
 #include <stdlib.h>
+#include <arch/acpi.h>
 #include "vt8237r.h"
 #include "chip.h"
 
@@ -147,9 +148,6 @@ static void pci_routing_fixup(struct device *dev)
  * This avoids having to handle any System Management Interrupts (SMIs).
  */
 
-extern u8 acpi_slp_type;
-
-
 static void setup_pm(device_t dev)
 {
 	u16 tmp;



From gerrit at coreboot.org  Sat Oct 15 00:27:04 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:27:04 +0200
Subject: [coreboot] New patch to review for coreboot: 027f405 use
	byteorder.h instead of implementing another byte swap function
References: <Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd+0@gerrit.coreboot.org>
Message-ID: <Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/277

-gerrit

commit 027f405c81ed81698bc089a742a7e05a8b3d7ad4
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 15:19:21 2011 -0700

    use byteorder.h instead of implementing another byte swap function
    
    Change-Id: Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/boot/selfboot.c |    8 +-------
 1 files changed, 1 insertions(+), 7 deletions(-)

diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index 5f7a8f1..7ae9f8c 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  */
 
+#include <arch/byteorder.h>
 #include <console/console.h>
 #include <fallback.h>
 #include <boot/elf.h>
@@ -30,13 +31,6 @@
 #include <cbfs.h>
 #include <lib.h>
 
-#if !CONFIG_BIG_ENDIAN
-#define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \
-		((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) )
-#else
-#define ntohl(x) (x)
-#endif
-
 /* Maximum physical address we can use for the coreboot bounce buffer.
  */
 #ifndef MAX_ADDR



From gerrit at coreboot.org  Sat Oct 15 00:27:08 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:27:08 +0200
Subject: [coreboot] New patch to review for coreboot: 30cb6c7 rework RTC
	driver output to make it more consistent.
References: <I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71+0@gerrit.coreboot.org>
Message-ID: <I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/278

-gerrit

commit 30cb6c723bce9cac3c8e5af1b1458352d7e68002
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 15:22:52 2011 -0700

    rework RTC driver output to make it more consistent.
    
    Also add a meaningful define (Not hooked up in Kconfig, that might
    or might not follow)
    
    Change-Id: I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/pc80/mc146818rtc.c |   13 ++++++++-----
 1 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c
index 4bbfa9e..f3bee9b 100644
--- a/src/pc80/mc146818rtc.c
+++ b/src/pc80/mc146818rtc.c
@@ -132,12 +132,14 @@ void rtc_init(int invalid)
 	checksum_invalid = !rtc_checksum_valid(PC_CKS_RANGE_START,
 			PC_CKS_RANGE_END,PC_CKS_LOC);
 
+#define CLEAR_CMOS 0
 	if (invalid || cmos_invalid || checksum_invalid) {
-		printk(BIOS_WARNING, "RTC:%s%s%s zeroing cmos\n",
+		printk(BIOS_WARNING, "RTC:%s%s%s%s\n",
 			invalid?" Clear requested":"",
 			cmos_invalid?" Power Problem":"",
-			checksum_invalid?" Checksum invalid":"");
-#if 0
+			checksum_invalid?" Checksum invalid":"",
+			CLEAR_CMOS?" zeroing cmos":"");
+#if CLEAR_CMOS
 		cmos_write(0, 0x01);
 		cmos_write(0, 0x03);
 		cmos_write(0, 0x05);
@@ -169,7 +171,7 @@ void rtc_init(int invalid)
 	checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START,
 			LB_CKS_RANGE_END,LB_CKS_LOC);
 	if(checksum_invalid)
-		printk(BIOS_DEBUG, "Invalid CMOS LB checksum\n");
+		printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n");
 
 	/* Make certain we have a valid checksum */
 	rtc_set_checksum(PC_CKS_RANGE_START,
@@ -229,7 +231,8 @@ int get_option(void *dest, const char *name)
 	/* find the requested entry record */
 	ct=cbfs_find_file("cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT);
 	if (!ct) {
-		printk(BIOS_ERR, "cmos_layout.bin could not be found. Options are disabled\n");
+		printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. "
+						"Options are disabled\n");
 		return(-2);
 	}
 	ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);



From gerrit at coreboot.org  Sat Oct 15 00:27:09 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 15 Oct 2011 00:27:09 +0200
Subject: [coreboot] New patch to review for coreboot: 7ae18c2 Fix our CMOS
	checksum algorithm so it matches what /dev/nvram expects
References: <I239f7e3aca05d3691aee16490dd801df2ccaefd1+0@gerrit.coreboot.org>
Message-ID: <I239f7e3aca05d3691aee16490dd801df2ccaefd1+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/279

-gerrit

commit 7ae18c212c2ccca0c7f4691db0bfb5c89d8ce0ac
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 15:24:03 2011 -0700

    Fix our CMOS checksum algorithm so it matches what /dev/nvram expects
    
    Our cmos checksum is inverted to what the Linux /dev/nvram device expects (and
    BIOSes use). This makes it impossible to use /dev/nvram with coreboot. Fix it!
    
    Change-Id: I239f7e3aca05d3691aee16490dd801df2ccaefd1
    Signed-off-by: Vadim Bendebury <vbendeb at google.com>
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/pc80/mc146818rtc.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c
index f3bee9b..034957a 100644
--- a/src/pc80/mc146818rtc.c
+++ b/src/pc80/mc146818rtc.c
@@ -98,7 +98,6 @@ static void rtc_set_checksum(int range_start, int range_end, int cks_loc)
 	for(i = range_start; i <= range_end; i++) {
 		sum += cmos_read(i);
 	}
-	sum = ~(sum & 0x0ffff);
 	cmos_write(((sum >> 8) & 0x0ff), cks_loc);
 	cmos_write(((sum >> 0) & 0x0ff), cks_loc+1);
 }



From gerrit at coreboot.org  Sat Oct 15 00:34:09 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 15 Oct 2011 00:34:09 +0200
Subject: [coreboot] New patch to review for coreboot: faa83fd Move linux
	2.6.11 workaround to generic code
References: <I85715ebae8a009cb816bc9ffd6372708f246bf66+0@gerrit.coreboot.org>
Message-ID: <I85715ebae8a009cb816bc9ffd6372708f246bf66+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/280

-gerrit

commit faa83fd3074371696f40629a174dad2e883a7553
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Oct 14 23:02:57 2011 +0200

    Move linux 2.6.11 workaround to generic code
    
    Linux 2.6.11 seems to require a certain order in CPUs listed in mptable,
    so enforce it. This was only done on arima/hdama, but now is generic.
    Unfortunately this is somewhat slow.
    
    Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/mpspec.c          |   15 +++++++---
 src/mainboard/arima/hdama/mptable.c |   50 +----------------------------------
 2 files changed, 12 insertions(+), 53 deletions(-)

diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c
index 209e0bb..d519cfa 100644
--- a/src/arch/x86/boot/mpspec.c
+++ b/src/arch/x86/boot/mpspec.c
@@ -134,6 +134,7 @@ void smp_write_processor(struct mp_config_table *mc,
 void smp_write_processors(struct mp_config_table *mc)
 {
 	int boot_apic_id;
+	int order_id;
 	unsigned apic_version;
 	unsigned cpu_features;
 	unsigned cpu_feature_flags;
@@ -145,6 +146,8 @@ void smp_write_processors(struct mp_config_table *mc)
 	result = cpuid(1);
 	cpu_features = result.eax;
 	cpu_feature_flags = result.edx;
+	/* order the output of the cpus to fix a bug in kernel 2.6.11 */
+	for(order_id = 0;order_id <256; order_id++) {
 	for(cpu = all_devices; cpu; cpu = cpu->next) {
 		unsigned long cpu_flag;
 		if ((cpu->path.type != DEVICE_PATH_APIC) ||
@@ -159,10 +162,14 @@ void smp_write_processors(struct mp_config_table *mc)
 		if (boot_apic_id == cpu->path.apic.apic_id) {
 			cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
 		}
-		smp_write_processor(mc,
-			cpu->path.apic.apic_id, apic_version,
-			cpu_flag, cpu_features, cpu_feature_flags
-		);
+		if(cpu->path.apic.apic_id == order_id) {
+			smp_write_processor(mc,
+				cpu->path.apic.apic_id, apic_version,
+				cpu_flag, cpu_features, cpu_feature_flags
+			);
+			break;
+		}
+            }
 	}
 }
 
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 19bbf25..466ba88 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -11,54 +11,6 @@
 #define HT_INIT_CONTROL 0x6c
 #define HTIC_BIOSR_Detect  (1<<5)
 
-/* If we assume a symmetric processor configuration we can
- * get all of the information we need to write the processor
- * entry from the bootstrap processor.
- * Plus I don't think linux really even cares.
- * Having the proper apicid's in the table so the non-bootstrap
- *  processors can be woken up should be enough.  Linux-2.6.11 work-around.
- */
-static void smp_write_processors_inorder(struct mp_config_table *mc)
-{
-        int boot_apic_id;
-	int order_id;
-        unsigned apic_version;
-        unsigned cpu_features;
-        unsigned cpu_feature_flags;
-        struct cpuid_result result;
-        device_t cpu;
-
-        boot_apic_id = lapicid();
-        apic_version = lapic_read(LAPIC_LVR) & 0xff;
-        result = cpuid(1);
-        cpu_features = result.eax;
-        cpu_feature_flags = result.edx;
-	/* order the output of the cpus to fix a bug in kernel 6 11 */
-	for(order_id = 0;order_id <256; order_id++) {
-            for(cpu = all_devices; cpu; cpu = cpu->next) {
-                unsigned long cpu_flag;
-                if ((cpu->path.type != DEVICE_PATH_APIC) ||
-                        (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
-                {
-                        continue;
-                }
-                if (!cpu->enabled) {
-                        continue;
-                }
-                cpu_flag = MPC_CPU_ENABLED;
-                if (boot_apic_id == cpu->path.apic.apic_id) {
-                        cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
-                }
-		if(cpu->path.apic.apic_id == order_id) {
-                    smp_write_processor(mc,
-                        cpu->path.apic.apic_id, apic_version,
-                        cpu_flag, cpu_features, cpu_feature_flags);
-		    break;
-		}
-            }
-	}
-}
-
 static unsigned node_link_to_bus(unsigned node, unsigned link)
 {
 	device_t dev;
@@ -125,7 +77,7 @@ static void *smp_write_config_table(void *v)
 
 	mptable_init(mc, LAPIC_ADDR);
 
-	smp_write_processors_inorder(mc);
+	smp_write_processors(mc);
 
 	apicid_base = max_apicid() + 1;
 	apicid_8111 = apicid_base;



From mopz0506 at gmail.com  Sat Oct 15 03:57:33 2011
From: mopz0506 at gmail.com (mopz0506 mopz0506)
Date: Sat, 15 Oct 2011 09:57:33 +0800
Subject: [coreboot] How to make "System Restart after Power Fail" working on
	SB800?
Message-ID: <CADBhXUTzpVWBV2XBbeXKYAn5u8XS1gQhh18Hrey29G7zBen9tA@mail.gmail.com>

Hi,

My mainboard is ASRock E350M1, it's sourthbridge is AMD SB800.

I want the machine to restart once I connect the power cable to
it, without press the POWER button on the front panel.

The ASRock's EFI BIOS can do this by set "Always Power On" to
"enable".

At present the coreboot (the cimx module) seems does not touch
"System Restart after Power Fail" feature.

If I use vendor's EFI BIOS and set "always restart after the
power is restored", then flash the coreboot to it, the box always
restart when power connected and I need not to press the POWER
button.

If I use vendor's EFI BIOS and set "keep power off after the
power is restored", then flash the coreboot to it, the box does
not up and I must press the POWER button.

If I clear the BIOS by connect the jumper to (pin1 - pin2), then
all setting lost and I must press the POWER button.

So seems the coreboot just use the setting (but never set it).

I think the code is in src\vendorcode\amd\cimx\sb800\SBPOR.c

const static AcpiRegWrite sbPmioPorInitTable[] =
    ......
{PMIO_BASE >> 8,  SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
    ......
}

and yes it does not touch the BIT1.

The BIOS Developer's Guide 3.6, P20, said I must to set
PMIO 74h [bits 1:0] to [01b] to get "always power on" working.
[00] / [10] / [11] does not work as what I hope.

So I change the line to always clean BIT1 to 0, as BDG required,

{PMIO_BASE >> 8,  SB_PMIOA_REG74, 0xF4, BIT0 + BIT3},

(just for test, I think the proper way is give a
 pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr to overwrite
 CIMX's default setting)

but it has no effect, the box keep off until I press POWER button.

before this code PMIO 24h [AcpiMMioEn] has been enabled so
MMIO working.

I checked the SB700 code src\southbridge\amd\sb700\sm.c, to see
how coreboot set "power_on_after_fail" bit in other chipset.

=================== code start =================
/* power after power fail */

on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;

get_option(&on, "power_on_after_fail");

byte = pm_ioread(0x74);

byte &= ~0x03;

if (on) {
    byte |= 2;
}

byte |= 1 << 2;

pm_iowrite(0x74, byte);

printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
=================== code end =================

what it did is a litter different and always set bit0 to 0 (CIMX set bit0
to 1, which is required by the manual):

1) clear bit[1:0] to [00b]
2) set bit[1] to [1b]
3) set bit[2] to [1b]

I don't know this code working or not since I do not own a SB700 mainboard.

If I did it on SB800 as below

{PMIO_BASE >> 8,  SB_PMIOA_REG74, 0xFC, BIT1 + BIT2},

coreboot fail to boot.

SB800 obsolete those coreboot code and replace it with new CIMX code.

I read the documents about all PM registers, and found nothing.
I search "power" in the whole .pdf, but most of them is difficult to
 understand for me.
I search the archive of mail list and seems every mainboard has different
method to set this feature.

I had tried set it on superio code (Winbond W83267hf), and does not work.

Also I observe that BIT0 is "Decen_acpi", and BIT1 is "Gbl_en_en", and
they are not "power on after power fail" bit.

Did I did anything wrong?

Did these bits need some ACPI code to working?

When the power cable connected, before I press the POWER button, the
mainboard keeps off due to the setting. in this case, the BIOS code
running or not?

Any suggesting?

Thanks for your help in advance,

mopz0506



From mopz0506 at gmail.com  Sat Oct 15 04:31:44 2011
From: mopz0506 at gmail.com (mopz0506 mopz0506)
Date: Sat, 15 Oct 2011 10:31:44 +0800
Subject: [coreboot] some url for SB700 in Wiki broken
Message-ID: <CADBhXUTd_AawaUszKkP46znb5Z3nuRK-Lswu9H9Mm=DEhhgE7A@mail.gmail.com>

Hi,

I tried to download SB700 manual and it seems broken, in this page:
http://www.coreboot.org/Datasheets#AMD_SB700.2FSB710.2FSB750

the guest disabled to edit it so I report it here.

AMD SB700/710/750 BIOS Developer?s Guide (BDG)
http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf

the new url is : http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf

AMD SB710 Databook
http://support.amd.com/us/Embedded_TechDocs/45215_sb710_ds_pub_1.25.pdf

the new url is: http://developer.amd.com/assets/45215_sb710_ds_pub_1.25.pdf

Thank you,

mopz0506



From peter at stuge.se  Sat Oct 15 04:43:29 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 15 Oct 2011 04:43:29 +0200
Subject: [coreboot] some url for SB700 in Wiki broken
In-Reply-To: <CADBhXUTd_AawaUszKkP46znb5Z3nuRK-Lswu9H9Mm=DEhhgE7A@mail.gmail.com>
References: <CADBhXUTd_AawaUszKkP46znb5Z3nuRK-Lswu9H9Mm=DEhhgE7A@mail.gmail.com>
Message-ID: <20111015024329.5841.qmail@stuge.se>

mopz0506 mopz0506 wrote:
> the new url is : http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf
> the new url is: http://developer.amd.com/assets/45215_sb710_ds_pub_1.25.pdf

I've updated all URLs for SB7x0. Thanks.


//Peter



From gerrit at coreboot.org  Sat Oct 15 07:04:04 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Sat, 15 Oct 2011 07:04:04 +0200
Subject: [coreboot] Patch set updated for coreboot: 9114cfc Fixes several
	issues with amd k8 SSDT P-state generation
References: <I61f6e2210b84ccba33a36c5efc866447b7134417+0@gerrit.coreboot.org>
Message-ID: <I61f6e2210b84ccba33a36c5efc866447b7134417+4@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/239

-gerrit

commit 9114cfc332720cedb487c140913a45cb65b9e5e1
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Thu Oct 6 18:43:43 2011 +0200

    Fixes several issues with amd k8 SSDT P-state generation
    
    First issue fixed:
    For multi-socket CPU the current implementation emitted
    Processor objects for cores in the first CPU only. This
    commit fixes the bug by really emitting one Processor
    object for each core. However, the unlikely case of mixed
    CPU models is still not handled correctly.
    
    Second issue fixed:
    One loop was wrong in case a processor in the table declares
    no P-states at all. The rewritten loop is safe. Some possibly
    dangerous array lengths were also fixed.
    
    Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV
    according to the BKDG. The current implementation always set it
    to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS.
    
    Fourth issue: If a processor without PowerNow! support was inserted in a
    system with coreboot configured with SET_FIDVID then the boot process hanged
    mysteriously and very early. Apparently because init_fidvid_ap tampers with
    non-existing registers. This commit fixes the bug by bailing out
    from init_fidvid_ap if PowerNow! capability is missing.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417
---
 src/cpu/amd/model_fxx/fidvid.c        |    6 ++-
 src/cpu/amd/model_fxx/powernow_acpi.c |   89 +++++++++++++++++++++++++--------
 2 files changed, 73 insertions(+), 22 deletions(-)

diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c
index bbafde6..6395a1e 100644
--- a/src/cpu/amd/model_fxx/fidvid.c
+++ b/src/cpu/amd/model_fxx/fidvid.c
@@ -347,13 +347,17 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
 	u32 fid_max;
 	int loop;
 
+	if((cpuid_edx(0x80000007)&0x06)!=0x06) {
+		return; /* FID/VID change not supported */
+	}
+
 	msr = rdmsr(0xc0010042);
 	fid_max = ((msr.lo >> 16) & 0x3f);	/* max fid */
 #if FX_SUPPORT
 	if (fid_max >= ((25 - 4) * 2)) {	/* FX max fid is 5G */
 		fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2;	/* maxFID = minFID + 1G */
 		if (fid_max >= ((25 - 4) * 2)) {
-			fid_max = (10 - 4) * 2;	// hard set to 2G
+			fid_max = (10 - 4) * 2;	/* hard set to 2G */
 		}
 	}
 #endif
diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index bbcf013..83d34f1 100644
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -586,15 +586,27 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	u8 cmp_cap;
 	struct cpuentry *data = NULL;
 	uint32_t control;
-	int i = 0, index, len = 0, Pstate_num = 0;
+	int i = 0, index = 0, len = 0, Pstate_num = 0, dev = 0;
 	msr_t msr;
-	u8 Pstate_fid[10];
-	u16 Pstate_feq[10];
-	u8 Pstate_vid[10];
-	u32 Pstate_power[10];
+	u8 Pstate_fid[MAXP+1];
+	u16 Pstate_feq[MAXP+1];
+	u8 Pstate_vid[MAXP+1];
+	u32 Pstate_power[MAXP+1];
 	u8 Max_fid, Start_fid, Start_vid, Max_vid;
-	struct cpuid_result cpuid1 = cpuid(0x80000001);
+	struct cpuid_result cpuid1;
+
+	/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
+	cpuid1 = cpuid(0x80000007);
+	if((cpuid1.edx & 0x6)!=0x6) {
+		printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
+		return 0;
+	}
 
+	cpuid1 = cpuid(0x80000001);
+
+	/* It has been said that we can safely assume that all CPU's
+	 * in the system have the same SYSCONF values
+	 */
 	msr = rdmsr(0xc0010042);
 	Max_fid = (msr.lo & 0x3F0000) >> 16;
 	Max_vid = (msr.hi & 0x3F0000) >> 16;
@@ -620,24 +632,51 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 		return 0;
 	}
 
-	/* IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */
-	control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (1 << 29);
+#if CONFIG_MAX_PHYSICAL_CPUS==1
+	/* IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */
+	control = (3 << 30) | (2 << 28) | (2 << 20) | (0 << 18) | (5 << 11);
+#else
+	/* MP-systems should default to RVO=0mV (no ramp voltage) */
+	/* IRT 80us RVO = 0mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */
+
+	control = (3 << 30) | (0 << 28) | (2 << 20) | (0 << 18) | (5 << 11);
+#endif
+	/* RVO (Ramp Voltage Offset)
+	 *   00   0mV (default for MP-systems)
+	 *   01  25mV
+	 *   10  50mV (default)
+	 *   11  75mV
+	 * IRT (Isochronous Release Time)
+	 *   00  10uS
+	 *   01  20uS
+	 *   10  40uS
+	 *   11  80uS (default)
+	 * MVS (Maximum Voltage Step)
+	 *   00  25mV (default)
+	 *   01  50mV (reserved)
+	 *   10 100mV (reserved)
+	 *   11 200mV (reserved)
+	 * VST (Voltage Stabilization Time)
+	 *   time = value*20uS  (default value: 5 => 100uS)
+	 * PLL_LOCK_TIME
+	 *   time = value*1uS (often seen value: 2uS)
+	 */
+
 	len = 0;
-	Pstate_num = 0;
 
-	Pstate_fid[Pstate_num] = Max_fid;
-	Pstate_feq[Pstate_num] = fid_to_freq(Max_fid);
-	Pstate_vid[Pstate_num] = Max_vid;
-	Pstate_power[Pstate_num] = data->pwr * 100;
-	Pstate_num++;
+	Pstate_fid[0] = Max_fid;
+	Pstate_feq[0] = fid_to_freq(Max_fid);
+	Pstate_vid[0] = Max_vid;
+	Pstate_power[0] = data->pwr * 100;
 
-	do {
+	for(Pstate_num = 1;
+	    (Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0);
+	    Pstate_num++) {
 		Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
 		Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz;
 		Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage);
 		Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100;
-		Pstate_num++;
-	} while ((Pstate_num < MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0));
+	}
 
 	for (i=0;i<Pstate_num;i++)
 		printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,
@@ -645,11 +684,19 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 		       vid_from_reg(Pstate_vid[i]),
 		       Pstate_power[i]);
 
-	for (index = 0; index < (cmp_cap + 1); index++) {
-		len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
-				Pstate_fid, Pstate_power, index,
-				pcontrol_blk, plen, onlyBSP, control);
+	/* Loop over all CPU's */
+	for (dev = 0x18; dev < 0x1c; dev++) {
+		if(dev_find_slot(0, PCI_DEVFN(dev, 0)) == NULL)
+			continue;
+
+		for (i = 0; i < (cmp_cap + 1); i++) {
+			len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
+					Pstate_fid, Pstate_power, index+i,
+					pcontrol_blk, plen, onlyBSP, control);
+		}
+		index += i;
 	}
+	printk(BIOS_DEBUG,"%d Processor objects emitted to SSDT\n",index);
 
 	return len;
 }



From gerrit at coreboot.org  Sat Oct 15 12:25:21 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 15 Oct 2011 12:25:21 +0200
Subject: [coreboot] Patch merged into coreboot/master: 43c4af9 reformat
	Makefile.bootblock.inc (>80 lines per char)
References: <I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4+0@gerrit.coreboot.org>
Message-ID: <E1RF1Qf-0000re-Q8@ra.coresystems.de>

the following patch was just integrated into master:
commit 43c4af942273a396bda883d7f4f92c17f3a9c408
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 15:09:25 2011 -0700

    reformat Makefile.bootblock.inc (>80 lines per char)
    
    Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4
    Signed-off-by: Stefan Reinauer <reinauer at google.com>


See http://review.coreboot.org/274 for details.

-gerrit



From gerrit at coreboot.org  Sat Oct 15 12:27:56 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 15 Oct 2011 12:27:56 +0200
Subject: [coreboot] Patch merged into coreboot/master: 6a8e422
	cbfs_and_run_core() is not part of the API, make it static.
References: <Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6+0@gerrit.coreboot.org>
Message-ID: <E1RF1TA-0004DO-UK@ra.coresystems.de>

the following patch was just integrated into master:
commit 6a8e4225befd6f6a6e035e628cb5e12b2b23bffc
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 14:50:19 2011 -0700

    cbfs_and_run_core() is not part of the API, make it static.
    
    It's only used in cbfs_and_run.c
    
    Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6
    Signed-off-by: Stefan Reinauer <reinauer at google.com>


See http://review.coreboot.org/273 for details.

-gerrit



From gerrit at coreboot.org  Sat Oct 15 12:30:04 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 15 Oct 2011 12:30:04 +0200
Subject: [coreboot] Patch merged into coreboot/master: 4c00556 use acpi.h
	include instead of manually adding acpi_slp_type.
References: <I2a3aaf10e453fa6cce8a993356f2a0587178209a+0@gerrit.coreboot.org>
Message-ID: <E1RF1VE-000865-P0@ra.coresystems.de>

the following patch was just integrated into master:
commit 4c00556c2f3a2a814c3a484f4ee924c5678037b0
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Oct 14 15:18:29 2011 -0700

    use acpi.h include instead of manually adding acpi_slp_type.
    
    Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a
    Signed-off-by: Stefan Reinauer <reinauer at google.com>


See http://review.coreboot.org/276 for details.

-gerrit



From gerrit at coreboot.org  Sat Oct 15 13:33:01 2011
From: gerrit at coreboot.org (Oskar Enoksson (enok@lysator.liu.se))
Date: Sat, 15 Oct 2011 13:33:01 +0200
Subject: [coreboot] New patch to review for coreboot: 437e073 Added block
	smbus block operations for amd8111 Fixed bug in one function
	prototype also: smbus_block_read should pass pointer to block
	length, not value. Makes no sense to me to pass a value.
References: <I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc+0@gerrit.coreboot.org>
Message-ID: <I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc+1@gerrit.coreboot.org>

Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/281

-gerrit

commit 437e07301e3239e50f842aa95fcbaf5525f1ae92
Author: Oskar Enoksson <enok at lysator.liu.se>
Date:   Fri Oct 14 02:16:48 2011 +0200

    Added block smbus block operations for amd8111
    Fixed bug in one function prototype also: smbus_block_read should
    pass pointer to block length, not value. Makes no sense to me to
    pass a value.
    
    Signed-off-by: Oskar Enoksson <enok at lysator.liu.se>
    Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc
---
 src/devices/smbus_ops.c                     |    2 +-
 src/include/device/smbus.h                  |    4 +-
 src/southbridge/amd/amd8111/acpi.c          |   25 +++++++
 src/southbridge/amd/amd8111/amd8111_smbus.h |   98 +++++++++++++++++++++++++++
 src/southbridge/amd/amd8111/early_smbus.c   |    9 +++
 5 files changed, 135 insertions(+), 3 deletions(-)

diff --git a/src/devices/smbus_ops.c b/src/devices/smbus_ops.c
index 75ca42b..d0e226f 100644
--- a/src/devices/smbus_ops.c
+++ b/src/devices/smbus_ops.c
@@ -124,7 +124,7 @@ int smbus_process_call(device_t dev, u8 cmd, u16 data)
 	return ops_smbus_bus(get_pbus_smbus(dev))->process_call(dev, cmd, data);
 }
 
-int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer)
+int smbus_block_read(device_t dev, u8 cmd, u8 *bytes, u8 *buffer)
 {
 	return ops_smbus_bus(get_pbus_smbus(dev))->block_read(dev, cmd,
 							      bytes, buffer);
diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h
index 073d7e2..bd8f8ce 100644
--- a/src/include/device/smbus.h
+++ b/src/include/device/smbus.h
@@ -17,7 +17,7 @@ struct smbus_bus_operations {
 	int (*read_word)   (device_t dev, u8 addr);
 	int (*write_word)  (device_t dev, u8 addr, u16 value);
 	int (*process_call)(device_t dev, u8 cmd, u16 data);
-	int (*block_read)  (device_t dev, u8 cmd, u8 bytes, u8 *buffer);
+	int (*block_read)  (device_t dev, u8 cmd, u8 *bytes, u8 *buffer);
 	int (*block_write) (device_t dev, u8 cmd, u8 bytes, const u8 *buffer);
 };
 
@@ -44,7 +44,7 @@ int smbus_write_byte(device_t dev, u8 addr, u8 val);
 int smbus_read_word(device_t dev, u8 addr);
 int smbus_write_word(device_t dev, u8 addr, u16 val);
 int smbus_process_call(device_t dev, u8 cmd, u16 data);
-int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer);
+int smbus_block_read(device_t dev, u8 cmd, u8 *bytes, u8 *buffer);
 int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer);
 
 #endif /* DEVICE_SMBUS_H */
diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index 2ad54b7..0c78b91 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -66,6 +66,29 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
 	return do_smbus_write_byte(res->base, device, address, val);
 }
 
+static int lsmbus_block_read(device_t dev, uint8_t cmd, u8 *bytes, u8 *buffer)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_block_read(res->base, device, cmd, bytes, buffer);
+}
+
+static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buffer)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_block_write(res->base, device, cmd, bytes, buffer);
+}
+
+
 #if CONFIG_GENERATE_ACPI_TABLES == 1
 unsigned pm_base;
 #endif
@@ -191,6 +214,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
 	.send_byte  = lsmbus_send_byte,
 	.read_byte  = lsmbus_read_byte,
 	.write_byte = lsmbus_write_byte,
+	.block_read = lsmbus_block_read,
+	.block_write= lsmbus_block_write,
 };
 
 static struct pci_operations lops_pci = {
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h
index fe9b3bf..f07893d 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.h
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.h
@@ -222,3 +222,101 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned
 	return 0;
 }
 
+static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 *bytes, u8 *buf)
+{
+	unsigned global_status_register;
+	unsigned i;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+
+	/* setup transaction */
+	/* disable interrupts */
+	outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
+	/* set the device I'm talking too */
+	outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+	/* set the command/address... */
+	outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD);
+	/* set up for a block data read */
+	outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL);
+
+	/* clear any lingering errors, so the transaction will run */
+	/* Do I need to write the bits to a 1 to clear an error? */
+	outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
+
+	/* clear the length word...*/
+	outw(0, smbus_io_base + SMBHSTDAT);
+
+	/* start the command */
+	outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inw(smbus_io_base + SMBGSTATUS);
+
+	/* read results of transaction */
+	*bytes = inw(smbus_io_base + SMBHSTDAT) & 0x3f;
+
+	if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
+		return SMBUS_ERROR;
+	}
+
+	/* read data block */
+	for(i=0; i<*bytes; i++) {
+		buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff;
+	}
+
+	return 0;
+}
+
+static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 bytes, const u8 *buf)
+{
+	unsigned global_status_register;
+	unsigned i;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+
+	/* setup transaction */
+	/* disable interrupts */
+	outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
+	/* set the device I'm talking too */
+	outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+	/* set the command/address... */
+	outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD);
+	/* set up for a block data write */
+	outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL);
+
+	/* clear any lingering errors, so the transaction will run */
+	/* Do I need to write the bits to a 1 to clear an error? */
+	outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
+
+	/* set the length word...*/
+	outw(bytes, smbus_io_base + SMBHSTDAT);
+
+	/* set the data block */
+	for(i=0; i<bytes; i++) {
+		outw(buf[i], smbus_io_base + SMBHSTFIFO);
+	}
+
+	/* start the command */
+	outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+	global_status_register = inw(smbus_io_base + SMBGSTATUS);
+
+	if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
+		return SMBUS_ERROR;
+	}
+	return 0;
+}
+
+
diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c
index e6d7084..9a58a99 100644
--- a/src/southbridge/amd/amd8111/early_smbus.c
+++ b/src/southbridge/amd/amd8111/early_smbus.c
@@ -46,3 +46,12 @@ static inline int smbus_write_byte(unsigned device, unsigned address, unsigned c
 	return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
 }
 
+static inline int smbus_block_read(unsigned device, unsigned cmd, u8 *bytes, u8 *buf)
+{
+	return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
+}
+
+static inline int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf)
+{
+	return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
+}



From gerrit at coreboot.org  Sat Oct 15 13:40:19 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 15 Oct 2011 13:40:19 +0200
Subject: [coreboot] Patch merged into coreboot/master: 4876404 AMD CPU and
	chipset fixes for compilation with gcc 4.6
References: <I05b08765b38d8d6cc9b7cbdaf87c127b33408c81+0@gerrit.coreboot.org>
Message-ID: <E1RF2bD-0004eQ-ME@ra.coresystems.de>

the following patch was just integrated into master:
commit 48764047d8720e3e6f9ae9119f8ae16b9d875cd7
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 17:04:02 2011 -0700

    AMD CPU and chipset fixes for compilation with gcc 4.6
    
    Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
    Signed-off-by: Stefan Reinauer <reinauer at google.com>


See http://review.coreboot.org/266 for details.

-gerrit



From mopz0506 at gmail.com  Sat Oct 15 13:52:44 2011
From: mopz0506 at gmail.com (mopz0506 mopz0506)
Date: Sat, 15 Oct 2011 19:52:44 +0800
Subject: [coreboot] How to make "System Restart after Power Fail"
	working on SB800?
In-Reply-To: <CADBhXUTzpVWBV2XBbeXKYAn5u8XS1gQhh18Hrey29G7zBen9tA@mail.gmail.com>
References: <CADBhXUTzpVWBV2XBbeXKYAn5u8XS1gQhh18Hrey29G7zBen9tA@mail.gmail.com>
Message-ID: <CADBhXURZhi1S=f_VpVqjJcE6NVs14k8KKrnCmS1tad=wVLvBZQ@mail.gmail.com>

Hi,

I fetch and read the RRG for SB700, found PMIO_REG74 is PwrFailShadow.

for SB800 there is no PwrFailShadow any more, instead AMD give it a
new, nonsense name, RtcShadow / RtcShawdow (typo?) and put it to
 PMIO_REG5B. Sucks.

I download SB800 BDG following URL in coreboot Wiki, PN is
 "45483_sb800_bdg_pub_3.02".

I check the SB900 code and there is a function AcLossControl(), which
 used RtcShadow to control "System Restart after Power Fail".

So I guess the BDG v3.02 for SB800 (3.6, P20) is a mistake. Maybe
someone copy & paste it from SB700 Guide (in a bugfix , Rev. 1.01,
 ha ha!)

Anyway I change

const static AcpiRegWrite sbPmioPorInitTable[] = {
   ... ...
{PMIO_BASE >> 8,  SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
   ... ...
}

to

1) {PMIO_BASE >> 8,  SB_PMIOA_REG5B, 0xF0, BIT0 + BIT2},
2) {PMIO_BASE >> 8,  SB_PMIOA_REG5B, 0xF0, BIT0 + BIT2 + BIT3},

both still does not work and I had to press POWER button.

Any idea?

Thanks,

mopz0506

On Sat, Oct 15, 2011 at 9:57 AM, mopz0506 mopz0506 <mopz0506 at gmail.com> wrote:
> Hi,
>
> My mainboard is ASRock E350M1, it's sourthbridge is AMD SB800.
>
> I want the machine to restart once I connect the power cable to
> it, without press the POWER button on the front panel.
>
> The ASRock's EFI BIOS can do this by set "Always Power On" to
> "enable".
>
> At present the coreboot (the cimx module) seems does not touch
> "System Restart after Power Fail" feature.
>
> If I use vendor's EFI BIOS and set "always restart after the
> power is restored", then flash the coreboot to it, the box always
> restart when power connected and I need not to press the POWER
> button.
>
> If I use vendor's EFI BIOS and set "keep power off after the
> power is restored", then flash the coreboot to it, the box does
> not up and I must press the POWER button.
>
> If I clear the BIOS by connect the jumper to (pin1 - pin2), then
> all setting lost and I must press the POWER button.
>
> So seems the coreboot just use the setting (but never set it).
>
> I think the code is in src\vendorcode\amd\cimx\sb800\SBPOR.c
>
> const static AcpiRegWrite sbPmioPorInitTable[] =
> ? ?......
> {PMIO_BASE >> 8, ?SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
> ? ?......
> }
>
> and yes it does not touch the BIT1.
>
> The BIOS Developer's Guide 3.6, P20, said I must to set
> PMIO 74h [bits 1:0] to [01b] to get "always power on" working.
> [00] / [10] / [11] does not work as what I hope.
>
> So I change the line to always clean BIT1 to 0, as BDG required,
>
> {PMIO_BASE >> 8, ?SB_PMIOA_REG74, 0xF4, BIT0 + BIT3},
>
> (just for test, I think the proper way is give a
> ?pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr to overwrite
> ?CIMX's default setting)
>
> but it has no effect, the box keep off until I press POWER button.
>
> before this code PMIO 24h [AcpiMMioEn] has been enabled so
> MMIO working.
>
> I checked the SB700 code src\southbridge\amd\sb700\sm.c, to see
> how coreboot set "power_on_after_fail" bit in other chipset.
>
> =================== code start =================
> /* power after power fail */
>
> on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
>
> get_option(&on, "power_on_after_fail");
>
> byte = pm_ioread(0x74);
>
> byte &= ~0x03;
>
> if (on) {
> ? ?byte |= 2;
> }
>
> byte |= 1 << 2;
>
> pm_iowrite(0x74, byte);
>
> printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
> =================== code end =================
>
> what it did is a litter different and always set bit0 to 0 (CIMX set bit0
> to 1, which is required by the manual):
>
> 1) clear bit[1:0] to [00b]
> 2) set bit[1] to [1b]
> 3) set bit[2] to [1b]
>
> I don't know this code working or not since I do not own a SB700 mainboard.
>
> If I did it on SB800 as below
>
> {PMIO_BASE >> 8, ?SB_PMIOA_REG74, 0xFC, BIT1 + BIT2},
>
> coreboot fail to boot.
>
> SB800 obsolete those coreboot code and replace it with new CIMX code.
>
> I read the documents about all PM registers, and found nothing.
> I search "power" in the whole .pdf, but most of them is difficult to
> ?understand for me.
> I search the archive of mail list and seems every mainboard has different
> method to set this feature.
>
> I had tried set it on superio code (Winbond W83267hf), and does not work.
>
> Also I observe that BIT0 is "Decen_acpi", and BIT1 is "Gbl_en_en", and
> they are not "power on after power fail" bit.
>
> Did I did anything wrong?
>
> Did these bits need some ACPI code to working?
>
> When the power cable connected, before I press the POWER button, the
> mainboard keeps off due to the setting. in this case, the BIOS code
> running or not?
>
> Any suggesting?
>
> Thanks for your help in advance,
>
> mopz0506
>



From paulepanter at users.sourceforge.net  Sat Oct 15 14:49:34 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sat, 15 Oct 2011 14:49:34 +0200
Subject: [coreboot] coreboot support for laptop HP 635 with AMD E-350 CPU:
 system data/information (flashrom, lspci, superiotool)
Message-ID: <1318682974.3714.53.camel@mattotaupa>

Dear coreboot and flashrom folks,


Carl-Daniel asked me on IRC to relay the following information to you
list subscribers.

In summary Carl-Daniel is trying to get the HP 635 laptop supported by
flashrom and to port coreboot to it. In this message you will find the
information/data/specifications [1] Carl-Daniel found out until now
attached and the URL of the file in flashrom?s file upload service. 

The HP 635 is a laptop with a AMD E-350 CPU and costs inclusive shipping
269 ? (price comparison: [2]).

flashrom runs on the system but does not find a chip [3].

        Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID
        1002:439d
        Super I/O ID 0x8518 is not on the list of flash capable
        controllers

?This means we not only have a really well-supported chipset (AMD
RS880M/A50M) the EC in that laptop ITE IT8518 is well-documented as
well. I have the IT8512 docs and they are quite extensive. Does anyone
have ITE IT8518 docs??

?Ah yes, indeed an ITE EC: The BIOS image contains "EC-V11 Copyright ITE
Tech. Inc.. This also means we can ask ITE nicely for distribution
rights without worrying about some closed bios vendor having a copyright
on that EC image.?

Output of `lspci` [4] and of `superiotool` [5] are also available.

The forced dump of the BIOS image [6] has a size of 2 MB and probably
contains some garbage. The access is restricted to a few though. The
executable of the BIOS upgrade file [7, probably different version] can
be extracted using `cabextract` [8].

Uwe noted the following.

        SCH5317 is LPC, so unlikely to be the match, yes.
        SMSC _does_ have some ECs though IIRC

Carl-Daniel will probably not have any Internet access during the next
two weeks. But I guess when getting back he would be delighted if he
receives some answer from other interested people porting the HP 635 and
he could get the documentation of the EC he asked for.

I do not know if he starts hacking and for example already works on the
flashrom support. Please join the channels #flashrom or #coreboot to get
a hold of him and discuss these issues with Carl-Daniel and the rest of
the coreboot/flashrom folks.


Thanks,

Paul


PS: Stefan, Uwe, I hope this message is what Carl-Daniel expected. If
not please correct my mistakes.


[1] http://www.coreboot.org/FAQ#Will_coreboot_work_on_my_machine.3F
[2] http://www.heise.de/preisvergleich/638422
[3] http://paste.flashrom.org/view.php?id=851
[4] http://paste.flashrom.org/view.php?id=852
[5] http://paste.flashrom.org/view.php?id=853
[6] http://paste.flashrom.org/view.php?id=854
   size: 2097152 bytes
   md5sum 31147d4d0371fb9bedc7c2cc01eb96ef
[7] ftp://ftp.hp.com/pub/softpaq/sp54001-54500/sp54155.exe
[8] http://www.cabextract.org.uk/
-------------- next part --------------
Nick: carldani
E-mail: c-d.hailfinger.devel.2006 at gmx.net
Board: HP 635 laptop (LH414EA/LH415EA)
Contents: 
flashrom v0.9.4-r1451 on Linux 2.6.32.29-0.3-pae (i686), built with libpci 3.0.1, GCC 4.3.4 [gcc-4_3-branch revision 152973], little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 2 usecs, 794M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 995 us, 10000 myus = 9974 us, 8 myus = 8 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "Hewlett-Packard"
DMI string system-product-name: "HP 635 Notebook PC              "
DMI string system-version: "058A100000004C10002600000"
DMI string baseboard-manufacturer: "Hewlett-Packard"
DMI string baseboard-product-name: "3577"
DMI string baseboard-version: "24.22"
DMI string chassis-type: "Notebook"
Laptop detected via DMI.
Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e.
========================================================================
WARNING! You seem to be running flashrom on an unsupported laptop.
Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See http://www.flashrom.org/Laptops for details.

If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Proceeding anyway because user forced us to.
Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. Enabling flash write... SPI base address is at 0xfec10000
AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0
PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1
SpiArbEnable=0, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0
NormSpeed is 16.5 MHz
GPIO11 used for SPI_DO
GPIO12 used for SPI_DI
GPIO31 used for SPI_HOLD
GPIO32 used for SPI_CS
GPIO47 used for SPI_CLK
SB700 IMC is not active.
ROM strap override is not active
OK.
This chipset supports the following protocols: LPC, FWH, SPI.
Super I/O ID 0x8518 is not on the list of flash capable controllers.
Probing for AMIC A25L05PT, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L05PU, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L10PT, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L10PU, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L20PT, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L20PU, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L40PT, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L40PU, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L80P, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L16PT, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L16PU, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L512, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L010, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L020, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L040, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L080, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L016, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25L032, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A25LQ032, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for Atmel AT25DF021, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF041A, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF081, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF081A, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF161, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF321, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF321A, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF641, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DQ161, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25F512B, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25FS010, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25FS040, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26DF041, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26DF081A, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26DF161, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26DF161A, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26F004, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45CS1282, 16896 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB011D, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB021D, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB041D, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB081D, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB161D, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB321C, 4224 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB321D, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB642D, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xe8, id2 0x23, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for EMST F25L008A, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B05, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B05T, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B10, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B10T, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B20, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B20T, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B40, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B40T, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B80, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B80T, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B16, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B16T, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B32, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B32T, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B64, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25B64T, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25F05, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25F10, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25F20, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25F40, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25F80, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25F16, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25F32, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25Q40, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25Q80(A), 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25Q16, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25Q32(A/B), 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25Q64, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25Q128, 16384 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon EN25QH16, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for Macronix MX25L512, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L1005, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L2005, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L4005, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L8005, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L1605, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L1635D, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L1635E, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L3205, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L3235D, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L6405, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L12805, 16384 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Numonyx M25PE10, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Numonyx M25PE20, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Numonyx M25PE40, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Numonyx M25PE80, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Numonyx M25PE16, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV010, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV016B, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV020, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV040, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV080B, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV512, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xe8, id2 0x23, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for Sanyo LF25FW203A, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for Spansion S25FL004A, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Spansion S25FL008A, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Spansion S25FL016A, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Spansion S25FL032A, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Spansion S25FL064A, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0xff, id2 0xff
Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0xff, id2 0xff
Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xff, id2 0xff
Probing for SST SST25VF016B, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST25VF032B, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST25VF064C, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xff, id2 0xff
Probing for SST SST25VF040B, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff
Probing for SST SST25VF080B, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xe8, id2 0x23, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x56, id2 0x8b, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xe8, id2 0x23, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xe8, id2 0x23, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content
Probing for ST M25P05-A, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P05, 64 kB: probe_spi_res1: id 0xff
Probing for ST M25P10-A, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P10, 128 kB: probe_spi_res1: id 0xff
Probing for ST M25P20, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P40, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P40-old, 512 kB: probe_spi_res1: id 0xff
Probing for ST M25P80, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P16, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P32, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P64, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P128, 16384 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25PX16, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25PX32, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25PX64, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xe8, id2 0x23, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W25Q80, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25Q16, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25Q32, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25Q64, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25Q128, 16384 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25X10, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25X20, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25X40, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25X80, 1024 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25X16, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25X32, 4096 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25X64, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xe8, id2 0x23, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xe8, id2 0x23, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x51, id2 0x59, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content
Probing for AMIC unknown AMIC SPI chip, 0 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel unknown Atmel SPI chip, 0 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Eon unknown Eon SPI chip, 0 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix unknown Macronix SPI chip, 0 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC unknown PMC SPI chip, 0 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST unknown SST SPI chip, 0 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST unknown ST SPI chip, 0 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Sanyo unknown Sanyo SPI chip, 0 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Generic unknown SPI chip (RDID), 0 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xff, id2 0xff
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
-------------- next part --------------
Nick: carldani
E-mail: c-d.hailfinger.devel.2006 at gmx.net
Board: HP 635 laptop (LH414EA/LH415EA) lspci
Contents: 
00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 14h Processor Root Complex [1022:1510]
	Subsystem: Advanced Micro Devices [AMD] Family 14h Processor Root Complex [1022:1510]
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 32
00: 22 10 10 15 06 00 20 02 00 00 00 06 00 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 10 15
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 02 20 00 00
50: 22 10 10 15 00 00 00 00 00 00 00 00 00 00 00 00
60: cd 00 00 00 00 00 04 02 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 10 00 00 03 00 00 00 00 31 20 00 00
90: 00 00 00 e0 4b 01 00 00 00 01 20 00 00 00 00 00
a0: 01 80 30 01 ef be ad de 01 00 00 00 01 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 10 00 01 01 01 12 63 80 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 80 80 00 00 00 00 00 00 00 00 00

00:01.0 VGA compatible controller [0300]: ATI Technologies Inc Wrestler [Radeon HD 6310] [1002:9802] (prog-if 00 [VGA controller])
	Subsystem: Hewlett-Packard Company Device [103c:3577]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 29
	Region 0: Memory at e0000000 (32-bit, prefetchable) [size=256M]
	Region 1: I/O ports at 4000 [size=256]
	Region 2: Memory at f0400000 (32-bit, non-prefetchable) [size=256K]
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Root Complex Integrated Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited
			ExtTag+ RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us
			ClockPM- Suprise- LLActRep- BwNot-
		LnkCtl:	ASPM Disabled; Disabled- Retrain- CommClk-
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB
	Capabilities: [a0] Message Signalled Interrupts: Mask- 64bit+ Count=1/1 Enable+
		Address: 00000000fee0300c  Data: 41b1
	Capabilities: [100] Vendor Specific Information <?>
	Kernel driver in use: fglrx_pci
	Kernel modules: fglrx
00: 02 10 02 98 07 04 10 00 00 00 00 03 10 00 80 00
10: 08 00 00 e0 01 40 00 00 00 00 40 f0 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 77 35
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 77 35
50: 01 58 03 06 00 00 00 00 10 a0 92 00 a0 8f 00 00
60: 10 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 05 00 81 00 0c 30 e0 fe 00 00 00 00 b1 41 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:01.1 Audio device [0403]: ATI Technologies Inc Wrestler HDMI Audio [Radeon HD 6250/6310] [1002:1314]
	Subsystem: Hewlett-Packard Company Device [103c:3577]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin B routed to IRQ 28
	Region 0: Memory at f0444000 (32-bit, non-prefetchable) [size=16K]
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Root Complex Integrated Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited
			ExtTag+ RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us
			ClockPM- Suprise- LLActRep- BwNot-
		LnkCtl:	ASPM Disabled; Disabled- Retrain- CommClk-
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Complian