[coreboot] New patch to review for coreboot: 37e4516 Added RAMINIT_SYSINFO. Also re-generated irq_tables.c
Oskar Enoksson (enok@lysator.liu.se)
gerrit at coreboot.org
Tue Oct 4 19:24:59 CEST 2011
Oskar Enoksson (enok at lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/236
-gerrit
commit 37e4516ea19db743daa0142ea00933586100bea5
Author: Oskar Enoksson <enok at lysator.liu.se>
Date: Tue Oct 4 16:31:20 2011 +0200
Added RAMINIT_SYSINFO. Also re-generated irq_tables.c
Signed-off-by: enok71 <enok at lysator.liu.se>
Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be
---
src/mainboard/hp/dl145_g1/Kconfig | 1 +
src/mainboard/hp/dl145_g1/get_bus_conf.c | 55 ++++-----
src/mainboard/hp/dl145_g1/irq_tables.c | 148 ++++++++-----------------
src/mainboard/hp/dl145_g1/mb_sysconf.h | 33 ++++++
src/mainboard/hp/dl145_g1/mptable.c | 37 +++----
src/mainboard/hp/dl145_g1/romstage.c | 177 +++++++++++++++---------------
6 files changed, 208 insertions(+), 243 deletions(-)
diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig
index eb90b07..ebd7ffd 100644
--- a/src/mainboard/hp/dl145_g1/Kconfig
+++ b/src/mainboard/hp/dl145_g1/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
+ select RAMINIT_SYSINFO
# select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select QRANK_DIMM_SUPPORT
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
index e4721ce..8fb52bd 100644
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -9,20 +9,12 @@
#include <cpu/amd/amdk8_sysconf.h>
#include <stdlib.h>
-
+#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_8131_0 = 1;
-unsigned char bus_8131_1 = 2;
-unsigned char bus_8131_2 = 3;
-unsigned char bus_8111_0 = 1;
-unsigned char bus_8111_1 = 4;
-unsigned apicid_8111 ;
-unsigned apicid_8131_1;
-unsigned apicid_8131_2;
-
-unsigned pci1234x[] =
+struct mb_sysconf_t mb_sysconf;
+
+static unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
@@ -34,7 +26,7 @@ unsigned pci1234x[] =
// 0x0000ff0,
// 0x0000ff0
};
-unsigned hcdnx[] =
+static unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
// 0x20202020,
@@ -45,8 +37,6 @@ unsigned hcdnx[] =
// 0x20202020,
// 0x20202020,
};
-unsigned sbdn3;
-
static unsigned get_bus_conf_done = 0;
@@ -58,11 +48,16 @@ void get_bus_conf(void)
device_t dev;
int i;
+ struct mb_sysconf_t *m;
if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1;
+ sysconf.mb = &mb_sysconf;
+
+ m = sysconf.mb;
+
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
@@ -72,36 +67,36 @@ void get_bus_conf(void)
get_sblk_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- sbdn3 = sysconf.hcdn[0] & 0xff;
+ m->sbdn3 = sysconf.hcdn[0] & 0xff;
- bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_8111_0 = bus_8131_0;
+ m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
+ m->bus_8111_0 = m->bus_8131_0;
/* 8111 */
- dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
+ dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
- bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0);
}
/* 8131-1 */
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
+ dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0));
if (dev) {
- bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0);
}
/* 8132-2 */
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
+ dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0));
if (dev) {
- bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0);
}
@@ -111,7 +106,7 @@ void get_bus_conf(void)
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
- apicid_8111 = apicid_base+0;
- apicid_8131_1 = apicid_base+1;
- apicid_8131_2 = apicid_base+2;
+ m->apicid_8111 = apicid_base+0;
+ m->apicid_8131_1 = apicid_base+1;
+ m->apicid_8131_2 = apicid_base+2;
}
diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c
index b53a992..cd5e5a7 100644
--- a/src/mainboard/hp/dl145_g1/irq_tables.c
+++ b/src/mainboard/hp/dl145_g1/irq_tables.c
@@ -1,107 +1,55 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Oskar Enoksson <enok at lysator.liu.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
- Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_8131_0;
-extern unsigned char bus_8131_1;
-extern unsigned char bus_8131_2;
-extern unsigned char bus_8111_0;
-extern unsigned char bus_8111_1;
-
-extern unsigned sbdn3;
-
-
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 9, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x07 << 3) | 0x3, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x1022, /* Vendor */
+ 0x746b, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x2d, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x07 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x0, 0x0},
+ {0x01, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0xdef8}}, 0x0, 0x0},
+ {0x01, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x03, (0x01 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0},
+ {0x03, (0x02 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x4, 0x0},
+ {0x01, (0x04 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0},
+ {0x02, (0x03 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x02, (0x01 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x03, (0x03 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}}, 0x3, 0x0},
+ }
+};
unsigned long write_pirq_routing_table(unsigned long addr)
{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
-
- uint8_t sum=0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be betweeen 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_8111_0;
- pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1022;
- pirq->rtr_device = 0x746b;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *) ( &pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
-//pcix bridge
-// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-// pirq_info++; slot_num++;
-
- pirq_info++; slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long) pirq_info;
-
+ return copy_pirq_routing_table(addr);
}
diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h
new file mode 100644
index 0000000..aecd9b6
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h
@@ -0,0 +1,33 @@
+#ifndef MB_SYSCONF_H
+
+#define MB_SYSCONF_H
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+//busnum is default
+/*
+unsigned char bus_8131_0 = 1;
+unsigned char bus_8131_1 = 2;
+unsigned char bus_8131_2 = 3;
+unsigned char bus_8111_0 = 1;
+unsigned char bus_8111_1 = 4;
+unsigned apicid_8111 ;
+unsigned apicid_8131_1;
+unsigned apicid_8131_2;
+unsigned sbdn3;
+*/
+struct mb_sysconf_t {
+ unsigned char bus_8131_0;
+ unsigned char bus_8131_1;
+ unsigned char bus_8131_2;
+ unsigned char bus_8111_0;
+ unsigned char bus_8111_1;
+
+ unsigned apicid_8111;
+ unsigned apicid_8131_1;
+ unsigned apicid_8131_2;
+
+ unsigned sbdn3;
+};
+
+#endif
+
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index 3cd9fd6..d8b1a6a 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -5,22 +5,13 @@
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_8131_0;
-extern unsigned char bus_8131_1;
-extern unsigned char bus_8131_2;
-extern unsigned char bus_8111_0;
-extern unsigned char bus_8111_1;
-extern unsigned apicid_8111;
-extern unsigned apicid_8131_1;
-extern unsigned apicid_8131_2;
-
-extern unsigned sbdn3;
+#include "mb_sysconf.h"
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
+ struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -30,31 +21,33 @@ static void *smp_write_config_table(void *v)
get_bus_conf();
+ m = sysconf.mb;
+
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
+ dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
+ smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base);
}
}
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
+ dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
+ smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base);
}
}
}
- mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
//
// The commented-out lines are auto-detected on my servers.
@@ -66,18 +59,18 @@ static void *smp_write_config_table(void *v)
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
// Integrated AMD USB
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13);
// On board ATI Rage XL
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
// On board Broadcom nics
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00);
// On board LSI SCSI
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
// PCIX-133 Slot
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index f51b4c4..7c34ff9 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -1,17 +1,17 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
+#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/amdk8.h"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/early_serial.c"
@@ -23,53 +23,45 @@
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
- } else {
- /* Ensure the CPU has control of the memory lines. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
- }
+ if (is_cpu_pre_c0()) {
+ // Set the memreset low.
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ // Ensure the BIOS has control of the memory lines.
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ } else {
+ // Ensure the CPU has control of the memory lines.
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ }
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset high. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
- udelay(90);
- }
+ if (is_cpu_pre_c0()) {
+ udelay(800);
+ // Set memreset high.
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ udelay(90);
+ }
}
#define SMBUS_HUB 0x18
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
+static inline void change_i2c_mux(unsigned device)
{
- int ret,i;
- unsigned device=(ctrl->channel0[0])>>8;
- /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
- i=2;
- do {
- ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- } while ((ret!=0) && (i-->0));
-
- smbus_write_byte(SMBUS_HUB, 0x03, 0);
+ int ret, i;
+ print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
+ i=2;
+ do {
+ ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
+ print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
+ } while ((ret!=0) && (i-->0));
+ ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
+ print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
}
-static inline void change_i2c_mux(unsigned device)
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
- int ret, i;
- print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
- i=2;
- do {
- ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
- } while ((ret!=0) && (i-->0));
- ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
- print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
+ change_i2c_mux(ctrl->channel0[0]>>8);
}
static inline int spd_read_byte(unsigned device, unsigned address)
@@ -77,6 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
+#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@@ -86,78 +79,80 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-#define RC0 ((1<<1)<<8) // Not sure about these values
-#define RC1 ((1<<2)<<8) // Not sure about these values
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const uint16_t spd_addr [] = {
- //first node
- RC0|DIMM0, RC0|DIMM2, 0, 0,
- RC0|DIMM1, RC0|DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
- RC1|DIMM0, RC1|DIMM2, 0, 0,
- RC1|DIMM1, RC1|DIMM3, 0, 0,
-#endif
- };
-
- int needs_reset;
- unsigned bsp_apicid = 0, nodes;
- struct mem_controller ctrl[8];
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ int needs_reset = 0;
+ unsigned bsp_apicid = 0;
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
+ if (bist == 0)
+ bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
+ console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+
setup_dl145g1_resource_map();
//setup_default_resource_map();
- needs_reset = setup_coherent_ht_domain();
-
- wait_all_core0_started();
+#if CONFIG_MEM_TRAIN_SEQ == 1
+ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+#endif
+ setup_coherent_ht_domain();
+ wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
+ // It is said that we should start core1 after all core0 launched
+ start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
#endif
+ ht_setup_chains_x(sysinfo);
- needs_reset |= ht_setup_chains_x();
-
- if (needs_reset) {
- print_info("ht reset -\n");
- soft_reset();
- }
-
- enable_smbus();
-
- int i;
- for(i=0;i<2;i++) {
- activate_spd_rom(&ctrl[i]);
- }
- for(i=2;i<8;i<<=1) {
- change_i2c_mux(i);
+ needs_reset |= optimize_link_coherent_ht();
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ if (needs_reset) {
+ print_info("ht reset -\n");
+ soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
- //dump_spd_registers(&ctrl[0]);
- //dump_spd_registers(&ctrl[1]);
- //dump_smbus_registers();
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- //It's the time to set ctrl now;
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- memreset_setup();
- sdram_initialize(nodes, ctrl);
+ enable_smbus();
- //dump_pci_devices();
+#define RC0 ((1<<1)<<8)
+#define RC1 ((1<<2)<<8)
+#if 0
+ change_i2c_mux(RC0>>8);
+ dump_smbus_registers();
+ change_i2c_mux(RC1>>8);
+ dump_smbus_registers();
+#endif
+ allow_all_aps_stop(bsp_apicid);
+ //It's the time to set ctrl now;
+ static const uint16_t spd_addr [] = {
+ //first node
+ RC0|DIMM0, RC0|DIMM2, 0, 0,
+ RC0|DIMM1, RC0|DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ //second node
+ RC1|DIMM0, RC1|DIMM2, 0, 0,
+ RC1|DIMM1, RC1|DIMM3, 0, 0,
+#endif
+ };
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+#if 0
+ change_i2c_mux(sysinfo->ctrl[0].channel0[0]>>8);
+ dump_spd_registers(&sysinfo->ctrl[0]);
+ change_i2c_mux(sysinfo->ctrl[1].channel0[0]>>8);
+ dump_spd_registers(&sysinfo->ctrl[1]);
+#endif
+ memreset_setup();
+ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+#if 0
+ dump_pci_devices();
+#endif
post_cache_as_ram();
}
More information about the coreboot
mailing list