[coreboot] Patch set updated for coreboot: 2e6a214 persimmon: complete the sb800 devicetree

Kerry Sheh (shekairui@gmail.com) gerrit at coreboot.org
Tue Oct 11 12:00:47 CEST 2011

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/232


commit 2e6a214fe93272b99f7bbb0c6786d8392653f412
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Oct 11 17:27:00 2011 +0800

    persimmon: complete the sb800 devicetree
    sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
    enable_dev() function. If the devicetree don't have this device,
    then sb_Before_Pci_Init will not get called.
    So the missing sb800 USB3 devicees was add to the mainboard devicetree.
    Because of no physical usb connector connected to USB3, the USB3 device setting was off.
    Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
 src/mainboard/amd/persimmon/devicetree.cb |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index 7da2169..b47e6b9 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -87,6 +87,8 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 15.1 off end # PCIe PortB
 					device pci 15.2 off end # PCIe PortC
 					device pci 15.3 off end # PCIe PortD
+					device pci 16.0 off end # OHCI USB3
+					device pci 16.2 off end # EHCI USB3
 					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb800

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