[coreboot] New patch to review for coreboot: 59f4c2c Fix compilation of VIA CN700 northbridge code with gcc 4.6

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/265

-gerrit

commit 59f4c2c0d334d96a6045ba12782c318cbda01997
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Oct 13 17:03:04 2011 -0700

    Fix compilation of VIA CN700 northbridge code with gcc 4.6
    
    Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/northbridge/via/cn700/raminit.c |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index df4010e..2c387bb 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -179,12 +179,20 @@ static void sdram_set_size(const struct mem_controller *ctrl)
 	case 0x01:
 		result = 0x10;	/* 1GB */
 		break;
+	default:
+		result = 0;
 	}
 
-	if (result == 0xff)
+	switch (result) {
+	case 0xff:
 		die("DRAM module size too big, not supported by CN700\n");
-	else
+		break;
+	case 0:
+		die("DRAM module has unknown density\n");
+		break;
+	default:
 		printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64);
+	}
 
 	pci_write_config8(ctrl->d0f3, 0x40, result);
 	pci_write_config8(ctrl->d0f3, 0x48, 0x00);