From gerrit at coreboot.org  Fri Sep  2 22:55:25 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 2 Sep 2011 22:55:25 +0200
Subject: [coreboot] New patch to review: 54caffb Fix FILO build system
References: <Iee682492f64f0f5da2a8702b8fe6f8b02c81b4c5+0@gerrit.coreboot.org>
Message-ID: <Iee682492f64f0f5da2a8702b8fe6f8b02c81b4c5+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/177

-gerrit

commit 54caffbbea39033208ace7fa6d0beef741344a7d
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Sep 2 22:44:15 2011 +0200

    Fix FILO build system
    
    This change:
    - deduplicates a whole lot of stuff in the Kconfig makefile
    - simplifies "verbose" support (V=1) to match coreboot's style
    - adds libpayload support to more kconfig targets (allyes, allno, defconfig...)
    - isolates libpayload build into its own directory to avoid file clashes
    
    Change-Id: Iee682492f64f0f5da2a8702b8fe6f8b02c81b4c5
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 Makefile              |   56 +++++-----
 util/kconfig/Makefile |  285 ++++++++++++++++---------------------------------
 2 files changed, 124 insertions(+), 217 deletions(-)

diff --git a/Makefile b/Makefile
index 2e8a9e5..1ebf62e 100644
--- a/Makefile
+++ b/Makefile
@@ -38,8 +38,11 @@ HAVE_DOTCONFIG := $(wildcard .config)
 BUILD_INFO = ($(shell whoami)@$(shell hostname)) $(shell LANG=C date)
 
 # Make is silent per default, but 'make V=1' will show all compiler calls.
+Q=@
 ifneq ($(V),1)
-Q := @
+ifneq ($(Q),)
+.SILENT:
+endif
 endif
 
 $(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile > .xcompile)))
@@ -114,52 +117,53 @@ libpayload:
 	@printf "Found Libpayload $(LIBPAYLOAD).\n"
 else
 libpayload: $(src)/$(LIB_CONFIG)
-	$(Q)printf "building libpayload.\n"
-	$(Q)make -C $(LIBCONFIG_PATH) distclean
-	$(Q)cp lib.config $(LIBCONFIG_PATH)/.config
-	$(Q)make -C $(LIBCONFIG_PATH) oldconfig
-	$(Q)make -C $(LIBCONFIG_PATH) DESTDIR=$(src)/build install
+	printf "building libpayload.\n"
+	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build distclean
+	cp lib.config $(LIBCONFIG_PATH)/.config
+	mkdir -p $(LIBCONFIG_PATH)/build
+	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build oldconfig
+	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build DESTDIR=$(src)/build install
 endif
 
 $(obj)/filo: $(src)/.config $(OBJS)  libpayload
-	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
+	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
+	$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
 
 $(TARGET): $(obj)/filo libpayload
-	$(Q)cp $(obj)/filo $@
-	$(Q)$(NM) $(obj)/filo | sort > $(obj)/filo.map
-	$(Q)printf "  STRIP   $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(STRIP) -s $@
+	cp $(obj)/filo $@
+	$(NM) $(obj)/filo | sort > $(obj)/filo.map
+	printf "  STRIP   $(subst $(shell pwd)/,,$(@))\n"
+	$(STRIP) -s $@
 
 include util/kconfig/Makefile
 
 $(obj)/%.o: $(src)/%.c libpayload
-	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
+	printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
+	$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
 
 $(obj)/%.S.o: $(src)/%.S
-	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(AS) $(ASFLAGS) -o $@ $<
+	printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
+	$(AS) $(ASFLAGS) -o $@ $<
 
 endif
 
 $(obj)/version.h: FORCE
-	$(Q)echo '#define PROGRAM_NAME "$(PROGRAM_NAME)"' > $@
-	$(Q)echo '#define PROGRAM_VERSION "$(PROGRAM_VERSION)"' >> $@
-	$(Q)echo '#define PROGRAM_VERSION_FULL "$(PROGRAM_VERSION) $(BUILD_INFO)"' >> $@
-	$(Q)echo '#define BUILD_INFO "$(BUILD_INFO)"' >> $@
+	echo '#define PROGRAM_NAME "$(PROGRAM_NAME)"' > $@
+	echo '#define PROGRAM_VERSION "$(PROGRAM_VERSION)"' >> $@
+	echo '#define PROGRAM_VERSION_FULL "$(PROGRAM_VERSION) $(BUILD_INFO)"' >> $@
+	echo '#define BUILD_INFO "$(BUILD_INFO)"' >> $@
 
 prepare:
-	$(Q)mkdir -p $(obj)/util/kconfig/lxdialog
-	$(Q)mkdir -p $(obj)/i386 $(obj)/fs $(obj)/drivers/flash
-	$(Q)mkdir -p $(obj)/main/grub
+	mkdir -p $(obj)/util/kconfig/lxdialog
+	mkdir -p $(obj)/i386 $(obj)/fs $(obj)/drivers/flash
+	mkdir -p $(obj)/main/grub
 
 clean:
-	$(Q)rm -rf $(obj)/i386 $(obj)/fs $(obj)/drivers $(obj)/main $(obj)/util
+	rm -rf $(obj)/i386 $(obj)/fs $(obj)/drivers $(obj)/main $(obj)/util
 
 distclean: clean
-	$(Q)rm -rf build
-	$(Q)rm -f .config lib.config .config.old .xcompile ..config.tmp .kconfig.d .tmpconfig*
+	rm -rf build
+	rm -f .config lib.config .config.old .xcompile ..config.tmp .kconfig.d .tmpconfig*
 
 FORCE:
 
diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile
index d6670fd..64a340c 100644
--- a/util/kconfig/Makefile
+++ b/util/kconfig/Makefile
@@ -2,7 +2,8 @@
 # Kernel configuration targets
 # These targets are used from top-level makefile
 
-PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig update-po-config
+PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig
+PHONY += randconfig allyesconfig allnoconfig allmodconfig defconfig
 
 _OS=$(shell uname -s |cut -c-7)
 regex-objs=
@@ -17,206 +18,108 @@ LIB_CONFIG  := $(src)/lib.config
 HAVE_FILO_CONFIG := $(wildcard $(FILO_CONFIG))
 HAVE_LIB_CONFIG := $(wildcard $(LIB_CONFIG))
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-xconfig: prepare $(objk)/qconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/qconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/qconf $(Kconfig)
-else
-xconfig: prepare $(objk)/qconf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
+# We don't know how to cope with FILO config being present and
+# libpayload config not.
+$(if $(and $(HAVE_FILO_CONFIG),$(filter 0,$(words $(LIB_CONFIG)))), \
+  FATAL:=1, \
+  FATAL:=0)
+
+LIBPAYLOAD_CONFIG_PRE := echo "Libpayload config for FILO." \
+    $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG) $(FILO_CONFIG).temp) \
+    $(if $(HAVE_LIB_CONFIG),; mv $(LIB_CONFIG) $(FILO_CONFIG))
+
+LIBPAYLOAD_CONFIG_POST := mv $(FILO_CONFIG) $(LIB_CONFIG) \
+        ; echo "Libpayload config done." \
+        $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG).temp $(FILO_CONFIG))
+
+ifeq ($(FATAL),1)
+xconfig gconfig menuconfig config oldconfig silentoldconfig:
+	echo "Lost libpayload config file."
+	rm -f $(FILO_CONFIG)
 else
 xconfig: prepare $(objk)/qconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/qconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/qconf $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/qconf $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/qconf $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-gconfig: prepare $(objk)/gconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/gconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/gconf $(Kconfig)
-else
-gconfig: prepare $(objk)/gconf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
 gconfig: prepare $(objk)/gconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/gconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/gconf $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/gconf $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/gconf $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-menuconfig: prepare $(objk)/mconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/mconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/mconf $(Kconfig)
-else
-menuconfig: prepare $(objk)/mconf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
 menuconfig: prepare $(objk)/mconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/mconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/mconf $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/mconf $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/mconf $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-config: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/conf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/conf $(Kconfig)
-else
-config: prepare $(objk)/conf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
 config: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/conf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/conf $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-oldconfig: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/conf -o $(Kconfig)
-else
 oldconfig: prepare $(objk)/conf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
-oldconfig: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv .config $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/conf -o $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -o $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
 silentoldconfig: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/conf -s $(Kconfig)
-else
-silentoldconfig: prepare $(objk)/conf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
-silentoldconfig: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv .config $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/conf -s $(Kconfig)
-
-endif
-
-# --- UNUSED, ignore ----------------------------------------------------------
-# Create new linux.pot file
-# Adjust charset to UTF-8 in .po file to accept UTF-8 in Kconfig files
-# The symlink is used to repair a deficiency in arch/um
-update-po-config: $(obj)/kxgettext $(obj)/gconf.glade.h
-	$(Q)echo "  GEN config"
-	$(Q)xgettext --default-domain=linux              \
-	    --add-comments --keyword=_ --keyword=N_      \
-	    --from-code=UTF-8                            \
-	    --files-from=scripts/kconfig/POTFILES.in     \
-	    --output $(obj)/config.pot
-	$(Q)sed -i s/CHARSET/UTF-8/ $(obj)/config.pot
-	$(Q)ln -fs Kconfig.i386 arch/um/Kconfig.arch
-	$(Q)(for i in `ls arch/`;                        \
-	    do                                           \
-		echo "  GEN $$i";                        \
-		$(obj)/kxgettext arch/$$i/Kconfig        \
-		     >> $(obj)/config.pot;               \
-	    done )
-	$(Q)msguniq --sort-by-file --to-code=UTF-8 $(obj)/config.pot \
-	    --output $(obj)/linux.pot
-	$(Q)rm -f arch/um/Kconfig.arch
-	$(Q)rm -f $(obj)/config.pot
-# --- UNUSED, ignore ----------------------------------------------------------
-
-PHONY += randconfig allyesconfig allnoconfig allmodconfig defconfig
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -s $(Kconfig)
 
 randconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -r $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -r $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -r $(Kconfig)
 
 allyesconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -y $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -y $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -y $(Kconfig)
 
 allnoconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -n $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -n $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -n $(Kconfig)
 
 allmodconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -m $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -m $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -m $(Kconfig)
 
 defconfig: prepare $(objk)/conf
+	$(LIBPAYLOAD_CONFIG_PRE)
 ifeq ($(KBUILD_DEFCONFIG),)
-	$(Q)$(objk)/conf -d $(Kconfig)
+	$(objk)/conf -D $(LIBCONFIG_PATH)/configs/defconfig $(LIBCONFIG_PATH)/Config.in
 else
 	@echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'"
-	$(Q)$(objk)/conf -D $(KBUILD_DEFCONFIG) $(Kconfig)
+	$(objk)/conf -D $(LIBCONFIG_PATH)/$(KBUILD_DEFCONFIG) $(LIBCONFIG_PATH)/Config.in
+endif
+	$(LIBPAYLOAD_CONFIG_POST)
+ifeq ($(KBUILD_DEFCONFIG),)
+	$(objk)/conf -d $(Kconfig)
+else
+	@echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'"
+	$(objk)/conf -D $(KBUILD_DEFCONFIG) $(Kconfig)
 endif
 
 %_defconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -D configs/$@ $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -D $(LIBCONFIG_PATH)/configs/$@ $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -D configs/$@ $(Kconfig)
+
+endif # "FATAL"
 
 # Help text used by make help
 help:
@@ -293,7 +196,7 @@ clean-files     += config.pot coreinfo.pot
 PHONY += $(objk)/dochecklxdialog
 $(addprefix $(obj)/,$(lxdialog)): $(objk)/dochecklxdialog
 $(objk)/dochecklxdialog:
-	$(Q)$(CONFIG_SHELL) $(check-lxdialog) -check $(HOSTCC) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES)
+	$(CONFIG_SHELL) $(check-lxdialog) -check $(HOSTCC) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES)
 
 always := dochecklxdialog
 
@@ -438,46 +341,46 @@ endif
 
 $(objk)/qconf: $(patsubst %,$(objk)/%,$(qconf-cxxobjs)) \
 	       $(patsubst %,$(objk)/%,$(qconf-objs))
-	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTLOADLIBES_qconf) -o $@ $^
+	$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTLOADLIBES_qconf) -o $@ $^
 $(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^
 $(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^
 $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^
 
 $(objk)/mconf.o: $(srck)/mconf.c
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
 $(objk)/conf.o: $(srck)/conf.c
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
 $(objk)/regex.o: $(srck)/regex.c
 	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -DHAVE_STRING_H -c -o $@ $<
 
 $(objk)/zconf.tab.o: $(objk)/zconf.tab.c $(objk)/lex.zconf.c \
 		     $(objk)/zconf.hash.c
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $(objk)/zconf.tab.c
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $(objk)/zconf.tab.c
 $(objk)/kconfig_load.o: $(srck)/kconfig_load.c $(objk)/lkc_defs.h
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
+	$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
 $(objk)/qconf.o: $(srck)/qconf.cc $(objk)/qconf.moc $(objk)/lkc_defs.h
-	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTCXXFLAGS_qconf.o) -c -o $@ $<
+	$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTCXXFLAGS_qconf.o) -c -o $@ $<
 $(objk)/gconf.o: $(srck)/gconf.c $(objk)/lkc_defs.h
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_gconf.o) -c -o $@ $<
+	$(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_gconf.o) -c -o $@ $<
 $(objk)/%.moc: $(srck)/%.h
-	$(Q)$(KC_QT_MOC) -i $< -o $@
+	$(KC_QT_MOC) -i $< -o $@
 $(objk)/lkc_defs.h: $(srck)/lkc_proto.h
-	$(Q)sed < $< > $@ 's/P(\([^,]*\),.*/#define \1 (\*\1_p)/'
+	sed < $< > $@ 's/P(\([^,]*\),.*/#define \1 (\*\1_p)/'
 
 $(objk)/lex.zconf.c: $(srck)/lex.zconf.c_shipped
-	$(Q)cp $< $@
+	cp $< $@
 $(objk)/zconf.hash.c: $(srck)/zconf.hash.c_shipped
-	$(Q)cp $< $@
+	cp $< $@
 $(objk)/zconf.tab.c: $(srck)/zconf.tab.c_shipped
-	$(Q)cp $< $@
+	cp $< $@
 
 $(objk)/lxdialog/lxdialog: $(objk)/dochecklxdialog \
 			   $(patsubst %,$(objk)/lxdialog/%,$(lxdialog))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) \
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) \
 		$(patsubst %,$(objk)/lxdialog/%,$(lxdialog)) -o $@
 $(objk)/lxdialog/%.o: $(srck)/lxdialog/%.c
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@
 



From gerrit at coreboot.org  Fri Sep  2 22:55:26 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 2 Sep 2011 22:55:26 +0200
Subject: [coreboot] Patch set updated: 7f65f07 Add POSIXy readdir/scandir
	support
References: <Iadc1daed3cab4cf2ead778c23ad756d36cbbb99a+0@gerrit.coreboot.org>
Message-ID: <Iadc1daed3cab4cf2ead778c23ad756d36cbbb99a+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/119

-gerrit

commit 7f65f079c80bf52ff9e2f12b3c118ad3dcb5647b
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jul 19 16:38:23 2011 +0200

    Add POSIXy readdir/scandir support
    
    This abuses the print_a_completion mechanism to build the right data
    structures to support opendir/readdir/closedir and scandir on top of
    them.
    
    It's BSD-licensed so it can eventually be moved over to libpayload.
    
    Change-Id: Iadc1daed3cab4cf2ead778c23ad756d36cbbb99a
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 fs/vfs.c                |  118 ++++++++++++++++++++++++++++++++++++++++++++++-
 include/dirent.h        |   28 +++++++++++
 include/grub/shared.h   |    2 +-
 main/grub/completions.c |   27 -----------
 4 files changed, 146 insertions(+), 29 deletions(-)

diff --git a/fs/vfs.c b/fs/vfs.c
index 49b38d8..18dbcbc 100644
--- a/fs/vfs.c
+++ b/fs/vfs.c
@@ -24,6 +24,7 @@
 #include <config.h>
 #include <fs.h>
 #include "filesys.h"
+#include <dirent.h>
 
 #define DEBUG_THIS CONFIG_DEBUG_VFS
 #include <debug.h>
@@ -241,7 +242,7 @@ void file_close(void)
 	devclose();
 }
 
-int dir(char *dirname)
+int dir(const char *dirname)
 {
 	char *dev = 0;
 	const char *path;
@@ -300,6 +301,8 @@ int dir(char *dirname)
 
 	retval = fsys->dir_func((char *) path);
 
+	print_possibilities = 0;
+
 out:
 	if (dev)
 		free(dev);
@@ -307,4 +310,117 @@ out:
 	return retval;
 }
 
+/* The following functions are BSD-L, Copyright 2011 secunet AG
+ * licensing is chosen to simplify migration to libpayload at some point */
+
+struct dirent **opendir_s;
+int opendir_ssize, opendir_selem;
+
+void print_a_completion(char *name)
+{
+	opendir_s[opendir_selem] = malloc(sizeof(struct dirent));
+	opendir_s[opendir_selem]->d_name = strdup(name);
+	opendir_selem++;
+	if (opendir_selem == opendir_ssize) {
+		opendir_ssize *= 2;
+		opendir_s = realloc(opendir_s, sizeof(struct dirent*)*opendir_ssize);
+	}
+	opendir_s[opendir_selem] = 0;
+}
+
+DIR *opendir(const char *path)
+{
+	DIR *p = malloc(sizeof(DIR));
+
+	if (opendir_s) free(opendir_s);
+	opendir_ssize = 32;
+	opendir_selem = 0;
+	opendir_s = malloc(sizeof(struct dirent*)*opendir_ssize);
+	dir(path);
+	p->items = opendir_s;
+	p->cur = opendir_s;
+	return p;
+}
+
+struct dirent *readdir(DIR *dirp)
+{
+	if (NULL == *dirp->cur) return NULL;
+
+	return *(dirp->cur++);
+}
+
+int closedir(DIR *dirp)
+{
+	if (!dirp) return -1;
+
+	struct dirent **cur = dirp->items;
+	while (*cur) {
+		free(*cur);
+		cur++;
+	}
+	free(dirp->items);
+	free(dirp);
+
+	return 0;
+}
+
+static int (*metafilter_flt)(const struct dirent *);
+static int (*metafilter_cmp)(const struct dirent **, const struct dirent **);
+
+static int metafilter(const struct dirent **a, const struct dirent **b)
+{
+	/* make sure that filtered out entries end up at the end, for simple elimination */
+	if ((metafilter_flt(*a) == 0) && (metafilter_flt(*b) == 0))
+		return 0;
+	if (metafilter_flt(*a) == 0)
+		return 1;
+	if (metafilter_flt(*b) == 0)
+		return -1;
+	return metafilter_cmp(a, b);
+}
+
+int scandir(const char *path, struct dirent ***namelist,
+	int (*filter)(const struct dirent *),
+	int (*compar)(const struct dirent **, const struct dirent **))
+{
+	DIR *dirp = opendir(path);
+
+	struct dirent **e = dirp->items;
+	int nelem = 0;
+	while (*e) {
+		nelem++;
+		e++;
+	}
+
+	if (filter) {
+		metafilter_flt = filter;
+		metafilter_cmp = compar;
+		compar = metafilter;
+	}
+
+	*namelist = malloc(sizeof(struct dirent*)*nelem);
+	memcpy(*namelist, dirp->items, sizeof(struct dirent*)*nelem);
+	qsort(*namelist, nelem, sizeof(struct dirent*), (int(*)(const void*, const void*))compar);
+
+	// if things were filtered, truncate them away
+	if (filter) {
+		int nelem2;
+		e = *namelist;
+		nelem2 = 0;
+		while ((nelem > nelem2) && filter(*e)) {
+			nelem2++;
+			e++;
+		}
+		realloc(namelist, sizeof(struct dirent**)*nelem2);
+	}
+
+	return nelem;
+}
+
+int alphasort(const struct dirent **a, const struct dirent **b)
+{
+	const struct dirent *a1 = *(const struct dirent **)(a);
+	const struct dirent *b1 = *(const struct dirent **)(b);
+	return strcmp(a1->d_name, b1->d_name);
+}
 
diff --git a/include/dirent.h b/include/dirent.h
new file mode 100644
index 0000000..19b3696
--- /dev/null
+++ b/include/dirent.h
@@ -0,0 +1,28 @@
+/* Copyright 2011 secunet AG
+ * written by Patrick Georgi <patrick.georgi at secunet.com>
+ *
+ * Licensed as BSD-L to ease migration to libpayload */
+
+#ifndef __DIRENT_H
+#define __DIRENT_H
+struct dirent {
+	char *d_name;
+};
+
+typedef struct {
+	struct dirent **items;
+	struct dirent **cur;
+} DIR;
+
+DIR *opendir(const char *path);
+struct dirent *readdir(DIR *dirp);
+int closedir(DIR *dirp); // 0 on success, -1 on error, with errno set
+
+int scandir(const char *path, struct dirent ***namelist,
+		int (*filter)(const struct dirent *),
+		int (*compar)(const struct dirent **, const struct dirent **));
+
+int alphasort(const struct dirent **a, const struct dirent **b);
+
+#endif
+
diff --git a/include/grub/shared.h b/include/grub/shared.h
index 8d876de..127b74f 100644
--- a/include/grub/shared.h
+++ b/include/grub/shared.h
@@ -295,7 +295,7 @@ void grub_putstr (const char *str);
 
 /* List the contents of the directory that was opened with GRUB_OPEN,
    printing all completions. */
-int dir (char *dirname);
+int dir (const char *dirname);
 
 /* Display device and filename completions. */
 void print_a_completion (char *filename);
diff --git a/main/grub/completions.c b/main/grub/completions.c
index 6588301..161026b 100644
--- a/main/grub/completions.c
+++ b/main/grub/completions.c
@@ -64,33 +64,6 @@ set_device (char *device)
 	return 0;
 }
 
-/* If DO_COMPLETION is true, just print NAME. Otherwise save the unique
-   part into UNIQUE_STRING.  */
-void print_a_completion(char *name)
-{
-	/* If NAME is "." or "..", do not count it.  */
-	if (strcmp(name, ".") == 0 || strcmp(name, "..") == 0)
-		return;
-
-	if (do_completion) {
-		char *buf = unique_string;
-
-		if (!unique)
-			while ((*buf++ = *name++));
-		else {
-			while (*buf && (*buf == *name)) {
-				buf++;
-				name++;
-			}
-			/* mismatch, strip it.  */
-			*buf = '\0';
-		}
-	} else
-		grub_printf(" %s", name);
-
-	unique++;
-}
-
 /*
  *  This lists the possible completions of a device string, filename, or
  *  any sane combination of the two.



From gerrit at coreboot.org  Fri Sep  2 22:55:26 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 2 Sep 2011 22:55:26 +0200
Subject: [coreboot] Patch set updated: b431050 Remove useless
	print_a_completion() stub
References: <I841d9baecbaf298114e508feec89f1b2ea864bb9+0@gerrit.coreboot.org>
Message-ID: <I841d9baecbaf298114e508feec89f1b2ea864bb9+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/118

-gerrit

commit b4310501fa616a4e5267b57adcb06fbc226a5a14
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jul 19 16:37:13 2011 +0200

    Remove useless print_a_completion() stub
    
    There's a real implementation elsewhere and this one only confuses
    things.
    
    Change-Id: I841d9baecbaf298114e508feec89f1b2ea864bb9
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 main/filo.c |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/main/filo.c b/main/filo.c
index c81d458..a8bf372 100644
--- a/main/filo.c
+++ b/main/filo.c
@@ -237,9 +237,4 @@ int main(void)
     return 0;
 }
 
-void print_a_completion (char *name)
-{
-	// Nothing yet.
-}
-
 #endif /* CONFIG_USE_GRUB */



From gerrit at coreboot.org  Fri Sep  2 22:55:26 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 2 Sep 2011 22:55:26 +0200
Subject: [coreboot] Patch set updated: f916d99 Update defconfig to silence
	build
References: <Iecc5fef8df78e66bb80b00d786aa4925f13c823a+0@gerrit.coreboot.org>
Message-ID: <Iecc5fef8df78e66bb80b00d786aa4925f13c823a+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/117

-gerrit

commit f916d994f716444edc72ec8af0c9020e16f486ea
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jul 19 16:35:34 2011 +0200

    Update defconfig to silence build
    
    Change-Id: Iecc5fef8df78e66bb80b00d786aa4925f13c823a
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 configs/defconfig |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/configs/defconfig b/configs/defconfig
index bee9611..0fe3019 100644
--- a/configs/defconfig
+++ b/configs/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # FILO version: 0.6.0
-# Fri Mar 26 12:50:23 2010
+# Thu Jul  7 11:47:53 2011
 #
 CONFIG_TARGET_I386=y
 
@@ -62,5 +62,6 @@ CONFIG_EXPERIMENTAL=y
 # CONFIG_DEBUG_PCI is not set
 # CONFIG_DEBUG_LINUXLOAD is not set
 # CONFIG_DEBUG_IDE is not set
+# CONFIG_DEBUG_USB is not set
 # CONFIG_DEBUG_ELTORITO is not set
 CONFIG_DEVELOPER_TOOLS=y



From gerrit at coreboot.org  Fri Sep  2 22:55:26 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 2 Sep 2011 22:55:26 +0200
Subject: [coreboot] Patch set updated: ad9b1d8 Adapt filo to libpayload
	changes
References: <I1c70eda7b260d7149c7079cb0d681c274f510ed8+0@gerrit.coreboot.org>
Message-ID: <I1c70eda7b260d7149c7079cb0d681c274f510ed8+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/116

-gerrit

commit ad9b1d81d3f46ccab9e7fc5570b0b8d495386547
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Fri Jul 22 10:00:38 2011 +0200

    Adapt filo to libpayload changes
    
    libpayload comes with CBFS and LZMA support now, and FILO's copy
    leads to conflicts (which is what the libpayload copy intends to solve)
    
    Change-Id: I1c70eda7b260d7149c7079cb0d681c274f510ed8
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 fs/Makefile.inc |    2 -
 fs/cbfs.c       |  236 -------------------------------------------------------
 fs/fsys_cbfs.c  |    2 +-
 include/cbfs.h  |  173 ----------------------------------------
 4 files changed, 1 insertions(+), 412 deletions(-)

diff --git a/fs/Makefile.inc b/fs/Makefile.inc
index 99c0207..4d8650b 100644
--- a/fs/Makefile.inc
+++ b/fs/Makefile.inc
@@ -31,5 +31,3 @@ TARGETS-$(CONFIG_FSYS_SQUASHFS) += fs/fsys_squashfs.o
 TARGETS-$(CONFIG_FSYS_SQUASHFS) += fs/squashfs_zlib.o
 TARGETS-$(CONFIG_ARTEC_BOOT) += fs/fsys_aboot.o
 TARGETS-$(CONFIG_FSYS_CBFS) += fs/fsys_cbfs.o
-TARGETS-$(CONFIG_FSYS_CBFS) += fs/cbfs.o
-TARGETS-$(CONFIG_FSYS_CBFS) += fs/lzma.o
diff --git a/fs/cbfs.c b/fs/cbfs.c
deleted file mode 100644
index 23e0a89..0000000
--- a/fs/cbfs.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008, Jordan Crouse <jordan at cosmicpenguin.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#include <arch/types.h>
-#include <arch/virtual.h>
-#include <cbfs.h>
-
-#define ALIGN(val,by) ((val+by-1)&~(by-1))
-#define cbfs_printf(...) /* printf(__VA_ARGS__) */
-#define printk_spew cbfs_printf
-#define printk_debug cbfs_printf
-#define printk_info cbfs_printf
-#define printk_err cbfs_printf
-
-#ifndef CONFIG_BIG_ENDIAN
-#define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \
-		((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) )
-#else
-#define ntohl(x) (x)
-#endif
-
-int cbfs_decompress(int algo, void *src, void *dst, int len)
-{
-	switch(algo) {
-	case CBFS_COMPRESS_NONE:
-		memcpy(dst, src, len);
-		return 0;
-
-	case CBFS_COMPRESS_LZMA: {
-		unsigned long ulzma(unsigned char *src, unsigned char *dst);
-		ulzma(src, dst);
-	}
-		return 0;
-
-	default:
-		printk_info( "CBFS:  Unknown compression type %d\n",
-		       algo);
-		return -1;
-	}
-}
-
-int cbfs_check_magic(struct cbfs_file *file)
-{
-	return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0;
-}
-
-struct cbfs_header *cbfs_master_header(void)
-{
-	struct cbfs_header *header;
-
-	void *ptr = phys_to_virt((void *)*((unsigned long *) phys_to_virt(CBFS_HEADPTR_ADDR)));
-	printk_spew("Check CBFS header at %p\n", ptr);
-	header = (struct cbfs_header *) ptr;
-
-	printk_spew("magic is %08x\n", ntohl(header->magic));
-	if (ntohl(header->magic) != CBFS_HEADER_MAGIC) {
-		printk_err("ERROR: No valid CBFS header found!\n");
-		return NULL;
-	}
-
-	printk_spew("Found CBFS header at %p\n", ptr);
-	return header;
-}
-
-struct cbfs_file *cbfs_find(const char *name)
-{
-	struct cbfs_header *header = cbfs_master_header();
-	unsigned long offset;
-
-	if (header == NULL)
-		return NULL;
-	offset = (unsigned long) phys_to_virt(0 - ntohl(header->romsize) + ntohl(header->offset));
-
-	int align= ntohl(header->align);
-
-	while(1) {
-		struct cbfs_file *file = (struct cbfs_file *) offset;
-		if (!cbfs_check_magic(file)) return NULL;
-		printk_debug("Check %s\n", CBFS_NAME(file));
-		if (!strcmp(CBFS_NAME(file), name))
-			return file;
-
-		int flen = ntohl(file->len);
-		int foffset = ntohl(file->offset);
-		printk_spew("CBFS: follow chain: %p + %x + %x + align -> ", (void *)offset, foffset, flen);
-
-		unsigned long oldoffset = offset;
-		offset = ALIGN(offset + foffset + flen, align);
-		printk_spew("%p\n", (void *)offset);
-		if (virt_to_phys(offset) <= virt_to_phys(oldoffset)) return NULL;
-
-		if (offset < (unsigned long)phys_to_virt(0xFFFFFFFF - ntohl(header->romsize)))
-			return NULL;
-	}
-}
-
-struct cbfs_stage *cbfs_find_file(const char *name, int type)
-{
-	struct cbfs_file *file = cbfs_find(name);
-
-	if (file == NULL) {
-		printk_info( "CBFS:  Could not find file %s\n",
-		       name);
-		return NULL;
-	}
-
-	if (ntohl(file->type) != type) {
-		printk_info( "CBFS:  File %s is of type %x instead of"
-		       "type %x\n", name, file->type, type);
-
-		return NULL;
-	}
-
-	return (void *) CBFS_SUBHEADER(file);
-}
-
-void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest)
-{
-	char name[17];
-	struct cbfs_optionrom *orom;
-	u8 *src;
-
-	sprintf(name,"pci%04x,%04x.rom", vendor, device);
-
-	orom = (struct cbfs_optionrom *)
-		cbfs_find_file(name, CBFS_TYPE_OPTIONROM);
-
-	if (orom == NULL)
-		return NULL;
-
-	/* They might have specified a dest address. If so, we can decompress. 
-	 * If not, there's not much hope of decompressing or relocating the rom.
-	 * in the common case, the expansion rom is uncompressed, we
-	 * pass 0 in for the dest, and all we have to do is find the rom and 
-	 * return a pointer to it. 
- 	 */
-
-	/* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */
-	src = ((unsigned char *) orom); // + sizeof(struct cbfs_optionrom);
-
-	if (! dest)
-		return src;
-
-	if (cbfs_decompress(ntohl(orom->compression),
-			     src,
-			     dest,
-			     ntohl(orom->len)))
-		return NULL;
-
-	return dest;
-}
-
-void * cbfs_load_stage(const char *name)
-{
-	struct cbfs_stage *stage = (struct cbfs_stage *)
-		cbfs_find_file(name, CBFS_TYPE_STAGE);
-	/* this is a mess. There is no ntohll. */
-	/* for now, assume compatible byte order until we solve this. */
-	u32 entry;
-
-	if (stage == NULL)
-		return (void *) -1;
-
-	printk_info("Stage: load %s @ %d/%d bytes, enter @ %llx\n", 
-			name,
-			(u32) stage->load, stage->memlen, 
-			stage->entry);
-	memset((void *) (u32) stage->load, 0, stage->memlen);
-
-	if (cbfs_decompress(stage->compression,
-			     ((unsigned char *) stage) +
-			     sizeof(struct cbfs_stage),
-			     (void *) (u32) stage->load,
-			     stage->len))
-		return (void *) -1;
-	printk_info("Stage: done loading.\n");
-
-	entry = stage->entry;
-//	return (void *) ntohl((u32) stage->entry);
-	return (void *) entry;
-}
-
-void * cbfs_get_file(const char *name)
-{
-	return cbfs_find(name);
-}
-
-int cbfs_execute_stage(const char *name)
-{
-	struct cbfs_stage *stage = (struct cbfs_stage *)
-		cbfs_find_file(name, CBFS_TYPE_STAGE);
-
-	if (stage == NULL)
-		return 1;
-
-	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
-		printk_info( "CBFS:  Unable to run %s:  Compressed file"
-		       "Not supported for in-place execution\n", name);
-		return 1;
-	}
-
-	/* FIXME: This isn't right */
-	printk_info( "CBFS: run @ %p\n", (void *) ntohl((u32) stage->entry));
-	return run_address((void *) ntohl((u32) stage->entry));
-}
-
-/**
- * run_address is passed the address of a function taking no parameters and
- * jumps to it, returning the result. 
- * @param f the address to call as a function. 
- * returns value returned by the function. 
- */
-
-int run_address(void *f)
-{
-	int (*v) (void);
-	v = f;
-	return v();
-}
-
diff --git a/fs/fsys_cbfs.c b/fs/fsys_cbfs.c
index 59c6e35..5c389e9 100644
--- a/fs/fsys_cbfs.c
+++ b/fs/fsys_cbfs.c
@@ -31,7 +31,7 @@ cbfs_mount (void)
     return 0;
 
   /* CBFS? */
-  if (!cbfs_master_header())
+  if (get_cbfs_header() == (void*)0xffffffff)
     return 0;
 
   return 1;
diff --git a/include/cbfs.h b/include/cbfs.h
deleted file mode 100644
index 9d6832c..0000000
--- a/include/cbfs.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_H_
-#define _CBFS_H_
-
-/** These are standard values for the known compression
-    alogrithms that coreboot knows about for stages and
-    payloads.  Of course, other LAR users can use whatever
-    values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE  0
-#define CBFS_COMPRESS_LZMA  1
-
-/** These are standard component types for well known
-    components (i.e - those that coreboot needs to consume.
-    Users are welcome to use any other value for their
-    components */
-
-#define CBFS_TYPE_STAGE     0x10
-#define CBFS_TYPE_PAYLOAD   0x20
-#define CBFS_TYPE_OPTIONROM 0x30
-
-/** this is the master cbfs header - it need to be
-    located somewhere in the bootblock.  Where it
-    actually lives is up to coreboot. A pointer to
-    this header will live at 0xFFFFFFFc, so we can
-    easily find it. */
-
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADPTR_ADDR 0xFFFFFFFc
-#define VERSION1 0x31313131
-
-struct cbfs_header {
-	u32 magic;
-        u32 version; 
-        u32 romsize;
-        u32 bootblocksize;
-	u32 align;
-	u32 offset;
-	u32 pad[2];
-} __attribute__((packed));
-
-/** This is a component header - every entry in the CBFS
-    will have this header.
-
-    This is how the component is arranged in the ROM:
-
-    --------------   <- 0
-    component header
-    --------------   <- sizeof(struct component)
-    component name
-    --------------   <- offset
-    data
-    ...
-    --------------   <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
-	char magic[8];
-	u32 len;
-	u32 type;
-	u32 checksum;
-	u32 offset;
-} __attribute__((packed));
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
-   component types */
-
-/** This is the sub-header for stage components.  Stages are
-    loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
-	u32 compression;  /** Compression type */
-	u64 entry;  /** entry point */
-	u64 load;   /** Where to load in memory */
-	u32 len;          /** length of data to load */
-	u32 memlen;	   /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components.  Payloads
-    are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
-	u32 type;
-	u32 compression;
-	u32 offset;
-	u64 load_addr;
-	u32 len;
-	u32 mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
-	struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
-#define PAYLOAD_SEGMENT_DATA   0x41544144
-#define PAYLOAD_SEGMENT_BSS    0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
-
-struct cbfs_optionrom {
-	u32 compression;
-	u32 len;
-} __attribute__((packed));
-
-#define CBFS_NAME(_c) (((char *) (_c)) + sizeof(struct cbfs_file))
-#define CBFS_SUBHEADER(_p) ( (void *) ((((u8 *) (_p)) + ntohl((_p)->offset))) )
-
-void * cbfs_load_stage(const char *name);
-int cbfs_execute_stage(const char *name);
-void * cbfs_get_file(const char *name);
-void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest);
-int run_address(void *f);
-int cbfs_decompress(int algo, void *src, void *dst, int len);
-struct cbfs_stage *cbfs_find_file(const char *name, int type);
-int cbfs_check_magic(struct cbfs_file *file);
-struct cbfs_header *cbfs_master_header(void);
-struct cbfs_file *cbfs_find(const char *name);
-void cbfs_and_run_core(char* filename, unsigned int ebp);
-
-#endif
-



From gerrit at coreboot.org  Fri Sep  2 23:07:54 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Sep 2011 23:07:54 +0200
Subject: [coreboot] Patch merged into master: ad9b1d8 Adapt filo to
	libpayload changes
References: <I1c70eda7b260d7149c7079cb0d681c274f510ed8+0@gerrit.coreboot.org>
Message-ID: <E1Qzaxu-0001k2-AH@ra.coresystems.de>

the following patch was just integrated into master:
commit ad9b1d81d3f46ccab9e7fc5570b0b8d495386547
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Fri Jul 22 10:00:38 2011 +0200

    Adapt filo to libpayload changes
    
    libpayload comes with CBFS and LZMA support now, and FILO's copy
    leads to conflicts (which is what the libpayload copy intends to solve)
    
    Change-Id: I1c70eda7b260d7149c7079cb0d681c274f510ed8
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/116 for details.

-gerrit



From gerrit at coreboot.org  Fri Sep  2 23:10:43 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 2 Sep 2011 23:10:43 +0200
Subject: [coreboot] Patch set updated: 61cd2db Fix FILO build system
References: <Iee682492f64f0f5da2a8702b8fe6f8b02c81b4c5+0@gerrit.coreboot.org>
Message-ID: <Iee682492f64f0f5da2a8702b8fe6f8b02c81b4c5+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/177

-gerrit

commit 61cd2db8ae5b41fae9e6baa015e224f55986051e
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Sep 2 22:44:15 2011 +0200

    Fix FILO build system
    
    This change:
    - deduplicates a whole lot of stuff in the Kconfig makefile
    - simplifies "verbose" support (V=1) to match coreboot's style
    - adds libpayload support to more kconfig targets (allyes, allno, defconfig...)
    - isolates libpayload build into its own directory to avoid file clashes
    
    Change-Id: Iee682492f64f0f5da2a8702b8fe6f8b02c81b4c5
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 Makefile              |   56 +++++-----
 util/kconfig/Makefile |  285 ++++++++++++++++---------------------------------
 2 files changed, 124 insertions(+), 217 deletions(-)

diff --git a/Makefile b/Makefile
index 2e8a9e5..1ebf62e 100644
--- a/Makefile
+++ b/Makefile
@@ -38,8 +38,11 @@ HAVE_DOTCONFIG := $(wildcard .config)
 BUILD_INFO = ($(shell whoami)@$(shell hostname)) $(shell LANG=C date)
 
 # Make is silent per default, but 'make V=1' will show all compiler calls.
+Q=@
 ifneq ($(V),1)
-Q := @
+ifneq ($(Q),)
+.SILENT:
+endif
 endif
 
 $(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile > .xcompile)))
@@ -114,52 +117,53 @@ libpayload:
 	@printf "Found Libpayload $(LIBPAYLOAD).\n"
 else
 libpayload: $(src)/$(LIB_CONFIG)
-	$(Q)printf "building libpayload.\n"
-	$(Q)make -C $(LIBCONFIG_PATH) distclean
-	$(Q)cp lib.config $(LIBCONFIG_PATH)/.config
-	$(Q)make -C $(LIBCONFIG_PATH) oldconfig
-	$(Q)make -C $(LIBCONFIG_PATH) DESTDIR=$(src)/build install
+	printf "building libpayload.\n"
+	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build distclean
+	cp lib.config $(LIBCONFIG_PATH)/.config
+	mkdir -p $(LIBCONFIG_PATH)/build
+	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build oldconfig
+	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build DESTDIR=$(src)/build install
 endif
 
 $(obj)/filo: $(src)/.config $(OBJS)  libpayload
-	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
+	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
+	$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
 
 $(TARGET): $(obj)/filo libpayload
-	$(Q)cp $(obj)/filo $@
-	$(Q)$(NM) $(obj)/filo | sort > $(obj)/filo.map
-	$(Q)printf "  STRIP   $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(STRIP) -s $@
+	cp $(obj)/filo $@
+	$(NM) $(obj)/filo | sort > $(obj)/filo.map
+	printf "  STRIP   $(subst $(shell pwd)/,,$(@))\n"
+	$(STRIP) -s $@
 
 include util/kconfig/Makefile
 
 $(obj)/%.o: $(src)/%.c libpayload
-	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
+	printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
+	$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
 
 $(obj)/%.S.o: $(src)/%.S
-	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(AS) $(ASFLAGS) -o $@ $<
+	printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
+	$(AS) $(ASFLAGS) -o $@ $<
 
 endif
 
 $(obj)/version.h: FORCE
-	$(Q)echo '#define PROGRAM_NAME "$(PROGRAM_NAME)"' > $@
-	$(Q)echo '#define PROGRAM_VERSION "$(PROGRAM_VERSION)"' >> $@
-	$(Q)echo '#define PROGRAM_VERSION_FULL "$(PROGRAM_VERSION) $(BUILD_INFO)"' >> $@
-	$(Q)echo '#define BUILD_INFO "$(BUILD_INFO)"' >> $@
+	echo '#define PROGRAM_NAME "$(PROGRAM_NAME)"' > $@
+	echo '#define PROGRAM_VERSION "$(PROGRAM_VERSION)"' >> $@
+	echo '#define PROGRAM_VERSION_FULL "$(PROGRAM_VERSION) $(BUILD_INFO)"' >> $@
+	echo '#define BUILD_INFO "$(BUILD_INFO)"' >> $@
 
 prepare:
-	$(Q)mkdir -p $(obj)/util/kconfig/lxdialog
-	$(Q)mkdir -p $(obj)/i386 $(obj)/fs $(obj)/drivers/flash
-	$(Q)mkdir -p $(obj)/main/grub
+	mkdir -p $(obj)/util/kconfig/lxdialog
+	mkdir -p $(obj)/i386 $(obj)/fs $(obj)/drivers/flash
+	mkdir -p $(obj)/main/grub
 
 clean:
-	$(Q)rm -rf $(obj)/i386 $(obj)/fs $(obj)/drivers $(obj)/main $(obj)/util
+	rm -rf $(obj)/i386 $(obj)/fs $(obj)/drivers $(obj)/main $(obj)/util
 
 distclean: clean
-	$(Q)rm -rf build
-	$(Q)rm -f .config lib.config .config.old .xcompile ..config.tmp .kconfig.d .tmpconfig*
+	rm -rf build
+	rm -f .config lib.config .config.old .xcompile ..config.tmp .kconfig.d .tmpconfig*
 
 FORCE:
 
diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile
index d6670fd..64a340c 100644
--- a/util/kconfig/Makefile
+++ b/util/kconfig/Makefile
@@ -2,7 +2,8 @@
 # Kernel configuration targets
 # These targets are used from top-level makefile
 
-PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig update-po-config
+PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig
+PHONY += randconfig allyesconfig allnoconfig allmodconfig defconfig
 
 _OS=$(shell uname -s |cut -c-7)
 regex-objs=
@@ -17,206 +18,108 @@ LIB_CONFIG  := $(src)/lib.config
 HAVE_FILO_CONFIG := $(wildcard $(FILO_CONFIG))
 HAVE_LIB_CONFIG := $(wildcard $(LIB_CONFIG))
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-xconfig: prepare $(objk)/qconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/qconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/qconf $(Kconfig)
-else
-xconfig: prepare $(objk)/qconf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
+# We don't know how to cope with FILO config being present and
+# libpayload config not.
+$(if $(and $(HAVE_FILO_CONFIG),$(filter 0,$(words $(LIB_CONFIG)))), \
+  FATAL:=1, \
+  FATAL:=0)
+
+LIBPAYLOAD_CONFIG_PRE := echo "Libpayload config for FILO." \
+    $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG) $(FILO_CONFIG).temp) \
+    $(if $(HAVE_LIB_CONFIG),; mv $(LIB_CONFIG) $(FILO_CONFIG))
+
+LIBPAYLOAD_CONFIG_POST := mv $(FILO_CONFIG) $(LIB_CONFIG) \
+        ; echo "Libpayload config done." \
+        $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG).temp $(FILO_CONFIG))
+
+ifeq ($(FATAL),1)
+xconfig gconfig menuconfig config oldconfig silentoldconfig:
+	echo "Lost libpayload config file."
+	rm -f $(FILO_CONFIG)
 else
 xconfig: prepare $(objk)/qconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/qconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/qconf $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/qconf $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/qconf $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-gconfig: prepare $(objk)/gconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/gconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/gconf $(Kconfig)
-else
-gconfig: prepare $(objk)/gconf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
 gconfig: prepare $(objk)/gconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/gconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/gconf $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/gconf $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/gconf $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-menuconfig: prepare $(objk)/mconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/mconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/mconf $(Kconfig)
-else
-menuconfig: prepare $(objk)/mconf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
 menuconfig: prepare $(objk)/mconf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/mconf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/mconf $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/mconf $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/mconf $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-config: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/conf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/conf $(Kconfig)
-else
-config: prepare $(objk)/conf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
 config: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/conf $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/conf $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
-oldconfig: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/conf -o $(Kconfig)
-else
 oldconfig: prepare $(objk)/conf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
-oldconfig: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv .config $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/conf -o $(Kconfig)
-endif
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -o $(Kconfig)
 
-ifneq ($(strip $(HAVE_FILO_CONFIG)),)
-ifneq ($(strip $(HAVE_LIB_CONFIG)),)
 silentoldconfig: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp"
-	$(Q)mv $(LIB_CONFIG) $(FILO_CONFIG)
-	$(Q)$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv $(FILO_CONFIG) $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG)
-	$(Q)$(objk)/conf -s $(Kconfig)
-else
-silentoldconfig: prepare $(objk)/conf
-	$(Q)printf "Lost libpayload config file.\n"
-	$(Q)rm -f $(FILO_CONFIG)
-endif
-else
-silentoldconfig: prepare $(objk)/conf
-	$(Q)printf "Libpayload config for FILO.\n"
-	$(Q)$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in
-	$(Q)mv .config $(LIB_CONFIG)
-	$(Q)printf "Libpayload config done.\n"
-	$(Q)$(objk)/conf -s $(Kconfig)
-
-endif
-
-# --- UNUSED, ignore ----------------------------------------------------------
-# Create new linux.pot file
-# Adjust charset to UTF-8 in .po file to accept UTF-8 in Kconfig files
-# The symlink is used to repair a deficiency in arch/um
-update-po-config: $(obj)/kxgettext $(obj)/gconf.glade.h
-	$(Q)echo "  GEN config"
-	$(Q)xgettext --default-domain=linux              \
-	    --add-comments --keyword=_ --keyword=N_      \
-	    --from-code=UTF-8                            \
-	    --files-from=scripts/kconfig/POTFILES.in     \
-	    --output $(obj)/config.pot
-	$(Q)sed -i s/CHARSET/UTF-8/ $(obj)/config.pot
-	$(Q)ln -fs Kconfig.i386 arch/um/Kconfig.arch
-	$(Q)(for i in `ls arch/`;                        \
-	    do                                           \
-		echo "  GEN $$i";                        \
-		$(obj)/kxgettext arch/$$i/Kconfig        \
-		     >> $(obj)/config.pot;               \
-	    done )
-	$(Q)msguniq --sort-by-file --to-code=UTF-8 $(obj)/config.pot \
-	    --output $(obj)/linux.pot
-	$(Q)rm -f arch/um/Kconfig.arch
-	$(Q)rm -f $(obj)/config.pot
-# --- UNUSED, ignore ----------------------------------------------------------
-
-PHONY += randconfig allyesconfig allnoconfig allmodconfig defconfig
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -s $(Kconfig)
 
 randconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -r $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -r $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -r $(Kconfig)
 
 allyesconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -y $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -y $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -y $(Kconfig)
 
 allnoconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -n $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -n $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -n $(Kconfig)
 
 allmodconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -m $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -m $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -m $(Kconfig)
 
 defconfig: prepare $(objk)/conf
+	$(LIBPAYLOAD_CONFIG_PRE)
 ifeq ($(KBUILD_DEFCONFIG),)
-	$(Q)$(objk)/conf -d $(Kconfig)
+	$(objk)/conf -D $(LIBCONFIG_PATH)/configs/defconfig $(LIBCONFIG_PATH)/Config.in
 else
 	@echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'"
-	$(Q)$(objk)/conf -D $(KBUILD_DEFCONFIG) $(Kconfig)
+	$(objk)/conf -D $(LIBCONFIG_PATH)/$(KBUILD_DEFCONFIG) $(LIBCONFIG_PATH)/Config.in
+endif
+	$(LIBPAYLOAD_CONFIG_POST)
+ifeq ($(KBUILD_DEFCONFIG),)
+	$(objk)/conf -d $(Kconfig)
+else
+	@echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'"
+	$(objk)/conf -D $(KBUILD_DEFCONFIG) $(Kconfig)
 endif
 
 %_defconfig: prepare $(objk)/conf
-	$(Q)$(objk)/conf -D configs/$@ $(Kconfig)
+	$(LIBPAYLOAD_CONFIG_PRE)
+	$(objk)/conf -D $(LIBCONFIG_PATH)/configs/$@ $(LIBCONFIG_PATH)/Config.in
+	$(LIBPAYLOAD_CONFIG_POST)
+	$(objk)/conf -D configs/$@ $(Kconfig)
+
+endif # "FATAL"
 
 # Help text used by make help
 help:
@@ -293,7 +196,7 @@ clean-files     += config.pot coreinfo.pot
 PHONY += $(objk)/dochecklxdialog
 $(addprefix $(obj)/,$(lxdialog)): $(objk)/dochecklxdialog
 $(objk)/dochecklxdialog:
-	$(Q)$(CONFIG_SHELL) $(check-lxdialog) -check $(HOSTCC) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES)
+	$(CONFIG_SHELL) $(check-lxdialog) -check $(HOSTCC) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES)
 
 always := dochecklxdialog
 
@@ -438,46 +341,46 @@ endif
 
 $(objk)/qconf: $(patsubst %,$(objk)/%,$(qconf-cxxobjs)) \
 	       $(patsubst %,$(objk)/%,$(qconf-objs))
-	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTLOADLIBES_qconf) -o $@ $^
+	$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTLOADLIBES_qconf) -o $@ $^
 $(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^
 $(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^
 $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^
 
 $(objk)/mconf.o: $(srck)/mconf.c
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
 $(objk)/conf.o: $(srck)/conf.c
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
 $(objk)/regex.o: $(srck)/regex.c
 	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -DHAVE_STRING_H -c -o $@ $<
 
 $(objk)/zconf.tab.o: $(objk)/zconf.tab.c $(objk)/lex.zconf.c \
 		     $(objk)/zconf.hash.c
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $(objk)/zconf.tab.c
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $(objk)/zconf.tab.c
 $(objk)/kconfig_load.o: $(srck)/kconfig_load.c $(objk)/lkc_defs.h
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
+	$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
 $(objk)/qconf.o: $(srck)/qconf.cc $(objk)/qconf.moc $(objk)/lkc_defs.h
-	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTCXXFLAGS_qconf.o) -c -o $@ $<
+	$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTCXXFLAGS_qconf.o) -c -o $@ $<
 $(objk)/gconf.o: $(srck)/gconf.c $(objk)/lkc_defs.h
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_gconf.o) -c -o $@ $<
+	$(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_gconf.o) -c -o $@ $<
 $(objk)/%.moc: $(srck)/%.h
-	$(Q)$(KC_QT_MOC) -i $< -o $@
+	$(KC_QT_MOC) -i $< -o $@
 $(objk)/lkc_defs.h: $(srck)/lkc_proto.h
-	$(Q)sed < $< > $@ 's/P(\([^,]*\),.*/#define \1 (\*\1_p)/'
+	sed < $< > $@ 's/P(\([^,]*\),.*/#define \1 (\*\1_p)/'
 
 $(objk)/lex.zconf.c: $(srck)/lex.zconf.c_shipped
-	$(Q)cp $< $@
+	cp $< $@
 $(objk)/zconf.hash.c: $(srck)/zconf.hash.c_shipped
-	$(Q)cp $< $@
+	cp $< $@
 $(objk)/zconf.tab.c: $(srck)/zconf.tab.c_shipped
-	$(Q)cp $< $@
+	cp $< $@
 
 $(objk)/lxdialog/lxdialog: $(objk)/dochecklxdialog \
 			   $(patsubst %,$(objk)/lxdialog/%,$(lxdialog))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) \
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) \
 		$(patsubst %,$(objk)/lxdialog/%,$(lxdialog)) -o $@
 $(objk)/lxdialog/%.o: $(srck)/lxdialog/%.c
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@
 



From gerrit at coreboot.org  Fri Sep  2 23:22:29 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Sep 2011 23:22:29 +0200
Subject: [coreboot] Patch merged into master: 61cd2db Fix FILO build system
References: <Iee682492f64f0f5da2a8702b8fe6f8b02c81b4c5+0@gerrit.coreboot.org>
Message-ID: <E1QzbC1-0005XU-DF@ra.coresystems.de>

the following patch was just integrated into master:
commit 61cd2db8ae5b41fae9e6baa015e224f55986051e
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Sep 2 22:44:15 2011 +0200

    Fix FILO build system
    
    This change:
    - deduplicates a whole lot of stuff in the Kconfig makefile
    - simplifies "verbose" support (V=1) to match coreboot's style
    - adds libpayload support to more kconfig targets (allyes, allno, defconfig...)
    - isolates libpayload build into its own directory to avoid file clashes
    
    Change-Id: Iee682492f64f0f5da2a8702b8fe6f8b02c81b4c5
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/177 for details.

-gerrit



From gerrit at coreboot.org  Fri Sep  2 23:41:41 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 2 Sep 2011 23:41:41 +0200
Subject: [coreboot] Patch set updated: 4e39840 mkelfImage: Use
	-fno-stack-protector if supported by gcc
References: <I28ef158829f5935f985cfd5a5440733685cf479a+0@gerrit.coreboot.org>
Message-ID: <I28ef158829f5935f985cfd5a5440733685cf479a+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/112

-gerrit

commit 4e39840e7dcc5c6e1e63359db630b6cde64ce236
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Sep 2 23:40:31 2011 +0200

    mkelfImage: Use -fno-stack-protector if supported by gcc
    
    Gcc 4.1 comes with an SSP https://wiki.ubuntu.com/GccSsp
    This is disabled to work around '__stack_chk_fail' symbol not found failures
    http://www.coreboot.org/FAQ/Obsolete#How_do_I_fix_stack_chk_fail_errors.3F
    
    The presence of -fno-stack-protector is tested for automatically
    
    Change-Id: I28ef158829f5935f985cfd5a5440733685cf479a
    Reported-by: Raymond Danks <raymonddanks at gmail.com>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/mkelfImage/Makefile |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/util/mkelfImage/Makefile b/util/mkelfImage/Makefile
index cd265cf..63569a9 100644
--- a/util/mkelfImage/Makefile
+++ b/util/mkelfImage/Makefile
@@ -14,7 +14,16 @@ pkgdatadir = $(datadir)/$(PACKAGE)
 pkglibdir = $(libdir)/$(PACKAGE)
 pkgincludedir = $(includedir)/$(PACKAGE)
 
-CPPFLAGS=-DVERSION='"$(VERSION)"' -DRELEASE_DATE='"$(RELEASE_DATE)"' -I include
+# $1 CC
+# $2 flag to test
+# $3 make statement to evaluate
+testcc=$(if $(shell echo "_start(void) {}" | \
+	$(1) -x c -nostdlib $(2) - -o /dev/null > /dev/null 2> /dev/null && echo success),\
+	$(eval $(3)))
+
+CPPFLAGS=-DVERSION='"$(VERSION)"' -DRELEASE_DATE='"$(RELEASE_DATE)"' -I include $(CFLAGS) $(LDFLAGS)
+$(call testcc,$(CC),-f-nostack-protector,CPPFLAGS+=-fno-stack-protector)
+
 HOST_CPPFLAGS=$(CPPFLAGS)
 I386_CPPFLAGS=$(CPPFLAGS) -I arch/i386/include
 IA64_CPPFLAGS=$(CPPFLAGS) -I arch/ia64/include



From gerrit at coreboot.org  Sat Sep  3 00:04:53 2011
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Sat, 3 Sep 2011 00:04:53 +0200
Subject: [coreboot] New patch to review: 11c5f02 Add support for the tracing
	infastructure in coreboot.
References: <I2cbeb3f104892b034c8756f86ed05bf71187c3f3+0@gerrit.coreboot.org>
Message-ID: <I2cbeb3f104892b034c8756f86ed05bf71187c3f3+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/178

-gerrit

commit 11c5f026823afc880cb490e87be28ae842154e28
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Sep 2 23:23:41 2011 +0200

    Add support for the tracing infastructure in coreboot.
    
    The compiler is forced to emmit special functions on every
    entry/exit of the function. Add a compile time option
    to support it. Function entries will be printed in
    the console. The CONFIG_TRACE has more documentation.
    
    Patch for userspace tools will follow.
    
    Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 Makefile.inc           |    4 +++
 src/Kconfig            |    9 ++++++++
 src/console/printk.c   |    3 ++
 src/console/vsprintf.c |    3 ++
 src/include/trace.h    |   53 ++++++++++++++++++++++++++++++++++++++++++++++++
 src/lib/Makefile.inc   |    1 +
 src/lib/trace.c        |   39 +++++++++++++++++++++++++++++++++++
 src/lib/uart8250.c     |    4 +++
 8 files changed, 116 insertions(+), 0 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 37e4fb6..167ab5b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -51,6 +51,10 @@ classes-y := ramstage romstage driver smm
 
 romstage-c-ccopts:=-D__PRE_RAM__
 romstage-S-ccopts:=-D__PRE_RAM__
+ifeq ($(CONFIG_TRACE),y)
+ramstage-c-ccopts:= -finstrument-functions
+endif
+
 smm-c-ccopts:=-D__SMM__
 smm-S-ccopts:=-D__SMM__
 
diff --git a/src/Kconfig b/src/Kconfig
index f96c903..e9ceed5 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -845,6 +845,15 @@ config LLSHELL
 	  Put llshell() in your (romstage) code to start the shell.
 	  See src/arch/x86/llshell/llshell.inc for details.
 
+config TRACE
+	bool "Trace function calls"
+	default n
+	help
+	  If enabled, every function will print information to console once
+	  the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
+	  the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
+	  of calling function. Please note some printk releated functions
+	  are omitted from trace to have good looking console dumps.
 endmenu
 
 config LIFT_BSP_APIC_ID
diff --git a/src/console/printk.c b/src/console/printk.c
index 488d4e5..7549088 100644
--- a/src/console/printk.c
+++ b/src/console/printk.c
@@ -8,6 +8,7 @@
 #include <smp/spinlock.h>
 #include <console/vtxprintf.h>
 #include <console/console.h>
+#include <trace.h>
 
 int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
@@ -23,6 +24,7 @@ int do_printk(int msg_level, const char *fmt, ...)
 		return 0;
 	}
 
+	DISABLE_TRACE;
 	spin_lock(&console_lock);
 
 	va_start(args, fmt);
@@ -32,6 +34,7 @@ int do_printk(int msg_level, const char *fmt, ...)
 	console_tx_flush();
 
 	spin_unlock(&console_lock);
+	ENABLE_TRACE;
 
 	return i;
 }
diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c
index 4a74523..435401b 100644
--- a/src/console/vsprintf.c
+++ b/src/console/vsprintf.c
@@ -22,6 +22,7 @@
 #include <string.h>
 #include <smp/spinlock.h>
 #include <console/vtxprintf.h>
+#include <trace.h>
 
 DECLARE_SPIN_LOCK(vsprintf_lock)
 
@@ -37,6 +38,7 @@ static int vsprintf(char *buf, const char *fmt, va_list args)
 {
 	int i;
 
+	DISABLE_TRACE;
 	spin_lock(&vsprintf_lock);
 
 	str_buf = buf;
@@ -44,6 +46,7 @@ static int vsprintf(char *buf, const char *fmt, va_list args)
 	*str_buf = '\0';
 
 	spin_unlock(&vsprintf_lock);
+	ENABLE_TRACE;
 
 	return i;
 }
diff --git a/src/include/trace.h b/src/include/trace.h
new file mode 100644
index 0000000..9f90766
--- /dev/null
+++ b/src/include/trace.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef __TRACE_H
+#define __TRACE_H
+
+void __cyg_profile_func_enter( void *, void * )
+				 __attribute__ ((no_instrument_function));
+
+void __cyg_profile_func_exit( void *, void * )
+				__attribute__ ((no_instrument_function));
+
+extern volatile int trace_dis;
+
+#ifdef __PRE_RAM__
+
+#define DISABLE_TRACE
+#define ENABLE_TRACE
+#define DISABLE_TRACE_ON_FUNCTION
+
+#else /* !__PRE_RAM__ */
+
+#if CONFIG_TRACE
+
+#define DISABLE_TRACE  do { trace_dis = 1; } while (0);
+#define ENABLE_TRACE    do { trace_dis = 0; } while (0);
+#define DISABLE_TRACE_ON_FUNCTION  __attribute__ ((no_instrument_function));
+
+#else /* !CONFIG_TRACE */
+
+#define DISABLE_TRACE
+#define ENABLE_TRACE
+#define DISABLE_TRACE_ON_FUNCTION
+
+#endif
+#endif
+#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 54935ca..3d8e889 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -14,6 +14,7 @@ romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
 
+ramstage-y += trace.c
 ramstage-y += memset.c
 ramstage-y += memcpy.c
 ramstage-y += memcmp.c
diff --git a/src/lib/trace.c b/src/lib/trace.c
new file mode 100644
index 0000000..8736c82
--- /dev/null
+++ b/src/lib/trace.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <trace.h>
+
+int volatile trace_dis = 0;
+
+void __cyg_profile_func_enter( void *func, void *callsite)
+{
+
+	if (trace_dis)
+		return;
+
+	DISABLE_TRACE
+	printk(BIOS_INFO, "~0x%08x(0x%08x)\n", (uint32_t) func, (uint32_t) callsite);
+	ENABLE_TRACE
+}
+
+void __cyg_profile_func_exit( void *func, void *callsite )
+{
+}
diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
index e7ddd0b..b224671 100644
--- a/src/lib/uart8250.c
+++ b/src/lib/uart8250.c
@@ -21,6 +21,8 @@
 #include <arch/io.h>
 #include <uart8250.h>
 #include <pc80/mc146818rtc.h>
+#include <trace.h>
+
 #if CONFIG_USE_OPTION_TABLE
 #include "option_table.h"
 #endif
@@ -69,6 +71,7 @@ unsigned char uart8250_rx_byte(unsigned base_port)
 
 void uart8250_init(unsigned base_port, unsigned divisor)
 {
+	DISABLE_TRACE;
 	/* Disable interrupts */
 	outb(0x0, base_port + UART_IER);
 	/* Enable FIFOs */
@@ -86,6 +89,7 @@ void uart8250_init(unsigned base_port, unsigned divisor)
 
 	/* Set to 3 for 8N1 */
 	outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
+	ENABLE_TRACE;
 }
 
 void uart_init(void)



From gerrit at coreboot.org  Sat Sep  3 00:04:54 2011
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Sat, 3 Sep 2011 00:04:54 +0200
Subject: [coreboot] New patch to review: 153ff73 Add support utils for
	tracing
References: <I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5+0@gerrit.coreboot.org>
Message-ID: <I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/179

-gerrit

commit 153ff739cd7ae573610c2deba8700b628468a839
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Sep 2 23:34:15 2011 +0200

    Add support utils for tracing
    
    Following patch adds a userspace util genprof
    which is able to convert the console printed
    traces to gmon.out file used by gprof & friends.
    The log2dress will replace the adresses in logfile
    with a line numbers.
    
    Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 util/genprof/Makefile  |   12 +++++
 util/genprof/README    |   31 ++++++++++++++
 util/genprof/genprof.c |  108 ++++++++++++++++++++++++++++++++++++++++++++++++
 util/genprof/log2dress |   20 +++++++++
 4 files changed, 171 insertions(+), 0 deletions(-)

diff --git a/util/genprof/Makefile b/util/genprof/Makefile
new file mode 100644
index 0000000..2ec77c9
--- /dev/null
+++ b/util/genprof/Makefile
@@ -0,0 +1,12 @@
+CC=gcc
+CFLAGS=-O2 -Wall
+
+all: genprof
+
+genprof: genprof.o
+	$(CC) $(CFLAGS) -o genprof $^
+
+clean:
+	rm -f genprof  *.o *~
+
+distclean: clean
diff --git a/util/genprof/README b/util/genprof/README
new file mode 100644
index 0000000..3483a2b
--- /dev/null
+++ b/util/genprof/README
@@ -0,0 +1,31 @@
+Function tracing
+----------------
+
+Enable CONFIG_TRACE in debug menu. Run the compiled image on target. You will get
+a log with a lot of lines like:
+
+...
+~0x001072e8(0x00100099)
+~0x00108bc0(0x0010730a)
+...
+
+First address is address of function which was just entered, the second address
+is address of functions which call that.
+
+You can use the log2dress to dress the log again:
+
+...
+src/arch/x86/lib/c_start.S:85 calls /home/ruik/coreboot/src/boot/selfboot.c:367
+/home/ruik/coreboot/src/boot/selfboot.c:370 calls /home/ruik/coreboot/src/devices/device.c:325
+...
+
+Alternatively, you can use genprof to generate a gmon.out file, which can be used
+by gprof to show the call traces. You will need to install uthash library to compile
+that.
+
+Great use is:
+
+make
+./genprof /tmp/yourlog ;  gprof ../../build/coreboot_ram |  ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png
+
+Which generates a PNG with a call graph.
diff --git a/util/genprof/genprof.c b/util/genprof/genprof.c
new file mode 100644
index 0000000..9fc39da
--- /dev/null
+++ b/util/genprof/genprof.c
@@ -0,0 +1,108 @@
+#include <stdio.h>
+#include <uthash.h>
+#include <sys/gmon_out.h>
+#include <stdlib.h>
+
+#define GMON_SEC "seconds        s"
+uint32_t mineip = 0xffffffff;
+uint32_t maxeip = 0;
+
+/* a hash structure to hold the arc */
+struct arec {
+	uint32_t eip;
+	uint32_t from;
+	uint32_t count;
+	UT_hash_handle hh;
+};
+
+struct arec *arc = NULL;
+
+void note_arc(uint32_t eip, uint32_t from)
+{
+	struct arec *s;
+
+	HASH_FIND_INT(arc, &eip, s);
+	if (s == NULL) {
+		s = malloc(sizeof(struct arec));
+		s->eip = eip;
+		s->from = from;
+		s->count = 1;
+		if (eip > maxeip)
+			maxeip = eip;
+		if (eip < mineip)
+			maxeip = eip;
+
+		HASH_ADD_INT(arc, eip, s);
+	} else {
+		s->count++;
+	}
+}
+
+int main(int argc, char* argv[])
+{
+	FILE *f, *fo;
+	struct arec *s;
+	uint32_t eip, from, tmp;
+	uint8_t tag;
+	uint16_t hit;
+
+	if ( argc < 2 )
+	{
+		fprintf(stderr, "Please specify the coreboot trace log as parameter\n");
+		return 1;
+	}
+
+	f = fopen(argv[1], "r");
+	fo = fopen("gmon.out", "w+");
+
+	if ((f == NULL) || (fo == NULL)) {
+		fprintf(stderr, "Unable to manipulate with the input file\n");
+		return 1;
+	}
+
+	while (!feof(f)) {
+		if (fscanf(f, "~%x(%x)%*[^\n]\n", &eip, &from) == 2) {
+			note_arc(eip, from);
+		} else if (fscanf(f, "%*c~%x(%x)%*[^\n]\n", &eip, &from) == 2) {
+			note_arc(eip, from);
+		} else {
+			/* just drop a line */
+			tmp = fscanf(f, "%*[^\n]\n");
+		}
+	}
+
+	/* write gprof header */
+	fwrite(GMON_MAGIC, 1, sizeof(GMON_MAGIC) - 1, fo);
+	tmp = GMON_VERSION;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	tmp = 0;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	/* write fake histogram */
+	tag = GMON_TAG_TIME_HIST;
+	fwrite(&tag, 1, sizeof(tag), fo);
+	fwrite(&mineip, 1, sizeof(mineip), fo);
+	fwrite(&maxeip, 1, sizeof(maxeip), fo);
+	/* size of histogram */
+	tmp = 1;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	/* prof rate */
+	tmp = 1000;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	fwrite(GMON_SEC, 1, sizeof(GMON_SEC) - 1, fo);
+	hit = 1;
+	fwrite(&hit, 1, sizeof(hit), fo);
+
+	/* write call graph data */
+	tag = GMON_TAG_CG_ARC;
+	for (s = arc; s != NULL; s = s->hh.next) {
+		fwrite(&tag, 1, sizeof(tag), fo);
+		fwrite(&s->from, 1, sizeof(s->from), fo);
+		fwrite(&s->eip, 1, sizeof(s->eip), fo);
+		fwrite(&s->count, 1, sizeof(s->count), fo);
+	}
+
+	fclose(fo);
+	return 0;
+}
diff --git a/util/genprof/log2dress b/util/genprof/log2dress
new file mode 100755
index 0000000..429f846
--- /dev/null
+++ b/util/genprof/log2dress
@@ -0,0 +1,20 @@
+#!/bin/bash
+#Parse a log and get back the function names and line numbers
+#Provide a log file as first argument
+
+#Please rewrite to something more saner !
+
+cat $1 | while read line ; do
+A=`echo $line | cut -c 1`
+
+if [ "$A" = '~' ] ; then
+FROM=`echo $line | tr \~ \( | tr \) \(  | awk -F\( '{print $3}'`
+TO=`echo $line  | tr \~ \( | tr \) \(|awk -F\( '{print $2}'`
+addr2line -e ../../build/coreboot_ram.debug "$FROM" | tr -d "\n"
+echo -n " calls "
+addr2line -e ../../build/coreboot_ram.debug "$TO"
+else
+echo "$line"
+fi
+
+done



From gerrit at coreboot.org  Sat Sep  3 00:23:07 2011
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Sat, 3 Sep 2011 00:23:07 +0200
Subject: [coreboot] Patch set updated: b3e5d4e Add support for the tracing
	infastructure in coreboot.
References: <I2cbeb3f104892b034c8756f86ed05bf71187c3f3+0@gerrit.coreboot.org>
Message-ID: <I2cbeb3f104892b034c8756f86ed05bf71187c3f3+2@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/178

-gerrit

commit b3e5d4e8902992e63e83f963b7acd1a56f6217f8
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Sep 2 23:23:41 2011 +0200

    Add support for the tracing infastructure in coreboot.
    
    The compiler is forced to emmit special functions on every
    entry/exit of the function. Add a compile time option
    to support it. Function entries will be printed in
    the console. The CONFIG_TRACE has more documentation.
    
    Patch for userspace tools will follow.
    
    Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 Makefile.inc           |    4 +++
 src/Kconfig            |    9 ++++++++
 src/console/printk.c   |    3 ++
 src/console/vsprintf.c |    3 ++
 src/include/trace.h    |   53 ++++++++++++++++++++++++++++++++++++++++++++++++
 src/lib/Makefile.inc   |    1 +
 src/lib/trace.c        |   39 +++++++++++++++++++++++++++++++++++
 src/lib/uart8250.c     |    4 +++
 8 files changed, 116 insertions(+), 0 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 37e4fb6..167ab5b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -51,6 +51,10 @@ classes-y := ramstage romstage driver smm
 
 romstage-c-ccopts:=-D__PRE_RAM__
 romstage-S-ccopts:=-D__PRE_RAM__
+ifeq ($(CONFIG_TRACE),y)
+ramstage-c-ccopts:= -finstrument-functions
+endif
+
 smm-c-ccopts:=-D__SMM__
 smm-S-ccopts:=-D__SMM__
 
diff --git a/src/Kconfig b/src/Kconfig
index f96c903..e9ceed5 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -845,6 +845,15 @@ config LLSHELL
 	  Put llshell() in your (romstage) code to start the shell.
 	  See src/arch/x86/llshell/llshell.inc for details.
 
+config TRACE
+	bool "Trace function calls"
+	default n
+	help
+	  If enabled, every function will print information to console once
+	  the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
+	  the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
+	  of calling function. Please note some printk releated functions
+	  are omitted from trace to have good looking console dumps.
 endmenu
 
 config LIFT_BSP_APIC_ID
diff --git a/src/console/printk.c b/src/console/printk.c
index 488d4e5..7549088 100644
--- a/src/console/printk.c
+++ b/src/console/printk.c
@@ -8,6 +8,7 @@
 #include <smp/spinlock.h>
 #include <console/vtxprintf.h>
 #include <console/console.h>
+#include <trace.h>
 
 int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
@@ -23,6 +24,7 @@ int do_printk(int msg_level, const char *fmt, ...)
 		return 0;
 	}
 
+	DISABLE_TRACE;
 	spin_lock(&console_lock);
 
 	va_start(args, fmt);
@@ -32,6 +34,7 @@ int do_printk(int msg_level, const char *fmt, ...)
 	console_tx_flush();
 
 	spin_unlock(&console_lock);
+	ENABLE_TRACE;
 
 	return i;
 }
diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c
index 4a74523..435401b 100644
--- a/src/console/vsprintf.c
+++ b/src/console/vsprintf.c
@@ -22,6 +22,7 @@
 #include <string.h>
 #include <smp/spinlock.h>
 #include <console/vtxprintf.h>
+#include <trace.h>
 
 DECLARE_SPIN_LOCK(vsprintf_lock)
 
@@ -37,6 +38,7 @@ static int vsprintf(char *buf, const char *fmt, va_list args)
 {
 	int i;
 
+	DISABLE_TRACE;
 	spin_lock(&vsprintf_lock);
 
 	str_buf = buf;
@@ -44,6 +46,7 @@ static int vsprintf(char *buf, const char *fmt, va_list args)
 	*str_buf = '\0';
 
 	spin_unlock(&vsprintf_lock);
+	ENABLE_TRACE;
 
 	return i;
 }
diff --git a/src/include/trace.h b/src/include/trace.h
new file mode 100644
index 0000000..9f90766
--- /dev/null
+++ b/src/include/trace.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef __TRACE_H
+#define __TRACE_H
+
+void __cyg_profile_func_enter( void *, void * )
+				 __attribute__ ((no_instrument_function));
+
+void __cyg_profile_func_exit( void *, void * )
+				__attribute__ ((no_instrument_function));
+
+extern volatile int trace_dis;
+
+#ifdef __PRE_RAM__
+
+#define DISABLE_TRACE
+#define ENABLE_TRACE
+#define DISABLE_TRACE_ON_FUNCTION
+
+#else /* !__PRE_RAM__ */
+
+#if CONFIG_TRACE
+
+#define DISABLE_TRACE  do { trace_dis = 1; } while (0);
+#define ENABLE_TRACE    do { trace_dis = 0; } while (0);
+#define DISABLE_TRACE_ON_FUNCTION  __attribute__ ((no_instrument_function));
+
+#else /* !CONFIG_TRACE */
+
+#define DISABLE_TRACE
+#define ENABLE_TRACE
+#define DISABLE_TRACE_ON_FUNCTION
+
+#endif
+#endif
+#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 54935ca..b207ffe 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,6 +33,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
+ramstage-$(CONFIG_TRACE) += trace.c
 
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
diff --git a/src/lib/trace.c b/src/lib/trace.c
new file mode 100644
index 0000000..8736c82
--- /dev/null
+++ b/src/lib/trace.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <trace.h>
+
+int volatile trace_dis = 0;
+
+void __cyg_profile_func_enter( void *func, void *callsite)
+{
+
+	if (trace_dis)
+		return;
+
+	DISABLE_TRACE
+	printk(BIOS_INFO, "~0x%08x(0x%08x)\n", (uint32_t) func, (uint32_t) callsite);
+	ENABLE_TRACE
+}
+
+void __cyg_profile_func_exit( void *func, void *callsite )
+{
+}
diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
index e7ddd0b..b224671 100644
--- a/src/lib/uart8250.c
+++ b/src/lib/uart8250.c
@@ -21,6 +21,8 @@
 #include <arch/io.h>
 #include <uart8250.h>
 #include <pc80/mc146818rtc.h>
+#include <trace.h>
+
 #if CONFIG_USE_OPTION_TABLE
 #include "option_table.h"
 #endif
@@ -69,6 +71,7 @@ unsigned char uart8250_rx_byte(unsigned base_port)
 
 void uart8250_init(unsigned base_port, unsigned divisor)
 {
+	DISABLE_TRACE;
 	/* Disable interrupts */
 	outb(0x0, base_port + UART_IER);
 	/* Enable FIFOs */
@@ -86,6 +89,7 @@ void uart8250_init(unsigned base_port, unsigned divisor)
 
 	/* Set to 3 for 8N1 */
 	outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
+	ENABLE_TRACE;
 }
 
 void uart_init(void)



From gerrit at coreboot.org  Sat Sep  3 00:23:08 2011
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Sat, 3 Sep 2011 00:23:08 +0200
Subject: [coreboot] Patch set updated: 20de823 Add support utils for tracing
References: <I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5+0@gerrit.coreboot.org>
Message-ID: <I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5+2@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/179

-gerrit

commit 20de8236d60d90397ebfa151e194cc851c28a227
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Sep 2 23:34:15 2011 +0200

    Add support utils for tracing
    
    Following patch adds a userspace util genprof
    which is able to convert the console printed
    traces to gmon.out file used by gprof & friends.
    The log2dress will replace the adresses in logfile
    with a line numbers.
    
    Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 util/genprof/Makefile  |   12 +++++
 util/genprof/README    |   31 ++++++++++++++
 util/genprof/genprof.c |  108 ++++++++++++++++++++++++++++++++++++++++++++++++
 util/genprof/log2dress |   20 +++++++++
 4 files changed, 171 insertions(+), 0 deletions(-)

diff --git a/util/genprof/Makefile b/util/genprof/Makefile
new file mode 100644
index 0000000..2ec77c9
--- /dev/null
+++ b/util/genprof/Makefile
@@ -0,0 +1,12 @@
+CC=gcc
+CFLAGS=-O2 -Wall
+
+all: genprof
+
+genprof: genprof.o
+	$(CC) $(CFLAGS) -o genprof $^
+
+clean:
+	rm -f genprof  *.o *~
+
+distclean: clean
diff --git a/util/genprof/README b/util/genprof/README
new file mode 100644
index 0000000..3483a2b
--- /dev/null
+++ b/util/genprof/README
@@ -0,0 +1,31 @@
+Function tracing
+----------------
+
+Enable CONFIG_TRACE in debug menu. Run the compiled image on target. You will get
+a log with a lot of lines like:
+
+...
+~0x001072e8(0x00100099)
+~0x00108bc0(0x0010730a)
+...
+
+First address is address of function which was just entered, the second address
+is address of functions which call that.
+
+You can use the log2dress to dress the log again:
+
+...
+src/arch/x86/lib/c_start.S:85 calls /home/ruik/coreboot/src/boot/selfboot.c:367
+/home/ruik/coreboot/src/boot/selfboot.c:370 calls /home/ruik/coreboot/src/devices/device.c:325
+...
+
+Alternatively, you can use genprof to generate a gmon.out file, which can be used
+by gprof to show the call traces. You will need to install uthash library to compile
+that.
+
+Great use is:
+
+make
+./genprof /tmp/yourlog ;  gprof ../../build/coreboot_ram |  ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png
+
+Which generates a PNG with a call graph.
diff --git a/util/genprof/genprof.c b/util/genprof/genprof.c
new file mode 100644
index 0000000..9fc39da
--- /dev/null
+++ b/util/genprof/genprof.c
@@ -0,0 +1,108 @@
+#include <stdio.h>
+#include <uthash.h>
+#include <sys/gmon_out.h>
+#include <stdlib.h>
+
+#define GMON_SEC "seconds        s"
+uint32_t mineip = 0xffffffff;
+uint32_t maxeip = 0;
+
+/* a hash structure to hold the arc */
+struct arec {
+	uint32_t eip;
+	uint32_t from;
+	uint32_t count;
+	UT_hash_handle hh;
+};
+
+struct arec *arc = NULL;
+
+void note_arc(uint32_t eip, uint32_t from)
+{
+	struct arec *s;
+
+	HASH_FIND_INT(arc, &eip, s);
+	if (s == NULL) {
+		s = malloc(sizeof(struct arec));
+		s->eip = eip;
+		s->from = from;
+		s->count = 1;
+		if (eip > maxeip)
+			maxeip = eip;
+		if (eip < mineip)
+			maxeip = eip;
+
+		HASH_ADD_INT(arc, eip, s);
+	} else {
+		s->count++;
+	}
+}
+
+int main(int argc, char* argv[])
+{
+	FILE *f, *fo;
+	struct arec *s;
+	uint32_t eip, from, tmp;
+	uint8_t tag;
+	uint16_t hit;
+
+	if ( argc < 2 )
+	{
+		fprintf(stderr, "Please specify the coreboot trace log as parameter\n");
+		return 1;
+	}
+
+	f = fopen(argv[1], "r");
+	fo = fopen("gmon.out", "w+");
+
+	if ((f == NULL) || (fo == NULL)) {
+		fprintf(stderr, "Unable to manipulate with the input file\n");
+		return 1;
+	}
+
+	while (!feof(f)) {
+		if (fscanf(f, "~%x(%x)%*[^\n]\n", &eip, &from) == 2) {
+			note_arc(eip, from);
+		} else if (fscanf(f, "%*c~%x(%x)%*[^\n]\n", &eip, &from) == 2) {
+			note_arc(eip, from);
+		} else {
+			/* just drop a line */
+			tmp = fscanf(f, "%*[^\n]\n");
+		}
+	}
+
+	/* write gprof header */
+	fwrite(GMON_MAGIC, 1, sizeof(GMON_MAGIC) - 1, fo);
+	tmp = GMON_VERSION;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	tmp = 0;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	/* write fake histogram */
+	tag = GMON_TAG_TIME_HIST;
+	fwrite(&tag, 1, sizeof(tag), fo);
+	fwrite(&mineip, 1, sizeof(mineip), fo);
+	fwrite(&maxeip, 1, sizeof(maxeip), fo);
+	/* size of histogram */
+	tmp = 1;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	/* prof rate */
+	tmp = 1000;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	fwrite(GMON_SEC, 1, sizeof(GMON_SEC) - 1, fo);
+	hit = 1;
+	fwrite(&hit, 1, sizeof(hit), fo);
+
+	/* write call graph data */
+	tag = GMON_TAG_CG_ARC;
+	for (s = arc; s != NULL; s = s->hh.next) {
+		fwrite(&tag, 1, sizeof(tag), fo);
+		fwrite(&s->from, 1, sizeof(s->from), fo);
+		fwrite(&s->eip, 1, sizeof(s->eip), fo);
+		fwrite(&s->count, 1, sizeof(s->count), fo);
+	}
+
+	fclose(fo);
+	return 0;
+}
diff --git a/util/genprof/log2dress b/util/genprof/log2dress
new file mode 100755
index 0000000..429f846
--- /dev/null
+++ b/util/genprof/log2dress
@@ -0,0 +1,20 @@
+#!/bin/bash
+#Parse a log and get back the function names and line numbers
+#Provide a log file as first argument
+
+#Please rewrite to something more saner !
+
+cat $1 | while read line ; do
+A=`echo $line | cut -c 1`
+
+if [ "$A" = '~' ] ; then
+FROM=`echo $line | tr \~ \( | tr \) \(  | awk -F\( '{print $3}'`
+TO=`echo $line  | tr \~ \( | tr \) \(|awk -F\( '{print $2}'`
+addr2line -e ../../build/coreboot_ram.debug "$FROM" | tr -d "\n"
+echo -n " calls "
+addr2line -e ../../build/coreboot_ram.debug "$TO"
+else
+echo "$line"
+fi
+
+done



From gerrit at coreboot.org  Sat Sep  3 00:34:34 2011
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Sat, 3 Sep 2011 00:34:34 +0200
Subject: [coreboot] Patch set updated: 5ef3380 Add support for the tracing
	infastructure in coreboot.
References: <I2cbeb3f104892b034c8756f86ed05bf71187c3f3+0@gerrit.coreboot.org>
Message-ID: <I2cbeb3f104892b034c8756f86ed05bf71187c3f3+3@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/178

-gerrit

commit 5ef3380428f35b9196ecfe7f52281bb26080c364
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Sep 2 23:23:41 2011 +0200

    Add support for the tracing infastructure in coreboot.
    
    The compiler is forced to emmit special functions on every
    entry/exit of the function. Add a compile time option
    to support it. Function entries will be printed in
    the console. The CONFIG_TRACE has more documentation.
    
    Patch for userspace tools will follow.
    
    Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 Makefile.inc           |    4 +++
 src/Kconfig            |    9 ++++++++
 src/console/printk.c   |    3 ++
 src/console/vsprintf.c |    3 ++
 src/include/trace.h    |   54 ++++++++++++++++++++++++++++++++++++++++++++++++
 src/lib/Makefile.inc   |    1 +
 src/lib/trace.c        |   39 ++++++++++++++++++++++++++++++++++
 src/lib/uart8250.c     |    4 +++
 8 files changed, 117 insertions(+), 0 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 37e4fb6..167ab5b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -51,6 +51,10 @@ classes-y := ramstage romstage driver smm
 
 romstage-c-ccopts:=-D__PRE_RAM__
 romstage-S-ccopts:=-D__PRE_RAM__
+ifeq ($(CONFIG_TRACE),y)
+ramstage-c-ccopts:= -finstrument-functions
+endif
+
 smm-c-ccopts:=-D__SMM__
 smm-S-ccopts:=-D__SMM__
 
diff --git a/src/Kconfig b/src/Kconfig
index f96c903..e9ceed5 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -845,6 +845,15 @@ config LLSHELL
 	  Put llshell() in your (romstage) code to start the shell.
 	  See src/arch/x86/llshell/llshell.inc for details.
 
+config TRACE
+	bool "Trace function calls"
+	default n
+	help
+	  If enabled, every function will print information to console once
+	  the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
+	  the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
+	  of calling function. Please note some printk releated functions
+	  are omitted from trace to have good looking console dumps.
 endmenu
 
 config LIFT_BSP_APIC_ID
diff --git a/src/console/printk.c b/src/console/printk.c
index 488d4e5..7549088 100644
--- a/src/console/printk.c
+++ b/src/console/printk.c
@@ -8,6 +8,7 @@
 #include <smp/spinlock.h>
 #include <console/vtxprintf.h>
 #include <console/console.h>
+#include <trace.h>
 
 int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
@@ -23,6 +24,7 @@ int do_printk(int msg_level, const char *fmt, ...)
 		return 0;
 	}
 
+	DISABLE_TRACE;
 	spin_lock(&console_lock);
 
 	va_start(args, fmt);
@@ -32,6 +34,7 @@ int do_printk(int msg_level, const char *fmt, ...)
 	console_tx_flush();
 
 	spin_unlock(&console_lock);
+	ENABLE_TRACE;
 
 	return i;
 }
diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c
index 4a74523..435401b 100644
--- a/src/console/vsprintf.c
+++ b/src/console/vsprintf.c
@@ -22,6 +22,7 @@
 #include <string.h>
 #include <smp/spinlock.h>
 #include <console/vtxprintf.h>
+#include <trace.h>
 
 DECLARE_SPIN_LOCK(vsprintf_lock)
 
@@ -37,6 +38,7 @@ static int vsprintf(char *buf, const char *fmt, va_list args)
 {
 	int i;
 
+	DISABLE_TRACE;
 	spin_lock(&vsprintf_lock);
 
 	str_buf = buf;
@@ -44,6 +46,7 @@ static int vsprintf(char *buf, const char *fmt, va_list args)
 	*str_buf = '\0';
 
 	spin_unlock(&vsprintf_lock);
+	ENABLE_TRACE;
 
 	return i;
 }
diff --git a/src/include/trace.h b/src/include/trace.h
new file mode 100644
index 0000000..ff5b6c2
--- /dev/null
+++ b/src/include/trace.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef __TRACE_H
+#define __TRACE_H
+
+
+#ifdef __PRE_RAM__
+
+#define DISABLE_TRACE
+#define ENABLE_TRACE
+#define DISABLE_TRACE_ON_FUNCTION
+
+#else /* !__PRE_RAM__ */
+
+#if CONFIG_TRACE
+
+void __cyg_profile_func_enter( void *, void * )
+				 __attribute__ ((no_instrument_function));
+
+void __cyg_profile_func_exit( void *, void * )
+				__attribute__ ((no_instrument_function));
+
+extern volatile int trace_dis;
+
+#define DISABLE_TRACE  do { trace_dis = 1; } while (0);
+#define ENABLE_TRACE    do { trace_dis = 0; } while (0);
+#define DISABLE_TRACE_ON_FUNCTION  __attribute__ ((no_instrument_function));
+
+#else /* !CONFIG_TRACE */
+
+#define DISABLE_TRACE
+#define ENABLE_TRACE
+#define DISABLE_TRACE_ON_FUNCTION
+
+#endif
+#endif
+#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 54935ca..b207ffe 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,6 +33,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
+ramstage-$(CONFIG_TRACE) += trace.c
 
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
diff --git a/src/lib/trace.c b/src/lib/trace.c
new file mode 100644
index 0000000..8736c82
--- /dev/null
+++ b/src/lib/trace.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <trace.h>
+
+int volatile trace_dis = 0;
+
+void __cyg_profile_func_enter( void *func, void *callsite)
+{
+
+	if (trace_dis)
+		return;
+
+	DISABLE_TRACE
+	printk(BIOS_INFO, "~0x%08x(0x%08x)\n", (uint32_t) func, (uint32_t) callsite);
+	ENABLE_TRACE
+}
+
+void __cyg_profile_func_exit( void *func, void *callsite )
+{
+}
diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
index e7ddd0b..b224671 100644
--- a/src/lib/uart8250.c
+++ b/src/lib/uart8250.c
@@ -21,6 +21,8 @@
 #include <arch/io.h>
 #include <uart8250.h>
 #include <pc80/mc146818rtc.h>
+#include <trace.h>
+
 #if CONFIG_USE_OPTION_TABLE
 #include "option_table.h"
 #endif
@@ -69,6 +71,7 @@ unsigned char uart8250_rx_byte(unsigned base_port)
 
 void uart8250_init(unsigned base_port, unsigned divisor)
 {
+	DISABLE_TRACE;
 	/* Disable interrupts */
 	outb(0x0, base_port + UART_IER);
 	/* Enable FIFOs */
@@ -86,6 +89,7 @@ void uart8250_init(unsigned base_port, unsigned divisor)
 
 	/* Set to 3 for 8N1 */
 	outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
+	ENABLE_TRACE;
 }
 
 void uart_init(void)



From gerrit at coreboot.org  Sat Sep  3 00:34:35 2011
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Sat, 3 Sep 2011 00:34:35 +0200
Subject: [coreboot] Patch set updated: 7700f5d Add support utils for tracing
References: <I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5+0@gerrit.coreboot.org>
Message-ID: <I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5+3@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/179

-gerrit

commit 7700f5df07fd80c65eced4deb7d0c6051fd9f2b6
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Sep 2 23:34:15 2011 +0200

    Add support utils for tracing
    
    Following patch adds a userspace util genprof
    which is able to convert the console printed
    traces to gmon.out file used by gprof & friends.
    The log2dress will replace the adresses in logfile
    with a line numbers.
    
    Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 util/genprof/Makefile  |   12 +++++
 util/genprof/README    |   31 ++++++++++++++
 util/genprof/genprof.c |  108 ++++++++++++++++++++++++++++++++++++++++++++++++
 util/genprof/log2dress |   20 +++++++++
 4 files changed, 171 insertions(+), 0 deletions(-)

diff --git a/util/genprof/Makefile b/util/genprof/Makefile
new file mode 100644
index 0000000..2ec77c9
--- /dev/null
+++ b/util/genprof/Makefile
@@ -0,0 +1,12 @@
+CC=gcc
+CFLAGS=-O2 -Wall
+
+all: genprof
+
+genprof: genprof.o
+	$(CC) $(CFLAGS) -o genprof $^
+
+clean:
+	rm -f genprof  *.o *~
+
+distclean: clean
diff --git a/util/genprof/README b/util/genprof/README
new file mode 100644
index 0000000..3483a2b
--- /dev/null
+++ b/util/genprof/README
@@ -0,0 +1,31 @@
+Function tracing
+----------------
+
+Enable CONFIG_TRACE in debug menu. Run the compiled image on target. You will get
+a log with a lot of lines like:
+
+...
+~0x001072e8(0x00100099)
+~0x00108bc0(0x0010730a)
+...
+
+First address is address of function which was just entered, the second address
+is address of functions which call that.
+
+You can use the log2dress to dress the log again:
+
+...
+src/arch/x86/lib/c_start.S:85 calls /home/ruik/coreboot/src/boot/selfboot.c:367
+/home/ruik/coreboot/src/boot/selfboot.c:370 calls /home/ruik/coreboot/src/devices/device.c:325
+...
+
+Alternatively, you can use genprof to generate a gmon.out file, which can be used
+by gprof to show the call traces. You will need to install uthash library to compile
+that.
+
+Great use is:
+
+make
+./genprof /tmp/yourlog ;  gprof ../../build/coreboot_ram |  ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png
+
+Which generates a PNG with a call graph.
diff --git a/util/genprof/genprof.c b/util/genprof/genprof.c
new file mode 100644
index 0000000..9fc39da
--- /dev/null
+++ b/util/genprof/genprof.c
@@ -0,0 +1,108 @@
+#include <stdio.h>
+#include <uthash.h>
+#include <sys/gmon_out.h>
+#include <stdlib.h>
+
+#define GMON_SEC "seconds        s"
+uint32_t mineip = 0xffffffff;
+uint32_t maxeip = 0;
+
+/* a hash structure to hold the arc */
+struct arec {
+	uint32_t eip;
+	uint32_t from;
+	uint32_t count;
+	UT_hash_handle hh;
+};
+
+struct arec *arc = NULL;
+
+void note_arc(uint32_t eip, uint32_t from)
+{
+	struct arec *s;
+
+	HASH_FIND_INT(arc, &eip, s);
+	if (s == NULL) {
+		s = malloc(sizeof(struct arec));
+		s->eip = eip;
+		s->from = from;
+		s->count = 1;
+		if (eip > maxeip)
+			maxeip = eip;
+		if (eip < mineip)
+			maxeip = eip;
+
+		HASH_ADD_INT(arc, eip, s);
+	} else {
+		s->count++;
+	}
+}
+
+int main(int argc, char* argv[])
+{
+	FILE *f, *fo;
+	struct arec *s;
+	uint32_t eip, from, tmp;
+	uint8_t tag;
+	uint16_t hit;
+
+	if ( argc < 2 )
+	{
+		fprintf(stderr, "Please specify the coreboot trace log as parameter\n");
+		return 1;
+	}
+
+	f = fopen(argv[1], "r");
+	fo = fopen("gmon.out", "w+");
+
+	if ((f == NULL) || (fo == NULL)) {
+		fprintf(stderr, "Unable to manipulate with the input file\n");
+		return 1;
+	}
+
+	while (!feof(f)) {
+		if (fscanf(f, "~%x(%x)%*[^\n]\n", &eip, &from) == 2) {
+			note_arc(eip, from);
+		} else if (fscanf(f, "%*c~%x(%x)%*[^\n]\n", &eip, &from) == 2) {
+			note_arc(eip, from);
+		} else {
+			/* just drop a line */
+			tmp = fscanf(f, "%*[^\n]\n");
+		}
+	}
+
+	/* write gprof header */
+	fwrite(GMON_MAGIC, 1, sizeof(GMON_MAGIC) - 1, fo);
+	tmp = GMON_VERSION;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	tmp = 0;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	/* write fake histogram */
+	tag = GMON_TAG_TIME_HIST;
+	fwrite(&tag, 1, sizeof(tag), fo);
+	fwrite(&mineip, 1, sizeof(mineip), fo);
+	fwrite(&maxeip, 1, sizeof(maxeip), fo);
+	/* size of histogram */
+	tmp = 1;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	/* prof rate */
+	tmp = 1000;
+	fwrite(&tmp, 1, sizeof(tmp), fo);
+	fwrite(GMON_SEC, 1, sizeof(GMON_SEC) - 1, fo);
+	hit = 1;
+	fwrite(&hit, 1, sizeof(hit), fo);
+
+	/* write call graph data */
+	tag = GMON_TAG_CG_ARC;
+	for (s = arc; s != NULL; s = s->hh.next) {
+		fwrite(&tag, 1, sizeof(tag), fo);
+		fwrite(&s->from, 1, sizeof(s->from), fo);
+		fwrite(&s->eip, 1, sizeof(s->eip), fo);
+		fwrite(&s->count, 1, sizeof(s->count), fo);
+	}
+
+	fclose(fo);
+	return 0;
+}
diff --git a/util/genprof/log2dress b/util/genprof/log2dress
new file mode 100755
index 0000000..429f846
--- /dev/null
+++ b/util/genprof/log2dress
@@ -0,0 +1,20 @@
+#!/bin/bash
+#Parse a log and get back the function names and line numbers
+#Provide a log file as first argument
+
+#Please rewrite to something more saner !
+
+cat $1 | while read line ; do
+A=`echo $line | cut -c 1`
+
+if [ "$A" = '~' ] ; then
+FROM=`echo $line | tr \~ \( | tr \) \(  | awk -F\( '{print $3}'`
+TO=`echo $line  | tr \~ \( | tr \) \(|awk -F\( '{print $2}'`
+addr2line -e ../../build/coreboot_ram.debug "$FROM" | tr -d "\n"
+echo -n " calls "
+addr2line -e ../../build/coreboot_ram.debug "$TO"
+else
+echo "$line"
+fi
+
+done



From r.marek at assembler.cz  Fri Sep  2 23:49:26 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 02 Sep 2011 23:49:26 +0200
Subject: [coreboot] [RFC] tracing execution flow
In-Reply-To: <4E5C0FB8.4040202@assembler.cz>
References: <4E5C0FB8.4040202@assembler.cz>
Message-ID: <4E614F66.8030206@assembler.cz>

Hi all,

I wrote a tool to convert the console traces to gprof file.
Now a generation of nice callgraphs is possible:

/genprof /tmp/yourlog ;  gprof ../../build/coreboot_ram |  ./gprof2dot.py -e0 
-n0 | dot -Tpng -o output.png

Check them on http://assembler.cz/output.png (for QEMU)
Check them on http://assembler.cz/output_cb.png (for Asrock 939 board)

As soon as I figure out how to deal with git thinking I still have some new 
revisions of my previous work I commit the changes to gerrit.

Thanks
Rudolf





From gerrit at coreboot.org  Sat Sep  3 13:35:38 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Sep 2011 13:35:38 +0200
Subject: [coreboot] New patch to review: 1874079 Simplify kconfig handling
	some more
References: <I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8+0@gerrit.coreboot.org>
Message-ID: <I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/180

-gerrit

commit 1874079af233466bf6988ac32748195028072dd2
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Sep 3 13:29:27 2011 +0200

    Simplify kconfig handling some more
    
    Inspired by http://patchwork.coreboot.org/patch/1757/, this
    simplifies the build some more.
    Also fixes menuconfig if the compiler is picky about file naming order.
    
    Change-Id: I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/kconfig/Makefile |   91 +++++++++++--------------------------------------
 1 files changed, 20 insertions(+), 71 deletions(-)

diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile
index 64a340c..17d7f46 100644
--- a/util/kconfig/Makefile
+++ b/util/kconfig/Makefile
@@ -24,88 +24,42 @@ $(if $(and $(HAVE_FILO_CONFIG),$(filter 0,$(words $(LIB_CONFIG)))), \
   FATAL:=1, \
   FATAL:=0)
 
-LIBPAYLOAD_CONFIG_PRE := echo "Libpayload config for FILO." \
-    $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG) $(FILO_CONFIG).temp) \
-    $(if $(HAVE_LIB_CONFIG),; mv $(LIB_CONFIG) $(FILO_CONFIG))
-
-LIBPAYLOAD_CONFIG_POST := mv $(FILO_CONFIG) $(LIB_CONFIG) \
-        ; echo "Libpayload config done." \
-        $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG).temp $(FILO_CONFIG))
-
-ifeq ($(FATAL),1)
-xconfig gconfig menuconfig config oldconfig silentoldconfig:
-	echo "Lost libpayload config file."
-	rm -f $(FILO_CONFIG)
-else
-xconfig: prepare $(objk)/qconf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/qconf $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+libpayload_config_%:
+	echo "Libpayload config for FILO."
+	$(MAKE) -C $(LIBCONFIG_PATH) KCONFIG_CONFIG=$(LIB_CONFIG) $(patsubst libpayload_config_%,%,$@)
+	echo "Libpayload config done."
+
+xconfig: prepare $(objk)/qconf libpayload_config_xconfig
 	$(objk)/qconf $(Kconfig)
 
-gconfig: prepare $(objk)/gconf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/gconf $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+gconfig: prepare $(objk)/gconf libpayload_config_gconfig
 	$(objk)/gconf $(Kconfig)
 
-menuconfig: prepare $(objk)/mconf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/mconf $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+menuconfig: prepare $(objk)/mconf libpayload_config_menuconfig
 	$(objk)/mconf $(Kconfig)
 
-config: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+config: prepare $(objk)/conf libpayload_config_config
 	$(objk)/conf $(Kconfig)
 
-oldconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+oldconfig: prepare $(objk)/conf libpayload_config_oldconfig
 	$(objk)/conf -o $(Kconfig)
 
-silentoldconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+silentoldconfig: prepare $(objk)/conf libpayload_config_silentoldconfig
 	$(objk)/conf -s $(Kconfig)
 
-randconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -r $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+randconfig: prepare $(objk)/conf libpayload_config_randconfig
 	$(objk)/conf -r $(Kconfig)
 
-allyesconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -y $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+allyesconfig: prepare $(objk)/conf libpayload_config_allyesconfig
 	$(objk)/conf -y $(Kconfig)
 
-allnoconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -n $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+allnoconfig: prepare $(objk)/conf libpayload_config_allnoconfig
 	$(objk)/conf -n $(Kconfig)
 
-allmodconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -m $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+allmodconfig: prepare $(objk)/conf libpayload_config_allmodconfig
 	$(objk)/conf -m $(Kconfig)
 
-defconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-ifeq ($(KBUILD_DEFCONFIG),)
-	$(objk)/conf -D $(LIBCONFIG_PATH)/configs/defconfig $(LIBCONFIG_PATH)/Config.in
-else
-	@echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'"
-	$(objk)/conf -D $(LIBCONFIG_PATH)/$(KBUILD_DEFCONFIG) $(LIBCONFIG_PATH)/Config.in
-endif
-	$(LIBPAYLOAD_CONFIG_POST)
+defconfig: prepare $(objk)/conf libpayload_config_defconfig
 ifeq ($(KBUILD_DEFCONFIG),)
 	$(objk)/conf -d $(Kconfig)
 else
@@ -113,14 +67,9 @@ else
 	$(objk)/conf -D $(KBUILD_DEFCONFIG) $(Kconfig)
 endif
 
-%_defconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -D $(LIBCONFIG_PATH)/configs/$@ $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+%_defconfig: prepare $(objk)/conf libpayload_config_%_defconfig
 	$(objk)/conf -D configs/$@ $(Kconfig)
 
-endif # "FATAL"
-
 # Help text used by make help
 help:
 	@echo  '  config	  - Update current config utilising a line-oriented program'
@@ -341,11 +290,11 @@ endif
 
 $(objk)/qconf: $(patsubst %,$(objk)/%,$(qconf-cxxobjs)) \
 	       $(patsubst %,$(objk)/%,$(qconf-objs))
-	$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTLOADLIBES_qconf) -o $@ $^
+	$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ $^ $(HOSTLOADLIBES_qconf)
 $(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs))
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) -o $@ $^ $(HOSTLOADLIBES_gconf)
 $(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs))
-	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ $(HOST_LOADLIBES)
 $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs))
 	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^
 



From gerrit at coreboot.org  Sat Sep  3 13:35:39 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Sep 2011 13:35:39 +0200
Subject: [coreboot] New patch to review: a81e32c Trivial compilation fix
References: <I9e1ef711b62a42b1ddbd620d09a9c19a6e1ff0db+0@gerrit.coreboot.org>
Message-ID: <I9e1ef711b62a42b1ddbd620d09a9c19a6e1ff0db+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/181

-gerrit

commit a81e32cd0ea95aeea75b894b00f0924f7d635216
Author: Aur?lien <footplus at gmail.com>
Date:   Thu Sep 9 18:39:10 2010 +0200

    Trivial compilation fix
    
    Change-Id: I9e1ef711b62a42b1ddbd620d09a9c19a6e1ff0db
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 main/grub/completions.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/main/grub/completions.c b/main/grub/completions.c
index 6588301..c54a558 100644
--- a/main/grub/completions.c
+++ b/main/grub/completions.c
@@ -23,6 +23,7 @@
 #include <config.h>
 #include <grub/shared.h>
 #define current_slice 0
+#define IS_PC_SLICE_TYPE_BSD(type) 0
 
 static int do_completion;
 static int unique;



From gerrit at coreboot.org  Sat Sep  3 13:35:39 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Sep 2011 13:35:39 +0200
Subject: [coreboot] New patch to review: e869861 Utility for generating an
	Artecboot image
References: <I855845fffae57472d027e20a8db25b19f106a488+0@gerrit.coreboot.org>
Message-ID: <I855845fffae57472d027e20a8db25b19f106a488+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/182

-gerrit

commit e8698619be9024fef2babeaccebd7a7a65ce3f2f
Author: Nathan Williams <nathan at traverse.com.au>
Date:   Mon Apr 4 01:36:13 2011 +0200

    Utility for generating an Artecboot image
    
    This program outputs a binary file with artecboot header and
    Linux kernel that can be used with the FILO Artecboot loader.
    
    Change-Id: I855845fffae57472d027e20a8db25b19f106a488
    Signed-off-by: Nathan Williams <nathan at traverse.com.au>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/artecimage.c |  200 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 200 insertions(+), 0 deletions(-)

diff --git a/util/artecimage.c b/util/artecimage.c
new file mode 100644
index 0000000..ee282cc
--- /dev/null
+++ b/util/artecimage.c
@@ -0,0 +1,200 @@
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+
+#define PROG_NAME "artecimage"
+#define VERSION "1.1"
+
+#define BUFSIZE 512
+
+// Artecboot header, gives information to loader
+
+#define ARTECBOOT_HEADER_MAGIC	0x10ADFACE
+#define CURRENT_VERSION		0x0102
+
+#define OS_UNKNOWN		0x00
+#define OS_LINUX		0x01
+#define OS_WINCE		0x02
+
+#define FLAG_INITRD		0x0001	// if set, the loader will provide initrd to kernel
+#define FLAG_FILESYSTEM		0x0002	// if set, the loader will use specified file names
+#define FLAG_CMDLINE		0x0004	// if set, the loader will pass the new command line
+
+#define ABOOT_FILE_KERNEL	"/kernel"
+#define ABOOT_FILE_INITRD	"/initrd"
+#define ABOOT_FILE_HEADER	"/header"
+
+#define DEV_SECTOR_SIZE		512
+#define DEV_SECTOR_BITS		9
+
+typedef struct __attribute__ ((packed))
+{
+	unsigned long	magicHeader;
+	unsigned short	bootVersion;
+	unsigned short	headerSize;		// also kernel image start
+	unsigned long	imageSize;		// NB! since 1.02 is the total image/partition size
+	unsigned long	bitFlags;
+	unsigned short	osType;
+	char		cmdLine[256];
+	unsigned long	kernelStart;		// used with Artecboot VFS / NULLFS
+	unsigned long	kernelSize;		// used with Artecboot VFS / NULLFS
+	unsigned long	initrdStart;		// used with Artecboot VFS / NULLFS
+	unsigned long	initrdSize;		// used with Artecboot VFS / NULLFS
+	char		kernelFile[100];	// valid only with FLAG_FILESYSTEM
+	char		initrdFile[100];	// valid only with FLAG_FILESYSTEM
+
+} ARTECBOOT_HEADER;
+
+void usage(void);
+
+int main(int argc, char **argv){
+	ARTECBOOT_HEADER bootHdr;
+	FILE *BINFILE = 0;
+	FILE *KERNFILE = 0;
+	FILE *INITRDFILE = 0;
+	char buf[BUFSIZE];
+	int c;
+	int i;
+	int verbose = 0;
+
+	/* clear header */
+	memset(&bootHdr, 0, sizeof(ARTECBOOT_HEADER));
+
+	while ((c = getopt(argc, argv, "c:hi:k:o:v")) != -1) {
+		switch(c) {
+			case 'c':
+				if (strlen(optarg) < sizeof(bootHdr.cmdLine)) {
+					strcpy(bootHdr.cmdLine, optarg);
+					bootHdr.bitFlags |= FLAG_CMDLINE;
+				} else {
+					usage();
+					printf("\nCommand line exceeds %d char limit\n", (sizeof(bootHdr.cmdLine) - 1));
+					return 1;
+				}
+				break;
+			case 'h':
+				usage();
+				return 0;
+				break;
+			case 'i':
+				INITRDFILE = fopen(optarg,"r");
+			        if(INITRDFILE == NULL){
+					usage();
+			                printf("\nError: Failed to open file '%s'\n\n", optarg);
+			                return 1;
+				}
+				break;
+			case 'k':
+				KERNFILE = fopen(optarg,"r");
+			        if(KERNFILE == NULL){
+					usage();
+			                printf("\nError: Failed to open file '%s'\n\n", optarg);
+			                return 1;
+				}
+				break;
+			case 'o':
+				BINFILE = fopen(optarg,"w");
+			        if(BINFILE == NULL){
+					usage();
+			                printf("\nError: Failed to open file '%s'\n\n", optarg);
+			                return 1;
+				}
+				break;
+			case 'v':
+				verbose = 1;
+				break;
+		}
+	}				
+	if(!BINFILE){
+		usage();
+		printf("\nError: No output file specified\n\n");
+		return 1;
+	}
+
+	if(!KERNFILE){
+		usage();
+		printf("\nError: No kernel image specified\n\n");
+		return 1;
+	}
+
+	bootHdr.magicHeader = ARTECBOOT_HEADER_MAGIC;
+	bootHdr.bootVersion = CURRENT_VERSION;
+	bootHdr.headerSize = sizeof(ARTECBOOT_HEADER);
+
+	/* Get kernel image size */
+	fseek(KERNFILE, 0L, SEEK_END);
+	bootHdr.imageSize = ftell(KERNFILE);
+
+	bootHdr.kernelSize = bootHdr.imageSize;
+	bootHdr.kernelStart = DEV_SECTOR_SIZE;
+
+	bootHdr.osType = OS_LINUX;
+
+	if(INITRDFILE){
+		/* Get initrd image size */
+		fseek(INITRDFILE, 0L, SEEK_END);
+		bootHdr.initrdSize = ftell(INITRDFILE);
+
+		/* Set INITRD flag */
+		bootHdr.bitFlags |= FLAG_INITRD;
+
+		/* Calculate start address (512 boundary) */
+		bootHdr.initrdStart = (bootHdr.kernelStart + bootHdr.imageSize);
+		bootHdr.initrdStart = (bootHdr.initrdStart >> DEV_SECTOR_BITS) + 1;
+		bootHdr.initrdStart <<= DEV_SECTOR_BITS;
+	}
+
+	fwrite(&bootHdr, 1, sizeof(ARTECBOOT_HEADER), BINFILE);
+	fseek(BINFILE, bootHdr.kernelStart, SEEK_SET);
+
+	/* Copy kernel into output file */	
+	fseek(KERNFILE, 0, SEEK_SET);
+	while((i = fread(&buf, 1, BUFSIZE, KERNFILE)) != 0){
+		fwrite(&buf, 1, i, BINFILE);
+	}
+	fclose(KERNFILE);
+
+	if(INITRDFILE){
+		fseek(BINFILE, bootHdr.initrdStart, SEEK_SET);
+
+		/* Copy initrd into output file */
+		fseek(INITRDFILE, 0, SEEK_SET);
+		while((i = fread(&buf, 1, BUFSIZE, INITRDFILE)) != 0){
+			fwrite(&buf, 1, i, BINFILE);
+		}
+		fclose(INITRDFILE);
+	}
+
+	fclose(BINFILE);
+	
+	if(verbose){
+		printf("magicHeader: 0x%04lx\n", bootHdr.magicHeader);
+		printf("bootVersion: 0x%04x\n", bootHdr.bootVersion);
+		printf("headerSize:  0x%08x\n", bootHdr.headerSize);
+		printf("imageSize:   0x%08lx\n", bootHdr.imageSize);
+		printf("bitFlags:    0x%08lx\n", bootHdr.bitFlags);
+		printf("osType:      0x%04x\n", bootHdr.osType);
+		printf("cmdLine:     %s\n", bootHdr.cmdLine);
+		printf("kernelStart: 0x%08lx\n", bootHdr.kernelStart);
+		printf("kernelSize:  0x%08lx\n", bootHdr.imageSize);
+		printf("initrdStart: 0x%08lx\n", bootHdr.initrdStart);
+		printf("initrdSize:  0x%08lx\n", bootHdr.initrdSize);
+		printf("kernelFile:  %s\n", bootHdr.kernelFile);
+		printf("initrdFile:  %s\n", bootHdr.initrdFile);
+	}
+	return 0;
+}
+
+void usage(void) {
+	printf(PROG_NAME " v" VERSION "\n"
+	       "Usage: " PROG_NAME " [-hv] [-c cmdline] [-i initrd] -k kernel -o outfile\n\n"
+	       "Options:\n"
+	       "  -c cmdline  Kernel command line (max 255 chars).\n"
+	       "  -h          Display this help.\n"
+	       "  -i initrd   initrd filename.\n"
+	       "  -k kernel   Linux kernel filename.\n"
+	       "  -o outfile  Write image to outfile.\n"
+	       "  -v          Verbose.\n"
+	);
+	return;
+}



From gerrit at coreboot.org  Sat Sep  3 13:39:49 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Sep 2011 13:39:49 +0200
Subject: [coreboot] Patch set updated: 79c690a Simplify kconfig handling
	some more
References: <I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8+0@gerrit.coreboot.org>
Message-ID: <I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/180

-gerrit

commit 79c690a5e0b60f318837f152df0f7baf412f2149
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Sep 3 13:29:27 2011 +0200

    Simplify kconfig handling some more
    
    Inspired by http://patchwork.coreboot.org/patch/1757/, this
    simplifies the build some more.
    Also fixes menuconfig if the compiler is picky about file naming order.
    
    Change-Id: I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/kconfig/Makefile |   97 ++++++++++---------------------------------------
 1 files changed, 20 insertions(+), 77 deletions(-)

diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile
index 64a340c..70c3870 100644
--- a/util/kconfig/Makefile
+++ b/util/kconfig/Makefile
@@ -18,94 +18,42 @@ LIB_CONFIG  := $(src)/lib.config
 HAVE_FILO_CONFIG := $(wildcard $(FILO_CONFIG))
 HAVE_LIB_CONFIG := $(wildcard $(LIB_CONFIG))
 
-# We don't know how to cope with FILO config being present and
-# libpayload config not.
-$(if $(and $(HAVE_FILO_CONFIG),$(filter 0,$(words $(LIB_CONFIG)))), \
-  FATAL:=1, \
-  FATAL:=0)
-
-LIBPAYLOAD_CONFIG_PRE := echo "Libpayload config for FILO." \
-    $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG) $(FILO_CONFIG).temp) \
-    $(if $(HAVE_LIB_CONFIG),; mv $(LIB_CONFIG) $(FILO_CONFIG))
-
-LIBPAYLOAD_CONFIG_POST := mv $(FILO_CONFIG) $(LIB_CONFIG) \
-        ; echo "Libpayload config done." \
-        $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG).temp $(FILO_CONFIG))
-
-ifeq ($(FATAL),1)
-xconfig gconfig menuconfig config oldconfig silentoldconfig:
-	echo "Lost libpayload config file."
-	rm -f $(FILO_CONFIG)
-else
-xconfig: prepare $(objk)/qconf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/qconf $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+libpayload_config_%:
+	echo "Libpayload config for FILO."
+	$(MAKE) -C $(LIBCONFIG_PATH) KCONFIG_CONFIG=$(LIB_CONFIG) $(patsubst libpayload_config_%,%,$@)
+	echo "Libpayload config done."
+
+xconfig: prepare $(objk)/qconf libpayload_config_xconfig
 	$(objk)/qconf $(Kconfig)
 
-gconfig: prepare $(objk)/gconf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/gconf $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+gconfig: prepare $(objk)/gconf libpayload_config_gconfig
 	$(objk)/gconf $(Kconfig)
 
-menuconfig: prepare $(objk)/mconf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/mconf $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+menuconfig: prepare $(objk)/mconf libpayload_config_menuconfig
 	$(objk)/mconf $(Kconfig)
 
-config: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+config: prepare $(objk)/conf libpayload_config_config
 	$(objk)/conf $(Kconfig)
 
-oldconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+oldconfig: prepare $(objk)/conf libpayload_config_oldconfig
 	$(objk)/conf -o $(Kconfig)
 
-silentoldconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+silentoldconfig: prepare $(objk)/conf libpayload_config_silentoldconfig
 	$(objk)/conf -s $(Kconfig)
 
-randconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -r $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+randconfig: prepare $(objk)/conf libpayload_config_randconfig
 	$(objk)/conf -r $(Kconfig)
 
-allyesconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -y $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+allyesconfig: prepare $(objk)/conf libpayload_config_allyesconfig
 	$(objk)/conf -y $(Kconfig)
 
-allnoconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -n $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+allnoconfig: prepare $(objk)/conf libpayload_config_allnoconfig
 	$(objk)/conf -n $(Kconfig)
 
-allmodconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -m $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+allmodconfig: prepare $(objk)/conf libpayload_config_allmodconfig
 	$(objk)/conf -m $(Kconfig)
 
-defconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-ifeq ($(KBUILD_DEFCONFIG),)
-	$(objk)/conf -D $(LIBCONFIG_PATH)/configs/defconfig $(LIBCONFIG_PATH)/Config.in
-else
-	@echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'"
-	$(objk)/conf -D $(LIBCONFIG_PATH)/$(KBUILD_DEFCONFIG) $(LIBCONFIG_PATH)/Config.in
-endif
-	$(LIBPAYLOAD_CONFIG_POST)
+defconfig: prepare $(objk)/conf libpayload_config_defconfig
 ifeq ($(KBUILD_DEFCONFIG),)
 	$(objk)/conf -d $(Kconfig)
 else
@@ -113,14 +61,9 @@ else
 	$(objk)/conf -D $(KBUILD_DEFCONFIG) $(Kconfig)
 endif
 
-%_defconfig: prepare $(objk)/conf
-	$(LIBPAYLOAD_CONFIG_PRE)
-	$(objk)/conf -D $(LIBCONFIG_PATH)/configs/$@ $(LIBCONFIG_PATH)/Config.in
-	$(LIBPAYLOAD_CONFIG_POST)
+%_defconfig: prepare $(objk)/conf libpayload_config_%_defconfig
 	$(objk)/conf -D configs/$@ $(Kconfig)
 
-endif # "FATAL"
-
 # Help text used by make help
 help:
 	@echo  '  config	  - Update current config utilising a line-oriented program'
@@ -341,11 +284,11 @@ endif
 
 $(objk)/qconf: $(patsubst %,$(objk)/%,$(qconf-cxxobjs)) \
 	       $(patsubst %,$(objk)/%,$(qconf-objs))
-	$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTLOADLIBES_qconf) -o $@ $^
+	$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ $^ $(HOSTLOADLIBES_qconf)
 $(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs))
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) -o $@ $^ $(HOSTLOADLIBES_gconf)
 $(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs))
-	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ $(HOST_LOADLIBES)
 $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs))
 	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^
 



From gerrit at coreboot.org  Sat Sep  3 13:48:04 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Sep 2011 13:48:04 +0200
Subject: [coreboot] New patch to review: 66367fa Replace while with do;
	while to avoid repetition
References: <Ie0a4fa622df881edeaab08f59bb888a903b864fd+0@gerrit.coreboot.org>
Message-ID: <Ie0a4fa622df881edeaab08f59bb888a903b864fd+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/183

-gerrit

commit 66367fa77ecc1501bdb2b081370268442e45408d
Author: Noe Rubinstein <nrubinstein at proformatique.com>
Date:   Thu May 5 15:44:40 2011 +0200

    Replace while with do; while to avoid repetition
    
    Cosmetic only; replaces some 'while' loops with 'do; while' loops to
    avoid repetition.
    
    Replacement performed by the Ruby expression:
    t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
    	"\\1do \\2\n\\1\\3;")
    
    Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
    Signed-off-by: Noe Rubinstein <nrubinstein at proformatique.com>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/northbridge/intel/e7520/raminit.c         |   55 +++++++++--------------
 src/northbridge/intel/e7525/raminit.c         |   55 +++++++++--------------
 src/northbridge/intel/i3100/raminit.c         |   55 +++++++++--------------
 src/northbridge/intel/i3100/raminit_ep80579.c |   60 ++++++++++---------------
 4 files changed, 90 insertions(+), 135 deletions(-)

diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 7a0661c..e9a60f1 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -1128,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 		write32(BAR+0x100, (0x83000000 | (i<<20)));
 
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 
 	}
 
@@ -1139,9 +1138,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs++) {
 		write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1152,9 +1150,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* EMRS dll's enabled */
@@ -1166,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000001);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	/* MRS reset dll's */
 	do_delay();
@@ -1187,9 +1183,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, mode_reg);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1202,25 +1197,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do 2 refreshes */
 	do_delay();
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	/* for good luck do 6 more */
@@ -1253,9 +1245,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do only if DDR2  EMRS dll's enabled */
@@ -1264,9 +1255,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 for(cs=0;cs<8;cs++) {
                         write32(BAR+DCALADDR, (0x0b940001));
                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-			data32 = read32(BAR+DCALCSR);
-			while(data32 & 0x80000000)
-				data32 = read32(BAR+DCALCSR);
+			do data32 = read32(BAR+DCALCSR);
+			while(data32 & 0x80000000);
                 }
         }
 
@@ -1310,9 +1300,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Bring memory subsystem on line */
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 495a142..e341596 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -1104,9 +1104,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 		write32(BAR+0x100, (0x83000000 | (i<<20)));
 
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 
 	}
 
@@ -1115,9 +1114,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs++) {
 		write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1128,9 +1126,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* EMRS dll's enabled */
@@ -1142,9 +1139,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000001);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	/* MRS reset dll's */
 	do_delay();
@@ -1163,9 +1159,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, mode_reg);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1178,25 +1173,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do 2 refreshes */
 	do_delay();
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	/* for good luck do 6 more */
@@ -1229,9 +1221,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do only if DDR2  EMRS dll's enabled */
@@ -1240,9 +1231,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 for(cs=0;cs<8;cs++) {
                         write32(BAR+DCALADDR, (0x0b940001));
                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-			data32 = read32(BAR+DCALCSR);
-			while(data32 & 0x80000000)
-				data32 = read32(BAR+DCALCSR);
+			do data32 = read32(BAR+DCALCSR);
+			while(data32 & 0x80000000);
                 }
         }
 
@@ -1283,9 +1273,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Bring memory subsystem on line */
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 86e610f..ced3de1 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -1020,9 +1020,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));
 		write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
 
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Apply NOP */
@@ -1030,9 +1029,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1040,9 +1038,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, 0x04000000);
 		write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* EMRS dll's enabled */
@@ -1051,9 +1048,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		/* fixme hard code AL additive latency */
 		write32(MCBAR+DCALADDR, 0x0b940001);
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	/* MRS reset dll's */
 	do_delay();
@@ -1064,9 +1060,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, mode_reg);
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
@@ -1076,25 +1071,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, 0x04000000);
 		write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do 2 refreshes */
 	do_delay();
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	/* for good luck do 6 more */
@@ -1127,9 +1119,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do only if DDR2  EMRS dll's enabled */
@@ -1137,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, (0x0b940001));
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	do_delay();
@@ -1173,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	for(cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
-		data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(MCBAR+DCALCSR);
+		do data32 = read32(MCBAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Bring memory subsystem on line */
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 8967594..de3ffce 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -534,9 +534,8 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 }
 
@@ -603,9 +602,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		udelay(16);
 		write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
 		write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* Apply NOP */
@@ -615,9 +613,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug_hex8(cs);
 		print_debug("\n");
 		write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* Precharge all banks */
@@ -628,9 +625,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, 0x04000000);
 		write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* EMRS: Enable DLLs, set OCD calibration mode to default */
@@ -641,9 +637,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 	/* MRS: Reset DLLs */
 	udelay(16);
@@ -653,9 +648,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, mode_reg);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* Precharge all banks */
@@ -666,9 +660,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, 0x04000000);
 		write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* Do 2 refreshes */
@@ -679,9 +672,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 			print_debug_hex8(cs);
 			print_debug("\n");
 			write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
-			data32 = read32(BAR+DCALCSR);
-			while (data32 & 0x80000000)
-				data32 = read32(BAR+DCALCSR);
+			do data32 = read32(BAR+DCALCSR);
+			while (data32 & 0x80000000);
 		}
 	}
 
@@ -693,9 +685,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	/* EMRS: Enable DLLs */
@@ -706,9 +697,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug("\n");
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
         }
 
 	udelay(16);
@@ -729,9 +719,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug_hex8(cs);
 		print_debug("\n");
 		write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
-		data32 = read32(BAR+DCALCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while (data32 & 0x80000000);
 	}
 
 	dump_dcal_regs();
@@ -756,9 +745,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		print_debug_hex8(cs);
 		print_debug("\n");
 		write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
-		data32 = read32(BAR+MBCSR);
-		while (data32 & 0x80000000)
-			data32 = read32(BAR+MBCSR);
+		do data32 = read32(BAR+MBCSR);
+		while (data32 & 0x80000000);
 		if (data32 & 0x40000000)
 			print_debug("failed!\n");
 	}



From gerrit at coreboot.org  Sat Sep  3 13:49:58 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Sep 2011 13:49:58 +0200
Subject: [coreboot] New patch to review: b8fe009 Report GSE chipset and warn
	if the code has been compiled for the wrong chipset.
References: <Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0+0@gerrit.coreboot.org>
Message-ID: <Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/184

-gerrit

commit b8fe009787a26f079b236a26ebc0c6e676c0c884
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Fri Apr 1 22:33:25 2011 +0200

    Report GSE chipset and warn if the code has been compiled for the wrong chipset.
    
    It would be nicer to unify the code so that it does all detection at runtime
    instead of compile time (but that would also significantly increase code size)
    so if someone else wants to give it a shot...
    
    Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/northbridge/intel/i945/early_init.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 21efc37..197c58f 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -42,7 +42,7 @@ static void i945m_detect_chipset(void)
 		printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
 		break;
 	case 2:
-		printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express");
 		break;
 	case 3:
 		printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express");
@@ -91,6 +91,9 @@ static void i945m_detect_chipset(void)
 		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
 	printk(BIOS_DEBUG, "\n");
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+	printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
+#endif
 }
 
 static void i945_detect_chipset(void)
@@ -137,6 +140,9 @@ static void i945_detect_chipset(void)
 		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
 	printk(BIOS_DEBUG, "\n");
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+	printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
+#endif
 }
 
 static void i945_setup_bars(void)



From gerrit at coreboot.org  Sat Sep  3 13:52:43 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Sep 2011 13:52:43 +0200
Subject: [coreboot] New patch to review: 4f27a0a inteltool: added more
	device IDs
References: <I6f2272ae4071025e671638e83bade6a96aac658b+0@gerrit.coreboot.org>
Message-ID: <I6f2272ae4071025e671638e83bade6a96aac658b+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/185

-gerrit

commit 4f27a0a423753b7b5d6d088c6a2411a6ecc7dad2
Author: Ruud Schramp <schramp at holmes.nl>
Date:   Mon Apr 4 07:53:19 2011 +0200

    inteltool: added more device IDs
    
    Change-Id: I6f2272ae4071025e671638e83bade6a96aac658b
    Signed-off-by: Ruud Schramp <schramp at holmes.nl>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/inteltool/inteltool.c |    2 ++
 util/inteltool/inteltool.h |    2 ++
 util/inteltool/memory.c    |    2 ++
 util/inteltool/pcie.c      |    6 ++++++
 4 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index a416106..93169d3 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -80,6 +80,8 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
 };
 
 #ifndef __DARWIN__
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index ca8066f..24846c8 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -78,6 +78,8 @@
 #define PCI_DEVICE_ID_INTEL_82Q35		0x29b0
 #define PCI_DEVICE_ID_INTEL_82G33		0x29c0
 #define PCI_DEVICE_ID_INTEL_82Q33		0x29d0
+#define PCI_DEVICE_ID_INTEL_X44 		0x29e0
+#define PCI_DEVICE_ID_INTEL_32X0		0x29F0
 #define PCI_DEVICE_ID_INTEL_GS45		0x2a40
 #define PCI_DEVICE_ID_INTEL_X58			0x3405
 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO		0x8100
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 256204c..9230419 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -109,6 +109,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 		printf("This northbridge does not have MCHBAR.\n");
 		return 1;
 	case PCI_DEVICE_ID_INTEL_GS45:
+	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_32X0:
 		mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
  		break;
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 1ca57b6..4913150 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -45,6 +45,8 @@ int print_epbar(struct pci_dev *nb)
  	case PCI_DEVICE_ID_INTEL_82Q35:
  	case PCI_DEVICE_ID_INTEL_82G33:
  	case PCI_DEVICE_ID_INTEL_82Q33:
+	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_32X0:
 	case PCI_DEVICE_ID_INTEL_GS45:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
@@ -104,6 +106,8 @@ int print_dmibar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_82Q35:
 	case PCI_DEVICE_ID_INTEL_82G33:
 	case PCI_DEVICE_ID_INTEL_82Q33:
+	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_32X0:
 	case PCI_DEVICE_ID_INTEL_GS45:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
@@ -167,6 +171,8 @@ int print_pciexbar(struct pci_dev *nb)
  	case PCI_DEVICE_ID_INTEL_82Q35:
  	case PCI_DEVICE_ID_INTEL_82G33:
  	case PCI_DEVICE_ID_INTEL_82Q33:
+	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_32X0:
 	case PCI_DEVICE_ID_INTEL_GS45:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:



From gerrit at coreboot.org  Sat Sep  3 21:25:29 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Sep 2011 21:25:29 +0200
Subject: [coreboot] New patch to review: f787a41 Adjust some code/comment of
	sb700 sata init
References: <I63480da60e51cdc68e64c302ad2d8a6197e288f6+0@gerrit.coreboot.org>
Message-ID: <I63480da60e51cdc68e64c302ad2d8a6197e288f6+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/186

-gerrit

commit f787a41e3ae338b7d337236b69761dddde2340fe
Author: Wang Qing Pei <wangqingpei at gmail.com>
Date:   Tue Nov 9 09:17:07 2010 +0100

    Adjust some code/comment of sb700 sata init
    
    The inline comment of sata_init function seems not placed correctly.
    Rearrange it.
    
    Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6
    Signed-off-by: Wang Qing Pei <wangqingpei at gmail.com>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/southbridge/amd/sb700/sata.c |    9 ++++-----
 1 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 411baf5..58b72ad 100755
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -91,14 +91,13 @@ static void sata_init(struct device *dev)
 
 	device_t sm_dev;
 	/* SATA SMBus Disable */
-	/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	/* Disable SATA SMBUS */
-	byte = pci_read_config8(sm_dev, 0xad);
-	byte |= (1 << 1);
-	/* Enable SATA and power saving */
+
 	byte = pci_read_config8(sm_dev, 0xad);
+	/* Disable SATA SMBUS */
 	byte |= (1 << 0);
+	/* Enable SATA and power saving */
+	byte |= (1 << 1);
 	byte |= (1 << 5);
 	pci_write_config8(sm_dev, 0xad, byte);
 



From gerrit at coreboot.org  Sat Sep  3 21:28:24 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Sep 2011 21:28:24 +0200
Subject: [coreboot] New patch to review: 7b67759 Disable dev3 on ma78gm-us2h
References: <Ia355ee385fd0f37793b4bdf1815c033670823eaa+0@gerrit.coreboot.org>
Message-ID: <Ia355ee385fd0f37793b4bdf1815c033670823eaa+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/187

-gerrit

commit 7b67759c7f1711e7e7305440bfd476f4f12486bd
Author: Wang Qing Pei <wangqingpei at gmail.com>
Date:   Tue Nov 9 09:09:47 2010 +0100

    Disable dev3 on ma78gm-us2h
    
    Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot.
    
    Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa
    Signed-off-by: Wang Qing Pei <wangqingpei at gmail.com>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/mainboard/gigabyte/ma78gm/devicetree.cb |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb
index 1aa859f..2fb4824 100644
--- a/src/mainboard/gigabyte/ma78gm/devicetree.cb
+++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb
@@ -13,7 +13,7 @@ chip northbridge/amd/amdfam10/root_complex
 					device pci 0.0 on end # HT  	0x9600
 					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
-					device pci 3.0 on end # PCIE P2P bridge	0x960b
+					device pci 3.0 off end # PCIE P2P bridge	0x960b
 					device pci 4.0 on end # PCIE P2P bridge 0x9604
 					device pci 5.0 off end # PCIE P2P bridge 0x9605
 					device pci 6.0 off end # PCIE P2P bridge 0x9606



From gerrit at coreboot.org  Sun Sep  4 05:50:44 2011
From: gerrit at coreboot.org (Raymond Danks (raymonddanks@gmail.com))
Date: Sun, 4 Sep 2011 05:50:44 +0200
Subject: [coreboot] Patch set updated: 56440ee mkelfImage: Use
	-fno-stack-protector if supported by gcc
References: <I28ef158829f5935f985cfd5a5440733685cf479a+0@gerrit.coreboot.org>
Message-ID: <I28ef158829f5935f985cfd5a5440733685cf479a+3@gerrit.coreboot.org>

Raymond Danks (raymonddanks at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/112

-gerrit

commit 56440ee651a1508722d3256003fe66d126b0f8e5
Author: Raymond Danks <raymonddanks at gmail.com>
Date:   Sat Sep 3 21:45:38 2011 -0600

    mkelfImage: Use -fno-stack-protector if supported by gcc
    
    Gcc 4.1 comes with an SSP https://wiki.ubuntu.com/GccSsp
    This is disabled to work around '__stack_chk_fail' symbol not found failures
    http://www.coreboot.org/FAQ/Obsolete#How_do_I_fix_stack_chk_fail_errors.3F
    
    The presence of -fno-stack-protector is tested for automatically by configure.
    
    Change-Id: I28ef158829f5935f985cfd5a5440733685cf479a
    Reported-by: Raymond Danks <raymonddanks at gmail.com>
    Signed-off-by: Raymond Danks <raymonddanks at gmail.com>
---
 util/mkelfImage/configure    |   38 +++++++++++++++++++++++++++++++++++++-
 util/mkelfImage/configure.ac |   21 +++++++++++++++++++++
 2 files changed, 58 insertions(+), 1 deletions(-)

diff --git a/util/mkelfImage/configure b/util/mkelfImage/configure
index b3021de..150e5c8 100755
--- a/util/mkelfImage/configure
+++ b/util/mkelfImage/configure
@@ -690,6 +690,7 @@ IA64_LD
 IA64_AS
 IA64_OBJCOPY
 HOST_CC
+libc_cv_fno_stack_protector
 HOST_CFLAGS
 I386_CFLAGS
 I386_ASFLAGS
@@ -4963,6 +4964,40 @@ IA64_LDFLAGS='-static --warn-multiple-gp --warn-common'
 
 
 
+{ echo "$as_me:$LINENO: checking for -fno-stack-protector" >&5
+echo $ECHO_N "checking for -fno-stack-protector... $ECHO_C" >&6; }
+if test "${libc_cv_fno_stack_protector+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+
+cat > conftest.c <<EOF
+int foo;
+main () { return 0;}
+EOF
+if { ac_try='$I386_CC -fno-stack-protector
+                           -o conftest conftest.c 1>&5'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }
+then
+  libc_cv_fno_stack_protector=yes
+else
+  libc_cv_fno_stack_protector=no
+fi
+rm -f conftest*
+fi
+{ echo "$as_me:$LINENO: result: $libc_cv_fno_stack_protector" >&5
+echo "${ECHO_T}$libc_cv_fno_stack_protector" >&6; }
+if test $libc_cv_fno_stack_protector = yes; then
+  I386_CFLAGS="$I386_CFLAGS -fno-stack-protector"
+  IA64_CFLAGS="$IA64_CFLAGS -fno-stack-protector"
+
+fi
+
+
+
 
 
 
@@ -5689,6 +5724,7 @@ IA64_LD!$IA64_LD$ac_delim
 IA64_AS!$IA64_AS$ac_delim
 IA64_OBJCOPY!$IA64_OBJCOPY$ac_delim
 HOST_CC!$HOST_CC$ac_delim
+libc_cv_fno_stack_protector!$libc_cv_fno_stack_protector$ac_delim
 HOST_CFLAGS!$HOST_CFLAGS$ac_delim
 I386_CFLAGS!$I386_CFLAGS$ac_delim
 I386_ASFLAGS!$I386_ASFLAGS$ac_delim
@@ -5700,7 +5736,7 @@ LIBOBJS!$LIBOBJS$ac_delim
 LTLIBOBJS!$LTLIBOBJS$ac_delim
 _ACEOF
 
-  if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 86; then
+  if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 87; then
     break
   elif $ac_last_try; then
     { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5
diff --git a/util/mkelfImage/configure.ac b/util/mkelfImage/configure.ac
index 7aebd36..a7fc37e 100644
--- a/util/mkelfImage/configure.ac
+++ b/util/mkelfImage/configure.ac
@@ -186,6 +186,27 @@ IA64_ASFLAGS='-mconstant-gp -mauto-pic'
 IA64_LDFLAGS='-static --warn-multiple-gp --warn-common'
 
 AC_SUBST([HOST_CC])
+
+AC_CACHE_CHECK(for -fno-stack-protector, libc_cv_fno_stack_protector, [
+cat > conftest.c <<EOF
+int foo;
+main () { return 0;}
+EOF
+if AC_TRY_COMMAND([$I386_CC -fno-stack-protector
+                           -o conftest conftest.c 1>&AS_MESSAGE_LOG_FD])
+then
+  libc_cv_fno_stack_protector=yes
+else
+  libc_cv_fno_stack_protector=no
+fi
+rm -f conftest*])
+if test $libc_cv_fno_stack_protector = yes; then
+  I386_CFLAGS="$I386_CFLAGS -fno-stack-protector"
+  IA64_CFLAGS="$IA64_CFLAGS -fno-stack-protector"
+  
+fi
+AC_SUBST(libc_cv_fno_stack_protector)
+
 AC_SUBST([HOST_CFLAGS])
 
 AC_SUBST([I386_CC])



From gerrit at coreboot.org  Sun Sep  4 12:21:39 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sun, 4 Sep 2011 12:21:39 +0200
Subject: [coreboot] Patch merged into master: e869861 Utility for generating
	an Artecboot image
References: <I855845fffae57472d027e20a8db25b19f106a488+0@gerrit.coreboot.org>
Message-ID: <E1R09pb-0000k2-9N@ra.coresystems.de>

the following patch was just integrated into master:
commit e8698619be9024fef2babeaccebd7a7a65ce3f2f
Author: Nathan Williams <nathan at traverse.com.au>
Date:   Mon Apr 4 01:36:13 2011 +0200

    Utility for generating an Artecboot image
    
    This program outputs a binary file with artecboot header and
    Linux kernel that can be used with the FILO Artecboot loader.
    
    Change-Id: I855845fffae57472d027e20a8db25b19f106a488
    Signed-off-by: Nathan Williams <nathan at traverse.com.au>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/182 for details.

-gerrit



From gerrit at coreboot.org  Sun Sep  4 12:22:01 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sun, 4 Sep 2011 12:22:01 +0200
Subject: [coreboot] Patch merged into master: 7b67759 Disable dev3 on
	ma78gm-us2h
References: <Ia355ee385fd0f37793b4bdf1815c033670823eaa+0@gerrit.coreboot.org>
Message-ID: <E1R09px-0000qx-9Q@ra.coresystems.de>

the following patch was just integrated into master:
commit 7b67759c7f1711e7e7305440bfd476f4f12486bd
Author: Wang Qing Pei <wangqingpei at gmail.com>
Date:   Tue Nov 9 09:09:47 2010 +0100

    Disable dev3 on ma78gm-us2h
    
    Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot.
    
    Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa
    Signed-off-by: Wang Qing Pei <wangqingpei at gmail.com>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/187 for details.

-gerrit



From gerrit at coreboot.org  Sun Sep  4 12:22:10 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sun, 4 Sep 2011 12:22:10 +0200
Subject: [coreboot] Patch merged into master: f787a41 Adjust some
	code/comment of sb700 sata init
References: <I63480da60e51cdc68e64c302ad2d8a6197e288f6+0@gerrit.coreboot.org>
Message-ID: <E1R09q6-0000vE-Qc@ra.coresystems.de>

the following patch was just integrated into master:
commit f787a41e3ae338b7d337236b69761dddde2340fe
Author: Wang Qing Pei <wangqingpei at gmail.com>
Date:   Tue Nov 9 09:17:07 2010 +0100

    Adjust some code/comment of sb700 sata init
    
    The inline comment of sata_init function seems not placed correctly.
    Rearrange it.
    
    Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6
    Signed-off-by: Wang Qing Pei <wangqingpei at gmail.com>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/186 for details.

-gerrit



From darmawan.salihun at gmail.com  Sun Sep  4 14:21:05 2011
From: darmawan.salihun at gmail.com (Darmawan Salihun)
Date: Sun, 4 Sep 2011 19:21:05 +0700
Subject: [coreboot] AMD Hudson FCH datasheet
Message-ID: <CAOabStxuMHybxHJqUDJ0eoT4wCi64QB1+rF-3WOBhTjRfiUh9Q@mail.gmail.com>

Hi everyone,

I'm looking for AMD Hudson datasheet. I've looked at the links in the
Coreboot datasheet section but only AMD Family 14h links exists.

Has the Hudson FCH datasheet made public?

Thanks,

Darmawan
-- 
--------------------------------------------------------------------
-= Human knowledge belongs to the world =-



From ljbomir at gmail.com  Sun Sep  4 16:58:40 2011
From: ljbomir at gmail.com (Lyubomir Minchev)
Date: Sun, 4 Sep 2011 17:58:40 +0300
Subject: [coreboot] question
Message-ID: <CAL4qxhg3tVAwYmWNP7qGW5rGik4QpwjUL6axqZ0aGktW3HHZ=A@mail.gmail.com>

Hi All,

I have Laptop HP Pavilion dv4 with Chipset Intel 82801 I (ICH9)

Shall it be compatible with coreboot ?

 some cut :
----------------------------------------------------------------------------------------------------------------------------
[0000:00]-+-00.0  Intel Corporation Mobile 4 Series Chipset Memory
Controller Hub [8086:2a40]
           +-01.0-[01]----00.0  nVidia Corporation G98 [GeForce 9200M GS]
[10de:06e8]
           +-1a.0  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #4 [8086:2937]
           +-1a.1  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #5 [8086:2938]
           +-1a.7  Intel Corporation 82801I (ICH9 Family) USB2 EHCI
Controller #2 [8086:293c]
           +-1b.0  Intel Corporation 82801I (ICH9 Family) HD Audio
Controller [8086:293e]
           +-1c.0-[02]--
           +-1c.1-[03]--
           +-1c.2-[04]----00.0  Intel Corporation PRO/Wireless 5100 AGN
[Shiloh] Network Connection [8086:4237]
           +-1c.3-[05]----00.0  Realtek Semiconductor Co., Ltd.
RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168]
           +-1c.4-[06]--+-00.0  JMicron Technology Corp. SD/MMC Host
Controller [197b:2382]
           |            +-00.2  JMicron Technology Corp. Standard SD Host
Controller [197b:2381]
           |            +-00.3  JMicron Technology Corp. MS Host Controller
[197b:2383]
           |            \-00.4  JMicron Technology Corp. xD Host Controller
[197b:2384]
           +-1c.5-[07-09]--
           +-1d.0  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #1 [8086:2934]
           +-1d.1  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #2 [8086:2935]
           +-1d.2  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #3 [8086:2936]
           +-1d.3  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #6 [8086:2939]
           +-1d.7  Intel Corporation 82801I (ICH9 Family) USB2 EHCI
Controller #1 [8086:293a]
           +-1e.0-[0a]--
           +-1f.0  Intel Corporation ICH9M LPC Interface Controller
[8086:2919]
           +-1f.2  Intel Corporation ICH9M/M-E SATA AHCI Controller
[8086:2929]
           \-1f.3  Intel Corporation 82801I (ICH9 Family) SMBus Controller
[8086:2930]

----------------------------------------------------------------------------------------------------------------------------Regards,

Lyubomir Minchev
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From gerrit at coreboot.org  Sun Sep  4 20:45:12 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sun, 4 Sep 2011 20:45:12 +0200
Subject: [coreboot] New patch to review: 0e277fb Add acpi_get_sleep_type()
	to i82371eb and P2B _PTS/_WAK methods
References: <I13feff0b8f49aa988e5467cdbef02981f0a6be8a+0@gerrit.coreboot.org>
Message-ID: <I13feff0b8f49aa988e5467cdbef02981f0a6be8a+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/188

-gerrit

commit 0e277fb131ed9eee75c1b1c6641b2ac7c2635165
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Mon Dec 13 22:39:46 2010 +0100

    Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods
    
    Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
    Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
    uses the same acpi wakeup vector as S3.
    Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
    the power LED while sleeping.
    acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
    it is used in both romstage and ramstage after patch 3/3, whereas
    i82371eb_early_pm.c is used only in romstage.
    I used the name acpi_get_sleep_type instead of  acpi_is_wakeup_early
    because I think acpi_is_wakeup_early is a bit misleading as a name since it
    doesn't return a boolean value.
    
    Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
    added check for acpi_slp_type == 2 (resume from S2) should not
    change behaviour of other boards:
    northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
    northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
    northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
    northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
    southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
    southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
    southbridge/via/vt8237r/vt8237r_lpc.c:238:  acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
    southbridge/via/vt8237r/vt8237r_lpc.c:239:  printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
    
    Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/acpi.c                    |    7 +++-
 src/lib/cbmem.c                             |    4 +-
 src/mainboard/asus/p2b/dsdt.asl             |   56 ++++++++++++++++++-------
 src/southbridge/intel/i82371eb/Kconfig      |    1 +
 src/southbridge/intel/i82371eb/Makefile.inc |    1 +
 src/southbridge/intel/i82371eb/smbus.c      |   13 +++++-
 src/southbridge/intel/i82371eb/wakeup.c     |   59 +++++++++++++++++++++++++++
 7 files changed, 122 insertions(+), 19 deletions(-)

diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index caf860e..f1be034 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -481,7 +481,8 @@ u8 acpi_slp_type = 0;
 
 static int acpi_is_wakeup(void)
 {
-	return (acpi_slp_type == 3);
+	/* Both resume from S2 and resume from S3 restart at CPU reset */
+	return (acpi_slp_type == 3 || acpi_slp_type == 2);
 }
 
 static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp)
@@ -567,9 +568,11 @@ void *acpi_find_wakeup_vector(void)
 	return wake_vec;
 }
 
+#if CONFIG_SMP
 extern char *lowmem_backup;
 extern char *lowmem_backup_ptr;
 extern int lowmem_backup_size;
+#endif
 
 #define WAKEUP_BASE 0x600
 
@@ -588,12 +591,14 @@ void acpi_jump_to_wakeup(void *vector)
 		return;
 	}
 
+#if CONFIG_SMP
 	// FIXME: This should go into the ACPI backup memory, too. No pork saussages.
 	/*
 	 * Just restore the SMP trampoline and continue with wakeup on
 	 * assembly level.
 	 */
 	memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
+#endif
 
 	/* Copy wakeup trampoline in place. */
 	memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index eecefcd..202f521 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -191,8 +191,10 @@ extern u8 acpi_slp_type;
 void cbmem_initialize(void)
 {
 #if CONFIG_HAVE_ACPI_RESUME
-	if (acpi_slp_type == 3) {
+	printk(BIOS_DEBUG, "%s: acpi_slp_type=%d\n", __func__, acpi_slp_type);
+	if (acpi_slp_type == 3 || acpi_slp_type == 2) {
 		if (!cbmem_reinit(high_tables_base)) {
+			printk(BIOS_DEBUG, "cbmem_reinit failed\n");
 			/* Something went wrong, our high memory area got wiped */
 			acpi_slp_type = 0;
 			cbmem_init(high_tables_base, high_tables_size);
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index 5e6411c..c5befa0 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -21,27 +21,51 @@
 
 DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
 {
-	/* For now only define 2 power states:
-	 *  - S0 which is fully on
-	 *  - S5 which is soft off
-	 * Any others would involve declaring the wake up methods.
-	 */
-
-	/* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */
 	/*
-	000b / 0x0: soft off/suspend to disk (soff/std)			s5
-	001b / 0x1: suspend to ram (str)				s3
-	010b / 0x2: powered on suspend, context lost (poscl)		s1
-	011b / 0x3: powered on suspend, cpu context lost (posccl)	s2
-	100b / 0x4: powered on suspend, context maintained (pos)	s4
-	101b / 0x5: working (clock control)				s0
-	110b / 0x6: reserved
-	111b / 0x7: reserved
-	*/
+	 * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
+	 *
+	 * 0: soft off/suspend to disk					S5
+	 * 1: suspend to ram						S3
+	 * 2: powered on suspend, context lost				S2
+	 *    Note: 'context lost' means the CPU restarts at the reset
+	 *          vector
+	 * 3: powered on suspend, CPU context lost			S1
+	 *    Note: Looks like 'CPU context lost' does _not_ mean the
+	 *          CPU restarts at the reset vector. Most likely only
+	 *          caches are lost, so both 0x3 and 0x4 map to acpi S1
+	 * 4: powered on suspend, context maintained			S1
+	 * 5: working (clock control)					S0
+	 * 6: reserved
+	 * 7: reserved
+	 */
 	Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
 	Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 })
 	Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
 
+	OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2)
+	Field (SIO1, ByteAcc, NoLock, Preserve)
+	{
+		FANP,	1, /* CPU/case fan power */
+		Offset (0x01),
+		PLED,	1,
+	}
+
+	Method (\_PTS, 1, NotSerialized)
+	{
+		/* Disable fan, blink power led */
+		Store (Zero, FANP)
+		Store (Zero, PLED)
+	}
+
+	Method (\_WAK, 1, NotSerialized)
+	{
+		/* Re-enable fan, stop power led blinking */
+		Store (One, FANP)
+		Store (One, PLED)
+		/* wake OK */
+		Return(Package(0x02){0x00, 0x00})
+	}
+
 	/* Root of the bus hierarchy */
 	Scope (\_SB)
 	{
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index 9b037fe..3b56796 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -1,6 +1,7 @@
 config SOUTHBRIDGE_INTEL_I82371EB
 	bool
 	select TINY_BOOTBLOCK
+	select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES
 
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index 940a17d..9e2c3eb 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -26,6 +26,7 @@ driver-y +=  smbus.c
 driver-y +=  reset.c
 driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
 driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c
+driver-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c
 
 romstage-y += early_pm.c
 romstage-y += early_smbus.c
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index b1a51c6..65af02a 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -31,6 +31,11 @@
 #include "i82371eb.h"
 #include "smbus.h"
 
+#if CONFIG_HAVE_ACPI_RESUME == 1
+extern u8 acpi_slp_type;
+int acpi_get_sleep_type(void);
+#endif
+
 static void pwrmgt_enable(struct device *dev)
 {
 	struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
@@ -87,7 +92,13 @@ static void pwrmgt_enable(struct device *dev)
 	outw(0xffff,     DEFAULT_PMBASE + GLBSTS);
 	outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
 
-	/* set pmcntrl default */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+	/* this reads PMCNTRL, so we have to call it before writing the
+	 * default value */
+	acpi_slp_type = acpi_get_sleep_type();
+#endif
+
+	/* set PMCNTRL default */
 	outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL);
 }
 
diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c
new file mode 100644
index 0000000..f018ad9
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/wakeup.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include "i82371eb.h"
+
+int acpi_get_sleep_type(void);
+
+/*
+ * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
+ *
+ * 0: soft off/suspend to disk					S5
+ * 1: suspend to ram						S3
+ * 2: powered on suspend, context lost				S2
+ *    Note: 'context lost' means the CPU restarts at the reset
+ *          vector
+ * 3: powered on suspend, CPU context lost			S1
+ *    Note: Looks like 'CPU context lost' does _not_ mean the
+ *          CPU restarts at the reset vector. Most likely only
+ *          caches are lost, so both 0x3 and 0x4 map to acpi S1
+ * 4: powered on suspend, context maintained			S1
+ * 5: working (clock control)					S0
+ * 6: reserved
+ * 7: reserved
+ */
+static const u8 acpi_sus_to_slp_typ[8] = {
+	5, 3, 2, 1, 1, 0, 0, 0
+};
+
+int acpi_get_sleep_type(void)
+{
+	u16 reg, result;
+
+	reg = inw(DEFAULT_PMBASE + PMCNTRL);
+	result = acpi_sus_to_slp_typ[(reg >> 10) & 7];
+
+	printk(BIOS_DEBUG, "Wakeup from ACPI sleep type S%d (PMCNTRL=%04x)\n", result, reg);
+
+	return result;
+}



From gerrit at coreboot.org  Sun Sep  4 20:45:12 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sun, 4 Sep 2011 20:45:12 +0200
Subject: [coreboot] New patch to review: aa0e057 Use ACPI table area to
	store cbmem_toc pointer needed for resume
References: <I9a0eca24d595b9d01d1ba7c81cc7fa0f05ae9229+0@gerrit.coreboot.org>
Message-ID: <I9a0eca24d595b9d01d1ba7c81cc7fa0f05ae9229+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/189

-gerrit

commit aa0e057d044217988052c580cc3c156e05296d48
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Mon Dec 13 22:42:48 2010 +0100

    Use ACPI table area to store cbmem_toc pointer needed for resume
    
    This adds a cbmem_toc_ptr_t structure, which is written just below the FADT,
    so we can find it using the FADP information.  The actual writing is only
    implemented for the Intel 82371EB southbridge.
    
    Also adds code to acpi.c resume codepath to use this pointer when the chipset
    has not overridden the weak get_cbmem_toc() function.
    
    Effectively the latter part affects all boards that already implement ACPI S2
    or S3 resume, but shouldn't change behaviour since none of them generate the
    structure:
    
    asus/m2v
    asus/m4a785-m
    asus/m2v-mx_se
    gigabyte/ma78gm
    gigabyte/ma785gmt
    jetway/pa78vm5
    iwill/dk8_htx
    asrock/939a785gmh
    amd/dbm690t
    amd/mahogany
    amd/tilapia_fam10
    amd/pistachio
    amd/serengeti_cheetah_fam10
    amd/serengeti_cheetah
    amd/mahogany_fam10
    kontron/kt690
    iei/kino-780am2-fam10
    technexion/tim5690
    technexion/tim8690
    
    Change-Id: I9a0eca24d595b9d01d1ba7c81cc7fa0f05ae9229
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/acpi.c                     |   12 ++++++++++++
 src/include/cbmem.h                          |    7 +++++++
 src/lib/cbmem.c                              |    5 ++++-
 src/southbridge/intel/i82371eb/acpi_tables.c |   14 ++++++++++++--
 4 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index f1be034..8baeaa4 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -517,6 +517,7 @@ void *acpi_find_wakeup_vector(void)
 	acpi_rsdt_t *rsdt;
 	acpi_facs_t *facs;
 	acpi_fadt_t *fadt;
+	cbmem_toc_ptr_t *cbmem_tocp;
 	void *wake_vec;
 	int i;
 
@@ -537,11 +538,22 @@ void *acpi_find_wakeup_vector(void)
 		return NULL;
 
 	printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp);
+	cbmem_tocp = (cbmem_toc_ptr_t *)(rsdp->rsdt_address - sizeof(cbmem_toc_ptr_t));
 	rsdt = (acpi_rsdt_t *) rsdp->rsdt_address;
 
 	end = (char *)rsdt + rsdt->header.length;
 	printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end);
 
+	if (get_cbmem_toc() == 0) {
+		if (cbmem_tocp->sig != CBMEM_TOC_PTR_SIG) {
+			printk(BIOS_DEBUG, "cbmem toc pointer not found at %p (sig %08x sz %d)\n", cbmem_tocp, cbmem_tocp->sig, sizeof(cbmem_toc_ptr_t));
+			return NULL;
+		}
+		set_cbmem_toc(cbmem_tocp->ptr);
+	} else {
+		printk(BIOS_DEBUG, "cbmem toc is at %p\n", get_cbmem_toc());
+	}
+
 	for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) {
 		fadt = (acpi_fadt_t *)rsdt->entry[i];
 		if (strncmp((char *)fadt, "FACP", 4) == 0)
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 7c5ec07..6bafa1e 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -41,6 +41,13 @@ extern uint64_t high_tables_base, high_tables_size;
 #define CBMEM_ID_SMBIOS         0x534d4254
 #define CBMEM_ID_NONE		0x00000000
 
+#define CBMEM_TOC_PTR_SIG	0x43425443
+
+typedef struct cbmem_toc_ptr {
+	u32 sig;
+	void *ptr;
+} __attribute__((packed)) cbmem_toc_ptr_t;
+
 void cbmem_initialize(void);
 
 void cbmem_init(u64 baseaddr, u64 size);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 202f521..516f557 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -39,6 +39,9 @@ struct cbmem_entry {
 #ifndef __PRE_RAM__
 static struct cbmem_entry *bss_cbmem_toc;
 
+/* chipset can override get/set_cbmem_toc to store the cbmem_toc address
+ * in nvram if available */
+
 struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
 {
 	return bss_cbmem_toc;
@@ -46,7 +49,7 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
 
 void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x)
 {
-	/* do nothing, this should be called by chipset to save TOC in NVRAM */
+	bss_cbmem_toc = x;
 }
 #else
 
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 2173a3d..1291c2d 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -26,6 +26,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
+#include <cbmem.h>
 #include "i82371eb.h"
 
 extern const unsigned char AmlCode[];
@@ -104,6 +105,7 @@ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(unsigned long curre
 unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
+	cbmem_toc_ptr_t *cbmem_tocp;
 	acpi_rsdp_t *rsdp;
 	acpi_rsdt_t *rsdt;
 	acpi_fadt_t *fadt;
@@ -113,20 +115,28 @@ unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start)
 	acpi_header_t *dsdt;
 
 	/* Align ACPI tables to 16 byte. */
-	start = (start + 0x0f) & -0x10;
-	current = start;
+	current = ALIGN(start, 16);
 
 	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT table. */
 	rsdp = (acpi_rsdp_t *) current;
 	current += sizeof(acpi_rsdp_t);
+
+	/* put cbmem toc ptr structure directly below rsdt */
+	printk(BIOS_INFO, "ACPI: Writing cbmem_toc pointer at %lx...\n", current);
+	cbmem_tocp = (cbmem_toc_ptr_t *) current;
+	current += sizeof(cbmem_toc_ptr_t);
+
 	rsdt = (acpi_rsdt_t *) current;
 	current += sizeof(acpi_rsdt_t);
 
 	/* Clear all table memory. */
 	memset((void *) start, 0, current - start);
 
+	cbmem_tocp->sig = CBMEM_TOC_PTR_SIG;
+	cbmem_tocp->ptr = get_cbmem_toc();
+
 	acpi_write_rsdp(rsdp, rsdt, NULL);
 	acpi_write_rsdt(rsdt);
 



From patrick at georgi-clan.de  Sun Sep  4 20:59:33 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 04 Sep 2011 20:59:33 +0200
Subject: [coreboot] FILO managed by Gerrit and Jenkins now,
	also coreboot patchwork status
Message-ID: <4E63CA95.1070904@georgi-clan.de>

Hi,

just a small heads-up (well, two):

FILO is now managed by Gerrit, using Jenkins for build-testing it. It 
uses the latest libpayload of coreboot to validate that things work.

I also cleaned out coreboot's patchwork instance some more - we now have 
less than 200 "unhandled" patches there, some of which might have been 
committed with small changes (so the automatic tool didn't pick it up), 
or exist several times with small variations (patch iterations on the 
list). These are marked "Accepted" or "Superseded" as appropriate.

I started moving other patches (really unhandled patches, that weren't 
noticed back then) to Gerrit, using the original author + date for the 
git commits (using the original author has the benefit that they're 
spammed by Gerrit about the patch status).
Afterwards I marked them "accepted" in patchwork (since they're properly 
tracked now).

I'd appreciate help with eliminating the backlog.


Patrick



From gerrit at coreboot.org  Sun Sep  4 21:31:28 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sun, 4 Sep 2011 21:31:28 +0200
Subject: [coreboot] Patch set updated: d40a6ca Use ACPI table area to store
	cbmem_toc pointer needed for resume
References: <I9a0eca24d595b9d01d1ba7c81cc7fa0f05ae9229+0@gerrit.coreboot.org>
Message-ID: <I9a0eca24d595b9d01d1ba7c81cc7fa0f05ae9229+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/189

-gerrit

commit d40a6caa2a5ab1df3bdb3f5a12f848289afd063d
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Mon Dec 13 22:42:48 2010 +0100

    Use ACPI table area to store cbmem_toc pointer needed for resume
    
    This adds a cbmem_toc_ptr_t structure, which is written just below the FADT,
    so we can find it using the FADP information.  The actual writing is only
    implemented for the Intel 82371EB southbridge.
    
    Also adds code to acpi.c resume codepath to use this pointer when the chipset
    has not overridden the weak get_cbmem_toc() function.
    
    Effectively the latter part affects all boards that already implement ACPI S2
    or S3 resume, but shouldn't change behaviour since none of them generate the
    structure:
    
    asus/m2v
    asus/m4a785-m
    asus/m2v-mx_se
    gigabyte/ma78gm
    gigabyte/ma785gmt
    jetway/pa78vm5
    iwill/dk8_htx
    asrock/939a785gmh
    amd/dbm690t
    amd/mahogany
    amd/tilapia_fam10
    amd/pistachio
    amd/serengeti_cheetah_fam10
    amd/serengeti_cheetah
    amd/mahogany_fam10
    kontron/kt690
    iei/kino-780am2-fam10
    technexion/tim5690
    technexion/tim8690
    
    Change-Id: I9a0eca24d595b9d01d1ba7c81cc7fa0f05ae9229
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/acpi.c                     |   12 ++++++++++++
 src/include/cbmem.h                          |    7 +++++++
 src/lib/cbmem.c                              |    5 ++++-
 src/southbridge/intel/i82371eb/acpi_tables.c |   14 ++++++++++++--
 4 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index f1be034..abafb04 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -517,6 +517,7 @@ void *acpi_find_wakeup_vector(void)
 	acpi_rsdt_t *rsdt;
 	acpi_facs_t *facs;
 	acpi_fadt_t *fadt;
+	cbmem_toc_ptr_t *cbmem_tocp;
 	void *wake_vec;
 	int i;
 
@@ -537,11 +538,22 @@ void *acpi_find_wakeup_vector(void)
 		return NULL;
 
 	printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp);
+	cbmem_tocp = (cbmem_toc_ptr_t *)(rsdp->rsdt_address - sizeof(cbmem_toc_ptr_t));
 	rsdt = (acpi_rsdt_t *) rsdp->rsdt_address;
 
 	end = (char *)rsdt + rsdt->header.length;
 	printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end);
 
+	if (get_cbmem_toc() == 0) {
+		if (cbmem_tocp->sig != CBMEM_TOC_PTR_SIG) {
+			printk(BIOS_DEBUG, "cbmem toc pointer not found at %p (sig %08x sz %lu)\n", cbmem_tocp, cbmem_tocp->sig, sizeof(cbmem_toc_ptr_t));
+			return NULL;
+		}
+		set_cbmem_toc(cbmem_tocp->ptr);
+	} else {
+		printk(BIOS_DEBUG, "cbmem toc is at %p\n", get_cbmem_toc());
+	}
+
 	for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) {
 		fadt = (acpi_fadt_t *)rsdt->entry[i];
 		if (strncmp((char *)fadt, "FACP", 4) == 0)
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 7c5ec07..6bafa1e 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -41,6 +41,13 @@ extern uint64_t high_tables_base, high_tables_size;
 #define CBMEM_ID_SMBIOS         0x534d4254
 #define CBMEM_ID_NONE		0x00000000
 
+#define CBMEM_TOC_PTR_SIG	0x43425443
+
+typedef struct cbmem_toc_ptr {
+	u32 sig;
+	void *ptr;
+} __attribute__((packed)) cbmem_toc_ptr_t;
+
 void cbmem_initialize(void);
 
 void cbmem_init(u64 baseaddr, u64 size);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 202f521..516f557 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -39,6 +39,9 @@ struct cbmem_entry {
 #ifndef __PRE_RAM__
 static struct cbmem_entry *bss_cbmem_toc;
 
+/* chipset can override get/set_cbmem_toc to store the cbmem_toc address
+ * in nvram if available */
+
 struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
 {
 	return bss_cbmem_toc;
@@ -46,7 +49,7 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
 
 void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x)
 {
-	/* do nothing, this should be called by chipset to save TOC in NVRAM */
+	bss_cbmem_toc = x;
 }
 #else
 
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 2173a3d..1291c2d 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -26,6 +26,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
+#include <cbmem.h>
 #include "i82371eb.h"
 
 extern const unsigned char AmlCode[];
@@ -104,6 +105,7 @@ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(unsigned long curre
 unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
+	cbmem_toc_ptr_t *cbmem_tocp;
 	acpi_rsdp_t *rsdp;
 	acpi_rsdt_t *rsdt;
 	acpi_fadt_t *fadt;
@@ -113,20 +115,28 @@ unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start)
 	acpi_header_t *dsdt;
 
 	/* Align ACPI tables to 16 byte. */
-	start = (start + 0x0f) & -0x10;
-	current = start;
+	current = ALIGN(start, 16);
 
 	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT table. */
 	rsdp = (acpi_rsdp_t *) current;
 	current += sizeof(acpi_rsdp_t);
+
+	/* put cbmem toc ptr structure directly below rsdt */
+	printk(BIOS_INFO, "ACPI: Writing cbmem_toc pointer at %lx...\n", current);
+	cbmem_tocp = (cbmem_toc_ptr_t *) current;
+	current += sizeof(cbmem_toc_ptr_t);
+
 	rsdt = (acpi_rsdt_t *) current;
 	current += sizeof(acpi_rsdt_t);
 
 	/* Clear all table memory. */
 	memset((void *) start, 0, current - start);
 
+	cbmem_tocp->sig = CBMEM_TOC_PTR_SIG;
+	cbmem_tocp->ptr = get_cbmem_toc();
+
 	acpi_write_rsdp(rsdp, rsdt, NULL);
 	acpi_write_rsdt(rsdt);
 



From corey.osgood at gmail.com  Sun Sep  4 23:15:47 2011
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sun, 4 Sep 2011 17:15:47 -0400
Subject: [coreboot] question
In-Reply-To: <CAL4qxhg3tVAwYmWNP7qGW5rGik4QpwjUL6axqZ0aGktW3HHZ=A@mail.gmail.com>
References: <CAL4qxhg3tVAwYmWNP7qGW5rGik4QpwjUL6axqZ0aGktW3HHZ=A@mail.gmail.com>
Message-ID: <CAD7TghLMoh6XYykMune8jnaR-beopCmz+0O5hiaejbeUG=DyNw@mail.gmail.com>

On Sun, Sep 4, 2011 at 10:58 AM, Lyubomir Minchev <ljbomir at gmail.com> wrote:

> Hi All,
>
> I have Laptop HP Pavilion dv4 with Chipset Intel 82801 I (ICH9)
>
> Shall it be compatible with coreboot ?
>
>
The simple answer is no, at this time your chipset is not supported.

-Corey
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From gerrit at coreboot.org  Mon Sep  5 13:35:56 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 5 Sep 2011 13:35:56 +0200
Subject: [coreboot] Patch merged into master: f916d99 Update defconfig to
	silence build
References: <Iecc5fef8df78e66bb80b00d786aa4925f13c823a+0@gerrit.coreboot.org>
Message-ID: <E1R0XT2-0005c0-Pm@ra.coresystems.de>

the following patch was just integrated into master:
commit f916d994f716444edc72ec8af0c9020e16f486ea
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jul 19 16:35:34 2011 +0200

    Update defconfig to silence build
    
    Change-Id: Iecc5fef8df78e66bb80b00d786aa4925f13c823a
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/117 for details.

-gerrit



From gerrit at coreboot.org  Mon Sep  5 13:36:03 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 5 Sep 2011 13:36:03 +0200
Subject: [coreboot] Patch merged into master: b431050 Remove useless
	print_a_completion() stub
References: <I841d9baecbaf298114e508feec89f1b2ea864bb9+0@gerrit.coreboot.org>
Message-ID: <E1R0XT9-0005eb-1w@ra.coresystems.de>

the following patch was just integrated into master:
commit b4310501fa616a4e5267b57adcb06fbc226a5a14
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jul 19 16:37:13 2011 +0200

    Remove useless print_a_completion() stub
    
    There's a real implementation elsewhere and this one only confuses
    things.
    
    Change-Id: I841d9baecbaf298114e508feec89f1b2ea864bb9
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/118 for details.

-gerrit



From gerrit at coreboot.org  Mon Sep  5 13:36:11 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 5 Sep 2011 13:36:11 +0200
Subject: [coreboot] Patch merged into master: 7f65f07 Add POSIXy
	readdir/scandir support
References: <Iadc1daed3cab4cf2ead778c23ad756d36cbbb99a+0@gerrit.coreboot.org>
Message-ID: <E1R0XTH-0005jb-Cq@ra.coresystems.de>

the following patch was just integrated into master:
commit 7f65f079c80bf52ff9e2f12b3c118ad3dcb5647b
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jul 19 16:38:23 2011 +0200

    Add POSIXy readdir/scandir support
    
    This abuses the print_a_completion mechanism to build the right data
    structures to support opendir/readdir/closedir and scandir on top of
    them.
    
    It's BSD-licensed so it can eventually be moved over to libpayload.
    
    Change-Id: Iadc1daed3cab4cf2ead778c23ad756d36cbbb99a
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/119 for details.

-gerrit



From gerrit at coreboot.org  Mon Sep  5 13:40:12 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:12 +0200
Subject: [coreboot] New patch to review: e6e5a03 More compatible use of
	mktemp
References: <I961a7ddcd39657c9463806d7b82757eff0a4ac57+0@gerrit.coreboot.org>
Message-ID: <I961a7ddcd39657c9463806d7b82757eff0a4ac57+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/190

-gerrit

commit e6e5a03bca182471fa00d937c3235ac00ef0234e
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Sep 1 09:16:37 2011 +0200

    More compatible use of mktemp
    
    Change-Id: I961a7ddcd39657c9463806d7b82757eff0a4ac57
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 util/xcompile/xcompile |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 5e9ce83..7c1adf3 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -35,7 +35,7 @@ for make in make gmake gnumake; do
 done
 
 GCCPREFIX=invalid
-TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz`
+TMPFILE=`mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.78gOIUGz`
 touch $TMPFILE
 
 # This should be a loop over all supported architectures



From gerrit at coreboot.org  Mon Sep  5 13:40:13 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:13 +0200
Subject: [coreboot] New patch to review: a7ae3fb Wait longer on ATAPI devices
References: <I347617c97bd02920e49b3cc45aa6c6b37573e0ff+0@gerrit.coreboot.org>
Message-ID: <I347617c97bd02920e49b3cc45aa6c6b37573e0ff+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/191

-gerrit

commit a7ae3fb9d6257f80036b0db090fbe021d04494b4
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Mar 8 12:43:29 2011 +0100

    Wait longer on ATAPI devices
    
    Some devices require more time for themselves to get up and running.
    
    Change-Id: I347617c97bd02920e49b3cc45aa6c6b37573e0ff
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 drivers/ide_new.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/ide_new.c b/drivers/ide_new.c
index 4f612be..ddcc027 100644
--- a/drivers/ide_new.c
+++ b/drivers/ide_new.c
@@ -633,7 +633,7 @@ ob_ide_atapi_drive_ready(struct ide_drive *drive)
 		if (!ob_ide_atapi_packet(drive,cmd)) break;
 
 		/* Give the drive some time to breathe */
-		mdelay(500);
+		mdelay(5000);
 	}
 
 	memset(cmd, 0, sizeof(*cmd));



From gerrit at coreboot.org  Mon Sep  5 13:40:13 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:13 +0200
Subject: [coreboot] New patch to review: a8b71bd Unlock ATAPI devices on boot
References: <I4f2a0ddafac2debe0a1564904f37025850cc519e+0@gerrit.coreboot.org>
Message-ID: <I4f2a0ddafac2debe0a1564904f37025850cc519e+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/192

-gerrit

commit a8b71bd56bf205fd2add685ba8e0f0412a123080
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Aug 24 11:07:21 2010 +0200

    Unlock ATAPI devices on boot
    
    This makes CD/DVD drives accessible that were locked prior to a
    reboot.
    
    Change-Id: I4f2a0ddafac2debe0a1564904f37025850cc519e
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 drivers/ide_new.c |   13 +++++++++++++
 drivers/ide_new.h |    1 +
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/drivers/ide_new.c b/drivers/ide_new.c
index ddcc027..a2870b8 100644
--- a/drivers/ide_new.c
+++ b/drivers/ide_new.c
@@ -658,6 +658,19 @@ ob_ide_atapi_drive_ready(struct ide_drive *drive)
 		return 1;
 	}
 
+	/* clear Persistent Prevent State */
+	memset (cmd, 0, sizeof(*cmd));
+	cmd->cdb[0] = ATAPI_PREVENT_ALLOW_MEDIUM_REMOVAL;
+	cmd->cdb[2] = 2;
+	if (ob_ide_atapi_packet(drive, cmd))
+		printf("could not persistently unlock device\n");
+
+	/* clear Prevent State */
+	memset (cmd, 0, sizeof(*cmd));
+	cmd->cdb[0] = ATAPI_PREVENT_ALLOW_MEDIUM_REMOVAL;
+	if (ob_ide_atapi_packet(drive, cmd))
+		printf("could not unlock device\n");
+
 	/*
 	 * finally, get capacity and block size
 	 */
diff --git a/drivers/ide_new.h b/drivers/ide_new.h
index 8d3979a..f667e41 100644
--- a/drivers/ide_new.h
+++ b/drivers/ide_new.h
@@ -70,6 +70,7 @@
 #define ATAPI_READ_10		0x28
 #define ATAPI_REQ_SENSE		0x03
 #define ATAPI_START_STOP_UNIT	0x1b
+#define ATAPI_PREVENT_ALLOW_MEDIUM_REMOVAL  0x1e
 #define ATAPI_READ_CAPACITY	0x25
 
 /*



From gerrit at coreboot.org  Mon Sep  5 13:40:14 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:14 +0200
Subject: [coreboot] New patch to review: 0ca6ae9 Show which file cannot be
	openend in file_open(), eases debuging.
References: <I06fd3576aa3443588e67234bce748f533c36a8ff+0@gerrit.coreboot.org>
Message-ID: <I06fd3576aa3443588e67234bce748f533c36a8ff+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/193

-gerrit

commit 0ca6ae94bb6be913aef972b93e8e1a05f98cdfad
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Thu Jun 3 15:39:46 2010 +0200

    Show which file cannot be openend in file_open(), eases debuging.
    
    Change-Id: I06fd3576aa3443588e67234bce748f533c36a8ff
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 fs/vfs.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/fs/vfs.c b/fs/vfs.c
index 18dbcbc..18db6ec 100644
--- a/fs/vfs.c
+++ b/fs/vfs.c
@@ -191,7 +191,7 @@ int file_open(const char *filename)
 	filepos = 0;
 	errnum = 0;
 	if (!fsys->dir_func((char *) path)) {
-		printf("File not found.\n");
+		printf("File not found '%s'.\n", filename);
 		goto out;
 	}
 	retval = 1;



From gerrit at coreboot.org  Mon Sep  5 13:40:14 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:14 +0200
Subject: [coreboot] New patch to review: 207611a Make 'configfile' and
	'root' commands be available from scripting mode.
References: <I042506e236b0fb7f10e20ea3f0f3764414167dce+0@gerrit.coreboot.org>
Message-ID: <I042506e236b0fb7f10e20ea3f0f3764414167dce+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/194

-gerrit

commit 207611a5910a4604c730658e5b919e93271b1ebc
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 11:46:29 2010 +0100

    Make 'configfile' and 'root' commands be available from scripting mode.
    
    When a 'configfile' command is encountered, restart with that new config
    file.
    
    Change-Id: I042506e236b0fb7f10e20ea3f0f3764414167dce
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 main/grub/builtins.c |    9 +++++++--
 main/grub/grub.c     |   16 +++++++++++++++-
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/main/grub/builtins.c b/main/grub/builtins.c
index b09076a..79d237e 100644
--- a/main/grub/builtins.c
+++ b/main/grub/builtins.c
@@ -49,6 +49,9 @@ unsigned long install_partition = 0x20000;
 unsigned long boot_drive = 0;
 char config_file[128] = "\0";
 
+/* indicator if we encountered a 'configfile' command and have to restart */
+int reload_configfile = 0;
+
 kernel_t kernel_type;
 
 /* The fallback entry.  */
@@ -91,6 +94,7 @@ void init_config(void)
 	fallback_entryno = -1;
 	fallback_entries[0] = -1;
 	grub_timeout = -1;
+	reload_configfile = 0;
 }
 
 int check_password(char *entered, char *expected, password_t type)
@@ -318,6 +322,7 @@ static int configfile_func(char *arg, int flags)
 	/* Force to load the configuration file.  */
 	is_opened = 0;
 	keep_cmdline_running = 0;
+	reload_configfile = 1;
 
 	/* Make sure that the user will not be authoritative.  */
 	auth = 0;
@@ -328,7 +333,7 @@ static int configfile_func(char *arg, int flags)
 static struct builtin builtin_configfile = {
 	"configfile",
 	configfile_func,
-	BUILTIN_CMDLINE | BUILTIN_HELP_LIST,
+	BUILTIN_CMDLINE | BUILTIN_MENU | BUILTIN_HELP_LIST,
 	"configfile FILE",
 	"Load FILE as the configuration file."
 };
@@ -1269,7 +1274,7 @@ static int root_func(char *arg, int flags)
 static struct builtin builtin_root = {
 	"root",
 	root_func,
-	BUILTIN_CMDLINE | BUILTIN_HELP_LIST,
+	BUILTIN_CMDLINE | BUILTIN_MENU | BUILTIN_HELP_LIST,
 	"root [DEVICE]",
 	"Set the current \"root device\" to the device DEVICE."
 };
diff --git a/main/grub/grub.c b/main/grub/grub.c
index 15f0ece..7881a98 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -28,6 +28,7 @@
 #include <arch/timer.h>
 
 extern char config_file[];
+extern int reload_configfile;
 
 char PASSWORD_BUF[PASSWORD_BUFLEN]; /* The buffer for the password.  */
 char DEFAULT_FILE_BUF[DEFAULT_FILE_BUFLEN]; /* THe buffer for the filename of "/boot/grub/default".  */
@@ -813,6 +814,11 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 			break;
 	}
 
+	/* return to reload the config file */
+	if (reload_configfile) {
+		return;
+	}
+
 	show_menu = 1;
 	goto restart;
 }
@@ -1004,9 +1010,12 @@ void grub_main(void)
 	/* Never return.  */
 	for (;;) {
 		char buf[10];	/* This is good enough.  */
-		char *default_file = (char *) DEFAULT_FILE_BUF;
+		char *default_file;
 		int i;
 
+restart:
+		default_file = (char *) DEFAULT_FILE_BUF;
+
 		reset();
 
 		/* Here load the configuration file.  */
@@ -1124,6 +1133,11 @@ void grub_main(void)
 								    cmdline);
 						(builtin->func) (arg, BUILTIN_MENU);
 						errnum = 0;
+
+						/* if the command was configfile, restart */
+						if (reload_configfile) {
+							goto restart;
+						}
 					} else
 						/* Ignored.  */
 						continue;



From gerrit at coreboot.org  Mon Sep  5 13:40:15 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:15 +0200
Subject: [coreboot] New patch to review: baef0d7 Add non-interactive mode
	for FILO
References: <I8c13d64832b6f8659927ec1e5fe3b527ef8cbdc4+0@gerrit.coreboot.org>
Message-ID: <I8c13d64832b6f8659927ec1e5fe3b527ef8cbdc4+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/195

-gerrit

commit baef0d7d5f7aa45289c113de918584ebdf3b8735
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 13:14:24 2010 +0100

    Add non-interactive mode for FILO
    
    It forbids modifications of the configuration loaded and prevents
    entering the command line mode.
    
    Change-Id: I8c13d64832b6f8659927ec1e5fe3b527ef8cbdc4
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 Config.in           |    7 +++++++
 main/filo.c         |   17 +++++++++++++++++
 main/grub/cmdline.c |    4 ++++
 main/grub/grub.c    |   40 +++++++++++++++++++++++++++++++++++++++-
 4 files changed, 67 insertions(+), 1 deletions(-)

diff --git a/Config.in b/Config.in
index 8981a48..b1da531 100644
--- a/Config.in
+++ b/Config.in
@@ -17,6 +17,13 @@ config USE_GRUB
 	help
 	  Use GRUB legacy like interface instead of autoboot?
 
+config NON_INTERACTIVE
+	bool "non-interactive interface"
+	default n
+	help
+	  Build a non-interactive interface to disallow modifications of
+	  the boot options, e.g. the kernel to load or the command line.
+
 config PROMPT
 	string "Command line prompt"
 	default "filo"
diff --git a/main/filo.c b/main/filo.c
index a8bf372..e37559b 100644
--- a/main/filo.c
+++ b/main/filo.c
@@ -156,6 +156,10 @@ int main(void)
 
 #ifdef CONFIG_AUTOBOOT_FILE
 #ifdef CONFIG_AUTOBOOT_DELAY
+#ifdef CONFIG_NON_INTERACTIVE
+#error "autoboot delay is not supported for non-interactive builds"
+#define autoboot_delay() 0 /* success */
+#else
 static inline int autoboot_delay(void)
 {
     u64 timeout;
@@ -189,13 +193,16 @@ static inline int autoboot_delay(void)
 	    return 0; /* default accepted */
     }
 }
+#endif /* CONFIG_NON_INTERACTIVE */
 #endif /* CONFIG_AUTOBOOT_DELAY */
 
 static void autoboot(void)
 {
+#ifndef CONFIG_NON_INTERACTIVE
     /* If Escape key is pressed already, skip autoboot */
     if (havechar() && getchar()==ESCAPE)
 	return;
+#endif /* CONFIG_NON_INTERACTIVE */
 
     if (autoboot_delay()==0) {
 	printf("boot: %s\n", CONFIG_AUTOBOOT_FILE);
@@ -215,6 +222,7 @@ int main(void)
     /* Try default image */
     autoboot();
 
+#ifndef CONFIG_NON_INTERACTIVE
     /* The above didn't work, ask user */
     while (havechar())
 	getchar();
@@ -233,6 +241,15 @@ int main(void)
 	if (line[0])
 	    boot(line);
     }
+#else /* ! CONFIG_NON_INTERACTIVE */
+    for (;;) {
+	printf("\nAutoboot failed! Press any key to reboot.\n");
+	getchar();
+	if (reset_handler) {
+	    reset_handler();
+	}
+    }
+#endif /* CONFIG_NON_INTERACTIVE */
 
     return 0;
 }
diff --git a/main/grub/cmdline.c b/main/grub/cmdline.c
index 1f56ac6..2ace871 100644
--- a/main/grub/cmdline.c
+++ b/main/grub/cmdline.c
@@ -40,6 +40,7 @@ char *skip_to(int after_equal, char *cmdline)
 	return cmdline;
 }
 
+#ifndef CONFIG_NON_INTERACTIVE
 /* Print a helpful message for the command-line interface.  */
 void print_cmdline_message(int type)
 {
@@ -67,6 +68,7 @@ void print_cmdline_message(int type)
 	grub_printf("\n");
 #endif
 }
+#endif /* CONFIG_NON_INTERACTIVE */
 
 /* Find the builtin whose command name is COMMAND and return the
  * pointer. If not found, return 0.
@@ -118,6 +120,7 @@ static void init_cmdline(void)
 	init_builtins();
 }
 
+#ifndef CONFIG_NON_INTERACTIVE
 /* Enter the command-line interface. HEAP is used for the command-line
  * buffer. Return only if FOREVER is nonzero and get_cmdline returns
  * nonzero (ESC is pushed).
@@ -179,6 +182,7 @@ void enter_cmdline(char *heap, int forever)
 		count_lines = -1;
 	}
 }
+#endif /* CONFIG_NON_INTERACTIVE */
 
 /* Run an entry from the script SCRIPT. HEAP is used for the
    command-line buffer. If an error occurs, return non-zero, otherwise
diff --git a/main/grub/grub.c b/main/grub/grub.c
index 7881a98..b1fcdd1 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -191,6 +191,16 @@ old:
 
 }
 
+static void reboot(void) {
+	for (;;) {
+		grub_printf("Press any key to reboot.\n");
+		getchar();
+		if (reset_handler) {
+			reset_handler();
+		}
+	}
+}
+
 /* Define if there is user specified preset menu string */
 /* #undef PRESET_MENU_STRING */
 
@@ -409,16 +419,27 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
       password to unlock the next set of features.");
 		} else {
 			if (config_entries)
+#ifndef CONFIG_NON_INTERACTIVE
 				grub_printf("\
       Press enter to boot the selected OS, \'e\' to edit the\n\
       commands before booting, \'a\' to modify the kernel arguments\n\
       before booting, or \'c\' for a command-line.");
+#else /* ! CONFIG_NON_INTERACTIVE */
+				grub_printf("\
+      Press enter to boot the selected OS, \'e\' to see the\n\
+      commands before booting.");
+#endif /* CONFIG_NON_INTERACTIVE */
 			else
+#ifndef CONFIG_NON_INTERACTIVE
 				grub_printf("\
       Press \'b\' to boot, \'e\' to edit the selected command in the\n\
       boot sequence, \'c\' for a command-line, \'o\' to open a new line\n\
       after (\'O\' for before) the selected line, \'d\' to remove the\n\
       selected line, or escape to go back to the main menu.");
+#else /* ! CONFIG_NON_INTERACTIVE */
+				grub_printf("\
+      Press \'b\' to boot or escape to go back to the main menu.");
+#endif /* CONFIG_NON_INTERACTIVE */
 		}
 
 		print_entries(3, 12, first_entry, entryno, menu_entries);
@@ -520,6 +541,7 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 				if ((c == '\n') || (c == '\r') || (c == 6))
 					break;
 			} else {
+#ifndef CONFIG_NON_INTERACTIVE
 				if ((c == 'd') || (c == 'o') || (c == 'O')) {
 					print_entry(4 + entryno, 0,
 						    get_entry(menu_entries, first_entry + entryno, 0));
@@ -565,6 +587,7 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 
 					print_entries(3, 12, first_entry, entryno, menu_entries);
 				}
+#endif /* CONFIG_NON_INTERACTIVE */
 
 				cur_entry = menu_entries;
 				if (c == 27)
@@ -645,6 +668,7 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 
 					if (config_entries)
 						run_menu(heap, NULL, new_num_entries, new_heap, 0);
+#ifndef CONFIG_NON_INTERACTIVE
 					else {
 						/* flush color map */
 						grub_printf(" ");
@@ -677,9 +701,11 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 							heap += (j - i);
 						}
 					}
+#endif /* CONFIG_NON_INTERACTIVE */
 
 					goto restart;
 				}
+#ifndef CONFIG_NON_INTERACTIVE
 				if (c == 'c') {
 					extern int keep_cmdline_running;
 					enter_cmdline(heap, 0);
@@ -778,6 +804,7 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 
 					break;
 				}
+#endif /* CONFIG_NON_INTERACTIVE */
 			}
 		}
 	}
@@ -1077,7 +1104,11 @@ restart:
 			}
 
 			if (!is_opened) {
-				grub_printf("Could not open menu.lst file '%s'. Entering command line.\n", config_file);
+#ifndef CONFIG_NON_INTERACTIVE
+				grub_printf("Could not open configuration file '%s'. Entering command line.\n", config_file);
+#else /* ! CONFIG_NON_INTERACTIVE */
+				grub_printf("Could not open configuration file '%s'.\n", config_file);
+#endif /* CONFIG_NON_INTERACTIVE */
 				// memset(myheap, 0, 256);
 				// run_script("terminal console\n\0", myheap);
 				break;
@@ -1205,10 +1236,17 @@ restart:
 		} while (is_preset);
 
 		if (!num_entries) {
+#ifndef CONFIG_NON_INTERACTIVE
 			/* If no acceptable config file, goto command-line, starting
 			   heap from where the config entries would have been stored
 			   if there were any.  */
 			enter_cmdline(config_entries, 1);
+#else /* ! CONFIG_NON_INTERACTIVE */
+			for (;;) {
+			    grub_printf("\nNo menu entries found. Giving up.\n");
+			    reboot();
+			}
+#endif /* CONFIG_NON_INTERACTIVE */
 		} else {
 			/* Run menu interface.  */
 			run_menu(menu_entries, config_entries, num_entries, menu_entries + menu_len, default_entry);



From gerrit at coreboot.org  Mon Sep  5 13:40:15 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:15 +0200
Subject: [coreboot] New patch to review: acf0475 Add nvram command
References: <Ib95ee0d4fa8dcaf002ffe2b18d4975e301d00a6a+0@gerrit.coreboot.org>
Message-ID: <Ib95ee0d4fa8dcaf002ffe2b18d4975e301d00a6a+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/196

-gerrit

commit acf04759bf35be686f264011154f562df813a228
Author: Stefan Reinauer <stefan.reinauer at coresystems.de>
Date:   Fri Jun 4 09:25:50 2010 +0200

    Add nvram command
    
    Change-Id: Ib95ee0d4fa8dcaf002ffe2b18d4975e301d00a6a
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 main/grub/builtins.c |   67 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 67 insertions(+), 0 deletions(-)

diff --git a/main/grub/builtins.c b/main/grub/builtins.c
index 79d237e..df14cf1 100644
--- a/main/grub/builtins.c
+++ b/main/grub/builtins.c
@@ -1098,6 +1098,70 @@ static struct builtin builtin_md5crypt = {
 };
 #endif				/* CONFIG_USE_MD5_PASSWORDS */
 
+#if CONFIG_DEVELOPER_TOOLS
+/* nvram */
+static int nvram_func(char *arg, int flags)
+{
+#define RTC_BOOT_BYTE 48 // Hard coded in coreboot
+	u8 rtc_boot_byte;
+	// bit len  name
+	//  0   1   boot_option
+	//  1   1   last_boot
+	//  4   4   reboot_bits
+
+	rtc_boot_byte = nvram_read(RTC_BOOT_BYTE);
+
+	if (memcmp(arg, "normal", 6) == 0) {
+		rtc_boot_byte &= 0x03;	// drop reboot_bits
+		rtc_boot_byte |= 1;	// normal
+		nvram_write(rtc_boot_byte, RTC_BOOT_BYTE);
+		return 0;
+	}
+
+	if (memcmp(arg, "fallback", 8) == 0) {
+		rtc_boot_byte &= 0x03;	// drop reboot_bits
+		rtc_boot_byte &= ~1;	// fallback
+		nvram_write(rtc_boot_byte, RTC_BOOT_BYTE);
+		return 0;
+	}
+
+	// TODO not really default, but rather "null everything out and fix the
+	// checksum"
+	if (memcmp(arg, "default", 7) == 0) {
+		int i;
+		int range_start = lib_sysinfo.cmos_range_start / 8;
+		int range_end = lib_sysinfo.cmos_range_end / 8;
+		for (i= range_start; i<range_end; i++)
+			nvram_write(0, i);
+		fix_options_checksum();
+		return 0;
+	}
+
+
+	if (!strlen(arg)) {
+		grub_printf("NVRAM Settings:\n");
+		grub_printf("  boot option: %s\n", 
+			(rtc_boot_byte & (1 << 0)) ? "Normal" : "Fallback");
+		grub_printf("  last boot:   %s\n", 
+			(rtc_boot_byte & (1 << 1)) ? "Normal" : "Fallback");
+		grub_printf("  reboot_bits: %d\n", (rtc_boot_byte >> 4));
+		return 0;
+	}
+
+	errnum = ERR_BAD_ARGUMENT;
+	return 1;
+}
+
+static struct builtin builtin_nvram = {
+	"nvram",
+	nvram_func,
+	BUILTIN_MENU | BUILTIN_CMDLINE | BUILTIN_NO_ECHO,
+	"nvram [normal|fallback]",
+	"Change the coreboot nvram to boot the normal or fallback"
+	    "image on the next boot."
+};
+#endif
+
 /* password */
 static int password_func(char *arg, int flags)
 {
@@ -1786,6 +1850,9 @@ struct builtin *builtin_table[] = {
 #ifdef CONFIG_USE_MD5_PASSWORDS
 	&builtin_md5crypt,
 #endif
+#ifdef CONFIG_DEVELOPER_TOOLS
+	&builtin_nvram,
+#endif
 	&builtin_password,
 	&builtin_pause,
 	&builtin_poweroff,



From gerrit at coreboot.org  Mon Sep  5 13:40:15 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:15 +0200
Subject: [coreboot] New patch to review: 0966f88 Add multiboot header
References: <Ibe8e879a3a6f533f97aa8381697afb1f14d1f87d+0@gerrit.coreboot.org>
Message-ID: <Ibe8e879a3a6f533f97aa8381697afb1f14d1f87d+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/197

-gerrit

commit 0966f88267d3723b22d8a5c088cb7daeab21e953
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Jun 7 13:53:31 2011 +0200

    Add multiboot header
    
    Change-Id: Ibe8e879a3a6f533f97aa8381697afb1f14d1f87d
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 Config.in         |    7 +++++++
 i386/ldscript     |    2 +-
 main/Makefile.inc |    1 +
 main/mb_hdr.c     |   32 ++++++++++++++++++++++++++++++++
 4 files changed, 41 insertions(+), 1 deletions(-)

diff --git a/Config.in b/Config.in
index b1da531..251bd2a 100644
--- a/Config.in
+++ b/Config.in
@@ -9,6 +9,13 @@ config TARGET_I386
 	bool
 	default y
 
+config MULTIBOOT_IMAGE
+	bool "Include a MultiBoot header"
+	default y
+	help
+	  Including a MultiBoot header makes FILO chainloadable by MultiBoot
+	  compliant boot loaders like GRUB.
+
 menu "Interface Options"
 
 config USE_GRUB
diff --git a/i386/ldscript b/i386/ldscript
index 7fba856..b260c51 100644
--- a/i386/ldscript
+++ b/i386/ldscript
@@ -40,7 +40,7 @@ SECTIONS
     /* Start of the program. 
      * Now the version string is in the note, we must include it
      * in the program. Otherwise we lose the string after relocation. */
-    . = ALIGN(16);
+    . = ALIGN(4096);
     _start = .;
 
     /* Putting ELF notes near beginning of file might help bootloaders.
diff --git a/main/Makefile.inc b/main/Makefile.inc
index c7290cf..e2fab04 100644
--- a/main/Makefile.inc
+++ b/main/Makefile.inc
@@ -16,6 +16,7 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
+TARGETS-$(CONFIG_MULTIBOOT_IMAGE) += main/mb_hdr.o
 TARGETS-y += main/filo.o main/strtox.o
 TARGETS-y += main/elfload.o main/ipchecksum.o 
 TARGETS-$(CONFIG_SUPPORT_SOUND) += main/sound.o
diff --git a/main/mb_hdr.c b/main/mb_hdr.c
new file mode 100644
index 0000000..bb01427
--- /dev/null
+++ b/main/mb_hdr.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of FILO.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Support for MultiBoot */
+#define MB_HEADER_MAGIC		0x1BADB002
+#define MB_RQ_FLAGS_4K		1
+#define MB_REQUESTED_FLAGS	(MB_RQ_FLAGS_4K)
+
+/* this header is parsed by the boot loader that loads FILO, e.g. GRUB */
+struct mb_header {
+	long magic;		/* multiboot magic */
+	long features;	/* requested features */
+	long chksum;	/* chksum for whole structure */
+} mb_header __attribute__((section(".hdr.mb"))) = {
+	.magic = MB_HEADER_MAGIC,
+	.features = MB_REQUESTED_FLAGS,
+	.chksum = -(MB_HEADER_MAGIC + MB_REQUESTED_FLAGS),
+};



From gerrit at coreboot.org  Mon Sep  5 13:40:16 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:16 +0200
Subject: [coreboot] New patch to review: 8d17f66 Allow switching between
	partitions on the current device
References: <I271f5f407297c072f35ac8410c278b1c9442d654+0@gerrit.coreboot.org>
Message-ID: <I271f5f407297c072f35ac8410c278b1c9442d654+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/198

-gerrit

commit 8d17f66e7e581c765ba92b7bc6f9448877d0dff4
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Mar 24 09:13:54 2011 +0100

    Allow switching between partitions on the current device
    
    root (,1) or configfile 2:/filo.lst work now and change the
    active partition on the current device (as defined by "root").
    
    Change-Id: I271f5f407297c072f35ac8410c278b1c9442d654
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 include/grub/shared.h |    2 +-
 main/grub/builtins.c  |  184 +++++++++++++++++++++++++++----------------------
 main/grub/grub.c      |    5 +-
 3 files changed, 104 insertions(+), 87 deletions(-)

diff --git a/include/grub/shared.h b/include/grub/shared.h
index 127b74f..9e74d7c 100644
--- a/include/grub/shared.h
+++ b/include/grub/shared.h
@@ -304,6 +304,6 @@ int print_completions (int is_filename, int is_completion);
 int check_password(char *entered, char* expected, password_t type);
 
 /* FILO specific stuff */
-void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev);
+void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev, int append);
 
 #endif /* ! GRUB_SHARED_HEADER */
diff --git a/main/grub/builtins.c b/main/grub/builtins.c
index df14cf1..fc216eb 100644
--- a/main/grub/builtins.c
+++ b/main/grub/builtins.c
@@ -303,8 +303,7 @@ static int configfile_func(char *arg, int flags)
 	extern int is_opened, keep_cmdline_running;
 
 	/* Check if the file ARG is present.  */
-	temp_space[0]=0;
-	copy_path_to_filo_bootline(arg, temp_space, 1);
+	copy_path_to_filo_bootline(arg, temp_space, 1, 0);
 	if (temp_space[0]==0) {
 		return help_func("configfile",0);
 	}
@@ -316,8 +315,7 @@ static int configfile_func(char *arg, int flags)
 	file_close();
 
 	/* Copy ARG to CONFIG_FILE.  */
-	memset(config_file, 0, 128);
-	copy_path_to_filo_bootline(arg, config_file, 1);
+	copy_path_to_filo_bootline(arg, config_file, 1, 0);
 
 	/* Force to load the configuration file.  */
 	is_opened = 0;
@@ -632,114 +630,140 @@ static struct builtin builtin_hiddenmenu = {
 };
 
 /**
+ * @param arg         linux style driver specifier
+ * @param drivername  driver name (out)
+ * @param disk        disk number (out)
+ * @return length of parsed string
+ */
+static
+int parse_linux_style_driver(char *arg, char *drivername, int *disk)
+{
+	int i = 0;
+
+	*disk = -1;
+	drivername[0] = '\0';
+	while ((i < 16) && (isalpha(arg[i]))) {
+		drivername[i] = arg[i];
+		i++;
+	}
+
+	if (i > 0) {
+		drivername[--i] = '\0';
+		*disk = arg[i]-'a';
+		i++;
+	}
+	return i;
+}
+
+/**
  * @param arg  source pointer with grub device names
  * @param path destination pointer (will be filled with filo device names)
  * @param use_rootdev values other than zero mean the root device set by the "root"
  * command is taken into regard here. This has to be zero when calling from root_func.
  */
 
-void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev)
+void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev, int append)
 {
 	char devicename[16];
 	char drivername[16];
 	int disk, part;
+	unsigned long addr;
 	int i, len;
 
-
-	/* Clean up */
 	memset(devicename, 0, 16);
 	memset(drivername, 0, 16);
+	disk = -1;
+	part = -1;
+	addr = -1;
 
-	/* Copy over the driver name: "hd", "ud", "sd" ... */
 	if (arg[0] == '(') {
+		// grub style device specifier
 		i = 1;
 		/* Read until we encounter a number, a comma or a closing
 		 * bracket
 		 */
-		while ((i <= 16) && (arg[i]) && (!isdigit(arg[i])) && (arg[i] != ',')
-		       && (arg[i] != ')')) {
+		while ((i <= 16) && (isalpha(arg[i]))) {
 			drivername[i - 1] = arg[i];
 			i++;
 		}
-	}
 
-	disk = -1;
-	part = -1;
-
-	len = strlen(drivername);
-	if (len) {		/* We have a driver. No idea if it exists though */
-		// The driver should decide this:
-		len++;		// skip driver name + opening bracket
-
-		// XXX put @ handling in here, too for flash at addr and mem at addr
-
-		if (isdigit(arg[len])) {
-			disk = arg[len] - '0';
-			len++;
-			if (isdigit(arg[len])) {	/* More than 9 drives? */
-				/* ok, get one more number. No more than 99 drives */
-				disk *= 10;
-				disk += arg[len] - '0';
-				len++;
-			}
+		if (isdigit(arg[i])) {
+			char *postnum;
+			disk = strtoul(arg+i, &postnum, 10);
+			i = postnum - arg;
 		}
-		if (arg[len] == ',') {
-			len++;
-			part = arg[len] - '0';
-			len++;
-			if (isdigit(arg[len])) {	/* More than 9 partitions? */
-				/* ok, get one more number. No more than 99
-				 * partitions */
-				part *= 10;
-				part += arg[len] - '0';
-				len++;
-			}
+
+		if (arg[i] == ',') {
+			char *postnum;
+			part = strtoul(arg+i+1, &postnum, 10) + 1;
+			i = postnum - arg;
 		}
-		if (arg[len] != ')') {
-			grub_printf("Drive Error.\n");
-			// set len = 0 --> just copy the drive name 
-			len = 0;
-		} else {
-			len++;	// skip closing bracket
+
+		if (arg[i] == '@') {
+			char *postnum;
+			addr = strtoul(arg+i+1, &postnum, 0);
+			i = postnum - arg;
 		}
-	}
 
-	if (disk == -1) {
-		int cnt = 0;
-		len = 0;
-		while ((arg[cnt] != 0) && (arg[cnt+1] != 0)) {
-			if (arg[cnt] == ':' && arg[cnt+1] == '/') {
-				/* The user did specify a FILO name already */
-				len = cnt;
-				break;
-			}
-			cnt++;
+		if (arg[i] == ')') i++;
+
+		arg += i;
+	} else if ((use_rootdev == 0) || (strchr(arg, ':') != NULL)) {
+		// linux-style device specifier or
+		// leading device name required (assume it's linux-style then)
+		i = parse_linux_style_driver(arg, drivername, &disk);
+
+		if (isdigit(arg[i])) {
+			char *postnum;
+			part = strtoul(arg+i, &postnum, 10);
+			i = postnum - arg;
 		}
-	} else {
-		if (part == -1) {	// No partition
-			sprintf(devicename, "%s%c:", drivername, disk + 'a');
-		} else {	// both disk and partition
-			sprintf(devicename, "%s%c%d:", drivername, disk + 'a', part + 1);
+
+		if (arg[i] == '@') {
+			char *postnum;
+			addr = strtoul(arg+i+1, &postnum, 0);
+			i = postnum - arg;
 		}
-		strncat(path, devicename, BOOT_LINE_LENGTH);
-		arg += len;	// skip original drive name
+
+		if (arg[i] == ':') i++;
+		arg += i;
 	}
 
-	if (use_rootdev && !len) {	// No drive was explicitly specified
-		if (strlen(root_device)) {	// But someone set a root device
-			strncat(path, root_device, BOOT_LINE_LENGTH);
-		}
+	if ((disk == -1) && (part != -1) && (strlen(drivername) == 0)) {
+		// special case for partition-only identifiers:
+		// take driver and disk number from root_device
+		i = parse_linux_style_driver(root_device, drivername, &disk);
 	}
 
-	/* Copy the rest over */
-	strncat(path, arg, BOOT_LINE_LENGTH);
+	if (!append) path[0] = 0;
+	if ((use_rootdev == 1) && (strlen(drivername) == 0)) {
+		strlcat(path, root_device, BOOT_LINE_LENGTH);
+	} else {
+		char buffer[32];
+		strlcat(path, drivername, BOOT_LINE_LENGTH);
+		if (disk != -1) {
+			snprintf(buffer, 31, "%c", 'a'+disk);
+			strlcat(path, buffer, BOOT_LINE_LENGTH);
+		}
+		if (part != -1) {
+			snprintf(buffer, 31, "%d", part);
+			strlcat(path, buffer, BOOT_LINE_LENGTH);
+		}
+		if (addr != -1) {
+			snprintf(buffer, 31, "@0x%x", addr);
+			strlcat(path, buffer, BOOT_LINE_LENGTH);
+		}
+		buffer[0]=':';
+		buffer[1]='\0';
+		strlcat(path, buffer, BOOT_LINE_LENGTH);
+	}
+	strlcat(path, arg, BOOT_LINE_LENGTH);
 }
 
 /* initrd */
 static int initrd_func(char *arg, int flags)
 {
-	initrd_space[0]=0; // Erase string
-	copy_path_to_filo_bootline(arg, initrd_space, 1);
+	copy_path_to_filo_bootline(arg, initrd_space, 1, 0);
 	if (!file_open(initrd_space)) {
 		initrd_space[0]=0; // Erase string
 		errnum = ERR_FILE_NOT_FOUND;
@@ -877,12 +901,8 @@ static int kernel_func(char *arg, int flags)
 
 	kernel_type = KERNEL_TYPE_NONE;
 
-	/* clear out boot_line. Kernel is the first thing */
-	boot_line[0] = 0;  // Erase string
-
 	/* Get the real boot line and extract the kernel name */
-	temp_space[0] = 0; // Erase string
-	copy_path_to_filo_bootline(arg, temp_space, 1);
+	copy_path_to_filo_bootline(arg, temp_space, 1, 0);
 	i=0; while ((temp_space[i] != 0) && (temp_space[i]!=' ')) i++;
 	temp_space[i] = 0;
 
@@ -897,7 +917,7 @@ static int kernel_func(char *arg, int flags)
 	/* Needed to pass grub checks */
 	kernel_type = KERNEL_TYPE_LINUX;
 
-	copy_path_to_filo_bootline(arg, boot_line, 1);
+	copy_path_to_filo_bootline(arg, boot_line, 1, 0);
 
 	return 0;
 }
@@ -1319,8 +1339,7 @@ static int root_func(char *arg, int flags)
 {
 	int len;
 
-	root_device[0] = 0; /* Clear root device */
-	copy_path_to_filo_bootline(arg, root_device, 0);
+	copy_path_to_filo_bootline(arg, root_device, 0, 0);
 
 	/* The following code handles an extra case
 	 * where the user specifies "root hde1" without
@@ -1790,8 +1809,7 @@ static int cat_func(char *arg, int flags)
 	char buf[4096];
 	int len;
 
-	temp_space[0]=0;
-	copy_path_to_filo_bootline(arg, temp_space, 1);
+	copy_path_to_filo_bootline(arg, temp_space, 1, 0);
 	if (temp_space[0]==0) {
 		return help_func("cat",0);
 	}
diff --git a/main/grub/grub.c b/main/grub/grub.c
index b1fcdd1..1afdadd 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -127,7 +127,7 @@ void manual_grub_menulst(void)
 				break;
 
 			if (line[0]) {
-				copy_path_to_filo_bootline(line, config_file, 0);
+				copy_path_to_filo_bootline(line, config_file, 0, 1);
 				break;
 			}
 		}
@@ -143,8 +143,7 @@ int probe_menulst(char *bootdevice, char *filename)
 	strcpy(menulst, bootdevice);
 	strncat(menulst, filename, 256);
 	/* Set string to zero: */
-	config_file[0] = 0;
-	copy_path_to_filo_bootline(menulst, config_file, 0);
+	copy_path_to_filo_bootline(menulst, config_file, 0, 0);
 	if (file_open(config_file)) {
 		/* We found a config file. Bail out */
 		/* The valid config file name stays in config_file[] */



From gerrit at coreboot.org  Mon Sep  5 13:40:17 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:17 +0200
Subject: [coreboot] New patch to review: fd737d2 ide: driver message pretty
	printing
References: <I49ee83b57084c621adca2cb76fd868eaa0f6b436+0@gerrit.coreboot.org>
Message-ID: <I49ee83b57084c621adca2cb76fd868eaa0f6b436+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/199

-gerrit

commit fd737d2ab180782fcb87f6bc48fdf50226199427
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Thu Jun 9 16:30:31 2011 +0200

    ide: driver message pretty printing
    
    This patch reduces the amount of debug messages generated by the IDE
    driver and changes some of them to be less technical, but more
    informative to the user.
    
    Change-Id: I49ee83b57084c621adca2cb76fd868eaa0f6b436
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 drivers/ide_new.c |   51 +++++++++++++++++++++++++--------------------------
 1 files changed, 25 insertions(+), 26 deletions(-)

diff --git a/drivers/ide_new.c b/drivers/ide_new.c
index a2870b8..3e24b9a 100644
--- a/drivers/ide_new.c
+++ b/drivers/ide_new.c
@@ -123,7 +123,7 @@ ob_ide_pio_insw(struct ide_drive *drive, unsigned int offset,
 	struct ide_channel *chan = drive->channel;
 
 	if (len & 1) {
-		printf("%d: command not word aligned\n", drive->nr);
+		debug("hd%c: command not word aligned\n", drive->nr + 'a');
 		return;
 	}
 
@@ -137,7 +137,7 @@ ob_ide_pio_outsw(struct ide_drive *drive, unsigned int offset,
 	struct ide_channel *chan = drive->channel;
 
 	if (len & 1) {
-		printf("%d: command not word aligned\n", drive->nr);
+		debug("hd%c: command not word aligned\n", drive->nr + 'a');
 		return;
 	}
 
@@ -165,7 +165,7 @@ ob_ide_error(struct ide_drive *drive, unsigned char stat, char *msg)
 		stat = ob_ide_pio_readb(drive, IDEREG_STATUS);
 
 	debug("ob_ide_error ");
-	printf("drive<%d>: %s:\n", drive->nr, msg);
+	printf("hd%c: %s:\n", drive->nr + 'a', msg);
 	debug("    cmd=%x, stat=%x", chan->ata_cmd.command, stat);
 
 	if ((stat & (BUSY_STAT | ERR_STAT)) == ERR_STAT) {
@@ -239,7 +239,7 @@ ob_ide_select_drive(struct ide_drive *drive)
 	unsigned char control = IDEHEAD_DEV0;
 
 	if (ob_ide_wait_stat(drive, 0, BUSY_STAT, NULL)) {
-		printf("select_drive: timed out\n");
+		debug("select_drive: timed out\n");
 		return 1;
 	}
 
@@ -257,7 +257,7 @@ ob_ide_select_drive(struct ide_drive *drive)
 	ob_ide_400ns_delay(drive);
 
 	if (ob_ide_wait_stat(drive, 0, BUSY_STAT, NULL)) {
-		printf("select_drive: timed out\n");
+		debug("select_drive: timed out\n");
 		return 1;
 	}
 
@@ -403,7 +403,7 @@ ob_ide_pio_data_in(struct ide_drive *drive, struct ata_command *cmd)
 	} while (bytes);
 
 	if (bytes)
-		printf("bytes=%d, stat=%x\n", bytes, stat);
+		debug("bytes=%d, stat=%x\n", bytes, stat);
 
 	return bytes ? 1 : 0;
 }
@@ -423,7 +423,7 @@ ob_ide_pio_packet(struct ide_drive *drive, struct atapi_command *cmd)
 		return 1;
 
 	if (cmd->buflen && cmd->data_direction == atapi_ddir_none)
-		printf("non-zero buflen but no data direction\n");
+		debug("non-zero buflen but no data direction\n");
 
 	memset(acmd, 0, sizeof(*acmd));
 	acmd->lcyl = cmd->buflen & 0xff;
@@ -455,7 +455,7 @@ ob_ide_pio_packet(struct ide_drive *drive, struct atapi_command *cmd)
 		 * we are doing a sense, ERR_STAT == CHECK_CONDITION
 		 */
 		if (cmd->cdb[0] != ATAPI_REQ_SENSE) {
-			printf("odd, drive didn't want to transfer %x\n", stat);
+			debug("odd, drive didn't want to transfer %x\n", stat);
 			return 1;
 		}
 	}
@@ -524,7 +524,7 @@ ob_ide_pio_packet(struct ide_drive *drive, struct atapi_command *cmd)
 		(void) ob_ide_wait_stat(drive, 0, BUSY_STAT, &stat);
 
 	if (bytes)
-		printf("cdb failed, bytes=%d, stat=%x\n", bytes, stat);
+		debug("cdb failed, bytes=%d, stat=%x\n", bytes, stat);
 
 	return (stat & ERR_STAT) || bytes;
 }
@@ -640,7 +640,7 @@ ob_ide_atapi_drive_ready(struct ide_drive *drive)
 	cmd->cdb[0] = ATAPI_TUR;
 
 	if (ob_ide_atapi_packet(drive, cmd)) {
-		printf("%d: TUR failed\n", drive->nr);
+		printf("hd%c: TUR failed\n", drive->nr + 'a');
 		return 1;
 	}
 
@@ -654,7 +654,7 @@ ob_ide_atapi_drive_ready(struct ide_drive *drive)
 	cmd->cdb[4] = 0x01;
 
 	if (ob_ide_atapi_packet(drive, cmd)) {
-		printf("%d: START_STOP unit failed\n", drive->nr);
+		printf("hd%c: START_STOP unit failed\n", drive->nr + 'a');
 		return 1;
 	}
 
@@ -663,13 +663,13 @@ ob_ide_atapi_drive_ready(struct ide_drive *drive)
 	cmd->cdb[0] = ATAPI_PREVENT_ALLOW_MEDIUM_REMOVAL;
 	cmd->cdb[2] = 2;
 	if (ob_ide_atapi_packet(drive, cmd))
-		printf("could not persistently unlock device\n");
+		printf("hd%c: could not persistently unlock device\n", drive->nr + 'a');
 
 	/* clear Prevent State */
 	memset (cmd, 0, sizeof(*cmd));
 	cmd->cdb[0] = ATAPI_PREVENT_ALLOW_MEDIUM_REMOVAL;
 	if (ob_ide_atapi_packet(drive, cmd))
-		printf("could not unlock device\n");
+		printf("hd%c: could not unlock device\n", drive->nr + 'a');
 
 	/*
 	 * finally, get capacity and block size
@@ -707,7 +707,7 @@ ob_ide_read_atapi(struct ide_drive *drive, unsigned long long block, unsigned ch
 
 	if (drive->bs == 2048) {
 		if (((block & 3) != 0) || ((sectors & 3) != 0)) {
-			printf("ob_ide_read_atapi: unaligned atapi access: %x blocks, starting from %x\n", sectors, block);
+			debug("ob_ide_read_atapi: unaligned atapi access: %x blocks, starting from %x\n", sectors, block);
 		}
 		block >>= 2;
 		sectors >>= 2;
@@ -854,9 +854,7 @@ ob_ide_read_sectors(struct ide_drive *drive, unsigned long long block,
 	if (block + sectors > (drive->sectors * (drive->bs / 512)))
 		return 1;
 
-#ifdef CONFIG_DEBUG_IDE
-		printf("ob_ide_read_sectors: block=%ld sectors=%u\n", (unsigned long) block, sectors);
-#endif
+	debug("ob_ide_read_sectors: block=%ld sectors=%u\n", (unsigned long) block, sectors);
 
 	if (drive->type == ide_type_ata)
 		return ob_ide_read_ata(drive, block, buf, sectors);
@@ -924,7 +922,7 @@ ob_ide_identify_drive(struct ide_drive *drive)
 	else if (drive->type == ide_type_atapi)
 		cmd->command = WIN_IDENTIFY_PACKET;
 	else {
-		printf("%s: called with bad device type %d\n", __FUNCTION__, drive->type);
+		debug("%s: called with bad device type %d\n", __FUNCTION__, drive->type);
 		return 1;
 	}
 
@@ -1348,7 +1346,7 @@ int ob_ide_init(int driveno)
 	int chan_index;
 
 	if (driveno >= IDE_MAX_DRIVES) {
-		printf("Unsupported drive number\n");
+		debug("Unsupported drive number\n");
 		return -1;
 	}
 
@@ -1392,28 +1390,29 @@ int ob_ide_init(int driveno)
 
 		ob_ide_identify_drives(chan);
 
-		printf("ata-%d: [io ports 0x%x-0x%x,0x%x]\n", chan_index,
+		printf("ATA-%d: [io ports 0x%x-0x%x,0x%x]\n", chan_index,
 				chan->io_regs[0], chan->io_regs[0] + 7,
 				chan->io_regs[8]);
 
 		for (j = 0; j < 2; j++) {
 			struct ide_drive *drive = &chan->drives[j];
-			char *media = "UNKNOWN";
+			const char *media = "UNKNOWN";
 			if (!drive->present)
 				continue;
-			printf("    drive%d [ATA%s ", j, drive->type == ide_type_atapi ? "PI" : "");
+			printf("* hd%c [ATA%s ", chan_index * 2 + j + 'a',
+			       drive->type == ide_type_atapi ? "PI" : "");
 			switch (drive->media) {
 			case ide_media_floppy:
-				media = "floppy";
+				media = "Floppy";
 				break;
 			case ide_media_cdrom:
-				media = "cdrom";
+				media = "CD-ROM";
 				break;
 			case ide_media_optical:
-				media = "mo";
+				media = "MO";
 				break;
 			case ide_media_disk:
-				media = "disk";
+				media = "Disk";
 				break;
 			}
 			printf("%s]: %s\n", media, drive->model);



From gerrit at coreboot.org  Mon Sep  5 13:40:17 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:17 +0200
Subject: [coreboot] New patch to review: 181d45d Set root device while
	probing boot_devices list
References: <Id1f27a08bd86bc9a872dd52347f19a55532a82e6+0@gerrit.coreboot.org>
Message-ID: <Id1f27a08bd86bc9a872dd52347f19a55532a82e6+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/200

-gerrit

commit 181d45d266a3e4627c82690a745c0f08018f8cf5
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 11:43:32 2010 +0100

    Set root device while probing boot_devices list
    
    This way we don't need to have absolute paths in the config file itself.
    
    Change-Id: Id1f27a08bd86bc9a872dd52347f19a55532a82e6
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 main/grub/grub.c |   17 ++++++++++++++---
 1 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/main/grub/grub.c b/main/grub/grub.c
index 1afdadd..0e8970c 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -139,11 +139,22 @@ void manual_grub_menulst(void)
 int probe_menulst(char *bootdevice, char *filename)
 {
 	char menulst[256];
-
-	strcpy(menulst, bootdevice);
+	struct builtin *root;
+	int use_root;
+
+	memset(menulst, 0, sizeof(menulst));
+	root = find_command("root");
+	if (root != NULL) {
+		(root->func)(bootdevice, BUILTIN_SCRIPT);
+		use_root = 1;
+	} else {
+		strcpy(menulst, bootdevice);
+		use_root = 0;
+	}
 	strncat(menulst, filename, 256);
+
 	/* Set string to zero: */
-	copy_path_to_filo_bootline(menulst, config_file, 0, 0);
+	copy_path_to_filo_bootline(menulst, config_file, use_root, 0);
 	if (file_open(config_file)) {
 		/* We found a config file. Bail out */
 		/* The valid config file name stays in config_file[] */



From gerrit at coreboot.org  Mon Sep  5 13:40:18 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 5 Sep 2011 13:40:18 +0200
Subject: [coreboot] New patch to review: e4f93b2 Show root device we're
	booted from in header.
References: <I9288f88f6673fafa41d13f2035ea3b9b6550dbb2+0@gerrit.coreboot.org>
Message-ID: <I9288f88f6673fafa41d13f2035ea3b9b6550dbb2+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/201

-gerrit

commit e4f93b2957a293efea945dac6566547ede17b591
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 12:05:40 2010 +0100

    Show root device we're booted from in header.
    
    Change-Id: I9288f88f6673fafa41d13f2035ea3b9b6550dbb2
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 main/grub/char_io.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/main/grub/char_io.c b/main/grub/char_io.c
index d2d9f6f..f37cc23 100644
--- a/main/grub/char_io.c
+++ b/main/grub/char_io.c
@@ -24,6 +24,8 @@
 #include <version.h>
 #include <grub/shared.h>
 
+extern char root_device[];
+
 char *err_list[] = {
 	[ERR_NONE] = 0,
 	[ERR_BAD_ARGUMENT] = "Invalid argument",
@@ -98,8 +100,10 @@ void init_page(void)
 {
 	color_set(1, NULL);
 	cls();
-	grub_printf("\n                                  %s %s\n\n", 
+	grub_printf("\n                                  %s %s\n",
 			PROGRAM_NAME, PROGRAM_VERSION);
+	grub_printf("                               root_dev = %s\n",
+			root_device[0] ? root_device : "unset");
 }
 
 /* The number of the history entries.  */



From svn at coreboot.org  Mon Sep  5 16:00:01 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 05 Sep 2011 16:00:01 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1R0ZiT-0004Ev-F4@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110905/67b9750f/attachment.html>

From ahardyx at yahoo.in  Mon Sep  5 16:46:09 2011
From: ahardyx at yahoo.in (Abhinav Hardikar)
Date: Mon, 5 Sep 2011 20:16:09 +0530 (IST)
Subject: [coreboot] [PATCH] Adding Jetway J7BXAN to mainboards list
In-Reply-To: <1314199890.95755.YahooMailNeo@web95411.mail.in2.yahoo.com>
References: <1313759615.12065.YahooMailNeo@web95407.mail.in2.yahoo.com>
	<1313768816.16560.19.camel@ts-laptop>
	<1313771107.73290.YahooMailNeo@web95415.mail.in2.yahoo.com>
	<1313772991.16560.36.camel@ts-laptop>
	<1313774179.82961.YahooMailNeo@web95415.mail.in2.yahoo.com>
	<1313774985.16560.39.camel@ts-laptop>
	<1313775779.84024.YahooMailNeo@web95411.mail.in2.yahoo.com>
	<1313776587.16560.52.camel@ts-laptop>
	<1313778901.36887.YahooMailNeo@web95404.mail.in2.yahoo.com>
	<1313783608.16560.61.camel@ts-laptop>
	<1313814943.58012.YahooMailNeo@web95401.mail.in2.yahoo.com>
	<1313816779.3185.YahooMailNeo@web95404.mail.in2.yahoo.com>
	<1313833027.24864.43.camel@ts-laptop>
	<1313835001.4676.40.camel@mattotaupa>
	<4E4F8E7E.9000202@georgi-clan.de>
	<1313849291.24262.YahooMailNeo@web95402.mail.in2.yahoo.com>
	<1313850454.24864.49.camel@ts-laptop>
	<1314199890.95755.YahooMailNeo@web95411.mail.in2.yahoo.com>
Message-ID: <1315233969.50372.YahooMailNeo@web95411.mail.in2.yahoo.com>

Ok sorry for the late reply!

I have posted the video of coreboot working on the mobo.
Now I am sending this working patch. I have tested it.

I just want you people to recheck if it is working. :)

Thanx for everything!
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From gerrit at coreboot.org  Mon Sep  5 18:03:50 2011
From: gerrit at coreboot.org (QingPei Wang (wangqingpei@gmail.com))
Date: Mon, 5 Sep 2011 18:03:50 +0200
Subject: [coreboot] New patch to review: 854cd94 Add AMD Family 10h PH-EO
	support
References: <If701c8a908edf1c486665d3ce4df65da0f65c802+0@gerrit.coreboot.org>
Message-ID: <If701c8a908edf1c486665d3ce4df65da0f65c802+1@gerrit.coreboot.org>

QingPei Wang (wangqingpei at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/202

-gerrit

commit 854cd94c4feba4304a09063727f7c2562b87af85
Author: QingPei Wang <wangqingpei at gmail.com>
Date:   Tue Sep 6 00:01:57 2011 +0800

    Add AMD Family 10h PH-EO support
    
    Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802
    Signed-off-by: QingPei Wang <wangqingpei at gmail.com>
---
 src/cpu/amd/model_10xxx/mc_patch_010000bf.h |  165 +++++++++++++++++++++++++++
 1 files changed, 165 insertions(+), 0 deletions(-)

diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000bf.h b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h
new file mode 100644
index 0000000..ea971bc
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h
@@ -0,0 +1,165 @@
+/*
+ ============================================================
+ Copyright (c) Advanced Micro Devices, Inc., 2004-2008
+ Copyright QingPei Wang <wangqingpei at gmail.com>
+
+ The  enclosed microcode  is intended  to be  used  with AMD
+ Microprocessors.  You  may   copy,  view  and  install  the
+ enclosed microcode  only for development  and deployment of
+ firmware,  BIOS,  or  operating  system code  for  computer
+ systems   that  contain  AMD   processors.   You   are  not
+ authorized  to use  the  enclosed microcode  for any  other
+ purpose.
+
+ THE  MICROCODE IS PROVIDED  "AS IS"  WITHOUT ANY  EXPRESS OR
+ IMPLIED WARRANTY  OF ANY KIND, INCLUDING BUT  NOT LIMITED TO
+ WARRANTIES    OF    MERCHANTABILITY,   NON-    INFRINGEMENT,
+ TITLE,FITNESS  FOR  ANY  PARTICULAR PURPOSE,  OR  WARRANTIES
+ ARISING FROM CONDUCT, COURSE  OF DEALING, OR USAGE OF TRADE.
+ AMD does not assume  any responsibility for any errors which
+ may  appear   in  this   microcode  or  any   other  related
+ information provided  to you by  AMD, or result from  use of
+ this microcode.   AMD is not obligated  to furnish, support,
+ or  make   any  further  information,   software,  technical
+ information, know-how, or show-how available related to this
+ microcode.
+
+ The  microcode is provided  with "RESTRICTED  RIGHTS."  Use,
+ duplication, or disclosure by the U.S. Government is subject
+ to  the  restrictions as  set  forth  in  FAR 52.227-14  and
+ DFAR252.227-7013,  et seq.,  or its  successor.  Use  of the
+ microcode    by    the    U.S.     Government    constitutes
+ acknowledgement  of   AMD's  proprietary  rights   in  them.
+ ============================================================
+*/
+
+
+0x10, 0x20, 0x17, 0x02, 0xbf, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00,
+0x42, 0x82, 0x02, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0xa0, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x74, 0x0f, 0x00, 0x00,
+0xbe, 0x01, 0x00, 0x00, 0x33, 0x0e, 0x00, 0x00, 0xa9, 0x01, 0x00, 0x00,
+0x75, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xa0, 0xfd, 0xff, 0x28, 0xc3, 0x3f, 0xc0, 0xcf,
+0xff, 0x07, 0xe2, 0x01, 0x0f, 0xde, 0x50, 0xfe, 0xf2, 0xdf, 0xff, 0x0f,
+0x3b, 0xfc, 0x01, 0xc5, 0x40, 0x03, 0xd4, 0x00, 0x80, 0xff, 0xfe, 0x7f,
+0xfe, 0xe1, 0x1b, 0xc8, 0x5b, 0xf6, 0xff, 0xff, 0x7b, 0x87, 0x5f, 0xad,
+0x6b, 0xf9, 0x6f, 0xfe, 0xfa, 0x1f, 0xfe, 0xb5, 0x00, 0x40, 0x11, 0x6a,
+0x0e, 0xc0, 0x9b, 0x56, 0xe8, 0x75, 0xe0, 0x0f, 0x38, 0x00, 0xcf, 0xcc,
+0xa0, 0xd7, 0x83, 0x3f, 0xff, 0x7b, 0xfc, 0xbf, 0x00, 0x3f, 0x0f, 0xff,
+0x35, 0x00, 0x80, 0xd0, 0x18, 0x07, 0x60, 0x19, 0x07, 0xf4, 0x7a, 0xf0,
+0xa6, 0x1c, 0x00, 0x38, 0x1f, 0xc0, 0xe7, 0xa0, 0xff, 0xff, 0x51, 0x9e,
+0x7f, 0x80, 0x9f, 0x87, 0x80, 0x0a, 0x00, 0x60, 0xd3, 0xe0, 0x4f, 0x10,
+0xfc, 0x32, 0xd8, 0x3a, 0x49, 0xff, 0x7f, 0xcb, 0xf0, 0x0f, 0xf0, 0xf3,
+0x8c, 0xff, 0xff, 0x00, 0xc3, 0x31, 0x17, 0xfd, 0x2c, 0x47, 0x0d, 0x00,
+0xd0, 0x32, 0xf0, 0x27, 0x1d, 0x7e, 0x19, 0x6c, 0x60, 0xf1, 0xff, 0x1f,
+0x7f, 0x38, 0xe6, 0xa2, 0x16, 0x35, 0xff, 0xff, 0xe7, 0xe1, 0x1f, 0xe0,
+0x00, 0xfe, 0xbf, 0x07, 0xbb, 0x9c, 0xf4, 0xff, 0x3f, 0x0f, 0xff, 0x00,
+0x07, 0xf8, 0xdf, 0x8d, 0x0b, 0x3e, 0x78, 0x73, 0x3f, 0x8b, 0xff, 0xff,
+0x70, 0xe5, 0xf0, 0x0b, 0x03, 0x00, 0x0f, 0x50, 0xff, 0x52, 0xfe, 0xbb,
+0xaf, 0xfa, 0x87, 0x7f, 0xff, 0x07, 0xc0, 0xff, 0xa5, 0x14, 0x1f, 0xbe,
+0xff, 0x9f, 0xc5, 0xff, 0xc4, 0xaa, 0x72, 0xf8, 0xef, 0x01, 0x80, 0xff,
+0xeb, 0xff, 0x00, 0x43, 0x37, 0x96, 0xfd, 0xc3, 0xf6, 0xff, 0xab, 0x80,
+0xff, 0x00, 0x3f, 0x0f, 0xff, 0xff, 0x8f, 0xe2, 0xfc, 0x02, 0x54, 0x39,
+0xda, 0xd5, 0x00, 0x80, 0xff, 0x68, 0x3c, 0xe0, 0xc1, 0x9b, 0xca, 0xfe,
+0xe4, 0xff, 0xff, 0x09, 0x87, 0x5f, 0x06, 0x5b, 0xfe, 0x0f, 0xc4, 0x03,
+0x1e, 0xfa, 0xa9, 0x7c, 0xe0, 0xff, 0x7b, 0x00, 0xc0, 0x7f, 0xe0, 0x1f,
+0xdf, 0xf0, 0x0f, 0xe0, 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
+0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, 0x00, 0xf0, 0xff, 0x3d,
+0x0f, 0xe0, 0x3f, 0xf0, 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0,
+0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
+0x1e, 0x00, 0xf8, 0xff, 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
+0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
+0x3f, 0x80, 0x7f, 0xc3, 0x7f, 0x0f, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8,
+0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
+0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0xbf, 0x07, 0x00,
+0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07,
+0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
+0x00, 0xff, 0xdf, 0x03, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00,
+0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
+0xf0, 0x6f, 0xf8, 0x07, 0x01, 0x80, 0xff, 0xef, 0x7f, 0xbf, 0xff, 0x81,
+0xdf, 0x95, 0xc1, 0xaf, 0xff, 0x91, 0xfc, 0x2f, 0x48, 0x57, 0x06, 0xbf,
+0xff, 0x4f, 0xb0, 0xff, 0x32, 0xd8, 0x3a, 0xfc, 0xd7, 0x00, 0x40, 0x95,
+0x81, 0xff, 0x94, 0x01, 0x1f, 0xe0, 0xe7, 0xe1, 0xff, 0xff, 0x53, 0xce,
+0x7f, 0xa9, 0xeb, 0x83, 0xff, 0xef, 0x4b, 0xfd, 0xfc, 0xbd, 0xbd, 0x0e,
+0xff, 0x7b, 0x00, 0xe0, 0x9c, 0x56, 0x0e, 0x00, 0xd0, 0x0f, 0xe0, 0x73,
+0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, 0xfc, 0x07, 0xfe, 0x01,
+0x0d, 0xff, 0x00, 0xfe, 0xe0, 0xfd, 0x35, 0x00, 0xe0, 0x0d, 0x2b, 0x07,
+0x3a, 0xf0, 0x07, 0xf4, 0x96, 0xff, 0xed, 0x3f, 0xff, 0xe1, 0x1f, 0xab,
+0x5b, 0x02, 0x00, 0xfe, 0xfb, 0x87, 0x7f, 0xac, 0x00, 0xa8, 0xcd, 0x1a,
+0x6f, 0x72, 0xc0, 0xff, 0xfc, 0x3c, 0xfc, 0x03, 0x1f, 0xc0, 0x7f, 0xe0,
+0xe0, 0xdf, 0xf0, 0x0f, 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
+0x0f, 0x00, 0xfc, 0x7f, 0xff, 0x7f, 0x79, 0xfc, 0x01, 0x7e, 0x1e, 0xfe,
+0x2b, 0x07, 0xe0, 0xfe, 0x07, 0xf0, 0x39, 0xe8, 0xc0, 0x3f, 0x80, 0xff,
+0x1f, 0xc0, 0xbf, 0xe1, 0xb9, 0x06, 0x00, 0x78, 0xf6, 0xff, 0xbf, 0x80,
+0xff, 0x00, 0x3f, 0x0f, 0xff, 0xff, 0x8f, 0xe2, 0xfc, 0x03, 0xfc, 0x3c,
+0x7f, 0x34, 0x1e, 0xf0, 0xd0, 0xef, 0xe5, 0xf3, 0xff, 0xdf, 0x03, 0x00,
+0xee, 0xa3, 0x72, 0x00, 0x83, 0x7e, 0x00, 0x9f, 0xf8, 0xfd, 0xff, 0x07,
+0x1f, 0xbe, 0xb1, 0xec, 0x65, 0x97, 0xff, 0x1f, 0x79, 0xf8, 0x07, 0xf8,
+0x80, 0xc4, 0x97, 0x01, 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
+0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, 0x07, 0xf0, 0x1f, 0xf8,
+0xf8, 0x37, 0xfc, 0x03, 0x00, 0xc0, 0xff, 0xf7, 0x3f, 0x80, 0xff, 0xc0,
+0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
+0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe, 0x7b, 0x00, 0xe0, 0xff,
+0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
+0x3f, 0x80, 0x7f, 0xc3, 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
+0xff, 0x3d, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
+0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
+0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x1e, 0x00, 0xf0, 0x1f, 0xf8, 0x07,
+0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
+0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, 0x00, 0xfc, 0x7f, 0x0f,
+0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
+0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, 0xc0, 0xbf, 0xe1, 0x1f,
+0x07, 0x00, 0xfe, 0xbf, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
+0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xe0, 0x1f, 0xc0, 0x7f,
+0x0f, 0xe0, 0xdf, 0xf0, 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
+0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
+0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
+
+
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,



From patrick at georgi-clan.de  Mon Sep  5 18:56:33 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 05 Sep 2011 18:56:33 +0200
Subject: [coreboot] [PATCH] Adding Jetway J7BXAN to mainboards list
In-Reply-To: <1315233969.50372.YahooMailNeo@web95411.mail.in2.yahoo.com>
References: <1313759615.12065.YahooMailNeo@web95407.mail.in2.yahoo.com>
	<1313768816.16560.19.camel@ts-laptop>
	<1313771107.73290.YahooMailNeo@web95415.mail.in2.yahoo.com>
	<1313772991.16560.36.camel@ts-laptop>
	<1313774179.82961.YahooMailNeo@web95415.mail.in2.yahoo.com>
	<1313774985.16560.39.camel@ts-laptop>
	<1313775779.84024.YahooMailNeo@web95411.mail.in2.yahoo.com>
	<1313776587.16560.52.camel@ts-laptop>
	<1313778901.36887.YahooMailNeo@web95404.mail.in2.yahoo.com>
	<1313783608.16560.61.camel@ts-laptop>
	<1313814943.58012.YahooMailNeo@web95401.mail.in2.yahoo.com>
	<1313816779.3185.YahooMailNeo@web95404.mail.in2.yahoo.com>
	<1313833027.24864.43.camel@ts-laptop>
	<1313835001.4676.40.camel@mattotaupa>
	<4E4F8E7E.9000202@georgi-clan.de>
	<1313849291.24262.YahooMailNeo@web95402.mail.in2.yahoo.com>
	<1313850454.24864.49.camel@ts-laptop>
	<1314199890.95755.YahooMailNeo@web95411.mail.in2.yahoo.com>
	<1315233969.50372.YahooMailNeo@web95411.mail.in2.yahoo.com>
Message-ID: <4b9da6103b9ce3490dae612a1736536f@mail.georgi-clan.de>

On Mon, 5 Sep 2011 20:16:09 +0530 (IST), Abhinav Hardikar wrote:
> I have posted the video of coreboot working on the mobo.
> Now I am sending this working patch. I have tested it.
Could you please submit it to our Gerrit instance?

See http://www.coreboot.org/Git for instructions.


Thanks,
Patrick



From gerrit at coreboot.org  Tue Sep  6 03:36:10 2011
From: gerrit at coreboot.org (QingPei Wang (wangqingpei@gmail.com))
Date: Tue, 6 Sep 2011 03:36:10 +0200
Subject: [coreboot] New patch to review: 7d680c9 append to the last patch.
References: <Ie1892168254e507404b0de8196f35778e22f3b26+0@gerrit.coreboot.org>
Message-ID: <Ie1892168254e507404b0de8196f35778e22f3b26+1@gerrit.coreboot.org>

QingPei Wang (wangqingpei at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/203

-gerrit

commit 7d680c9ca12758ca72f27c6810bbc99714dd015e
Author: QingPei Wang <wangqingpei at gmail.com>
Date:   Tue Sep 6 09:22:38 2011 +0800

    append to the last patch.
    
    make coreboot could loop up the CPU table to find the PH-E0.
    
    Change-Id: Ie1892168254e507404b0de8196f35778e22f3b26
    Signed-off-by: QingPei Wang <wangqingpei at gmail.com>
---
 src/cpu/amd/model_10xxx/model_10xxx_init.c |    1 +
 src/cpu/amd/model_10xxx/update_microcode.c |    2 ++
 src/northbridge/amd/amdmct/amddefs.h       |    3 ++-
 3 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 2e8bbfe..cf11135 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -157,6 +157,7 @@ static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
 	{ X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */
 	{ X86_VENDOR_AMD, 0x100F81 },           /* HY-D1 */
+	{ X86_VENDOR_AMD, 0x100FA0 },           /* PH-E0 */
 	{ 0, 0 },
 };
 
diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
index fa3b4f8..a9faafa 100644
--- a/src/cpu/amd/model_10xxx/update_microcode.c
+++ b/src/cpu/amd/model_10xxx/update_microcode.c
@@ -51,6 +51,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
  * 00100F62h (DA-C2)     1062h                  0100009Fh
  * 00100F63h (DA-C3)     1043h                  010000b6h
  * 00100F81h (HY-D1)     1081h                  010000c4h
+ * 00100FA0h (PH-E0)     10A0h                  010000bfh
  */
 
 #include CONFIG_AMD_UCODE_PATCH_FILE
@@ -78,6 +79,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
 		0x100f62, 0x1062,
 		0x100f63, 0x1043,
 		0x100f81, 0x1081,
+		0x100fa0, 0x10A0,
 	};
 
 	u32 new_id;
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 7852668..d302085 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -46,6 +46,7 @@
 #define	AMD_RB_C3	0x08000000	/* ??? C3 */
 #define	AMD_DA_C3	0x10000000	/* XXXX C3 */
 #define	AMD_HY_D1	0x20000000	/* Istanbul D1 */
+#define AMD_PH_E0	0x40000000	/* Phenom II X4 X6 */
 
 /*
  * Groups - Create as many as you wish, from the above public values
@@ -64,7 +65,7 @@
 #define	AMD_DR_GT_B0	(AMD_DR_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_GT_Bx	(AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
 #define	AMD_DR_ALL	(AMD_DR_Bx)
-#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1)
+#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
 #define AMD_FAM10_LT_D  (AMD_FAM10_ALL & ~(AMD_HY_D0))
 #define	AMD_FAM10_GT_B0	(AMD_FAM10_ALL & ~(AMD_DR_B0))
 #define	AMD_DA_Cx       (AMD_DA_C2 | AMD_DA_C3)



From gerrit at coreboot.org  Tue Sep  6 08:30:28 2011
From: gerrit at coreboot.org (QingPei Wang (wangqingpei@gmail.com))
Date: Tue, 6 Sep 2011 08:30:28 +0200
Subject: [coreboot] Patch set updated: 093a614 Add AMD Family 10h PH-EO
	support
References: <If701c8a908edf1c486665d3ce4df65da0f65c802+0@gerrit.coreboot.org>
Message-ID: <If701c8a908edf1c486665d3ce4df65da0f65c802+2@gerrit.coreboot.org>

QingPei Wang (wangqingpei at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/202

-gerrit

commit 093a6146f2775b4de6a5dff28b0fafc269632e0f
Author: QingPei Wang <wangqingpei at gmail.com>
Date:   Tue Sep 6 00:01:57 2011 +0800

    Add AMD Family 10h PH-EO support
    
    Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802
    Signed-off-by: QingPei Wang <wangqingpei at gmail.com>
---
 src/cpu/amd/model_10xxx/mc_patch_010000bf.h |  165 +++++++++++++++++++++++++++
 src/cpu/amd/model_10xxx/model_10xxx_init.c  |    1 +
 src/cpu/amd/model_10xxx/update_microcode.c  |    2 +
 src/northbridge/amd/amdmct/amddefs.h        |    3 +-
 4 files changed, 170 insertions(+), 1 deletions(-)

diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000bf.h b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h
new file mode 100644
index 0000000..ea971bc
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h
@@ -0,0 +1,165 @@
+/*
+ ============================================================
+ Copyright (c) Advanced Micro Devices, Inc., 2004-2008
+ Copyright QingPei Wang <wangqingpei at gmail.com>
+
+ The  enclosed microcode  is intended  to be  used  with AMD
+ Microprocessors.  You  may   copy,  view  and  install  the
+ enclosed microcode  only for development  and deployment of
+ firmware,  BIOS,  or  operating  system code  for  computer
+ systems   that  contain  AMD   processors.   You   are  not
+ authorized  to use  the  enclosed microcode  for any  other
+ purpose.
+
+ THE  MICROCODE IS PROVIDED  "AS IS"  WITHOUT ANY  EXPRESS OR
+ IMPLIED WARRANTY  OF ANY KIND, INCLUDING BUT  NOT LIMITED TO
+ WARRANTIES    OF    MERCHANTABILITY,   NON-    INFRINGEMENT,
+ TITLE,FITNESS  FOR  ANY  PARTICULAR PURPOSE,  OR  WARRANTIES
+ ARISING FROM CONDUCT, COURSE  OF DEALING, OR USAGE OF TRADE.
+ AMD does not assume  any responsibility for any errors which
+ may  appear   in  this   microcode  or  any   other  related
+ information provided  to you by  AMD, or result from  use of
+ this microcode.   AMD is not obligated  to furnish, support,
+ or  make   any  further  information,   software,  technical
+ information, know-how, or show-how available related to this
+ microcode.
+
+ The  microcode is provided  with "RESTRICTED  RIGHTS."  Use,
+ duplication, or disclosure by the U.S. Government is subject
+ to  the  restrictions as  set  forth  in  FAR 52.227-14  and
+ DFAR252.227-7013,  et seq.,  or its  successor.  Use  of the
+ microcode    by    the    U.S.     Government    constitutes
+ acknowledgement  of   AMD's  proprietary  rights   in  them.
+ ============================================================
+*/
+
+
+0x10, 0x20, 0x17, 0x02, 0xbf, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00,
+0x42, 0x82, 0x02, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0xa0, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x74, 0x0f, 0x00, 0x00,
+0xbe, 0x01, 0x00, 0x00, 0x33, 0x0e, 0x00, 0x00, 0xa9, 0x01, 0x00, 0x00,
+0x75, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xa0, 0xfd, 0xff, 0x28, 0xc3, 0x3f, 0xc0, 0xcf,
+0xff, 0x07, 0xe2, 0x01, 0x0f, 0xde, 0x50, 0xfe, 0xf2, 0xdf, 0xff, 0x0f,
+0x3b, 0xfc, 0x01, 0xc5, 0x40, 0x03, 0xd4, 0x00, 0x80, 0xff, 0xfe, 0x7f,
+0xfe, 0xe1, 0x1b, 0xc8, 0x5b, 0xf6, 0xff, 0xff, 0x7b, 0x87, 0x5f, 0xad,
+0x6b, 0xf9, 0x6f, 0xfe, 0xfa, 0x1f, 0xfe, 0xb5, 0x00, 0x40, 0x11, 0x6a,
+0x0e, 0xc0, 0x9b, 0x56, 0xe8, 0x75, 0xe0, 0x0f, 0x38, 0x00, 0xcf, 0xcc,
+0xa0, 0xd7, 0x83, 0x3f, 0xff, 0x7b, 0xfc, 0xbf, 0x00, 0x3f, 0x0f, 0xff,
+0x35, 0x00, 0x80, 0xd0, 0x18, 0x07, 0x60, 0x19, 0x07, 0xf4, 0x7a, 0xf0,
+0xa6, 0x1c, 0x00, 0x38, 0x1f, 0xc0, 0xe7, 0xa0, 0xff, 0xff, 0x51, 0x9e,
+0x7f, 0x80, 0x9f, 0x87, 0x80, 0x0a, 0x00, 0x60, 0xd3, 0xe0, 0x4f, 0x10,
+0xfc, 0x32, 0xd8, 0x3a, 0x49, 0xff, 0x7f, 0xcb, 0xf0, 0x0f, 0xf0, 0xf3,
+0x8c, 0xff, 0xff, 0x00, 0xc3, 0x31, 0x17, 0xfd, 0x2c, 0x47, 0x0d, 0x00,
+0xd0, 0x32, 0xf0, 0x27, 0x1d, 0x7e, 0x19, 0x6c, 0x60, 0xf1, 0xff, 0x1f,
+0x7f, 0x38, 0xe6, 0xa2, 0x16, 0x35, 0xff, 0xff, 0xe7, 0xe1, 0x1f, 0xe0,
+0x00, 0xfe, 0xbf, 0x07, 0xbb, 0x9c, 0xf4, 0xff, 0x3f, 0x0f, 0xff, 0x00,
+0x07, 0xf8, 0xdf, 0x8d, 0x0b, 0x3e, 0x78, 0x73, 0x3f, 0x8b, 0xff, 0xff,
+0x70, 0xe5, 0xf0, 0x0b, 0x03, 0x00, 0x0f, 0x50, 0xff, 0x52, 0xfe, 0xbb,
+0xaf, 0xfa, 0x87, 0x7f, 0xff, 0x07, 0xc0, 0xff, 0xa5, 0x14, 0x1f, 0xbe,
+0xff, 0x9f, 0xc5, 0xff, 0xc4, 0xaa, 0x72, 0xf8, 0xef, 0x01, 0x80, 0xff,
+0xeb, 0xff, 0x00, 0x43, 0x37, 0x96, 0xfd, 0xc3, 0xf6, 0xff, 0xab, 0x80,
+0xff, 0x00, 0x3f, 0x0f, 0xff, 0xff, 0x8f, 0xe2, 0xfc, 0x02, 0x54, 0x39,
+0xda, 0xd5, 0x00, 0x80, 0xff, 0x68, 0x3c, 0xe0, 0xc1, 0x9b, 0xca, 0xfe,
+0xe4, 0xff, 0xff, 0x09, 0x87, 0x5f, 0x06, 0x5b, 0xfe, 0x0f, 0xc4, 0x03,
+0x1e, 0xfa, 0xa9, 0x7c, 0xe0, 0xff, 0x7b, 0x00, 0xc0, 0x7f, 0xe0, 0x1f,
+0xdf, 0xf0, 0x0f, 0xe0, 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
+0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, 0x00, 0xf0, 0xff, 0x3d,
+0x0f, 0xe0, 0x3f, 0xf0, 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0,
+0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
+0x1e, 0x00, 0xf8, 0xff, 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
+0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
+0x3f, 0x80, 0x7f, 0xc3, 0x7f, 0x0f, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8,
+0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
+0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0xbf, 0x07, 0x00,
+0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07,
+0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
+0x00, 0xff, 0xdf, 0x03, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00,
+0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
+0xf0, 0x6f, 0xf8, 0x07, 0x01, 0x80, 0xff, 0xef, 0x7f, 0xbf, 0xff, 0x81,
+0xdf, 0x95, 0xc1, 0xaf, 0xff, 0x91, 0xfc, 0x2f, 0x48, 0x57, 0x06, 0xbf,
+0xff, 0x4f, 0xb0, 0xff, 0x32, 0xd8, 0x3a, 0xfc, 0xd7, 0x00, 0x40, 0x95,
+0x81, 0xff, 0x94, 0x01, 0x1f, 0xe0, 0xe7, 0xe1, 0xff, 0xff, 0x53, 0xce,
+0x7f, 0xa9, 0xeb, 0x83, 0xff, 0xef, 0x4b, 0xfd, 0xfc, 0xbd, 0xbd, 0x0e,
+0xff, 0x7b, 0x00, 0xe0, 0x9c, 0x56, 0x0e, 0x00, 0xd0, 0x0f, 0xe0, 0x73,
+0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, 0xfc, 0x07, 0xfe, 0x01,
+0x0d, 0xff, 0x00, 0xfe, 0xe0, 0xfd, 0x35, 0x00, 0xe0, 0x0d, 0x2b, 0x07,
+0x3a, 0xf0, 0x07, 0xf4, 0x96, 0xff, 0xed, 0x3f, 0xff, 0xe1, 0x1f, 0xab,
+0x5b, 0x02, 0x00, 0xfe, 0xfb, 0x87, 0x7f, 0xac, 0x00, 0xa8, 0xcd, 0x1a,
+0x6f, 0x72, 0xc0, 0xff, 0xfc, 0x3c, 0xfc, 0x03, 0x1f, 0xc0, 0x7f, 0xe0,
+0xe0, 0xdf, 0xf0, 0x0f, 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
+0x0f, 0x00, 0xfc, 0x7f, 0xff, 0x7f, 0x79, 0xfc, 0x01, 0x7e, 0x1e, 0xfe,
+0x2b, 0x07, 0xe0, 0xfe, 0x07, 0xf0, 0x39, 0xe8, 0xc0, 0x3f, 0x80, 0xff,
+0x1f, 0xc0, 0xbf, 0xe1, 0xb9, 0x06, 0x00, 0x78, 0xf6, 0xff, 0xbf, 0x80,
+0xff, 0x00, 0x3f, 0x0f, 0xff, 0xff, 0x8f, 0xe2, 0xfc, 0x03, 0xfc, 0x3c,
+0x7f, 0x34, 0x1e, 0xf0, 0xd0, 0xef, 0xe5, 0xf3, 0xff, 0xdf, 0x03, 0x00,
+0xee, 0xa3, 0x72, 0x00, 0x83, 0x7e, 0x00, 0x9f, 0xf8, 0xfd, 0xff, 0x07,
+0x1f, 0xbe, 0xb1, 0xec, 0x65, 0x97, 0xff, 0x1f, 0x79, 0xf8, 0x07, 0xf8,
+0x80, 0xc4, 0x97, 0x01, 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
+0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, 0x07, 0xf0, 0x1f, 0xf8,
+0xf8, 0x37, 0xfc, 0x03, 0x00, 0xc0, 0xff, 0xf7, 0x3f, 0x80, 0xff, 0xc0,
+0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
+0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe, 0x7b, 0x00, 0xe0, 0xff,
+0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
+0x3f, 0x80, 0x7f, 0xc3, 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
+0xff, 0x3d, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
+0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
+0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x1e, 0x00, 0xf0, 0x1f, 0xf8, 0x07,
+0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
+0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, 0x00, 0xfc, 0x7f, 0x0f,
+0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
+0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, 0xc0, 0xbf, 0xe1, 0x1f,
+0x07, 0x00, 0xfe, 0xbf, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
+0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xe0, 0x1f, 0xc0, 0x7f,
+0x0f, 0xe0, 0xdf, 0xf0, 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
+0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
+0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
+
+
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 2e8bbfe..cf11135 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -157,6 +157,7 @@ static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
 	{ X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */
 	{ X86_VENDOR_AMD, 0x100F81 },           /* HY-D1 */
+	{ X86_VENDOR_AMD, 0x100FA0 },           /* PH-E0 */
 	{ 0, 0 },
 };
 
diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
index fa3b4f8..a9faafa 100644
--- a/src/cpu/amd/model_10xxx/update_microcode.c
+++ b/src/cpu/amd/model_10xxx/update_microcode.c
@@ -51,6 +51,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
  * 00100F62h (DA-C2)     1062h                  0100009Fh
  * 00100F63h (DA-C3)     1043h                  010000b6h
  * 00100F81h (HY-D1)     1081h                  010000c4h
+ * 00100FA0h (PH-E0)     10A0h                  010000bfh
  */
 
 #include CONFIG_AMD_UCODE_PATCH_FILE
@@ -78,6 +79,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
 		0x100f62, 0x1062,
 		0x100f63, 0x1043,
 		0x100f81, 0x1081,
+		0x100fa0, 0x10A0,
 	};
 
 	u32 new_id;
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 7852668..d302085 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -46,6 +46,7 @@
 #define	AMD_RB_C3	0x08000000	/* ??? C3 */
 #define	AMD_DA_C3	0x10000000	/* XXXX C3 */
 #define	AMD_HY_D1	0x20000000	/* Istanbul D1 */
+#define AMD_PH_E0	0x40000000	/* Phenom II X4 X6 */
 
 /*
  * Groups - Create as many as you wish, from the above public values
@@ -64,7 +65,7 @@
 #define	AMD_DR_GT_B0	(AMD_DR_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_GT_Bx	(AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
 #define	AMD_DR_ALL	(AMD_DR_Bx)
-#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1)
+#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
 #define AMD_FAM10_LT_D  (AMD_FAM10_ALL & ~(AMD_HY_D0))
 #define	AMD_FAM10_GT_B0	(AMD_FAM10_ALL & ~(AMD_DR_B0))
 #define	AMD_DA_Cx       (AMD_DA_C2 | AMD_DA_C3)



From gerrit at coreboot.org  Tue Sep  6 09:28:08 2011
From: gerrit at coreboot.org (QingPei Wang (wangqingpei@gmail.com))
Date: Tue, 6 Sep 2011 09:28:08 +0200
Subject: [coreboot] New patch to review: 7282fb1 Add IT8721F support
References: <Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f+0@gerrit.coreboot.org>
Message-ID: <Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f+1@gerrit.coreboot.org>

QingPei Wang (wangqingpei at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/204

-gerrit

commit 7282fb149f713a9bdfb3703c4b17e455a267ac11
Author: QingPei Wang <wangqingpei at gmail.com>
Date:   Tue Sep 6 15:24:36 2011 +0800

    Add IT8721F support
    
    only the serial port is tested, keyboard/mouse are gonna
    to be tested later, it may also need some more patches
    to make it work completely.
    
    Change-Id: Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f
    Signed-off-by: QingPei Wang <wangqingpei at gmail.com>
---
 src/superio/ite/Kconfig                |    2 +
 src/superio/ite/Makefile.inc           |    1 +
 src/superio/ite/it8721f/Makefile.inc   |   22 ++++++++
 src/superio/ite/it8721f/chip.h         |   35 ++++++++++++
 src/superio/ite/it8721f/early_serial.c |   93 ++++++++++++++++++++++++++++++++
 src/superio/ite/it8721f/it8721f.h      |   43 +++++++++++++++
 src/superio/ite/it8721f/superio.c      |   78 ++++++++++++++++++++++++++
 7 files changed, 274 insertions(+), 0 deletions(-)

diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig
index cb0c571..d045bf4 100644
--- a/src/superio/ite/Kconfig
+++ b/src/superio/ite/Kconfig
@@ -36,3 +36,5 @@ config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
 	default n
 config SUPERIO_ITE_IT8718F
 	bool
+config SUPERIO_ITE_IT8721F
+	bool
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index 21f7707..1e734fe 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -24,3 +24,4 @@ subdirs-y += it8705f
 subdirs-y += it8712f
 subdirs-y += it8716f
 subdirs-y += it8718f
+subdirs-y += it8721f
diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc
new file mode 100644
index 0000000..3908237
--- /dev/null
+++ b/src/superio/ite/it8721f/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c
+
diff --git a/src/superio/ite/it8721f/chip.h b/src/superio/ite/it8721f/chip.h
new file mode 100644
index 0000000..3de6ca3
--- /dev/null
+++ b/src/superio/ite/it8721f/chip.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) QingPei Wang <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_ITE_IT8721F_CHIP_H
+#define SUPERIO_ITE_IT8721F_CHIP_H
+
+#include <device/device.h>
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_ite_it8721f_ops;
+
+struct superio_ite_it8721f_config {
+	
+	struct pc_keyboard keyboard;
+};
+
+#endif
diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c
new file mode 100644
index 0000000..cf17d0e
--- /dev/null
+++ b/src/superio/ite/it8721f/early_serial.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8721f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE                     0x2e
+#define SIO_INDEX                    SIO_BASE
+#define SIO_DATA                     (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8721F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
+#define IT8721F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
+#define IT8721F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
+#define IT8721F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
+
+static void it8721f_sio_write(u8 ldn, u8 index, u8 value)
+{
+	outb(IT8721F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+static void it8721f_enter_conf(void)
+{
+	u16 port = 0x2e; /* TODO: Don't hardcode! */
+
+	outb(0x87, port);
+	outb(0x01, port);
+	outb(0x55, port);
+	outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8721f_exit_conf(void)
+{
+	it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CC, 0x02);
+}
+
+/* Select 24MHz CLKIN (48MHz default). */
+void it8721f_24mhz_clkin(void)
+{
+	it8721f_enter_conf();
+	it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CLOCKSEL, 0x1);
+	it8721f_exit_conf();
+}
+
+
+/* Enable the serial port(s). */
+void it8721f_enable_serial(device_t dev, u16 iobase)
+{
+	/* (1) Enter the configuration state (MB PnP mode). */
+	it8721f_enter_conf();
+
+	/* (2) Modify the data of configuration registers. */
+
+	/*
+	 * Select the chip to configure (if there's more than one).
+	 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+	 * If this register is not written, both chips are configured.
+	 */
+
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+	/* Enable serial port(s). */
+	it8721f_sio_write(IT8721F_SP1, 0x30, 0x1); /* Serial port 1 */
+	it8721f_sio_write(IT8721F_SP2, 0x30, 0x1); /* Serial port 2 */
+
+	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8721f_exit_conf();
+}
diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h
new file mode 100644
index 0000000..cd68632
--- /dev/null
+++ b/src/superio/ite/it8721f/it8721f.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_ITE_IT8721F_IT8721F_H
+#define SUPERIO_ITE_IT8721F_IT8721F_H
+
+
+
+#define IT8721F_FDC  0x00 /* Floppy */
+#define IT8721F_SP1  0x01 /* Com1 */
+#define IT8721F_SP2  0x02 /* Com2 */
+#define IT8721F_PP   0x03 /* Parallel port */
+#define IT8721F_EC   0x04 /* Environment controller */
+#define IT8721F_KBCK 0x05 /* PS/2 keyboard */
+#define IT8721F_KBCM 0x06 /* PS/2 mouse */
+#define IT8721F_GPIO 0x07 /* GPIO */
+#define IT8721F_IR   0x0a /* Consumer IR */
+
+#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+void it8721f_24mhz_clkin(void);
+void it8721f_disable_reboot(void);
+void it8721f_enable_serial(device_t dev, u16 iobase);
+#endif
+
+#endif
diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c
new file mode 100644
index 0000000..846afef
--- /dev/null
+++ b/src/superio/ite/it8721f/superio.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "it8721f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ite_it8721f_config *conf = dev->chip_info;
+
+	if (!dev->enabled)
+		return;
+
+	switch (dev->path.pnp.device) {
+	case IT8721F_FDC: /* TODO. */
+		break;
+	case IT8721F_PP: /* TODO. */
+		break;
+	case IT8721F_EC: /* TODO. */
+		break;
+	case IT8721F_KBCK:
+		pc_keyboard_init(&conf->keyboard);
+		break;
+	case IT8721F_KBCM: /* TODO. */
+		break;
+	case IT8721F_IR: /* TODO. */
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+/* TODO: FDC, PP, EC, KBCM, IR. */
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, IT8721F_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, IT8721F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
+	{ &ops, IT8721F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8721f_ops = {
+	CHIP_NAME("ITE IT8721F Super I/O")
+	.enable_dev = enable_dev,
+};



From patrick at georgi-clan.de  Tue Sep  6 10:27:27 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 06 Sep 2011 10:27:27 +0200
Subject: [coreboot] FILO managed by Gerrit and Jenkins now,
	also  coreboot patchwork status
In-Reply-To: <CAEVFfeTPShxcmEVujoW4W=4FfK+87EkDEfNM8ZBp5r2Vx4Y6gA@mail.gmail.com>
References: <4E63CA95.1070904@georgi-clan.de>
	<CAEVFfeTPShxcmEVujoW4W=4FfK+87EkDEfNM8ZBp5r2Vx4Y6gA@mail.gmail.com>
Message-ID: <232ccfd754052822f975f031cca95b24@mail.georgi-clan.de>

On Tue, 6 Sep 2011 11:21:39 +0300, Tadas Slotkus wrote:
> Hi,?I would prefer that patch mails have a [FILO] tag instead of
> [coreboot].
That tag is created by the mailing list handler itself. I guess I could 
enhance the mail template a bit, to add the project name at appropriate 
places ("patch added for coreboot" or sth like that).

> Anyways,?great improvement!
Thanks


Patrick



From devtadas at gmail.com  Tue Sep  6 10:21:39 2011
From: devtadas at gmail.com (Tadas Slotkus)
Date: Tue, 6 Sep 2011 11:21:39 +0300
Subject: [coreboot] FILO managed by Gerrit and Jenkins now,
 also coreboot patchwork status
In-Reply-To: <4E63CA95.1070904@georgi-clan.de>
References: <4E63CA95.1070904@georgi-clan.de>
Message-ID: <CAEVFfeTPShxcmEVujoW4W=4FfK+87EkDEfNM8ZBp5r2Vx4Y6gA@mail.gmail.com>

>
> FILO is now managed by Gerrit, using Jenkins for build-testing it. It uses
> the latest libpayload of coreboot to validate that things work.
>

Hi, I would prefer that patch mails have a [FILO] tag instead of [coreboot].
Anyways, great improvement!

Thanks,
Tadas
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From xdrudis at tinet.cat  Tue Sep  6 14:13:35 2011
From: xdrudis at tinet.cat (Xavi Drudis Ferran)
Date: Tue, 06 Sep 2011 14:13:35 +0200
Subject: [coreboot] [off-topic] Treacherous computing in Windows 8 ?
Message-ID: <43537.1315311215@tinet.org>

Sorry for the noise. I just read this and haven't really analized it.
It looks like more of the same trend of locking down the software 
users can use by checking signatures in the boot loader. 
What I haven't researched is whether that will imply also that
firmware needs to be signed, where will the truststores be (so who will
control what software can run) or whether "secure" hardware will 
be very popular in the market or just a failed attempt at seizing power, or 
whether this will divide options into only two : open hardware with free software 
or closed hardware with propietary preapproved telecontrolled software. 


Heise: Windows 8 to include secure boot using UEFI 2.3.1
http://www.h-online.com/security/news/item/Windows-8-to-include-secure-boot-using-UEFI-2-3-1-1335246.html
(I think there's a German version too)




From gerrit at coreboot.org  Tue Sep  6 15:12:21 2011
From: gerrit at coreboot.org (QingPei Wang (wangqingpei@gmail.com))
Date: Tue, 6 Sep 2011 15:12:21 +0200
Subject: [coreboot] New patch to review for coreboot: deb6f0f Add ASUS
	M5A88-V mainboard support
References: <I9725ccdbb25365c4007621318efee80b131fec29+0@gerrit.coreboot.org>
Message-ID: <I9725ccdbb25365c4007621318efee80b131fec29+1@gerrit.coreboot.org>

QingPei Wang (wangqingpei at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/205

-gerrit

commit deb6f0f225bddd2fa786f94689555a21add12d13
Author: QingPei Wang <wangqingpei at gmail.com>
Date:   Tue Sep 6 21:09:40 2011 +0800

    Add ASUS M5A88-V mainboard support
    
    it's a AMD 880+800 mainboard. I port the code
    based on the AMD reference code.
    
    Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
    Signed-off-by: QingPei Wang <wangqingpei at gmail.com>
---
 src/mainboard/asus/Kconfig                  |    3 +
 src/mainboard/asus/m5a88-v/Kconfig          |  107 ++
 src/mainboard/asus/m5a88-v/Makefile.inc     |   20 +
 src/mainboard/asus/m5a88-v/acpi/cpstate.asl |   75 ++
 src/mainboard/asus/m5a88-v/acpi/ide.asl     |  244 ++++
 src/mainboard/asus/m5a88-v/acpi/routing.asl |  398 ++++++
 src/mainboard/asus/m5a88-v/acpi/sata.asl    |  149 +++
 src/mainboard/asus/m5a88-v/acpi/usb.asl     |  161 +++
 src/mainboard/asus/m5a88-v/acpi_tables.c    |  274 ++++
 src/mainboard/asus/m5a88-v/chip.h           |   22 +
 src/mainboard/asus/m5a88-v/cmos.layout      |   98 ++
 src/mainboard/asus/m5a88-v/devicetree.cb    |  124 ++
 src/mainboard/asus/m5a88-v/dsdt.asl         | 1824 +++++++++++++++++++++++++++
 src/mainboard/asus/m5a88-v/fadt.c           |  201 +++
 src/mainboard/asus/m5a88-v/get_bus_conf.c   |  147 +++
 src/mainboard/asus/m5a88-v/irq_tables.c     |  111 ++
 src/mainboard/asus/m5a88-v/mainboard.c      |  150 +++
 src/mainboard/asus/m5a88-v/mb_sysconf.h     |   43 +
 src/mainboard/asus/m5a88-v/mptable.c        |  160 +++
 src/mainboard/asus/m5a88-v/pmio.c           |   53 +
 src/mainboard/asus/m5a88-v/pmio.h           |   33 +
 src/mainboard/asus/m5a88-v/reset.c          |   63 +
 src/mainboard/asus/m5a88-v/resourcemap.c    |  278 ++++
 src/mainboard/asus/m5a88-v/romstage.c       |  280 ++++
 24 files changed, 5018 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig
index 875fd5a..77b7997 100644
--- a/src/mainboard/asus/Kconfig
+++ b/src/mainboard/asus/Kconfig
@@ -37,6 +37,8 @@ config BOARD_ASUS_M4A785M
 	bool "M4A785-M"
 config BOARD_ASUS_M4A78_EM
 	bool "M4A78-EM"
+config BOARD_ASUS_M5A88_V
+	bool "M5A88-V"
 config BOARD_ASUS_MEW_AM
 	bool "MEW-AM"
 config BOARD_ASUS_MEW_VM
@@ -64,6 +66,7 @@ source "src/mainboard/asus/m2v/Kconfig"
 source "src/mainboard/asus/m2v-mx_se/Kconfig"
 source "src/mainboard/asus/m4a785-m/Kconfig"
 source "src/mainboard/asus/m4a78-em/Kconfig"
+source "src/mainboard/asus/m5a88-v/Kconfig"
 source "src/mainboard/asus/mew-am/Kconfig"
 source "src/mainboard/asus/mew-vm/Kconfig"
 source "src/mainboard/asus/p2b/Kconfig"
diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig
new file mode 100644
index 0000000..48a1fe3
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/Kconfig
@@ -0,0 +1,107 @@
+if BOARD_ASUS_M5A88_V
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_SOCKET_AM3
+	select DIMM_DDR3
+	select DIMM_REGISTERED
+	select QRANK_DIMM_SUPPORT
+	select NORTHBRIDGE_AMD_AMDFAM10
+	select SOUTHBRIDGE_AMD_RS780
+	select SOUTHBRIDGE_AMD_CIMX_SB800
+	select SUPERIO_ITE_IT8721F 
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select AMDMCT
+	select HAVE_MP_TABLE
+	select HAVE_ACPI_TABLES
+	select BOARD_HAS_FADT
+	select GENERATE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_2048
+	select RAMINIT_SYSINFO
+	select ENABLE_APIC_EXT_ID
+	select TINY_BOOTBLOCK
+	select GFXUMA
+	select HAVE_DEBUG_CAR
+	select SET_FIDVID
+
+config AMD_CIMX_SB800
+        bool
+        default y
+
+config MAINBOARD_DIR
+	string
+	default asus/m5a88-v
+
+config APIC_ID_OFFSET
+	hex
+	default 0x0
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "M5A88PM-V"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+
+config MEM_TRAIN_SEQ
+	int
+	default 2
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x1
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config AMD_UCODE_PATCH_FILE
+	string
+	default "mc_patch_010000bf.h"
+
+config RAMTOP
+	hex
+	default 0x2000000
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+config RAMBASE
+	hex
+	default 0x200000
+
+config VGA_BIOS_ID
+        string
+        default "1002,9715"
+
+endif #BOARD_ASUS_M5A88_V
diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc
new file mode 100644
index 0000000..cf8ec26
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/Makefile.inc
@@ -0,0 +1,20 @@
+#romstage-y += reset.c #FIXME romstage have include test_rest.c
+romstage-y += pmio.c
+
+ramstage-y += reset.c
+ramstage-y += pmio.c
+
+#SB800 CIMx share AGESA V5 lib code
+ifneq ($(CONFIG_AMD_AGESA),y)
+ AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+ romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+ ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+
+ AGESA_INC := -I$(AGESA_ROOT)/ \
+	      -I$(AGESA_ROOT)/Include \
+	      -I$(AGESA_ROOT)/Proc/IDS/ \
+	      -I$(AGESA_ROOT)/Proc/CPU/ \
+	      -I$(AGESA_ROOT)/Proc/CPU/Family
+
+ CFLAGS += $(AGESA_INC)
+endif
diff --git a/src/mainboard/asus/m5a88-v/acpi/cpstate.asl b/src/mainboard/asus/m5a88-v/acpi/cpstate.asl
new file mode 100644
index 0000000..5eca9cc
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}
diff --git a/src/mainboard/asus/m5a88-v/acpi/ide.asl b/src/mainboard/asus/m5a88-v/acpi/ide.asl
new file mode 100644
index 0000000..c79c18c
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}
diff --git a/src/mainboard/asus/m5a88-v/acpi/routing.asl b/src/mainboard/asus/m5a88-v/acpi/routing.asl
new file mode 100644
index 0000000..cb50394
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/acpi/routing.asl
@@ -0,0 +1,398 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+
+		Package(){0x0009FFFF, 0, INTB, 0 },
+		Package(){0x0009FFFF, 1, INTC, 0 },
+		Package(){0x0009FFFF, 2, INTD, 0 },
+		Package(){0x0009FFFF, 3, INTA, 0 },
+
+		Package(){0x000AFFFF, 0, INTC, 0 },
+		Package(){0x000AFFFF, 1, INTD, 0 },
+		Package(){0x000AFFFF, 2, INTA, 0 },
+		Package(){0x000AFFFF, 3, INTB, 0 },
+
+		Package(){0x000BFFFF, 0, INTD, 0 },
+		Package(){0x000BFFFF, 1, INTA, 0 },
+		Package(){0x000BFFFF, 2, INTB, 0 },
+		Package(){0x000BFFFF, 3, INTC, 0 },
+
+		Package(){0x000CFFFF, 0, INTA, 0 },
+		Package(){0x000CFFFF, 1, INTB, 0 },
+		Package(){0x000CFFFF, 2, INTC, 0 },
+		Package(){0x000CFFFF, 3, INTD, 0 },
+
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		Package(){0x0016FFFF, 1, INTB, 0 },
+
+		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+
+		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, 0, 18 },
+		package(){0x0001FFFF, 1, 0, 19 },
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, 0, 17 }, */
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Package(){0x0006FFFF, 0, 0, 18 }, */
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Package(){0x0007FFFF, 0, 0, 19 }, */
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Dev 9 - PCIe Bridge for network card */
+		Package(){0x0009FFFF, 0, 0, 17 },
+		/* Package(){0x0009FFFF, 1, 0, 16 }, */
+		/* Package(){0x0009FFFF, 2, 0, 17 }, */
+		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		/* Bus 0, Dev A - PCIe Bridge for network card */
+		Package(){0x000AFFFF, 0, 0, 18 },
+		/* Package(){0x000AFFFF, 1, 0, 16 }, */
+		/* Package(){0x000AFFFF, 2, 0, 17 }, */
+		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, 0, 18 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		/* Package(){0x0012FFFF, 2, 0, 18 }, */
+
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+		/* Package(){0x0013FFFF, 2, 0, 16 }, */
+
+		/* Package(){0x00140000, 0, 0, 16 }, */
+
+		Package(){0x0016FFFF, 0, 0, 18 },
+		Package(){0x0016FFFF, 1, 0, 17 },
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+
+		/* TODO: pcie */
+		Package(){0x0015FFFF, 0, 0, 16 },
+		Package(){0x0015FFFF, 1, 0, 17 },
+		Package(){0x0015FFFF, 2, 0, 18 },
+		Package(){0x0015FFFF, 3, 0, 19 },
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+	Name(APR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE0, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APE0, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PE1, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APE1, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PE2, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APE2, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE3, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APE3, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+		Package(){0x0007FFFF, 0, 0, 0x16 },
+		Package(){0x0007FFFF, 1, 0, 0x17 },
+		Package(){0x0007FFFF, 2, 0, 0x14 },
+		Package(){0x0007FFFF, 3, 0, 0x15 },
+	})
+}
diff --git a/src/mainboard/asus/m5a88-v/acpi/sata.asl b/src/mainboard/asus/m5a88-v/acpi/sata.asl
new file mode 100644
index 0000000..bd4acf0
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00110000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}
diff --git a/src/mainboard/asus/m5a88-v/acpi/usb.asl b/src/mainboard/asus/m5a88-v/acpi/usb.asl
new file mode 100644
index 0000000..181d685
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/acpi/usb.asl
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "usb.asl"
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+    	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+	Scope (\_GPE) {
+		Method (_L1A) {
+			UCOC()
+			if (LEqual(GPB5,PLC5)) {
+				Not(PLC5,PLC5)
+				Store(PLC5, \_SB.PT5D)
+			}
+		}
+	}
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ 	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}
diff --git a/src/mainboard/asus/m5a88-v/acpi_tables.c b/src/mainboard/asus/m5a88-v/acpi_tables.c
new file mode 100644
index 0000000..7c8ca76
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/acpi_tables.c
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+#include "mb_sysconf.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+extern const unsigned char AmlCode_ssdt2[];
+extern const unsigned char AmlCode_ssdt3[];
+extern const unsigned char AmlCode_ssdt4[];
+extern const unsigned char AmlCode_ssdt5[];
+#endif
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+	acpi_header_t *ssdtx;
+	void *p;
+	int i;
+#endif
+
+	get_bus_conf();	/* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	/* SLIT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdp, slit);
+
+	/* SSDT */
+	current	  = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)current;
+	memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+	current += ssdt->length;
+	memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+	//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
+	update_ssdt((void*)ssdt);
+	/* recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	current = acpi_add_ssdt_pstates(rsdp, current);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+
+	/* same htio, but different position? We may have to copy,
+	change HCIN, and recalculate the checknum and add_table */
+
+	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+		if((sysconf.pci1234[i] & 1) != 1 ) continue;
+		u8 c;
+		if (i < 7) {
+			c = (u8) ('4' + i - 1);
+		} else {
+			c = (u8) ('A' + i - 1 - 6);
+		}
+		current	  = ( current + 0x07) & -0x08;
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
+		ssdtx = (acpi_header_t *)current;
+		switch (sysconf.hcid[i]) {
+		case 1:
+			p = &AmlCode_ssdt2;
+			break;
+		case 2:
+			p = &AmlCode_ssdt3;
+			break;
+		case 3:	/* 8131 */
+			p = &AmlCode_ssdt4;
+			break;
+		default:
+			/* HTX no io apic */
+			p = &AmlCode_ssdt5;
+			break;
+		}
+		memcpy(ssdtx, p, sizeof(acpi_header_t));
+		current += ssdtx->length;
+		memcpy(ssdtx, p, ssdtx->length);
+		update_ssdtx((void *)ssdtx, i);
+		ssdtx->checksum = 0;
+		ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
+		acpi_add_table(rsdp, ssdtx);
+	}
+#endif
+
+	/* DSDT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FDAT */
+#if CONFIG_BOARD_HAS_FADT == 1
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+#endif
+
+#if DUMP_ACPI_TABLES == 1
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/asus/m5a88-v/chip.h b/src/mainboard/asus/m5a88-v/chip.h
new file mode 100644
index 0000000..d5b991d
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/chip.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/asus/m5a88-v/cmos.layout b/src/mainboard/asus/m5a88-v/cmos.layout
new file mode 100644
index 0000000..53fdef5
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/cmos.layout
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/asus/m5a88-v/devicetree.cb b/src/mainboard/asus/m5a88-v/devicetree.cb
new file mode 100644
index 0000000..06e56cd
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/devicetree.cb
@@ -0,0 +1,124 @@
+# sample config for advansus/A785E-I
+chip northbridge/amd/amdfam10/root_complex
+	device lapic_cluster 0 on
+		chip cpu/amd/socket_AM3  #L1 and DDR3
+			 device lapic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id.
+		chip northbridge/amd/amdfam10
+			device pci 18.0 on #  northbridge
+				chip southbridge/amd/rs780
+					device pci 0.0 on end # HT  	0x9600
+					device pci 1.0 on end # Internal Graphics P2P bridge 0x9712
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
+					device pci 3.0 off end # PCIE P2P bridge 0x960b
+					device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless
+					device pci 5.0 off end # PCIE P2P bridge 0x9605
+					device pci 6.0 off end # PCIE P2P bridge 0x9606
+					device pci 7.0 off end # PCIE P2P bridge 0x9607
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					device pci 9.0 on end # Ethernet
+					device pci a.0 on end # Ethernet
+					register "gppsb_configuration" = "4"	# Configuration E
+					register "gpp_configuration" = "3"	# Configuration D
+					register "port_enable" = "0x6f6"
+					register "gfx_dev2_dev3" = "0"
+					register "gfx_dual_slot" = "0"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+					register "gfx_tmds" = "1"
+					register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
+					register "gfx_ddi_config" = "1"  # Lanes 0-3 DDI_SL
+				end
+				chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.2 on end # USB
+	 				device pci 14.0 on # SM
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x439c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on
+                                                chip superio/ite/it8721f
+                                                        device pnp 2e.0 off #  Floppy
+                                                                io 0x60 = 0x3f0
+                                                                irq 0x70 = 6
+                                                                drq 0x74 = 2
+                                                        end
+                                                        device pnp 2e.1 off #  Parallel Port
+                                                                io 0x60 = 0x378
+                                                                irq 0x70 = 7
+                                                        end
+                                                        device pnp 2e.2 on #  Com1
+                                                                io 0x60 = 0x3f8
+                                                                irq 0x70 = 4
+                                                        end
+                                                        device pnp 2e.3 on #  Com2
+                                                                io 0x60 = 0x2f8
+                                                                irq 0x70 = 3
+                                                        end
+                                                        device pnp 2e.5 on #  Keyboard
+                                                                io 0x60 = 0x60
+                                                                io 0x62 = 0x64
+                                                                irq 0x70 = 1
+                                                                irq 0x72 = 12
+                                                        end
+                                                        device pnp 2e.6 off  # SFI
+                                                                io 0x62 = 0x100
+                                                        end
+                                                        device pnp 2e.7 off #  GPIO_GAME_MIDI
+                                                                io 0x60 = 0x220
+                                                                io 0x62 = 0x300
+                                                                irq 0x70 = 9
+                                                        end
+                                                        device pnp 2e.8 off end #  WDTO_PLED
+                                                        device pnp 2e.9 off end #  GPIO_SUSLED
+                                                        device pnp 2e.a off end #  ACPI
+                                                        device pnp 2e.b on #  HW Monitor
+                                                                io 0x60 = 0x290
+                                                                irq 0x70 = 5
+                                                        end
+                                                end     #superio/winbond/w83627hf
+					end # LPC	0x439d
+					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+					device pci 14.5 on end # USB 2
+					device pci 14.6 off end # Gec
+					device pci 15.0 on end # PCIe 0
+					device pci 15.1 on end # PCIe 1
+					device pci 15.2 on end # PCIe 2
+					device pci 15.3 on end # PCIe 3
+					device pci 16.0 on end # USB
+					device pci 16.2 on end # USB
+					#register "gpp_configuration" = "0" #4:0:0:0
+					#register "gpp_configuration" = "2" #2:2:0:0
+					#register "gpp_configuration" = "3" #2:1:1:0
+					register "gpp_configuration" = "4" #1:1:1:1
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				end	#southbridge/amd/cimx/sb800
+			end #  device pci 18.0
+
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+		end
+	end #pci_domain
+end
diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl
new file mode 100644
index 0000000..b9a699b
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/dsdt.asl
@@ -0,0 +1,1824 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"ASUS    ",               /* OEMID */
+	"M5A88   ",	     /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include "../../../arch/x86/acpi/debug.asl" */		/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			CPU0,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU1,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU2,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU3,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+	} /* End _PR scope */
+
+	/* PIC IRQ mapping registers, C00h-C01h. */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PIRA, 0x00000008,	/* Index 0 */
+		PIRB, 0x00000008,	/* Index 1 */
+		PIRC, 0x00000008,	/* Index 2 */
+		PIRD, 0x00000008,	/* Index 3 */
+		PIRE, 0x00000008,	/* Index 4 */
+		PIRF, 0x00000008,	/* Index 5 */
+		PIRG, 0x00000008,	/* Index 6 */
+		PIRH, 0x00000008,	/* Index 7 */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk. TODO: should be 0x60 */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve){
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+
+	#include "acpi/routing.asl"
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+		Method(CIRQ, 0x00, NotSerialized){
+			Store(0, PIRA)
+			Store(0, PIRB)
+			Store(0, PIRC)
+			Store(0, PIRD)
+			Store(0, PIRE)
+			Store(0, PIRF)
+			Store(0, PIRG)
+			Store(0, PIRH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PIRA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PIRA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PIRB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PIRB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PIRC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PIRC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIRD) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIRD)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRD, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRD)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PIRE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PIRE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PIRF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PIRF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PIRG) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PIRG)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRG, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRG)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PIRH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PIRH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			/* Notify (\_TZ.TZ00, 0x80) */
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event - Moved to USB.asl */
+		/* Method(_L1A) {
+		*	DBGO("\\_GPE\\_L1A\n")
+		* }
+		*/
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	#include "acpi/usb.asl"
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			External (TOM1)
+			External (TOM2)
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+			/* GPP */
+			Device(PBR9) {
+				Name(_ADR, 0x00090000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS9) }   /* APIC mode */
+					Return (PS9)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR9 */
+
+			Device(PBRa) {
+				Name(_ADR, 0x000A0000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APSa) }   /* APIC mode */
+					Return (PSa)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBRa */
+
+			Device(PE20) {
+				Name(_ADR, 0x00150000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE0) }   /* APIC mode */
+					Return (PE0)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE20 */
+			Device(PE21) {
+				Name(_ADR, 0x00150001)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE1) }   /* APIC mode */
+					Return (PE1)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE21 */
+			Device(PE22) {
+				Name(_ADR, 0x00150002)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE2) }   /* APIC mode */
+					Return (APE2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE22 */
+			Device(PE23) {
+				Name(_ADR, 0x00150003)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE3) }   /* APIC mode */
+					Return (PE3)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE23 */
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00110000)
+				#include "acpi/sata.asl"
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00120000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00120002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00160000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UOH6) {
+				Name(_ADR, 0x00160002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00140005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				#include "acpi/ide.asl"
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#if 0
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#endif
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* length */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+#if 0
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/*  Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/*  Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+#endif
+                                /* memory space for PCI BARs below 4GB */
+                                Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+#if 0
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM1, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	Subtract(TOM2, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+#endif
+                                CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+                                CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+                                /*
+                                 * Declare memory between TOM1 and 4GB as available
+                                 * for PCI MMIO.
+                                 * Use ShiftLeft to avoid 64bit constant (for XP).
+                                 * This will work even if the OS does 32bit arithmetic, as
+                                 * 32bit (0x00000000 - TOM1) will wrap and give the same
+                                 * result as 64bit (0x100000000 - TOM1).
+                                 */
+                                Store(TOM1, MM1B)
+                                ShiftLeft(0x10000000, 4, Local0)
+                                Subtract(Local0, TOM1, Local0)
+                                Store(Local0, MM1L)
+
+				Return(CRES) /* note to change the Name buffer */
+			}  /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+#if 0
+	/* SMBUS Support */
+	Mutex (SBX0, 0x00)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x10, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+			If (LEqual (Local0, Zero)) {
+				Release (SBX0)
+				Return (0x0)
+			}
+
+			Store (0x1F, HSTS)
+			Store (Or (ShiftLeft (Arg1, One), One), HADD)
+			Store (Arg2, HCMD)
+			If (LEqual (Arg0, 0x07)) {
+				Store (0x48, HCNT) /* read byte */
+			}
+
+			Store (SWTC (0x03E8), Local1) /* 1000 ms */
+			If (LEqual (Local1, Zero)) {
+				If (LEqual (Arg0, 0x07)) {
+					Store (DAT0, Local0)
+				}
+			}
+			Else {
+				Store (Local1, Local0)
+			}
+
+			Release (SBX0)
+		}
+
+		/* DBGO("the value of SMBusData0 register ") */
+		/* DBGO(Arg2) */
+		/* DBGO(" is ") */
+		/* DBGO(Local0) */
+		/* DBGO("\n") */
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 2732)
+		Name (THOT, 800)
+		Name (TCRT, 850)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+				If (LGreater (Local0, 0x10)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400, KELV))
+				}
+
+				Store (SMBR (0x07, 0x4C, 0x01), Local0)
+				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+				If (LGreater (Local0, 0x10)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Multiply (Local1, 10, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+#endif
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/m5a88-v/fadt.c b/src/mainboard/asus/m5a88-v/fadt.c
new file mode 100644
index 0000000..53540e7
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/fadt.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "pmio.h"
+
+/*extern*/ u16 pm_base = 0x800;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of rs780. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+#define ACPI_PM_EVT_BLK		(pm_base + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK	(pm_base + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK	(pm_base + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK		(pm_base + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK		(pm_base + 0x10) /* 8 bytes */
+#define ACPI_CPU_CONTORL	(pm_base + 0x08) /* 6 bytes */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	pm_base &= 0xFFFF;
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
+	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
+	pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
+	pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
+	pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
+	pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
+	pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
+	pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+
+	/* CpuControl is in \_PR.CPU0, 6 bytes */
+	pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
+	pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
+
+	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
+	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
+
+	pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
+	pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+
+	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
+					* the contents of the PM registers at
+					* index 60-6B to decode ACPI I/O address.
+					* AcpiSmiEn & SmiCmdEn*/
+	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
+
+	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}
diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c
new file mode 100644
index 0000000..2a3f70b
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/multicore.h>
+#endif
+#include <cpu/amd/amdfam10_sysconf.h>
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+int bus_isa;
+u8 bus_rs780[11];
+u8 bus_sb800[3];
+u32 apicid_sb800;
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+	0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+	0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_rs780;
+u32 sbdn_sb800;
+
+extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+	u32 apicid_base;
+	device_t dev;
+	int i, j;
+
+	if (get_bus_conf_done == 1)
+		return;		/* do it only once */
+	get_bus_conf_done = 1;
+
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+	for (i = 0; i < sysconf.hc_possible_num; i++) {
+		sysconf.pci1234[i] = pci1234x[i];
+		sysconf.hcdn[i] = hcdnx[i];
+	}
+
+	get_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
+	sbdn_rs780 = sysconf.sbdn;
+	sbdn_sb800 = 0;
+
+	for (i = 0; i < 3; i++) {
+		bus_sb800[i] = 0;
+	}
+	for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
+		bus_rs780[i] = 0;
+	}
+
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+	bus_type[0] = 1;	/* pci */
+
+	bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb800[0] = bus_rs780[0];
+
+	bus_type[bus_rs780[0]] = 1;
+
+	/* sb800 */
+	dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+	if (dev) {
+		bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb800[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	for (i = 0; i < 4; i++) {
+		dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x15, i));
+		if (dev) {
+			bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+			bus_isa++;
+		}
+	}
+	for (j = bus_sb800[2]; j < bus_isa; j++)
+		bus_type[j] = 1;
+
+	/* rs780 */
+	for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
+		dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
+		if (dev) {
+			bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			if(255 != bus_rs780[i]) {
+				bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+				bus_isa++;
+				bus_type[bus_rs780[i]] = 1; /* PCI bus. */
+			}
+		}
+	}
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+	apicid_sb800 = apicid_base + 0;
+}
diff --git a/src/mainboard/asus/m5a88-v/irq_tables.c b/src/mainboard/asus/m5a88-v/irq_tables.c
new file mode 100644
index 0000000..fd74e3a
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/irq_tables.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			    u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+
+extern u8 bus_isa;
+extern u8 bus_rs780[8];
+extern u8 bus_sb800[2];
+extern unsigned long sbdn_sb800;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb800[0];
+	pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+	slot_num++;
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
new file mode 100644
index 0000000..534c71c
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -0,0 +1,150 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "pmio.h"
+#include "chip.h"
+
+uint64_t uma_memory_base, uma_memory_size;
+
+u8 is_dev3_present(void);
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+void enable_int_gfx(void);
+
+/* GPIO6. */
+void enable_int_gfx(void)
+{
+	u8 byte;
+
+	volatile u8 *gpio_reg;
+
+	pm_iowrite(0xEA, 0x01);	/* diable the PCIB */
+	/* Disable Gec */
+	byte = pm_ioread(0xF6);
+	byte |= 1;
+	pm_iowrite(0xF6, byte);
+	/* make sure the fed80000 is accessible */
+	byte = pm_ioread(0x24);
+	byte |= 1;
+	pm_iowrite(0x24, byte);
+
+	gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
+
+	*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
+	*(gpio_reg + 170) = 0x1; /* gpio_gate */
+
+	gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
+
+	*(gpio_reg + 0x6) = 0x8;
+	*(gpio_reg + 170) = 0x0;
+}
+
+void set_pcie_dereset()
+{
+}
+
+void set_pcie_reset(void)
+{
+}
+
+u8 is_dev3_present(void)
+{
+	return 0;
+}
+
+
+/*************************************************
+* enable the dedicated function in M5A88-V board.
+* This function called early than rs780_enable.
+*************************************************/
+static void m5a88pm_v_enable(device_t dev)
+{
+
+	printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev);
+
+#if (CONFIG_GFXUMA == 1)
+	msr_t msr, msr2;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	/* refer to UMA Size Consideration in 780 BDG. */
+	switch (msr.lo) {
+	case 0x10000000:	/* 256M system memory */
+		uma_memory_size = 0x4000000;	/* 64M recommended UMA */
+		break;
+
+	case 0x20000000:	/* 512M system memory */
+		uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+		break;
+
+	default:		/* 1GB and above system memory */
+		uma_memory_size = 0x10000000;	/* 256M recommended UMA */
+		break;
+	}
+
+	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+		    __func__, uma_memory_size, uma_memory_base);
+
+	/* TODO: TOP_MEM2 */
+#else
+	uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+	uma_memory_base = 0x38000000;	/* 1GB  system memory supposed */
+#endif
+
+	set_pcie_dereset();
+	enable_int_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	/* UMA is removed from system memory in the northbridge code, but
+	 * in some circumstances we want the memory mentioned as reserved.
+ 	 */
+#if (CONFIG_GFXUMA == 1)
+	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+		    uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+			    uma_memory_size);
+#endif
+	return 0;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("ASUS M5A88-V Mainboard")
+	.enable_dev = m5a88pm_v_enable,
+};
diff --git a/src/mainboard/asus/m5a88-v/mb_sysconf.h b/src/mainboard/asus/m5a88-v/mb_sysconf.h
new file mode 100644
index 0000000..ca5870c
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/mb_sysconf.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+	u8 bus_isa;
+	u8 bus_8132_0;
+	u8 bus_8132_1;
+	u8 bus_8132_2;
+	u8 bus_8111_0;
+	u8 bus_8111_1;
+	u8 bus_8132a[31][3];
+	u8 bus_8151[31][2];
+
+	u32 apicid_8111;
+	u32 apicid_8132_1;
+	u32 apicid_8132_2;
+	u32 apicid_8132a[31][2];
+	u32 sbdn3;
+	u32 sbdn3a[31];
+	u32 sbdn5[31];
+	u32 bus_type[256];
+};
+
+#endif
diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c
new file mode 100644
index 0000000..dc76b81
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/mptable.c
@@ -0,0 +1,160 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include "pmio.h"
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern int bus_isa;
+extern u8 bus_rs780[11];
+extern u8 bus_sb800[2];
+extern u32 apicid_sb800;
+extern u32 bus_type[256];
+extern u32 sbdn_rs780;
+extern u32 sbdn_sb800;
+
+u8 intr_data[] = {
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
+};
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	u32 dword;
+	u8 byte;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LAPIC_ADDR);
+
+	smp_write_processors(mc);
+
+	get_bus_conf();
+
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/* I/O APICs:   APIC ID Version State   Address */
+
+	dword = 0;
+	dword = pm_ioread(0x34) & 0xF0;
+	dword |= (pm_ioread(0x35) & 0xFF) << 8;
+	dword |= (pm_ioread(0x36) & 0xFF) << 16;
+	dword |= (pm_ioread(0x37) & 0xFF) << 24;
+	smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#if CONFIG_GENERATE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
+
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);
+
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+	/* on board NIC & Slot PCIE.  */
+	/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
+/* 	PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
+	PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
+	/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
+	PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
+	/* configuration B doesnt need dev 5,6,7 */
+	/*
+	 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
+	 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
+	 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
+	 */
+	PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
+	PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum =
+	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+		     mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/m5a88-v/pmio.c b/src/mainboard/asus/m5a88-v/pmio.c
new file mode 100644
index 0000000..aa4e61e
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/pmio.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "pmio.h"
+
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
+{
+	outb(reg, port_base);
+	outb(value, port_base + 1);
+}
+
+static u8 pmio_read_index(u16 port_base, u8 reg)
+{
+	outb(reg, port_base);
+	return inb(port_base + 1);
+}
+
+void pm_iowrite(u8 reg, u8 value)
+{
+	pmio_write_index(PM_INDEX, reg, value);
+}
+
+u8 pm_ioread(u8 reg)
+{
+	return pmio_read_index(PM_INDEX, reg);
+}
+
+void pm2_iowrite(u8 reg, u8 value)
+{
+	pmio_write_index(PM2_INDEX, reg, value);
+}
+
+u8 pm2_ioread(u8 reg)
+{
+	return pmio_read_index(PM2_INDEX, reg);
+}
diff --git a/src/mainboard/asus/m5a88-v/pmio.h b/src/mainboard/asus/m5a88-v/pmio.h
new file mode 100644
index 0000000..78ab6e9
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/pmio.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _PMIO_H_
+#define _PMIO_H_
+
+#define PM_INDEX	0xCD6
+#define PM_DATA		0xCD7
+#define PM2_INDEX	0xCD0
+#define PM2_DATA	0xCD1
+
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+#endif
diff --git a/src/mainboard/asus/m5a88-v/reset.c b/src/mainboard/asus/m5a88-v/reset.c
new file mode 100644
index 0000000..5212b3a
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/reset.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes, htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for (i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c
new file mode 100644
index 0000000..06102b0
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/resourcemap.c
@@ -0,0 +1,278 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration regin i
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+	};
+
+	int max;
+	max = ARRAY_SIZE(register_values);
+	setup_resource_map(register_values, max);
+}
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
new file mode 100644
index 0000000..6971bde
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -0,0 +1,280 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+//#define SYSTEM_TYPE 0	/* SERVER */
+#define SYSTEM_TYPE 1	/* DESKTOP */
+//#define SYSTEM_TYPE 2	/* MOBILE */
+
+//used by incoherent_ht
+#define FAM10_SCAN_PCI_BUS 0
+#define FAM10_ALLOCATE_IO_RANGE 0
+
+#include <lib.h>
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <cpu/amd/model_10xxx_rev.h>
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdfam10/reset_test.c"
+#include <console/loglevel.h>
+#include "cpu/x86/bist.h"
+#include "superio/ite/it8721f/early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include <SbEarly.h>
+#include <SBPLATFORM.h> /* SB OEM constants */
+#include <southbridge/amd/cimx/sb800/smbus.h>
+#include "northbridge/amd/amdfam10/debug.c"
+
+static void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+static int spd_read_byte(u32 device, u32 address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/pci.c"
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#if CONFIG_UPDATE_CPU_MICROCODE
+#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "northbridge/amd/amdfam10/early_ht.c"
+#include "spd.h"
+
+#include <reset.h>
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
+//FIXME copyed from sb800
+#include <pmio.h>
+static void sb800_clk_output_48Mhz(void)
+{
+        /* AcpiMMioDecodeEn */
+        u8 reg8;
+        reg8 = pm_ioread(0x24);
+        reg8 |= 1;
+        reg8 &= ~(1 << 1);
+        pm_iowrite(0x24, reg8);
+
+        *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+        *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
+}
+#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
+	u32 bsp_apicid = 0, val;
+	msr_t msr;
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		/* mov bsp to bus 0xff when > 8 nodes */
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		//enable port80 decoding and southbridge poweron init
+		sb_poweron_init();
+	}
+
+	post_code(0x30);
+
+	if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
+		/* All cores run this but the BSP(node0,core0) is the only core that returns. */
+	}
+
+	post_code(0x32);
+
+	enable_rs780_dev8();
+	sb800_clk_output_48Mhz();
+
+	/* w83627hf_set_clksel_48(PNP_DEV(0x2e, 0)); */
+	/* w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); */
+	it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+	printk(BIOS_DEBUG, "\n");
+
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+	printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	/* Setup sysinfo defaults */
+	set_sysinfo_in_ram(0);
+
+#if CONFIG_UPDATE_CPU_MICROCODE
+	update_microcode(val);
+#endif
+	post_code(0x33);
+
+	cpuSetAMDMSR();
+	post_code(0x34);
+
+	amd_ht_init(sysinfo);
+	post_code(0x35);
+
+	/* Setup nodes PCI space and start core 0 AP init. */
+	finalize_node_setup(sysinfo);
+
+	/* Setup any mainboard PCI settings etc. */
+	setup_mb_resource_map();
+	post_code(0x36);
+
+	/* wait for all the APs core0 started by finalize_node_setup. */
+	/* FIXME: A bunch of cores are going to start output to serial at once.
+	   It would be nice to fixup prink spinlocks for ROM XIP mode.
+	   I think it could be done by putting the spinlock flag in the cache
+	   of the BSP located right after sysinfo.
+	 */
+	wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* Core0 on each node is configured. Now setup any additional cores. */
+	printk(BIOS_DEBUG, "start_other_cores()\n");
+	start_other_cores();
+	post_code(0x37);
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+
+	post_code(0x38);
+
+	/* run _early_setup before soft-reset. */
+	rs780_early_setup();
+
+#if CONFIG_SET_FIDVID == 1
+	msr = rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	post_code(0x39);
+
+	if (!warm_reset_detect(0)) {			// BSP is node 0
+		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+	} else {
+		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
+	}
+
+	post_code(0x3A);
+
+	/* show final fid and vid */
+	msr=rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+#endif
+
+	rs780_htinit();
+
+	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	if (!warm_reset_detect(0)) {
+		print_info("...WARM RESET...\n\n\n");
+		soft_reset();
+		die("After soft_reset_x - shouldn't see this message!!!\n");
+	}
+
+	post_code(0x3B);
+
+	/* It's the time to set ctrl in sysinfo now; */
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+	post_code(0x40);
+
+//	die("Die Before MCT init.");
+
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
+	raminit_amdmct(sysinfo);
+	post_code(0x41);
+
+/*
+	dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
+*/
+
+//	ram_check(0x00200000, 0x00200000 + (640 * 1024));
+//	ram_check(0x40200000, 0x40200000 + (640 * 1024));
+
+//	die("After MCT init before CAR disabled.");
+
+	rs780_before_pci_init();
+
+	post_code(0x42);
+	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
+	post_code(0x43);	// Should never see this post code.
+}
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+
+	return 0;
+}



From paulepanter at users.sourceforge.net  Tue Sep  6 16:28:47 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 06 Sep 2011 16:28:47 +0200
Subject: [coreboot] New patch to review for coreboot: deb6f0f Add ASUS
 M5A88-V mainboard support
In-Reply-To: <I9725ccdbb25365c4007621318efee80b131fec29+1@gerrit.coreboot.org>
References: <I9725ccdbb25365c4007621318efee80b131fec29+0@gerrit.coreboot.org>
	<I9725ccdbb25365c4007621318efee80b131fec29+1@gerrit.coreboot.org>
Message-ID: <1315319338.4717.13.camel@mattotaupa>

Dear QingPei,


Am Dienstag, den 06.09.2011, 15:12 +0200 schrieb QingPei Wang:

> commit deb6f0f225bddd2fa786f94689555a21add12d13
> Author: QingPei Wang <wangqingpei at gmail.com>
> Date:   Tue Sep 6 21:09:40 2011 +0800
> 
>     Add ASUS M5A88-V mainboard support
>     
>     it's a AMD 880+800 mainboard. I port the code
>     based on the AMD reference code.

nice job! Thank you for doing that.

Could you please add to the commit message what you have tested, i. e.
what does work and what does not work? Additionally what operating
system did you test? Is that patch applicable to master with your other
two(?) patches or does it depend on other patches send by AMD not yet in
master?
    
>     Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
>     Signed-off-by: QingPei Wang <wangqingpei at gmail.com>
> ---
>  src/mainboard/asus/Kconfig                  |    3 +
>  src/mainboard/asus/m5a88-v/Kconfig          |  107 ++
>  src/mainboard/asus/m5a88-v/Makefile.inc     |   20 +
>  src/mainboard/asus/m5a88-v/acpi/cpstate.asl |   75 ++
>  src/mainboard/asus/m5a88-v/acpi/ide.asl     |  244 ++++
>  src/mainboard/asus/m5a88-v/acpi/routing.asl |  398 ++++++
>  src/mainboard/asus/m5a88-v/acpi/sata.asl    |  149 +++
>  src/mainboard/asus/m5a88-v/acpi/usb.asl     |  161 +++
>  src/mainboard/asus/m5a88-v/acpi_tables.c    |  274 ++++
>  src/mainboard/asus/m5a88-v/chip.h           |   22 +
>  src/mainboard/asus/m5a88-v/cmos.layout      |   98 ++
>  src/mainboard/asus/m5a88-v/devicetree.cb    |  124 ++
>  src/mainboard/asus/m5a88-v/dsdt.asl         | 1824 +++++++++++++++++++++++++++
>  src/mainboard/asus/m5a88-v/fadt.c           |  201 +++
>  src/mainboard/asus/m5a88-v/get_bus_conf.c   |  147 +++
>  src/mainboard/asus/m5a88-v/irq_tables.c     |  111 ++
>  src/mainboard/asus/m5a88-v/mainboard.c      |  150 +++
>  src/mainboard/asus/m5a88-v/mb_sysconf.h     |   43 +
>  src/mainboard/asus/m5a88-v/mptable.c        |  160 +++
>  src/mainboard/asus/m5a88-v/pmio.c           |   53 +
>  src/mainboard/asus/m5a88-v/pmio.h           |   33 +
>  src/mainboard/asus/m5a88-v/reset.c          |   63 +
>  src/mainboard/asus/m5a88-v/resourcemap.c    |  278 ++++
>  src/mainboard/asus/m5a88-v/romstage.c       |  280 ++++
>  24 files changed, 5018 insertions(+), 0 deletions(-)

[?]

The diff is pretty big. I guess a lot of files have been copied over?
Can Gerrit send smaller diffs by using `git format-patch -M -C` (?) or
so?


Thanks,

Paul
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From wangqingpei at gmail.com  Tue Sep  6 16:42:22 2011
From: wangqingpei at gmail.com (QingPei Wang)
Date: Tue, 6 Sep 2011 22:42:22 +0800
Subject: [coreboot] New patch to review for coreboot: deb6f0f Add ASUS
 M5A88-V mainboard support
In-Reply-To: <1315319338.4717.13.camel@mattotaupa>
References: <I9725ccdbb25365c4007621318efee80b131fec29+0@gerrit.coreboot.org>
	<I9725ccdbb25365c4007621318efee80b131fec29+1@gerrit.coreboot.org>
	<1315319338.4717.13.camel@mattotaupa>
Message-ID: <CADuV8k52-fsCVYM_2Kg5Q_0_Zu7D8hy3_0VpRTZ8fSB8zDij7w@mail.gmail.com>

hi Paul,
i tested by my opensuse 11.2 without X windows. the patch is applicable to
the former two patches which i sent before.
And it does not depend on any other patches by AMD at this moment.
And i am trying to get familiar with gerrit at this moment. I just learned
how to submit the patches, still does not know
how to use "git format-patch" things.

The attachment is a simple boot log with the board. I will cost more time to
make this better.


Best wishes
Wang Qing Pei
Phone: 86+018930528086


On Tue, Sep 6, 2011 at 10:28 PM, Paul Menzel <
paulepanter at users.sourceforge.net> wrote:

> Dear QingPei,
>
>
> Am Dienstag, den 06.09.2011, 15:12 +0200 schrieb QingPei Wang:
>
> > commit deb6f0f225bddd2fa786f94689555a21add12d13
> > Author: QingPei Wang <wangqingpei at gmail.com>
> > Date:   Tue Sep 6 21:09:40 2011 +0800
> >
> >     Add ASUS M5A88-V mainboard support
> >
> >     it's a AMD 880+800 mainboard. I port the code
> >     based on the AMD reference code.
>
> nice job! Thank you for doing that.
>
> Could you please add to the commit message what you have tested, i. e.
> what does work and what does not work? Additionally what operating
> system did you test? Is that patch applicable to master with your other
> two(?) patches or does it depend on other patches send by AMD not yet in
> master?
>



>
> >     Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
> >     Signed-off-by: QingPei Wang <wangqingpei at gmail.com>
> > ---
> >  src/mainboard/asus/Kconfig                  |    3 +
> >  src/mainboard/asus/m5a88-v/Kconfig          |  107 ++
> >  src/mainboard/asus/m5a88-v/Makefile.inc     |   20 +
> >  src/mainboard/asus/m5a88-v/acpi/cpstate.asl |   75 ++
> >  src/mainboard/asus/m5a88-v/acpi/ide.asl     |  244 ++++
> >  src/mainboard/asus/m5a88-v/acpi/routing.asl |  398 ++++++
> >  src/mainboard/asus/m5a88-v/acpi/sata.asl    |  149 +++
> >  src/mainboard/asus/m5a88-v/acpi/usb.asl     |  161 +++
> >  src/mainboard/asus/m5a88-v/acpi_tables.c    |  274 ++++
> >  src/mainboard/asus/m5a88-v/chip.h           |   22 +
> >  src/mainboard/asus/m5a88-v/cmos.layout      |   98 ++
> >  src/mainboard/asus/m5a88-v/devicetree.cb    |  124 ++
> >  src/mainboard/asus/m5a88-v/dsdt.asl         | 1824
> +++++++++++++++++++++++++++
> >  src/mainboard/asus/m5a88-v/fadt.c           |  201 +++
> >  src/mainboard/asus/m5a88-v/get_bus_conf.c   |  147 +++
> >  src/mainboard/asus/m5a88-v/irq_tables.c     |  111 ++
> >  src/mainboard/asus/m5a88-v/mainboard.c      |  150 +++
> >  src/mainboard/asus/m5a88-v/mb_sysconf.h     |   43 +
> >  src/mainboard/asus/m5a88-v/mptable.c        |  160 +++
> >  src/mainboard/asus/m5a88-v/pmio.c           |   53 +
> >  src/mainboard/asus/m5a88-v/pmio.h           |   33 +
> >  src/mainboard/asus/m5a88-v/reset.c          |   63 +
> >  src/mainboard/asus/m5a88-v/resourcemap.c    |  278 ++++
> >  src/mainboard/asus/m5a88-v/romstage.c       |  280 ++++
> >  24 files changed, 5018 insertions(+), 0 deletions(-)
>
> [?]
>
> The diff is pretty big. I guess a lot of files have been copied over?
> Can Gerrit send smaller diffs by using `git format-patch -M -C` (?) or
> so?
>
>
> Thanks,
>
> Paul
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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coreboot-4.0-1657-g2aac3f6-dirty Sat Sep  3 23:55:35 CST 2011 starting...

BSP Family_Model: 00100fa0 
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00 
cpu_init_detectedx = 00000000 
microcode: equivalent rev id  = 0x10a0, current patch id = 0x00000000
microcode: patch id to apply = 0x010000bf
microcode: updated to patch id = 0x010000bf  success

cpuSetAMDMSR  done
Enter amd_ht_init()
Exit amd_ht_init()
cpuSetAMDPCI 00cpuSetAMDPCI  revision 40000000 done
Prep FID/VID Node:00 
P-state info in MSRC001_0064 is invalid !!!
P-state info in MSRc0010064 is invalid !!!
  F3x80: e600e681 
  F3x84: 80e641e6 
  F3xD4: c8810f26 
  F3xD8: 03001316 
  F3xDC: 0000611a 
core0 started: 
start_other_cores()
init node: 00  cores: 05 
Start other core - nodeid: 00  cores: 05
started ap apicid:      cccccooooorrrrreeeeexxxxx:::::          ---------------     {{{{{     A
AAAAPPPPPIIIIICCCCCIIIIIDDDDD     =====     0000034521     NNNNNOOOOODDDDDEEEEEIIIIIDDDDD     =
====     0000000000     CCCCCOOOOORRRRREEEEEIIIIIDDDDD     =====     0000024315}}}}}     ------
---------




*m mmmmiiiiAiccccPcrrr rrooo0ooccc1ccooooodddddeeeee:::::     eeeeeqqqqquuuuuiiiiivvvvvaaaaalll
lleeeeennnnnttttt     rrrrreeeeevvvvv     iiiiiddddd          =====     00000xxxxx1111100000aaa
aa00000,,,,,     cccccuuuuurrrrrrrrrreeeeennnnnttttt     pppppaaaaatttttccccchhhhh     iiiiiddd
dd     =====     00000xxxxx0000000000000000000000000000000000000000




startemmdiimmmcciiirrccc
oorrrcoooccccooddoooeeddd:eee: :::    pppppaaattaatcctthhccc  hhh   iiiiidddd  d  tt 
tootto  ooa   apaaapppppppppllllyylyy  y ==    ===00   x000x0xxx00001111100000000000000000bb000
ffbbbfff




mmmmm*iiii icccAccrrrPrrooo ooccc0ccooo2oodddddeeeee:::::     uuuuupppppdddddaaaaattttteeeeeddd
dd     tttttooooo     pppppaaaaatttttccccchhhhh     iiiiiddddd     =====     00000xxxxx00000111
1100000000000000000000bbbbbfffff          sssssuuuuucccccccccceeeeessssssssss









sctccccpppppauuuuurSSSSSteeeeeettttdtAAAAAMMMM
MDDDDDMMMMMSSSSSRRRRR     * AP 0 3FdIFFFoXIIIXXXnMMMMeEEE!E!!
 ! C  PCCCPPPUUU U  V VeVVreeerrrsssisiioioonon nn   uuununnknkknknonnwooowwwnnn n  o oroo 
rrr   nnnonootott t s  usssuuupppppppoporootrrrttteeededd!d!! !   



sFtIFFFiIInaXIXXirMXMMttEMEE_e!E!!fd ! iC  Cd
PCCPvUPPUi UUdV   eVVV_reeeasrrrpisss(iiisoootnonna n gu  uenuuknnn1nkkk)nnn ooooawwwpnwnn
i nco   irooo rrrdn   :nnn oooo0ttt5 t s  s
usspuuupppppppoorootrrretttdeeeddd!!! !   



F*  dd  I ooddDAnnooVPeennI eeD0
 4


on AsPtiiiiannnn:riiii ttttt0e____5ffffdiiii
dddd
vvvviiiidddd____aaaapppp((((ssssttttaaaaggggeeee1111))))    aaaappppiiiicccciiiidddd::::   
 00001324



*FFFFIIII DDDDAVVVVPIIII DDDD0   5 oooonnnn    AAAAPPPP::::    00002413



started

rs780_early_setup()
fam10_optimization()
rs780_por_init

Begin FIDVID MSR 0xc0010071 0x01800001 0x3c013440 
FIDVID on BSP, APIC_id: 00
BSP fid = 0
Wait for AP stage 1: ap_apicid = 1
	readback = 1000001
	common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 2
	readback = 2000001
	common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 3
	readback = 3000001
	common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 4
	readback = 4000001
	common_fid(packed) = 0
Wait for AP stage 1: ap_apicid = 5
	readback = 5000001
	common_fid(packed) = 0
common_fid = 0
End FIDVIDMSR 0xc0010071 0x01800001 0x3c013440 
rs780_htinit cpu_ht_freq=b.
rs780_htinit: HT3 mode
...WARM RESET...




coreboot-4.0-1657-g2aac3f6-dirty Sat Sep  3 23:55:35 CST 2011 starting...

BSP Family_Model: 00100fa0 
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00 
cpu_init_detectedx = 00000000 
microcode: equivalent rev id  = 0x10a0, current patch id = 0x00000000
microcode: patch id to apply = 0x010000bf
microcode: updated to patch id = 0x010000bf  success

cpuSetAMDMSR  done
Enter amd_ht_init()
Exit amd_ht_init()
cpuSetAMDPCI 00cpuSetAMDPCI  revision 40000000 done
Prep FID/VID Node:00 
P-state info in MSRC001_0064 is invalid !!!
P-state info in MSRc0010064 is invalid !!!
  F3x80: e600e681 
  F3x84: 80e641e6 
  F3xD4: c8810f26 
  F3xD8: 03001316 
  F3xDC: 0000611a 
core0 started: 
start_other_cores()
init node: 00  cores: 05 
Start other core - nodeid: 00  cores: 05
started ap apicid:      cccccooooorrrrreeeeexxxxx:::::          ---------------     {{{{{     A
AAAAPPPPPIIIIICCCCCIIIIIDDDDD     =====     0000043512     NNNNNOOOOODDDDDEEEEEIIIIIDDDDD     =
====     0000000000     CCCCCOOOOORRRRREEEEEIIIIIDDDDD     =====     0000034152}}}}}     ------
---------




* mmmAmmiiiiiPcccc crrr0rroo1ooocccccooooodddddeeeee:::::     eeeeeqqqqquuuuuiiiiivvvvvaaaaalll
lleeeeennnnnttttt     rrrrreeeeevvvvv     iiiiiddddd          =====     00000xxxxx1111100000aaa
aa00000,,,,,     cccccuuuuurrrrrrrrrreeeeennnnnttttt     pppppaaaaatttttccccchhhhh     iiiiiddd
dd     =====     00000xxxxx0000000000000000000000000000000000000000




startedmmmmmiiiiic
ccccrrrrrooooocccccooooodddddeeeee:::::     pppppaaaaatttttccccchhhhh     iiiiiddddd     tt
tttooooo     aaaaapppppppppplllllyyyyy     =====     00000xxxxx000001111100000000000000000000bb
bbbfffff




m*mmmmiiii icccAccrrPrrro oooo0cccccooooo2dddddeeeee:::::     uuuuupppppdddddaaaaattttteeeeeddd
dd     tttttooooo     pppppaaaaatttttccccchhhhh     iiiiiddddd     =====     00000xxxxx00000111
1100000000000000000000bbbbbfffff          sssssuuuuucccccccccceeeeessssssssss









scctcccpappppruuuuuSSSSSteeeeeettdtttAAAAA
MMMMMDDDDDMMMMMSSSSSRRRRR     * AP 03 FFdFFIIoIIXnXXXMeMMMEEEE
!!!!    CCCCPPPPUUUU    VVVVeeeerrrrssssiiiioooonnnn    uuuunnnnkkkknnnnoooowwwwnnnn    ooo
orrrr    nnnnooootttt    ssssuuuuppppppppoooorrrrtttteeeedddd!!!!    



sFFitIFFIIInaXXXirMXMttEMM_e!EEEd !!!fC   iCCCd
PPvUPPUi UU dV  _eVVVsreeesrrrtisssaiiigooooennn2 n   u uanuunpknnkinkkconnniwooonwwwd nnn:
    oooo0rrr2 r  n n
onnotoot tt s  sussupuupppppopporoortrrtteteededd!d!! !   



*   ddd  odAoooPnnn eeene0

4

siiitinnanniriiittttte____ffffdiiiidd
ddvvvviiiidddd____ssssttttaaaaggggeeee2222    aaaappppiiiicccciiiidddd::::    00005341



* AP 05started

rs780_early_setup()
fam10_optimization()
rs780_por_init

Begin FIDVID MSR 0xc0010071 0x01800001 0x3c013440 
End FIDVIDMSR 0xc0010071 0x01800001 0x3c013440 
rs780_htinit cpu_ht_freq=b.
rs780_htinit: HT3 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
	 DIMMPresence: DIMMValid=1
	 DIMMPresence: DIMMPresent=1
	 DIMMPresence: RegDIMMPresent=0
	 DIMMPresence: DimmECCPresent=0
	 DIMMPresence: DimmPARPresent=0
	 DIMMPresence: Dimmx4Present=0
	 DIMMPresence: Dimmx8Present=1
	 DIMMPresence: Dimmx16Present=0
	 DIMMPresence: DimmPlPresent=0
	 DIMMPresence: DimmDRPresent=1
	 DIMMPresence: DimmQRPresent=0
	 DIMMPresence: DATAload[0]=2
	 DIMMPresence: MAload[0]=10
	 DIMMPresence: MAdimms[0]=1
	 DIMMPresence: DATAload[1]=0
	 DIMMPresence: MAload[1]=0
	 DIMMPresence: MAdimms[1]=0
	 DIMMPresence: Status 1000
	 DIMMPresence: ErrStatus 0
	 DIMMPresence: ErrCode 0
	 DIMMPresence: Done

		DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
		DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1000
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done

AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

		DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 3
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done

AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done

InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done

AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: 90092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 10000
AutoConfig_D: DramConfigHi: f40000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done

		DCTInit_D: AutoConfig_D Done
		DCTInit_D: PlatformSpec_D Done
		DCTInit_D: StartupDCT_D
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
 Node: 00  base: 00  limit: ffffff  BottomIO: c00000
 Node: 00  base: 03  limit: 13fffff 
 Node: 01  base: 00  limit: 00 
 Node: 02  base: 00  limit: 00 
 Node: 03  base: 00  limit: 00 
 Node: 04  base: 00  limit: 00 
 Node: 05  base: 00  limit: 00 
 Node: 06  base: 00  limit: 00 
 Node: 07  base: 00  limit: 00 
mctAutoInitMCT_D: CPUMemTyping_D
	 CPUMemTyping: Cache32bTOP:c00000
	 CPUMemTyping: Bottom32bIO:c00000
	 CPUMemTyping: Bottom40bIO:1400000
mctAutoInitMCT_D: DQSTiming_D
TrainRcvrEn: Status 1100
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 1100
InterleaveNodes_D: ErrStatus 0
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done

InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 1100
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done

mctAutoInitMCT_D: ECCInit_D
All Done
raminit_amdmct end:
v_esp=000cbef8
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now 
Clearing initial memory region: Done
Loading image.
Searching for fallback/coreboot_ram
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (1212416 bytes), entry @ 0x200000
Stage: done loading.
Jumping to image.
coreboot-4.0-1657-g2aac3f6-dirty Sat Sep  3 23:55:35 CST 2011 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PCI: 00:14.4: enabled 0
PCI: 00:14.5: enabled 1
PCI: 00:14.6: enabled 0
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.2: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
Compare with tree...
Root Device: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:18.0: enabled 1
   PCI: 00:00.0: enabled 1
   PCI: 00:01.0: enabled 1
   PCI: 00:02.0: enabled 1
   PCI: 00:03.0: enabled 0
   PCI: 00:04.0: enabled 1
   PCI: 00:05.0: enabled 0
   PCI: 00:06.0: enabled 0
   PCI: 00:07.0: enabled 0
   PCI: 00:08.0: enabled 0
   PCI: 00:09.0: enabled 1
   PCI: 00:0a.0: enabled 1
   PCI: 00:11.0: enabled 1
   PCI: 00:12.0: enabled 1
   PCI: 00:12.2: enabled 1
   PCI: 00:13.0: enabled 1
   PCI: 00:13.2: enabled 1
   PCI: 00:14.0: enabled 1
    I2C: 00:50: enabled 1
    I2C: 00:51: enabled 1
    I2C: 00:52: enabled 1
    I2C: 00:53: enabled 1
   PCI: 00:14.1: enabled 1
   PCI: 00:14.2: enabled 1
   PCI: 00:14.3: enabled 1
    PNP: 002e.0: enabled 0
    PNP: 002e.1: enabled 0
    PNP: 002e.2: enabled 1
    PNP: 002e.3: enabled 1
    PNP: 002e.5: enabled 1
    PNP: 002e.6: enabled 0
    PNP: 002e.7: enabled 0
    PNP: 002e.8: enabled 0
    PNP: 002e.9: enabled 0
    PNP: 002e.a: enabled 0
    PNP: 002e.b: enabled 1
   PCI: 00:14.4: enabled 0
   PCI: 00:14.5: enabled 1
   PCI: 00:14.6: enabled 0
   PCI: 00:15.0: enabled 1
   PCI: 00:15.1: enabled 1
   PCI: 00:15.2: enabled 1
   PCI: 00:15.3: enabled 1
   PCI: 00:16.0: enabled 1
   PCI: 00:16.2: enabled 1
  PCI: 00:18.1: enabled 1
  PCI: 00:18.2: enabled 1
  PCI: 00:18.3: enabled 1
  PCI: 00:18.4: enabled 1
Mainboard ASUS M5A88PMEnable. dev=0x0021fe6c
m5a88pm_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
m5a88pm_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000001
m5a88pm_enable: uma size 0x10000000, memory start 0xb0000000
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  PCI: 00:18.3 siblings=5
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
CPU: APIC: 02 enabled
CPU: APIC: 03 enabled
CPU: APIC: 04 enabled
CPU: APIC: 05 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
PCI: Using configuration type 1
rs780_enable: dev=002203b8, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0181
PCI: pci_scan_bus for bus 00
PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
PCI: pci_scan_bus upper limit too big. Using 0xff.
rs780_enable: dev=002203b8, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
rs780_enable: dev=00220568, VID_DID=0x96021022
Bus-0, Dev-1, Fun-0.
GC is accessible from now on.
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
PCI: 00:01.0 [1022/9602] enabled
rs780_enable: dev=00220718, VID_DID=0x96031022
Bus-0, Dev-2,3, Fun-0. enable=1
rs780_gfx_init, nb_dev=0x002203b8, dev=0x00220718, port=0x2.
misc 28 = 0
rs780_gfx_init step5.9.12.1.
rs780_gfx_init step5.9.12.3.
rs780_gfx_init step5.9.12.9.
rs780_gfx_init step1.
device = 2
rs780_gfx_init single_port_configuration.
PcieLinkTraining port=2:lc current state=2030400
rs780_gfx_init single_port_configuration step12.
rs780_gfx_init single_port_configuration step13.
rs780_gfx_init single_port_configuration step14.
PCI: Static device PCI: 00:02.0 not found, disabling it.
rs780_enable: dev=002208c8, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=0
rs780_enable: dev=002209e8, VID_DID=0x96041022
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x20, port=0x4
PcieLinkTraining port=4:lc current state=10203
PcieTrainPort port=0x4 result=0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1022/9604] enabled
rs780_enable: dev=00220ac0, VID_DID=0x96051022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00220b98, VID_DID=0x96061022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00220c70, VID_DID=0x96071022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00220d48, VID_DID=0x960a1022
Bus-0, Dev-8, Fun-0. enable=0
rs780_enable: dev=00220e20, VID_DID=0x96081022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x48, port=0x9
PcieLinkTraining port=9:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=48
PcieTrainPort reg=0x10000
PcieTrainPort port=0x9 result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:09.0 subordinate bus PCI Express
PCI: 00:09.0 [1022/9608] enabled
rs780_enable: dev=00220ef8, VID_DID=0x96091022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x50, port=0xa
PcieLinkTraining port=a:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=50
PcieTrainPort reg=0x10000
PcieTrainPort port=0xa result=1
disable_pcie_bar3()
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1022/9609] enabled
sb800_enable() PCI: 00:11.0 [1002/4390] enabled
sb800_enable() PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb800_enable() PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb800_enable() PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb800_enable() PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb800_enable() sm_init().
IOAPIC: Clearing IOAPIC at 0xfec00000
IOAPIC: 23 interrupts
IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x08
IOAPIC: 23 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
PCI: 00:14.0 [1002/4385] enabled
sb800_enable() PCI: 00:14.1 [1002/439c] enabled
sb800_enable() hda enabled
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] disabled
sb800_enable() PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
sb800_enable() gec disabled
sb800_enable() PCI: 00:15.0 [1002/43a0] bus ops
PCI: 00:15.0 [1002/43a0] enabled
sb800_enable() PCI: 00:15.1 [1002/43a1] bus ops
PCI: 00:15.1 [1002/43a1] enabled
sb800_enable() PCI: 00:15.2 [1002/43a2] bus ops
PCI: 00:15.2 [1002/43a2] enabled
sb800_enable() PCI: 00:15.3 [1002/43a3] bus ops
PCI: 00:15.3 [1002/43a3] enabled
sb800_enable() PCI: 00:16.0 [1002/4397] ops
PCI: 00:16.0 [1002/4397] enabled
sb800_enable() PCI: 00:16.2 [1002/4396] ops
PCI: 00:16.2 [1002/4396] enabled
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:05.0 [1002/9715] enabled
PCI: 01:05.1 [1002/970f] enabled
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:09.0
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [1106/3403] enabled
PCI: 03:00.1 [1106/0415] enabled
PCI: pci_scan_bus returning with max=003
Capability: type 0x01 @ 0x50
Capability: type 0x05 @ 0x80
Capability: type 0x10 @ 0x98
Capability: type 0x01 @ 0x50
Capability: type 0x05 @ 0x70
Capability: type 0x10 @ 0x90
do_pci_scan_bridge returns max 3
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [1b21/1042] enabled
PCI: pci_scan_bus returning with max=004
Capability: type 0x05 @ 0x50
Capability: type 0x11 @ 0x68
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
do_pci_scan_bridge returns max 4
scan_static_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 enabled
PNP: 002e.5 enabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
PNP: 002e.b enabled
scan_static_bus for PCI: 00:14.3 done
do_pci_scan_bridge for PCI: 00:15.0
PCI: pci_scan_bus for bus 05
PCI: pci_scan_bus returning with max=005
do_pci_scan_bridge returns max 5
do_pci_scan_bridge for PCI: 00:15.1
PCI: pci_scan_bus for bus 06
PCI: 06:00.0 [10ec/8168] enabled
PCI: pci_scan_bus returning with max=006
do_pci_scan_bridge returns max 6
do_pci_scan_bridge for PCI: 00:15.2
PCI: pci_scan_bus for bus 07
PCI: pci_scan_bus returning with max=007
do_pci_scan_bridge returns max 7
do_pci_scan_bridge for PCI: 00:15.3
PCI: pci_scan_bus for bus 08
PCI: pci_scan_bus returning with max=008
do_pci_scan_bridge returns max 8
PCI: pci_scan_bus returning with max=008
PCI: pci_scan_bus returning with max=008
PCI_DOMAIN: 0000 passpw: enabled
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC: 02 missing read_resources
APIC: 03 missing read_resources
APIC: 04 missing read_resources
APIC: 05 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:00.0 register 1c(00000004), read-only ignoring it
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 2 link: 0
PCI: 00:04.0 read_resources bus 2 link: 0 done
PCI: 00:09.0 read_resources bus 3 link: 0
PCI: 00:09.0 read_resources bus 3 link: 0 done
PCI: 00:0a.0 read_resources bus 4 link: 0
PCI: 00:0a.0 read_resources bus 4 link: 0 done
PCI: 00:14.0 read_resources bus 0 link: 0
I2C: 00:50 missing read_resources
I2C: 00:51 missing read_resources
I2C: 00:52 missing read_resources
I2C: 00:53 missing read_resources
PCI: 00:14.0 read_resources bus 0 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PNP: 002e.3 missing read_resources
PNP: 002e.b missing read_resources
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:15.0 read_resources bus 5 link: 0
PCI: 00:15.0 read_resources bus 5 link: 0 done
PCI: 00:15.1 read_resources bus 6 link: 0
PCI: 00:15.1 read_resources bus 6 link: 0 done
PCI: 00:15.2 read_resources bus 7 link: 0
PCI: 00:15.2 read_resources bus 7 link: 0 done
PCI: 00:15.3 read_resources bus 8 link: 0
PCI: 00:15.3 read_resources bus 8 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:18.0 read_resources bus 0 link: 3
PCI: 00:18.0 read_resources bus 0 link: 3 done
PCI: 00:18.0 read_resources bus 0 link: 4
PCI: 00:18.0 read_resources bus 0 link: 4 done
PCI: 00:18.0 read_resources bus 0 link: 5
PCI: 00:18.0 read_resources bus 0 link: 5 done
PCI: 00:18.0 read_resources bus 0 link: 6
PCI: 00:18.0 read_resources bus 0 link: 6 done
PCI: 00:18.0 read_resources bus 0 link: 7
PCI: 00:18.0 read_resources bus 0 link: 7 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: 01
   APIC: 02
   APIC: 03
   APIC: 04
   APIC: 05
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 100000
00
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10
000100
  PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 i
ndex c0010058
   PCI: 00:18.0 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0
    PCI: 00:00.0
    PCI: 00:01.0 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff flags 80102 index 1c
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81202 index 24
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 01:05.0
     PCI: 01:05.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 inde
x 10
     PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
     PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18
     PCI: 01:05.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 2
4
     PCI: 01:05.1
     PCI: 01:05.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
    PCI: 00:02.0
    PCI: 00:03.0
    PCI: 00:04.0
    PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 ind
ex 24
    PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 00:05.0
    PCI: 00:06.0
    PCI: 00:07.0
    PCI: 00:08.0
    PCI: 00:09.0 child on link 0 PCI: 03:00.0
    PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 ind
ex 24
    PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 03:00.0
     PCI: 03:00.0 resource base 0 size 800 align 11 gran 11 limit ffffffffffffffff flags 201 in
dex 10
     PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 18
     PCI: 03:00.1
     PCI: 03:00.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
     PCI: 03:00.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
     PCI: 03:00.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
     PCI: 03:00.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
     PCI: 03:00.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
     PCI: 03:00.1 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 3
0
    PCI: 00:0a.0 child on link 0 PCI: 04:00.0
    PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 ind
ex 24
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 04:00.0
     PCI: 04:00.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 i
ndex 10
    PCI: 00:11.0
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
    PCI: 00:12.0
    PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:12.2
    PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:13.0
    PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:13.2
    PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:14.0 child on link 0 I2C: 00:50
     I2C: 00:50
     I2C: 00:51
     I2C: 00:52
     I2C: 00:53
    PCI: 00:14.1
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:14.2
    PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 in
dex 10
    PCI: 00:14.3 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index
 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0
     PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74
     PNP: 002e.1
     PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2
     PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
     PNP: 002e.3
     PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.5
     PNP: 002e.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72
     PNP: 002e.6
     PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
     PNP: 002e.7
     PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
     PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.8
     PNP: 002e.9
     PNP: 002e.a
     PNP: 002e.b
     PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
    PCI: 00:14.4
    PCI: 00:14.5
    PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:14.6
    PCI: 00:15.0
    PCI: 00:15.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:15.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 ind
ex 24
    PCI: 00:15.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 00:15.1 child on link 0 PCI: 06:00.0
    PCI: 00:15.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:15.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 ind
ex 24
    PCI: 00:15.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 06:00.0
     PCI: 06:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
     PCI: 06:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 
index 18
     PCI: 06:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 
index 20
    PCI: 00:15.2
    PCI: 00:15.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:15.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 ind
ex 24
    PCI: 00:15.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 00:15.3
    PCI: 00:15.3 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:15.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 ind
ex 24
    PCI: 00:15.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 00:16.0
    PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:16.2
    PCI: 00:16.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:18.0
    PCI: 00:18.1
    PCI: 00:18.2
    PCI: 00:18.3
    PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 9
4
    PCI: 00:18.4
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
   PCI: 00:18.4
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff
PCI: 01:05.0 14 *  [0x0 - 0xff] io
PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:00.0 18 *  [0x0 - 0xff] io
PCI: 03:00.1 20 *  [0x400 - 0x40f] io
PCI: 03:00.1 10 *  [0x410 - 0x417] io
PCI: 03:00.1 18 *  [0x418 - 0x41f] io
PCI: 03:00.1 14 *  [0x420 - 0x423] io
PCI: 03:00.1 1c *  [0x424 - 0x427] io
PCI: 00:09.0 compute_resources_io: base: 428 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:15.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:15.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:15.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 06:00.0 10 *  [0x0 - 0xff] io
PCI: 00:15.1 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:15.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:15.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:15.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:15.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:01.0 1c *  [0x0 - 0xfff] io
PCI: 00:09.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:15.1 1c *  [0x2000 - 0x2fff] io
PCI: 00:11.0 20 *  [0x3000 - 0x300f] io
PCI: 00:14.1 20 *  [0x3010 - 0x301f] io
PCI: 00:11.0 10 *  [0x3020 - 0x3027] io
PCI: 00:11.0 18 *  [0x3028 - 0x302f] io
PCI: 00:14.1 10 *  [0x3030 - 0x3037] io
PCI: 00:14.1 18 *  [0x3038 - 0x303f] io
PCI: 00:11.0 14 *  [0x3040 - 0x3043] io
PCI: 00:11.0 1c *  [0x3044 - 0x3047] io
PCI: 00:14.1 14 *  [0x3048 - 0x304b] io
PCI: 00:14.1 1c *  [0x304c - 0x304f] io
PCI: 00:18.0 compute_resources_io: base: 3050 size: 4000 align: 12 gran: 12 limit: ffff done
PCI: 00:18.0 10d8 *  [0x0 - 0x3fff] io
PCI_DOMAIN: 0000 compute_resources_io: base: 4000 size: 4000 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 01:05.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit:
 ffffffff done
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff done
PCI: 00:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff
PCI: 00:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff done
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff done
PCI: 00:15.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff
PCI: 00:15.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff done
PCI: 00:15.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff
PCI: 06:00.0 20 *  [0x0 - 0x3fff] prefmem
PCI: 06:00.0 18 *  [0x4000 - 0x4fff] prefmem
PCI: 00:15.1 compute_resources_prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: fffff
fffffffffff done
PCI: 00:15.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff
PCI: 00:15.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff done
PCI: 00:15.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff
PCI: 00:15.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffff
fff done
PCI: 00:01.0 24 *  [0x0 - 0xfffffff] prefmem
PCI: 00:15.1 24 *  [0x10000000 - 0x100fffff] prefmem
PCI: 00:18.0 compute_resources_prefmem: base: 10100000 size: 10100000 align: 28 gran: 20 limit:
 ffffffff done
PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 24 *  [0x0 - 0xfffff] mem
PCI: 01:05.0 18 *  [0x100000 - 0x10ffff] mem
PCI: 01:05.1 10 *  [0x110000 - 0x113fff] mem
PCI: 00:01.0 compute_resources_mem: base: 114000 size: 200000 align: 20 gran: 20 limit: fffffff
f done
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:09.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.1 30 *  [0x0 - 0xffff] mem
PCI: 03:00.0 10 *  [0x10000 - 0x107ff] mem
PCI: 00:09.0 compute_resources_mem: base: 10800 size: 100000 align: 20 gran: 20 limit: ffffffff
 done
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:00.0 10 *  [0x0 - 0x7fff] mem
PCI: 00:0a.0 compute_resources_mem: base: 8000 size: 100000 align: 20 gran: 20 limit: ffffffff 
done
PCI: 00:15.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:15.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:15.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:15.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:15.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:15.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:15.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:15.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.3 94 *  [0x0 - 0x3ffffff] mem
PCI: 00:01.0 20 *  [0x4000000 - 0x41fffff] mem
PCI: 00:09.0 20 *  [0x4200000 - 0x42fffff] mem
PCI: 00:0a.0 20 *  [0x4300000 - 0x43fffff] mem
PCI: 00:14.2 10 *  [0x4400000 - 0x4403fff] mem
PCI: 00:12.0 10 *  [0x4404000 - 0x4404fff] mem
PCI: 00:13.0 10 *  [0x4405000 - 0x4405fff] mem
PCI: 00:14.5 10 *  [0x4406000 - 0x4406fff] mem
PCI: 00:16.0 10 *  [0x4407000 - 0x4407fff] mem
PCI: 00:11.0 24 *  [0x4408000 - 0x44083ff] mem
PCI: 00:12.2 10 *  [0x4408400 - 0x44084ff] mem
PCI: 00:13.2 10 *  [0x4408500 - 0x44085ff] mem
PCI: 00:16.2 10 *  [0x4408600 - 0x44086ff] mem
PCI: 00:14.3 a0 *  [0x4408700 - 0x4408700] mem
PCI: 00:18.0 compute_resources_mem: base: 4408701 size: 4500000 align: 26 gran: 20 limit: fffff
fff done
PCI: 00:18.0 10b8 *  [0x0 - 0x100fffff] prefmem
PCI: 00:18.0 10b0 *  [0x14000000 - 0x184fffff] mem
PCI: 00:18.3 94 *  [0x1c000000 - 0x1fffffff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 20000000 size: 20000000 align: 28 gran: 0 limit: 
ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 01:05.0
constrain_resources: PCI: 01:05.1
constrain_resources: PCI: 00:04.0
constrain_resources: PCI: 00:09.0
constrain_resources: PCI: 03:00.0
constrain_resources: PCI: 03:00.1
constrain_resources: PCI: 00:0a.0
constrain_resources: PCI: 04:00.0
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:12.2
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:13.2
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 00:50
constrain_resources: I2C: 00:51
constrain_resources: I2C: 00:52
constrain_resources: I2C: 00:53
constrain_resources: PCI: 00:14.1
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PNP: 002e.2
constrain_resources: PNP: 002e.3
skipping PNP: 002e.3 at 60 fixed resource, size=0!
skipping PNP: 002e.3 at 70 fixed resource, size=0!
constrain_resources: PNP: 002e.5
skipping PNP: 002e.5 at 72 fixed resource, size=0!
constrain_resources: PNP: 002e.b
skipping PNP: 002e.b at 60 fixed resource, size=0!
skipping PNP: 002e.b at 70 fixed resource, size=0!
constrain_resources: PCI: 00:14.5
constrain_resources: PCI: 00:15.0
constrain_resources: PCI: 00:15.1
constrain_resources: PCI: 06:00.0
constrain_resources: PCI: 00:15.2
constrain_resources: PCI: 00:15.3
constrain_resources: PCI: 00:16.0
constrain_resources: PCI: 00:16.2
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
	lim->base 00000000 lim->limit dfffffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:4000 align:12 gran:0 limit:ffff
Assigned: PCI: 00:18.0 10d8 *  [0x1000 - 0x4fff] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 5000 size: 4000 align: 12 gran: 0 done
PCI: 00:18.0 allocate_resources_io: base:1000 size:4000 align:12 gran:12 limit:ffff
Assigned: PCI: 00:01.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:09.0 1c *  [0x2000 - 0x2fff] io
Assigned: PCI: 00:15.1 1c *  [0x3000 - 0x3fff] io
Assigned: PCI: 00:11.0 20 *  [0x4000 - 0x400f] io
Assigned: PCI: 00:14.1 20 *  [0x4010 - 0x401f] io
Assigned: PCI: 00:11.0 10 *  [0x4020 - 0x4027] io
Assigned: PCI: 00:11.0 18 *  [0x4028 - 0x402f] io
Assigned: PCI: 00:14.1 10 *  [0x4030 - 0x4037] io
Assigned: PCI: 00:14.1 18 *  [0x4038 - 0x403f] io
Assigned: PCI: 00:11.0 14 *  [0x4040 - 0x4043] io
Assigned: PCI: 00:11.0 1c *  [0x4044 - 0x4047] io
Assigned: PCI: 00:14.1 14 *  [0x4048 - 0x404b] io
Assigned: PCI: 00:14.1 1c *  [0x404c - 0x404f] io
PCI: 00:18.0 allocate_resources_io: next_base: 4050 size: 4000 align: 12 gran: 12 done
PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:05.0 14 *  [0x1000 - 0x10ff] io
PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI: 00:04.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:04.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:09.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 03:00.0 18 *  [0x2000 - 0x20ff] io
Assigned: PCI: 03:00.1 20 *  [0x2400 - 0x240f] io
Assigned: PCI: 03:00.1 10 *  [0x2410 - 0x2417] io
Assigned: PCI: 03:00.1 18 *  [0x2418 - 0x241f] io
Assigned: PCI: 03:00.1 14 *  [0x2420 - 0x2423] io
Assigned: PCI: 03:00.1 1c *  [0x2424 - 0x2427] io
PCI: 00:09.0 allocate_resources_io: next_base: 2428 size: 1000 align: 12 gran: 12 done
PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:15.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:15.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:15.1 allocate_resources_io: base:3000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 06:00.0 10 *  [0x3000 - 0x30ff] io
PCI: 00:15.1 allocate_resources_io: next_base: 3100 size: 1000 align: 12 gran: 12 done
PCI: 00:15.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:15.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:15.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:15.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:20000000 align:28 gran:0 limit:dfff
ffff
Assigned: PCI: 00:18.0 10b8 *  [0xc0000000 - 0xd00fffff] prefmem
Assigned: PCI: 00:18.0 10b0 *  [0xd4000000 - 0xd84fffff] mem
Assigned: PCI: 00:18.3 94 *  [0xdc000000 - 0xdfffffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: e0000000 size: 20000000 align: 28 gran: 0 d
one
PCI: 00:18.0 allocate_resources_prefmem: base:c0000000 size:10100000 align:28 gran:20 limit:dff
fffff
Assigned: PCI: 00:01.0 24 *  [0xc0000000 - 0xcfffffff] prefmem
Assigned: PCI: 00:15.1 24 *  [0xd0000000 - 0xd00fffff] prefmem
PCI: 00:18.0 allocate_resources_prefmem: next_base: d0100000 size: 10100000 align: 28 gran: 20 
done
PCI: 00:01.0 allocate_resources_prefmem: base:c0000000 size:10000000 align:28 gran:20 limit:dff
fffff
Assigned: PCI: 01:05.0 10 *  [0xc0000000 - 0xcfffffff] prefmem
PCI: 00:01.0 allocate_resources_prefmem: next_base: d0000000 size: 10000000 align: 28 gran: 20 
done
PCI: 00:04.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:04.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:09.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:09.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:0a.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:0a.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:15.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.1 allocate_resources_prefmem: base:d0000000 size:100000 align:20 gran:20 limit:dffff
fff
Assigned: PCI: 06:00.0 20 *  [0xd0000000 - 0xd0003fff] prefmem
Assigned: PCI: 06:00.0 18 *  [0xd0004000 - 0xd0004fff] prefmem
PCI: 00:15.1 allocate_resources_prefmem: next_base: d0005000 size: 100000 align: 20 gran: 20 do
ne
PCI: 00:15.2 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:15.2 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.3 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:15.3 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 allocate_resources_mem: base:d4000000 size:4500000 align:26 gran:20 limit:dfffffff
Assigned: PCI: 00:18.3 94 *  [0xd4000000 - 0xd7ffffff] mem
Assigned: PCI: 00:01.0 20 *  [0xd8000000 - 0xd81fffff] mem
Assigned: PCI: 00:09.0 20 *  [0xd8200000 - 0xd82fffff] mem
Assigned: PCI: 00:0a.0 20 *  [0xd8300000 - 0xd83fffff] mem
Assigned: PCI: 00:14.2 10 *  [0xd8400000 - 0xd8403fff] mem
Assigned: PCI: 00:12.0 10 *  [0xd8404000 - 0xd8404fff] mem
Assigned: PCI: 00:13.0 10 *  [0xd8405000 - 0xd8405fff] mem
Assigned: PCI: 00:14.5 10 *  [0xd8406000 - 0xd8406fff] mem
Assigned: PCI: 00:16.0 10 *  [0xd8407000 - 0xd8407fff] mem
Assigned: PCI: 00:11.0 24 *  [0xd8408000 - 0xd84083ff] mem
Assigned: PCI: 00:12.2 10 *  [0xd8408400 - 0xd84084ff] mem
Assigned: PCI: 00:13.2 10 *  [0xd8408500 - 0xd84085ff] mem
Assigned: PCI: 00:16.2 10 *  [0xd8408600 - 0xd84086ff] mem
Assigned: PCI: 00:14.3 a0 *  [0xd8408700 - 0xd8408700] mem
PCI: 00:18.0 allocate_resources_mem: next_base: d8408701 size: 4500000 align: 26 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:d8000000 size:200000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 01:05.0 24 *  [0xd8000000 - 0xd80fffff] mem
Assigned: PCI: 01:05.0 18 *  [0xd8100000 - 0xd810ffff] mem
Assigned: PCI: 01:05.1 10 *  [0xd8110000 - 0xd8113fff] mem
PCI: 00:01.0 allocate_resources_mem: next_base: d8114000 size: 200000 align: 20 gran: 20 done
PCI: 00:04.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:04.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:09.0 allocate_resources_mem: base:d8200000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 03:00.1 30 *  [0xd8200000 - 0xd820ffff] mem
Assigned: PCI: 03:00.0 10 *  [0xd8210000 - 0xd82107ff] mem
PCI: 00:09.0 allocate_resources_mem: next_base: d8210800 size: 100000 align: 20 gran: 20 done
PCI: 00:0a.0 allocate_resources_mem: base:d8300000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 04:00.0 10 *  [0xd8300000 - 0xd8307fff] mem
PCI: 00:0a.0 allocate_resources_mem: next_base: d8308000 size: 100000 align: 20 gran: 20 done
PCI: 00:15.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:15.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.1 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:15.1 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.2 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:15.2 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.3 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:15.3 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
 split: 64K table at =afff0000
0: mmio_basek=00300000, basek=00400000, limitk=00500000
Adding UMA memory area
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 10d8 <- [0x0000001000 - 0x0000004fff] size 0x00004000 gran 0x0c io <node 0 link 0>
PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00d00fffff] size 0x10100000 gran 0x14 prefmem <node 0 li
nk 0>
PCI: 00:18.0 10b0 <- [0x00d4000000 - 0x00d84fffff] size 0x04500000 gran 0x14 mem <node 0 link 0
>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00d8000000 - 0x00d81fffff] size 0x00200000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:05.0 10 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem
PCI: 01:05.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:05.0 18 <- [0x00d8100000 - 0x00d810ffff] size 0x00010000 gran 0x10 mem
PCI: 01:05.0 24 <- [0x00d8000000 - 0x00d80fffff] size 0x00100000 gran 0x14 mem
PCI: 01:05.1 10 <- [0x00d8110000 - 0x00d8113fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:04.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:04.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:04.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:09.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:09.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:09.0 20 <- [0x00d8200000 - 0x00d82fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x00d8210000 - 0x00d82107ff] size 0x00000800 gran 0x0b mem64
PCI: 03:00.0 18 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 03:00.1 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03 io
PCI: 03:00.1 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02 io
PCI: 03:00.1 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03 io
PCI: 03:00.1 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02 io
PCI: 03:00.1 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04 io
PCI: 03:00.1 30 <- [0x00d8200000 - 0x00d820ffff] size 0x00010000 gran 0x10 romem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
PCI: 00:0a.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:0a.0 20 <- [0x00d8300000 - 0x00d83fffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:0a.0 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00d8300000 - 0x00d8307fff] size 0x00008000 gran 0x0f mem64
PCI: 00:0a.0 assign_resources, bus 4 link: 0
PCI: 00:11.0 10 <- [0x0000004020 - 0x0000004027] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000004040 - 0x0000004043] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000004028 - 0x000000402f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000004044 - 0x0000004047] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000004000 - 0x000000400f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00d8408000 - 0x00d84083ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00d8404000 - 0x00d8404fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00d8408400 - 0x00d84084ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00d8405000 - 0x00d8405fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00d8408500 - 0x00d84085ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.1 10 <- [0x0000004030 - 0x0000004037] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000004048 - 0x000000404b] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000004038 - 0x000000403f] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x000000404c - 0x000000404f] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000004010 - 0x000000401f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00d8400000 - 0x00d8403fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00d8408700 - 0x00d8408700] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
ERROR: PNP: 002e.2 74 drq size: 0x0000000001 not assigned
ERROR: PNP: 002e.2 75 drq size: 0x0000000001 not assigned
PNP: 002e.3 missing set_resources
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io
PNP: 002e.5 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran 0x03 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000b] size 0x00000000 gran 0x00 irq
PNP: 002e.b missing set_resources
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.5 10 <- [0x00d8406000 - 0x00d8406fff] size 0x00001000 gran 0x0c mem
PCI: 00:15.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
PCI: 00:15.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 00:15.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 05 mem
PCI: 00:15.1 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 06 io
PCI: 00:15.1 24 <- [0x00d0000000 - 0x00d00fffff] size 0x00100000 gran 0x14 bus 06 prefmem
PCI: 00:15.1 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 06 mem
PCI: 00:15.1 assign_resources, bus 6 link: 0
PCI: 06:00.0 10 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io
PCI: 06:00.0 18 <- [0x00d0004000 - 0x00d0004fff] size 0x00001000 gran 0x0c prefmem64
PCI: 06:00.0 20 <- [0x00d0000000 - 0x00d0003fff] size 0x00004000 gran 0x0e prefmem64
PCI: 00:15.1 assign_resources, bus 6 link: 0
PCI: 00:15.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 07 io
PCI: 00:15.2 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 07 prefmem
PCI: 00:15.2 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 07 mem
PCI: 00:15.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 08 io
PCI: 00:15.3 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 08 prefmem
PCI: 00:15.3 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 08 mem
PCI: 00:16.0 10 <- [0x00d8407000 - 0x00d8407fff] size 0x00001000 gran 0x0c mem
PCI: 00:16.2 10 <- [0x00d8408600 - 0x00d84086ff] size 0x00000100 gran 0x08 mem
PCI: 00:18.3 94 <- [0x00d4000000 - 0x00d7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.3 94 <- [0x00d4000000 - 0x00d7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:18.3 94 <- [0x00dc000000 - 0x00dfffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.3 94 <- [0x00dc000000 - 0x00dfffffff] size 0x04000000 gran 0x1a mem <gart>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: 01
   APIC: 02
   APIC: 03
   APIC: 04
   APIC: 05
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 1000 size 4000 align 12 gran 0 limit ffff flags 40040100 index
 10000000
  PCI_DOMAIN: 0000 resource base c0000000 size 20000000 align 28 gran 0 limit dfffffff flags 40
040200 index 10000100
  PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 i
ndex c0010058
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
  PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 inde
x 20
  PCI_DOMAIN: 0000 resource base 100000000 size 30000000 align 0 gran 0 limit 0 flags e0004200 
index 30
  PCI_DOMAIN: 0000 resource base b0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 i
ndex 7
   PCI: 00:18.0 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base 1000 size 4000 align 12 gran 12 limit ffff flags 60080100 index 1
0d8
   PCI: 00:18.0 resource base c0000000 size 10100000 align 28 gran 20 limit dfffffff flags 6008
1200 index 10b8
   PCI: 00:18.0 resource base d4000000 size 4500000 align 26 gran 20 limit dfffffff flags 60080
200 index 10b0
    PCI: 00:00.0
    PCI: 00:01.0 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 
1c
    PCI: 00:01.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 600
81202 index 24
    PCI: 00:01.0 resource base d8000000 size 200000 align 20 gran 20 limit dfffffff flags 60080
202 index 20
     PCI: 01:05.0
     PCI: 01:05.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60
001200 index 10
     PCI: 01:05.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
     PCI: 01:05.0 resource base d8100000 size 10000 align 16 gran 16 limit dfffffff flags 60000
200 index 18
     PCI: 01:05.0 resource base d8000000 size 100000 align 20 gran 20 limit dfffffff flags 6000
0200 index 24
     PCI: 01:05.1
     PCI: 01:05.1 resource base d8110000 size 4000 align 14 gran 14 limit dfffffff flags 600002
00 index 10
    PCI: 00:02.0
    PCI: 00:03.0
    PCI: 00:04.0
    PCI: 00:04.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:04.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 i
ndex 24
    PCI: 00:04.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 i
ndex 20
    PCI: 00:05.0
    PCI: 00:06.0
    PCI: 00:07.0
    PCI: 00:08.0
    PCI: 00:09.0 child on link 0 PCI: 03:00.0
    PCI: 00:09.0 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 
1c
    PCI: 00:09.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 i
ndex 24
    PCI: 00:09.0 resource base d8200000 size 100000 align 20 gran 20 limit dfffffff flags 60080
202 index 20
     PCI: 03:00.0
     PCI: 03:00.0 resource base d8210000 size 800 align 11 gran 11 limit dfffffff flags 6000020
1 index 10
     PCI: 03:00.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 18
     PCI: 03:00.1
     PCI: 03:00.1 resource base 2410 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
     PCI: 03:00.1 resource base 2420 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
     PCI: 03:00.1 resource base 2418 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
     PCI: 03:00.1 resource base 2424 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
     PCI: 03:00.1 resource base 2400 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
     PCI: 03:00.1 resource base d8200000 size 10000 align 16 gran 16 limit dfffffff flags 60002
200 index 30
    PCI: 00:0a.0 child on link 0 PCI: 04:00.0
    PCI: 00:0a.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:0a.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 i
ndex 24
    PCI: 00:0a.0 resource base d8300000 size 100000 align 20 gran 20 limit dfffffff flags 60080
202 index 20
     PCI: 04:00.0
     PCI: 04:00.0 resource base d8300000 size 8000 align 15 gran 15 limit dfffffff flags 600002
01 index 10
    PCI: 00:11.0
    PCI: 00:11.0 resource base 4020 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
    PCI: 00:11.0 resource base 4040 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
    PCI: 00:11.0 resource base 4028 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
    PCI: 00:11.0 resource base 4044 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
    PCI: 00:11.0 resource base 4000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
    PCI: 00:11.0 resource base d8408000 size 400 align 10 gran 10 limit dfffffff flags 60000200
 index 24
    PCI: 00:12.0
    PCI: 00:12.0 resource base d8404000 size 1000 align 12 gran 12 limit dfffffff flags 6000020
0 index 10
    PCI: 00:12.2
    PCI: 00:12.2 resource base d8408400 size 100 align 8 gran 8 limit dfffffff flags 60000200 i
ndex 10
    PCI: 00:13.0
    PCI: 00:13.0 resource base d8405000 size 1000 align 12 gran 12 limit dfffffff flags 6000020
0 index 10
    PCI: 00:13.2
    PCI: 00:13.2 resource base d8408500 size 100 align 8 gran 8 limit dfffffff flags 60000200 i
ndex 10
    PCI: 00:14.0 child on link 0 I2C: 00:50
     I2C: 00:50
     I2C: 00:51
     I2C: 00:52
     I2C: 00:53
    PCI: 00:14.1
    PCI: 00:14.1 resource base 4030 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
    PCI: 00:14.1 resource base 4048 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
    PCI: 00:14.1 resource base 4038 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
    PCI: 00:14.1 resource base 404c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
    PCI: 00:14.1 resource base 4010 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
    PCI: 00:14.2
    PCI: 00:14.2 resource base d8400000 size 4000 align 14 gran 14 limit dfffffff flags 6000020
1 index 10
    PCI: 00:14.3 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base d8408700 size 1 align 0 gran 0 limit dfffffff flags 60000200 ind
ex a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index
 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0
     PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74
     PNP: 002e.1
     PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2
     PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
     PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
     PNP: 002e.3
     PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.5
     PNP: 002e.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
     PNP: 002e.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags e0000400 index 72
     PNP: 002e.6
     PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
     PNP: 002e.7
     PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
     PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.8
     PNP: 002e.9
     PNP: 002e.a
     PNP: 002e.b
     PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
    PCI: 00:14.4
    PCI: 00:14.5
    PCI: 00:14.5 resource base d8406000 size 1000 align 12 gran 12 limit dfffffff flags 6000020
0 index 10
    PCI: 00:14.6
    PCI: 00:15.0
    PCI: 00:15.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:15.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 i
ndex 24
    PCI: 00:15.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 i
ndex 20
    PCI: 00:15.1 child on link 0 PCI: 06:00.0
    PCI: 00:15.1 resource base 3000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 
1c
    PCI: 00:15.1 resource base d0000000 size 100000 align 20 gran 20 limit dfffffff flags 60081
202 index 24
    PCI: 00:15.1 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 i
ndex 20
     PCI: 06:00.0
     PCI: 06:00.0 resource base 3000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
     PCI: 06:00.0 resource base d0004000 size 1000 align 12 gran 12 limit dfffffff flags 600012
01 index 18
     PCI: 06:00.0 resource base d0000000 size 4000 align 14 gran 14 limit dfffffff flags 600012
01 index 20
    PCI: 00:15.2
    PCI: 00:15.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:15.2 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 i
ndex 24
    PCI: 00:15.2 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 i
ndex 20
    PCI: 00:15.3
    PCI: 00:15.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:15.3 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 i
ndex 24
    PCI: 00:15.3 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 i
ndex 20
    PCI: 00:16.0
    PCI: 00:16.0 resource base d8407000 size 1000 align 12 gran 12 limit dfffffff flags 6000020
0 index 10
    PCI: 00:16.2
    PCI: 00:16.2 resource base d8408600 size 100 align 8 gran 8 limit dfffffff flags 60000200 i
ndex 10
    PCI: 00:18.0
    PCI: 00:18.1
    PCI: 00:18.2
    PCI: 00:18.3
    PCI: 00:18.3 resource base d4000000 size 4000000 align 26 gran 26 limit dfffffff flags 6000
0200 index 94
    PCI: 00:18.4
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.3 resource base dc000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000
200 index 94
   PCI: 00:18.4
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1612/3060
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1612/3060
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 1612/3060
PCI: 00:18.4 cmd <- 00
PCI: 00:00.0 subsystem <- 1612/3060
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 07
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 00
PCI: 00:09.0 bridge ctrl <- 0003
PCI: 00:09.0 cmd <- 07
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 06
PCI: 00:11.0 subsystem <- 1612/3060
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 cmd <- 02
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 cmd <- 02
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1612/3060
PCI: 00:14.0 cmd <- 403
PCI: 00:14.1 subsystem <- 1612/3060
PCI: 00:14.1 cmd <- 01
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 cmd <- 0f
PCI: 00:14.5 cmd <- 02
PCI: 00:15.0 bridge ctrl <- 0003
PCI: 00:15.0 cmd <- 00
PCI: 00:15.1 bridge ctrl <- 0003
PCI: 00:15.1 cmd <- 07
PCI: 00:15.2 bridge ctrl <- 0003
PCI: 00:15.2 cmd <- 00
PCI: 00:15.3 bridge ctrl <- 0003
PCI: 00:15.3 cmd <- 00
PCI: 00:16.0 cmd <- 02
PCI: 00:16.2 cmd <- 02
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 cmd <- 00
PCI: 01:05.0 cmd <- 03
PCI: 01:05.1 cmd <- 02
PCI: 03:00.0 cmd <- 03
PCI: 03:00.1 cmd <- 03
PCI: 04:00.0 cmd <- 02
PCI: 06:00.0 cmd <- 03
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00000000, offset=0x00210000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device 100fa0
CPU: family 10, model 0a, stepping 00
nodeid = 00, coreid = 00
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 4096MB, range:  512MB, type WB
Setting variable MTRR 1, base: 4608MB, range:  256MB, type WB
Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
CPU model: AMD Processor model unknown
siblings = 05, CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
CPU: vendor AMD device 100fa0
CPU: family 10, model 0a, stepping 00
nodeid = 00, coreid = 01
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 4096MB, range:  512MB, type WB
Setting variable MTRR 1, base: 4608MB, range:  256MB, type WB
Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x01 done.
CPU model: AMD Processor model unknown
siblings = 05, CPU #1 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 2.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #2
CPU: vendor AMD device 100fa0
CPU: family 10, model 0a, stepping 00
nodeid = 00, coreid = 02
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 4096MB, range:  512MB, type WB
Setting variable MTRR 1, base: 4608MB, range:  256MB, type WB
Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x02 done.
CPU model: AMD Processor model unknown
siblings = 05, CPU #2 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #3
CPU: vendor AMD device 100fa0
CPU: family 10, model 0a, stepping 00
nodeid = 00, coreid = 03
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 4096MB, range:  512MB, type WB
Setting variable MTRR 1, base: 4608MB, range:  256MB, type WB
Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x03 done.
CPU model: AMD Processor model unknown
siblings = 05, CPU #3 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 4.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #4
CPU: vendor AMD device 100fa0
CPU: family 10, model 0a, stepping 00
nodeid = 00, coreid = 04
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 4096MB, range:  512MB, type WB
Setting variable MTRR 1, base: 4608MB, range:  256MB, type WB
Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x04 done.
CPU model: AMD Processor model unknown
siblings = 05, CPU #4 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 5.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #5
Waiting for 1 CPUS to stop
CPU: vendor AMD device 100fa0
CPU: family 10, model 0a, stepping 00
nodeid = 00, coreid = 05
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 4096MB, range:  512MB, type WB
Setting variable MTRR 1, base: 4608MB, range:  256MB, type WB
Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x05 done.
CPU model: AMD Processor model unknown
siblings = 05, CPU #5 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:18.1 init
Searching for pci1022,1201.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1022,1201.rom'.
PCI: 00:18.2 init
Searching for pci1022,1202.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1022,1202.rom'.
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:18.4 init
Searching for pci1022,1204.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1022,1204.rom'.
PCI: 00:00.0 init
Searching for pci1022,9601.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1022,9601.rom'.
PCI: 00:11.0 init
Searching for pci1002,4390.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1002,4390.rom'.
PCI: 00:12.0 init
PCI: 00:12.2 init
PCI: 00:13.0 init
PCI: 00:13.2 init
PCI: 00:14.0 init
Searching for pci1002,4385.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1002,4385.rom'.
PCI: 00:14.1 init
Searching for pci1002,439c.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1002,439c.rom'.
PCI: 00:14.2 init
PCI: 00:14.3 init
PCI: 00:14.5 init
PCI: 00:15.0 init
PCI: 00:15.1 init
PCI: 00:15.2 init
PCI: 00:15.3 init
PCI: 00:16.0 init
PCI: 00:16.2 init
PCI: 00:18.0 init
PCI: 00:18.1 init
Searching for pci1022,1201.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1022,1201.rom'.
PCI: 00:18.2 init
Searching for pci1022,1202.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1022,1202.rom'.
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:18.4 init
Searching for pci1022,1204.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1022,1204.rom'.
PCI: 01:05.0 init
Searching for pci1002,9715.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1002,9715.rom'.
PCI: 01:05.1 init
Searching for pci1002,970f.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1002,970f.rom'.
PCI: 03:00.0 init
Searching for pci1106,3403.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1106,3403.rom'.
PCI: 03:00.1 init
Searching for pci1106,0415.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1106,0415.rom'.
On card, ROM address for PCI: 03:00.1 = d8200000
PCI expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect expansion ROM header signature 0000
PCI: 04:00.0 init
Searching for pci1b21,1042.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci1b21,1042.rom'.
PNP: 002e.2 init
PNP: 002e.5 init
Keyboard init...
No PS/2 keyboard detected.
PCI: 06:00.0 init
Searching for pci10ec,8168.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
No file header found at fffffc00, searching for header
No file header found at fffffc40, searching for header
No file header found at fffffc80, searching for header
No file header found at fffffcc0, searching for header
No file header found at fffffd00, searching for header
No file header found at fffffd40, searching for header
No file header found at fffffd80, searching for header
No file header found at fffffdc0, searching for header
No file header found at fffffe00, searching for header
No file header found at fffffe40, searching for header
No file header found at fffffe80, searching for header
No file header found at fffffec0, searching for header
No file header found at ffffff00, searching for header
No file header found at ffffff40, searching for header
No file header found at ffffff80, searching for header
No file header found at ffffffc0, searching for header
Could not find file 'pci10ec,8168.rom'.
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 0
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PCI: 00:14.4: enabled 0
PCI: 00:14.5: enabled 1
PCI: 00:14.6: enabled 0
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.2: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
APIC: 04: enabled 1
APIC: 05: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 01:05.0: enabled 1
PCI: 01:05.1: enabled 1
PCI: 03:00.0: enabled 1
PCI: 03:00.1: enabled 1
PCI: 04:00.0: enabled 1
PCI: 06:00.0: enabled 1
Initializing CBMEM area to 0xafff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to afff0200...ok
High Tables Base is afff0000.
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0xafff0400...write_pirq_routing_table done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f0594
Adding CBMEM entry as no. 3
Wrote the mp table end at: afff1410 - afff1594
MP table: 404 bytes.
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at afff2400...
ACPI:    * HPET at afff24c8
ACPI: added table 1/32, length now 40
ACPI:    * MADT at afff2500
ACPI: added table 2/32, length now 44
ACPI:    * SRAT at afff2580
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
SRAT: lapic cpu_index=04, node_id=00, apic_id=04
SRAT: lapic cpu_index=05, node_id=00, apic_id=05
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=000c0000
ACPI: added table 3/32, length now 48
ACPI:   * SLIT at afff2688
ACPI: added table 4/32, length now 52
ACPI:    * SSDT at afff26c0
ACPI: added table 5/32, length now 56
ACPI:    * SSDT for PState at afff2cf5
ACPI:    * DSDT at afff2cf8
ACPI:    * DSDT @ afff2cf8 Length 288b
ACPI:	* FACS at afff5588
ACPI:    * FADT at afff55c8
pm_base: 0x0800
ACPI: added table 6/32, length now 60
ACPI: done.
ACPI tables: 12988 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: afffd800
Root Device (ASUS M5A88PM Mainboard)
APIC_CLUSTER: 0 (AMD FAM10 Root Complex)
APIC: 00 (socket AM3)
PCI_DOMAIN: 0000 (AMD FAM10 Root Complex)
PCI: 00:18.0 (AMD FAM10 Northbridge)
PCI: 00:00.0 (ATI RS780)
PCI: 00:01.0 (ATI RS780)
PCI: 00:02.0 (ATI RS780)
PCI: 00:03.0 (ATI RS780)
PCI: 00:04.0 (ATI RS780)
PCI: 00:05.0 (ATI RS780)
PCI: 00:06.0 (ATI RS780)
PCI: 00:07.0 (ATI RS780)
PCI: 00:08.0 (ATI RS780)
PCI: 00:09.0 (ATI RS780)
PCI: 00:0a.0 (ATI RS780)
PCI: 00:11.0 (ATI SB800)
PCI: 00:12.0 (ATI SB800)
PCI: 00:12.2 (ATI SB800)
PCI: 00:13.0 (ATI SB800)
PCI: 00:13.2 (ATI SB800)
PCI: 00:14.0 (ATI SB800)
I2C: 00:50 ()
I2C: 00:51 ()
I2C: 00:52 ()
I2C: 00:53 ()
PCI: 00:14.1 (ATI SB800)
PCI: 00:14.2 (ATI SB800)
PCI: 00:14.3 (ATI SB800)
PNP: 002e.0 (ITE IT8721F Super I/O)
PNP: 002e.1 (ITE IT8721F Super I/O)
PNP: 002e.2 (ITE IT8721F Super I/O)
PNP: 002e.3 (ITE IT8721F Super I/O)
PNP: 002e.5 (ITE IT8721F Super I/O)
PNP: 002e.6 (ITE IT8721F Super I/O)
PNP: 002e.7 (ITE IT8721F Super I/O)
PNP: 002e.8 (ITE IT8721F Super I/O)
PNP: 002e.9 (ITE IT8721F Super I/O)
PNP: 002e.a (ITE IT8721F Super I/O)
PNP: 002e.b (ITE IT8721F Super I/O)
PCI: 00:14.4 (ATI SB800)
PCI: 00:14.5 (ATI SB800)
PCI: 00:14.6 (ATI SB800)
PCI: 00:15.0 (ATI SB800)
PCI: 00:15.1 (ATI SB800)
PCI: 00:15.2 (ATI SB800)
PCI: 00:15.3 (ATI SB800)
PCI: 00:16.0 (ATI SB800)
PCI: 00:16.2 (ATI SB800)
PCI: 00:18.1 (AMD FAM10 Northbridge)
PCI: 00:18.2 (AMD FAM10 Northbridge)
PCI: 00:18.3 (AMD FAM10 Northbridge)
PCI: 00:18.4 (AMD FAM10 Northbridge)
APIC: 01 ()
APIC: 02 ()
APIC: 03 ()
APIC: 04 ()
APIC: 05 ()
PCI: 00:18.0 ()
PCI: 00:18.1 ()
PCI: 00:18.2 ()
PCI: 00:18.3 ()
PCI: 00:18.4 ()
PCI: 01:05.0 ()
PCI: 01:05.1 ()
PCI: 03:00.0 ()
PCI: 03:00.1 ()
PCI: 04:00.0 ()
PCI: 06:00.0 ()
SMBIOS tables: 272 bytes.
Adding CBMEM entry as no. 6
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum 6fde
New low_table_end: 0x00000518
Now going to write high coreboot table at 0xafffe000
rom_table_end = 0xafffe000
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0xafffe000 to 0xb0000000 
Adding high table area
uma_memory_start=0xb0000000, uma_memory_size=0x10000000 
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-00000000affeffff: RAM
 3. 00000000afff0000-00000000afffffff: CONFIGURATION TABLES
 4. 00000000b0000000-00000000bfffffff: RESERVED
 5. 00000000e0000000-00000000efffffff: RESERVED
 6. 0000000100000000-000000012fffffff: RAM
Wrote coreboot table at: afffe000 - afffe204  checksum c7c2
coreboot table: 516 bytes.
Multiboot Information structure has been written.
 0. FREE SPACE b0000000 00000000
 1. GDT        afff0200 00000200
 2. IRQ TABLE  afff0400 00001000
 3. SMP TABLE  afff1400 00001000
 4. ACPI       afff2400 0000b400
 5. SMBIOS     afffd800 00000800
 6. COREBOOT   afffe000 00002000
Searching for fallback/payload
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Got a payload
Loading segment from rom address 0xffe2b5b8
  data (compression=1)
  New segment dstaddr 0xe8670 memsize 0x17990 srcaddr 0xffe2b5f0 filesize 0xbecb
  (cleaned up) New segment addr 0xe8670 size 0x17990 offset 0xffe2b5f0 filesize 0xbecb
Loading segment from rom address 0xffe2b5d4
  Entry Point 0x000fc4e7
Loading Segment: addr: 0x00000000000e8670 memsz: 0x0000000000017990 filesz: 0x000000000000becb
lb: [0x0000000000200000, 0x0000000000328000)
Post relocation: addr: 0x00000000000e8670 memsz: 0x0000000000017990 filesz: 0x000000000000becb
using LZMA
[ 0x000e8670, 00100000, 0x00100000) <- ffe2b5f0
dest 000e8670, end 00100000, bouncebuffer afda0000
Loaded segments
Jumping to boot code at fc4e7
entry    = 0x000fc4e7
lb_start = 0x00200000
lb_size  = 0x00128000
adjust   = 0xafcc8000
buffer   = 0xafda0000
     elf_boot_notes = 0x0021fa20
adjusted_boot_notes = 0xafee7a20
Start bios (version pre-0.6.2-20110903_235549-linux-rvv5.cn.oracle.com)
Found mainboard ASUS M5A88PM
Found CBFS header at 0xfffffbee
Ram Size=0xafff0000 (0x0000000030000000 high)
Relocating init from 0x000e8be0 to 0xaffd6450 (size 39560)
CPU Mhz=800
Found 6 cpu(s) max supported 6 cpu(s)
Copying PIR from 0xafff0400 to 0x000fd790
Copying MPTABLE from 0xafff1400/afff1410 to 0x000fd5f0
Copying ACPI RSDP from 0xafff2400 to 0x000fd5d0
SMBIOS ptr=0x000fd5b0 table=0xaffefdf0
Scan for VGA option rom
EHCI init on dev 00:12.2 (regs=0xd8408420)
EHCI init on dev 00:13.2 (regs=0xd8408520)
OHCI init on dev 00:14.5 (regs=0xd8406000)
EHCI init on dev 00:16.2 (regs=0xd8408620)
Found 0 lpt ports
Found 2 serial ports
ATA controller 0 at 4020/4040/0 (irq 0 dev 88)
ATA controller 1 at 4028/4044/0 (irq 0 dev 88)
ATA controller 2 at 1f0/3f4/0 (irq 14 dev a1)
ATA controller 3 at 170/374/0 (irq 15 dev a1)
ATA controller 4 at 2410/2420/0 (irq 0 dev 301)
ATA controller 5 at 2418/2424/0 (irq 0 dev 301)
ata1-0: ST3250620NS ATA-7 Hard-Disk (232 GiBytes)
Searching bootorder for: /pci at i0cf8/*@11/drive at 1/disk at 0
Got ps2 nak (status=51)
All threads complete.
Scan for option roms
Press F12 for boot menu.

drive 0x000fd520: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=488397168
Returned 61440 bytes of ZoneHigh
e820 map has 7 items:
  0: 0000000000000000 - 000000000009fc00 = 1
  1: 000000000009fc00 - 00000000000a0000 = 2
  2: 00000000000f0000 - 0000000000100000 = 2
  3: 0000000000100000 - 00000000affef000 = 1
  4: 00000000affef000 - 00000000c0000000 = 2
  5: 00000000e0000000 - 00000000f0000000 = 2
  6: 0000000100000000 - 0000000130000000 = 1
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00
pnp call arg1=0

From harald.gutmann at gmx.net  Tue Sep  6 17:42:49 2011
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Tue, 6 Sep 2011 17:42:49 +0200
Subject: [coreboot] MSI 890-GXM-G65 (MS-7642) support / any interested users?
Message-ID: <201109061742.49930.harald.gutmann@gmx.net>

Hello!

I recently bought the above mentionend mainboard and it is used in my new 
desktop computer.

As I used bevore the Gigabyte M57SLI-S4 I'd really like to see coreboot 
support again on my new mainboard.

Actually I'm not fully up to date with the shape of coreboot and it supported 
components but I think it should be possible to get this board working with 
coreboot.

Matthias Mattsson asked for coreboot support of this mainboard some while ago, 
but these days the SB880 was supported. I think now this platform should be 
supported.

The recent flashrom version finds the following:
Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 
0x4015
Chip status register is 00
Found Winbond flash chip "W25Q16" (2048 kB, SPI) at physical address 0xffe00000.

Therefore I guess that flashrom support should be fine, but it is as of now 
untested.

lspci gives the following components:
00:00.0 Host bridge: Advanced Micro Devices [AMD] RS880 Host Bridge
00:01.0 PCI bridge: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge 
(int gfx)
00:05.0 PCI bridge: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE 
port 1)
00:06.0 PCI bridge: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE 
port 2)
00:11.0 SATA controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA 
Controller [AHCI mode] (rev 40)
00:12.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 
Controller
00:12.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI 
Controller
00:13.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 
Controller
00:13.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI 
Controller
00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 42)
00:14.3 ISA bridge: ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host controller 
(rev 40)
00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge (rev 40)
00:14.5 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2 
Controller
00:15.0 PCI bridge: ATI Technologies Inc SB700/SB800 PCI to PCI bridge (PCIE 
port 0)
00:16.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 
Controller
00:16.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI 
Controller
00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor 
HyperTransport Configuration
00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address 
Map
00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM 
Controller
00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor 
Miscellaneous Control
00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link 
Control
01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4290]
01:05.1 Audio device: ATI Technologies Inc RS880 Audio Device [Radeon HD 4200]
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI 
Express Gigabit Ethernet controller (rev 03)
03:00.0 USB Controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 
03)
04:05.0 Multimedia audio controller: VIA Technologies Inc. ICE1712 [Envy24] 
PCI Multi-Channel I/O Controller (rev 02)
05:00.0 IDE interface: JMicron Technology Corp. JMB368 IDE controller

This should be an RS880/RS890 northbridge. The processor is fam10h.


Can anyone give me a statement if there is already a similar board working or 
which board would be the best starting point to look at?

Any hints and recommendations are welcome.



Kind regards,
Harald Gutmann




From wangqingpei at gmail.com  Tue Sep  6 18:18:12 2011
From: wangqingpei at gmail.com (QingPei Wang)
Date: Wed, 7 Sep 2011 00:18:12 +0800
Subject: [coreboot] MSI 890-GXM-G65 (MS-7642) support / any interested
	users?
In-Reply-To: <201109061742.49930.harald.gutmann@gmx.net>
References: <201109061742.49930.harald.gutmann@gmx.net>
Message-ID: <CADuV8k5g_+cPytdPCR4Tg8JL1fPq5Jjjn5XhychA2dgTUAyB3g@mail.gmail.com>

hi,
  just take a look at the patch which i just send, it's ASUS M5A88-V, much
the same as yours


Best wishes
Wang Qing Pei
Phone: 86+018930528086


On Tue, Sep 6, 2011 at 11:42 PM, Harald Gutmann <harald.gutmann at gmx.net>wrote:

> Hello!
>
> I recently bought the above mentionend mainboard and it is used in my new
> desktop computer.
>
> As I used bevore the Gigabyte M57SLI-S4 I'd really like to see coreboot
> support again on my new mainboard.
>
> Actually I'm not fully up to date with the shape of coreboot and it
> supported
> components but I think it should be possible to get this board working with
> coreboot.
>
> Matthias Mattsson asked for coreboot support of this mainboard some while
> ago,
> but these days the SB880 was supported. I think now this platform should be
> supported.
>
> The recent flashrom version finds the following:
> Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2
> 0x4015
> Chip status register is 00
> Found Winbond flash chip "W25Q16" (2048 kB, SPI) at physical address
> 0xffe00000.
>
> Therefore I guess that flashrom support should be fine, but it is as of now
> untested.
>
> lspci gives the following components:
> 00:00.0 Host bridge: Advanced Micro Devices [AMD] RS880 Host Bridge
> 00:01.0 PCI bridge: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI
> bridge
> (int gfx)
> 00:05.0 PCI bridge: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge
> (PCIE
> port 1)
> 00:06.0 PCI bridge: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge
> (PCIE
> port 2)
> 00:11.0 SATA controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA
> Controller [AHCI mode] (rev 40)
> 00:12.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0
> Controller
> 00:12.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI
> Controller
> 00:13.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0
> Controller
> 00:13.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI
> Controller
> 00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 42)
> 00:14.3 ISA bridge: ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host
> controller
> (rev 40)
> 00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge (rev 40)
> 00:14.5 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2
> Controller
> 00:15.0 PCI bridge: ATI Technologies Inc SB700/SB800 PCI to PCI bridge
> (PCIE
> port 0)
> 00:16.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0
> Controller
> 00:16.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI
> Controller
> 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor
> HyperTransport Configuration
> 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor
> Address
> Map
> 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM
> Controller
> 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor
> Miscellaneous Control
> 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link
> Control
> 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD
> 4290]
> 01:05.1 Audio device: ATI Technologies Inc RS880 Audio Device [Radeon HD
> 4200]
> 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
> PCI
> Express Gigabit Ethernet controller (rev 03)
> 03:00.0 USB Controller: NEC Corporation uPD720200 USB 3.0 Host Controller
> (rev
> 03)
> 04:05.0 Multimedia audio controller: VIA Technologies Inc. ICE1712 [Envy24]
> PCI Multi-Channel I/O Controller (rev 02)
> 05:00.0 IDE interface: JMicron Technology Corp. JMB368 IDE controller
>
> This should be an RS880/RS890 northbridge. The processor is fam10h.
>
>
> Can anyone give me a statement if there is already a similar board working
> or
> which board would be the best starting point to look at?
>
> Any hints and recommendations are welcome.
>
>
>
> Kind regards,
> Harald Gutmann
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From gerrit at coreboot.org  Wed Sep  7 01:08:58 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 01:08:58 +0200
Subject: [coreboot] Patch merged into coreboot/master: 5cb524a AMD F14
	southbridge update
References: <Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e+0@gerrit.coreboot.org>
Message-ID: <E1R14lG-0007zp-AL@ra.coresystems.de>

the following patch was just integrated into master:
commit 5cb524a357dc0c3b4f959ca44a50b00c1dd76b77
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Aug 18 18:03:44 2011 +0800

    AMD F14 southbridge update
    
    This change adds the southbridge related code to support
    the update of the AMD Family14 cpus to the rec C0 level.
    Some of the changes reside in mainboard folders but they
    reference changed files in the southbridge folder so they
    are included herein.
    
    Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
    Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
    Signed-off-by: efdesign98 <efdesign98 at gmail.com>
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>

See http://review.coreboot.org/135 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 01:10:07 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 01:10:07 +0200
Subject: [coreboot] Patch merged into coreboot/master: 5c1e354 AMD SB800
	southbridge update
References: <I2176885549277b335c0c41b48457d09b9b76b703+0@gerrit.coreboot.org>
Message-ID: <E1R14mN-0008Ik-2J@ra.coresystems.de>

the following patch was just integrated into master:
commit 5c1e35472b33b04ff018f500fd719d4b2474be5d
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Aug 18 18:44:00 2011 +0800

    AMD SB800 southbridge update
    
    This patch enables access to the registers of the hardware monitor
    logical device in the superio via isa ports 0x295/0x296.
    Previously this was not enabled in the SB8xx LPC device.
    This is required for initialisation in init_hwm() in
    src/superio/winbond/w83627hf/superio.c and also by OS-level
    sensor monitoring such as lm-sensors to access temperature,
    fan monitoring and control and voltage registers.
    asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.
    
    Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
    Signed-off-by: Per Hansen <perh52 at runbox.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>

See http://review.coreboot.org/159 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 01:10:30 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 01:10:30 +0200
Subject: [coreboot] Patch merged into coreboot/master: 000ea38 AMD F14 Rev
	C0 update
References: <Iacd1c7b20e889da61a2085188766285f27e5c018+0@gerrit.coreboot.org>
Message-ID: <E1R14mk-0008TX-96@ra.coresystems.de>

the following patch was just integrated into master:
commit 000ea3878c8d28dc79897c997f5ca82366542da8
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Aug 18 18:58:40 2011 +0800

    AMD F14 Rev C0 update
    
    Add AMD Family14 Rev C0 cpu id
    
    Change-Id: Iacd1c7b20e889da61a2085188766285f27e5c018
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>

See http://review.coreboot.org/160 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 01:27:58 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 01:27:58 +0200
Subject: [coreboot] Patch merged into coreboot/master: 7700f5d Add support
	utils for tracing
References: <I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5+0@gerrit.coreboot.org>
Message-ID: <E1R153e-0005OR-JG@ra.coresystems.de>

the following patch was just integrated into master:
commit 7700f5df07fd80c65eced4deb7d0c6051fd9f2b6
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Sep 2 23:34:15 2011 +0200

    Add support utils for tracing
    
    Following patch adds a userspace util genprof
    which is able to convert the console printed
    traces to gmon.out file used by gprof & friends.
    The log2dress will replace the adresses in logfile
    with a line numbers.
    
    Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

See http://review.coreboot.org/179 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 01:26:48 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 01:26:48 +0200
Subject: [coreboot] Patch merged into coreboot/master: 5ef3380 Add support
	for the tracing infastructure in coreboot.
References: <I2cbeb3f104892b034c8756f86ed05bf71187c3f3+0@gerrit.coreboot.org>
Message-ID: <E1R152W-0003zP-71@ra.coresystems.de>

the following patch was just integrated into master:
commit 5ef3380428f35b9196ecfe7f52281bb26080c364
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Sep 2 23:23:41 2011 +0200

    Add support for the tracing infastructure in coreboot.
    
    The compiler is forced to emmit special functions on every
    entry/exit of the function. Add a compile time option
    to support it. Function entries will be printed in
    the console. The CONFIG_TRACE has more documentation.
    
    Patch for userspace tools will follow.
    
    Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

See http://review.coreboot.org/178 for details.

-gerrit



From paulepanter at users.sourceforge.net  Wed Sep  7 09:46:14 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 07 Sep 2011 09:46:14 +0200
Subject: [coreboot] New patch to review for coreboot: deb6f0f Add ASUS
 M5A88-V mainboard support
In-Reply-To: <CADuV8k52-fsCVYM_2Kg5Q_0_Zu7D8hy3_0VpRTZ8fSB8zDij7w@mail.gmail.com>
References: <I9725ccdbb25365c4007621318efee80b131fec29+0@gerrit.coreboot.org>
	<I9725ccdbb25365c4007621318efee80b131fec29+1@gerrit.coreboot.org>
	<1315319338.4717.13.camel@mattotaupa>
	<CADuV8k52-fsCVYM_2Kg5Q_0_Zu7D8hy3_0VpRTZ8fSB8zDij7w@mail.gmail.com>
Message-ID: <1315381580.3553.29.camel@mattotaupa>

Dear Quing Pei,


Am Dienstag, den 06.09.2011, 22:42 +0800 schrieb QingPei Wang:

> i tested by my opensuse 11.2 without X windows.

could you just test if X works please so that nobody wanting to buy that
board gets wrong expectations?

Additionally:

Is suspend/resume working?
Are all ports working (hard drive, USB, ?)?
How long does coreboot + payload take on your board to load/initialize?

> the patch is applicable to the former two patches which i sent before.
> And it does not depend on any other patches by AMD at this moment.

Some patches were committed tonight. Could you retest with them please?

> And i am trying to get familiar with gerrit at this moment. I just
> learned how to submit the patches, still does not know how to use "git
> format-patch" things.
> 
> The attachment is a simple boot log with the board. I will cost more time to
> make this better.

A TODO would also be nice. ;-)

> On Tue, Sep 6, 2011 at 10:28 PM, Paul Menzel wrote:

> > Am Dienstag, den 06.09.2011, 15:12 +0200 schrieb QingPei Wang:
> >
> > > commit deb6f0f225bddd2fa786f94689555a21add12d13
> > > Author: QingPei Wang <wangqingpei at gmail.com>
> > > Date:   Tue Sep 6 21:09:40 2011 +0800
> > >
> > >     Add ASUS M5A88-V mainboard support
> > >
> > >     it's a AMD 880+800 mainboard. I port the code
> > >     based on the AMD reference code.

You can use the following Git commands to adapt your patch.

        cd pathtoyourgitcorebootfolder
        
Update the user information (just a suggestion).

        git config --global user.name Quingpei Wang (your Chinese spelling here)
        
Update all remote repositories.

        git fetch

Take a look at the changes.

        git log origin/master # where `origin` is the remote coreboot respository

Checkout your branch with your ASUS M5A88-V stuff.

        git branch # show all local branches
        git checkout m5a88 # substitude m5a88

Put your changes on top of the latest master.

        git rebase origin/master # if there are conflicts, but there should not

Update (amend) the commit message of the last commit to for example add
information, what you have tested.

        git commit --amend -s
        
If you also want to amend files, you have to add the changed file before
amending.

        git add yourfilewithtoamendedchanges
        git add --patch yourfilewithtoamendedchanges # only parts of the
        file
        git commit --amend -s

        git commit -a --amend -s

If you also want to add commits prior to the list one.

        git rebase -i HEAD~8 # number of commits going back

If you need more information the manual pages are also quite good. For
example `git help rebase` opens the manual page for `git rebase`.


Thanks,

Paul


[1] http://review.coreboot.org/#q,status:merged,n,z
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From Kerry.She at amd.com  Wed Sep  7 11:51:11 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Wed, 7 Sep 2011 17:51:11 +0800
Subject: [coreboot]  E350M1 does not POST
Message-ID: <F53A09371FB723428826B442A4B20A410758DECB@sbjgexmb1.amd.com>

 

> -----Original Message-----

> From: coreboot-bounces at coreboot.org [mailto:coreboot- 

> bounces at coreboot.org] On Behalf Of perh52 at runbox.com

> Sent: Friday, August 19, 2011 12:37 AM

> To: coreboot

> Subject: [coreboot] E350M1 does not POST

> 

> >>> Hi,

> >>>

> >>>> Upon booting, I get this:

> >>>

> >>> [...]

> >>>

> >>> you could try commit 0df0e14fb, that may or may not work, the 

> >>> commit

> after

> >>> that broke fusion boards completely, apparently.

> >>>

> >>> Florian

> >>>

> >> Thank you! I can confirm that 0df0e14fb works properly.

> >> -Marshall

> >

> >Frank,

> >

> >It looks like we have a regression. Is there some dependency on the 

> >other patches that have not yet been committed?

> >

> >Marc

> 

> Unfortunately git bisect is no help here because the commit which 

> caused the regression was a huge one.

> 

> It's important that large patches are broken down into a set of small 

> comprehensible patches, each with an explanatory commit message.

> 

> <<quote from git-bisect-lk2009.html documentation>> ...

> sometimes "interesting" changes of behavior in the software are 

> introduced in some commits.

> 

> In fact people are specially interested in commits that introduce a 

> "bad" behavior, called a bug or a regression. They are interested in 

> these commits because a commit (hopefully) contains a very small set 

> of source code changes. And it's much easier to understand and 

> properly fix a problem when you only need to check a very small set of


> changes, than when you don't know where look in the first place.

> 

> So to help people find commits that introduce a "bad" behavior, the 

> "git bisect" set of commands was invented.

 

Hello, All

 

Since commit 84cbce2 cause E350M1 not POST, Following patches should
resolve this regression problem, please see the attachment in detail.

I have test it on a Persimmon mainboard, anybody can have a test on
E350M1?

Thanks

--

Kerry sheh

 

 

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From Kerry.She at amd.com  Wed Sep  7 09:53:26 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Wed, 7 Sep 2011 15:53:26 +0800
Subject: [coreboot] E350M1 does not POST
In-Reply-To: <E1Qu5au-0000TM-Aq@taishi.runbox.com>
References: <E1Qu5au-0000TM-Aq@taishi.runbox.com>
Message-ID: <F53A09371FB723428826B442A4B20A410758DCA9@sbjgexmb1.amd.com>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-
> bounces at coreboot.org] On Behalf Of perh52 at runbox.com
> Sent: Friday, August 19, 2011 12:37 AM
> To: coreboot
> Subject: [coreboot] E350M1 does not POST
> 
> >>> Hi,
> >>>
> >>>> Upon booting, I get this:
> >>>
> >>> [...]
> >>>
> >>> you could try commit 0df0e14fb, that may or may not work, the
commit
> after
> >>> that broke fusion boards completely, apparently.
> >>>
> >>> Florian
> >>>
> >> Thank you! I can confirm that 0df0e14fb works properly.
> >> -Marshall
> >
> >Frank,
> >
> >It looks like we have a regression. Is there some dependency on the
> >other patches that have not yet been committed?
> >
> >Marc
> 
> Unfortunately git bisect is no help here because the commit which
caused
> the regression was a huge one.
> 
> It's important that large patches are broken down into a set of small
> comprehensible patches, each with an explanatory commit message.
> 
> <<quote from git-bisect-lk2009.html documentation>>
> ...
> sometimes "interesting" changes of behavior in the software are
> introduced in some commits.
> 
> In fact people are specially interested in commits that introduce a
> "bad" behavior, called a bug or a regression. They are interested in
> these commits because a commit (hopefully) contains a very small set
> of source code changes. And it's much easier to understand and
> properly fix a problem when you only need to check a very small set of
> changes, than when you don't know where look in the first place.
> 
> So to help people find commits that introduce a "bad" behavior, the
> "git bisect" set of commands was invented.
Hello, All

Since commit 84cbce2 cause E350M1 not POST,
Following patches should resolve this regression problem, please see the
attachment in detail.
I have test it on a Persimmon mainboard, 
anybody can have a test on E350M1?
Thanks
--
Kerry sheh

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From mbuschman at lucidmachines.com  Wed Sep  7 18:38:47 2011
From: mbuschman at lucidmachines.com (Marshall Buschman)
Date: Wed, 07 Sep 2011 11:38:47 -0500
Subject: [coreboot] E350M1 does not POST
In-Reply-To: <F53A09371FB723428826B442A4B20A410758DCA9@sbjgexmb1.amd.com>
References: <E1Qu5au-0000TM-Aq@taishi.runbox.com>
	<F53A09371FB723428826B442A4B20A410758DCA9@sbjgexmb1.amd.com>
Message-ID: <4E679E17.7070902@lucidmachines.com>

I have access to an E350M1. I will test these patches tonight and report 
back with results.

Thank you!
-Marshall Buschman

On 09/07/2011 02:53 AM, She, Kerry wrote:
>
>> -----Original Message-----
>> From: coreboot-bounces at coreboot.org [mailto:coreboot-
>> bounces at coreboot.org] On Behalf Of perh52 at runbox.com
>> Sent: Friday, August 19, 2011 12:37 AM
>> To: coreboot
>> Subject: [coreboot] E350M1 does not POST
>>
>>>>> Hi,
>>>>>
>>>>>> Upon booting, I get this:
>>>>> [...]
>>>>>
>>>>> you could try commit 0df0e14fb, that may or may not work, the
> commit
>> after
>>>>> that broke fusion boards completely, apparently.
>>>>>
>>>>> Florian
>>>>>
>>>> Thank you! I can confirm that 0df0e14fb works properly.
>>>> -Marshall
>>> Frank,
>>>
>>> It looks like we have a regression. Is there some dependency on the
>>> other patches that have not yet been committed?
>>>
>>> Marc
>> Unfortunately git bisect is no help here because the commit which
> caused
>> the regression was a huge one.
>>
>> It's important that large patches are broken down into a set of small
>> comprehensible patches, each with an explanatory commit message.
>>
>> <<quote from git-bisect-lk2009.html documentation>>
>> ...
>> sometimes "interesting" changes of behavior in the software are
>> introduced in some commits.
>>
>> In fact people are specially interested in commits that introduce a
>> "bad" behavior, called a bug or a regression. They are interested in
>> these commits because a commit (hopefully) contains a very small set
>> of source code changes. And it's much easier to understand and
>> properly fix a problem when you only need to check a very small set of
>> changes, than when you don't know where look in the first place.
>>
>> So to help people find commits that introduce a "bad" behavior, the
>> "git bisect" set of commands was invented.
> Hello, All
>
> Since commit 84cbce2 cause E350M1 not POST,
> Following patches should resolve this regression problem, please see the
> attachment in detail.
> I have test it on a Persimmon mainboard,
> anybody can have a test on E350M1?
> Thanks
> --
> Kerry sheh
>
>
>

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From stefanb at linux.vnet.ibm.com  Wed Sep  7 16:30:02 2011
From: stefanb at linux.vnet.ibm.com (Stefan Berger)
Date: Wed, 07 Sep 2011 10:30:02 -0400
Subject: [coreboot] TPM support for SeaBIOS -- looking for a tester on real
	hardware
Message-ID: <4E677FEA.1060503@linux.vnet.ibm.com>

Hello!

   Would anybody be interested in testing the TPM support I added to 
SeaBIOS. I unfortunately don't have a motherboard myself where I could 
try it. I have added the support to SeaBIOS for the TPM device model in 
Qemu.  What you would need for trying it is a motherboard with a TPM 1.2 
on it. The SeaBIOS TPM support should recognize it, initialize the TPM 
and allow the user to enter another SeaBIOS menu.

Regards,
    Stefan




From gerrit at coreboot.org  Wed Sep  7 22:16:52 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 22:16:52 +0200
Subject: [coreboot] Patch merged into filo/master: 79c690a Simplify kconfig
	handling some more
References: <I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8+0@gerrit.coreboot.org>
Message-ID: <E1R1OYG-0000tf-IG@ra.coresystems.de>

the following patch was just integrated into master:
commit 79c690a5e0b60f318837f152df0f7baf412f2149
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Sep 3 13:29:27 2011 +0200

    Simplify kconfig handling some more
    
    Inspired by http://patchwork.coreboot.org/patch/1757/, this
    simplifies the build some more.
    Also fixes menuconfig if the compiler is picky about file naming order.
    
    Change-Id: I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/180 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 22:18:17 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 22:18:17 +0200
Subject: [coreboot] Patch merged into filo/master: e4f93b2 Show root device
	we're booted from in header.
References: <I9288f88f6673fafa41d13f2035ea3b9b6550dbb2+0@gerrit.coreboot.org>
Message-ID: <E1R1OZd-0001Cw-MS@ra.coresystems.de>

the following patch was just integrated into master:
commit e4f93b2957a293efea945dac6566547ede17b591
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 12:05:40 2010 +0100

    Show root device we're booted from in header.
    
    Change-Id: I9288f88f6673fafa41d13f2035ea3b9b6550dbb2
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/201 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 22:19:57 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 22:19:57 +0200
Subject: [coreboot] Patch merged into filo/master: e6e5a03 More compatible
	use of mktemp
References: <I961a7ddcd39657c9463806d7b82757eff0a4ac57+0@gerrit.coreboot.org>
Message-ID: <E1R1ObF-0002AN-AB@ra.coresystems.de>

the following patch was just integrated into master:
commit e6e5a03bca182471fa00d937c3235ac00ef0234e
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Sep 1 09:16:37 2011 +0200

    More compatible use of mktemp
    
    Change-Id: I961a7ddcd39657c9463806d7b82757eff0a4ac57
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/190 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 22:20:41 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 22:20:41 +0200
Subject: [coreboot] Patch merged into filo/master: 0ca6ae9 Show which file
	cannot be openend in file_open(), eases debuging.
References: <I06fd3576aa3443588e67234bce748f533c36a8ff+0@gerrit.coreboot.org>
Message-ID: <E1R1Obx-0002a5-Lb@ra.coresystems.de>

the following patch was just integrated into master:
commit 0ca6ae94bb6be913aef972b93e8e1a05f98cdfad
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Thu Jun 3 15:39:46 2010 +0200

    Show which file cannot be openend in file_open(), eases debuging.
    
    Change-Id: I06fd3576aa3443588e67234bce748f533c36a8ff
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/193 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 22:24:06 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Sep 2011 22:24:06 +0200
Subject: [coreboot] Patch set updated for filo: 521f67f Trivial compilation
	fix
References: <I9e1ef711b62a42b1ddbd620d09a9c19a6e1ff0db+0@gerrit.coreboot.org>
Message-ID: <I9e1ef711b62a42b1ddbd620d09a9c19a6e1ff0db+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/181

-gerrit

commit 521f67f31f65e07ed91b24512d0af71abb0ec0bb
Author: Aur?lien <footplus at gmail.com>
Date:   Thu Sep 9 18:39:10 2010 +0200

    Trivial compilation fix
    
    Change-Id: I9e1ef711b62a42b1ddbd620d09a9c19a6e1ff0db
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 main/grub/completions.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/main/grub/completions.c b/main/grub/completions.c
index 161026b..a3aeba2 100644
--- a/main/grub/completions.c
+++ b/main/grub/completions.c
@@ -23,6 +23,7 @@
 #include <config.h>
 #include <grub/shared.h>
 #define current_slice 0
+#define IS_PC_SLICE_TYPE_BSD(type) 0
 
 static int do_completion;
 static int unique;



From gerrit at coreboot.org  Wed Sep  7 22:25:03 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Sep 2011 22:25:03 +0200
Subject: [coreboot] Patch set updated for filo: ed521a9 Add multiboot header
References: <Ibe8e879a3a6f533f97aa8381697afb1f14d1f87d+0@gerrit.coreboot.org>
Message-ID: <Ibe8e879a3a6f533f97aa8381697afb1f14d1f87d+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/197

-gerrit

commit ed521a9675301224fbc6e27dd4ce3d85e9370d14
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Jun 7 13:53:31 2011 +0200

    Add multiboot header
    
    Change-Id: Ibe8e879a3a6f533f97aa8381697afb1f14d1f87d
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 Config.in         |    7 +++++++
 i386/ldscript     |    2 +-
 main/Makefile.inc |    1 +
 main/mb_hdr.c     |   32 ++++++++++++++++++++++++++++++++
 4 files changed, 41 insertions(+), 1 deletions(-)

diff --git a/Config.in b/Config.in
index 8981a48..a8cbfbb 100644
--- a/Config.in
+++ b/Config.in
@@ -9,6 +9,13 @@ config TARGET_I386
 	bool
 	default y
 
+config MULTIBOOT_IMAGE
+	bool "Include a MultiBoot header"
+	default y
+	help
+	  Including a MultiBoot header makes FILO chainloadable by MultiBoot
+	  compliant boot loaders like GRUB.
+
 menu "Interface Options"
 
 config USE_GRUB
diff --git a/i386/ldscript b/i386/ldscript
index 7fba856..b260c51 100644
--- a/i386/ldscript
+++ b/i386/ldscript
@@ -40,7 +40,7 @@ SECTIONS
     /* Start of the program. 
      * Now the version string is in the note, we must include it
      * in the program. Otherwise we lose the string after relocation. */
-    . = ALIGN(16);
+    . = ALIGN(4096);
     _start = .;
 
     /* Putting ELF notes near beginning of file might help bootloaders.
diff --git a/main/Makefile.inc b/main/Makefile.inc
index c7290cf..e2fab04 100644
--- a/main/Makefile.inc
+++ b/main/Makefile.inc
@@ -16,6 +16,7 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
+TARGETS-$(CONFIG_MULTIBOOT_IMAGE) += main/mb_hdr.o
 TARGETS-y += main/filo.o main/strtox.o
 TARGETS-y += main/elfload.o main/ipchecksum.o 
 TARGETS-$(CONFIG_SUPPORT_SOUND) += main/sound.o
diff --git a/main/mb_hdr.c b/main/mb_hdr.c
new file mode 100644
index 0000000..bb01427
--- /dev/null
+++ b/main/mb_hdr.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of FILO.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Support for MultiBoot */
+#define MB_HEADER_MAGIC		0x1BADB002
+#define MB_RQ_FLAGS_4K		1
+#define MB_REQUESTED_FLAGS	(MB_RQ_FLAGS_4K)
+
+/* this header is parsed by the boot loader that loads FILO, e.g. GRUB */
+struct mb_header {
+	long magic;		/* multiboot magic */
+	long features;	/* requested features */
+	long chksum;	/* chksum for whole structure */
+} mb_header __attribute__((section(".hdr.mb"))) = {
+	.magic = MB_HEADER_MAGIC,
+	.features = MB_REQUESTED_FLAGS,
+	.chksum = -(MB_HEADER_MAGIC + MB_REQUESTED_FLAGS),
+};



From gerrit at coreboot.org  Wed Sep  7 22:26:21 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Sep 2011 22:26:21 +0200
Subject: [coreboot] Patch set updated for filo: c6906e3 Unlock ATAPI devices
	on boot
References: <I4f2a0ddafac2debe0a1564904f37025850cc519e+0@gerrit.coreboot.org>
Message-ID: <I4f2a0ddafac2debe0a1564904f37025850cc519e+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/192

-gerrit

commit c6906e35334a7383706cb5933d688292f39c8de8
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Aug 24 11:07:21 2010 +0200

    Unlock ATAPI devices on boot
    
    This makes CD/DVD drives accessible that were locked prior to a
    reboot.
    
    Change-Id: I4f2a0ddafac2debe0a1564904f37025850cc519e
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 drivers/ide_new.c |   13 +++++++++++++
 drivers/ide_new.h |    1 +
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/drivers/ide_new.c b/drivers/ide_new.c
index 4f612be..e034d6e 100644
--- a/drivers/ide_new.c
+++ b/drivers/ide_new.c
@@ -658,6 +658,19 @@ ob_ide_atapi_drive_ready(struct ide_drive *drive)
 		return 1;
 	}
 
+	/* clear Persistent Prevent State */
+	memset (cmd, 0, sizeof(*cmd));
+	cmd->cdb[0] = ATAPI_PREVENT_ALLOW_MEDIUM_REMOVAL;
+	cmd->cdb[2] = 2;
+	if (ob_ide_atapi_packet(drive, cmd))
+		printf("could not persistently unlock device\n");
+
+	/* clear Prevent State */
+	memset (cmd, 0, sizeof(*cmd));
+	cmd->cdb[0] = ATAPI_PREVENT_ALLOW_MEDIUM_REMOVAL;
+	if (ob_ide_atapi_packet(drive, cmd))
+		printf("could not unlock device\n");
+
 	/*
 	 * finally, get capacity and block size
 	 */
diff --git a/drivers/ide_new.h b/drivers/ide_new.h
index 8d3979a..f667e41 100644
--- a/drivers/ide_new.h
+++ b/drivers/ide_new.h
@@ -70,6 +70,7 @@
 #define ATAPI_READ_10		0x28
 #define ATAPI_REQ_SENSE		0x03
 #define ATAPI_START_STOP_UNIT	0x1b
+#define ATAPI_PREVENT_ALLOW_MEDIUM_REMOVAL  0x1e
 #define ATAPI_READ_CAPACITY	0x25
 
 /*



From gerrit at coreboot.org  Wed Sep  7 22:27:24 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 22:27:24 +0200
Subject: [coreboot] Patch merged into filo/master: 521f67f Trivial
	compilation fix
References: <I9e1ef711b62a42b1ddbd620d09a9c19a6e1ff0db+0@gerrit.coreboot.org>
Message-ID: <E1R1OiS-00060z-2c@ra.coresystems.de>

the following patch was just integrated into master:
commit 521f67f31f65e07ed91b24512d0af71abb0ec0bb
Author: Aur??lien <footplus at gmail.com>
Date:   Thu Sep 9 18:39:10 2010 +0200

    Trivial compilation fix
    
    Change-Id: I9e1ef711b62a42b1ddbd620d09a9c19a6e1ff0db
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/181 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 22:28:27 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 22:28:27 +0200
Subject: [coreboot] Patch merged into filo/master: ed521a9 Add multiboot
	header
References: <Ibe8e879a3a6f533f97aa8381697afb1f14d1f87d+0@gerrit.coreboot.org>
Message-ID: <E1R1OjT-0006d7-RY@ra.coresystems.de>

the following patch was just integrated into master:
commit ed521a9675301224fbc6e27dd4ce3d85e9370d14
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Jun 7 13:53:31 2011 +0200

    Add multiboot header
    
    Change-Id: Ibe8e879a3a6f533f97aa8381697afb1f14d1f87d
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/197 for details.

-gerrit



From gerrit at coreboot.org  Wed Sep  7 22:29:07 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Sep 2011 22:29:07 +0200
Subject: [coreboot] Patch merged into filo/master: c6906e3 Unlock ATAPI
	devices on boot
References: <I4f2a0ddafac2debe0a1564904f37025850cc519e+0@gerrit.coreboot.org>
Message-ID: <E1R1Ok7-000774-00@ra.coresystems.de>

the following patch was just integrated into master:
commit c6906e35334a7383706cb5933d688292f39c8de8
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Aug 24 11:07:21 2010 +0200

    Unlock ATAPI devices on boot
    
    This makes CD/DVD drives accessible that were locked prior to a
    reboot.
    
    Change-Id: I4f2a0ddafac2debe0a1564904f37025850cc519e
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/192 for details.

-gerrit



From mbuschman at lucidmachines.com  Thu Sep  8 04:01:42 2011
From: mbuschman at lucidmachines.com (Marshall Buschman)
Date: Wed, 07 Sep 2011 21:01:42 -0500
Subject: [coreboot] E350M1 does not POST
In-Reply-To: <4E679E17.7070902@lucidmachines.com>
References: <E1Qu5au-0000TM-Aq@taishi.runbox.com>
	<F53A09371FB723428826B442A4B20A410758DCA9@sbjgexmb1.amd.com>
	<4E679E17.7070902@lucidmachines.com>
Message-ID: <4E682206.9090808@lucidmachines.com>

On 09/07/2011 11:38 AM, Marshall Buschman wrote:
> I have access to an E350M1. I will test these patches tonight and 
> report back with results.
>
> Thank you!
> -Marshall Buschman
>
> On 09/07/2011 02:53 AM, She, Kerry wrote:
>>> -----Original Message-----
>>> From:coreboot-bounces at coreboot.org  [mailto:coreboot-
>>> bounces at coreboot.org] On Behalf Ofperh52 at runbox.com
>>> Sent: Friday, August 19, 2011 12:37 AM
>>> To: coreboot
>>> Subject: [coreboot] E350M1 does not POST
>>>
>>>>>> Hi,
>>>>>>
>>>>>>> Upon booting, I get this:
>>>>>> [...]
>>>>>>
>>>>>> you could try commit 0df0e14fb, that may or may not work, the
>> commit
>>> after
>>>>>> that broke fusion boards completely, apparently.
>>>>>>
>>>>>> Florian
>>>>>>
>>>>> Thank you! I can confirm that 0df0e14fb works properly.
>>>>> -Marshall
>>>> Frank,
>>>>
>>>> It looks like we have a regression. Is there some dependency on the
>>>> other patches that have not yet been committed?
>>>>
>>>> Marc
>>> Unfortunately git bisect is no help here because the commit which
>> caused
>>> the regression was a huge one.
>>>
>>> It's important that large patches are broken down into a set of small
>>> comprehensible patches, each with an explanatory commit message.
>>>
>>> <<quote from git-bisect-lk2009.html documentation>>
>>> ...
>>> sometimes "interesting" changes of behavior in the software are
>>> introduced in some commits.
>>>
>>> In fact people are specially interested in commits that introduce a
>>> "bad" behavior, called a bug or a regression. They are interested in
>>> these commits because a commit (hopefully) contains a very small set
>>> of source code changes. And it's much easier to understand and
>>> properly fix a problem when you only need to check a very small set of
>>> changes, than when you don't know where look in the first place.
>>>
>>> So to help people find commits that introduce a "bad" behavior, the
>>> "git bisect" set of commands was invented.
>> Hello, All
>>
>> Since commit 84cbce2 cause E350M1 not POST,
>> Following patches should resolve this regression problem, please see the
>> attachment in detail.
>> I have test it on a Persimmon mainboard,
>> anybody can have a test on E350M1?
>> Thanks
>> --
>> Kerry sheh
>>
>>
>>
>
>
>
Hello Kerry:

I have tested your patch set, and it does make the E350M1 boot.
The bad news is there is now a delay of approximately 5 minutes and 20 
seconds before any serial output is displayed.

The coreboot log is available at 
http://www.lucidmachines.com/coreboot/kerrypatches20110907.txt

Please let me know if I can assist further.

Thank you!
-Marshall Buschman

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From Kerry.She at amd.com  Thu Sep  8 06:56:09 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Thu, 8 Sep 2011 12:56:09 +0800
Subject: [coreboot] E350M1 does not POST
In-Reply-To: <4E682206.9090808@lucidmachines.com>
References: <E1Qu5au-0000TM-Aq@taishi.runbox.com><F53A09371FB723428826B442A4B20A410758DCA9@sbjgexmb1.amd.com><4E679E17.7070902@lucidmachines.com>
	<4E682206.9090808@lucidmachines.com>
Message-ID: <F53A09371FB723428826B442A4B20A41075EB688@sbjgexmb1.amd.com>

Hello, Marshall

 

From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Marshall Buschman
Sent: Thursday, September 08, 2011 10:02 AM
To: coreboot at coreboot.org
Subject: Re: [coreboot] E350M1 does not POST

 

On 09/07/2011 11:38 AM, Marshall Buschman wrote: 

I have access to an E350M1. I will test these patches tonight and report
back with results.

Thank you!
-Marshall Buschman

On 09/07/2011 02:53 AM, She, Kerry wrote: 

 

	-----Original Message-----
	From: coreboot-bounces at coreboot.org [mailto:coreboot-
	bounces at coreboot.org] On Behalf Of perh52 at runbox.com
	Sent: Friday, August 19, 2011 12:37 AM
	To: coreboot
	Subject: [coreboot] E350M1 does not POST
	 

				Hi,
				 

				Upon booting, I get this:

				[...]
				 
				you could try commit 0df0e14fb, that may
or may not work, the

commit

	after

				that broke fusion boards completely,
apparently.
				 
				Florian
				 

			Thank you! I can confirm that 0df0e14fb works
properly.
			-Marshall

		Frank,
		 
		It looks like we have a regression. Is there some
dependency on the
		other patches that have not yet been committed?
		 
		Marc

	Unfortunately git bisect is no help here because the commit
which

caused

	the regression was a huge one.
	 
	It's important that large patches are broken down into a set of
small
	comprehensible patches, each with an explanatory commit message.
	 
	<<quote from git-bisect-lk2009.html documentation>>
	...
	sometimes "interesting" changes of behavior in the software are
	introduced in some commits.
	 
	In fact people are specially interested in commits that
introduce a
	"bad" behavior, called a bug or a regression. They are
interested in
	these commits because a commit (hopefully) contains a very small
set
	of source code changes. And it's much easier to understand and
	properly fix a problem when you only need to check a very small
set of
	changes, than when you don't know where look in the first place.
	 
	So to help people find commits that introduce a "bad" behavior,
the
	"git bisect" set of commands was invented.

Hello, All
 
Since commit 84cbce2 cause E350M1 not POST,
Following patches should resolve this regression problem, please see the
attachment in detail.
I have test it on a Persimmon mainboard, 
anybody can have a test on E350M1?
Thanks
--
Kerry sheh
 










Hello Kerry:

I have tested your patch set, and it does make the E350M1 boot.
The bad news is there is now a delay of approximately 5 minutes and 20
seconds before any serial output is displayed.

The coreboot log is available at
http://www.lucidmachines.com/coreboot/kerrypatches20110907.txt

Please let me know if I can assist further.

Thanks a lot,

I have a test based on commit 8679e52 with both F14 C0 and B0 processor
on different persimmon mainboard,

But unfortunately I can't reproduce the problem you have met.

Family14 Revision C0 processor(BSP Family_Model:00500f20)

Family14 Revision B0 processor(BSP Family_Model: 00500f10) is same as
the one you use.

 

There is not much difference between E350M1 and persimmon code,

so I'm not sure whether the root cause is commit 84cbce2 or other
commit, such as sb800 update etc. 

Can you have a test base on commit 84cbce2 ?

Many Thanks 

Kerry Sheh



Thank you!
-Marshall Buschman

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From svens at stackframe.org  Thu Sep  8 08:47:50 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Thu, 08 Sep 2011 08:47:50 +0200
Subject: [coreboot] TPM support for SeaBIOS -- looking for a tester on
	real hardware
In-Reply-To: <4E677FEA.1060503@linux.vnet.ibm.com> (Stefan Berger's message of
	"Wed\, 07 Sep 2011 10\:30\:02 -0400")
References: <4E677FEA.1060503@linux.vnet.ibm.com>
Message-ID: <87zkif8r8p.fsf@begreifnix.stackframe.org>

Hi Stefan,

Stefan Berger <stefanb at linux.vnet.ibm.com> writes:

>   Would anybody be interested in testing the TPM support I added to
> SeaBIOS. I unfortunately don't have a motherboard myself where I could
> try it. I have added the support to SeaBIOS for the TPM device model
> in Qemu.  What you would need for trying it is a motherboard with a
> TPM 1.2 on it. The SeaBIOS TPM support should recognize it, initialize
> the TPM and allow the user to enter another SeaBIOS menu.

I have coreboot + seabios running on Thinkpad X60s and T60p. IIRC both
models have TPM onboard. I could give it a try, but i don't know if i
have to add any code to coreboot for HW initialization. Actually i have
no clue how TPM works, never played with it so far... :)

Regards

Sven



From scott at notabs.org  Thu Sep  8 09:09:14 2011
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 8 Sep 2011 02:09:14 -0500
Subject: [coreboot] E350M1 does not POST
In-Reply-To: <4E682206.9090808@lucidmachines.com>
References: <E1Qu5au-0000TM-Aq@taishi.runbox.com><F53A09371FB723428826B442A4B20A410758DCA9@sbjgexmb1.amd.com><4E679E17.7070902@lucidmachines.com>
	<4E682206.9090808@lucidmachines.com>
Message-ID: <0248A1B65ECC482A8DA3FE0FA09C69E0@asusp67>

Marshall Buschman wrote:

...

]Hello Kerry:
]
]I have tested your patch set, and it does make the E350M1 boot.
]The bad news is there is now a delay of approximately 5 minutes and 20
]seconds before any serial output is displayed.
]
]The coreboot log is available at
]http://www.lucidmachines.com/coreboot/kerrypatches20110907.txt
]
]Please let me know if I can assist further.
]
]Thank you!
]-Marshall Buschman

The problem of early serial output causing a large boot delay is not new. It
is caused by serial port logging before the SB800 LPC clock is configured,
and/or serial port logging before the SIO baud rate is setup. The original
LPC clock fix was in romstage.c, then later moved to sb800 bootblock.c,
function enable_clocks(). Marshall's log file is missing the following early
serial output, which suggests a problem with the needed early SB800 LPC
clock programming, or SIO baud rate programming:

    POST: 0x30
    SB800 - Cfg.c - sb800_cimx_config - Start.
    SB800 - Cfg.c - sb800_cimx_config - End.
    POST: 0x31

I am not in a position to try this on real hardware, but I did do a quick
simnow test. It looks like function enable_clocks() is correctly executing
before the first serial output. But the above lines of early serial output
are logged before the SIO baud rate is programmed. Here is some discussion
of this problem:

http://patchwork.coreboot.org/patch/3178/

That old patch should overcome the problem for the above post code logging.
But the new SB800 logging in sb800_cimx_config() probably needs removing
also.

Thanks,
Scott




From Kerry.She at amd.com  Thu Sep  8 09:30:45 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Thu, 8 Sep 2011 15:30:45 +0800
Subject: [coreboot] E350M1 does not POST
In-Reply-To: <0248A1B65ECC482A8DA3FE0FA09C69E0@asusp67>
References: <E1Qu5au-0000TM-Aq@taishi.runbox.com><F53A09371FB723428826B442A4B20A410758DCA9@sbjgexmb1.amd.com><4E679E17.7070902@lucidmachines.com><4E682206.9090808@lucidmachines.com>
	<0248A1B65ECC482A8DA3FE0FA09C69E0@asusp67>
Message-ID: <F53A09371FB723428826B442A4B20A41075EB874@sbjgexmb1.amd.com>

Hello, Scott

> -----Original Message-----
> From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Scott Duplichan
> Sent: Thursday, September 08, 2011 3:09 PM
> To: 'Marshall Buschman'; coreboot at coreboot.org
> Subject: Re: [coreboot] E350M1 does not POST
> 
> Marshall Buschman wrote:
> 
> ...
> 
> ]Hello Kerry:
> ]
> ]I have tested your patch set, and it does make the E350M1 boot.
> ]The bad news is there is now a delay of approximately 5 minutes and
20
> ]seconds before any serial output is displayed.
> ]
> ]The coreboot log is available at
> ]http://www.lucidmachines.com/coreboot/kerrypatches20110907.txt
> ]
> ]Please let me know if I can assist further.
> ]
> ]Thank you!
> ]-Marshall Buschman
> 
> The problem of early serial output causing a large boot delay is not
new.
> It
> is caused by serial port logging before the SB800 LPC clock is
configured,
> and/or serial port logging before the SIO baud rate is setup. The
> original
> LPC clock fix was in romstage.c, then later moved to sb800
bootblock.c,
> function enable_clocks(). Marshall's log file is missing the following
> early
> serial output, which suggests a problem with the needed early SB800
LPC
> clock programming, or SIO baud rate programming:
> 
>     POST: 0x30
>     SB800 - Cfg.c - sb800_cimx_config - Start.
>     SB800 - Cfg.c - sb800_cimx_config - End.
>     POST: 0x31
> 
> I am not in a position to try this on real hardware, but I did do a
quick
> simnow test. It looks like function enable_clocks() is correctly
> executing
> before the first serial output. But the above lines of early serial
> output
> are logged before the SIO baud rate is programmed. Here is some
> discussion
> of this problem:
> 
> http://patchwork.coreboot.org/patch/3178/
> 
> That old patch should overcome the problem for the above post code
> logging.

This is quite helpful information, 
we should print after the console initialization was done.

> But the new SB800 logging in sb800_cimx_config() probably needs
removing
also.
>
I agree to remove the logging.
Many Thanks
--
Kerry sheh
 
> Thanks,
> Scott
> 
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot





From gerrit at coreboot.org  Thu Sep  8 12:08:35 2011
From: gerrit at coreboot.org (Kerry She (shekairui@gmail.com))
Date: Thu, 8 Sep 2011 12:08:35 +0200
Subject: [coreboot] New patch to review for coreboot: 2a4646a rs780: hide
	unused gpp ports
References: <Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb+0@gerrit.coreboot.org>
Message-ID: <Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb+1@gerrit.coreboot.org>

Kerry She (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/206

-gerrit

commit 2a4646ab3db39a4dc3f816f64377c502894f0fb7
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Sep 8 18:08:30 2011 +0800

    rs780: hide unused gpp ports
    
    hide unused gpp ports, test on avalue/eax-785e
    
    Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/southbridge/amd/rs780/gfx.c   |    2 ++
 src/southbridge/amd/rs780/pcie.c  |   20 ++++++++++++++++++++
 src/southbridge/amd/rs780/rs780.c |    5 ++++-
 src/southbridge/amd/rs780/rs780.h |    1 +
 4 files changed, 27 insertions(+), 1 deletions(-)

diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 9262bb9..3c06d44 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -1009,6 +1009,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
 			set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
 		}
 	} else {		/* step 13.b Link Training was successful */
+		AtiPcieCfg.PortDetect |= 1 << 2; /* Port 2 */
 		set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
 		reg32 = nbpcie_p_read_index(dev, 0x29);
 		width = reg32 & 0xFF;
@@ -1064,6 +1065,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
 
 	} else {		/* step 16.b Link Training was successful */
+		AtiPcieCfg.PortDetect |= 1 << dev_ind;
 		reg32 = nbpcie_p_read_index(dev, 0xa2);
 		width = (reg32 >> 4) & 0x7;
 		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index 9cbd832..992f45e 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -390,3 +390,23 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
 		switching_gpp_configurations(nb_dev, sb_dev);
 	ValidatePortEn(nb_dev);
 }
+
+/**
+ * Hide unused Gpp port
+ */
+void pcie_hide_unused_ports(device_t nb_dev)
+{
+	u8 port = 2;
+	u16 hide = 0x6FC;
+
+	for (port = 2; port <= 10; port++) {
+		if (port == 8)
+			continue;
+		hide &= ~((AtiPcieCfg.PortDetect & (1 << port)) |
+				(AtiPcieCfg.PortHp & (1 << port)));
+	}
+	printk(BIOS_INFO, "rs780 unused GPP ports bitmap=0x%03x, force disabled\n", hide);
+	set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFC, (hide & 0xFC)); /* bridge 2-7 */
+	set_nbmisc_enable_bits(nb_dev, 0x0C, 0x30000, ((hide >> 9) & 0x3) << 16); /* bridge 9-a */
+}
+
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index d8f1be3..b8c7d04 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -362,7 +362,10 @@ void rs780_enable(device_t dev)
 		if (dev->enabled)
 			rs780_gpp_sb_init(nb_dev, dev, dev_ind);
 
-		if (dev_ind == 10) disable_pcie_bar3(nb_dev);
+		if (dev_ind == 10) {
+			disable_pcie_bar3(nb_dev);
+			pcie_hide_unused_ports(nb_dev);
+		}
 		break;
 	default:
 		printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index aba3e69..5b8d251 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -213,4 +213,5 @@ u32 extractbits(u32 source, int lsb, int msb);
 int cpuidFamily(void);
 int is_family0Fh(void);
 int is_family10h(void);
+void pcie_hide_unused_ports(device_t nb_dev);
 #endif				/* RS780_H */



From gerrit at coreboot.org  Thu Sep  8 12:08:36 2011
From: gerrit at coreboot.org (Kerry She (shekairui@gmail.com))
Date: Thu, 8 Sep 2011 12:08:36 +0200
Subject: [coreboot] New patch to review for coreboot: ce9121c sb800: hide
	unused gpp ports
References: <I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0+0@gerrit.coreboot.org>
Message-ID: <I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0+1@gerrit.coreboot.org>

Kerry She (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/207

-gerrit

commit ce9121cbd2021a05e18dcf03166c39d9e3ed0002
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Sep 8 18:27:40 2011 +0800

    sb800: hide unused gpp ports
    
    hide unused gpp ports, test on avalue/eax-785e
    
    Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/mainboard/advansus/a785e-i/platform_cfg.h |    6 ++++++
 src/mainboard/amd/inagua/platform_cfg.h       |    6 ++++++
 src/mainboard/amd/persimmon/platform_cfg.h    |    6 ++++++
 src/mainboard/asrock/e350m1/platform_cfg.h    |    6 ++++++
 src/southbridge/amd/cimx/sb800/cfg.c          |    2 +-
 5 files changed, 25 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h
index ee68386..5fd49d6 100644
--- a/src/mainboard/advansus/a785e-i/platform_cfg.h
+++ b/src/mainboard/advansus/a785e-i/platform_cfg.h
@@ -211,6 +211,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index d37c7e6..ed761c4 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -211,6 +211,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index c6d2bd5..5c88719 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -211,6 +211,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
index 3267651..201d107 100644
--- a/src/mainboard/asrock/e350m1/platform_cfg.h
+++ b/src/mainboard/asrock/e350m1/platform_cfg.h
@@ -211,6 +211,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 45a460b..3245449 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -110,7 +110,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
 	sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 	sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 	sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
-	sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
+	sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS;
 	sb_config->NbSbGen2 = NB_SB_GEN2;
 	sb_config->GppGen2 = SB_GPP_GEN2;
 



From gerrit at coreboot.org  Thu Sep  8 12:08:36 2011
From: gerrit at coreboot.org (Kerry She (shekairui@gmail.com))
Date: Thu, 8 Sep 2011 12:08:36 +0200
Subject: [coreboot] New patch to review for coreboot: de5f0b5 mainboard: add
	avalue/eax-785 ITX mainboard
References: <I483363f5ff9fbfc5cda2f0521660751212f3e326+0@gerrit.coreboot.org>
Message-ID: <I483363f5ff9fbfc5cda2f0521660751212f3e326+1@gerrit.coreboot.org>

Kerry She (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/208

-gerrit

commit de5f0b56372bb436e75556a734a1bd72d1b96c70
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Sep 8 18:28:05 2011 +0800

    mainboard: add avalue/eax-785 ITX mainboard
    
    It's AM3 Socket, 880M + SB850 chipset, similar with advansus/a785e-i.
    Onboard device UART, VGA, SATA, PCI Slot, 2 X16 PCIe slot, 4 X1 Pcie
    slot, Lan, audio, PS2 keyboard/mouse and USB are verified.
    
    Change-Id: I483363f5ff9fbfc5cda2f0521660751212f3e326
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/mainboard/Kconfig                          |    3 +
 src/mainboard/avalue/Kconfig                   |   35 +
 src/mainboard/avalue/eax-785e/Kconfig          |  108 ++
 src/mainboard/avalue/eax-785e/Makefile.inc     |   18 +
 src/mainboard/avalue/eax-785e/acpi/cpstate.asl |   75 +
 src/mainboard/avalue/eax-785e/acpi/ide.asl     |  244 ++++
 src/mainboard/avalue/eax-785e/acpi/routing.asl |  398 ++++++
 src/mainboard/avalue/eax-785e/acpi/sata.asl    |  149 ++
 src/mainboard/avalue/eax-785e/acpi/usb.asl     |  161 +++
 src/mainboard/avalue/eax-785e/acpi_tables.c    |  274 ++++
 src/mainboard/avalue/eax-785e/chip.h           |   22 +
 src/mainboard/avalue/eax-785e/cmos.layout      |   98 ++
 src/mainboard/avalue/eax-785e/devicetree.cb    |  111 ++
 src/mainboard/avalue/eax-785e/dsdt.asl         | 1824 ++++++++++++++++++++++++
 src/mainboard/avalue/eax-785e/fadt.c           |  188 +++
 src/mainboard/avalue/eax-785e/get_bus_conf.c   |  154 ++
 src/mainboard/avalue/eax-785e/irq_tables.c     |  111 ++
 src/mainboard/avalue/eax-785e/mainboard.c      |  148 ++
 src/mainboard/avalue/eax-785e/mb_sysconf.h     |   43 +
 src/mainboard/avalue/eax-785e/mptable.c        |  158 ++
 src/mainboard/avalue/eax-785e/platform_cfg.h   |  235 +++
 src/mainboard/avalue/eax-785e/reset.c          |   63 +
 src/mainboard/avalue/eax-785e/resourcemap.c    |  278 ++++
 src/mainboard/avalue/eax-785e/romstage.c       |  266 ++++
 24 files changed, 5164 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index ed00318..13032a6 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -26,6 +26,8 @@ config VENDOR_ASUS
 	bool "ASUS"
 config VENDOR_A_TREND
 	bool "A-Trend"
+config VENDOR_AVALUE
+	bool "AVALUE"
 config VENDOR_AXUS
 	bool "AXUS"
 config VENDOR_AZZA
@@ -134,6 +136,7 @@ source "src/mainboard/artecgroup/Kconfig"
 source "src/mainboard/asi/Kconfig"
 source "src/mainboard/asrock/Kconfig"
 source "src/mainboard/asus/Kconfig"
+source "src/mainboard/avalue/Kconfig"
 source "src/mainboard/axus/Kconfig"
 source "src/mainboard/azza/Kconfig"
 source "src/mainboard/bcom/Kconfig"
diff --git a/src/mainboard/avalue/Kconfig b/src/mainboard/avalue/Kconfig
new file mode 100644
index 0000000..47e3486
--- /dev/null
+++ b/src/mainboard/avalue/Kconfig
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+if VENDOR_AVALUE
+
+choice
+	prompt "Mainboard model"
+
+config BOARD_AVALUE_EAX_785E
+	bool "EAX-785E"
+
+endchoice
+
+source "src/mainboard/avalue/eax-785e/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "AVALUE"
+
+endif # VENDOR_AVALUE
diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig
new file mode 100644
index 0000000..7aa90c8
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/Kconfig
@@ -0,0 +1,108 @@
+if BOARD_AVALUE_EAX_785E
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_SOCKET_AM3
+	select DIMM_DDR3
+	select DIMM_REGISTERED
+	select QRANK_DIMM_SUPPORT
+	select NORTHBRIDGE_AMD_AMDFAM10
+	select SOUTHBRIDGE_AMD_RS780
+	select SOUTHBRIDGE_AMD_CIMX_SB800
+	select SUPERIO_WINBOND_W83627HF #COM1, COM2
+	#select SUPERIO_FINTEK_F81216AD #COM3, COM4
+	select SB_SUPERIO_HWM
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select AMDMCT
+	select HAVE_MP_TABLE
+	select HAVE_ACPI_TABLES
+	select BOARD_HAS_FADT
+	select BOARD_ROMSIZE_KB_2048
+	select RAMINIT_SYSINFO
+	select ENABLE_APIC_EXT_ID
+	select TINY_BOOTBLOCK
+	select GFXUMA
+	select HAVE_DEBUG_CAR
+	select SET_FIDVID
+
+config MAINBOARD_DIR
+	string
+	default avalue/eax-785e
+
+config APIC_ID_OFFSET
+	hex
+	default 0x0
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EAX-785E"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+
+config MEM_TRAIN_SEQ
+	int
+	default 2
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x1
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config AMD_UCODE_PATCH_FILE
+	string
+	default "mc_patch_010000b6.h"
+
+config RAMTOP
+	hex
+	default 0x2000000
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+config RAMBASE
+	hex
+	default 0x200000
+
+config VGA_BIOS_ID
+        string
+        default "1002,9712"
+
+config SIO_PORT
+        hex
+        default 0x2E
+
+endif #BOARD_AVALUE_EAX_785E
diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc
new file mode 100644
index 0000000..737bb1c
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/Makefile.inc
@@ -0,0 +1,18 @@
+#romstage-y += reset.c #FIXME romstage have include test_rest.c
+
+ramstage-y += reset.c
+
+#SB800 CIMx share AGESA V5 lib code
+ifneq ($(CONFIG_AMD_AGESA),y)
+ AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+ romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+ ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+
+ AGESA_INC := -I$(AGESA_ROOT)/ \
+	      -I$(AGESA_ROOT)/Include \
+	      -I$(AGESA_ROOT)/Proc/IDS/ \
+	      -I$(AGESA_ROOT)/Proc/CPU/ \
+	      -I$(AGESA_ROOT)/Proc/CPU/Family
+
+ CFLAGS += $(AGESA_INC)
+endif
diff --git a/src/mainboard/avalue/eax-785e/acpi/cpstate.asl b/src/mainboard/avalue/eax-785e/acpi/cpstate.asl
new file mode 100644
index 0000000..5eca9cc
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}
diff --git a/src/mainboard/avalue/eax-785e/acpi/ide.asl b/src/mainboard/avalue/eax-785e/acpi/ide.asl
new file mode 100644
index 0000000..c79c18c
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}
diff --git a/src/mainboard/avalue/eax-785e/acpi/routing.asl b/src/mainboard/avalue/eax-785e/acpi/routing.asl
new file mode 100644
index 0000000..cb50394
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/routing.asl
@@ -0,0 +1,398 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+
+		Package(){0x0009FFFF, 0, INTB, 0 },
+		Package(){0x0009FFFF, 1, INTC, 0 },
+		Package(){0x0009FFFF, 2, INTD, 0 },
+		Package(){0x0009FFFF, 3, INTA, 0 },
+
+		Package(){0x000AFFFF, 0, INTC, 0 },
+		Package(){0x000AFFFF, 1, INTD, 0 },
+		Package(){0x000AFFFF, 2, INTA, 0 },
+		Package(){0x000AFFFF, 3, INTB, 0 },
+
+		Package(){0x000BFFFF, 0, INTD, 0 },
+		Package(){0x000BFFFF, 1, INTA, 0 },
+		Package(){0x000BFFFF, 2, INTB, 0 },
+		Package(){0x000BFFFF, 3, INTC, 0 },
+
+		Package(){0x000CFFFF, 0, INTA, 0 },
+		Package(){0x000CFFFF, 1, INTB, 0 },
+		Package(){0x000CFFFF, 2, INTC, 0 },
+		Package(){0x000CFFFF, 3, INTD, 0 },
+
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		Package(){0x0016FFFF, 1, INTB, 0 },
+
+		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+
+		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, 0, 18 },
+		package(){0x0001FFFF, 1, 0, 19 },
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, 0, 17 }, */
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Package(){0x0006FFFF, 0, 0, 18 }, */
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Package(){0x0007FFFF, 0, 0, 19 }, */
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Dev 9 - PCIe Bridge for network card */
+		Package(){0x0009FFFF, 0, 0, 17 },
+		/* Package(){0x0009FFFF, 1, 0, 16 }, */
+		/* Package(){0x0009FFFF, 2, 0, 17 }, */
+		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		/* Bus 0, Dev A - PCIe Bridge for network card */
+		Package(){0x000AFFFF, 0, 0, 18 },
+		/* Package(){0x000AFFFF, 1, 0, 16 }, */
+		/* Package(){0x000AFFFF, 2, 0, 17 }, */
+		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, 0, 18 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		/* Package(){0x0012FFFF, 2, 0, 18 }, */
+
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+		/* Package(){0x0013FFFF, 2, 0, 16 }, */
+
+		/* Package(){0x00140000, 0, 0, 16 }, */
+
+		Package(){0x0016FFFF, 0, 0, 18 },
+		Package(){0x0016FFFF, 1, 0, 17 },
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+
+		/* TODO: pcie */
+		Package(){0x0015FFFF, 0, 0, 16 },
+		Package(){0x0015FFFF, 1, 0, 17 },
+		Package(){0x0015FFFF, 2, 0, 18 },
+		Package(){0x0015FFFF, 3, 0, 19 },
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+	Name(APR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE0, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APE0, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PE1, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APE1, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PE2, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APE2, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE3, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APE3, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+		Package(){0x0007FFFF, 0, 0, 0x16 },
+		Package(){0x0007FFFF, 1, 0, 0x17 },
+		Package(){0x0007FFFF, 2, 0, 0x14 },
+		Package(){0x0007FFFF, 3, 0, 0x15 },
+	})
+}
diff --git a/src/mainboard/avalue/eax-785e/acpi/sata.asl b/src/mainboard/avalue/eax-785e/acpi/sata.asl
new file mode 100644
index 0000000..bd4acf0
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00110000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}
diff --git a/src/mainboard/avalue/eax-785e/acpi/usb.asl b/src/mainboard/avalue/eax-785e/acpi/usb.asl
new file mode 100644
index 0000000..81ea9a2
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/usb.asl
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "usb.asl"
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+	Scope (\_GPE) {
+		Method (_L1A) {
+			UCOC()
+			if (LEqual(GPB5,PLC5)) {
+				Not(PLC5,PLC5)
+				Store(PLC5, \_SB.PT5D)
+			}
+		}
+	}
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}
diff --git a/src/mainboard/avalue/eax-785e/acpi_tables.c b/src/mainboard/avalue/eax-785e/acpi_tables.c
new file mode 100644
index 0000000..7c8ca76
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi_tables.c
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+#include "mb_sysconf.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+extern const unsigned char AmlCode_ssdt2[];
+extern const unsigned char AmlCode_ssdt3[];
+extern const unsigned char AmlCode_ssdt4[];
+extern const unsigned char AmlCode_ssdt5[];
+#endif
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+	acpi_header_t *ssdtx;
+	void *p;
+	int i;
+#endif
+
+	get_bus_conf();	/* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	/* SLIT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdp, slit);
+
+	/* SSDT */
+	current	  = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)current;
+	memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+	current += ssdt->length;
+	memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+	//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
+	update_ssdt((void*)ssdt);
+	/* recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	current = acpi_add_ssdt_pstates(rsdp, current);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+
+	/* same htio, but different position? We may have to copy,
+	change HCIN, and recalculate the checknum and add_table */
+
+	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+		if((sysconf.pci1234[i] & 1) != 1 ) continue;
+		u8 c;
+		if (i < 7) {
+			c = (u8) ('4' + i - 1);
+		} else {
+			c = (u8) ('A' + i - 1 - 6);
+		}
+		current	  = ( current + 0x07) & -0x08;
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
+		ssdtx = (acpi_header_t *)current;
+		switch (sysconf.hcid[i]) {
+		case 1:
+			p = &AmlCode_ssdt2;
+			break;
+		case 2:
+			p = &AmlCode_ssdt3;
+			break;
+		case 3:	/* 8131 */
+			p = &AmlCode_ssdt4;
+			break;
+		default:
+			/* HTX no io apic */
+			p = &AmlCode_ssdt5;
+			break;
+		}
+		memcpy(ssdtx, p, sizeof(acpi_header_t));
+		current += ssdtx->length;
+		memcpy(ssdtx, p, ssdtx->length);
+		update_ssdtx((void *)ssdtx, i);
+		ssdtx->checksum = 0;
+		ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
+		acpi_add_table(rsdp, ssdtx);
+	}
+#endif
+
+	/* DSDT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FDAT */
+#if CONFIG_BOARD_HAS_FADT == 1
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+#endif
+
+#if DUMP_ACPI_TABLES == 1
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/avalue/eax-785e/chip.h b/src/mainboard/avalue/eax-785e/chip.h
new file mode 100644
index 0000000..5957589
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/chip.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/avalue/eax-785e/cmos.layout b/src/mainboard/avalue/eax-785e/cmos.layout
new file mode 100644
index 0000000..53fdef5
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/cmos.layout
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/avalue/eax-785e/devicetree.cb b/src/mainboard/avalue/eax-785e/devicetree.cb
new file mode 100644
index 0000000..bf58f90
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/devicetree.cb
@@ -0,0 +1,111 @@
+# sample config for avalue/EAX-785E
+chip northbridge/amd/amdfam10/root_complex
+	device lapic_cluster 0 on
+		chip cpu/amd/socket_AM3  #L1 and DDR3
+			 device lapic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id.
+		chip northbridge/amd/amdfam10
+			device pci 18.0 on #  northbridge
+				chip southbridge/amd/rs780
+					device pci 0.0 on end # HT 0x9600
+					device pci 1.0 on end # Internal Graphics P2P bridge 0x9712
+					device pci 2.0 on end # GFX_RX0-7/TX0-7   PCIEx16_1 slot
+					device pci 3.0 on end # GFX_RX8-15/TX8-15 PCIEx16_2 slot
+					device pci 4.0 on end # PortB GPP_RX/TX0 PCIEx1_1 slot
+					device pci 5.0 on end # PortC GPP_RX/TX1 PCIEx1_2 slot
+					device pci 6.0 on end # PortD GPP_RX/TX2 PCIEx1_3 slot
+					device pci 7.0 on end # PortE GPP_RX/TX3 PCIEx1_4 slot
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					device pci 9.0 on end # Ethernet
+					device pci a.0 on end # Ethernet
+					register "gppsb_configuration" = "4"	# Configuration E
+					register "gpp_configuration" = "3"	# Configuration D
+					register "port_enable" = "0x6FE"
+					register "gfx_dev2_dev3" = "0" #no use
+					register "gfx_dual_slot" = "1" # 0 single slot, 1 dual slot
+					register "gfx_lane_reversal" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+					register "gfx_tmds" = "1"
+					register "gfx_pcie_config" = "4" # 2x8 GFX, one on Lanes 0-7, one on Lanes 8-15
+					register "gfx_ddi_config" = "0"  # no DDI_SL
+				end
+				chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.2 on end # USB
+					device pci 14.0 on end # SM
+					device pci 14.1 on end # IDE    0x439c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on
+                                                chip superio/winbond/w83627hf
+                                                        device pnp 2e.0 off #  Floppy
+                                                                io 0x60 = 0x3f0
+                                                                irq 0x70 = 6
+                                                                drq 0x74 = 2
+                                                        end
+                                                        device pnp 2e.1 off #  Parallel Port
+                                                                io 0x60 = 0x378
+                                                                irq 0x70 = 7
+                                                        end
+                                                        device pnp 2e.2 on #  Com1
+                                                                io 0x60 = 0x3f8
+                                                                irq 0x70 = 4
+                                                        end
+                                                        device pnp 2e.3 on #  Com2
+                                                                io 0x60 = 0x2f8
+                                                                irq 0x70 = 3
+                                                        end
+                                                        device pnp 2e.5 on #  PS/2 Keyboard & mouse
+                                                                io 0x60 = 0x60
+                                                                io 0x62 = 0x64
+                                                                irq 0x70 = 1
+                                                                irq 0x72 = 12
+                                                        end
+                                                        device pnp 2e.6 off  # SFI
+                                                                io 0x62 = 0x100
+                                                        end
+                                                        device pnp 2e.7 off #  GPIO_GAME_MIDI
+                                                                io 0x60 = 0x220
+                                                                io 0x62 = 0x300
+                                                                irq 0x70 = 9
+                                                        end
+                                                        device pnp 2e.8 off end #  WDTO_PLED
+                                                        device pnp 2e.9 off end #  GPIO_SUSLED
+                                                        device pnp 2e.a off end #  ACPI
+                                                        device pnp 2e.b on #  HW Monitor
+                                                                io 0x60 = 0x290
+                                                                irq 0x70 = 5
+                                                        end
+                                                end     #superio/winbond/w83627hf
+					end # LPC	0x439d
+					device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+					device pci 14.5 on end # USB 2
+					device pci 14.6 off end # Gec
+					device pci 15.0 off end # PCIe 0
+					device pci 15.1 off end # PCIe 1
+					device pci 15.2 off end # PCIe 2
+					device pci 15.3 on end # PCIe 3
+					device pci 16.0 on end # USB
+					device pci 16.2 on end # USB
+					#register "gpp_configuration" = "0" #4:0:0:0
+					#register "gpp_configuration" = "2" #2:2:0:0
+					#register "gpp_configuration" = "3" #2:1:1:0
+					register "gpp_configuration" = "4" #1:1:1:1
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				end	#southbridge/amd/cimx/sb800
+			end #  device pci 18.0
+
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+		end
+	end #pci_domain
+end
diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl
new file mode 100644
index 0000000..1287f95
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/dsdt.asl
@@ -0,0 +1,1824 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"AVALUE  ",               /* OEMID */
+	"EAX-785E",	     /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include "../../../arch/x86/acpi/debug.asl" */		/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			CPU0,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU1,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU2,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU3,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+	} /* End _PR scope */
+
+	/* PIC IRQ mapping registers, C00h-C01h. */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PIRA, 0x00000008,	/* Index 0 */
+		PIRB, 0x00000008,	/* Index 1 */
+		PIRC, 0x00000008,	/* Index 2 */
+		PIRD, 0x00000008,	/* Index 3 */
+		PIRE, 0x00000008,	/* Index 4 */
+		PIRF, 0x00000008,	/* Index 5 */
+		PIRG, 0x00000008,	/* Index 6 */
+		PIRH, 0x00000008,	/* Index 7 */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk. TODO: should be 0x60 */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve){
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+
+	#include "acpi/routing.asl"
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+		Method(CIRQ, 0x00, NotSerialized){
+			Store(0, PIRA)
+			Store(0, PIRB)
+			Store(0, PIRC)
+			Store(0, PIRD)
+			Store(0, PIRE)
+			Store(0, PIRF)
+			Store(0, PIRG)
+			Store(0, PIRH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PIRA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PIRA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PIRB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PIRB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PIRC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PIRC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIRD) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIRD)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRD, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRD)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PIRE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PIRE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PIRF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PIRF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PIRG) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PIRG)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRG, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRG)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PIRH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PIRH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			/* Notify (\_TZ.TZ00, 0x80) */
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event - Moved to USB.asl */
+		/* Method(_L1A) {
+		*	DBGO("\\_GPE\\_L1A\n")
+		* }
+		*/
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	#include "acpi/usb.asl"
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			External (TOM1)
+			External (TOM2)
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+			/* GPP */
+			Device(PBR9) {
+				Name(_ADR, 0x00090000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS9) }   /* APIC mode */
+					Return (PS9)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR9 */
+
+			Device(PBRa) {
+				Name(_ADR, 0x000A0000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APSa) }   /* APIC mode */
+					Return (PSa)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBRa */
+
+			Device(PE20) {
+				Name(_ADR, 0x00150000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE0) }   /* APIC mode */
+					Return (PE0)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE20 */
+			Device(PE21) {
+				Name(_ADR, 0x00150001)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE1) }   /* APIC mode */
+					Return (PE1)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE21 */
+			Device(PE22) {
+				Name(_ADR, 0x00150002)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE2) }   /* APIC mode */
+					Return (APE2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE22 */
+			Device(PE23) {
+				Name(_ADR, 0x00150003)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE3) }   /* APIC mode */
+					Return (PE3)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE23 */
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00110000)
+				#include "acpi/sata.asl"
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00120000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00120002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00160000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UOH6) {
+				Name(_ADR, 0x00160002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00140005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				#include "acpi/ide.asl"
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#if 0
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#endif
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* length */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+#if 0
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/*  Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/*  Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+#endif
+                                /* memory space for PCI BARs below 4GB */
+                                Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+#if 0
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM1, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	Subtract(TOM2, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+#endif
+                                CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+                                CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+                                /*
+                                 * Declare memory between TOM1 and 4GB as available
+                                 * for PCI MMIO.
+                                 * Use ShiftLeft to avoid 64bit constant (for XP).
+                                 * This will work even if the OS does 32bit arithmetic, as
+                                 * 32bit (0x00000000 - TOM1) will wrap and give the same
+                                 * result as 64bit (0x100000000 - TOM1).
+                                 */
+                                Store(TOM1, MM1B)
+                                ShiftLeft(0x10000000, 4, Local0)
+                                Subtract(Local0, TOM1, Local0)
+                                Store(Local0, MM1L)
+
+				Return(CRES) /* note to change the Name buffer */
+			}  /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+#if 0
+	/* SMBUS Support */
+	Mutex (SBX0, 0x00)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x10, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+			If (LEqual (Local0, Zero)) {
+				Release (SBX0)
+				Return (0x0)
+			}
+
+			Store (0x1F, HSTS)
+			Store (Or (ShiftLeft (Arg1, One), One), HADD)
+			Store (Arg2, HCMD)
+			If (LEqual (Arg0, 0x07)) {
+				Store (0x48, HCNT) /* read byte */
+			}
+
+			Store (SWTC (0x03E8), Local1) /* 1000 ms */
+			If (LEqual (Local1, Zero)) {
+				If (LEqual (Arg0, 0x07)) {
+					Store (DAT0, Local0)
+				}
+			}
+			Else {
+				Store (Local1, Local0)
+			}
+
+			Release (SBX0)
+		}
+
+		/* DBGO("the value of SMBusData0 register ") */
+		/* DBGO(Arg2) */
+		/* DBGO(" is ") */
+		/* DBGO(Local0) */
+		/* DBGO("\n") */
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 2732)
+		Name (THOT, 800)
+		Name (TCRT, 850)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+				If (LGreater (Local0, 0x10)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400, KELV))
+				}
+
+				Store (SMBR (0x07, 0x4C, 0x01), Local0)
+				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+				If (LGreater (Local0, 0x10)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Multiply (Local1, 10, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+#endif
+}
+/* End of ASL file */
diff --git a/src/mainboard/avalue/eax-785e/fadt.c b/src/mainboard/avalue/eax-785e/fadt.c
new file mode 100644
index 0000000..f84b379
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/fadt.c
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "SBPLATFORM.h"
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	u16 val = 0;
+	acpi_header_t *header = &(fadt->header);
+
+	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	val = PM1_EVT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+	val = PM1_CNT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+	val = PM1_TMR_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+	val = GPE0_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
+
+	/* CpuControl is in \_PR.CPU0, 6 bytes */
+	val = CPU_CNT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+	val = 0;
+	WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+	val = ACPI_PMA_CNT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
+
+	/* AcpiDecodeEnable, When set, SB uses the contents of the
+	 * PM registers at index 60-6B to decode ACPI I/O address.
+	 * AcpiSmiEn & SmiCmdEn*/
+	val = BIT0 | BIT1 | BIT2 | BIT4;
+	WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
+
+	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, PM1_CNT_BLK_ADDRESS);		  /* set SCI_EN */
+
+	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}
diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c
new file mode 100644
index 0000000..20a856e
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/multicore.h>
+#endif
+#include <cpu/amd/amdfam10_sysconf.h>
+#if CONFIG_AMD_SB_CIMX == 1
+#include <sb_cimx.h>
+#endif
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+int bus_isa;
+u8 bus_rs780[11];
+u8 bus_sb800[3];
+u32 apicid_sb800;
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+	0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+	0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_rs780;
+u32 sbdn_sb800;
+
+extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+	u32 apicid_base;
+	device_t dev;
+	int i, j;
+
+	if (get_bus_conf_done == 1)
+		return;		/* do it only once */
+	get_bus_conf_done = 1;
+
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+	for (i = 0; i < sysconf.hc_possible_num; i++) {
+		sysconf.pci1234[i] = pci1234x[i];
+		sysconf.hcdn[i] = hcdnx[i];
+	}
+
+	get_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
+	sbdn_rs780 = sysconf.sbdn;
+	sbdn_sb800 = 0;
+
+	for (i = 0; i < 3; i++) {
+		bus_sb800[i] = 0;
+	}
+	for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
+		bus_rs780[i] = 0;
+	}
+
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+	bus_type[0] = 1;	/* pci */
+
+	bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb800[0] = bus_rs780[0];
+
+	bus_type[bus_rs780[0]] = 1;
+
+	/* sb800 */
+	dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+	if (dev) {
+		bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb800[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	for (i = 0; i < 4; i++) {
+		dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x15, i));
+		if (dev) {
+			bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+			bus_isa++;
+		}
+	}
+	for (j = bus_sb800[2]; j < bus_isa; j++)
+		bus_type[j] = 1;
+
+	/* rs780 */
+	for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
+		dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
+		if (dev) {
+			bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			if(255 != bus_rs780[i]) {
+				bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+				bus_isa++;
+				bus_type[bus_rs780[i]] = 1; /* PCI bus. */
+			}
+		}
+	}
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+	apicid_sb800 = apicid_base + 0;
+
+#if CONFIG_AMD_SB_CIMX == 1
+	sb_Late_Post();
+#endif
+}
diff --git a/src/mainboard/avalue/eax-785e/irq_tables.c b/src/mainboard/avalue/eax-785e/irq_tables.c
new file mode 100644
index 0000000..fd74e3a
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/irq_tables.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			    u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+
+extern u8 bus_isa;
+extern u8 bus_rs780[8];
+extern u8 bus_sb800[2];
+extern unsigned long sbdn_sb800;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb800[0];
+	pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+	slot_num++;
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
new file mode 100644
index 0000000..7f55c03
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/mainboard.c
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "SBPLATFORM.h"
+#include "chip.h"
+
+uint64_t uma_memory_base, uma_memory_size;
+
+u8 is_dev3_present(void);
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+void enable_int_gfx(void);
+
+/* GPIO6. */
+void enable_int_gfx(void)
+{
+	volatile u8 *gpio_reg;
+
+#ifdef UNUSED_CODE
+	RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
+	RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
+#endif
+	/* make sure the Acpi MMIO(fed80000) is accessible */
+        RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
+
+	gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
+
+	*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
+	*(gpio_reg + 170) = 0x1; /* gpio_gate */
+
+	gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
+
+	*(gpio_reg + 0x6) = 0x8;
+	*(gpio_reg + 170) = 0x0;
+}
+
+void set_pcie_dereset()
+{
+}
+
+void set_pcie_reset(void)
+{
+}
+
+u8 is_dev3_present(void)
+{
+	return 1;
+}
+
+
+/*************************************************
+* enable the dedicated function in EAX-785E board.
+* This function called early than rs780_enable.
+*************************************************/
+static void eax_785e(device_t dev)
+{
+	/* Leave it for furture use. */
+	/* struct mainboard_config *mainboard =
+	   (struct mainboard_config *)dev->chip_info; */
+
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+#if (CONFIG_GFXUMA == 1)
+	msr_t msr, msr2;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	/* refer to UMA Size Consideration in 780 BDG. */
+	switch (msr.lo) {
+	case 0x10000000:	/* 256M system memory */
+		uma_memory_size = 0x4000000;	/* 64M recommended UMA */
+		break;
+
+	case 0x20000000:	/* 512M system memory */
+		uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+		break;
+
+	default:		/* 1GB and above system memory */
+		uma_memory_size = 0x10000000;	/* 256M recommended UMA */
+		break;
+	}
+
+	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+		    __func__, uma_memory_size, uma_memory_base);
+
+	/* TODO: TOP_MEM2 */
+#else
+	uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+	uma_memory_base = 0x38000000;	/* 1GB  system memory supposed */
+#endif
+
+	set_pcie_dereset();
+	enable_int_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	/* UMA is removed from system memory in the northbridge code, but
+	 * in some circumstances we want the memory mentioned as reserved.
+	 */
+#if (CONFIG_GFXUMA == 1)
+	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+		    uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+			    uma_memory_size);
+#endif
+	return 0;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+	.enable_dev = eax_785e,
+};
diff --git a/src/mainboard/avalue/eax-785e/mb_sysconf.h b/src/mainboard/avalue/eax-785e/mb_sysconf.h
new file mode 100644
index 0000000..ca5870c
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/mb_sysconf.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+	u8 bus_isa;
+	u8 bus_8132_0;
+	u8 bus_8132_1;
+	u8 bus_8132_2;
+	u8 bus_8111_0;
+	u8 bus_8111_1;
+	u8 bus_8132a[31][3];
+	u8 bus_8151[31][2];
+
+	u32 apicid_8111;
+	u32 apicid_8132_1;
+	u32 apicid_8132_2;
+	u32 apicid_8132a[31][2];
+	u32 sbdn3;
+	u32 sbdn3a[31];
+	u32 sbdn5[31];
+	u32 bus_type[256];
+};
+
+#endif
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
new file mode 100644
index 0000000..e4fc23b
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <SBPLATFORM.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern int bus_isa;
+extern u8 bus_rs780[11];
+extern u8 bus_sb800[2];
+extern u32 apicid_sb800;
+extern u32 bus_type[256];
+extern u32 sbdn_rs780;
+extern u32 sbdn_sb800;
+
+u8 intr_data[] = {
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
+};
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	u32 dword;
+	u8 byte;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LAPIC_ADDR);
+
+	smp_write_processors(mc);
+
+	get_bus_conf();
+
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+	dword &= 0xFFFFFFF0;
+
+	smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#if CONFIG_GENERATE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
+
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);
+	PCI_INT(0x0, 0x14, 0x4, 0x11);
+
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+	/* on board NIC & Slot PCIE.  */
+	/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
+/* 	PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
+	PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
+	/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
+	PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
+	/* configuration B doesnt need dev 5,6,7 */
+	/*
+	 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
+	 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
+	 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
+	 */
+	PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
+	PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum =
+	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+		     mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h
new file mode 100644
index 0000000..24dcae0
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/platform_cfg.h
@@ -0,0 +1,235 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _EAX_785E_CFG_H_
+#define _EAX_785E_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M			0
+#define BIOS_SIZE_2M			1
+#define BIOS_SIZE_4M			3
+#define BIOS_SIZE_8M			7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#ifndef BIOS_SIZE
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+  #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+  #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+  #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+  #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ *  0 - Disable Spread Spectrum function
+ *  1 - Enable  Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM			0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ *  0 - Disable hpet
+ *  1 - Enable  hpet
+ */
+#define HPET_TIMER			1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ *   0 - Disable
+ *   1 - Enable
+ *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG		0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ *   0 - disable
+ *   1 - enable
+ *  PCI SLOT 0 define at BIT0
+ *  PCI SLOT 1 define at BIT1
+ *  PCI SLOT 2 define at BIT2
+ *  PCI SLOT 3 define at BIT3
+ *  PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL			0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE			NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE			0
+#define IDE_NATIVE_MODE			1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE			IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ *  PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK		0x00
+#define INTERNAL_CLOCK		0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED	1
+
+
+/**
+ * @def   AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def   AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def   AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO			0
+#define AZALIA_DISABLE			1
+#define AZALIA_ENABLE			2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER		AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ *  0 - disable
+ *  1 - enable
+ */
+#define AZALIA_PIN_CONFIG		1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ *  SDIN0 is define at BIT0 & BIT1
+ *   00 - GPIO PIN
+ *   01 - Reserved
+ *   10 - As a Azalia SDIN pin
+ *  SDIN1 is define at BIT2 & BIT3
+ *  SDIN2 is define at BIT4 & BIT5
+ *  SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN		0xAA
+#define AZALIA_SDIN_PIN			0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ *  GPP_CFGMODE_X4000
+ *  GPP_CFGMODE_X2200
+ *  GPP_CFGMODE_X2110
+ *  GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE			GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ *    0  - Disable
+ *    1  - Enable
+ */
+#define NB_SB_GEN2			TRUE
+
+/**
+ * @def SB_GEN2
+ *    0  - Disable
+ *    1  - Enable
+ */
+#define SB_GPP_GEN2			TRUE
+
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
+
+/**
+ * @def   GEC_CONFIG
+ *    0  - Enable
+ *    1  - Disable
+ */
+#define GEC_CONFIG			0
+
+/**
+ * @def SIO_HWM_BASE_ADDRESS  Super IO HWM base address
+ */
+#define SIO_HWM_BASE_ADDRESS		0x290
+
+#endif
diff --git a/src/mainboard/avalue/eax-785e/reset.c b/src/mainboard/avalue/eax-785e/reset.c
new file mode 100644
index 0000000..5212b3a
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/reset.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes, htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for (i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
diff --git a/src/mainboard/avalue/eax-785e/resourcemap.c b/src/mainboard/avalue/eax-785e/resourcemap.c
new file mode 100644
index 0000000..06102b0
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/resourcemap.c
@@ -0,0 +1,278 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration regin i
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+	};
+
+	int max;
+	max = ARRAY_SIZE(register_values);
+	setup_resource_map(register_values, max);
+}
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
new file mode 100644
index 0000000..beea992
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+//#define SYSTEM_TYPE 0	/* SERVER */
+#define SYSTEM_TYPE 1	/* DESKTOP */
+//#define SYSTEM_TYPE 2	/* MOBILE */
+
+//used by incoherent_ht
+#define FAM10_SCAN_PCI_BUS 0
+#define FAM10_ALLOCATE_IO_RANGE 0
+
+#include <lib.h>
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <cpu/amd/model_10xxx_rev.h>
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdfam10/reset_test.c"
+#include <console/loglevel.h>
+#include "cpu/x86/bist.h"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include <sb_cimx.h>
+#include <SBPLATFORM.h> /* SB OEM constants */
+#include <southbridge/amd/cimx/sb800/smbus.h>
+#include "northbridge/amd/amdfam10/debug.c"
+
+static void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+static int spd_read_byte(u32 device, u32 address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/pci.c"
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#if CONFIG_UPDATE_CPU_MICROCODE
+#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "northbridge/amd/amdfam10/early_ht.c"
+#include "spd.h"
+
+#include <reset.h>
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
+	u32 bsp_apicid = 0, val;
+	msr_t msr;
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		/* mov bsp to bus 0xff when > 8 nodes */
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		//enable port80 decoding and southbridge poweron init
+		sb_Poweron_Init();
+	}
+
+	post_code(0x30);
+
+	if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
+		/* All cores run this but the BSP(node0,core0) is the only core that returns. */
+	}
+
+	post_code(0x32);
+
+	enable_rs780_dev8();
+	sb800_clk_output_48Mhz();
+
+	w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0));
+	w83627hf_enable_serial(0, CONFIG_TTYS0_BASE);
+
+	uart_init();
+	console_init();
+	printk(BIOS_DEBUG, "\n");
+
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+	printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	/* Setup sysinfo defaults */
+	set_sysinfo_in_ram(0);
+
+#if CONFIG_UPDATE_CPU_MICROCODE
+	update_microcode(val);
+#endif
+	post_code(0x33);
+
+	cpuSetAMDMSR();
+	post_code(0x34);
+
+	amd_ht_init(sysinfo);
+	post_code(0x35);
+
+	/* Setup nodes PCI space and start core 0 AP init. */
+	finalize_node_setup(sysinfo);
+
+	/* Setup any mainboard PCI settings etc. */
+	setup_mb_resource_map();
+	post_code(0x36);
+
+	/* wait for all the APs core0 started by finalize_node_setup. */
+	/* FIXME: A bunch of cores are going to start output to serial at once.
+	   It would be nice to fixup prink spinlocks for ROM XIP mode.
+	   I think it could be done by putting the spinlock flag in the cache
+	   of the BSP located right after sysinfo.
+	 */
+	wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* Core0 on each node is configured. Now setup any additional cores. */
+	printk(BIOS_DEBUG, "start_other_cores()\n");
+	start_other_cores();
+	post_code(0x37);
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+
+	post_code(0x38);
+
+	/* run _early_setup before soft-reset. */
+	rs780_early_setup();
+
+#if CONFIG_SET_FIDVID == 1
+	msr = rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	post_code(0x39);
+
+	if (!warm_reset_detect(0)) {			// BSP is node 0
+		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+	} else {
+		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
+	}
+
+	post_code(0x3A);
+
+	/* show final fid and vid */
+	msr=rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+#endif
+
+	rs780_htinit();
+
+	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	if (!warm_reset_detect(0)) {
+		print_info("...WARM RESET...\n\n\n");
+		soft_reset();
+		die("After soft_reset_x - shouldn't see this message!!!\n");
+	}
+
+	post_code(0x3B);
+
+	/* It's the time to set ctrl in sysinfo now; */
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+	post_code(0x40);
+
+//	die("Die Before MCT init.");
+
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
+	raminit_amdmct(sysinfo);
+	post_code(0x41);
+
+/*
+	dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
+*/
+
+//	ram_check(0x00200000, 0x00200000 + (640 * 1024));
+//	ram_check(0x40200000, 0x40200000 + (640 * 1024));
+
+//	die("After MCT init before CAR disabled.");
+
+	rs780_before_pci_init();
+
+	post_code(0x42);
+	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
+	post_code(0x43);	// Should never see this post code.
+}
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+
+	return 0;
+}



From r.marek at assembler.cz  Thu Sep  8 12:49:51 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 08 Sep 2011 12:49:51 +0200
Subject: [coreboot] TPM support for SeaBIOS -- looking for a tester on
 real hardware
In-Reply-To: <87zkif8r8p.fsf@begreifnix.stackframe.org>
References: <4E677FEA.1060503@linux.vnet.ibm.com>
	<87zkif8r8p.fsf@begreifnix.stackframe.org>
Message-ID: <4E689DCF.1030804@assembler.cz>

Hi

 >no clue how TPM works, never played with it so far... :)

Well as far I know it is just a LPC device (if it is 1,1 device), make 
sure the region for that chip is decoded and enable
decoding of 0xfed0_0000 (sorry do not remember right range out of my 
head) in chipset which is needed for special LPC cycles. That is all I 
know. This special cycles have something in common with SKINIT or maybe 
with TPM 1.2

http://www.informit.com/articles/article.aspx?p=1154764&seqNum=3

Thanks
Rudolf






From stefanb at linux.vnet.ibm.com  Thu Sep  8 14:19:07 2011
From: stefanb at linux.vnet.ibm.com (Stefan Berger)
Date: Thu, 08 Sep 2011 08:19:07 -0400
Subject: [coreboot] TPM support for SeaBIOS -- looking for a tester on
 real hardware
In-Reply-To: <4E689DCF.1030804@assembler.cz>
References: <4E677FEA.1060503@linux.vnet.ibm.com>
	<87zkif8r8p.fsf@begreifnix.stackframe.org>
	<4E689DCF.1030804@assembler.cz>
Message-ID: <4E68B2BB.6050409@linux.vnet.ibm.com>

On 09/08/2011 06:49 AM, Rudolf Marek wrote:
> Hi
>
> >no clue how TPM works, never played with it so far... :)
>
> Well as far I know it is just a LPC device (if it is 1,1 device), make 
> sure the region for that chip is decoded and enable
> decoding of 0xfed0_0000 (sorry do not remember right range out of my 
> head) in chipset which is needed for special LPC cycles. That is all I 
> know. This special cycles have something in common with SKINIT or 
> maybe with TPM 1.2
>
A TPM 1.2 device has its mmio region at fed4 0000 - fed4 4fff. I am not 
sure whether coreboot needs to program some other hardware to enable 
that region but in Qemu with TPM device model SeaBIOS either did that or 
it 'just worked'.

    Stefan

> http://www.informit.com/articles/article.aspx?p=1154764&seqNum=3
>
> Thanks
> Rudolf
>
>
>




From stefanb at linux.vnet.ibm.com  Thu Sep  8 14:31:35 2011
From: stefanb at linux.vnet.ibm.com (Stefan Berger)
Date: Thu, 08 Sep 2011 08:31:35 -0400
Subject: [coreboot] TPM support for SeaBIOS -- looking for a tester on
 real hardware
In-Reply-To: <87zkif8r8p.fsf@begreifnix.stackframe.org>
References: <4E677FEA.1060503@linux.vnet.ibm.com>
	<87zkif8r8p.fsf@begreifnix.stackframe.org>
Message-ID: <4E68B5A7.7010508@linux.vnet.ibm.com>

On 09/08/2011 02:47 AM, Sven Schnelle wrote:
> Hi Stefan,
>
> Stefan Berger<stefanb at linux.vnet.ibm.com>  writes:
>
>>    Would anybody be interested in testing the TPM support I added to
>> SeaBIOS. I unfortunately don't have a motherboard myself where I could
>> try it. I have added the support to SeaBIOS for the TPM device model
>> in Qemu.  What you would need for trying it is a motherboard with a
>> TPM 1.2 on it. The SeaBIOS TPM support should recognize it, initialize
>> the TPM and allow the user to enter another SeaBIOS menu.
> I have coreboot + seabios running on Thinkpad X60s and T60p. IIRC both
> models have TPM onboard. I could give it a try, but i don't know if i
> have to add any code to coreboot for HW initialization. Actually i have
> no clue how TPM works, never played with it so far... :)
>
Could you pick up the patches from the SeaBIOS mailing list and try them?
The latest patches were posted in this thread:

http://www.seabios.org/pipermail/seabios/2011-August/002252.html


For compilation, the .config file in SeaBIOS would have to have

CONFIG_TCGBIOS=y

set for the TPM support to be compiled in.

Regards,
     Stefan
> Regards
>
> Sven
>




From gerrit at coreboot.org  Thu Sep  8 15:11:25 2011
From: gerrit at coreboot.org (Kerry She (shekairui@gmail.com))
Date: Thu, 8 Sep 2011 15:11:25 +0200
Subject: [coreboot] Patch set updated for coreboot: c718b21 rs780: hide
	unused gpp ports
References: <Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb+0@gerrit.coreboot.org>
Message-ID: <Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb+2@gerrit.coreboot.org>

Kerry She (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/206

-gerrit

commit c718b21c97e55b1ba9cacfa8abda1e695bde704f
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Sep 8 21:10:33 2011 +0800

    rs780: hide unused gpp ports
    
    hide unused gpp ports, test on avalue/eax-785e
    
    Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/southbridge/amd/rs780/gfx.c   |    2 ++
 src/southbridge/amd/rs780/pcie.c  |   19 +++++++++++++++++++
 src/southbridge/amd/rs780/rs780.c |    5 ++++-
 src/southbridge/amd/rs780/rs780.h |    1 +
 4 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 9262bb9..3c06d44 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -1009,6 +1009,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
 			set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
 		}
 	} else {		/* step 13.b Link Training was successful */
+		AtiPcieCfg.PortDetect |= 1 << 2; /* Port 2 */
 		set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
 		reg32 = nbpcie_p_read_index(dev, 0x29);
 		width = reg32 & 0xFF;
@@ -1064,6 +1065,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
 
 	} else {		/* step 16.b Link Training was successful */
+		AtiPcieCfg.PortDetect |= 1 << dev_ind;
 		reg32 = nbpcie_p_read_index(dev, 0xa2);
 		width = (reg32 >> 4) & 0x7;
 		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index 9cbd832..5c9647a 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -390,3 +390,22 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
 		switching_gpp_configurations(nb_dev, sb_dev);
 	ValidatePortEn(nb_dev);
 }
+
+/**
+ * Hide unused Gpp port
+ */
+void pcie_hide_unused_ports(device_t nb_dev)
+{
+	u8 port = 2;
+	u16 hide = 0x6FC;
+
+	for (port = 2; port <= 10; port++) {
+		if (port == 8)
+			continue;
+		hide &= ~((AtiPcieCfg.PortDetect & (1 << port)) |
+				(AtiPcieCfg.PortHp & (1 << port)));
+	}
+	printk(BIOS_INFO, "rs780 unused GPP ports bitmap=0x%03x, force disabled\n", hide);
+	set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFC, (hide & 0xFC)); /* bridge 2-7 */
+	set_nbmisc_enable_bits(nb_dev, 0x0C, 0x30000, ((hide >> 9) & 0x3) << 16); /* bridge 9-a */
+}
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index d8f1be3..b8c7d04 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -362,7 +362,10 @@ void rs780_enable(device_t dev)
 		if (dev->enabled)
 			rs780_gpp_sb_init(nb_dev, dev, dev_ind);
 
-		if (dev_ind == 10) disable_pcie_bar3(nb_dev);
+		if (dev_ind == 10) {
+			disable_pcie_bar3(nb_dev);
+			pcie_hide_unused_ports(nb_dev);
+		}
 		break;
 	default:
 		printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index aba3e69..5b8d251 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -213,4 +213,5 @@ u32 extractbits(u32 source, int lsb, int msb);
 int cpuidFamily(void);
 int is_family0Fh(void);
 int is_family10h(void);
+void pcie_hide_unused_ports(device_t nb_dev);
 #endif				/* RS780_H */



From gerrit at coreboot.org  Thu Sep  8 15:18:05 2011
From: gerrit at coreboot.org (Kerry She (shekairui@gmail.com))
Date: Thu, 8 Sep 2011 15:18:05 +0200
Subject: [coreboot] Patch set updated for coreboot: cda789e sb800: hide
	unused gpp ports
References: <I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0+0@gerrit.coreboot.org>
Message-ID: <I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0+2@gerrit.coreboot.org>

Kerry She (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/207

-gerrit

commit cda789ebb7bef35cee1ffe2bb007941be0348dee
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Sep 8 21:14:47 2011 +0800

    sb800: hide unused gpp ports
    
    hide unused gpp ports, test on avalue/eax-785e
    
    Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/mainboard/advansus/a785e-i/platform_cfg.h |    6 ++++++
 src/mainboard/amd/inagua/platform_cfg.h       |    6 ++++++
 src/mainboard/amd/persimmon/platform_cfg.h    |    6 ++++++
 src/mainboard/asrock/e350m1/platform_cfg.h    |    6 ++++++
 src/southbridge/amd/cimx/sb800/cfg.c          |    2 +-
 5 files changed, 25 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h
index ee68386..5fd49d6 100644
--- a/src/mainboard/advansus/a785e-i/platform_cfg.h
+++ b/src/mainboard/advansus/a785e-i/platform_cfg.h
@@ -211,6 +211,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index d37c7e6..ed761c4 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -211,6 +211,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index c6d2bd5..5c88719 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -211,6 +211,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
index 3267651..201d107 100644
--- a/src/mainboard/asrock/e350m1/platform_cfg.h
+++ b/src/mainboard/asrock/e350m1/platform_cfg.h
@@ -211,6 +211,12 @@
  */
 #define SB_GPP_GEN2			TRUE
 
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
 
 /**
  * @def   GEC_CONFIG
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 45a460b..3245449 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -110,7 +110,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
 	sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 	sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 	sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
-	sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
+	sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS;
 	sb_config->NbSbGen2 = NB_SB_GEN2;
 	sb_config->GppGen2 = SB_GPP_GEN2;
 



From gerrit at coreboot.org  Thu Sep  8 15:18:06 2011
From: gerrit at coreboot.org (Kerry She (shekairui@gmail.com))
Date: Thu, 8 Sep 2011 15:18:06 +0200
Subject: [coreboot] Patch set updated for coreboot: 8ef54d0 mainboard: add
	avalue/eax-785 ITX mainboard
References: <I483363f5ff9fbfc5cda2f0521660751212f3e326+0@gerrit.coreboot.org>
Message-ID: <I483363f5ff9fbfc5cda2f0521660751212f3e326+2@gerrit.coreboot.org>

Kerry She (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/208

-gerrit

commit 8ef54d0e84cdf9959c209815f511802a9cf230e1
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Sep 8 21:16:19 2011 +0800

    mainboard: add avalue/eax-785 ITX mainboard
    
    It's AM3 Socket, 880M + SB850 chipset, similar with advansus/a785e-i.
    Onboard device UART, VGA, SATA, PCI Slot, 2 X16 PCIe slot, 4 X1 Pcie
    slot, Lan, audio, PS2 keyboard/mouse and USB are verified.
    
    Change-Id: I483363f5ff9fbfc5cda2f0521660751212f3e326
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/mainboard/Kconfig                          |    3 +
 src/mainboard/avalue/Kconfig                   |   35 +
 src/mainboard/avalue/eax-785e/Kconfig          |  108 ++
 src/mainboard/avalue/eax-785e/Makefile.inc     |   18 +
 src/mainboard/avalue/eax-785e/acpi/cpstate.asl |   75 +
 src/mainboard/avalue/eax-785e/acpi/ide.asl     |  244 ++++
 src/mainboard/avalue/eax-785e/acpi/routing.asl |  398 ++++++
 src/mainboard/avalue/eax-785e/acpi/sata.asl    |  149 ++
 src/mainboard/avalue/eax-785e/acpi/usb.asl     |  161 +++
 src/mainboard/avalue/eax-785e/acpi_tables.c    |  274 ++++
 src/mainboard/avalue/eax-785e/chip.h           |   22 +
 src/mainboard/avalue/eax-785e/cmos.layout      |   98 ++
 src/mainboard/avalue/eax-785e/devicetree.cb    |  111 ++
 src/mainboard/avalue/eax-785e/dsdt.asl         | 1824 ++++++++++++++++++++++++
 src/mainboard/avalue/eax-785e/fadt.c           |  188 +++
 src/mainboard/avalue/eax-785e/get_bus_conf.c   |  154 ++
 src/mainboard/avalue/eax-785e/irq_tables.c     |  111 ++
 src/mainboard/avalue/eax-785e/mainboard.c      |  148 ++
 src/mainboard/avalue/eax-785e/mb_sysconf.h     |   43 +
 src/mainboard/avalue/eax-785e/mptable.c        |  158 ++
 src/mainboard/avalue/eax-785e/platform_cfg.h   |  235 +++
 src/mainboard/avalue/eax-785e/reset.c          |   63 +
 src/mainboard/avalue/eax-785e/resourcemap.c    |  278 ++++
 src/mainboard/avalue/eax-785e/romstage.c       |  266 ++++
 24 files changed, 5164 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index ed00318..13032a6 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -26,6 +26,8 @@ config VENDOR_ASUS
 	bool "ASUS"
 config VENDOR_A_TREND
 	bool "A-Trend"
+config VENDOR_AVALUE
+	bool "AVALUE"
 config VENDOR_AXUS
 	bool "AXUS"
 config VENDOR_AZZA
@@ -134,6 +136,7 @@ source "src/mainboard/artecgroup/Kconfig"
 source "src/mainboard/asi/Kconfig"
 source "src/mainboard/asrock/Kconfig"
 source "src/mainboard/asus/Kconfig"
+source "src/mainboard/avalue/Kconfig"
 source "src/mainboard/axus/Kconfig"
 source "src/mainboard/azza/Kconfig"
 source "src/mainboard/bcom/Kconfig"
diff --git a/src/mainboard/avalue/Kconfig b/src/mainboard/avalue/Kconfig
new file mode 100644
index 0000000..47e3486
--- /dev/null
+++ b/src/mainboard/avalue/Kconfig
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+if VENDOR_AVALUE
+
+choice
+	prompt "Mainboard model"
+
+config BOARD_AVALUE_EAX_785E
+	bool "EAX-785E"
+
+endchoice
+
+source "src/mainboard/avalue/eax-785e/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "AVALUE"
+
+endif # VENDOR_AVALUE
diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig
new file mode 100644
index 0000000..7aa90c8
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/Kconfig
@@ -0,0 +1,108 @@
+if BOARD_AVALUE_EAX_785E
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_SOCKET_AM3
+	select DIMM_DDR3
+	select DIMM_REGISTERED
+	select QRANK_DIMM_SUPPORT
+	select NORTHBRIDGE_AMD_AMDFAM10
+	select SOUTHBRIDGE_AMD_RS780
+	select SOUTHBRIDGE_AMD_CIMX_SB800
+	select SUPERIO_WINBOND_W83627HF #COM1, COM2
+	#select SUPERIO_FINTEK_F81216AD #COM3, COM4
+	select SB_SUPERIO_HWM
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select AMDMCT
+	select HAVE_MP_TABLE
+	select HAVE_ACPI_TABLES
+	select BOARD_HAS_FADT
+	select BOARD_ROMSIZE_KB_2048
+	select RAMINIT_SYSINFO
+	select ENABLE_APIC_EXT_ID
+	select TINY_BOOTBLOCK
+	select GFXUMA
+	select HAVE_DEBUG_CAR
+	select SET_FIDVID
+
+config MAINBOARD_DIR
+	string
+	default avalue/eax-785e
+
+config APIC_ID_OFFSET
+	hex
+	default 0x0
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EAX-785E"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+
+config MEM_TRAIN_SEQ
+	int
+	default 2
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x1
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config AMD_UCODE_PATCH_FILE
+	string
+	default "mc_patch_010000b6.h"
+
+config RAMTOP
+	hex
+	default 0x2000000
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+config RAMBASE
+	hex
+	default 0x200000
+
+config VGA_BIOS_ID
+        string
+        default "1002,9712"
+
+config SIO_PORT
+        hex
+        default 0x2E
+
+endif #BOARD_AVALUE_EAX_785E
diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc
new file mode 100644
index 0000000..737bb1c
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/Makefile.inc
@@ -0,0 +1,18 @@
+#romstage-y += reset.c #FIXME romstage have include test_rest.c
+
+ramstage-y += reset.c
+
+#SB800 CIMx share AGESA V5 lib code
+ifneq ($(CONFIG_AMD_AGESA),y)
+ AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+ romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+ ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+
+ AGESA_INC := -I$(AGESA_ROOT)/ \
+	      -I$(AGESA_ROOT)/Include \
+	      -I$(AGESA_ROOT)/Proc/IDS/ \
+	      -I$(AGESA_ROOT)/Proc/CPU/ \
+	      -I$(AGESA_ROOT)/Proc/CPU/Family
+
+ CFLAGS += $(AGESA_INC)
+endif
diff --git a/src/mainboard/avalue/eax-785e/acpi/cpstate.asl b/src/mainboard/avalue/eax-785e/acpi/cpstate.asl
new file mode 100644
index 0000000..5eca9cc
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}
diff --git a/src/mainboard/avalue/eax-785e/acpi/ide.asl b/src/mainboard/avalue/eax-785e/acpi/ide.asl
new file mode 100644
index 0000000..c79c18c
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}
diff --git a/src/mainboard/avalue/eax-785e/acpi/routing.asl b/src/mainboard/avalue/eax-785e/acpi/routing.asl
new file mode 100644
index 0000000..cb50394
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/routing.asl
@@ -0,0 +1,398 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+
+		Package(){0x0009FFFF, 0, INTB, 0 },
+		Package(){0x0009FFFF, 1, INTC, 0 },
+		Package(){0x0009FFFF, 2, INTD, 0 },
+		Package(){0x0009FFFF, 3, INTA, 0 },
+
+		Package(){0x000AFFFF, 0, INTC, 0 },
+		Package(){0x000AFFFF, 1, INTD, 0 },
+		Package(){0x000AFFFF, 2, INTA, 0 },
+		Package(){0x000AFFFF, 3, INTB, 0 },
+
+		Package(){0x000BFFFF, 0, INTD, 0 },
+		Package(){0x000BFFFF, 1, INTA, 0 },
+		Package(){0x000BFFFF, 2, INTB, 0 },
+		Package(){0x000BFFFF, 3, INTC, 0 },
+
+		Package(){0x000CFFFF, 0, INTA, 0 },
+		Package(){0x000CFFFF, 1, INTB, 0 },
+		Package(){0x000CFFFF, 2, INTC, 0 },
+		Package(){0x000CFFFF, 3, INTD, 0 },
+
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		Package(){0x0016FFFF, 1, INTB, 0 },
+
+		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+
+		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, 0, 18 },
+		package(){0x0001FFFF, 1, 0, 19 },
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, 0, 17 }, */
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Package(){0x0006FFFF, 0, 0, 18 }, */
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Package(){0x0007FFFF, 0, 0, 19 }, */
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Dev 9 - PCIe Bridge for network card */
+		Package(){0x0009FFFF, 0, 0, 17 },
+		/* Package(){0x0009FFFF, 1, 0, 16 }, */
+		/* Package(){0x0009FFFF, 2, 0, 17 }, */
+		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		/* Bus 0, Dev A - PCIe Bridge for network card */
+		Package(){0x000AFFFF, 0, 0, 18 },
+		/* Package(){0x000AFFFF, 1, 0, 16 }, */
+		/* Package(){0x000AFFFF, 2, 0, 17 }, */
+		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, 0, 18 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		/* Package(){0x0012FFFF, 2, 0, 18 }, */
+
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+		/* Package(){0x0013FFFF, 2, 0, 16 }, */
+
+		/* Package(){0x00140000, 0, 0, 16 }, */
+
+		Package(){0x0016FFFF, 0, 0, 18 },
+		Package(){0x0016FFFF, 1, 0, 17 },
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+
+		/* TODO: pcie */
+		Package(){0x0015FFFF, 0, 0, 16 },
+		Package(){0x0015FFFF, 1, 0, 17 },
+		Package(){0x0015FFFF, 2, 0, 18 },
+		Package(){0x0015FFFF, 3, 0, 19 },
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+	Name(APR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE0, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APE0, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PE1, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APE1, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PE2, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APE2, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE3, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APE3, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+		Package(){0x0007FFFF, 0, 0, 0x16 },
+		Package(){0x0007FFFF, 1, 0, 0x17 },
+		Package(){0x0007FFFF, 2, 0, 0x14 },
+		Package(){0x0007FFFF, 3, 0, 0x15 },
+	})
+}
diff --git a/src/mainboard/avalue/eax-785e/acpi/sata.asl b/src/mainboard/avalue/eax-785e/acpi/sata.asl
new file mode 100644
index 0000000..bd4acf0
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00110000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}
diff --git a/src/mainboard/avalue/eax-785e/acpi/usb.asl b/src/mainboard/avalue/eax-785e/acpi/usb.asl
new file mode 100644
index 0000000..81ea9a2
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi/usb.asl
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "usb.asl"
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+	Scope (\_GPE) {
+		Method (_L1A) {
+			UCOC()
+			if (LEqual(GPB5,PLC5)) {
+				Not(PLC5,PLC5)
+				Store(PLC5, \_SB.PT5D)
+			}
+		}
+	}
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}
diff --git a/src/mainboard/avalue/eax-785e/acpi_tables.c b/src/mainboard/avalue/eax-785e/acpi_tables.c
new file mode 100644
index 0000000..7c8ca76
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/acpi_tables.c
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+#include "mb_sysconf.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+extern const unsigned char AmlCode_ssdt2[];
+extern const unsigned char AmlCode_ssdt3[];
+extern const unsigned char AmlCode_ssdt4[];
+extern const unsigned char AmlCode_ssdt5[];
+#endif
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+	acpi_header_t *ssdtx;
+	void *p;
+	int i;
+#endif
+
+	get_bus_conf();	/* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	/* SLIT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdp, slit);
+
+	/* SSDT */
+	current	  = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)current;
+	memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+	current += ssdt->length;
+	memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+	//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
+	update_ssdt((void*)ssdt);
+	/* recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	current = acpi_add_ssdt_pstates(rsdp, current);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+
+	/* same htio, but different position? We may have to copy,
+	change HCIN, and recalculate the checknum and add_table */
+
+	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+		if((sysconf.pci1234[i] & 1) != 1 ) continue;
+		u8 c;
+		if (i < 7) {
+			c = (u8) ('4' + i - 1);
+		} else {
+			c = (u8) ('A' + i - 1 - 6);
+		}
+		current	  = ( current + 0x07) & -0x08;
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
+		ssdtx = (acpi_header_t *)current;
+		switch (sysconf.hcid[i]) {
+		case 1:
+			p = &AmlCode_ssdt2;
+			break;
+		case 2:
+			p = &AmlCode_ssdt3;
+			break;
+		case 3:	/* 8131 */
+			p = &AmlCode_ssdt4;
+			break;
+		default:
+			/* HTX no io apic */
+			p = &AmlCode_ssdt5;
+			break;
+		}
+		memcpy(ssdtx, p, sizeof(acpi_header_t));
+		current += ssdtx->length;
+		memcpy(ssdtx, p, ssdtx->length);
+		update_ssdtx((void *)ssdtx, i);
+		ssdtx->checksum = 0;
+		ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
+		acpi_add_table(rsdp, ssdtx);
+	}
+#endif
+
+	/* DSDT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FDAT */
+#if CONFIG_BOARD_HAS_FADT == 1
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+#endif
+
+#if DUMP_ACPI_TABLES == 1
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/avalue/eax-785e/chip.h b/src/mainboard/avalue/eax-785e/chip.h
new file mode 100644
index 0000000..5957589
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/chip.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/avalue/eax-785e/cmos.layout b/src/mainboard/avalue/eax-785e/cmos.layout
new file mode 100644
index 0000000..53fdef5
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/cmos.layout
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/avalue/eax-785e/devicetree.cb b/src/mainboard/avalue/eax-785e/devicetree.cb
new file mode 100644
index 0000000..bf58f90
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/devicetree.cb
@@ -0,0 +1,111 @@
+# sample config for avalue/EAX-785E
+chip northbridge/amd/amdfam10/root_complex
+	device lapic_cluster 0 on
+		chip cpu/amd/socket_AM3  #L1 and DDR3
+			 device lapic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id.
+		chip northbridge/amd/amdfam10
+			device pci 18.0 on #  northbridge
+				chip southbridge/amd/rs780
+					device pci 0.0 on end # HT 0x9600
+					device pci 1.0 on end # Internal Graphics P2P bridge 0x9712
+					device pci 2.0 on end # GFX_RX0-7/TX0-7   PCIEx16_1 slot
+					device pci 3.0 on end # GFX_RX8-15/TX8-15 PCIEx16_2 slot
+					device pci 4.0 on end # PortB GPP_RX/TX0 PCIEx1_1 slot
+					device pci 5.0 on end # PortC GPP_RX/TX1 PCIEx1_2 slot
+					device pci 6.0 on end # PortD GPP_RX/TX2 PCIEx1_3 slot
+					device pci 7.0 on end # PortE GPP_RX/TX3 PCIEx1_4 slot
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					device pci 9.0 on end # Ethernet
+					device pci a.0 on end # Ethernet
+					register "gppsb_configuration" = "4"	# Configuration E
+					register "gpp_configuration" = "3"	# Configuration D
+					register "port_enable" = "0x6FE"
+					register "gfx_dev2_dev3" = "0" #no use
+					register "gfx_dual_slot" = "1" # 0 single slot, 1 dual slot
+					register "gfx_lane_reversal" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+					register "gfx_tmds" = "1"
+					register "gfx_pcie_config" = "4" # 2x8 GFX, one on Lanes 0-7, one on Lanes 8-15
+					register "gfx_ddi_config" = "0"  # no DDI_SL
+				end
+				chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.2 on end # USB
+					device pci 14.0 on end # SM
+					device pci 14.1 on end # IDE    0x439c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on
+                                                chip superio/winbond/w83627hf
+                                                        device pnp 2e.0 off #  Floppy
+                                                                io 0x60 = 0x3f0
+                                                                irq 0x70 = 6
+                                                                drq 0x74 = 2
+                                                        end
+                                                        device pnp 2e.1 off #  Parallel Port
+                                                                io 0x60 = 0x378
+                                                                irq 0x70 = 7
+                                                        end
+                                                        device pnp 2e.2 on #  Com1
+                                                                io 0x60 = 0x3f8
+                                                                irq 0x70 = 4
+                                                        end
+                                                        device pnp 2e.3 on #  Com2
+                                                                io 0x60 = 0x2f8
+                                                                irq 0x70 = 3
+                                                        end
+                                                        device pnp 2e.5 on #  PS/2 Keyboard & mouse
+                                                                io 0x60 = 0x60
+                                                                io 0x62 = 0x64
+                                                                irq 0x70 = 1
+                                                                irq 0x72 = 12
+                                                        end
+                                                        device pnp 2e.6 off  # SFI
+                                                                io 0x62 = 0x100
+                                                        end
+                                                        device pnp 2e.7 off #  GPIO_GAME_MIDI
+                                                                io 0x60 = 0x220
+                                                                io 0x62 = 0x300
+                                                                irq 0x70 = 9
+                                                        end
+                                                        device pnp 2e.8 off end #  WDTO_PLED
+                                                        device pnp 2e.9 off end #  GPIO_SUSLED
+                                                        device pnp 2e.a off end #  ACPI
+                                                        device pnp 2e.b on #  HW Monitor
+                                                                io 0x60 = 0x290
+                                                                irq 0x70 = 5
+                                                        end
+                                                end     #superio/winbond/w83627hf
+					end # LPC	0x439d
+					device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+					device pci 14.5 on end # USB 2
+					device pci 14.6 off end # Gec
+					device pci 15.0 off end # PCIe 0
+					device pci 15.1 off end # PCIe 1
+					device pci 15.2 off end # PCIe 2
+					device pci 15.3 on end # PCIe 3
+					device pci 16.0 on end # USB
+					device pci 16.2 on end # USB
+					#register "gpp_configuration" = "0" #4:0:0:0
+					#register "gpp_configuration" = "2" #2:2:0:0
+					#register "gpp_configuration" = "3" #2:1:1:0
+					register "gpp_configuration" = "4" #1:1:1:1
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				end	#southbridge/amd/cimx/sb800
+			end #  device pci 18.0
+
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+		end
+	end #pci_domain
+end
diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl
new file mode 100644
index 0000000..1287f95
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/dsdt.asl
@@ -0,0 +1,1824 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"AVALUE  ",               /* OEMID */
+	"EAX-785E",	     /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include "../../../arch/x86/acpi/debug.asl" */		/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			CPU0,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU1,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU2,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU3,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+	} /* End _PR scope */
+
+	/* PIC IRQ mapping registers, C00h-C01h. */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PIRA, 0x00000008,	/* Index 0 */
+		PIRB, 0x00000008,	/* Index 1 */
+		PIRC, 0x00000008,	/* Index 2 */
+		PIRD, 0x00000008,	/* Index 3 */
+		PIRE, 0x00000008,	/* Index 4 */
+		PIRF, 0x00000008,	/* Index 5 */
+		PIRG, 0x00000008,	/* Index 6 */
+		PIRH, 0x00000008,	/* Index 7 */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk. TODO: should be 0x60 */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve){
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+
+	#include "acpi/routing.asl"
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+		Method(CIRQ, 0x00, NotSerialized){
+			Store(0, PIRA)
+			Store(0, PIRB)
+			Store(0, PIRC)
+			Store(0, PIRD)
+			Store(0, PIRE)
+			Store(0, PIRF)
+			Store(0, PIRG)
+			Store(0, PIRH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PIRA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PIRA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PIRB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PIRB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PIRC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PIRC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIRD) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIRD)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRD, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRD)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PIRE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PIRE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PIRF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PIRF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PIRG) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PIRG)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRG, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRG)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PIRH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PIRH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			/* Notify (\_TZ.TZ00, 0x80) */
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event - Moved to USB.asl */
+		/* Method(_L1A) {
+		*	DBGO("\\_GPE\\_L1A\n")
+		* }
+		*/
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	#include "acpi/usb.asl"
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			External (TOM1)
+			External (TOM2)
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+			/* GPP */
+			Device(PBR9) {
+				Name(_ADR, 0x00090000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS9) }   /* APIC mode */
+					Return (PS9)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR9 */
+
+			Device(PBRa) {
+				Name(_ADR, 0x000A0000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APSa) }   /* APIC mode */
+					Return (PSa)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBRa */
+
+			Device(PE20) {
+				Name(_ADR, 0x00150000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE0) }   /* APIC mode */
+					Return (PE0)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE20 */
+			Device(PE21) {
+				Name(_ADR, 0x00150001)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE1) }   /* APIC mode */
+					Return (PE1)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE21 */
+			Device(PE22) {
+				Name(_ADR, 0x00150002)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE2) }   /* APIC mode */
+					Return (APE2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE22 */
+			Device(PE23) {
+				Name(_ADR, 0x00150003)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE3) }   /* APIC mode */
+					Return (PE3)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE23 */
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00110000)
+				#include "acpi/sata.asl"
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00120000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00120002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00160000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UOH6) {
+				Name(_ADR, 0x00160002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00140005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				#include "acpi/ide.asl"
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#if 0
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#endif
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* length */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+#if 0
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/*  Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/*  Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+#endif
+                                /* memory space for PCI BARs below 4GB */
+                                Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+#if 0
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM1, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	Subtract(TOM2, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+#endif
+                                CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+                                CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+                                /*
+                                 * Declare memory between TOM1 and 4GB as available
+                                 * for PCI MMIO.
+                                 * Use ShiftLeft to avoid 64bit constant (for XP).
+                                 * This will work even if the OS does 32bit arithmetic, as
+                                 * 32bit (0x00000000 - TOM1) will wrap and give the same
+                                 * result as 64bit (0x100000000 - TOM1).
+                                 */
+                                Store(TOM1, MM1B)
+                                ShiftLeft(0x10000000, 4, Local0)
+                                Subtract(Local0, TOM1, Local0)
+                                Store(Local0, MM1L)
+
+				Return(CRES) /* note to change the Name buffer */
+			}  /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+#if 0
+	/* SMBUS Support */
+	Mutex (SBX0, 0x00)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x10, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+			If (LEqual (Local0, Zero)) {
+				Release (SBX0)
+				Return (0x0)
+			}
+
+			Store (0x1F, HSTS)
+			Store (Or (ShiftLeft (Arg1, One), One), HADD)
+			Store (Arg2, HCMD)
+			If (LEqual (Arg0, 0x07)) {
+				Store (0x48, HCNT) /* read byte */
+			}
+
+			Store (SWTC (0x03E8), Local1) /* 1000 ms */
+			If (LEqual (Local1, Zero)) {
+				If (LEqual (Arg0, 0x07)) {
+					Store (DAT0, Local0)
+				}
+			}
+			Else {
+				Store (Local1, Local0)
+			}
+
+			Release (SBX0)
+		}
+
+		/* DBGO("the value of SMBusData0 register ") */
+		/* DBGO(Arg2) */
+		/* DBGO(" is ") */
+		/* DBGO(Local0) */
+		/* DBGO("\n") */
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 2732)
+		Name (THOT, 800)
+		Name (TCRT, 850)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+				If (LGreater (Local0, 0x10)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400, KELV))
+				}
+
+				Store (SMBR (0x07, 0x4C, 0x01), Local0)
+				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+				If (LGreater (Local0, 0x10)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Multiply (Local1, 10, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+#endif
+}
+/* End of ASL file */
diff --git a/src/mainboard/avalue/eax-785e/fadt.c b/src/mainboard/avalue/eax-785e/fadt.c
new file mode 100644
index 0000000..f84b379
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/fadt.c
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "SBPLATFORM.h"
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	u16 val = 0;
+	acpi_header_t *header = &(fadt->header);
+
+	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	val = PM1_EVT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+	val = PM1_CNT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+	val = PM1_TMR_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+	val = GPE0_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
+
+	/* CpuControl is in \_PR.CPU0, 6 bytes */
+	val = CPU_CNT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+	val = 0;
+	WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+	val = ACPI_PMA_CNT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
+
+	/* AcpiDecodeEnable, When set, SB uses the contents of the
+	 * PM registers at index 60-6B to decode ACPI I/O address.
+	 * AcpiSmiEn & SmiCmdEn*/
+	val = BIT0 | BIT1 | BIT2 | BIT4;
+	WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
+
+	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, PM1_CNT_BLK_ADDRESS);		  /* set SCI_EN */
+
+	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}
diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c
new file mode 100644
index 0000000..20a856e
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/multicore.h>
+#endif
+#include <cpu/amd/amdfam10_sysconf.h>
+#if CONFIG_AMD_SB_CIMX == 1
+#include <sb_cimx.h>
+#endif
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+int bus_isa;
+u8 bus_rs780[11];
+u8 bus_sb800[3];
+u32 apicid_sb800;
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+	0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+	0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_rs780;
+u32 sbdn_sb800;
+
+extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+	u32 apicid_base;
+	device_t dev;
+	int i, j;
+
+	if (get_bus_conf_done == 1)
+		return;		/* do it only once */
+	get_bus_conf_done = 1;
+
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+	for (i = 0; i < sysconf.hc_possible_num; i++) {
+		sysconf.pci1234[i] = pci1234x[i];
+		sysconf.hcdn[i] = hcdnx[i];
+	}
+
+	get_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
+	sbdn_rs780 = sysconf.sbdn;
+	sbdn_sb800 = 0;
+
+	for (i = 0; i < 3; i++) {
+		bus_sb800[i] = 0;
+	}
+	for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
+		bus_rs780[i] = 0;
+	}
+
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+	bus_type[0] = 1;	/* pci */
+
+	bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb800[0] = bus_rs780[0];
+
+	bus_type[bus_rs780[0]] = 1;
+
+	/* sb800 */
+	dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+	if (dev) {
+		bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb800[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	for (i = 0; i < 4; i++) {
+		dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x15, i));
+		if (dev) {
+			bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+			bus_isa++;
+		}
+	}
+	for (j = bus_sb800[2]; j < bus_isa; j++)
+		bus_type[j] = 1;
+
+	/* rs780 */
+	for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
+		dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
+		if (dev) {
+			bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			if(255 != bus_rs780[i]) {
+				bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+				bus_isa++;
+				bus_type[bus_rs780[i]] = 1; /* PCI bus. */
+			}
+		}
+	}
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+	apicid_sb800 = apicid_base + 0;
+
+#if CONFIG_AMD_SB_CIMX == 1
+	sb_Late_Post();
+#endif
+}
diff --git a/src/mainboard/avalue/eax-785e/irq_tables.c b/src/mainboard/avalue/eax-785e/irq_tables.c
new file mode 100644
index 0000000..fd74e3a
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/irq_tables.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			    u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+
+extern u8 bus_isa;
+extern u8 bus_rs780[8];
+extern u8 bus_sb800[2];
+extern unsigned long sbdn_sb800;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb800[0];
+	pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+	slot_num++;
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
new file mode 100644
index 0000000..7f55c03
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/mainboard.c
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "SBPLATFORM.h"
+#include "chip.h"
+
+uint64_t uma_memory_base, uma_memory_size;
+
+u8 is_dev3_present(void);
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+void enable_int_gfx(void);
+
+/* GPIO6. */
+void enable_int_gfx(void)
+{
+	volatile u8 *gpio_reg;
+
+#ifdef UNUSED_CODE
+	RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
+	RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
+#endif
+	/* make sure the Acpi MMIO(fed80000) is accessible */
+        RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
+
+	gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
+
+	*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
+	*(gpio_reg + 170) = 0x1; /* gpio_gate */
+
+	gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
+
+	*(gpio_reg + 0x6) = 0x8;
+	*(gpio_reg + 170) = 0x0;
+}
+
+void set_pcie_dereset()
+{
+}
+
+void set_pcie_reset(void)
+{
+}
+
+u8 is_dev3_present(void)
+{
+	return 1;
+}
+
+
+/*************************************************
+* enable the dedicated function in EAX-785E board.
+* This function called early than rs780_enable.
+*************************************************/
+static void eax_785e(device_t dev)
+{
+	/* Leave it for furture use. */
+	/* struct mainboard_config *mainboard =
+	   (struct mainboard_config *)dev->chip_info; */
+
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+#if (CONFIG_GFXUMA == 1)
+	msr_t msr, msr2;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	/* refer to UMA Size Consideration in 780 BDG. */
+	switch (msr.lo) {
+	case 0x10000000:	/* 256M system memory */
+		uma_memory_size = 0x4000000;	/* 64M recommended UMA */
+		break;
+
+	case 0x20000000:	/* 512M system memory */
+		uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+		break;
+
+	default:		/* 1GB and above system memory */
+		uma_memory_size = 0x10000000;	/* 256M recommended UMA */
+		break;
+	}
+
+	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+		    __func__, uma_memory_size, uma_memory_base);
+
+	/* TODO: TOP_MEM2 */
+#else
+	uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+	uma_memory_base = 0x38000000;	/* 1GB  system memory supposed */
+#endif
+
+	set_pcie_dereset();
+	enable_int_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	/* UMA is removed from system memory in the northbridge code, but
+	 * in some circumstances we want the memory mentioned as reserved.
+	 */
+#if (CONFIG_GFXUMA == 1)
+	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+		    uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+			    uma_memory_size);
+#endif
+	return 0;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+	.enable_dev = eax_785e,
+};
diff --git a/src/mainboard/avalue/eax-785e/mb_sysconf.h b/src/mainboard/avalue/eax-785e/mb_sysconf.h
new file mode 100644
index 0000000..ca5870c
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/mb_sysconf.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+	u8 bus_isa;
+	u8 bus_8132_0;
+	u8 bus_8132_1;
+	u8 bus_8132_2;
+	u8 bus_8111_0;
+	u8 bus_8111_1;
+	u8 bus_8132a[31][3];
+	u8 bus_8151[31][2];
+
+	u32 apicid_8111;
+	u32 apicid_8132_1;
+	u32 apicid_8132_2;
+	u32 apicid_8132a[31][2];
+	u32 sbdn3;
+	u32 sbdn3a[31];
+	u32 sbdn5[31];
+	u32 bus_type[256];
+};
+
+#endif
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
new file mode 100644
index 0000000..e4fc23b
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <SBPLATFORM.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern int bus_isa;
+extern u8 bus_rs780[11];
+extern u8 bus_sb800[2];
+extern u32 apicid_sb800;
+extern u32 bus_type[256];
+extern u32 sbdn_rs780;
+extern u32 sbdn_sb800;
+
+u8 intr_data[] = {
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
+};
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	u32 dword;
+	u8 byte;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LAPIC_ADDR);
+
+	smp_write_processors(mc);
+
+	get_bus_conf();
+
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+	dword &= 0xFFFFFFF0;
+
+	smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#if CONFIG_GENERATE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
+
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);
+	PCI_INT(0x0, 0x14, 0x4, 0x11);
+
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+	/* on board NIC & Slot PCIE.  */
+	/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
+/* 	PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
+	PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
+	/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
+	PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
+	/* configuration B doesnt need dev 5,6,7 */
+	/*
+	 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
+	 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
+	 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
+	 */
+	PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
+	PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum =
+	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+		     mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h
new file mode 100644
index 0000000..24dcae0
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/platform_cfg.h
@@ -0,0 +1,235 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _EAX_785E_CFG_H_
+#define _EAX_785E_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M			0
+#define BIOS_SIZE_2M			1
+#define BIOS_SIZE_4M			3
+#define BIOS_SIZE_8M			7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#ifndef BIOS_SIZE
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+  #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+  #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+  #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+  #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ *  0 - Disable Spread Spectrum function
+ *  1 - Enable  Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM			0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ *  0 - Disable hpet
+ *  1 - Enable  hpet
+ */
+#define HPET_TIMER			1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ *   0 - Disable
+ *   1 - Enable
+ *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG		0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ *   0 - disable
+ *   1 - enable
+ *  PCI SLOT 0 define at BIT0
+ *  PCI SLOT 1 define at BIT1
+ *  PCI SLOT 2 define at BIT2
+ *  PCI SLOT 3 define at BIT3
+ *  PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL			0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE			NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE			0
+#define IDE_NATIVE_MODE			1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE			IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ *  PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK		0x00
+#define INTERNAL_CLOCK		0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED	1
+
+
+/**
+ * @def   AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def   AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def   AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO			0
+#define AZALIA_DISABLE			1
+#define AZALIA_ENABLE			2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER		AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ *  0 - disable
+ *  1 - enable
+ */
+#define AZALIA_PIN_CONFIG		1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ *  SDIN0 is define at BIT0 & BIT1
+ *   00 - GPIO PIN
+ *   01 - Reserved
+ *   10 - As a Azalia SDIN pin
+ *  SDIN1 is define at BIT2 & BIT3
+ *  SDIN2 is define at BIT4 & BIT5
+ *  SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN		0xAA
+#define AZALIA_SDIN_PIN			0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ *  GPP_CFGMODE_X4000
+ *  GPP_CFGMODE_X2200
+ *  GPP_CFGMODE_X2110
+ *  GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE			GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ *    0  - Disable
+ *    1  - Enable
+ */
+#define NB_SB_GEN2			TRUE
+
+/**
+ * @def SB_GEN2
+ *    0  - Disable
+ *    1  - Enable
+ */
+#define SB_GPP_GEN2			TRUE
+
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ *    TRUE   - ports visable always, even port empty
+ *    FALSE  - ports invisable if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS		FALSE
+
+/**
+ * @def   GEC_CONFIG
+ *    0  - Enable
+ *    1  - Disable
+ */
+#define GEC_CONFIG			0
+
+/**
+ * @def SIO_HWM_BASE_ADDRESS  Super IO HWM base address
+ */
+#define SIO_HWM_BASE_ADDRESS		0x290
+
+#endif
diff --git a/src/mainboard/avalue/eax-785e/reset.c b/src/mainboard/avalue/eax-785e/reset.c
new file mode 100644
index 0000000..5212b3a
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/reset.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes, htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for (i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
diff --git a/src/mainboard/avalue/eax-785e/resourcemap.c b/src/mainboard/avalue/eax-785e/resourcemap.c
new file mode 100644
index 0000000..06102b0
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/resourcemap.c
@@ -0,0 +1,278 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration regin i
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+	};
+
+	int max;
+	max = ARRAY_SIZE(register_values);
+	setup_resource_map(register_values, max);
+}
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
new file mode 100644
index 0000000..beea992
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+//#define SYSTEM_TYPE 0	/* SERVER */
+#define SYSTEM_TYPE 1	/* DESKTOP */
+//#define SYSTEM_TYPE 2	/* MOBILE */
+
+//used by incoherent_ht
+#define FAM10_SCAN_PCI_BUS 0
+#define FAM10_ALLOCATE_IO_RANGE 0
+
+#include <lib.h>
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <cpu/amd/model_10xxx_rev.h>
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdfam10/reset_test.c"
+#include <console/loglevel.h>
+#include "cpu/x86/bist.h"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include <sb_cimx.h>
+#include <SBPLATFORM.h> /* SB OEM constants */
+#include <southbridge/amd/cimx/sb800/smbus.h>
+#include "northbridge/amd/amdfam10/debug.c"
+
+static void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+static int spd_read_byte(u32 device, u32 address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/pci.c"
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#if CONFIG_UPDATE_CPU_MICROCODE
+#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "northbridge/amd/amdfam10/early_ht.c"
+#include "spd.h"
+
+#include <reset.h>
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
+	u32 bsp_apicid = 0, val;
+	msr_t msr;
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		/* mov bsp to bus 0xff when > 8 nodes */
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		//enable port80 decoding and southbridge poweron init
+		sb_Poweron_Init();
+	}
+
+	post_code(0x30);
+
+	if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
+		/* All cores run this but the BSP(node0,core0) is the only core that returns. */
+	}
+
+	post_code(0x32);
+
+	enable_rs780_dev8();
+	sb800_clk_output_48Mhz();
+
+	w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0));
+	w83627hf_enable_serial(0, CONFIG_TTYS0_BASE);
+
+	uart_init();
+	console_init();
+	printk(BIOS_DEBUG, "\n");
+
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+	printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	/* Setup sysinfo defaults */
+	set_sysinfo_in_ram(0);
+
+#if CONFIG_UPDATE_CPU_MICROCODE
+	update_microcode(val);
+#endif
+	post_code(0x33);
+
+	cpuSetAMDMSR();
+	post_code(0x34);
+
+	amd_ht_init(sysinfo);
+	post_code(0x35);
+
+	/* Setup nodes PCI space and start core 0 AP init. */
+	finalize_node_setup(sysinfo);
+
+	/* Setup any mainboard PCI settings etc. */
+	setup_mb_resource_map();
+	post_code(0x36);
+
+	/* wait for all the APs core0 started by finalize_node_setup. */
+	/* FIXME: A bunch of cores are going to start output to serial at once.
+	   It would be nice to fixup prink spinlocks for ROM XIP mode.
+	   I think it could be done by putting the spinlock flag in the cache
+	   of the BSP located right after sysinfo.
+	 */
+	wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* Core0 on each node is configured. Now setup any additional cores. */
+	printk(BIOS_DEBUG, "start_other_cores()\n");
+	start_other_cores();
+	post_code(0x37);
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+
+	post_code(0x38);
+
+	/* run _early_setup before soft-reset. */
+	rs780_early_setup();
+
+#if CONFIG_SET_FIDVID == 1
+	msr = rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	post_code(0x39);
+
+	if (!warm_reset_detect(0)) {			// BSP is node 0
+		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+	} else {
+		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
+	}
+
+	post_code(0x3A);
+
+	/* show final fid and vid */
+	msr=rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+#endif
+
+	rs780_htinit();
+
+	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	if (!warm_reset_detect(0)) {
+		print_info("...WARM RESET...\n\n\n");
+		soft_reset();
+		die("After soft_reset_x - shouldn't see this message!!!\n");
+	}
+
+	post_code(0x3B);
+
+	/* It's the time to set ctrl in sysinfo now; */
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+	post_code(0x40);
+
+//	die("Die Before MCT init.");
+
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
+	raminit_amdmct(sysinfo);
+	post_code(0x41);
+
+/*
+	dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
+*/
+
+//	ram_check(0x00200000, 0x00200000 + (640 * 1024));
+//	ram_check(0x40200000, 0x40200000 + (640 * 1024));
+
+//	die("After MCT init before CAR disabled.");
+
+	rs780_before_pci_init();
+
+	post_code(0x42);
+	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
+	post_code(0x43);	// Should never see this post code.
+}
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+
+	return 0;
+}



From mbuschman at lucidmachines.com  Thu Sep  8 17:49:52 2011
From: mbuschman at lucidmachines.com (Marshall Buschman)
Date: Thu, 08 Sep 2011 10:49:52 -0500
Subject: [coreboot] E350M1 does not POST
In-Reply-To: <F53A09371FB723428826B442A4B20A41075EB688@sbjgexmb1.amd.com>
References: <E1Qu5au-0000TM-Aq@taishi.runbox.com><F53A09371FB723428826B442A4B20A410758DCA9@sbjgexmb1.amd.com><4E679E17.7070902@lucidmachines.com>
	<4E682206.9090808@lucidmachines.com>
	<F53A09371FB723428826B442A4B20A41075EB688@sbjgexmb1.amd.com>
Message-ID: <4E68E420.7090803@lucidmachines.com>

On 09/07/2011 11:56 PM, She, Kerry wrote:
>
> Hello, Marshall
>
> *From:*coreboot-bounces at coreboot.org 
> [mailto:coreboot-bounces at coreboot.org] *On Behalf Of *Marshall Buschman
> *Sent:* Thursday, September 08, 2011 10:02 AM
> *To:* coreboot at coreboot.org
> *Subject:* Re: [coreboot] E350M1 does not POST
>
> On 09/07/2011 11:38 AM, Marshall Buschman wrote:
>
> I have access to an E350M1. I will test these patches tonight and 
> report back with results.
>
> Thank you!
> -Marshall Buschman
>
> On 09/07/2011 02:53 AM, She, Kerry wrote:
>
>   
>
>     -----Original Message-----
>
>     From:coreboot-bounces at coreboot.org  <mailto:coreboot-bounces at coreboot.org>  [mailto:coreboot-
>
>     bounces at coreboot.org  <mailto:bounces at coreboot.org>] On Behalf Ofperh52 at runbox.com  <mailto:perh52 at runbox.com>
>
>     Sent: Friday, August 19, 2011 12:37 AM
>
>     To: coreboot
>
>     Subject: [coreboot] E350M1 does not POST
>
>       
>
>                 Hi,
>
>                   
>
>                     Upon booting, I get this:
>
>                 [...]
>
>                   
>
>                 you could try commit 0df0e14fb, that may or may not work, the
>
> commit
>
>     after
>
>                 that broke fusion boards completely, apparently.
>
>                   
>
>                 Florian
>
>                   
>
>             Thank you! I can confirm that 0df0e14fb works properly.
>
>             -Marshall
>
>         Frank,
>
>           
>
>         It looks like we have a regression. Is there some dependency on the
>
>         other patches that have not yet been committed?
>
>           
>
>         Marc
>
>     Unfortunately git bisect is no help here because the commit which
>
> caused
>
>     the regression was a huge one.
>
>       
>
>     It's important that large patches are broken down into a set of small
>
>     comprehensible patches, each with an explanatory commit message.
>
>       
>
>     <<quote from git-bisect-lk2009.html documentation>>
>
>     ...
>
>     sometimes "interesting" changes of behavior in the software are
>
>     introduced in some commits.
>
>       
>
>     In fact people are specially interested in commits that introduce a
>
>     "bad" behavior, called a bug or a regression. They are interested in
>
>     these commits because a commit (hopefully) contains a very small set
>
>     of source code changes. And it's much easier to understand and
>
>     properly fix a problem when you only need to check a very small set of
>
>     changes, than when you don't know where look in the first place.
>
>       
>
>     So to help people find commits that introduce a "bad" behavior, the
>
>     "git bisect" set of commands was invented.
>
> Hello, All
>   
> Since commit 84cbce2 cause E350M1 not POST,
> Following patches should resolve this regression problem, please see the
> attachment in detail.
> I have test it on a Persimmon mainboard,
> anybody can have a test on E350M1?
> Thanks
> --
> Kerry sheh
>   
>
>
>
>
>
>
> Hello Kerry:
>
> I have tested your patch set, and it does make the E350M1 boot.
> The bad news is there is now a delay of approximately 5 minutes and 20 
> seconds before any serial output is displayed.
>
> The coreboot log is available at 
> http://www.lucidmachines.com/coreboot/kerrypatches20110907.txt
>
> Please let me know if I can assist further.
>
> Thanks a lot,
>
> I have a test based on commit 8679e52 with both F14 C0 and B0 
> processor on different persimmon mainboard,
>
> But unfortunately I can't reproduce the problem you have met.
>
> Family14 Revision C0 processor(BSP Family_Model:00500f20)
>
> Family14 Revision B0 processor(BSP Family_Model: 00500f10) is same as 
> the one you use.
>
> There is not much difference between E350M1 and persimmon code,
>
> so I'm not sure whether the root cause is commit 84cbce2 or other 
> commit, such as sb800 update etc.
>
> Can you have a test base on commit 84cbce2 ?
>
> Many Thanks
>
> Kerry Sheh
>
>
>
> Thank you!
> -Marshall Buschman
>
>
>
Hello Kerry:
I'll test with your patches and 84cbce2 and report back.

Thank you!
-Marshall
-------------- next part --------------
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From svens at stackframe.org  Thu Sep  8 21:45:27 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Thu, 08 Sep 2011 21:45:27 +0200
Subject: [coreboot] TPM support for SeaBIOS -- looking for a tester on
	real hardware
In-Reply-To: <4E68B5A7.7010508@linux.vnet.ibm.com> (Stefan Berger's message of
	"Thu\, 08 Sep 2011 08\:31\:35 -0400")
References: <4E677FEA.1060503@linux.vnet.ibm.com>
	<87zkif8r8p.fsf@begreifnix.stackframe.org>
	<4E68B5A7.7010508@linux.vnet.ibm.com>
Message-ID: <87vct295t4.fsf@begreifnix.stackframe.org>

Hi Stefan,

Stefan Berger <stefanb at linux.vnet.ibm.com> writes:

> On 09/08/2011 02:47 AM, Sven Schnelle wrote:
>> Stefan Berger<stefanb at linux.vnet.ibm.com>  writes:
>>
>>>    Would anybody be interested in testing the TPM support I added to
>>> SeaBIOS. I unfortunately don't have a motherboard myself where I could
>>> try it. I have added the support to SeaBIOS for the TPM device model
>>> in Qemu.  What you would need for trying it is a motherboard with a
>>> TPM 1.2 on it. The SeaBIOS TPM support should recognize it, initialize
>>> the TPM and allow the user to enter another SeaBIOS menu.
>> I have coreboot + seabios running on Thinkpad X60s and T60p. IIRC both
>> models have TPM onboard. I could give it a try, but i don't know if i
>> have to add any code to coreboot for HW initialization. Actually i have
>> no clue how TPM works, never played with it so far... :)
>>
> Could you pick up the patches from the SeaBIOS mailing list and try them?
> The latest patches were posted in this thread:
>
> http://www.seabios.org/pipermail/seabios/2011-August/002252.html

I've applied your TPM/TCG patches to seabios. I've seen that
CONFIG_TCGBIOS depends on !COREBOOT. Is there a specific reason for
this?

tis_probe() failed to read the Device/Vendor ID from the MMIO space. 
Linux detects the TPM device and can read the register:

[    0.549893] tpm_tis 00:0a: 1.2 TPM (device-id 0x3202, rev-id 5)

After i added the following, seabios was able to read the DID_VID register:

diff --git a/src/tpm_drivers.c b/src/tpm_drivers.c
index e03c9bd..7103d54 100644
--- a/src/tpm_drivers.c
+++ b/src/tpm_drivers.c
@@ -28,6 +28,8 @@ static u32 tpm_default_durations[3] = {
 static u32 tis_probe(void)
 {
     u32 rc = 0;
+
+    writeb(TIS_REG(0, TIS_REG_ACCESS), TIS_ACCESS_REQUEST_USE);
     u32 didvid = readl(TIS_REG(0, TIS_REG_DID_VID));

     if ((didvid != 0) && (didvid != 0xffffffff))

After that i was able to read the IDs. However, this made my Thinkpad
take about 15s until seabios showed the SeaBIOS version line on the
screen. SeaBIOS also didn't show the F11 message.

I haven't tried to debug that further - fear that this will have to wait
for the weekend. Just want to send you the results from the first
(short) test.

Sven



From marcj303 at gmail.com  Thu Sep  8 23:22:44 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 8 Sep 2011 15:22:44 -0600
Subject: [coreboot] TPM support for SeaBIOS -- looking for a tester on
 real hardware
In-Reply-To: <4E677FEA.1060503@linux.vnet.ibm.com>
References: <4E677FEA.1060503@linux.vnet.ibm.com>
Message-ID: <CALrs_3hyZ6VC2GWwmrOVccS+GsT7x5jjv3H6xk5=puvnQjZ4iw@mail.gmail.com>

On Wed, Sep 7, 2011 at 8:30 AM, Stefan Berger
<stefanb at linux.vnet.ibm.com> wrote:
> Hello!
>
> ?Would anybody be interested in testing the TPM support I added to SeaBIOS.
> I unfortunately don't have a motherboard myself where I could try it. I have
> added the support to SeaBIOS for the TPM device model in Qemu. ?What you
> would need for trying it is a motherboard with a TPM 1.2 on it. The SeaBIOS
> TPM support should recognize it, initialize the TPM and allow the user to
> enter another SeaBIOS menu.
>
> Regards,
> ? Stefan


Hi Stefan,

This is excelent stuff. i am at the Linux Plumbers Conf this week, but
I really want to try your TPM on hardware soon.I need to identify a
some hardwar e to test with and I'll keep you posted on my results.

Marc




-- 
http://se-eng.com



From gerrit at coreboot.org  Fri Sep  9 09:49:13 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 9 Sep 2011 09:49:13 +0200
Subject: [coreboot] Patch set updated for filo: 1a7a12a Add nvram command
References: <Ib95ee0d4fa8dcaf002ffe2b18d4975e301d00a6a+0@gerrit.coreboot.org>
Message-ID: <Ib95ee0d4fa8dcaf002ffe2b18d4975e301d00a6a+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/196

-gerrit

commit 1a7a12a4cf5908948cec51134a14eda0c4fde28a
Author: Stefan Reinauer <stefan.reinauer at coresystems.de>
Date:   Fri Jun 4 09:25:50 2010 +0200

    Add nvram command
    
    Change-Id: Ib95ee0d4fa8dcaf002ffe2b18d4975e301d00a6a
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 main/grub/builtins.c |   67 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 67 insertions(+), 0 deletions(-)

diff --git a/main/grub/builtins.c b/main/grub/builtins.c
index b09076a..6b10202 100644
--- a/main/grub/builtins.c
+++ b/main/grub/builtins.c
@@ -1093,6 +1093,70 @@ static struct builtin builtin_md5crypt = {
 };
 #endif				/* CONFIG_USE_MD5_PASSWORDS */
 
+#if CONFIG_DEVELOPER_TOOLS
+/* nvram */
+static int nvram_func(char *arg, int flags)
+{
+#define RTC_BOOT_BYTE 48 // Hard coded in coreboot
+	u8 rtc_boot_byte;
+	// bit len  name
+	//  0   1   boot_option
+	//  1   1   last_boot
+	//  4   4   reboot_bits
+
+	rtc_boot_byte = nvram_read(RTC_BOOT_BYTE);
+
+	if (memcmp(arg, "normal", 6) == 0) {
+		rtc_boot_byte &= 0x03;	// drop reboot_bits
+		rtc_boot_byte |= 1;	// normal
+		nvram_write(rtc_boot_byte, RTC_BOOT_BYTE);
+		return 0;
+	}
+
+	if (memcmp(arg, "fallback", 8) == 0) {
+		rtc_boot_byte &= 0x03;	// drop reboot_bits
+		rtc_boot_byte &= ~1;	// fallback
+		nvram_write(rtc_boot_byte, RTC_BOOT_BYTE);
+		return 0;
+	}
+
+	// TODO not really default, but rather "null everything out and fix the
+	// checksum"
+	if (memcmp(arg, "default", 7) == 0) {
+		int i;
+		int range_start = lib_sysinfo.cmos_range_start / 8;
+		int range_end = lib_sysinfo.cmos_range_end / 8;
+		for (i= range_start; i<range_end; i++)
+			nvram_write(0, i);
+		fix_options_checksum();
+		return 0;
+	}
+
+
+	if (!strlen(arg)) {
+		grub_printf("NVRAM Settings:\n");
+		grub_printf("  boot option: %s\n",
+			(rtc_boot_byte & (1 << 0)) ? "Normal" : "Fallback");
+		grub_printf("  last boot:   %s\n",
+			(rtc_boot_byte & (1 << 1)) ? "Normal" : "Fallback");
+		grub_printf("  reboot_bits: %d\n", (rtc_boot_byte >> 4));
+		return 0;
+	}
+
+	errnum = ERR_BAD_ARGUMENT;
+	return 1;
+}
+
+static struct builtin builtin_nvram = {
+	"nvram",
+	nvram_func,
+	BUILTIN_MENU | BUILTIN_CMDLINE | BUILTIN_NO_ECHO,
+	"nvram [normal|fallback]",
+	"Change the coreboot nvram to boot the normal or fallback"
+	    "image on the next boot."
+};
+#endif
+
 /* password */
 static int password_func(char *arg, int flags)
 {
@@ -1781,6 +1845,9 @@ struct builtin *builtin_table[] = {
 #ifdef CONFIG_USE_MD5_PASSWORDS
 	&builtin_md5crypt,
 #endif
+#ifdef CONFIG_DEVELOPER_TOOLS
+	&builtin_nvram,
+#endif
 	&builtin_password,
 	&builtin_pause,
 	&builtin_poweroff,



From gerrit at coreboot.org  Fri Sep  9 09:50:53 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 9 Sep 2011 09:50:53 +0200
Subject: [coreboot] Patch merged into filo/master: 1a7a12a Add nvram command
References: <Ib95ee0d4fa8dcaf002ffe2b18d4975e301d00a6a+0@gerrit.coreboot.org>
Message-ID: <E1R1vrR-0000Im-Az@ra.coresystems.de>

the following patch was just integrated into master:
commit 1a7a12a4cf5908948cec51134a14eda0c4fde28a
Author: Stefan Reinauer <stefan.reinauer at coresystems.de>
Date:   Fri Jun 4 09:25:50 2010 +0200

    Add nvram command
    
    Change-Id: Ib95ee0d4fa8dcaf002ffe2b18d4975e301d00a6a
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/196 for details.

-gerrit



From gerrit at coreboot.org  Fri Sep  9 09:52:25 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 9 Sep 2011 09:52:25 +0200
Subject: [coreboot] Patch set updated for filo: 9518da0 Make 'configfile'
	and 'root' commands be available from scripting mode.
References: <I042506e236b0fb7f10e20ea3f0f3764414167dce+0@gerrit.coreboot.org>
Message-ID: <I042506e236b0fb7f10e20ea3f0f3764414167dce+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/194

-gerrit

commit 9518da06954afafe1c6929096e4e3f2311bd13d9
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 11:46:29 2010 +0100

    Make 'configfile' and 'root' commands be available from scripting mode.
    
    When a 'configfile' command is encountered, restart with that new config
    file.
    
    Change-Id: I042506e236b0fb7f10e20ea3f0f3764414167dce
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 main/grub/builtins.c |    9 +++++++--
 main/grub/grub.c     |   16 +++++++++++++++-
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/main/grub/builtins.c b/main/grub/builtins.c
index 6b10202..c926b7d 100644
--- a/main/grub/builtins.c
+++ b/main/grub/builtins.c
@@ -49,6 +49,9 @@ unsigned long install_partition = 0x20000;
 unsigned long boot_drive = 0;
 char config_file[128] = "\0";
 
+/* indicator if we encountered a 'configfile' command and have to restart */
+int reload_configfile = 0;
+
 kernel_t kernel_type;
 
 /* The fallback entry.  */
@@ -91,6 +94,7 @@ void init_config(void)
 	fallback_entryno = -1;
 	fallback_entries[0] = -1;
 	grub_timeout = -1;
+	reload_configfile = 0;
 }
 
 int check_password(char *entered, char *expected, password_t type)
@@ -318,6 +322,7 @@ static int configfile_func(char *arg, int flags)
 	/* Force to load the configuration file.  */
 	is_opened = 0;
 	keep_cmdline_running = 0;
+	reload_configfile = 1;
 
 	/* Make sure that the user will not be authoritative.  */
 	auth = 0;
@@ -328,7 +333,7 @@ static int configfile_func(char *arg, int flags)
 static struct builtin builtin_configfile = {
 	"configfile",
 	configfile_func,
-	BUILTIN_CMDLINE | BUILTIN_HELP_LIST,
+	BUILTIN_CMDLINE | BUILTIN_MENU | BUILTIN_HELP_LIST,
 	"configfile FILE",
 	"Load FILE as the configuration file."
 };
@@ -1333,7 +1338,7 @@ static int root_func(char *arg, int flags)
 static struct builtin builtin_root = {
 	"root",
 	root_func,
-	BUILTIN_CMDLINE | BUILTIN_HELP_LIST,
+	BUILTIN_CMDLINE | BUILTIN_MENU | BUILTIN_HELP_LIST,
 	"root [DEVICE]",
 	"Set the current \"root device\" to the device DEVICE."
 };
diff --git a/main/grub/grub.c b/main/grub/grub.c
index 15f0ece..7881a98 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -28,6 +28,7 @@
 #include <arch/timer.h>
 
 extern char config_file[];
+extern int reload_configfile;
 
 char PASSWORD_BUF[PASSWORD_BUFLEN]; /* The buffer for the password.  */
 char DEFAULT_FILE_BUF[DEFAULT_FILE_BUFLEN]; /* THe buffer for the filename of "/boot/grub/default".  */
@@ -813,6 +814,11 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 			break;
 	}
 
+	/* return to reload the config file */
+	if (reload_configfile) {
+		return;
+	}
+
 	show_menu = 1;
 	goto restart;
 }
@@ -1004,9 +1010,12 @@ void grub_main(void)
 	/* Never return.  */
 	for (;;) {
 		char buf[10];	/* This is good enough.  */
-		char *default_file = (char *) DEFAULT_FILE_BUF;
+		char *default_file;
 		int i;
 
+restart:
+		default_file = (char *) DEFAULT_FILE_BUF;
+
 		reset();
 
 		/* Here load the configuration file.  */
@@ -1124,6 +1133,11 @@ void grub_main(void)
 								    cmdline);
 						(builtin->func) (arg, BUILTIN_MENU);
 						errnum = 0;
+
+						/* if the command was configfile, restart */
+						if (reload_configfile) {
+							goto restart;
+						}
 					} else
 						/* Ignored.  */
 						continue;



From gerrit at coreboot.org  Fri Sep  9 09:54:33 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 9 Sep 2011 09:54:33 +0200
Subject: [coreboot] Patch merged into filo/master: 9518da0 Make 'configfile'
	and 'root' commands be available from scripting mode.
References: <I042506e236b0fb7f10e20ea3f0f3764414167dce+0@gerrit.coreboot.org>
Message-ID: <E1R1vuz-000280-60@ra.coresystems.de>

the following patch was just integrated into master:
commit 9518da06954afafe1c6929096e4e3f2311bd13d9
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 11:46:29 2010 +0100

    Make 'configfile' and 'root' commands be available from scripting mode.
    
    When a 'configfile' command is encountered, restart with that new config
    file.
    
    Change-Id: I042506e236b0fb7f10e20ea3f0f3764414167dce
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/194 for details.

-gerrit



From gerrit at coreboot.org  Fri Sep  9 10:01:19 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 9 Sep 2011 10:01:19 +0200
Subject: [coreboot] Patch set updated for filo: 3fa954b Add non-interactive
	mode for FILO
References: <I8c13d64832b6f8659927ec1e5fe3b527ef8cbdc4+0@gerrit.coreboot.org>
Message-ID: <I8c13d64832b6f8659927ec1e5fe3b527ef8cbdc4+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/195

-gerrit

commit 3fa954bd32a3b990ce7a6dda83890cd481422273
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 13:14:24 2010 +0100

    Add non-interactive mode for FILO
    
    It forbids modifications of the configuration loaded and prevents
    entering the command line mode.
    
    Change-Id: I8c13d64832b6f8659927ec1e5fe3b527ef8cbdc4
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 Config.in           |    7 +++++++
 main/filo.c         |   17 +++++++++++++++++
 main/grub/cmdline.c |    4 ++++
 main/grub/grub.c    |   40 +++++++++++++++++++++++++++++++++++++++-
 4 files changed, 67 insertions(+), 1 deletions(-)

diff --git a/Config.in b/Config.in
index a8cbfbb..251bd2a 100644
--- a/Config.in
+++ b/Config.in
@@ -24,6 +24,13 @@ config USE_GRUB
 	help
 	  Use GRUB legacy like interface instead of autoboot?
 
+config NON_INTERACTIVE
+	bool "non-interactive interface"
+	default n
+	help
+	  Build a non-interactive interface to disallow modifications of
+	  the boot options, e.g. the kernel to load or the command line.
+
 config PROMPT
 	string "Command line prompt"
 	default "filo"
diff --git a/main/filo.c b/main/filo.c
index a8bf372..e37559b 100644
--- a/main/filo.c
+++ b/main/filo.c
@@ -156,6 +156,10 @@ int main(void)
 
 #ifdef CONFIG_AUTOBOOT_FILE
 #ifdef CONFIG_AUTOBOOT_DELAY
+#ifdef CONFIG_NON_INTERACTIVE
+#error "autoboot delay is not supported for non-interactive builds"
+#define autoboot_delay() 0 /* success */
+#else
 static inline int autoboot_delay(void)
 {
     u64 timeout;
@@ -189,13 +193,16 @@ static inline int autoboot_delay(void)
 	    return 0; /* default accepted */
     }
 }
+#endif /* CONFIG_NON_INTERACTIVE */
 #endif /* CONFIG_AUTOBOOT_DELAY */
 
 static void autoboot(void)
 {
+#ifndef CONFIG_NON_INTERACTIVE
     /* If Escape key is pressed already, skip autoboot */
     if (havechar() && getchar()==ESCAPE)
 	return;
+#endif /* CONFIG_NON_INTERACTIVE */
 
     if (autoboot_delay()==0) {
 	printf("boot: %s\n", CONFIG_AUTOBOOT_FILE);
@@ -215,6 +222,7 @@ int main(void)
     /* Try default image */
     autoboot();
 
+#ifndef CONFIG_NON_INTERACTIVE
     /* The above didn't work, ask user */
     while (havechar())
 	getchar();
@@ -233,6 +241,15 @@ int main(void)
 	if (line[0])
 	    boot(line);
     }
+#else /* ! CONFIG_NON_INTERACTIVE */
+    for (;;) {
+	printf("\nAutoboot failed! Press any key to reboot.\n");
+	getchar();
+	if (reset_handler) {
+	    reset_handler();
+	}
+    }
+#endif /* CONFIG_NON_INTERACTIVE */
 
     return 0;
 }
diff --git a/main/grub/cmdline.c b/main/grub/cmdline.c
index 1f56ac6..2ace871 100644
--- a/main/grub/cmdline.c
+++ b/main/grub/cmdline.c
@@ -40,6 +40,7 @@ char *skip_to(int after_equal, char *cmdline)
 	return cmdline;
 }
 
+#ifndef CONFIG_NON_INTERACTIVE
 /* Print a helpful message for the command-line interface.  */
 void print_cmdline_message(int type)
 {
@@ -67,6 +68,7 @@ void print_cmdline_message(int type)
 	grub_printf("\n");
 #endif
 }
+#endif /* CONFIG_NON_INTERACTIVE */
 
 /* Find the builtin whose command name is COMMAND and return the
  * pointer. If not found, return 0.
@@ -118,6 +120,7 @@ static void init_cmdline(void)
 	init_builtins();
 }
 
+#ifndef CONFIG_NON_INTERACTIVE
 /* Enter the command-line interface. HEAP is used for the command-line
  * buffer. Return only if FOREVER is nonzero and get_cmdline returns
  * nonzero (ESC is pushed).
@@ -179,6 +182,7 @@ void enter_cmdline(char *heap, int forever)
 		count_lines = -1;
 	}
 }
+#endif /* CONFIG_NON_INTERACTIVE */
 
 /* Run an entry from the script SCRIPT. HEAP is used for the
    command-line buffer. If an error occurs, return non-zero, otherwise
diff --git a/main/grub/grub.c b/main/grub/grub.c
index 7881a98..b1fcdd1 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -191,6 +191,16 @@ old:
 
 }
 
+static void reboot(void) {
+	for (;;) {
+		grub_printf("Press any key to reboot.\n");
+		getchar();
+		if (reset_handler) {
+			reset_handler();
+		}
+	}
+}
+
 /* Define if there is user specified preset menu string */
 /* #undef PRESET_MENU_STRING */
 
@@ -409,16 +419,27 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
       password to unlock the next set of features.");
 		} else {
 			if (config_entries)
+#ifndef CONFIG_NON_INTERACTIVE
 				grub_printf("\
       Press enter to boot the selected OS, \'e\' to edit the\n\
       commands before booting, \'a\' to modify the kernel arguments\n\
       before booting, or \'c\' for a command-line.");
+#else /* ! CONFIG_NON_INTERACTIVE */
+				grub_printf("\
+      Press enter to boot the selected OS, \'e\' to see the\n\
+      commands before booting.");
+#endif /* CONFIG_NON_INTERACTIVE */
 			else
+#ifndef CONFIG_NON_INTERACTIVE
 				grub_printf("\
       Press \'b\' to boot, \'e\' to edit the selected command in the\n\
       boot sequence, \'c\' for a command-line, \'o\' to open a new line\n\
       after (\'O\' for before) the selected line, \'d\' to remove the\n\
       selected line, or escape to go back to the main menu.");
+#else /* ! CONFIG_NON_INTERACTIVE */
+				grub_printf("\
+      Press \'b\' to boot or escape to go back to the main menu.");
+#endif /* CONFIG_NON_INTERACTIVE */
 		}
 
 		print_entries(3, 12, first_entry, entryno, menu_entries);
@@ -520,6 +541,7 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 				if ((c == '\n') || (c == '\r') || (c == 6))
 					break;
 			} else {
+#ifndef CONFIG_NON_INTERACTIVE
 				if ((c == 'd') || (c == 'o') || (c == 'O')) {
 					print_entry(4 + entryno, 0,
 						    get_entry(menu_entries, first_entry + entryno, 0));
@@ -565,6 +587,7 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 
 					print_entries(3, 12, first_entry, entryno, menu_entries);
 				}
+#endif /* CONFIG_NON_INTERACTIVE */
 
 				cur_entry = menu_entries;
 				if (c == 27)
@@ -645,6 +668,7 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 
 					if (config_entries)
 						run_menu(heap, NULL, new_num_entries, new_heap, 0);
+#ifndef CONFIG_NON_INTERACTIVE
 					else {
 						/* flush color map */
 						grub_printf(" ");
@@ -677,9 +701,11 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 							heap += (j - i);
 						}
 					}
+#endif /* CONFIG_NON_INTERACTIVE */
 
 					goto restart;
 				}
+#ifndef CONFIG_NON_INTERACTIVE
 				if (c == 'c') {
 					extern int keep_cmdline_running;
 					enter_cmdline(heap, 0);
@@ -778,6 +804,7 @@ static void run_menu(char *menu_entries, char *config_entries, int num_entries,
 
 					break;
 				}
+#endif /* CONFIG_NON_INTERACTIVE */
 			}
 		}
 	}
@@ -1077,7 +1104,11 @@ restart:
 			}
 
 			if (!is_opened) {
-				grub_printf("Could not open menu.lst file '%s'. Entering command line.\n", config_file);
+#ifndef CONFIG_NON_INTERACTIVE
+				grub_printf("Could not open configuration file '%s'. Entering command line.\n", config_file);
+#else /* ! CONFIG_NON_INTERACTIVE */
+				grub_printf("Could not open configuration file '%s'.\n", config_file);
+#endif /* CONFIG_NON_INTERACTIVE */
 				// memset(myheap, 0, 256);
 				// run_script("terminal console\n\0", myheap);
 				break;
@@ -1205,10 +1236,17 @@ restart:
 		} while (is_preset);
 
 		if (!num_entries) {
+#ifndef CONFIG_NON_INTERACTIVE
 			/* If no acceptable config file, goto command-line, starting
 			   heap from where the config entries would have been stored
 			   if there were any.  */
 			enter_cmdline(config_entries, 1);
+#else /* ! CONFIG_NON_INTERACTIVE */
+			for (;;) {
+			    grub_printf("\nNo menu entries found. Giving up.\n");
+			    reboot();
+			}
+#endif /* CONFIG_NON_INTERACTIVE */
 		} else {
 			/* Run menu interface.  */
 			run_menu(menu_entries, config_entries, num_entries, menu_entries + menu_len, default_entry);



From gerrit at coreboot.org  Fri Sep  9 10:02:48 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 9 Sep 2011 10:02:48 +0200
Subject: [coreboot] Patch merged into filo/master: 3fa954b Add
	non-interactive mode for FILO
References: <I8c13d64832b6f8659927ec1e5fe3b527ef8cbdc4+0@gerrit.coreboot.org>
Message-ID: <E1R1w2y-0004ZN-Eu@ra.coresystems.de>

the following patch was just integrated into master:
commit 3fa954bd32a3b990ce7a6dda83890cd481422273
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 13:14:24 2010 +0100

    Add non-interactive mode for FILO
    
    It forbids modifications of the configuration loaded and prevents
    entering the command line mode.
    
    Change-Id: I8c13d64832b6f8659927ec1e5fe3b527ef8cbdc4
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/195 for details.

-gerrit



From gerrit at coreboot.org  Fri Sep  9 10:06:22 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 9 Sep 2011 10:06:22 +0200
Subject: [coreboot] Patch set updated for filo: 876ac94 Allow switching
	between partitions on the current device
References: <I271f5f407297c072f35ac8410c278b1c9442d654+0@gerrit.coreboot.org>
Message-ID: <I271f5f407297c072f35ac8410c278b1c9442d654+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/198

-gerrit

commit 876ac941e9209166c83667a7eaffe7eab98e33d2
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Mar 24 09:13:54 2011 +0100

    Allow switching between partitions on the current device
    
    root (,1) or configfile 2:/filo.lst work now and change the
    active partition on the current device (as defined by "root").
    
    Change-Id: I271f5f407297c072f35ac8410c278b1c9442d654
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 include/grub/shared.h |    2 +-
 main/grub/builtins.c  |  184 +++++++++++++++++++++++++++----------------------
 main/grub/grub.c      |    5 +-
 3 files changed, 104 insertions(+), 87 deletions(-)

diff --git a/include/grub/shared.h b/include/grub/shared.h
index 127b74f..9e74d7c 100644
--- a/include/grub/shared.h
+++ b/include/grub/shared.h
@@ -304,6 +304,6 @@ int print_completions (int is_filename, int is_completion);
 int check_password(char *entered, char* expected, password_t type);
 
 /* FILO specific stuff */
-void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev);
+void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev, int append);
 
 #endif /* ! GRUB_SHARED_HEADER */
diff --git a/main/grub/builtins.c b/main/grub/builtins.c
index c926b7d..e2f4612 100644
--- a/main/grub/builtins.c
+++ b/main/grub/builtins.c
@@ -303,8 +303,7 @@ static int configfile_func(char *arg, int flags)
 	extern int is_opened, keep_cmdline_running;
 
 	/* Check if the file ARG is present.  */
-	temp_space[0]=0;
-	copy_path_to_filo_bootline(arg, temp_space, 1);
+	copy_path_to_filo_bootline(arg, temp_space, 1, 0);
 	if (temp_space[0]==0) {
 		return help_func("configfile",0);
 	}
@@ -316,8 +315,7 @@ static int configfile_func(char *arg, int flags)
 	file_close();
 
 	/* Copy ARG to CONFIG_FILE.  */
-	memset(config_file, 0, 128);
-	copy_path_to_filo_bootline(arg, config_file, 1);
+	copy_path_to_filo_bootline(arg, config_file, 1, 0);
 
 	/* Force to load the configuration file.  */
 	is_opened = 0;
@@ -632,114 +630,140 @@ static struct builtin builtin_hiddenmenu = {
 };
 
 /**
+ * @param arg         linux style driver specifier
+ * @param drivername  driver name (out)
+ * @param disk        disk number (out)
+ * @return length of parsed string
+ */
+static
+int parse_linux_style_driver(char *arg, char *drivername, int *disk)
+{
+	int i = 0;
+
+	*disk = -1;
+	drivername[0] = '\0';
+	while ((i < 16) && (isalpha(arg[i]))) {
+		drivername[i] = arg[i];
+		i++;
+	}
+
+	if (i > 0) {
+		drivername[--i] = '\0';
+		*disk = arg[i]-'a';
+		i++;
+	}
+	return i;
+}
+
+/**
  * @param arg  source pointer with grub device names
  * @param path destination pointer (will be filled with filo device names)
  * @param use_rootdev values other than zero mean the root device set by the "root"
  * command is taken into regard here. This has to be zero when calling from root_func.
  */
 
-void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev)
+void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev, int append)
 {
 	char devicename[16];
 	char drivername[16];
 	int disk, part;
+	unsigned long addr;
 	int i, len;
 
-
-	/* Clean up */
 	memset(devicename, 0, 16);
 	memset(drivername, 0, 16);
+	disk = -1;
+	part = -1;
+	addr = -1;
 
-	/* Copy over the driver name: "hd", "ud", "sd" ... */
 	if (arg[0] == '(') {
+		// grub style device specifier
 		i = 1;
 		/* Read until we encounter a number, a comma or a closing
 		 * bracket
 		 */
-		while ((i <= 16) && (arg[i]) && (!isdigit(arg[i])) && (arg[i] != ',')
-		       && (arg[i] != ')')) {
+		while ((i <= 16) && (isalpha(arg[i]))) {
 			drivername[i - 1] = arg[i];
 			i++;
 		}
-	}
 
-	disk = -1;
-	part = -1;
-
-	len = strlen(drivername);
-	if (len) {		/* We have a driver. No idea if it exists though */
-		// The driver should decide this:
-		len++;		// skip driver name + opening bracket
-
-		// XXX put @ handling in here, too for flash at addr and mem at addr
-
-		if (isdigit(arg[len])) {
-			disk = arg[len] - '0';
-			len++;
-			if (isdigit(arg[len])) {	/* More than 9 drives? */
-				/* ok, get one more number. No more than 99 drives */
-				disk *= 10;
-				disk += arg[len] - '0';
-				len++;
-			}
+		if (isdigit(arg[i])) {
+			char *postnum;
+			disk = strtoul(arg+i, &postnum, 10);
+			i = postnum - arg;
 		}
-		if (arg[len] == ',') {
-			len++;
-			part = arg[len] - '0';
-			len++;
-			if (isdigit(arg[len])) {	/* More than 9 partitions? */
-				/* ok, get one more number. No more than 99
-				 * partitions */
-				part *= 10;
-				part += arg[len] - '0';
-				len++;
-			}
+
+		if (arg[i] == ',') {
+			char *postnum;
+			part = strtoul(arg+i+1, &postnum, 10) + 1;
+			i = postnum - arg;
 		}
-		if (arg[len] != ')') {
-			grub_printf("Drive Error.\n");
-			// set len = 0 --> just copy the drive name 
-			len = 0;
-		} else {
-			len++;	// skip closing bracket
+
+		if (arg[i] == '@') {
+			char *postnum;
+			addr = strtoul(arg+i+1, &postnum, 0);
+			i = postnum - arg;
 		}
-	}
 
-	if (disk == -1) {
-		int cnt = 0;
-		len = 0;
-		while ((arg[cnt] != 0) && (arg[cnt+1] != 0)) {
-			if (arg[cnt] == ':' && arg[cnt+1] == '/') {
-				/* The user did specify a FILO name already */
-				len = cnt;
-				break;
-			}
-			cnt++;
+		if (arg[i] == ')') i++;
+
+		arg += i;
+	} else if ((use_rootdev == 0) || (strchr(arg, ':') != NULL)) {
+		// linux-style device specifier or
+		// leading device name required (assume it's linux-style then)
+		i = parse_linux_style_driver(arg, drivername, &disk);
+
+		if (isdigit(arg[i])) {
+			char *postnum;
+			part = strtoul(arg+i, &postnum, 10);
+			i = postnum - arg;
 		}
-	} else {
-		if (part == -1) {	// No partition
-			sprintf(devicename, "%s%c:", drivername, disk + 'a');
-		} else {	// both disk and partition
-			sprintf(devicename, "%s%c%d:", drivername, disk + 'a', part + 1);
+
+		if (arg[i] == '@') {
+			char *postnum;
+			addr = strtoul(arg+i+1, &postnum, 0);
+			i = postnum - arg;
 		}
-		strncat(path, devicename, BOOT_LINE_LENGTH);
-		arg += len;	// skip original drive name
+
+		if (arg[i] == ':') i++;
+		arg += i;
 	}
 
-	if (use_rootdev && !len) {	// No drive was explicitly specified
-		if (strlen(root_device)) {	// But someone set a root device
-			strncat(path, root_device, BOOT_LINE_LENGTH);
-		}
+	if ((disk == -1) && (part != -1) && (strlen(drivername) == 0)) {
+		// special case for partition-only identifiers:
+		// take driver and disk number from root_device
+		i = parse_linux_style_driver(root_device, drivername, &disk);
 	}
 
-	/* Copy the rest over */
-	strncat(path, arg, BOOT_LINE_LENGTH);
+	if (!append) path[0] = 0;
+	if ((use_rootdev == 1) && (strlen(drivername) == 0)) {
+		strlcat(path, root_device, BOOT_LINE_LENGTH);
+	} else {
+		char buffer[32];
+		strlcat(path, drivername, BOOT_LINE_LENGTH);
+		if (disk != -1) {
+			snprintf(buffer, 31, "%c", 'a'+disk);
+			strlcat(path, buffer, BOOT_LINE_LENGTH);
+		}
+		if (part != -1) {
+			snprintf(buffer, 31, "%d", part);
+			strlcat(path, buffer, BOOT_LINE_LENGTH);
+		}
+		if (addr != -1) {
+			snprintf(buffer, 31, "@0x%x", addr);
+			strlcat(path, buffer, BOOT_LINE_LENGTH);
+		}
+		buffer[0]=':';
+		buffer[1]='\0';
+		strlcat(path, buffer, BOOT_LINE_LENGTH);
+	}
+	strlcat(path, arg, BOOT_LINE_LENGTH);
 }
 
 /* initrd */
 static int initrd_func(char *arg, int flags)
 {
-	initrd_space[0]=0; // Erase string
-	copy_path_to_filo_bootline(arg, initrd_space, 1);
+	copy_path_to_filo_bootline(arg, initrd_space, 1, 0);
 	if (!file_open(initrd_space)) {
 		initrd_space[0]=0; // Erase string
 		errnum = ERR_FILE_NOT_FOUND;
@@ -877,12 +901,8 @@ static int kernel_func(char *arg, int flags)
 
 	kernel_type = KERNEL_TYPE_NONE;
 
-	/* clear out boot_line. Kernel is the first thing */
-	boot_line[0] = 0;  // Erase string
-
 	/* Get the real boot line and extract the kernel name */
-	temp_space[0] = 0; // Erase string
-	copy_path_to_filo_bootline(arg, temp_space, 1);
+	copy_path_to_filo_bootline(arg, temp_space, 1, 0);
 	i=0; while ((temp_space[i] != 0) && (temp_space[i]!=' ')) i++;
 	temp_space[i] = 0;
 
@@ -897,7 +917,7 @@ static int kernel_func(char *arg, int flags)
 	/* Needed to pass grub checks */
 	kernel_type = KERNEL_TYPE_LINUX;
 
-	copy_path_to_filo_bootline(arg, boot_line, 1);
+	copy_path_to_filo_bootline(arg, boot_line, 1, 0);
 
 	return 0;
 }
@@ -1319,8 +1339,7 @@ static int root_func(char *arg, int flags)
 {
 	int len;
 
-	root_device[0] = 0; /* Clear root device */
-	copy_path_to_filo_bootline(arg, root_device, 0);
+	copy_path_to_filo_bootline(arg, root_device, 0, 0);
 
 	/* The following code handles an extra case
 	 * where the user specifies "root hde1" without
@@ -1790,8 +1809,7 @@ static int cat_func(char *arg, int flags)
 	char buf[4096];
 	int len;
 
-	temp_space[0]=0;
-	copy_path_to_filo_bootline(arg, temp_space, 1);
+	copy_path_to_filo_bootline(arg, temp_space, 1, 0);
 	if (temp_space[0]==0) {
 		return help_func("cat",0);
 	}
diff --git a/main/grub/grub.c b/main/grub/grub.c
index 7881a98..f4deedf 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -127,7 +127,7 @@ void manual_grub_menulst(void)
 				break;
 
 			if (line[0]) {
-				copy_path_to_filo_bootline(line, config_file, 0);
+				copy_path_to_filo_bootline(line, config_file, 0, 1);
 				break;
 			}
 		}
@@ -143,8 +143,7 @@ int probe_menulst(char *bootdevice, char *filename)
 	strcpy(menulst, bootdevice);
 	strncat(menulst, filename, 256);
 	/* Set string to zero: */
-	config_file[0] = 0;
-	copy_path_to_filo_bootline(menulst, config_file, 0);
+	copy_path_to_filo_bootline(menulst, config_file, 0, 0);
 	if (file_open(config_file)) {
 		/* We found a config file. Bail out */
 		/* The valid config file name stays in config_file[] */



From gerrit at coreboot.org  Fri Sep  9 10:10:46 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 9 Sep 2011 10:10:46 +0200
Subject: [coreboot] Patch set updated for filo: 98010ff Allow switching
	between partitions on the current device
References: <I271f5f407297c072f35ac8410c278b1c9442d654+0@gerrit.coreboot.org>
Message-ID: <I271f5f407297c072f35ac8410c278b1c9442d654+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/198

-gerrit

commit 98010ffea7f8a203cfb26adef3ac3834cc8748d8
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Mar 24 09:13:54 2011 +0100

    Allow switching between partitions on the current device
    
    root (,1) or configfile 2:/filo.lst work now and change the
    active partition on the current device (as defined by "root").
    
    Change-Id: I271f5f407297c072f35ac8410c278b1c9442d654
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 include/grub/shared.h |    2 +-
 main/grub/builtins.c  |  184 +++++++++++++++++++++++++++----------------------
 main/grub/grub.c      |    5 +-
 3 files changed, 104 insertions(+), 87 deletions(-)

diff --git a/include/grub/shared.h b/include/grub/shared.h
index 127b74f..9e74d7c 100644
--- a/include/grub/shared.h
+++ b/include/grub/shared.h
@@ -304,6 +304,6 @@ int print_completions (int is_filename, int is_completion);
 int check_password(char *entered, char* expected, password_t type);
 
 /* FILO specific stuff */
-void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev);
+void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev, int append);
 
 #endif /* ! GRUB_SHARED_HEADER */
diff --git a/main/grub/builtins.c b/main/grub/builtins.c
index c926b7d..e2f4612 100644
--- a/main/grub/builtins.c
+++ b/main/grub/builtins.c
@@ -303,8 +303,7 @@ static int configfile_func(char *arg, int flags)
 	extern int is_opened, keep_cmdline_running;
 
 	/* Check if the file ARG is present.  */
-	temp_space[0]=0;
-	copy_path_to_filo_bootline(arg, temp_space, 1);
+	copy_path_to_filo_bootline(arg, temp_space, 1, 0);
 	if (temp_space[0]==0) {
 		return help_func("configfile",0);
 	}
@@ -316,8 +315,7 @@ static int configfile_func(char *arg, int flags)
 	file_close();
 
 	/* Copy ARG to CONFIG_FILE.  */
-	memset(config_file, 0, 128);
-	copy_path_to_filo_bootline(arg, config_file, 1);
+	copy_path_to_filo_bootline(arg, config_file, 1, 0);
 
 	/* Force to load the configuration file.  */
 	is_opened = 0;
@@ -632,114 +630,140 @@ static struct builtin builtin_hiddenmenu = {
 };
 
 /**
+ * @param arg         linux style driver specifier
+ * @param drivername  driver name (out)
+ * @param disk        disk number (out)
+ * @return length of parsed string
+ */
+static
+int parse_linux_style_driver(char *arg, char *drivername, int *disk)
+{
+	int i = 0;
+
+	*disk = -1;
+	drivername[0] = '\0';
+	while ((i < 16) && (isalpha(arg[i]))) {
+		drivername[i] = arg[i];
+		i++;
+	}
+
+	if (i > 0) {
+		drivername[--i] = '\0';
+		*disk = arg[i]-'a';
+		i++;
+	}
+	return i;
+}
+
+/**
  * @param arg  source pointer with grub device names
  * @param path destination pointer (will be filled with filo device names)
  * @param use_rootdev values other than zero mean the root device set by the "root"
  * command is taken into regard here. This has to be zero when calling from root_func.
  */
 
-void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev)
+void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev, int append)
 {
 	char devicename[16];
 	char drivername[16];
 	int disk, part;
+	unsigned long addr;
 	int i, len;
 
-
-	/* Clean up */
 	memset(devicename, 0, 16);
 	memset(drivername, 0, 16);
+	disk = -1;
+	part = -1;
+	addr = -1;
 
-	/* Copy over the driver name: "hd", "ud", "sd" ... */
 	if (arg[0] == '(') {
+		// grub style device specifier
 		i = 1;
 		/* Read until we encounter a number, a comma or a closing
 		 * bracket
 		 */
-		while ((i <= 16) && (arg[i]) && (!isdigit(arg[i])) && (arg[i] != ',')
-		       && (arg[i] != ')')) {
+		while ((i <= 16) && (isalpha(arg[i]))) {
 			drivername[i - 1] = arg[i];
 			i++;
 		}
-	}
 
-	disk = -1;
-	part = -1;
-
-	len = strlen(drivername);
-	if (len) {		/* We have a driver. No idea if it exists though */
-		// The driver should decide this:
-		len++;		// skip driver name + opening bracket
-
-		// XXX put @ handling in here, too for flash at addr and mem at addr
-
-		if (isdigit(arg[len])) {
-			disk = arg[len] - '0';
-			len++;
-			if (isdigit(arg[len])) {	/* More than 9 drives? */
-				/* ok, get one more number. No more than 99 drives */
-				disk *= 10;
-				disk += arg[len] - '0';
-				len++;
-			}
+		if (isdigit(arg[i])) {
+			char *postnum;
+			disk = strtoul(arg+i, &postnum, 10);
+			i = postnum - arg;
 		}
-		if (arg[len] == ',') {
-			len++;
-			part = arg[len] - '0';
-			len++;
-			if (isdigit(arg[len])) {	/* More than 9 partitions? */
-				/* ok, get one more number. No more than 99
-				 * partitions */
-				part *= 10;
-				part += arg[len] - '0';
-				len++;
-			}
+
+		if (arg[i] == ',') {
+			char *postnum;
+			part = strtoul(arg+i+1, &postnum, 10) + 1;
+			i = postnum - arg;
 		}
-		if (arg[len] != ')') {
-			grub_printf("Drive Error.\n");
-			// set len = 0 --> just copy the drive name 
-			len = 0;
-		} else {
-			len++;	// skip closing bracket
+
+		if (arg[i] == '@') {
+			char *postnum;
+			addr = strtoul(arg+i+1, &postnum, 0);
+			i = postnum - arg;
 		}
-	}
 
-	if (disk == -1) {
-		int cnt = 0;
-		len = 0;
-		while ((arg[cnt] != 0) && (arg[cnt+1] != 0)) {
-			if (arg[cnt] == ':' && arg[cnt+1] == '/') {
-				/* The user did specify a FILO name already */
-				len = cnt;
-				break;
-			}
-			cnt++;
+		if (arg[i] == ')') i++;
+
+		arg += i;
+	} else if ((use_rootdev == 0) || (strchr(arg, ':') != NULL)) {
+		// linux-style device specifier or
+		// leading device name required (assume it's linux-style then)
+		i = parse_linux_style_driver(arg, drivername, &disk);
+
+		if (isdigit(arg[i])) {
+			char *postnum;
+			part = strtoul(arg+i, &postnum, 10);
+			i = postnum - arg;
 		}
-	} else {
-		if (part == -1) {	// No partition
-			sprintf(devicename, "%s%c:", drivername, disk + 'a');
-		} else {	// both disk and partition
-			sprintf(devicename, "%s%c%d:", drivername, disk + 'a', part + 1);
+
+		if (arg[i] == '@') {
+			char *postnum;
+			addr = strtoul(arg+i+1, &postnum, 0);
+			i = postnum - arg;
 		}
-		strncat(path, devicename, BOOT_LINE_LENGTH);
-		arg += len;	// skip original drive name
+
+		if (arg[i] == ':') i++;
+		arg += i;
 	}
 
-	if (use_rootdev && !len) {	// No drive was explicitly specified
-		if (strlen(root_device)) {	// But someone set a root device
-			strncat(path, root_device, BOOT_LINE_LENGTH);
-		}
+	if ((disk == -1) && (part != -1) && (strlen(drivername) == 0)) {
+		// special case for partition-only identifiers:
+		// take driver and disk number from root_device
+		i = parse_linux_style_driver(root_device, drivername, &disk);
 	}
 
-	/* Copy the rest over */
-	strncat(path, arg, BOOT_LINE_LENGTH);
+	if (!append) path[0] = 0;
+	if ((use_rootdev == 1) && (strlen(drivername) == 0)) {
+		strlcat(path, root_device, BOOT_LINE_LENGTH);
+	} else {
+		char buffer[32];
+		strlcat(path, drivername, BOOT_LINE_LENGTH);
+		if (disk != -1) {
+			snprintf(buffer, 31, "%c", 'a'+disk);
+			strlcat(path, buffer, BOOT_LINE_LENGTH);
+		}
+		if (part != -1) {
+			snprintf(buffer, 31, "%d", part);
+			strlcat(path, buffer, BOOT_LINE_LENGTH);
+		}
+		if (addr != -1) {
+			snprintf(buffer, 31, "@0x%x", addr);
+			strlcat(path, buffer, BOOT_LINE_LENGTH);
+		}
+		buffer[0]=':';
+		buffer[1]='\0';
+		strlcat(path, buffer, BOOT_LINE_LENGTH);
+	}
+	strlcat(path, arg, BOOT_LINE_LENGTH);
 }
 
 /* initrd */
 static int initrd_func(char *arg, int flags)
 {
-	initrd_space[0]=0; // Erase string
-	copy_path_to_filo_bootline(arg, initrd_space, 1);
+	copy_path_to_filo_bootline(arg, initrd_space, 1, 0);
 	if (!file_open(initrd_space)) {
 		initrd_space[0]=0; // Erase string
 		errnum = ERR_FILE_NOT_FOUND;
@@ -877,12 +901,8 @@ static int kernel_func(char *arg, int flags)
 
 	kernel_type = KERNEL_TYPE_NONE;
 
-	/* clear out boot_line. Kernel is the first thing */
-	boot_line[0] = 0;  // Erase string
-
 	/* Get the real boot line and extract the kernel name */
-	temp_space[0] = 0; // Erase string
-	copy_path_to_filo_bootline(arg, temp_space, 1);
+	copy_path_to_filo_bootline(arg, temp_space, 1, 0);
 	i=0; while ((temp_space[i] != 0) && (temp_space[i]!=' ')) i++;
 	temp_space[i] = 0;
 
@@ -897,7 +917,7 @@ static int kernel_func(char *arg, int flags)
 	/* Needed to pass grub checks */
 	kernel_type = KERNEL_TYPE_LINUX;
 
-	copy_path_to_filo_bootline(arg, boot_line, 1);
+	copy_path_to_filo_bootline(arg, boot_line, 1, 0);
 
 	return 0;
 }
@@ -1319,8 +1339,7 @@ static int root_func(char *arg, int flags)
 {
 	int len;
 
-	root_device[0] = 0; /* Clear root device */
-	copy_path_to_filo_bootline(arg, root_device, 0);
+	copy_path_to_filo_bootline(arg, root_device, 0, 0);
 
 	/* The following code handles an extra case
 	 * where the user specifies "root hde1" without
@@ -1790,8 +1809,7 @@ static int cat_func(char *arg, int flags)
 	char buf[4096];
 	int len;
 
-	temp_space[0]=0;
-	copy_path_to_filo_bootline(arg, temp_space, 1);
+	copy_path_to_filo_bootline(arg, temp_space, 1, 0);
 	if (temp_space[0]==0) {
 		return help_func("cat",0);
 	}
diff --git a/main/grub/grub.c b/main/grub/grub.c
index b1fcdd1..1afdadd 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -127,7 +127,7 @@ void manual_grub_menulst(void)
 				break;
 
 			if (line[0]) {
-				copy_path_to_filo_bootline(line, config_file, 0);
+				copy_path_to_filo_bootline(line, config_file, 0, 1);
 				break;
 			}
 		}
@@ -143,8 +143,7 @@ int probe_menulst(char *bootdevice, char *filename)
 	strcpy(menulst, bootdevice);
 	strncat(menulst, filename, 256);
 	/* Set string to zero: */
-	config_file[0] = 0;
-	copy_path_to_filo_bootline(menulst, config_file, 0);
+	copy_path_to_filo_bootline(menulst, config_file, 0, 0);
 	if (file_open(config_file)) {
 		/* We found a config file. Bail out */
 		/* The valid config file name stays in config_file[] */



From gerrit at coreboot.org  Fri Sep  9 10:12:27 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 9 Sep 2011 10:12:27 +0200
Subject: [coreboot] Patch merged into filo/master: 98010ff Allow switching
	between partitions on the current device
References: <I271f5f407297c072f35ac8410c278b1c9442d654+0@gerrit.coreboot.org>
Message-ID: <E1R1wCJ-0007i5-Ii@ra.coresystems.de>

the following patch was just integrated into master:
commit 98010ffea7f8a203cfb26adef3ac3834cc8748d8
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Mar 24 09:13:54 2011 +0100

    Allow switching between partitions on the current device
    
    root (,1) or configfile 2:/filo.lst work now and change the
    active partition on the current device (as defined by "root").
    
    Change-Id: I271f5f407297c072f35ac8410c278b1c9442d654
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/198 for details.

-gerrit



From gerrit at coreboot.org  Fri Sep  9 10:37:57 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 9 Sep 2011 10:37:57 +0200
Subject: [coreboot] Patch merged into filo/master: 181d45d Set root device
	while probing boot_devices list
References: <Id1f27a08bd86bc9a872dd52347f19a55532a82e6+0@gerrit.coreboot.org>
Message-ID: <E1R1wb0-0002eG-0I@ra.coresystems.de>

the following patch was just integrated into master:
commit 181d45d266a3e4627c82690a745c0f08018f8cf5
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 8 11:43:32 2010 +0100

    Set root device while probing boot_devices list
    
    This way we don't need to have absolute paths in the config file itself.
    
    Change-Id: Id1f27a08bd86bc9a872dd52347f19a55532a82e6
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/200 for details.

-gerrit



From gerrit at coreboot.org  Fri Sep  9 11:40:05 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 9 Sep 2011 11:40:05 +0200
Subject: [coreboot] Patch merged into coreboot/master: b8fe009 Report GSE
	chipset and warn if the code has been compiled for the wrong
	chipset.
References: <Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0+0@gerrit.coreboot.org>
Message-ID: <E1R1xZ7-0002A2-JF@ra.coresystems.de>

the following patch was just integrated into master:
commit b8fe009787a26f079b236a26ebc0c6e676c0c884
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Fri Apr 1 22:33:25 2011 +0200

    Report GSE chipset and warn if the code has been compiled for the wrong chipset.
    
    It would be nicer to unify the code so that it does all detection at runtime
    instead of compile time (but that would also significantly increase code size)
    so if someone else wants to give it a shot...
    
    Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/184 for details.

-gerrit



From gerrit at coreboot.org  Fri Sep  9 11:40:31 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 9 Sep 2011 11:40:31 +0200
Subject: [coreboot] Patch merged into coreboot/master: ca06106 Crank up CPU
	speed on Intel Core and Core2 CPUs
References: <Ia6225eea97299a473cf50eccc6c5e7de830b1ddc+0@gerrit.coreboot.org>
Message-ID: <E1R1xZX-0002P7-Eu@ra.coresystems.de>

the following patch was just integrated into master:
commit ca06106e0e8de1777aa311c4ea1c1fd45f7eee38
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Aug 9 08:52:14 2011 +0200

    Crank up CPU speed on Intel Core and Core2 CPUs
    
    The CPUs start on their slowest speed, and were left that way by
    coreboot. This change will speed up coreboot a bit, as well as
    systems that don't change the clock for whatever reason.
    
    Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

See http://review.coreboot.org/176 for details.

-gerrit



From gerrit at coreboot.org  Fri Sep  9 11:40:49 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 9 Sep 2011 11:40:49 +0200
Subject: [coreboot] Patch merged into coreboot/master: 66367fa Replace while
	with do; while to avoid repetition
References: <Ie0a4fa622df881edeaab08f59bb888a903b864fd+0@gerrit.coreboot.org>
Message-ID: <E1R1xZp-0002Xc-1p@ra.coresystems.de>

the following patch was just integrated into master:
commit 66367fa77ecc1501bdb2b081370268442e45408d
Author: Noe Rubinstein <nrubinstein at proformatique.com>
Date:   Thu May 5 15:44:40 2011 +0200

    Replace while with do; while to avoid repetition
    
    Cosmetic only; replaces some 'while' loops with 'do; while' loops to
    avoid repetition.
    
    Replacement performed by the Ruby expression:
    t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
    	"\\1do \\2\n\\1\\3;")
    
    Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
    Signed-off-by: Noe Rubinstein <nrubinstein at proformatique.com>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/183 for details.

-gerrit



From ps947 at yahoo.de  Fri Sep  9 15:22:10 2011
From: ps947 at yahoo.de (Peter Schmidt)
Date: Fri, 9 Sep 2011 14:22:10 +0100 (BST)
Subject: [coreboot] barbarians at the gates
Message-ID: <1315574530.62733.YahooMailNeo@web132102.mail.ird.yahoo.com>

Hi,

seems like more and more dongle-functionality is going into UEFI:

http://www.h-online.com/security/news/item/Windows-8-to-include-secure-boot-using-UEFI-2-3-1-1335246.html
http://vr-zone.com/articles/the-upgrade-path-to-ivy-bridge-might-be-blocked-by-changes-to-uefi/13513.html

Since their "Next-Gen" "Trusted Computing" "Deep Shit" was an utter failure, one could expect, that sooner or later they would be at the gates again with this, "functionality".


Besides spreading the word around, that there IS an alternative to UEFI, what else can I as a customer do, to ensure there will always be at least a few mainboards which run fully stable (and maybe even out-of-the-box) with coreboot (+SeaBIOS/GRUB) ?

1. Preferring hardware with such support? Sure.
This filter here? http://gh.de/?cat=mbson&sort=p? allows me to filter for all sorts of stuff, but not, for coreboot support. That is just sad.
Only by accident do I know, that this http://gh.de/610927 IS already supported by coreboot.

I stumbled upon the information in the http://www.coreboot.org/Supported_Motherboards but really only accidentally, because I did not search, because I did not expect that new (= currently purchasable) boards are supported by coreboot! That is why me thinks, spreading the word, is not such a bad idea, and quite necessary. How to do that, without sounding like a zealot? The decision for coreboot, is not so much about today, is also about the products available in 5 or 10 years from now on!


2. Actually buying that hardware. Definitely!
Probably for Christmas I am going to set up a HTPC, I'll use a mainboard with coreboot support.


**But** how do I make it crystal clear to the seller/manufacturer that the coreboot-support is the reason that make me buy this particular product and not all the marketing bla bla?

Any ideas?

I do not want to write some lame e-mail claiming or demanding something. The moment I give him my money in exchange for the product, I really would like him to understand, that is is the coreboot support I am after. All mainboards have PCIe and DRAM banks, but the one I am buying, has coreboot support.




From rminnich at gmail.com  Fri Sep  9 17:43:08 2011
From: rminnich at gmail.com (ron minnich)
Date: Fri, 9 Sep 2011 08:43:08 -0700
Subject: [coreboot] I865 memory controller status
In-Reply-To: <4D9B4575.4000801@settoplinux.org>
References: <BANLkTimrxLMkRCfAhggfxaz0Tyzy8Rokeg@mail.gmail.com>
	<BANLkTi=d+MjSWXFWsxhFU_+VaPyf3=FA7Q@mail.gmail.com>
	<BANLkTi=bEVPkmBNgZ-FLooz+4c-5E_kEMg@mail.gmail.com>
	<BANLkTikcUReKoVCsgcBnknUOrbAWzDtGZA@mail.gmail.com>
	<4D9B4575.4000801@settoplinux.org>
Message-ID: <CAP6exYLKKSmxvewGhcq9iwVJhTwVXWVJGyzJBBWA5buxdQKXog@mail.gmail.com>

On Tue, Apr 5, 2011 at 9:38 AM, Joseph Smith <joe at settoplinux.org> wrote:

> Yeah and Intel is great at only giving you half the picture ;-)

If you have half the picture you're doing unusually well :-)

ron



From sharkx.forever at gmail.com  Sat Sep 10 06:45:05 2011
From: sharkx.forever at gmail.com (sharkx forever)
Date: Sat, 10 Sep 2011 00:45:05 -0400
Subject: [coreboot] coreboot on dell vostro 1400?
Message-ID: <CAK_y_Nr-TaBLHXDsaKsxqGQ2bPyXdKKc1dcxAzxibhi9TMx50Q@mail.gmail.com>

Hi all,  I have a dell vostro 1400 laptop and I would like to install
coreboot on it.  Could somebody let me know if it is possible?


 The laptop has:

Intel(R) Core(TM)2 Duo T7500 @ 2.20GHz cpu.

Intel 965GM Express chipset for integrated graphics.


More detailed specifications can be found at:

http://support.dell.com/support/edocs/systems/Vos1400/en/OM/specs.htm


==============================================================

The output of "lspci -tvnn" is as follows:


[ Note: I will be replacing Intel PRO/Wireless 4965 AGN card with Atheros
ar9280 based mini card. So please consider atheros chipset based wireless
card in place of the intel card. ]


-[0000:00]-+-00.0 Intel Corporation Mobile PM965/GM965/GL960 Memory
Controller Hub [8086:2a00]

+-02.0 Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller
[8086:2a02]

+-02.1 Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller
[8086:2a03]

+-1a.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4
[8086:2834]

+-1a.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5
[8086:2835]

+-1a.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2
[8086:283a]

+-1b.0 Intel Corporation 82801H (ICH8 Family) HD Audio Controller
[8086:284b]

+-1c.0-[0000:0b]--

+-1c.1-[0000:0c]----00.0 Intel Corporation PRO/Wireless 4965 AG or AGN
[Kedron] Network Connection [8086:4229]

+-1c.3-[0000:0d-0e]--

+-1c.5-[0000:09]----00.0 Broadcom Corporation NetLink BCM5906M Fast Ethernet
PCI Express [14e4:1713]

+-1d.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1
[8086:2830]

+-1d.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2
[8086:2831]

+-1d.2 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3
[8086:2832]

+-1d.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1
[8086:2836]

+-1e.0-[0000:03]--+-01.0 Ricoh Co Ltd R5C832 IEEE 1394 Controller
[1180:0832]

| +-01.1 Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter [1180:0822]

| +-01.2 Ricoh Co Ltd R5C843 MMC Host Controller [1180:0843]

| +-01.3 Ricoh Co Ltd R5C592 Memory Stick Bus Host Adapter [1180:0592]

| \-01.4 Ricoh Co Ltd xD-Picture Card Controller [1180:0852]

+-1f.0 Intel Corporation 82801HEM (ICH8M) LPC Interface Controller
[8086:2815]

+-1f.1 Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) IDE Controller
[8086:2850]

+-1f.2 Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) SATA IDE Controller
[8086:2828]

\-1f.3 Intel Corporation 82801H (ICH8 Family) SMBus Controller [8086:283e]

==============================================================

# superiotool

superiotool r3844

No Super I/O found


# flashrom

flashrom v0.9.1-r946

No coreboot table found.

Found chipset "Intel ICH8M", enabling flash write... OK.

This chipset supports the following protocols: FWH,SPI.

Calibrating delay loop... OK.

Found chip "Spansion S25FL008A" (1024 KB, SPI) at physical address
0xfff00000.

Error: No filename specified.


# ectool

EC RAM:

00: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

10: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

20: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

30: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

40: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

50: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

60: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

70: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

80: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

90: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

a0: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

b0: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

c0: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

d0: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

e0: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

f0: 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c 5c

Not dumping EC IDX RAM.

===================================================================


 Thanks.
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From btrotter at gmail.com  Sat Sep 10 08:41:49 2011
From: btrotter at gmail.com (Brendan Trotter)
Date: Sat, 10 Sep 2011 16:11:49 +0930
Subject: [coreboot] barbarians at the gates
In-Reply-To: <1315574530.62733.YahooMailNeo@web132102.mail.ird.yahoo.com>
References: <1315574530.62733.YahooMailNeo@web132102.mail.ird.yahoo.com>
Message-ID: <CAELHeEdZRDvXhiPgmAu3zXXtp_JgqAssQfH4aGxYj-oMBX03zg@mail.gmail.com>

Hi,

On Fri, Sep 9, 2011 at 10:52 PM, Peter Schmidt <ps947 at yahoo.de> wrote:
> seems like more and more dongle-functionality is going into UEFI:
>
> http://www.h-online.com/security/news/item/Windows-8-to-include-secure-boot-using-UEFI-2-3-1-1335246.html
> http://vr-zone.com/articles/the-upgrade-path-to-ivy-bridge-might-be-blocked-by-changes-to-uefi/13513.html
>
> Since their "Next-Gen" "Trusted Computing" "Deep Shit" was an utter failure, one could expect, that sooner or later they would be at the gates again with this, "functionality".
>
>
> Besides spreading the word around, that there IS an alternative to UEFI, what else can I as a customer do, to ensure there will always be at least a few mainboards which run fully stable (and maybe even out-of-the-box) with coreboot (+SeaBIOS/GRUB) ?

>From a consumer's perspective, "fully stable" is expected; and using
"fully stable" as a marketing strategy isn't likely to get more than a
groan. The main things actual consumers care about are things like
faster boot times, maintenance and setup hassle, compatibility with
industry standards (BIOS, EFI, ACPI, SMBIOS, PXE, etc) and security.

If you take a look at these areas; for boot times coreboot does have
an advantage. For maintenance and setup hassle it's a nightmare
(unless you can find motherboards/computers that have coreboot
pre-installed). For compatibility with industry standards it's "hit or
miss" (it's hard to be more "EFI compatible" than EFI, for example).
For security coreboot mostly fails (there's a tendency for coreboot
developers to whine about things like the "bad" uses of TPM rather
than recognizing the demand from improved security and then taking
steps to match or exceed the capabilities of alternatives).

I can almost guarantee that someone will say "open source", and they
will be right - open source is an important advantage for people that
are prepared to read/understand the source code.

Unfortunately most actual consumers can't read or understand the
source code (and most of those that can have better things to do), so
actual consumers don't care. The (mostly theoretical) "many eyes"
benefit of open source is not superior to the (very real) "sue your
asses if you screw it up" benefit of dealing with "for profit"
companies. These are *not* mutually exclusive. For example, it would
increase consumer confidence a lot if people could choose to pay for
some sort of "fitness for a particular purpose" guarantee. Even
something simple like "If you want to, you can send us $5 and if
coreboot doesn't work as advertised we'll give you $50" would send a
clear message to consumers that you believe in the reliability of
coreboot enough to try to make profit from that reliability; even if
no consumer ever takes up the challenge and pays that $5. The reverse
is also true - if you don't try to make profit from coreboot in some
way, then some consumers (fortunately not all - things are getting
better) may assume you're unwilling to accept any risk because you
don't have any faith in coreboot yourselves.

Of course a lot of people won't like parts of what I've said. I can't
blame them - I don't like parts of what I've said either. The fact is
that the world is sad and broken, regardless of whether any of us like
it or not.


> **But** how do I make it crystal clear to the seller/manufacturer that the coreboot-support is the reason that make me buy this particular product and not all the marketing bla bla?
>
> Any ideas?
>
> I do not want to write some lame e-mail claiming or demanding something. The moment I give him my money in exchange for the product, I really would like him to understand, that is is the coreboot support I am after. All mainboards have PCIe and DRAM banks, but the one I am buying, has coreboot support.

A much better idea would be telling the retailer "Screw you, I'm
buying a motherboard with coreboot pre-installed directly from
coreboot.org because none of the products you sell mention coreboot
compatibility and I don't want to end up with something that doesn't
work". Retailers don't care why they made a sale as long as they make
a sale, but they do care about lost sales.


Cheers,

Brendan



From david.hendricks at gmail.com  Sat Sep 10 20:22:35 2011
From: david.hendricks at gmail.com (David Hendricks)
Date: Sat, 10 Sep 2011 11:22:35 -0700
Subject: [coreboot] barbarians at the gates
In-Reply-To: <1315574530.62733.YahooMailNeo@web132102.mail.ird.yahoo.com>
References: <1315574530.62733.YahooMailNeo@web132102.mail.ird.yahoo.com>
Message-ID: <CAJ_ov579CAysjUGSfbaV7agd9-eFt6vnK=op90BfcwEZ3UFC9Q@mail.gmail.com>

Unfortunately, as a consumer there isn't a whole lot that can be done. It's
sort of like trying to buy a PC with Linux instead of Windows -- Due to
volume, the cheapest and most readily-available hardware is ironically
likely to have the Microsoft tax built into the pricetag. Similarly, nearly
all PC motherboards will have the cost of proprietary BIOS royalties
built-in. So replacing proprietary BIOS with Coreboot does not really help
the vendor to realize potential cost savings.

IMHO the best thing is to get involved with the development communities,
especially for stuff like servers and HTPC machines, and hopefully inspire
some new products that are designed with Coreboot in-mind from the very
beginning. The good news is that this has become much easier thanks to AMD
who has upstreamed all the low-level code necessary to make that happen for
modern hardware such as Fusion :-)
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From towardsoss at gmail.com  Sat Sep 10 22:25:30 2011
From: towardsoss at gmail.com (Niklas Cholmkvist)
Date: Sat, 10 Sep 2011 23:25:30 +0300
Subject: [coreboot] barbarians at the gates
Message-ID: <4E6BC7BA.3050909@gmail.com>

Brendan Trotter typed:
> A much better idea would be telling the retailer "Screw you, I'm
> buying a motherboard with coreboot pre-installed directly from
> coreboot.org because none of the products you sell mention coreboot
> compatibility and I don't want to end up with something that doesn't
> work". Retailers don't care why they made a sale as long as they make
> a sale, but they do care about lost sales.
On the main page http://www.coreboot.org/ which redirects to
http://www.coreboot.org/Welcome_to_coreboot there's lots of information
but I see no "get coreboot" anywhere. Maybe coreboot is still in its
infant stages to go so boldly forward yet.
-- 
Niklas Cholmkvist

Public GPG/PGP key block
ID:           1024D/C09E670B
Fingerprint:  8487 ECE3 8ED9 870B BB56  95E7 9AD2 946A C09E 670B
Key download:
https://sites.google.com/site/towardsfloss/main-page/NiklasCholmkvist.asc
[For authenticity and privacy on the internet with prime number based
mathematics]

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From sharkx.forever at gmail.com  Sat Sep 10 23:11:50 2011
From: sharkx.forever at gmail.com (sharkx forever)
Date: Sat, 10 Sep 2011 17:11:50 -0400
Subject: [coreboot] coreboot on dell vostro 1400?
In-Reply-To: <CAK_y_Nr-TaBLHXDsaKsxqGQ2bPyXdKKc1dcxAzxibhi9TMx50Q@mail.gmail.com>
References: <CAK_y_Nr-TaBLHXDsaKsxqGQ2bPyXdKKc1dcxAzxibhi9TMx50Q@mail.gmail.com>
Message-ID: <CAK_y_No+h5Vmzigqp_QWUZtwC0-m7mk8bC_E7V_hkAFz=ngufw@mail.gmail.com>

Further info:

# inteltool

Intel CPU: Family 6, Model f
Intel Northbridge: 8086:2a00 (PM965)
Intel Southbridge: 8086:2815 (ICH8-M)


# dmidecode

# dmidecode 2.9
SMBIOS 2.4 present.
45 structures occupying 1977 bytes.
Table at 0x000F7190.

inetltool recognizes Northbridge as PM965 but lspci says GM965.  I am not
sure which one it is.

I am not sure if is helpful, but the data sheet for Intel 965 Express
Chipset Family can be found at:
http://www.intel.com/design/chipsets/datashts/313053.htm

If you need any more information about my system, please let me know.
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From david.hendricks at gmail.com  Sun Sep 11 09:47:29 2011
From: david.hendricks at gmail.com (David Hendricks)
Date: Sun, 11 Sep 2011 00:47:29 -0700
Subject: [coreboot] barbarians at the gates
In-Reply-To: <4E6BC7BA.3050909@gmail.com>
References: <4E6BC7BA.3050909@gmail.com>
Message-ID: <CAJ_ov57JTczim9GsCv0iWf4oGx1PjW1MQA87YZNyQSt2eDAd2Q@mail.gmail.com>

On Sat, Sep 10, 2011 at 1:25 PM, Niklas Cholmkvist <towardsoss at gmail.com>wrote:

> On the main page http://www.coreboot.org/ which redirects to
> http://www.coreboot.org/Welcome_to_coreboot there's lots of information
> but I see no "get coreboot" anywhere. Maybe coreboot is still in its
> infant stages to go so boldly forward yet.


Actually, Coreboot has had sources on-line to boot real hardware for over a
decade :-)

Check the "Downloads" link from the main website:
http://www.coreboot.org/Download_coreboot
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From stefanb at linux.vnet.ibm.com  Sun Sep 11 18:45:59 2011
From: stefanb at linux.vnet.ibm.com (Stefan Berger)
Date: Sun, 11 Sep 2011 12:45:59 -0400
Subject: [coreboot] TPM support for SeaBIOS -- looking for a tester on
 real hardware
In-Reply-To: <CALrs_3hyZ6VC2GWwmrOVccS+GsT7x5jjv3H6xk5=puvnQjZ4iw@mail.gmail.com>
References: <4E677FEA.1060503@linux.vnet.ibm.com>
	<CALrs_3hyZ6VC2GWwmrOVccS+GsT7x5jjv3H6xk5=puvnQjZ4iw@mail.gmail.com>
Message-ID: <4E6CE5C7.8000806@linux.vnet.ibm.com>

On 09/08/2011 05:22 PM, Marc Jones wrote:
> On Wed, Sep 7, 2011 at 8:30 AM, Stefan Berger
> <stefanb at linux.vnet.ibm.com>  wrote:
>> Hello!
>>
>>   Would anybody be interested in testing the TPM support I added to SeaBIOS.
>> I unfortunately don't have a motherboard myself where I could try it. I have
>> added the support to SeaBIOS for the TPM device model in Qemu.  What you
>> would need for trying it is a motherboard with a TPM 1.2 on it. The SeaBIOS
>> TPM support should recognize it, initialize the TPM and allow the user to
>> enter another SeaBIOS menu.
>>
>> Regards,
>>    Stefan
>
> Hi Stefan,
>
> This is excelent stuff. i am at the Linux Plumbers Conf this week, but
> I really want to try your TPM on hardware soon.I need to identify a
> some hardwar e to test with and I'll keep you posted on my results.
This is really good to hear. :-)

Let me know how it goes.

   Stefan
> Marc
>
>
>
>




From stefanb at linux.vnet.ibm.com  Sun Sep 11 19:38:43 2011
From: stefanb at linux.vnet.ibm.com (Stefan Berger)
Date: Sun, 11 Sep 2011 13:38:43 -0400
Subject: [coreboot] TPM support for SeaBIOS -- looking for a tester on
 real hardware
In-Reply-To: <87vct295t4.fsf@begreifnix.stackframe.org>
References: <4E677FEA.1060503@linux.vnet.ibm.com>
	<87zkif8r8p.fsf@begreifnix.stackframe.org>
	<4E68B5A7.7010508@linux.vnet.ibm.com>
	<87vct295t4.fsf@begreifnix.stackframe.org>
Message-ID: <4E6CF223.9060907@linux.vnet.ibm.com>

On 09/08/2011 03:45 PM, Sven Schnelle wrote:
> Hi Stefan,
>
> Stefan Berger<stefanb at linux.vnet.ibm.com>  writes:
>
>> On 09/08/2011 02:47 AM, Sven Schnelle wrote:
>>> Stefan Berger<stefanb at linux.vnet.ibm.com>   writes:
>>>
>>>>     Would anybody be interested in testing the TPM support I added to
>>>> SeaBIOS. I unfortunately don't have a motherboard myself where I could
>>>> try it. I have added the support to SeaBIOS for the TPM device model
>>>> in Qemu.  What you would need for trying it is a motherboard with a
>>>> TPM 1.2 on it. The SeaBIOS TPM support should recognize it, initialize
>>>> the TPM and allow the user to enter another SeaBIOS menu.
>>> I have coreboot + seabios running on Thinkpad X60s and T60p. IIRC both
>>> models have TPM onboard. I could give it a try, but i don't know if i
>>> have to add any code to coreboot for HW initialization. Actually i have
>>> no clue how TPM works, never played with it so far... :)
>>>
>> Could you pick up the patches from the SeaBIOS mailing list and try them?
>> The latest patches were posted in this thread:
>>
>> http://www.seabios.org/pipermail/seabios/2011-August/002252.html
> I've applied your TPM/TCG patches to seabios. I've seen that
> CONFIG_TCGBIOS depends on !COREBOOT. Is there a specific reason for
> this?
>
I believe the reason for this is that SeaBIOS's ACPI table support is 
not compiled in if compiled for COREBOOT. At least some part of the TPM 
support does depend on the ACPI tables, i.e., for all the logging.

> tis_probe() failed to read the Device/Vendor ID from the MMIO space.
> Linux detects the TPM device and can read the register:
>
> [    0.549893] tpm_tis 00:0a: 1.2 TPM (device-id 0x3202, rev-id 5)
>
> After i added the following, seabios was able to read the DID_VID register:
>
> diff --git a/src/tpm_drivers.c b/src/tpm_drivers.c
> index e03c9bd..7103d54 100644
> --- a/src/tpm_drivers.c
> +++ b/src/tpm_drivers.c
> @@ -28,6 +28,8 @@ static u32 tpm_default_durations[3] = {
>   static u32 tis_probe(void)
>   {
>       u32 rc = 0;
> +
> +    writeb(TIS_REG(0, TIS_REG_ACCESS), TIS_ACCESS_REQUEST_USE);
I suppose reading 'didvid' returned 0xFFFFFFFF before? I am surprised 
that these most basic registers are 'hidden' if the locality is not in 
use. This for sure isn't the case for registers of other localities 
where one can read at least the state if another locality is currently 
active.
>       u32 didvid = readl(TIS_REG(0, TIS_REG_DID_VID));
>
>       if ((didvid != 0)&&  (didvid != 0xffffffff))
>
> After that i was able to read the IDs. However, this made my Thinkpad
> take about 15s until seabios showed the SeaBIOS version line on the
> screen. SeaBIOS also didn't show the F11 message.
>
> I haven't tried to debug that further - fear that this will have to wait
> for the weekend. Just want to send you the results from the first
> (short) test.
Let me know how this went.
Maybe  enabling the debugging messages shows something useful. Try 
setting the DEBUG_tcg to 0 in src/config.h.

    Stefan
> Sven
>




From tihokibertron at gmail.com  Mon Sep 12 00:53:33 2011
From: tihokibertron at gmail.com (tiho taskov)
Date: Mon, 12 Sep 2011 01:53:33 +0300
Subject: [coreboot] ARM SoC ID
Message-ID: <CABy0V07=rjhmsUe-AkKJhiXnefu07w+CmrQcMbh0cjneZjNbWA@mail.gmail.com>

I want to know what stance the coreboot community is taking on the
issue with identifying basic initialization parameters for a
pre-compiled linux kernel booting on a random SoC.



From patrick at georgi-clan.de  Mon Sep 12 11:47:49 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 12 Sep 2011 11:47:49 +0200
Subject: [coreboot] barbarians at the gates
In-Reply-To: <1315574530.62733.YahooMailNeo@web132102.mail.ird.yahoo.com>
References: <1315574530.62733.YahooMailNeo@web132102.mail.ird.yahoo.com>
Message-ID: <4E6DD545.9030904@georgi-clan.de>

Am 09.09.2011 15:22, schrieb Peter Schmidt:
> seems like more and more dongle-functionality is going into UEFI:
>
> http://www.h-online.com/security/news/item/Windows-8-to-include-secure-boot-using-UEFI-2-3-1-1335246.html
> http://vr-zone.com/articles/the-upgrade-path-to-ivy-bridge-might-be-blocked-by-changes-to-uefi/13513.html
How is this relevant to coreboot?


Patrick



From ps947 at yahoo.de  Mon Sep 12 13:06:07 2011
From: ps947 at yahoo.de (Peter Schmidt)
Date: Mon, 12 Sep 2011 12:06:07 +0100 (BST)
Subject: [coreboot] barbarians at the gates
In-Reply-To: <4E6DD545.9030904@georgi-clan.de>
References: <1315574530.62733.YahooMailNeo@web132102.mail.ird.yahoo.com>
	<4E6DD545.9030904@georgi-clan.de>
Message-ID: <1315825567.11637.YahooMailNeo@web132109.mail.ird.yahoo.com>

>> seems like more and more dongle-functionality is going into UEFI:
>>
>> http://www.h-online.com/security/news/item/Windows-8-to-include-secure-boot-using-UEFI-2-3-1-1335246.html
>> http://vr-zone.com/articles/the-upgrade-path-to-ivy-bridge-might-be-blocked-by-changes-to-uefi/13513.html
>How is this relevant to coreboot?

Coreboot is the alternative to UEFI.
If UEFI is such a threat to customer freedom and also, if problems are expected, that these are two reasons to have a second look at coreboot.

I am not interested in running a cracked Windows or whatever, I just do not want this functionality on my hardware.
Also, I do not wish to pay for its developement!

With Linux there are already problems with UEFI, because the mainboard/UEFI manufacturers do not adhere to the standards. (No link this time, please search yourself.)
I do not like that as well.

And since I am the customer, please, let me decide what I pay for.

Peter




From gerrit at coreboot.org  Mon Sep 12 14:55:25 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 12 Sep 2011 14:55:25 +0200
Subject: [coreboot] Patch merged into coreboot/master: c2b6a77 Miscellaneous
	AMD F14 warning fixes
References: <I6b204fe0af16a97d982f46f0dfeaccc4b8eb883e+0@gerrit.coreboot.org>
Message-ID: <E1R362n-00079Z-U8@ra.coresystems.de>

the following patch was just integrated into master:
commit c2b6a778ca9c1b3a3cdee18b8d60c35891123d9e
Author: efdesign98 <efdesign98 at gmail.com>
Date:   Thu Aug 4 16:18:16 2011 -0600

    Miscellaneous AMD F14 warning fixes
    
    This commit adds in some more fixes to AMD F14 compile
    warnings.  The change in the mtrr.c file is in prep-
    aration for changes yet to com, but it is currently
    innocuous.
    
    Change-Id: I6b204fe0af16a97d982f46f0dfeaccc4b8eb883e
    Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
    Signed-off-by: efdesign98 <efdesign98 at gmail.com>

See http://review.coreboot.org/133 for details.

-gerrit



From tihokibertron at gmail.com  Mon Sep 12 15:13:04 2011
From: tihokibertron at gmail.com (tiho taskov)
Date: Mon, 12 Sep 2011 16:13:04 +0300
Subject: [coreboot] Patrick, ARM SoC
Message-ID: <CABy0V04Z0fxGY=uStkVbazFns=LcghgGdYrrj8bv1aUzSxdECg@mail.gmail.com>

Well, I heard that a possible solution would be including a standard
formatted device ID string in silico. Would coreboot be useful for
implementing this by passing it as a boot parameter?



From gerrit at coreboot.org  Mon Sep 12 15:56:13 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 12 Sep 2011 15:56:13 +0200
Subject: [coreboot] Patch merged into coreboot/master: 0e277fb Add
	acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods
References: <I13feff0b8f49aa988e5467cdbef02981f0a6be8a+0@gerrit.coreboot.org>
Message-ID: <E1R36zd-0006au-R3@ra.coresystems.de>

the following patch was just integrated into master:
commit 0e277fb131ed9eee75c1b1c6641b2ac7c2635165
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Mon Dec 13 22:39:46 2010 +0100

    Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods
    
    Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
    Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
    uses the same acpi wakeup vector as S3.
    Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
    the power LED while sleeping.
    acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
    it is used in both romstage and ramstage after patch 3/3, whereas
    i82371eb_early_pm.c is used only in romstage.
    I used the name acpi_get_sleep_type instead of  acpi_is_wakeup_early
    because I think acpi_is_wakeup_early is a bit misleading as a name since it
    doesn't return a boolean value.
    
    Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
    added check for acpi_slp_type == 2 (resume from S2) should not
    change behaviour of other boards:
    northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
    northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
    northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
    northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
    southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
    southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
    southbridge/via/vt8237r/vt8237r_lpc.c:238:  acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
    southbridge/via/vt8237r/vt8237r_lpc.c:239:  printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
    
    Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/188 for details.

-gerrit



From gerrit at coreboot.org  Mon Sep 12 15:58:12 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Mon, 12 Sep 2011 15:58:12 +0200
Subject: [coreboot] Patch set updated for coreboot: 936fb7f inteltool: added
	more device IDs
References: <I6f2272ae4071025e671638e83bade6a96aac658b+0@gerrit.coreboot.org>
Message-ID: <I6f2272ae4071025e671638e83bade6a96aac658b+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/185

-gerrit

commit 936fb7f5689917bbed45a9e21eda6685b27d0f9a
Author: Ruud Schramp <schramp at holmes.nl>
Date:   Mon Apr 4 07:53:19 2011 +0200

    inteltool: added more device IDs
    
    Change-Id: I6f2272ae4071025e671638e83bade6a96aac658b
    Signed-off-by: Ruud Schramp <schramp at holmes.nl>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/inteltool/inteltool.c |    2 ++
 util/inteltool/inteltool.h |    2 ++
 util/inteltool/memory.c    |    2 ++
 util/inteltool/pcie.c      |    6 ++++++
 4 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index a416106..93169d3 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -80,6 +80,8 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
 };
 
 #ifndef __DARWIN__
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index ca8066f..bddd17c 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -78,6 +78,8 @@
 #define PCI_DEVICE_ID_INTEL_82Q35		0x29b0
 #define PCI_DEVICE_ID_INTEL_82G33		0x29c0
 #define PCI_DEVICE_ID_INTEL_82Q33		0x29d0
+#define PCI_DEVICE_ID_INTEL_X44 		0x29e0
+#define PCI_DEVICE_ID_INTEL_32X0		0x29f0
 #define PCI_DEVICE_ID_INTEL_GS45		0x2a40
 #define PCI_DEVICE_ID_INTEL_X58			0x3405
 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO		0x8100
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 256204c..9230419 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -109,6 +109,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 		printf("This northbridge does not have MCHBAR.\n");
 		return 1;
 	case PCI_DEVICE_ID_INTEL_GS45:
+	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_32X0:
 		mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
  		break;
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 1ca57b6..4913150 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -45,6 +45,8 @@ int print_epbar(struct pci_dev *nb)
  	case PCI_DEVICE_ID_INTEL_82Q35:
  	case PCI_DEVICE_ID_INTEL_82G33:
  	case PCI_DEVICE_ID_INTEL_82Q33:
+	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_32X0:
 	case PCI_DEVICE_ID_INTEL_GS45:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
@@ -104,6 +106,8 @@ int print_dmibar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_82Q35:
 	case PCI_DEVICE_ID_INTEL_82G33:
 	case PCI_DEVICE_ID_INTEL_82Q33:
+	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_32X0:
 	case PCI_DEVICE_ID_INTEL_GS45:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
@@ -167,6 +171,8 @@ int print_pciexbar(struct pci_dev *nb)
  	case PCI_DEVICE_ID_INTEL_82Q35:
  	case PCI_DEVICE_ID_INTEL_82G33:
  	case PCI_DEVICE_ID_INTEL_82Q33:
+	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_32X0:
 	case PCI_DEVICE_ID_INTEL_GS45:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:



From svn at coreboot.org  Mon Sep 12 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 12 Sep 2011 16:00:02 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1R373K-0002WZ-Pr@ra.coresystems.de>

An HTML attachment was scrubbed...
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From gerrit at coreboot.org  Mon Sep 12 16:41:21 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 12 Sep 2011 16:41:21 +0200
Subject: [coreboot] Patch merged into coreboot/master: 936fb7f inteltool:
	added more device IDs
References: <I6f2272ae4071025e671638e83bade6a96aac658b+0@gerrit.coreboot.org>
Message-ID: <E1R37hJ-0002HF-Ts@ra.coresystems.de>

the following patch was just integrated into master:
commit 936fb7f5689917bbed45a9e21eda6685b27d0f9a
Author: Ruud Schramp <schramp at holmes.nl>
Date:   Mon Apr 4 07:53:19 2011 +0200

    inteltool: added more device IDs
    
    Change-Id: I6f2272ae4071025e671638e83bade6a96aac658b
    Signed-off-by: Ruud Schramp <schramp at holmes.nl>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

See http://review.coreboot.org/185 for details.

-gerrit



From dspjm1 at gmail.com  Mon Sep 12 17:48:07 2011
From: dspjm1 at gmail.com (Jianmin Pan)
Date: Mon, 12 Sep 2011 23:48:07 +0800
Subject: [coreboot] I am reading the source code of coreboot,
	how do I understand the functions
Message-ID: <CAAgJb5tu4U7x+AQMQC+VQtjBt_jEwbfis2RCP02RHjcWeVkZHQ@mail.gmail.com>

I am a newbie to coreboot, I am wondering is there an easy approach to
understand the functions.
For instance, when I am reading fallback_boot.c, it's very difficult for me
to understand such functions as inb(), outb(),RTC_PORT().
The method I am using now is to grep the function name and find out which
file it is in. Then read it. However, I still feel inconvenient.
I am used to use vim.
So, anybody have good suggestions?
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From patrick at georgi-clan.de  Mon Sep 12 21:07:38 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 12 Sep 2011 21:07:38 +0200
Subject: [coreboot] barbarians at the gates
In-Reply-To: <1315825567.11637.YahooMailNeo@web132109.mail.ird.yahoo.com>
References: <1315574530.62733.YahooMailNeo@web132102.mail.ird.yahoo.com>
	<4E6DD545.9030904@georgi-clan.de>
	<1315825567.11637.YahooMailNeo@web132109.mail.ird.yahoo.com>
Message-ID: <4E6E587A.3020508@georgi-clan.de>

Am Mo 12 Sep 2011 13:06:07 CEST schrieb Peter Schmidt:
> Coreboot is the alternative to UEFI.
It's complementary. UEFI (or what the consumer understands by it) 
barely covers hardware initialization, while coreboot doesn't really 
concern itself with firmware APIs.

> With Linux there are already problems with UEFI, because the mainboard/UEFI manufacturers do not adhere to the standards. (No link this time, please search yourself.)
That's just the continuation of their inability of reading specs that 
they proudly presented to the world with BIOS interfaces. Their main 
advantage back then was a lack of a single, unified, formal spec. (But 
mjg's rants are amusing to read, yes)

> And since I am the customer, please, let me decide what I pay for.
That plea is best directed towards mainboard vendors.

In the end, I still wonder why such things are discussed on this list. 
Preaching to the choir and all that (and creating weird public 
perception of what coreboot developer think about technology, as can be 
seen elsewhere in this thread).

How about you bring this up with: mainboard vendors, Intel (as UEFI 
fanboy #1), Tianocore (providing the user interfacing half of UEFI)? 
They are more likely to have any influence on the matter.


Patrick



From patrick at georgi-clan.de  Mon Sep 12 21:17:40 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 12 Sep 2011 21:17:40 +0200
Subject: [coreboot] I am reading the source code of coreboot,
 how do I understand the functions
In-Reply-To: <CAAgJb5tu4U7x+AQMQC+VQtjBt_jEwbfis2RCP02RHjcWeVkZHQ@mail.gmail.com>
References: <CAAgJb5tu4U7x+AQMQC+VQtjBt_jEwbfis2RCP02RHjcWeVkZHQ@mail.gmail.com>
Message-ID: <4E6E5AD4.60604@georgi-clan.de>

Am Mo 12 Sep 2011 17:48:07 CEST schrieb Jianmin Pan:
> I am used to use vim.
> So, anybody have good suggestions?
Install ctags, run "ctags -R src" in the toplevel directory, which 
creates the "tags" file.

Then in vi, use ":ta identifier" to look up the declaration of 
identifier, ctrl-] to look up the current word
(see http://ctags.sourceforge.net/ctags.html#HOW%20TO%20USE%20WITH%20VI)


Patrick



From dhendrix at google.com  Mon Sep 12 21:51:31 2011
From: dhendrix at google.com (David Hendricks)
Date: Mon, 12 Sep 2011 12:51:31 -0700
Subject: [coreboot] ARM SoC ID
In-Reply-To: <CABy0V07=rjhmsUe-AkKJhiXnefu07w+CmrQcMbh0cjneZjNbWA@mail.gmail.com>
References: <CABy0V07=rjhmsUe-AkKJhiXnefu07w+CmrQcMbh0cjneZjNbWA@mail.gmail.com>
Message-ID: <CAKOoyUd-pAVpJN_rPZu0fcb7CnB97QLK9Ma4g+YU_GbuQg+baw@mail.gmail.com>

On Sun, Sep 11, 2011 at 3:53 PM, tiho taskov <tihokibertron at gmail.com>wrote:

> I want to know what stance the coreboot community is taking on the
> issue with identifying basic initialization parameters for a
> pre-compiled linux kernel booting on a random SoC.
>

>From Coreboot's perspective, this sort of thing should be handled in the
payload / bootloader (SeaBIOS, GRUB/GRUB2, etc).

FWIW, there have also been discussions about using U-Boot as a payload for
Coreboot:
http://blogs.coreboot.org/blog/2011/04/30/u-boot-as-coreboot-payload/ .  One
advantage of the U-Boot approach is that U-Boot supports the Flattened
Device Tree (FDT) which is useful for passing init parameters, device
topology, etc. to Linux. AFAIK, this is the standard approach for PowerPC,
is gaining popularity for ARM, and can also be applied to x86. Here are some
additional resources if this interests you:
2011 Linux Plumbers Conference talk:
http://linuxplumbersconf.org/ocw/proposals/47
2010 Embedded Linux Conference talk:
http://elinux.org/images/b/b6/ARM_Device_Tree_Status_Report.pdf

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From tsylla at gmail.com  Mon Sep 12 22:15:31 2011
From: tsylla at gmail.com (Tom Sylla)
Date: Mon, 12 Sep 2011 13:15:31 -0700
Subject: [coreboot] I am reading the source code of coreboot,
 how do I understand the functions
In-Reply-To: <CAAgJb5tu4U7x+AQMQC+VQtjBt_jEwbfis2RCP02RHjcWeVkZHQ@mail.gmail.com>
References: <CAAgJb5tu4U7x+AQMQC+VQtjBt_jEwbfis2RCP02RHjcWeVkZHQ@mail.gmail.com>
Message-ID: <CAAxijve0CTJns5bDb-EGTY9dUjXZuw5eSPNwJ1wVHOdG76bE1g@mail.gmail.com>

If you want to browse around a bit, there is an LXR cross reference of
coreboot available here:
http://lxr.linux.no/coreboot

Tom

On Mon, Sep 12, 2011 at 8:48 AM, Jianmin Pan <dspjm1 at gmail.com> wrote:
> I am a newbie to coreboot, I am wondering is there an easy approach to
> understand the functions.
> For instance, when I am reading fallback_boot.c, it's very difficult for me
> to understand such functions as inb(), outb(),RTC_PORT().
> The method I am using now is to grep the function name and find out which
> file it is in. Then read it. However, I still feel inconvenient.
> I am used to use vim.
> So, anybody have good suggestions?
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From Kerry.She at amd.com  Tue Sep 13 04:39:13 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Tue, 13 Sep 2011 10:39:13 +0800
Subject: [coreboot] I am reading the source code of coreboot,
	how do I understand the functions
In-Reply-To: <4E6E5AD4.60604@georgi-clan.de>
References: <CAAgJb5tu4U7x+AQMQC+VQtjBt_jEwbfis2RCP02RHjcWeVkZHQ@mail.gmail.com>
	<4E6E5AD4.60604@georgi-clan.de>
Message-ID: <F53A09371FB723428826B442A4B20A410764261E@sbjgexmb1.amd.com>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Patrick Georgi
> Sent: Tuesday, September 13, 2011 3:18 AM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] I am reading the source code of coreboot, how
do
> I understand the functions
> 
> Am Mo 12 Sep 2011 17:48:07 CEST schrieb Jianmin Pan:
> > I am used to use vim.
> > So, anybody have good suggestions?
> Install ctags, run "ctags -R src" in the toplevel directory, which
> creates the "tags" file.
> 
> Then in vi, use ":ta identifier" to look up the declaration of
> identifier, ctrl-] to look up the current word
> (see
http://ctags.sourceforge.net/ctags.html#HOW%20TO%20USE%20WITH%20VI)

Cscope is another choice also,
cscope provice more search types than ctags
http://cscope.sourceforge.net/
http://cscope.sourceforge.net/cscope_vim_tutorial.html
cscope -Rbk to build the database first,
add following section to the ~/.vimrc, then can use the hotkey.
 
if has("cscope")
    " use both cscope and ctag for 'ctrl-]', ':ta', and 'vim -t'
    set cscopetag

    " check cscope for definition of a symbol before checking ctags: set
to 1
    " if you want the reverse search order.
    set csto=0
    
    " add any cscope database in current directory
    if filereadable("cscope.out")
    	""if $CSCOPE_DB != ""
           cs add cscope.out .
        ""endif
    " else add the database pointed to by environment variable
    elseif $CSCOPE_DB != ""
        cs add $CSCOPE_DB
    endif

    " show msg when any other cscope db added
    set cscopeverbose

    " To do the first type of search, hit 'CTRL-\', followed by one of
the
    " cscope search types above (s,g,c,t,e,f,i,d).  The result of your
cscope
    " search will be displayed in the current window.  You can use
CTRL-T to
    " go back to where you were before the search.
    nmap <C-\>s :cs find s <C-R>=expand("<cword>")<CR><CR>
    nmap <C-\>g :cs find g <C-R>=expand("<cword>")<CR><CR>
    nmap <C-\>c :cs find c <C-R>=expand("<cword>")<CR><CR>
    nmap <C-\>t :cs find t <C-R>=expand("<cword>")<CR><CR>
    nmap <C-\>e :cs find e <C-R>=expand("<cword>")<CR><CR>
    nmap <C-\>f :cs find f <C-R>=expand("<cfile>")<CR><CR>
    nmap <C-\>i :cs find i ^<C-R>=expand("<cfile>")<CR>$<CR>
    nmap <C-\>d :cs find d <C-R>=expand("<cword>")<CR><CR>
endif

thanks
Kerry
> 
> Patrick
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot





From gerrit at coreboot.org  Tue Sep 13 07:37:51 2011
From: gerrit at coreboot.org (QingPei Wang (wangqingpei@gmail.com))
Date: Tue, 13 Sep 2011 07:37:51 +0200
Subject: [coreboot] Patch set updated for coreboot: 5d309cb Add IT8721F
	support
References: <Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f+0@gerrit.coreboot.org>
Message-ID: <Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f+2@gerrit.coreboot.org>

QingPei Wang (wangqingpei at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/204

-gerrit

commit 5d309cb75821600495e77769b225b89476de8493
Author: QingPei Wang <wangqingpei at gmail.com>
Date:   Tue Sep 13 13:35:43 2011 +0800

    Add IT8721F support
    
    only the serial port is tested, keyboard/mouse are gonna
    to be tested later, it may also need some more patches
    to make it work completely.
    
    Change-Id: Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f
    Signed-off-by: QingPei Wang <wangqingpei at gmail.com>
---
 src/superio/ite/Kconfig                |    2 +
 src/superio/ite/Makefile.inc           |    1 +
 src/superio/ite/it8721f/Makefile.inc   |   22 ++++++++
 src/superio/ite/it8721f/chip.h         |   34 ++++++++++++
 src/superio/ite/it8721f/early_serial.c |   93 ++++++++++++++++++++++++++++++++
 src/superio/ite/it8721f/it8721f.h      |   41 ++++++++++++++
 src/superio/ite/it8721f/superio.c      |   78 ++++++++++++++++++++++++++
 7 files changed, 271 insertions(+), 0 deletions(-)

diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig
index cb0c571..d045bf4 100644
--- a/src/superio/ite/Kconfig
+++ b/src/superio/ite/Kconfig
@@ -36,3 +36,5 @@ config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
 	default n
 config SUPERIO_ITE_IT8718F
 	bool
+config SUPERIO_ITE_IT8721F
+	bool
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index 21f7707..1e734fe 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -24,3 +24,4 @@ subdirs-y += it8705f
 subdirs-y += it8712f
 subdirs-y += it8716f
 subdirs-y += it8718f
+subdirs-y += it8721f
diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc
new file mode 100644
index 0000000..3908237
--- /dev/null
+++ b/src/superio/ite/it8721f/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_