[coreboot] E350M1 does not POST

[Scott Duplichan]

Marshall Buschman wrote:

...

]Hello Kerry:
]
]I have tested your patch set, and it does make the E350M1 boot.
]The bad news is there is now a delay of approximately 5 minutes and 20
]seconds before any serial output is displayed.
]
]The coreboot log is available at
]http://www.lucidmachines.com/coreboot/kerrypatches20110907.txt
]
]Please let me know if I can assist further.
]
]Thank you!
]-Marshall Buschman

The problem of early serial output causing a large boot delay is not new. It
is caused by serial port logging before the SB800 LPC clock is configured,
and/or serial port logging before the SIO baud rate is setup. The original
LPC clock fix was in romstage.c, then later moved to sb800 bootblock.c,
function enable_clocks(). Marshall's log file is missing the following early
serial output, which suggests a problem with the needed early SB800 LPC
clock programming, or SIO baud rate programming:

    POST: 0x30
    SB800 - Cfg.c - sb800_cimx_config - Start.
    SB800 - Cfg.c - sb800_cimx_config - End.
    POST: 0x31

I am not in a position to try this on real hardware, but I did do a quick
simnow test. It looks like function enable_clocks() is correctly executing
before the first serial output. But the above lines of early serial output
are logged before the SIO baud rate is programmed. Here is some discussion
of this problem:

http://patchwork.coreboot.org/patch/3178/

That old patch should overcome the problem for the above post code logging.
But the new SB800 logging in sb800_cimx_config() probably needs removing
also.

Thanks,
Scott