[coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
patrick at georgi-clan.de
Sun Sep 25 09:06:51 CEST 2011
Am Freitag, 23. September 2011 01:45:09 schrieb Oskar Enoksson:
> As for the "dead" behaviour in recent versions I bisected my way down
> to commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That
> commit adds "TINY_BOOTBLOCK support" to AMD-8111 southbridge. I
> understand that this commit splits up things into a "romstage" and
> "coreboot_ram". But what is going wrong, and what should I do? All
> hints appreciated.
Try a smaller image size (and write it into flash top-aligned). If
things work then, the bootblock doesn't correctly set up ROM mapping
Check src/northbridge/amd/amdfam10/bootblock.c and adapt that for your
northbridge (amdk8, right?). For that you'll also need to add
BOOTBLOCK_NORTHBRIDGE_INIT to amdk8's Kconfig (similar to amdfam10) to
make the build system use it.
Also check src/southbridge/amd/amd8111/bootblock.c - maybe the PCI ID
More information about the coreboot