[coreboot] New patch to review for coreboot: 2f34f0c Unbreak all boards where chipset is capable of selection of FSB/serial APIC bus

Rudolf Marek (r.marek@assembler.cz) gerrit at coreboot.org
Mon Apr 23 00:00:46 CEST 2012

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/921


commit 2f34f0c19b365f2cf1ac221dd6bdb667e92f5baf
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Sun Apr 22 23:52:23 2012 +0200

    Unbreak all boards where chipset is capable of selection of FSB/serial APIC bus
    The commit Change I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f contains #ifdef instead
    of #if making the FSB/serial bus selection for APIC always to fall to serial APIC bus
    This bug is not visible on most chipsets, because this bit is RO, but it do broke
    VIA K8T890 chipsets.
    Change-Id: I89c4855922199eca7f921c3e4eb500656544c8e5
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
 src/arch/x86/lib/ioapic.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index e974d7c..57b99e2 100644
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -89,7 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 		ioapic_interrupts = 24;
 	printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
 	 * For the Pentium 4 and above APICs deliver their interrupts
 	 * on the front side bus, enable that.
@@ -98,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 	io_apic_write(ioapic_base, 0x03,
 		      io_apic_read(ioapic_base, 0x03) | (1 << 0));
 	printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
 	io_apic_write(ioapic_base, 0x03, 0);

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