[coreboot] Dual SPI Flash adapter attempt 2.0

[Oliver Schinagl]

Really quick update,

routed a sideway version. Wow, that was a huge pain. Lots of via's. 
Don't wanna have to redo this one :)

Oliver

On 04/23/12 20:23, Oliver Schinagl wrote:
> Hi!
>
> I've worked on a rotated version and planning to do two other
> orientations as well, so early feedback is good, so I don't have to redo
> them again :)
>
> Silk screening isn't 100% right, since I still need to rename them
> eventually somehow (edit .pcb file directly is probably the easiest way?)
>
> On 04/20/12 14:50, Oliver Schinagl wrote:
>> Hi list(s),
>>
>> Here's my second attempt at routing the previously mailed png of my
>> schema.
>>
>> It was a lot trickier to route then my previous version, but I think it
>> worked out!
>>
>> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>
>> Hopefully there's no obvious mistakes and can start working on
>> alternative layouts (so it is insert-able in different angles).
>>
>> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
>> That said, DRC check passes when I set the copper width/distance to
>> 7mil's instead of the current 8 mils.
>>
>> I'm planning on having these PCB's manufactured by Seeed studio and
>> their minimal width is much smaller.
>>
>> Minimum trace width: 6mil
>> Minimum trace/vias/pads space : 6mil
>> Minimum silkscreen width : 4mil
>> Minimum silkscreen text size : 32mil
>>
>> I've used a grid size of 10mil and distances of 8 mils, as I didn't want
>> to rely on the minimum of seed. The silkscreen I positioned using a grid
>> size of 5 mil's however. Not sure what they mean with a 'minimum
>> silkscreen text size' however.
>>
>> Anyhow, feedback greatly appreciated, so I can start working on
>> alternative layouts :)
>>
>>
>
>

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