From gerrit at coreboot.org Wed Aug 1 08:32:11 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Aug 2012 08:32:11 +0200 Subject: [coreboot] New patch to review for coreboot: 3dc036b Remove uma_memory_base from build if no GFXUMA References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1385 -gerrit commit 3dc036bd59e0534a41d6c1f81d0c2f3a4b0ab6bf Author: Ky?sti M?lkki Date: Wed Aug 1 08:05:22 2012 +0300 Remove uma_memory_base from build if no GFXUMA This patch validates the previous "drop uma_memory_base" patches; there are no more references to uma_memory_base when GFXUMA is not selected. Change-Id: I735b5e765b0c5cb4af1b4a7470cfe1af2bda7d38 Signed-off-by: Ky?sti M?lkki --- src/devices/device.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index 92a4447..6b1902d 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -54,10 +54,11 @@ struct resource *free_resources = NULL; DECLARE_SPIN_LOCK(dev_lock) - +#if CONFIG_GFXUMA /* IGD UMA memory */ uint64_t uma_memory_base = 0; uint64_t uma_memory_size = 0; +#endif /** * Allocate a new device structure. From gerrit at coreboot.org Wed Aug 1 09:42:35 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Aug 2012 09:42:35 +0200 Subject: [coreboot] New patch to review for coreboot: c539aeb Add infrastructure to distribute MSRs across CPUs on init References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1386 -gerrit commit c539aeba4a570f209667255f1fd68c48bc46e12a Author: Ky?sti M?lkki Date: Tue Jul 31 20:52:47 2012 +0300 Add infrastructure to distribute MSRs across CPUs on init Some MSRs need to be replicated from one CPU to another. As the first step handle TOP_MEM and TOP_MEM2 for AMD CPUs. There is no need to regenerate MTRR setup from the registered memory resources separately for each CPU, doing it once and saving a copy in a table should do it. Also writing of MTRR MSRs to CPUs should be synchronized, reading from a table should simplify that process. The created table can be moved to cbmem to use it on S2/S3 resumes. Change-Id: I9bf0c47f825f7174b5108a32fba56e9fec5bb62b Signed-off-by: Ky?sti M?lkki --- src/cpu/x86/mtrr/Makefile.inc | 1 + src/cpu/x86/mtrr/msr.c | 51 +++++++++++++++++++++++++++++++++++++++++ src/include/cpu/x86/msr.h | 7 +++++ 3 files changed, 59 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index cecb826..65a53d3 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1 +1,2 @@ ramstage-y += mtrr.c +ramstage-y += msr.c diff --git a/src/cpu/x86/mtrr/msr.c b/src/cpu/x86/mtrr/msr.c new file mode 100644 index 0000000..b79c75e --- /dev/null +++ b/src/cpu/x86/mtrr/msr.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include + +/* Storage for MSRs that need to be replicated over + * all CPUs after power-on and S2/S3 resumes. + */ +static struct msr_non_volatile_struct { + uint64_t tolm; /* Top of low RAM < 4GB. */ + uint64_t tom; /* Top of RAM. */ + +#if 0 + msrinit_t mtrr[MAX_MTRRS]; /* TODO */ +#endif +} msr_non_volatile; + +void msr_nv_setup_ramtop(uint64_t tolm, uint64_t tom) +{ + msr_non_volatile.tolm = tolm; + msr_non_volatile.tom = tom; +} + +uint64_t msr_nv_get_tolm(void) +{ + return msr_non_volatile.tolm; +} + +uint64_t msr_nv_get_tom(void) +{ + return msr_non_volatile.tom; +} + diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 40926df..17d105d 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -17,6 +17,8 @@ static void wrmsr(unsigned long index, msr_t msr) #else +#include + typedef struct msr_struct { unsigned lo; @@ -59,6 +61,11 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms ); } +/* Utility functions for non-volatile copy of MSRs. */ +void msr_nv_setup_ramtop(uint64_t tolm, uint64_t tom); +uint64_t msr_nv_get_tolm(void); +uint64_t msr_nv_get_tom(void); + #endif /* __ROMCC__ */ #endif /* CPU_X86_MSR_H */ From gerrit at coreboot.org Wed Aug 1 10:39:10 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 1 Aug 2012 10:39:10 +0200 Subject: [coreboot] Patch set updated for coreboot: 2785a0c AMD F15tn northbridge: Remove the misleading 0x100 from the limitk. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1265 -gerrit commit 2785a0c0c64b140a1e0a57ca060b7b4d193a91e5 Author: zbao Date: Wed Aug 1 18:23:49 2012 +0800 AMD F15tn northbridge: Remove the misleading 0x100 from the limitk. I dont known if missed something, but why an extra 0x100 was added to limit? My board would get the wrong memory table entry 7f000000-7fffffff as RAM, which is higher than TOM. coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000005e13efff: RAM 3. 000000005e13f000-000000005effffff: CONFIGURATION TABLES 4. 000000005f000000-000000007effffff: RESERVED 5. 000000007f000000-000000007fffffff: RAM 6. 00000000a0000000-00000000afffffff: RESERVED Ronald G. Minnich: I think someone who wrote the code was trying to round up the next 0x100 boundary and did it incorrectly. Here is code that would do it correctly: limitk = ((resource_t)((d.mask + 0x00000ff) & 0x1fffff00)) << 9 ; Zheng: Plus 0xFF is correct, but the d.mask take bit 0 as enable it. This bit should be clear when we try to calculate the limitk. Change-Id: I3848ed5f23001e5bd61a19833650fe13df26eef3 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 12aab33..85de812 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -790,7 +790,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; sizek = limitk - basek; From gerrit at coreboot.org Wed Aug 1 10:46:51 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 1 Aug 2012 10:46:51 +0200 Subject: [coreboot] Patch set updated for coreboot: 117b2d4 AMD Thatcher Board based on trinity References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1382 -gerrit commit 117b2d40a13d75355a14ac25f828afd2b57f043c Author: zbao Date: Wed Aug 1 18:31:15 2012 +0800 AMD Thatcher Board based on trinity Thatcher features: Family 15 trinity FP2. Hudson. close to Parmer. This board and parmer both need to revert the change http://review.coreboot.org/#/c/1359/, and add thatcher's own chip.h,otherwise the mainboard_enable can not be called. Change-Id: I54e1cfca845fbcea1d3aad5eff08d760d0d215c9 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/thatcher/BiosCallOuts.c | 737 ++++++++++ src/mainboard/amd/thatcher/BiosCallOuts.h | 82 ++ src/mainboard/amd/thatcher/Kconfig | 115 ++ src/mainboard/amd/thatcher/Makefile.inc | 33 + src/mainboard/amd/thatcher/OptionsIds.h | 67 + src/mainboard/amd/thatcher/PlatformGnbPcie.c | 206 +++ .../amd/thatcher/PlatformGnbPcieComplex.h | 72 + src/mainboard/amd/thatcher/acpi/AmdImc.asl | 95 ++ src/mainboard/amd/thatcher/acpi/cpstate.asl | 115 ++ src/mainboard/amd/thatcher/acpi/ide.asl | 244 ++++ src/mainboard/amd/thatcher/acpi/routing.asl | 356 +++++ src/mainboard/amd/thatcher/acpi/sata.asl | 148 ++ src/mainboard/amd/thatcher/acpi/usb.asl | 114 ++ src/mainboard/amd/thatcher/acpi_tables.c | 329 +++++ src/mainboard/amd/thatcher/agesawrapper.c | 775 +++++++++++ src/mainboard/amd/thatcher/agesawrapper.h | 97 ++ src/mainboard/amd/thatcher/buildOpts.c | 513 +++++++ src/mainboard/amd/thatcher/cmos.layout | 114 ++ src/mainboard/amd/thatcher/devicetree.cb | 104 ++ src/mainboard/amd/thatcher/dimmSpd.c | 166 +++ src/mainboard/amd/thatcher/dimmSpd.h | 59 + src/mainboard/amd/thatcher/dsdt.asl | 1421 ++++++++++++++++++++ src/mainboard/amd/thatcher/fadt.c | 202 +++ src/mainboard/amd/thatcher/get_bus_conf.c | 140 ++ src/mainboard/amd/thatcher/irq_tables.c | 112 ++ src/mainboard/amd/thatcher/mainboard.c | 76 ++ src/mainboard/amd/thatcher/mptable.c | 206 +++ src/mainboard/amd/thatcher/pmio.c | 53 + src/mainboard/amd/thatcher/pmio.h | 33 + src/mainboard/amd/thatcher/reset.c | 64 + src/mainboard/amd/thatcher/romstage.c | 179 +++ 32 files changed, 7030 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index eaaf877..2276129 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -39,6 +39,8 @@ config BOARD_AMD_UNIONSTATION bool "Unionstation" config BOARD_AMD_PARMER bool "Parmer" +config BOARD_AMD_THATCHER + bool "Thatcher" endchoice source "src/mainboard/amd/db800/Kconfig" @@ -59,6 +61,7 @@ source "src/mainboard/amd/south_station/Kconfig" source "src/mainboard/amd/torpedo/Kconfig" source "src/mainboard/amd/union_station/Kconfig" source "src/mainboard/amd/parmer/Kconfig" +source "src/mainboard/amd/thatcher/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c new file mode 100644 index 0000000..34936e0 --- /dev/null +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -0,0 +1,737 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" + +STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GET_IDS_INIT_DATA, + BiosGetIdsInitData + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, + + {AGESA_FCH_OEM_CALLOUT, + Fch_Oem_config + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + break; + } + } + + if(i >= CallOutCount) + { + return AGESA_UNSUPPORTED; + } + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + +CONST IDS_NV_ITEM IdsData[] = +{ + /*{ + AGESA_IDS_NV_MAIN_PLL_CON, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID_EN, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID, + 0x8 + }, + + { + AGESA_IDS_NV_CUSTOM_NB_PSTATE, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL, + }, + { + AGESA_IDS_NV_FORCE_NB_PSTATE, + }, + */ + { + 0xFFFF, + 0xFFFF + } +}; + +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) + +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + IDS_NV_ITEM *IdsPtr; + + IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; + + if (Data == IDS_CALLOUT_INIT) { + for (i = 0; i < NUM_IDS_ENTRIES; i++) { + IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; + IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/** + * AMD Thatcher Platform ALC272 Verb Table + */ +const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, + {0x12, 0x411111F0}, + {0x13, 0x411111F0}, + {0x14, 0x411111F0}, + {0x15, 0x411111F0}, + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, + {0x18, 0x01a19840}, + {0x19, 0x411111F0}, + {0x1a, 0x01813030}, + {0x1b, 0x411111F0}, + {0x1d, 0x40130605}, + {0x1e, 0x01441120}, + {0x21, 0x01211010}, + {0xff, 0xffffffff} +}; + +const CODEC_TBL_LIST ThatcherCodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + +/* Parmer Hardware Monitor Fan Control + * Hardware limitation: + * HWM failed to read the input temperture vi I2C, + * if other software switch the I2C switch by mistake or intention. + * We recommend to using IMC to control Fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + FCH_HWM_FAN_CTR oem_factl[5] = { + /*temperatuer input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ + /* Parmer FanOUT0 Fan header J32 */ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + /* Parmer FanOUT1 Fan header J31*/ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + }; + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + + /* Enable IMC fan control. the recommand way */ +#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + + /* Thermal Zone Parameter */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x35; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0E;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 1; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0; + + /* IMC Fan Policy temperature thresholds */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 105;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 60; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 105; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x54; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 1; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 80; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; + + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 100; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; + + /* IMC Function */ + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; + + /* NOTE: + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, + * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. + * so we remove it from AGESA code. Please Seee FchInitLateHwm. + */ + +#else /* HWM fan control, the way not recommand */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, GEC, IMC etc. + */ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + + if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); + /* Azalia Controller Front Panel OEM Table Pointer */ + + /* Fan Control */ + oem_fan_control(FchParams_env); + + /* XHCI configuration */ + FchParams_env->Usb.Xhci0Enable = FALSE; + FchParams_env->Usb.Xhci1Enable = FALSE; + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.h b/src/mainboard/amd/thatcher/BiosCallOuts.h new file mode 100644 index 0000000..1993c64 --- /dev/null +++ b/src/mainboard/amd/thatcher/BiosCallOuts.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define REQUIRED_CALLOUTS 12 +#define BIOS_HEAP_START_ADDRESS 0x010000000 +#define BIOS_HEAP_SIZE 0x30000 +#define BSP_STACK_BASE_ADDR 0x30000 + + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* FCH OEM Config*/ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig new file mode 100644 index 0000000..82a154b --- /dev/null +++ b/src/mainboard/amd/thatcher/Kconfig @@ -0,0 +1,115 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_THATCHER + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select SUPERIO_SMSC_LPC47N217 + select BOARD_ROMSIZE_KB_4096 + select TINY_BOOTBLOCK + select GFXUMA + select UDELAY_LAPIC + +config MAINBOARD_DIR + string + default amd/thatcher + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Thatcher" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS_ID + string + default "1002,9917" + +config WARNINGS_ARE_ERRORS + bool + default n + +endif # BOARD_AMD_THATCHER diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc new file mode 100644 index 0000000..e345243 --- /dev/null +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c + +ramstage-y += reset.c +ramstage-y += pmio.c diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h new file mode 100644 index 0000000..0a1d328 --- /dev/null +++ b/src/mainboard/amd/thatcher/OptionsIds.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c new file mode 100644 index 0000000..e4308e4 --- /dev/null +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +PCIe_PORT_DESCRIPTOR PortList [] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), + PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ + { + 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + +#if 1 + /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, +#endif +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, +// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) + }, + // GFX Lane 15-12 + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) + }, + // GFX Lane 11-8 + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) + }, + // GFX Lane 7-4 + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) + } +}; + +PCIe_COMPLEX_DESCRIPTOR Trinity = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *TrinityPcieComplexListPtr; + VOID *TrinityPciePortPtr; + VOID *TrinityPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } + + TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (TrinityPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (TrinityPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 7, + &InitEarly->StdHeader); + + LibAmdMemFill (TrinityPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 6, + &InitEarly->StdHeader); + + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; +} diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h b/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..c10d251 --- /dev/null +++ b/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/thatcher/acpi/AmdImc.asl b/src/mainboard/amd/thatcher/acpi/AmdImc.asl new file mode 100644 index 0000000..937c10a --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/AmdImc.asl @@ -0,0 +1,95 @@ +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + While (LNotEqual(Local0, 0xFA)) { + Store(MRG0, Local0) + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/amd/thatcher/acpi/cpstate.asl b/src/mainboard/amd/thatcher/acpi/cpstate.asl new file mode 100644 index 0000000..0747c5c --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/cpstate.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/thatcher/acpi/ide.asl b/src/mainboard/amd/thatcher/acpi/ide.asl new file mode 100644 index 0000000..765a67e --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/thatcher/acpi/routing.asl b/src/mainboard/amd/thatcher/acpi/routing.asl new file mode 100644 index 0000000..cc03701 --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/routing.asl @@ -0,0 +1,356 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 Pcie Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + +#if 0 //parmer not use + Name(PS3, Package(){ + /* The external GFX - Hooked to PCIe slot 3 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS3, Package(){ + /* The external GFX - Hooked to PCIe slot 3 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) +#endif + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 0*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 0*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 1*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 1*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 2*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 2*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 3 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 3*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + /* SB PCI Bridge J21, J22 */ + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, +/* + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, +*/ + }) +} diff --git a/src/mainboard/amd/thatcher/acpi/sata.asl b/src/mainboard/amd/thatcher/acpi/sata.asl new file mode 100644 index 0000000..8fd9e9b --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/sata.asl @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/thatcher/acpi/usb.asl b/src/mainboard/amd/thatcher/acpi/usb.asl new file mode 100644 index 0000000..7780a15 --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/usb.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + } + } +} diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c new file mode 100644 index 0000000..0a64535 --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -0,0 +1,329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include +#include + +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 + +static void dump_mem(u32 start, u32 end) +{ + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* Not implemented */ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; /* it will used by fadt */ + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ /* it needs 64 bit alignment */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; /* it will be used by fadt */ + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FADT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *) current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c new file mode 100644 index 0000000..509f472 --- /dev/null +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -0,0 +1,775 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include +#include +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include +#include +#include +#include + +VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 heap; + +#if CONFIG_HAVE_ACPI_RESUME + /* Both romstage and ramstage has this S3 detect. */ + if (acpi_get_sleep_type() == 3) + heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + else +#endif + heap = BIOS_HEAP_START_ADDRESS; /* Low mem */ + + return heap; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost (PostParams); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct (&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + + status = AmdInitEnv (EnvParam); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate(AmdLateParams); + /* CDIT table is not created. */ + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + /* agesawrapper_amdreadeventlog(); */ + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#if CONFIG_HAVE_ACPI_RESUME == 1 + +UINT32 agesawrapper_amdinitresume(VOID) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; +#if 1 /* TODO: Get the param from Nv storage. */ + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); +#endif + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +#ifndef __PRE_RAM__ + +extern FCH_DATA_BLOCK InitEnvCfgDefault; +STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) +{ + FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; + FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; + FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; + FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; + FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; + FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; + FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; + FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; + FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; + FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ + FchParams->Gpp.GppPhyPllPowerDown = TRUE; + FchParams->Gpp.GppDynamicPowerSaving = TRUE; + FchParams->Gpp.UmiPhyPllPowerDown = TRUE; + FchParams->Gpp.NewGppAlgorithm = TRUE; + FchParams->Gpp.GppPortMinPollingTime = 40; + + FchParams->Spi.SpiSpeed = 2; + FchParams->Ir.IrConfig = 3; + + FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; + FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; + FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; + FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; + FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; + FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; + FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; + FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; + FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; + FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; + FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; + FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; + FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; + FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; + FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; + FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; + FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; + FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; + FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; + FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; + FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; + FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; + FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; + FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; + FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; + FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; + FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; + FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; +} + +UINT32 agesawrapper_fchs3earlyrestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + + FchInitS3EarlyRestore(&FchParams); + + return status; +} +#endif + +UINT32 agesawrapper_amds3laterestore (VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + +#if 1 /* TODO:Get params from Volatile storage. */ + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); +#endif + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#ifndef __PRE_RAM__ + +extern UINT8 picr_data[0x54], intr_data[0x54]; + +UINT32 agesawrapper_fchs3laterestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + UINT8 byte; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + return status; +} +#endif + +#ifndef __PRE_RAM__ + +UINT32 agesawrapper_amdS3Save(VOID) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); +#if 1 /* TODO: Save the params to NvStorage */ + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); +#endif + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + +#if 1 /* TODO: Save the params to VolatileStorage */ + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); +#endif + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} + +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + +UINT32 +agesawrapper_amdreadeventlog ( + UINT8 HeapStatus + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/thatcher/agesawrapper.h b/src/mainboard/amd/thatcher/agesawrapper.h new file mode 100644 index 0000000..db893cd --- /dev/null +++ b/src/mainboard/amd/thatcher/agesawrapper.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitcpuio (void); +void *agesawrapper_getlateinitptr (int pick); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); +UINT32 agesawrapper_amdS3Save(VOID); +UINT32 agesawrapper_amdinitresume(VOID); +UINT32 agesawrapper_amds3laterestore (VOID); + +UINT32 agesawrapper_fchs3earlyrestore (VOID); +UINT32 agesawrapper_fchs3laterestore (VOID); + +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + +#endif diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c new file mode 100644 index 0000000..67e4223 --- /dev/null +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -0,0 +1,513 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + */ + +#include "AGESA.h" +//#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT FALSE +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT TRUE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT TRUE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +#define INSTALL_FM2_SOCKET_SUPPORT FALSE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +//#define BLDOPT_REMOVE_DMI FALSE //TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +// Specify the default values for the VRM controlling the VDDNB plane. +// If not specified, the values used for the core VRM will be applied +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 + +#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 +#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 + +#if CONFIG_GFXUMA +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#endif + +#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList + +//#include "VirgoInstall.h" + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 +#define FCH_NO_XHCI_SUPPORT TRUE +GPIO_CONTROL thatcher_gpio[] = { + {183, Function1, PullUpB}, + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket + // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +// Customer table +UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]); + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout new file mode 100644 index 0000000..f6b5806 --- /dev/null +++ b/src/mainboard/amd/thatcher/cmos.layout @@ -0,0 +1,114 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb new file mode 100644 index 0000000..2a91e1a --- /dev/null +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -0,0 +1,104 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family15tn/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 on end # PCIE SLOT0 x16 + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end + end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/lpc47n217 + device pnp 2e.3 off # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end #superio/smsc/lpc47n217 + end + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 +# device pci 14.6 on end # Gec + device pci 14.7 on end + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 +# device pci 16.0 off end # XHCI0 Hudson2 only +# device pci 16.2 off end # XHCI1 Hudson2 only + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + end #southbridge/amd/hudson +# device pci 18.0 on end + #device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/thatcher/dimmSpd.c b/src/mainboard/amd/thatcher/dimmSpd.c new file mode 100644 index 0000000..29d6a29 --- /dev/null +++ b/src/mainboard/amd/thatcher/dimmSpd.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "dimmSpd.h" + +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*#pragma optimize ("", off) // for source level debug + *--------------------------------------------------------------------------- + * + * SPD address table - porting required + */ + +static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm +{ + // socket 0 + { + {0xA0, 0x00}, // channel 0 dimms + {0xA2, 0x00}, // channel 1 dimms + }, + // socket 1 + { + {0x00, 0x00}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, +}; + +/*----------------------------------------------------------------------------- + * + * readSmbusByteData - read a single SPD byte from any offset + */ + +static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +{ + unsigned int status; + UINT64 limit; + + address |= 1; // set read bit + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command + + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} + +/*----------------------------------------------------------------------------- + * + * readSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + */ + +static int readSmbusByte (int iobase, int address, char *buffer) +{ + unsigned int status; + UINT64 limit; + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} + +/*--------------------------------------------------------------------------- + * + * readspd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ + +static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +{ + int index, error; + + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; + + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) + { + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } + + return 0; +} + +static void writePmReg (int reg, int data) +{ + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); +} + +static void setupFch (int ioBase) +{ + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + //writePmReg (0x29, 0x80); + //writePmReg (0x28, 0x61); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz +} + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) +{ + int spdAddress, ioBase; + + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + ioBase = 0xB00; + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); +} diff --git a/src/mainboard/amd/thatcher/dimmSpd.h b/src/mainboard/amd/thatcher/dimmSpd.h new file mode 100644 index 0000000..c19cecc --- /dev/null +++ b/src/mainboard/amd/thatcher/dimmSpd.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl new file mode 100644 index 0000000..e0cc3fd --- /dev/null +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -0,0 +1,1421 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "PARMER ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0xEE), + UPWS, 3, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + Scope(\_SB) { + /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + //Store(0, PIRA) + //Store(0, PIRB) + //Store(0, PIRC) + //Store(0, PIRD) + //Store(0, PIRE) + //Store(0, PIRF) + //Store(0, PIRG) + //Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + //Store(0x1F, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + //Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + //Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + //Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + //Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + //Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + //Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + //Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + //Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + //Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + //if (LEqual(Arg0,3)){ + // Store(0,URRE) + //} + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + //Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + //if (LEqual(Arg0,3)){ + // Store(1,URRE) + //} + + /* Arbitrarily clear PciExpWakeStatus */ + //Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + //#include "acpi/usb.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices Dev0 ,Func0*/ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + +#if 0 //not used in Parmer + /* Dev3 is also an external GFX bridge */ + Device(PBR3) { + Name(_ADR, 0x00030000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR3 */ +#endif + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + //#include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + Name(_PRW, Package() {0x0B, 4}) + } /* end XHC0 */ + Device(XHC1) { + Name(_ADR, 0x00100001) + Name(_PRW, Package() {0x0B, 4}) + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + //#include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x03B0, /* range minimum */ + 0x03DF, /* range maximum */ + 0x0000, /* translation */ + 0x0030 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + /* TODO: It is unstable. */ + //#include "acpi/AmdImc.asl" /* Hudson IMC function */ + //ITZE() /* enable IMC Fan Control*/ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ +} +/* End of ASL file */ diff --git a/src/mainboard/amd/thatcher/fadt.c b/src/mainboard/amd/thatcher/fadt.c new file mode 100644 index 0000000..b72208c --- /dev/null +++ b/src/mainboard/amd/thatcher/fadt.c @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include +#include +#include +#include +#include +#include "pmio.h" + +/*extern*/ u16 pm_base = 0x800; +/* pm_base should be set in sb acpi */ +/* pm_base should be got from bar2 of sb800. Here I compact ACPI + * registers into 32 bytes limit. + * */ + +#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */ +#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */ +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + pm_base &= 0xFFFF; + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + #if 1 + pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); + pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); + pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); + pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); + pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); + pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); + pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); + pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF); + pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8); + + pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ + pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ + + pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); + pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); + #endif + + pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses + * the contents of the PM registers at + * index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;//0xFE00;// + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5 | 1 << 10;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;//0xFE00;//ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c new file mode 100644 index 0000000..ad5e1d7 --- /dev/null +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_sb800[3]; +u32 apicid_sb800; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_sb800; + +static u32 get_bus_conf_done = 0; + +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } + } +#else + status = agesawrapper_amdinitlate(); + if (status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); +#endif + + sbdn_sb800 = 0; + + for (i = 0; i < 3; i++) { + bus_sb800[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + + /* sb800 */ + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + + if (dev) { + bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb800[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + if (dev) { + bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sb800[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_sb800 = apicid_base; +} diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c new file mode 100644 index 0000000..3bcd3fb --- /dev/null +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern u8 bus_isa; +extern u8 bus_sb800[2]; +extern unsigned long sbdn_sb800; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb800[0]; + pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c new file mode 100644 index 0000000..52581b8 --- /dev/null +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "BiosCallOuts.h" +#include +#include "agesawrapper.h" + +/************************************************* + * enable the dedicated function in thatcher board. + *************************************************/ +static void thatcher_enable(device_t dev) +{ + msr_t msr; + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ + msr = rdmsr(0xC0011020); + msr.lo &= ~(1 << 28); + wrmsr(0xC0011020, msr); + + msr = rdmsr(0xC0011022); + msr.lo &= ~(1 << 4); + msr.lo &= ~(1 << 13); + wrmsr(0xC0011022, msr); + + msr = rdmsr(0xC0011023); + msr.lo &= ~(1 << 23); + wrmsr(0xC0011023, msr); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); + if (acpi_slp_type == 3) + agesawrapper_fchs3earlyrestore(); + +#endif + setup_uma_memory(); +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = thatcher_enable, +}; diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c new file mode 100644 index 0000000..329f731 --- /dev/null +++ b/src/mainboard/amd/thatcher/mptable.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "pmio.h" +#include +#include + +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +#define IO_APIC_ID CONFIG_MAX_CPUS +extern u8 bus_sb800[3]; + +extern u32 bus_type[256]; +extern u32 sbdn_sb800; +extern u32 apicid_sb800; + +u8 picr_data[] = { + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 dword; + u8 byte; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + get_bus_conf(); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + + dword = 0; + dword = pm_ioread(0x34) & 0xF0; + dword |= (pm_ioread(0x35) & 0xFF) << 8; + dword |= (pm_ioread(0x36) & 0xFF) << 16; + dword |= (pm_ioread(0x37) & 0xFF) << 24; + /* Set IO APIC ID onto IO_APIC_ID */ + write32 (dword, 0x00); + write32 (dword + 0x10, IO_APIC_ID << 24); + apicid_sb800 = IO_APIC_ID; + smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); + PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); + PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/thatcher/pmio.c b/src/mainboard/amd/thatcher/pmio.c new file mode 100644 index 0000000..a8f1d3d --- /dev/null +++ b/src/mainboard/amd/thatcher/pmio.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include /*inb, outb*/ +#include "pmio.h" + +static void pmio_write_index(u16 port_base, u8 reg, u8 value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static u8 pmio_read_index(u16 port_base, u8 reg) +{ + outb(reg, port_base); + return inb(port_base + 1); +} + +void pm_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM_INDEX, reg, value); +} + +u8 pm_ioread(u8 reg) +{ + return pmio_read_index(PM_INDEX, reg); +} + +void pm2_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM2_INDEX, reg, value); +} + +u8 pm2_ioread(u8 reg) +{ + return pmio_read_index(PM2_INDEX, reg); +} diff --git a/src/mainboard/amd/thatcher/pmio.h b/src/mainboard/amd/thatcher/pmio.h new file mode 100644 index 0000000..bc15fd9 --- /dev/null +++ b/src/mainboard/amd/thatcher/pmio.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PMIO_H_ +#define _PMIO_H_ + +#define PM_INDEX 0xCD6 +#define PM_DATA 0xCD7 +#define PM2_INDEX 0xCD0 +#define PM2_DATA 0xCD1 + +void pm_iowrite(u8 reg, u8 value); +u8 pm_ioread(u8 reg); +void pm2_iowrite(u8 reg, u8 value); +u8 pm2_ioread(u8 reg); + +#endif diff --git a/src/mainboard/amd/thatcher/reset.c b/src/mainboard/amd/thatcher/reset.c new file mode 100644 index 0000000..5735fa2 --- /dev/null +++ b/src/mainboard/amd/thatcher/reset.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c new file mode 100644 index 0000000..f7ffa4e --- /dev/null +++ b/src/mainboard/amd/thatcher/romstage.c @@ -0,0 +1,179 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "southbridge/amd/agesa/hudson/hudson.h" +#include "src/superio/smsc/lpc47n217/early_serial.c" +#include "cpu/amd/agesa/s3_resume.h" +#include "src/drivers/pc80/i8254.c" +#include "src/drivers/pc80/i8259.c" +#include "cbmem.h" + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void disable_cache_as_ram(void); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + u8 byte; + device_t dev; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + val = agesawrapper_amdinitmmio(); + + hudson_lpc_port80(); + //__asm__ volatile ("1: jmp 1b"); + /* TODO: */ + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + post_code(0x31); + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + outb(0xea, 0xcd6); + outb(0x1, 0xcd7); + *(u8 *)0xfed80101 = 0x98; + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + + post_code(0x38); + printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + + post_code(0x39); + + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + +#if CONFIG_HAVE_ACPI_RESUME + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + disable_cache_as_ram(); + enable_cache(); +#if CONFIG_HAVE_ACPI_RESUME + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = (void *)backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x50); + copy_and_run(0); + + post_code(0x54); /* Should never see this post code. */ +} From gerrit at coreboot.org Wed Aug 1 10:57:18 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 1 Aug 2012 10:57:18 +0200 Subject: [coreboot] Patch merged into coreboot/master: 15fa0ed Intel Sandybridge: add reserved memory as resources References: Message-ID: the following patch was just integrated into master: commit 15fa0edd877b491a807340d018369f303aee0722 Author: Ky?sti M?lkki Date: Thu Jul 26 23:51:20 2012 +0300 Intel Sandybridge: add reserved memory as resources Reserved memory resources will get removed from memory table at the end of write_coreboot_table(), Change-Id: I02711b4be4f25054bd3361295d8d4dc996b2eb3e Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Sun Jul 29 08:17:27 2012, giving +1 Reviewed-By: Anton Kochkov at Wed Aug 1 10:57:17 2012, giving +2 See http://review.coreboot.org/1372 for details. -gerrit From gerrit at coreboot.org Wed Aug 1 10:58:45 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 1 Aug 2012 10:58:45 +0200 Subject: [coreboot] Patch merged into coreboot/master: b0ab0b5 Intel Sandybridge and UMA: use mmio_resource() References: Message-ID: the following patch was just integrated into master: commit b0ab0b5948d3452f12b071f6105add111a5c9d03 Author: Ky?sti M?lkki Date: Fri Jul 27 13:12:03 2012 +0300 Intel Sandybridge and UMA: use mmio_resource() With SandyBridge northbridge code, uma_memory_size was reset to zero before variable MTRRs were set. This means MTRR setup routine did not previously create a un-cacheable hole for uma. Keep the behaviour that way, mmio_resource() has a prerequisuite that the new region does not overlap with any cacheable ram_resource(). The result is not optimal setup in the number of used MTRRs, but continue with this approach until MTRR algorithm is improved. Change-Id: I63c8df19ad6b6350d46a3eca3055abf684b8b114 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Sun Jul 29 08:02:08 2012, giving +1 Reviewed-By: Anton Kochkov at Wed Aug 1 10:58:44 2012, giving +2 See http://review.coreboot.org/1373 for details. -gerrit From gerrit at coreboot.org Wed Aug 1 11:53:28 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 1 Aug 2012 11:53:28 +0200 Subject: [coreboot] Patch merged into coreboot/master: b161e56 Intel and GFXUMA: drop redundant use of lb_add_memory_range() References: Message-ID: the following patch was just integrated into master: commit b161e5614ce6660b14a10d39d9a673715b88160c Author: Ky?sti M?lkki Date: Wed Jul 18 14:38:54 2012 +0300 Intel and GFXUMA: drop redundant use of lb_add_memory_range() Use of uma_resource() in northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Fri Jul 27 15:20:11 2012, giving +1 Reviewed-By: Anton Kochkov at Wed Aug 1 11:52:53 2012, giving +2 See http://review.coreboot.org/1238 for details. -gerrit From gerrit at coreboot.org Wed Aug 1 11:54:56 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 1 Aug 2012 11:54:56 +0200 Subject: [coreboot] Patch merged into coreboot/master: c33f6d0 AMD and GFXUMA : drop redundant use of lb_add_memory_range() References: Message-ID: the following patch was just integrated into master: commit c33f6d04c9b8c67891002f26038933f00ba8c2fd Author: Ky?sti M?lkki Date: Sun Jul 29 10:34:59 2012 +0300 AMD and GFXUMA : drop redundant use of lb_add_memory_range() See commit 505414a6cfb2aeef455b5144e4b96fc27f19eb39. Change-Id: Icc04af9726ae54141581aecc84c40e8aac54591d Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Sun Jul 29 10:22:58 2012, giving +1 Reviewed-By: Anton Kochkov at Wed Aug 1 11:54:09 2012, giving +2 See http://review.coreboot.org/1378 for details. -gerrit From gerrit at coreboot.org Wed Aug 1 15:43:13 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Aug 2012 15:43:13 +0200 Subject: [coreboot] New patch to review for coreboot: a7e36bf AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1387 -gerrit commit a7e36bf088ae53eb57025c6b8e0f85dfd5503a71 Author: Ky?sti M?lkki Date: Tue Jul 31 20:51:48 2012 +0300 AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/mtrr/amd_mtrr.c | 24 ++++++++++++++++++++ src/include/cpu/amd/mtrr.h | 5 ++++ src/northbridge/amd/agesa/family10/northbridge.c | 1 + src/northbridge/amd/agesa/family12/northbridge.c | 23 ++++--------------- src/northbridge/amd/agesa/family14/northbridge.c | 21 +++-------------- src/northbridge/amd/agesa/family15/northbridge.c | 22 ++++-------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 22 ++++-------------- src/northbridge/amd/amdfam10/northbridge.c | 22 +++--------------- src/northbridge/amd/amdk8/northbridge.c | 21 ++++------------- 9 files changed, 58 insertions(+), 103 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index f639d59..7787d7e 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -116,6 +116,30 @@ static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) } } +/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, + * so they can be distributed to AP CPUs. Not strictly MTRRs, + * but this is not that bad a place to have this code. + */ +void setup_bsp_ramtop(void) +{ + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk(BIOS_INFO, + "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk(BIOS_INFO, + "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + msr_nv_setup_ramtop((uint64_t) msr.hi<<32 | msr.lo, + (uint64_t) msr2.hi<<32 | msr2.lo); +} + void amd_setup_mtrrs(void) { unsigned long address_bits; diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 3637dd9..5e2ab8e 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -39,6 +39,11 @@ #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); + +/* To distribute topmem MSRs to APs. */ +void setup_bsp_ramtop(void); +#define bsp_topmem(x) msr_nv_get_tolm(x) +#define bsp_topmem2(x) msr_nv_get_tom(x) #endif #endif /* CPU_AMD_MTRR_H */ diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 831aec0..17bcf03 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -923,6 +923,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); #if CONFIG_GFXUMA #error Northbridge does not set uma_memory_base or uma_memory_size. #endif diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f3f03a4..9f1b712 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -472,21 +472,9 @@ static void set_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family12h BKDG. */ /* Please reference MemNGetUmaSizeLN () */ /* @@ -495,19 +483,17 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ } else if (sys_mem >= 0x40000000) { uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ } else { uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -611,6 +597,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index af6dfcc..d4a1c08 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -520,24 +520,12 @@ static void domain_read_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family14h BKDG. */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = top_mem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ } else { @@ -551,8 +539,6 @@ static void setup_uma_memory(void) uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -574,6 +560,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a080293..6ce73cb 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -632,20 +632,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -654,20 +643,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { + sys_mem = topmem + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 * ONE_MB)) { uma_memory_size = 512 * ONE_MB; } else if (sys_mem >= 1024 * ONE_MB) { uma_memory_size = 256 * ONE_MB; } else { uma_memory_size = 64 * ONE_MB; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -686,6 +673,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index f7f31a0..6d92867 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -641,20 +641,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -663,20 +652,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { uma_memory_size = 512 << ONE_MB_SHIFT; } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { uma_memory_size = 256 << ONE_MB_SHIFT; } else { uma_memory_size = 64 << ONE_MB_SHIFT; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -696,6 +683,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 15b29f6..386a369 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -851,22 +851,9 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - + uint32_t topmem = (uint32_t) bsp_topmem(); /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -880,11 +867,9 @@ static void setup_uma_memory(void) break; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -903,6 +888,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index bec02f0..29f4709 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -826,21 +826,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); + uint32_t topmem = (uint32_t) bsp_topmem(); #if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x2000000; /* 32M recommended UMA */ break; @@ -859,7 +849,7 @@ static void setup_uma_memory(void) } #else /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -874,11 +864,9 @@ static void setup_uma_memory(void) } #endif - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -896,6 +884,7 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if 0 From gerrit at coreboot.org Wed Aug 1 15:43:14 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Aug 2012 15:43:14 +0200 Subject: [coreboot] New patch to review for coreboot: 904f425 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1388 -gerrit commit 904f4257ab0b0bcf4ec35c8eaf807ca78eed66ab Author: Ky?sti M?lkki Date: Wed Aug 1 14:32:13 2012 +0300 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/mtrr/amd_mtrr.c | 49 ++++++++++++++++++------------------------ 1 files changed, 21 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 7787d7e..8abc3d3 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -102,20 +102,6 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc } -static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) -{ - struct mem_state *state = gp; - unsigned long topk; - - topk = resk(res->base + res->size); - if (state->tom2k < topk) { - state->tom2k = topk; - } - if ((topk < 4*1024*1024) && (state->tomk < topk)) { - state->tomk = topk; - } -} - /* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, * so they can be distributed to AP CPUs. Not strictly MTRRs, * but this is not that bad a place to have this code. @@ -140,6 +126,25 @@ void setup_bsp_ramtop(void) (uint64_t) msr2.hi<<32 | msr2.lo); } +static void setup_ap_ramtop(void) +{ + msr_t msr; + uint64_t v; + + v = bsp_topmem(); + if (!v) + return; + + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM, msr); + + v = bsp_topmem2(); + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM2, msr); +} + void amd_setup_mtrrs(void) { unsigned long address_bits; @@ -171,9 +176,6 @@ void amd_setup_mtrrs(void) state.tomk = state.tom2k = 0; search_global_resources( - IORESOURCE_MEM | IORESOURCE_UMA_FB, IORESOURCE_MEM | IORESOURCE_UMA_FB, - uma_fb_resource, &state); - search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_fixed_mtrr_resource, &state); @@ -181,20 +183,11 @@ void amd_setup_mtrrs(void) disable_cache(); - /* Round state.tomk up to the next greater size that will fit in TOP_MEM */ - state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tomk >> 22; - msr.lo = state.tomk << 10; - wrmsr(TOP_MEM, msr); + setup_ap_ramtop(); /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if(state.tom2k > (4*1024*1024)) { - /* Round state.tomk up to the next greater size that will fit in TOP_MEM2 */ - state.tom2k = (state.tom2k + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tom2k >> 22; - msr.lo = state.tom2k << 10; - wrmsr(TOP_MEM2, msr); + if (bsp_topmem2() > (uint64_t)1<<32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if(has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB; From gerrit at coreboot.org Wed Aug 1 15:43:14 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Aug 2012 15:43:14 +0200 Subject: [coreboot] Patch set updated for coreboot: f6e19b9 Add infrastructure to distribute MSRs across CPUs on init References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1386 -gerrit commit f6e19b99e7d4ec6d082670cbfa1e40bd68303e38 Author: Ky?sti M?lkki Date: Tue Jul 31 20:52:47 2012 +0300 Add infrastructure to distribute MSRs across CPUs on init Some MSRs need to be replicated from one CPU to another. As the first step handle TOP_MEM and TOP_MEM2 for AMD CPUs. There is no need to regenerate MTRR setup from the registered memory resources separately for each CPU, doing it once and saving a copy in a table should do it. Also writing of MTRR MSRs to CPUs should be synchronized, reading from a table should simplify that process. The created table can be moved to cbmem to use it on S2/S3 resumes. Change-Id: I9bf0c47f825f7174b5108a32fba56e9fec5bb62b Signed-off-by: Ky?sti M?lkki --- src/cpu/x86/mtrr/Makefile.inc | 1 + src/cpu/x86/mtrr/msr.c | 51 +++++++++++++++++++++++++++++++++++++++++ src/include/cpu/x86/msr.h | 7 +++++ 3 files changed, 59 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index cecb826..65a53d3 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1 +1,2 @@ ramstage-y += mtrr.c +ramstage-y += msr.c diff --git a/src/cpu/x86/mtrr/msr.c b/src/cpu/x86/mtrr/msr.c new file mode 100644 index 0000000..b79c75e --- /dev/null +++ b/src/cpu/x86/mtrr/msr.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include + +/* Storage for MSRs that need to be replicated over + * all CPUs after power-on and S2/S3 resumes. + */ +static struct msr_non_volatile_struct { + uint64_t tolm; /* Top of low RAM < 4GB. */ + uint64_t tom; /* Top of RAM. */ + +#if 0 + msrinit_t mtrr[MAX_MTRRS]; /* TODO */ +#endif +} msr_non_volatile; + +void msr_nv_setup_ramtop(uint64_t tolm, uint64_t tom) +{ + msr_non_volatile.tolm = tolm; + msr_non_volatile.tom = tom; +} + +uint64_t msr_nv_get_tolm(void) +{ + return msr_non_volatile.tolm; +} + +uint64_t msr_nv_get_tom(void) +{ + return msr_non_volatile.tom; +} + diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 40926df..17d105d 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -17,6 +17,8 @@ static void wrmsr(unsigned long index, msr_t msr) #else +#include + typedef struct msr_struct { unsigned lo; @@ -59,6 +61,11 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms ); } +/* Utility functions for non-volatile copy of MSRs. */ +void msr_nv_setup_ramtop(uint64_t tolm, uint64_t tom); +uint64_t msr_nv_get_tolm(void); +uint64_t msr_nv_get_tom(void); + #endif /* __ROMCC__ */ #endif /* CPU_X86_MSR_H */ From gerrit at coreboot.org Wed Aug 1 17:24:05 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 1 Aug 2012 17:24:05 +0200 Subject: [coreboot] Patch merged into coreboot/master: 2785a0c AMD F15tn northbridge: Remove the misleading 0x100 from the limitk. References: Message-ID: the following patch was just integrated into master: commit 2785a0c0c64b140a1e0a57ca060b7b4d193a91e5 Author: zbao Date: Wed Aug 1 18:23:49 2012 +0800 AMD F15tn northbridge: Remove the misleading 0x100 from the limitk. I dont known if missed something, but why an extra 0x100 was added to limit? My board would get the wrong memory table entry 7f000000-7fffffff as RAM, which is higher than TOM. coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000005e13efff: RAM 3. 000000005e13f000-000000005effffff: CONFIGURATION TABLES 4. 000000005f000000-000000007effffff: RESERVED 5. 000000007f000000-000000007fffffff: RAM 6. 00000000a0000000-00000000afffffff: RESERVED Ronald G. Minnich: I think someone who wrote the code was trying to round up the next 0x100 boundary and did it incorrectly. Here is code that would do it correctly: limitk = ((resource_t)((d.mask + 0x00000ff) & 0x1fffff00)) << 9 ; Zheng: Plus 0xFF is correct, but the d.mask take bit 0 as enable it. This bit should be clear when we try to calculate the limitk. Change-Id: I3848ed5f23001e5bd61a19833650fe13df26eef3 Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Wed Aug 1 10:55:35 2012, giving +1 Reviewed-By: Ronald G. Minnich at Wed Aug 1 17:24:04 2012, giving +2 See http://review.coreboot.org/1265 for details. -gerrit From gerrit at coreboot.org Wed Aug 1 19:25:23 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Aug 2012 19:25:23 +0200 Subject: [coreboot] Patch set updated for coreboot: 9b11754 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1388 -gerrit commit 9b11754878a693d844505df00bb02ec2e9666b6b Author: Ky?sti M?lkki Date: Wed Aug 1 14:32:13 2012 +0300 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/mtrr/amd_mtrr.c | 49 ++++++++++++++++++------------------------ 1 files changed, 21 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 7787d7e..8abc3d3 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -102,20 +102,6 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc } -static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) -{ - struct mem_state *state = gp; - unsigned long topk; - - topk = resk(res->base + res->size); - if (state->tom2k < topk) { - state->tom2k = topk; - } - if ((topk < 4*1024*1024) && (state->tomk < topk)) { - state->tomk = topk; - } -} - /* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, * so they can be distributed to AP CPUs. Not strictly MTRRs, * but this is not that bad a place to have this code. @@ -140,6 +126,25 @@ void setup_bsp_ramtop(void) (uint64_t) msr2.hi<<32 | msr2.lo); } +static void setup_ap_ramtop(void) +{ + msr_t msr; + uint64_t v; + + v = bsp_topmem(); + if (!v) + return; + + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM, msr); + + v = bsp_topmem2(); + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM2, msr); +} + void amd_setup_mtrrs(void) { unsigned long address_bits; @@ -171,9 +176,6 @@ void amd_setup_mtrrs(void) state.tomk = state.tom2k = 0; search_global_resources( - IORESOURCE_MEM | IORESOURCE_UMA_FB, IORESOURCE_MEM | IORESOURCE_UMA_FB, - uma_fb_resource, &state); - search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_fixed_mtrr_resource, &state); @@ -181,20 +183,11 @@ void amd_setup_mtrrs(void) disable_cache(); - /* Round state.tomk up to the next greater size that will fit in TOP_MEM */ - state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tomk >> 22; - msr.lo = state.tomk << 10; - wrmsr(TOP_MEM, msr); + setup_ap_ramtop(); /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if(state.tom2k > (4*1024*1024)) { - /* Round state.tomk up to the next greater size that will fit in TOP_MEM2 */ - state.tom2k = (state.tom2k + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tom2k >> 22; - msr.lo = state.tom2k << 10; - wrmsr(TOP_MEM2, msr); + if (bsp_topmem2() > (uint64_t)1<<32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if(has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB; From gerrit at coreboot.org Wed Aug 1 19:25:24 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Aug 2012 19:25:24 +0200 Subject: [coreboot] Patch set updated for coreboot: 9267f48 AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1387 -gerrit commit 9267f48774c23393e40ea09bacc2f2aaa81b5d2a Author: Ky?sti M?lkki Date: Tue Jul 31 20:51:48 2012 +0300 AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/mtrr/amd_mtrr.c | 24 ++++++++++++++++++++ src/include/cpu/amd/mtrr.h | 5 ++++ src/northbridge/amd/agesa/family10/northbridge.c | 1 + src/northbridge/amd/agesa/family12/northbridge.c | 23 ++++--------------- src/northbridge/amd/agesa/family14/northbridge.c | 23 ++++--------------- src/northbridge/amd/agesa/family15/northbridge.c | 22 ++++-------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 23 +++++-------------- src/northbridge/amd/amdfam10/northbridge.c | 22 +++--------------- src/northbridge/amd/amdk8/northbridge.c | 21 ++++------------- 9 files changed, 60 insertions(+), 104 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index f639d59..7787d7e 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -116,6 +116,30 @@ static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) } } +/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, + * so they can be distributed to AP CPUs. Not strictly MTRRs, + * but this is not that bad a place to have this code. + */ +void setup_bsp_ramtop(void) +{ + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk(BIOS_INFO, + "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk(BIOS_INFO, + "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + msr_nv_setup_ramtop((uint64_t) msr.hi<<32 | msr.lo, + (uint64_t) msr2.hi<<32 | msr2.lo); +} + void amd_setup_mtrrs(void) { unsigned long address_bits; diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 3637dd9..5e2ab8e 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -39,6 +39,11 @@ #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); + +/* To distribute topmem MSRs to APs. */ +void setup_bsp_ramtop(void); +#define bsp_topmem(x) msr_nv_get_tolm(x) +#define bsp_topmem2(x) msr_nv_get_tom(x) #endif #endif /* CPU_AMD_MTRR_H */ diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 831aec0..17bcf03 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -923,6 +923,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); #if CONFIG_GFXUMA #error Northbridge does not set uma_memory_base or uma_memory_size. #endif diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f3f03a4..9f1b712 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -472,21 +472,9 @@ static void set_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family12h BKDG. */ /* Please reference MemNGetUmaSizeLN () */ /* @@ -495,19 +483,17 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ } else if (sys_mem >= 0x40000000) { uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ } else { uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -611,6 +597,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index af6dfcc..a5a6be0 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -520,24 +520,12 @@ static void domain_read_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family14h BKDG. */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ } else { @@ -548,11 +536,9 @@ static void setup_uma_memory(void) } } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -574,6 +560,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a080293..6ce73cb 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -632,20 +632,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -654,20 +643,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { + sys_mem = topmem + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 * ONE_MB)) { uma_memory_size = 512 * ONE_MB; } else if (sys_mem >= 1024 * ONE_MB) { uma_memory_size = 256 * ONE_MB; } else { uma_memory_size = 64 * ONE_MB; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -686,6 +673,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index f7f31a0..52d6170 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -31,6 +31,7 @@ #include #include +#include #include #include @@ -641,20 +642,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -663,20 +653,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { uma_memory_size = 512 << ONE_MB_SHIFT; } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { uma_memory_size = 256 << ONE_MB_SHIFT; } else { uma_memory_size = 64 << ONE_MB_SHIFT; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -696,6 +684,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 15b29f6..386a369 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -851,22 +851,9 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - + uint32_t topmem = (uint32_t) bsp_topmem(); /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -880,11 +867,9 @@ static void setup_uma_memory(void) break; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -903,6 +888,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index bec02f0..29f4709 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -826,21 +826,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); + uint32_t topmem = (uint32_t) bsp_topmem(); #if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x2000000; /* 32M recommended UMA */ break; @@ -859,7 +849,7 @@ static void setup_uma_memory(void) } #else /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -874,11 +864,9 @@ static void setup_uma_memory(void) } #endif - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -896,6 +884,7 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if 0 From gerrit at coreboot.org Thu Aug 2 08:23:26 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 08:23:26 +0200 Subject: [coreboot] New patch to review for coreboot: f6a4652 RTC: Add a routine to check if the CMOS date is valid If the CMOS is cleared or someone writes some random date/time on purpose, the CMOS date register has a invalid date. This will hurts some OS, like Windows 7, which hangs at MS logo forever. When we detect that, we need to write a reasonable date in CMOS. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1389 -gerrit commit f6a465239a81ea8e983855e832652b44f5353071 Author: zbao Date: Thu Aug 2 16:07:40 2012 +0800 RTC: Add a routine to check if the CMOS date is valid If the CMOS is cleared or someone writes some random date/time on purpose, the CMOS date register has a invalid date. This will hurts some OS, like Windows 7, which hangs at MS logo forever. When we detect that, we need to write a reasonable date in CMOS. Change-Id: Ic1c7a2d60e711265686441c77bdf7891a7efb42e Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/drivers/pc80/mc146818rtc.c | 40 +++++++++++++++++++++++++++++++++------- src/include/pc80/mc146818rtc.h | 2 ++ 2 files changed, 35 insertions(+), 7 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 99d670d..af5b9e2 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -148,13 +148,13 @@ void rtc_init(int invalid) if (cmos_invalid) { /* Now setup a default date of Sat 1 January 2000 */ - cmos_write(0, 0x00); /* seconds */ - cmos_write(0, 0x02); /* minutes */ - cmos_write(1, 0x04); /* hours */ - cmos_write(7, 0x06); /* day of week */ - cmos_write(1, 0x07); /* day of month */ - cmos_write(1, 0x08); /* month */ - cmos_write(0, 0x09); /* year */ + cmos_write(0, RTC_CLK_SECOND); + cmos_write(0, RTC_CLK_MINUTE); + cmos_write(1, RTC_CLK_HOUR); + cmos_write(7, RTC_CLK_DAYOFWEEK); + cmos_write(1, RTC_CLK_DAYOFMONTH); + cmos_write(1, RTC_CLK_MINUTE); + cmos_write(0, RTC_CLK_YEAR); } #endif } @@ -338,3 +338,29 @@ int set_option(const char *name, void *value) return 0; } #endif /* CONFIG_USE_OPTION_TABLE */ + +/* + * If the CMOS is cleared, the rtc_reg has the invalid date. That + * hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need + * to make sure the date is valid. + */ +void rtc_check_update_coms_date(u8 has_century) +{ + u8 year; + + /* Note: We need to check if the hardware supports RTC_CLK_ALTCENTURY. */ + year = cmos_read(RTC_CLK_YEAR); + + /* TODO: So far rtc_year is the only entry to check if the date is valid. */ + if (year > 0x99) { /* Invalid date */ + /* Now setup a default date of Sat 1 January 2000 */ + cmos_write(0, RTC_CLK_SECOND); + cmos_write(0, RTC_CLK_MINUTE); + cmos_write(1, RTC_CLK_HOUR); + cmos_write(7, RTC_CLK_DAYOFWEEK); + cmos_write(1, RTC_CLK_DAYOFMONTH); + cmos_write(1, RTC_CLK_MINUTE); + cmos_write(0, RTC_CLK_YEAR); + has_century ? cmos_write(0x20, RTC_CLK_ALTCENTURY) : NULL; + } +} diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 9f18ba4..2d93b6f 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -87,6 +87,7 @@ #define RTC_CLK_DAYOFMONTH 7 #define RTC_CLK_MONTH 8 #define RTC_CLK_YEAR 9 +#define RTC_CLK_ALTCENTURY 0x32 /* On PCs, the checksum is built only over bytes 16..45 */ #define PC_CKS_RANGE_START 16 @@ -136,6 +137,7 @@ static inline void cmos_write32(u8 offset, u32 value) #if !defined(__ROMCC__) void rtc_init(int invalid); +void rtc_check_update_coms_date(u8 has_century); #if CONFIG_USE_OPTION_TABLE int set_option(const char *name, void *val); int get_option(void *dest, const char *name); From gerrit at coreboot.org Thu Aug 2 08:23:27 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 08:23:27 +0200 Subject: [coreboot] New patch to review for coreboot: 3bfaab1 AMD hudson: Call the rtc update if needed. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1390 -gerrit commit 3bfaab18c4dec160856b8a53ec867d0a195484cf Author: zbao Date: Thu Aug 2 16:08:38 2012 +0800 AMD hudson: Call the rtc update if needed. Change-Id: I5e427cfb42430ebebdb4c1e48bd25860c0fec45f Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/southbridge/amd/agesa/hudson/lpc.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 4dd6083..708d1ea 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -67,6 +67,8 @@ static void lpc_init(device_t dev) byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); + + rtc_check_update_coms_date(1); } static void hudson_lpc_read_resources(device_t dev) From gerrit at coreboot.org Thu Aug 2 08:26:07 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 08:26:07 +0200 Subject: [coreboot] Patch set updated for coreboot: 746a8ba RTC: Add a routine to check if the CMOS date is valid References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1389 -gerrit commit 746a8bab1c1c108769315d794b17ae2c7f70ed75 Author: zbao Date: Thu Aug 2 16:07:40 2012 +0800 RTC: Add a routine to check if the CMOS date is valid If the CMOS is cleared or someone writes some random date/time on purpose, the CMOS date register has a invalid date. This will hurts some OS, like Windows 7, which hangs at MS logo forever. When we detect that, we need to write a reasonable date in CMOS. Change-Id: Ic1c7a2d60e711265686441c77bdf7891a7efb42e Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/drivers/pc80/mc146818rtc.c | 40 +++++++++++++++++++++++++++++++++------- src/include/pc80/mc146818rtc.h | 2 ++ 2 files changed, 35 insertions(+), 7 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 99d670d..af5b9e2 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -148,13 +148,13 @@ void rtc_init(int invalid) if (cmos_invalid) { /* Now setup a default date of Sat 1 January 2000 */ - cmos_write(0, 0x00); /* seconds */ - cmos_write(0, 0x02); /* minutes */ - cmos_write(1, 0x04); /* hours */ - cmos_write(7, 0x06); /* day of week */ - cmos_write(1, 0x07); /* day of month */ - cmos_write(1, 0x08); /* month */ - cmos_write(0, 0x09); /* year */ + cmos_write(0, RTC_CLK_SECOND); + cmos_write(0, RTC_CLK_MINUTE); + cmos_write(1, RTC_CLK_HOUR); + cmos_write(7, RTC_CLK_DAYOFWEEK); + cmos_write(1, RTC_CLK_DAYOFMONTH); + cmos_write(1, RTC_CLK_MINUTE); + cmos_write(0, RTC_CLK_YEAR); } #endif } @@ -338,3 +338,29 @@ int set_option(const char *name, void *value) return 0; } #endif /* CONFIG_USE_OPTION_TABLE */ + +/* + * If the CMOS is cleared, the rtc_reg has the invalid date. That + * hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need + * to make sure the date is valid. + */ +void rtc_check_update_coms_date(u8 has_century) +{ + u8 year; + + /* Note: We need to check if the hardware supports RTC_CLK_ALTCENTURY. */ + year = cmos_read(RTC_CLK_YEAR); + + /* TODO: So far rtc_year is the only entry to check if the date is valid. */ + if (year > 0x99) { /* Invalid date */ + /* Now setup a default date of Sat 1 January 2000 */ + cmos_write(0, RTC_CLK_SECOND); + cmos_write(0, RTC_CLK_MINUTE); + cmos_write(1, RTC_CLK_HOUR); + cmos_write(7, RTC_CLK_DAYOFWEEK); + cmos_write(1, RTC_CLK_DAYOFMONTH); + cmos_write(1, RTC_CLK_MINUTE); + cmos_write(0, RTC_CLK_YEAR); + has_century ? cmos_write(0x20, RTC_CLK_ALTCENTURY) : NULL; + } +} diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 9f18ba4..2d93b6f 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -87,6 +87,7 @@ #define RTC_CLK_DAYOFMONTH 7 #define RTC_CLK_MONTH 8 #define RTC_CLK_YEAR 9 +#define RTC_CLK_ALTCENTURY 0x32 /* On PCs, the checksum is built only over bytes 16..45 */ #define PC_CKS_RANGE_START 16 @@ -136,6 +137,7 @@ static inline void cmos_write32(u8 offset, u32 value) #if !defined(__ROMCC__) void rtc_init(int invalid); +void rtc_check_update_coms_date(u8 has_century); #if CONFIG_USE_OPTION_TABLE int set_option(const char *name, void *val); int get_option(void *dest, const char *name); From gerrit at coreboot.org Thu Aug 2 08:26:08 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 08:26:08 +0200 Subject: [coreboot] Patch set updated for coreboot: c22db8e AMD hudson: Call the rtc update if needed. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1390 -gerrit commit c22db8e4be7f10668e1ce1c54e86736660fe16c7 Author: zbao Date: Thu Aug 2 16:08:38 2012 +0800 AMD hudson: Call the rtc update if needed. Change-Id: I5e427cfb42430ebebdb4c1e48bd25860c0fec45f Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/southbridge/amd/agesa/hudson/lpc.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 4dd6083..708d1ea 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -67,6 +67,8 @@ static void lpc_init(device_t dev) byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); + + rtc_check_update_coms_date(1); } static void hudson_lpc_read_resources(device_t dev) From gerrit at coreboot.org Thu Aug 2 08:46:34 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 08:46:34 +0200 Subject: [coreboot] Patch set updated for coreboot: 41b3dd0 RTC: Add a routine to check if the CMOS date is valid References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1389 -gerrit commit 41b3dd08ffc03c4b434cad25256b03bfb89a0107 Author: zbao Date: Thu Aug 2 16:30:23 2012 +0800 RTC: Add a routine to check if the CMOS date is valid If the CMOS is cleared or someone writes some random date/time on purpose, the CMOS date register has a invalid date. This will hurts some OS, like Windows 7, which hangs at MS logo forever. When we detect that, we need to write a reasonable date in CMOS. Change-Id: Ic1c7a2d60e711265686441c77bdf7891a7efb42e Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/drivers/pc80/mc146818rtc.c | 42 +++++++++++++++++++++++++++++++++------ src/include/pc80/mc146818rtc.h | 5 ++++ 2 files changed, 40 insertions(+), 7 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 99d670d..60cd14c 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -148,13 +148,13 @@ void rtc_init(int invalid) if (cmos_invalid) { /* Now setup a default date of Sat 1 January 2000 */ - cmos_write(0, 0x00); /* seconds */ - cmos_write(0, 0x02); /* minutes */ - cmos_write(1, 0x04); /* hours */ - cmos_write(7, 0x06); /* day of week */ - cmos_write(1, 0x07); /* day of month */ - cmos_write(1, 0x08); /* month */ - cmos_write(0, 0x09); /* year */ + cmos_write(0, RTC_CLK_SECOND); + cmos_write(0, RTC_CLK_MINUTE); + cmos_write(1, RTC_CLK_HOUR); + cmos_write(7, RTC_CLK_DAYOFWEEK); + cmos_write(1, RTC_CLK_DAYOFMONTH); + cmos_write(1, RTC_CLK_MINUTE); + cmos_write(0, RTC_CLK_YEAR); } #endif } @@ -338,3 +338,31 @@ int set_option(const char *name, void *value) return 0; } #endif /* CONFIG_USE_OPTION_TABLE */ + +/* + * If the CMOS is cleared, the rtc_reg has the invalid date. That + * hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need + * to make sure the date is valid. + */ +void rtc_check_update_coms_date(u8 has_century) +{ + u8 year, century; + + /* Note: We need to check if the hardware supports RTC_CLK_ALTCENTURY. */ + century = has_century ? cmos_read(RTC_CLK_ALTCENTURY) : 0; + year = cmos_read(RTC_CLK_YEAR); + + /* TODO: If century is 0xFF, 100% that the cmos is cleared. + * Other than that, so far rtc_year is the only entry to check if the date is valid. */ + if (century > 0x99 || year > 0x99) { /* Invalid date */ + /* Now setup a default date of Sat 1 January 2000 */ + cmos_write(0, RTC_CLK_SECOND); + cmos_write(0, RTC_CLK_MINUTE); + cmos_write(1, RTC_CLK_HOUR); + cmos_write(7, RTC_CLK_DAYOFWEEK); + cmos_write(1, RTC_CLK_DAYOFMONTH); + cmos_write(1, RTC_CLK_MINUTE); + cmos_write(0, RTC_CLK_YEAR); + has_century ? cmos_write(0x20, RTC_CLK_ALTCENTURY) : NULL; + } +} diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 9f18ba4..58b307e 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -87,6 +87,10 @@ #define RTC_CLK_DAYOFMONTH 7 #define RTC_CLK_MONTH 8 #define RTC_CLK_YEAR 9 +#define RTC_CLK_ALTCENTURY 0x32 + +#define RTC_HAS_ALTCENTURY 1 +#define RTC_HAS_NO_ALTCENTURY 0 /* On PCs, the checksum is built only over bytes 16..45 */ #define PC_CKS_RANGE_START 16 @@ -136,6 +140,7 @@ static inline void cmos_write32(u8 offset, u32 value) #if !defined(__ROMCC__) void rtc_init(int invalid); +void rtc_check_update_coms_date(u8 has_century); #if CONFIG_USE_OPTION_TABLE int set_option(const char *name, void *val); int get_option(void *dest, const char *name); From gerrit at coreboot.org Thu Aug 2 08:46:41 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 08:46:41 +0200 Subject: [coreboot] Patch set updated for coreboot: 4d7572c AMD hudson: Call the rtc update if needed. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1390 -gerrit commit 4d7572ceef76acf9a0a8a71ee62ab495b6277f64 Author: zbao Date: Thu Aug 2 16:32:04 2012 +0800 AMD hudson: Call the rtc update if needed. Parmer and thather hang at windows 7 booting process. Setting the valid date in CMOS can fix that. Change-Id: I5e427cfb42430ebebdb4c1e48bd25860c0fec45f Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/southbridge/amd/agesa/hudson/lpc.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 4dd6083..99204d6 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -67,6 +67,8 @@ static void lpc_init(device_t dev) byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); + + rtc_check_update_coms_date(RTC_HAS_ALTCENTURY); } static void hudson_lpc_read_resources(device_t dev) From gerrit at coreboot.org Thu Aug 2 10:51:56 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 10:51:56 +0200 Subject: [coreboot] Patch set updated for coreboot: d102e6b AMD Thatcher Board based on trinity References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1382 -gerrit commit d102e6b120fb2e4910da565ab293add8d332ab25 Author: zbao Date: Thu Aug 2 18:36:36 2012 +0800 AMD Thatcher Board based on trinity Thatcher features: Family 15 trinity FP2. Hudson. close to Parmer. This board and parmer both need to revert the change http://review.coreboot.org/#/c/1359/, and add thatcher's own chip.h,otherwise the mainboard_enable can not be called. Change-Id: I54e1cfca845fbcea1d3aad5eff08d760d0d215c9 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/thatcher/BiosCallOuts.c | 737 ++++++++++ src/mainboard/amd/thatcher/BiosCallOuts.h | 82 ++ src/mainboard/amd/thatcher/Kconfig | 115 ++ src/mainboard/amd/thatcher/Makefile.inc | 33 + src/mainboard/amd/thatcher/OptionsIds.h | 67 + src/mainboard/amd/thatcher/PlatformGnbPcie.c | 206 +++ .../amd/thatcher/PlatformGnbPcieComplex.h | 72 + src/mainboard/amd/thatcher/acpi/AmdImc.asl | 95 ++ src/mainboard/amd/thatcher/acpi/cpstate.asl | 115 ++ src/mainboard/amd/thatcher/acpi/ide.asl | 244 ++++ src/mainboard/amd/thatcher/acpi/routing.asl | 356 +++++ src/mainboard/amd/thatcher/acpi/sata.asl | 148 ++ src/mainboard/amd/thatcher/acpi/usb.asl | 114 ++ src/mainboard/amd/thatcher/acpi_tables.c | 329 +++++ src/mainboard/amd/thatcher/agesawrapper.c | 775 +++++++++++ src/mainboard/amd/thatcher/agesawrapper.h | 97 ++ src/mainboard/amd/thatcher/buildOpts.c | 513 +++++++ src/mainboard/amd/thatcher/cmos.layout | 114 ++ src/mainboard/amd/thatcher/devicetree.cb | 104 ++ src/mainboard/amd/thatcher/dimmSpd.c | 166 +++ src/mainboard/amd/thatcher/dimmSpd.h | 59 + src/mainboard/amd/thatcher/dsdt.asl | 1421 ++++++++++++++++++++ src/mainboard/amd/thatcher/fadt.c | 202 +++ src/mainboard/amd/thatcher/get_bus_conf.c | 140 ++ src/mainboard/amd/thatcher/irq_tables.c | 112 ++ src/mainboard/amd/thatcher/mainboard.c | 74 + src/mainboard/amd/thatcher/mptable.c | 206 +++ src/mainboard/amd/thatcher/pmio.c | 53 + src/mainboard/amd/thatcher/pmio.h | 33 + src/mainboard/amd/thatcher/reset.c | 64 + src/mainboard/amd/thatcher/romstage.c | 179 +++ 32 files changed, 7028 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index eaaf877..2276129 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -39,6 +39,8 @@ config BOARD_AMD_UNIONSTATION bool "Unionstation" config BOARD_AMD_PARMER bool "Parmer" +config BOARD_AMD_THATCHER + bool "Thatcher" endchoice source "src/mainboard/amd/db800/Kconfig" @@ -59,6 +61,7 @@ source "src/mainboard/amd/south_station/Kconfig" source "src/mainboard/amd/torpedo/Kconfig" source "src/mainboard/amd/union_station/Kconfig" source "src/mainboard/amd/parmer/Kconfig" +source "src/mainboard/amd/thatcher/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c new file mode 100644 index 0000000..34936e0 --- /dev/null +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -0,0 +1,737 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" + +STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GET_IDS_INIT_DATA, + BiosGetIdsInitData + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, + + {AGESA_FCH_OEM_CALLOUT, + Fch_Oem_config + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + break; + } + } + + if(i >= CallOutCount) + { + return AGESA_UNSUPPORTED; + } + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + +CONST IDS_NV_ITEM IdsData[] = +{ + /*{ + AGESA_IDS_NV_MAIN_PLL_CON, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID_EN, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID, + 0x8 + }, + + { + AGESA_IDS_NV_CUSTOM_NB_PSTATE, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL, + }, + { + AGESA_IDS_NV_FORCE_NB_PSTATE, + }, + */ + { + 0xFFFF, + 0xFFFF + } +}; + +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) + +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + IDS_NV_ITEM *IdsPtr; + + IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; + + if (Data == IDS_CALLOUT_INIT) { + for (i = 0; i < NUM_IDS_ENTRIES; i++) { + IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; + IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/** + * AMD Thatcher Platform ALC272 Verb Table + */ +const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, + {0x12, 0x411111F0}, + {0x13, 0x411111F0}, + {0x14, 0x411111F0}, + {0x15, 0x411111F0}, + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, + {0x18, 0x01a19840}, + {0x19, 0x411111F0}, + {0x1a, 0x01813030}, + {0x1b, 0x411111F0}, + {0x1d, 0x40130605}, + {0x1e, 0x01441120}, + {0x21, 0x01211010}, + {0xff, 0xffffffff} +}; + +const CODEC_TBL_LIST ThatcherCodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + +/* Parmer Hardware Monitor Fan Control + * Hardware limitation: + * HWM failed to read the input temperture vi I2C, + * if other software switch the I2C switch by mistake or intention. + * We recommend to using IMC to control Fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + FCH_HWM_FAN_CTR oem_factl[5] = { + /*temperatuer input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ + /* Parmer FanOUT0 Fan header J32 */ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + /* Parmer FanOUT1 Fan header J31*/ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + }; + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + + /* Enable IMC fan control. the recommand way */ +#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + + /* Thermal Zone Parameter */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x35; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0E;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 1; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0; + + /* IMC Fan Policy temperature thresholds */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 105;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 60; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 105; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x54; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 1; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 80; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; + + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 100; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; + + /* IMC Function */ + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; + + /* NOTE: + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, + * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. + * so we remove it from AGESA code. Please Seee FchInitLateHwm. + */ + +#else /* HWM fan control, the way not recommand */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, GEC, IMC etc. + */ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + + if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); + /* Azalia Controller Front Panel OEM Table Pointer */ + + /* Fan Control */ + oem_fan_control(FchParams_env); + + /* XHCI configuration */ + FchParams_env->Usb.Xhci0Enable = FALSE; + FchParams_env->Usb.Xhci1Enable = FALSE; + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.h b/src/mainboard/amd/thatcher/BiosCallOuts.h new file mode 100644 index 0000000..1993c64 --- /dev/null +++ b/src/mainboard/amd/thatcher/BiosCallOuts.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define REQUIRED_CALLOUTS 12 +#define BIOS_HEAP_START_ADDRESS 0x010000000 +#define BIOS_HEAP_SIZE 0x30000 +#define BSP_STACK_BASE_ADDR 0x30000 + + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* FCH OEM Config*/ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig new file mode 100644 index 0000000..82a154b --- /dev/null +++ b/src/mainboard/amd/thatcher/Kconfig @@ -0,0 +1,115 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_THATCHER + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select SUPERIO_SMSC_LPC47N217 + select BOARD_ROMSIZE_KB_4096 + select TINY_BOOTBLOCK + select GFXUMA + select UDELAY_LAPIC + +config MAINBOARD_DIR + string + default amd/thatcher + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Thatcher" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS_ID + string + default "1002,9917" + +config WARNINGS_ARE_ERRORS + bool + default n + +endif # BOARD_AMD_THATCHER diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc new file mode 100644 index 0000000..e345243 --- /dev/null +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c + +ramstage-y += reset.c +ramstage-y += pmio.c diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h new file mode 100644 index 0000000..0a1d328 --- /dev/null +++ b/src/mainboard/amd/thatcher/OptionsIds.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c new file mode 100644 index 0000000..e4308e4 --- /dev/null +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +PCIe_PORT_DESCRIPTOR PortList [] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), + PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ + { + 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + +#if 1 + /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, +#endif +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, +// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) + }, + // GFX Lane 15-12 + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) + }, + // GFX Lane 11-8 + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) + }, + // GFX Lane 7-4 + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) + } +}; + +PCIe_COMPLEX_DESCRIPTOR Trinity = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *TrinityPcieComplexListPtr; + VOID *TrinityPciePortPtr; + VOID *TrinityPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } + + TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (TrinityPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (TrinityPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 7, + &InitEarly->StdHeader); + + LibAmdMemFill (TrinityPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 6, + &InitEarly->StdHeader); + + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; +} diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h b/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..c10d251 --- /dev/null +++ b/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/thatcher/acpi/AmdImc.asl b/src/mainboard/amd/thatcher/acpi/AmdImc.asl new file mode 100644 index 0000000..937c10a --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/AmdImc.asl @@ -0,0 +1,95 @@ +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + While (LNotEqual(Local0, 0xFA)) { + Store(MRG0, Local0) + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/amd/thatcher/acpi/cpstate.asl b/src/mainboard/amd/thatcher/acpi/cpstate.asl new file mode 100644 index 0000000..0747c5c --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/cpstate.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/thatcher/acpi/ide.asl b/src/mainboard/amd/thatcher/acpi/ide.asl new file mode 100644 index 0000000..765a67e --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/thatcher/acpi/routing.asl b/src/mainboard/amd/thatcher/acpi/routing.asl new file mode 100644 index 0000000..cc03701 --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/routing.asl @@ -0,0 +1,356 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 Pcie Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + +#if 0 //parmer not use + Name(PS3, Package(){ + /* The external GFX - Hooked to PCIe slot 3 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS3, Package(){ + /* The external GFX - Hooked to PCIe slot 3 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) +#endif + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 0*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 0*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 1*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 1*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 2*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 2*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 3 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 3*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + /* SB PCI Bridge J21, J22 */ + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, +/* + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, +*/ + }) +} diff --git a/src/mainboard/amd/thatcher/acpi/sata.asl b/src/mainboard/amd/thatcher/acpi/sata.asl new file mode 100644 index 0000000..8fd9e9b --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/sata.asl @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/thatcher/acpi/usb.asl b/src/mainboard/amd/thatcher/acpi/usb.asl new file mode 100644 index 0000000..7780a15 --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi/usb.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + } + } +} diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c new file mode 100644 index 0000000..0a64535 --- /dev/null +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -0,0 +1,329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include +#include + +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 + +static void dump_mem(u32 start, u32 end) +{ + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* Not implemented */ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; /* it will used by fadt */ + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ /* it needs 64 bit alignment */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; /* it will be used by fadt */ + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FADT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *) current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = (current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c new file mode 100644 index 0000000..509f472 --- /dev/null +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -0,0 +1,775 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include +#include +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include +#include +#include +#include + +VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 heap; + +#if CONFIG_HAVE_ACPI_RESUME + /* Both romstage and ramstage has this S3 detect. */ + if (acpi_get_sleep_type() == 3) + heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + else +#endif + heap = BIOS_HEAP_START_ADDRESS; /* Low mem */ + + return heap; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost (PostParams); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct (&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + + status = AmdInitEnv (EnvParam); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate(AmdLateParams); + /* CDIT table is not created. */ + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + /* agesawrapper_amdreadeventlog(); */ + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#if CONFIG_HAVE_ACPI_RESUME == 1 + +UINT32 agesawrapper_amdinitresume(VOID) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; +#if 1 /* TODO: Get the param from Nv storage. */ + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); +#endif + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +#ifndef __PRE_RAM__ + +extern FCH_DATA_BLOCK InitEnvCfgDefault; +STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) +{ + FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; + FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; + FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; + FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; + FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; + FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; + FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; + FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; + FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; + FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ + FchParams->Gpp.GppPhyPllPowerDown = TRUE; + FchParams->Gpp.GppDynamicPowerSaving = TRUE; + FchParams->Gpp.UmiPhyPllPowerDown = TRUE; + FchParams->Gpp.NewGppAlgorithm = TRUE; + FchParams->Gpp.GppPortMinPollingTime = 40; + + FchParams->Spi.SpiSpeed = 2; + FchParams->Ir.IrConfig = 3; + + FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; + FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; + FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; + FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; + FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; + FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; + FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; + FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; + FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; + FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; + FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; + FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; + FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; + FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; + FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; + FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; + FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; + FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; + FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; + FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; + FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; + FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; + FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; + FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; + FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; + FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; + FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; + FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; +} + +UINT32 agesawrapper_fchs3earlyrestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + + FchInitS3EarlyRestore(&FchParams); + + return status; +} +#endif + +UINT32 agesawrapper_amds3laterestore (VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + +#if 1 /* TODO:Get params from Volatile storage. */ + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); +#endif + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#ifndef __PRE_RAM__ + +extern UINT8 picr_data[0x54], intr_data[0x54]; + +UINT32 agesawrapper_fchs3laterestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + UINT8 byte; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + return status; +} +#endif + +#ifndef __PRE_RAM__ + +UINT32 agesawrapper_amdS3Save(VOID) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); +#if 1 /* TODO: Save the params to NvStorage */ + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); +#endif + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + +#if 1 /* TODO: Save the params to VolatileStorage */ + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); +#endif + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} + +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + +UINT32 +agesawrapper_amdreadeventlog ( + UINT8 HeapStatus + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/thatcher/agesawrapper.h b/src/mainboard/amd/thatcher/agesawrapper.h new file mode 100644 index 0000000..db893cd --- /dev/null +++ b/src/mainboard/amd/thatcher/agesawrapper.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitcpuio (void); +void *agesawrapper_getlateinitptr (int pick); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); +UINT32 agesawrapper_amdS3Save(VOID); +UINT32 agesawrapper_amdinitresume(VOID); +UINT32 agesawrapper_amds3laterestore (VOID); + +UINT32 agesawrapper_fchs3earlyrestore (VOID); +UINT32 agesawrapper_fchs3laterestore (VOID); + +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + +#endif diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c new file mode 100644 index 0000000..67e4223 --- /dev/null +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -0,0 +1,513 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + */ + +#include "AGESA.h" +//#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT FALSE +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT TRUE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT TRUE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +#define INSTALL_FM2_SOCKET_SUPPORT FALSE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +//#define BLDOPT_REMOVE_DMI FALSE //TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +// Specify the default values for the VRM controlling the VDDNB plane. +// If not specified, the values used for the core VRM will be applied +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 + +#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 +#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 + +#if CONFIG_GFXUMA +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#endif + +#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList + +//#include "VirgoInstall.h" + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 +#define FCH_NO_XHCI_SUPPORT TRUE +GPIO_CONTROL thatcher_gpio[] = { + {183, Function1, PullUpB}, + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket + // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +// Customer table +UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]); + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout new file mode 100644 index 0000000..f6b5806 --- /dev/null +++ b/src/mainboard/amd/thatcher/cmos.layout @@ -0,0 +1,114 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb new file mode 100644 index 0000000..2a91e1a --- /dev/null +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -0,0 +1,104 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family15tn/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 on end # PCIE SLOT0 x16 + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end + end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/lpc47n217 + device pnp 2e.3 off # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end #superio/smsc/lpc47n217 + end + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 +# device pci 14.6 on end # Gec + device pci 14.7 on end + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 +# device pci 16.0 off end # XHCI0 Hudson2 only +# device pci 16.2 off end # XHCI1 Hudson2 only + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + end #southbridge/amd/hudson +# device pci 18.0 on end + #device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/thatcher/dimmSpd.c b/src/mainboard/amd/thatcher/dimmSpd.c new file mode 100644 index 0000000..29d6a29 --- /dev/null +++ b/src/mainboard/amd/thatcher/dimmSpd.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "dimmSpd.h" + +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*#pragma optimize ("", off) // for source level debug + *--------------------------------------------------------------------------- + * + * SPD address table - porting required + */ + +static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm +{ + // socket 0 + { + {0xA0, 0x00}, // channel 0 dimms + {0xA2, 0x00}, // channel 1 dimms + }, + // socket 1 + { + {0x00, 0x00}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, +}; + +/*----------------------------------------------------------------------------- + * + * readSmbusByteData - read a single SPD byte from any offset + */ + +static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +{ + unsigned int status; + UINT64 limit; + + address |= 1; // set read bit + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command + + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} + +/*----------------------------------------------------------------------------- + * + * readSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + */ + +static int readSmbusByte (int iobase, int address, char *buffer) +{ + unsigned int status; + UINT64 limit; + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} + +/*--------------------------------------------------------------------------- + * + * readspd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ + +static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +{ + int index, error; + + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; + + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) + { + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } + + return 0; +} + +static void writePmReg (int reg, int data) +{ + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); +} + +static void setupFch (int ioBase) +{ + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + //writePmReg (0x29, 0x80); + //writePmReg (0x28, 0x61); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz +} + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) +{ + int spdAddress, ioBase; + + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + ioBase = 0xB00; + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); +} diff --git a/src/mainboard/amd/thatcher/dimmSpd.h b/src/mainboard/amd/thatcher/dimmSpd.h new file mode 100644 index 0000000..c19cecc --- /dev/null +++ b/src/mainboard/amd/thatcher/dimmSpd.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl new file mode 100644 index 0000000..e0cc3fd --- /dev/null +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -0,0 +1,1421 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "PARMER ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0xEE), + UPWS, 3, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + Scope(\_SB) { + /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + //Store(0, PIRA) + //Store(0, PIRB) + //Store(0, PIRC) + //Store(0, PIRD) + //Store(0, PIRE) + //Store(0, PIRF) + //Store(0, PIRG) + //Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + //Store(0x1F, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + //Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + //Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + //Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + //Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + //Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + //Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + //Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + //Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + //Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + //if (LEqual(Arg0,3)){ + // Store(0,URRE) + //} + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + //Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + //if (LEqual(Arg0,3)){ + // Store(1,URRE) + //} + + /* Arbitrarily clear PciExpWakeStatus */ + //Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + //#include "acpi/usb.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices Dev0 ,Func0*/ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + +#if 0 //not used in Parmer + /* Dev3 is also an external GFX bridge */ + Device(PBR3) { + Name(_ADR, 0x00030000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR3 */ +#endif + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + //#include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + Name(_PRW, Package() {0x0B, 4}) + } /* end XHC0 */ + Device(XHC1) { + Name(_ADR, 0x00100001) + Name(_PRW, Package() {0x0B, 4}) + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + //#include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x03B0, /* range minimum */ + 0x03DF, /* range maximum */ + 0x0000, /* translation */ + 0x0030 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + /* TODO: It is unstable. */ + //#include "acpi/AmdImc.asl" /* Hudson IMC function */ + //ITZE() /* enable IMC Fan Control*/ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ +} +/* End of ASL file */ diff --git a/src/mainboard/amd/thatcher/fadt.c b/src/mainboard/amd/thatcher/fadt.c new file mode 100644 index 0000000..b72208c --- /dev/null +++ b/src/mainboard/amd/thatcher/fadt.c @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include +#include +#include +#include +#include +#include "pmio.h" + +/*extern*/ u16 pm_base = 0x800; +/* pm_base should be set in sb acpi */ +/* pm_base should be got from bar2 of sb800. Here I compact ACPI + * registers into 32 bytes limit. + * */ + +#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */ +#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */ +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + pm_base &= 0xFFFF; + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + #if 1 + pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); + pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); + pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); + pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); + pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); + pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); + pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); + pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF); + pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8); + + pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ + pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ + + pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); + pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); + #endif + + pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses + * the contents of the PM registers at + * index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;//0xFE00;// + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5 | 1 << 10;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;//0xFE00;//ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c new file mode 100644 index 0000000..ad5e1d7 --- /dev/null +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_sb800[3]; +u32 apicid_sb800; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_sb800; + +static u32 get_bus_conf_done = 0; + +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } + } +#else + status = agesawrapper_amdinitlate(); + if (status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); +#endif + + sbdn_sb800 = 0; + + for (i = 0; i < 3; i++) { + bus_sb800[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + + /* sb800 */ + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + + if (dev) { + bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb800[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + if (dev) { + bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sb800[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_sb800 = apicid_base; +} diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c new file mode 100644 index 0000000..3bcd3fb --- /dev/null +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern u8 bus_isa; +extern u8 bus_sb800[2]; +extern unsigned long sbdn_sb800; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb800[0]; + pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c new file mode 100644 index 0000000..b2a01d4 --- /dev/null +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "BiosCallOuts.h" +#include +#include "agesawrapper.h" + +/************************************************* + * enable the dedicated function in thatcher board. + *************************************************/ +static void thatcher_enable(device_t dev) +{ + msr_t msr; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + msr = rdmsr(0xC0011020); + msr.lo &= ~(1 << 28); + wrmsr(0xC0011020, msr); + + msr = rdmsr(0xC0011022); + msr.lo &= ~(1 << 4); + msr.lo &= ~(1 << 13); + wrmsr(0xC0011022, msr); + + msr = rdmsr(0xC0011023); + msr.lo &= ~(1 << 23); + wrmsr(0xC0011023, msr); + + /* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); + if (acpi_slp_type == 3) + agesawrapper_fchs3earlyrestore(); + +#endif +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = thatcher_enable, +}; diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c new file mode 100644 index 0000000..329f731 --- /dev/null +++ b/src/mainboard/amd/thatcher/mptable.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "pmio.h" +#include +#include + +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +#define IO_APIC_ID CONFIG_MAX_CPUS +extern u8 bus_sb800[3]; + +extern u32 bus_type[256]; +extern u32 sbdn_sb800; +extern u32 apicid_sb800; + +u8 picr_data[] = { + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 dword; + u8 byte; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + get_bus_conf(); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + + dword = 0; + dword = pm_ioread(0x34) & 0xF0; + dword |= (pm_ioread(0x35) & 0xFF) << 8; + dword |= (pm_ioread(0x36) & 0xFF) << 16; + dword |= (pm_ioread(0x37) & 0xFF) << 24; + /* Set IO APIC ID onto IO_APIC_ID */ + write32 (dword, 0x00); + write32 (dword + 0x10, IO_APIC_ID << 24); + apicid_sb800 = IO_APIC_ID; + smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); + PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); + PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/thatcher/pmio.c b/src/mainboard/amd/thatcher/pmio.c new file mode 100644 index 0000000..a8f1d3d --- /dev/null +++ b/src/mainboard/amd/thatcher/pmio.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include /*inb, outb*/ +#include "pmio.h" + +static void pmio_write_index(u16 port_base, u8 reg, u8 value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static u8 pmio_read_index(u16 port_base, u8 reg) +{ + outb(reg, port_base); + return inb(port_base + 1); +} + +void pm_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM_INDEX, reg, value); +} + +u8 pm_ioread(u8 reg) +{ + return pmio_read_index(PM_INDEX, reg); +} + +void pm2_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM2_INDEX, reg, value); +} + +u8 pm2_ioread(u8 reg) +{ + return pmio_read_index(PM2_INDEX, reg); +} diff --git a/src/mainboard/amd/thatcher/pmio.h b/src/mainboard/amd/thatcher/pmio.h new file mode 100644 index 0000000..bc15fd9 --- /dev/null +++ b/src/mainboard/amd/thatcher/pmio.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PMIO_H_ +#define _PMIO_H_ + +#define PM_INDEX 0xCD6 +#define PM_DATA 0xCD7 +#define PM2_INDEX 0xCD0 +#define PM2_DATA 0xCD1 + +void pm_iowrite(u8 reg, u8 value); +u8 pm_ioread(u8 reg); +void pm2_iowrite(u8 reg, u8 value); +u8 pm2_ioread(u8 reg); + +#endif diff --git a/src/mainboard/amd/thatcher/reset.c b/src/mainboard/amd/thatcher/reset.c new file mode 100644 index 0000000..5735fa2 --- /dev/null +++ b/src/mainboard/amd/thatcher/reset.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c new file mode 100644 index 0000000..f7ffa4e --- /dev/null +++ b/src/mainboard/amd/thatcher/romstage.c @@ -0,0 +1,179 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "southbridge/amd/agesa/hudson/hudson.h" +#include "src/superio/smsc/lpc47n217/early_serial.c" +#include "cpu/amd/agesa/s3_resume.h" +#include "src/drivers/pc80/i8254.c" +#include "src/drivers/pc80/i8259.c" +#include "cbmem.h" + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void disable_cache_as_ram(void); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + u8 byte; + device_t dev; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + val = agesawrapper_amdinitmmio(); + + hudson_lpc_port80(); + //__asm__ volatile ("1: jmp 1b"); + /* TODO: */ + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + post_code(0x31); + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + outb(0xea, 0xcd6); + outb(0x1, 0xcd7); + *(u8 *)0xfed80101 = 0x98; + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + + post_code(0x38); + printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + + post_code(0x39); + + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + +#if CONFIG_HAVE_ACPI_RESUME + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + disable_cache_as_ram(); + enable_cache(); +#if CONFIG_HAVE_ACPI_RESUME + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = (void *)backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x50); + copy_and_run(0); + + post_code(0x54); /* Should never see this post code. */ +} From gerrit at coreboot.org Thu Aug 2 10:51:56 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 10:51:56 +0200 Subject: [coreboot] Patch set updated for coreboot: 3ae2587 AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1246 -gerrit commit 3ae258787d3392a671a62ca3d94f10dce5eeb4a0 Author: Ky?sti M?lkki Date: Fri Jul 20 08:24:49 2012 +0300 AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base The code in rs690 or rs780 is always used with K8 or AMDFAM10 northbridge. Without GFXUMA, both of these set the same static value indirectly using the variable uma_memory_base. Make the register setting with immediate value, to remove the obscure use of variable uma_memory_base. Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d Signed-off-by: Ky?sti M?lkki --- src/northbridge/amd/amdfam10/northbridge.c | 3 --- src/northbridge/amd/amdk8/northbridge.c | 3 --- src/southbridge/amd/rs690/cmn.c | 6 ++++++ src/southbridge/amd/rs780/cmn.c | 6 ++++++ 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c53da22..68e79ad 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -885,9 +885,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c4a8acd..21f2808 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -879,9 +879,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif } diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 68c46e9..004cf78 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -316,7 +316,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) void rs690_set_tom(device_t nb_dev) { /* set TOM */ +#if CONFIG_GFXUMA pci_write_config32(nb_dev, 0x90, uma_memory_base); nbmc_write_index(nb_dev, 0x1e, uma_memory_base); +#else + /* 1GB system memory supposed */ + pci_write_config32(nb_dev, 0x90, 0x38000000); + nbmc_write_index(nb_dev, 0x1e, 0x38000000); +#endif } diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 5c72a04..30da675 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -357,8 +357,14 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) void rs780_set_tom(device_t nb_dev) { /* set TOM */ +#if CONFIG_GFXUMA pci_write_config32(nb_dev, 0x90, uma_memory_base); //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); +#else + /* 1GB system memory supposed */ + pci_write_config32(nb_dev, 0x90, 0x38000000); + //nbmc_write_index(nb_dev, 0x1e, 0x38000000); +#endif } // extract single bit From gerrit at coreboot.org Thu Aug 2 10:51:57 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 10:51:57 +0200 Subject: [coreboot] Patch set updated for coreboot: a54defe AMD Agesa and GFXUMA: drop use of uma_memory_base References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1247 -gerrit commit a54defe30fa86f01a1b02907594ef4a08217544b Author: Ky?sti M?lkki Date: Fri Jul 20 08:31:37 2012 +0300 AMD Agesa and GFXUMA: drop use of uma_memory_base Without GFXUMA, variables were not referenced anywhere. Fail builds on Family10 if GFXUMA is selected, because the northbridge code does not set UMA base or size. Change-Id: I15b91cf6241e9a890398eed03824b753828a0a51 Signed-off-by: Ky?sti M?lkki --- src/northbridge/amd/agesa/family10/northbridge.c | 4 ++++ src/northbridge/amd/agesa/family12/northbridge.c | 3 --- src/northbridge/amd/agesa/family14/northbridge.c | 3 --- src/northbridge/amd/agesa/family15/northbridge.c | 3 --- src/northbridge/amd/agesa/family15tn/northbridge.c | 3 --- 5 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index c4acedf..831aec0 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -923,6 +923,10 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif +#if CONFIG_GFXUMA +#error Northbridge does not set uma_memory_base or uma_memory_size. +#endif + #if CONFIG_PCI_64BIT_PREF_MEM for (link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index d7458ff..7ac8996 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -508,9 +508,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - uma_memory_base = 0x30000000; /* 1GB system memory supported */ #endif } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index dbc432a..6cdff27 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -553,9 +553,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - uma_memory_base = 0x30000000; /* 1GB system memory supported */ #endif } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 2036dbf..be86fda 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -668,9 +668,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */ - uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */ #endif } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index fc4115e..b572e24 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -677,9 +677,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 256 << ONE_MB_SHIFT; /* 256M recommended UMA */ - uma_memory_base = 768 << ONE_MB_SHIFT; /* 1GB system memory supported */ #endif } From gerrit at coreboot.org Thu Aug 2 10:51:58 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 10:51:58 +0200 Subject: [coreboot] Patch set updated for coreboot: 629ebf4 AMD and GFXUMA: move setup_uma_memory() to northbridge References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1379 -gerrit commit 629ebf423d20fc56c4e8ae1828192162b3bc9b72 Author: Ky?sti M?lkki Date: Thu Jul 19 19:26:43 2012 +0300 AMD and GFXUMA: move setup_uma_memory() to northbridge UMA region can be determined at any time after the amount of RAM is known and before the uma_resource() call. Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e Signed-off-by: Ky?sti M?lkki --- src/include/device/device.h | 1 - src/mainboard/advansus/a785e-i/mainboard.c | 2 -- src/mainboard/amd/bimini_fam10/mainboard.c | 2 -- src/mainboard/amd/dbm690t/mainboard.c | 2 -- src/mainboard/amd/dinar/mainboard.c | 1 - src/mainboard/amd/inagua/mainboard.c | 2 -- src/mainboard/amd/mahogany/mainboard.c | 1 - src/mainboard/amd/mahogany_fam10/mainboard.c | 2 -- src/mainboard/amd/parmer/mainboard.c | 2 -- src/mainboard/amd/persimmon/mainboard.c | 3 --- src/mainboard/amd/pistachio/mainboard.c | 3 --- src/mainboard/amd/south_station/mainboard.c | 2 -- src/mainboard/amd/tilapia_fam10/mainboard.c | 2 -- src/mainboard/amd/torpedo/mainboard.c | 1 - src/mainboard/amd/union_station/mainboard.c | 2 -- src/mainboard/asrock/939a785gmh/mainboard.c | 2 -- src/mainboard/asrock/e350m1/mainboard.c | 1 - src/mainboard/asus/m4a78-em/mainboard.c | 2 -- src/mainboard/asus/m4a785-m/mainboard.c | 2 -- src/mainboard/asus/m5a88-v/mainboard.c | 2 -- src/mainboard/avalue/eax-785e/mainboard.c | 2 -- src/mainboard/gigabyte/ma785gm/mainboard.c | 2 -- src/mainboard/gigabyte/ma785gmt/mainboard.c | 2 -- src/mainboard/gigabyte/ma78gm/mainboard.c | 2 -- src/mainboard/iei/kino-780am2-fam10/mainboard.c | 2 -- src/mainboard/jetway/pa78vm5/mainboard.c | 2 -- src/mainboard/kontron/kt690/mainboard.c | 2 -- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 1 - src/mainboard/technexion/tim5690/mainboard.c | 2 -- src/mainboard/technexion/tim8690/mainboard.c | 2 -- src/northbridge/amd/agesa/family12/northbridge.c | 4 +++- src/northbridge/amd/agesa/family14/northbridge.c | 4 +++- src/northbridge/amd/agesa/family15/northbridge.c | 4 +++- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 +++- src/northbridge/amd/amdfam10/northbridge.c | 4 +++- src/northbridge/amd/amdk8/northbridge.c | 4 +++- 36 files changed, 18 insertions(+), 62 deletions(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index eaf84c6..9e9d000 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -112,7 +112,6 @@ extern struct resource *free_resources; extern struct bus *free_links; /* IGD UMA memory */ -void setup_uma_memory(void); extern uint64_t uma_memory_base; extern uint64_t uma_memory_size; diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 6c190f0..356ea1c 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -78,8 +78,6 @@ static void a785e_i_enable(device_t dev) { printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); enable_int_gfx(); } diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index f587ac1..aecb036 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -128,8 +128,6 @@ static void bimini_enable(device_t dev) { printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); enable_int_gfx(); /* get_ide_dma66(); */ diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index fbff55b..0121879 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -185,8 +185,6 @@ static void dbm690t_enable(device_t dev) { printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev); - setup_uma_memory(); - enable_onboard_nic(); get_ide_dma66(); set_thermal_config(); diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 6301b4f..af70ddc 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -72,7 +72,6 @@ void set_pcie_dereset(void *nbconfig) static void dinar_enable(device_t dev) { printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); - setup_uma_memory(); } int add_mainboard_resources(struct lb_memory *mem) diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index dc83258..9099a4d 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -78,8 +78,6 @@ static void inagua_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - setup_uma_memory(); - /* Inagua mainboard specific setting */ set_pcie_dereset(); } diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 43ea66f..66d0d28 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -101,7 +101,6 @@ u8 is_dev3_present(void) static void mahogany_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); - setup_uma_memory(); set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index b47cdff..d1701fd 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -103,8 +103,6 @@ static void mahogany_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ } diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 0d73a4c..095f02f 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -44,9 +44,7 @@ static void parmer_enable(device_t dev) acpi_slp_type = acpi_get_sleep_type(); if (acpi_slp_type == 3) agesawrapper_fchs3earlyrestore(); - #endif - setup_uma_memory(); } int add_mainboard_resources(struct lb_memory *mem) diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index aa3bc1b..3bf05db 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -64,9 +64,6 @@ static void persimmon_enable(device_t dev) #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); #endif - - setup_uma_memory(); - } int add_mainboard_resources(struct lb_memory *mem) diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 1355c37..32912f4 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -255,10 +255,7 @@ static void pistachio_enable(device_t dev) { printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev); - setup_uma_memory(); - enable_onboard_nic(); - set_thermal_config(); } diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 715b40a..dbfce2b 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -79,8 +79,6 @@ static void southstation_led_init(void) static void southstation_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - setup_uma_memory(); - southstation_led_init(); } diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index cf3e3d3..f655513 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -278,8 +278,6 @@ static void tilapia_enable(device_t dev) { printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ set_thermal_config(); diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 839ec5c..91e3ead 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -56,7 +56,6 @@ void set_pcie_dereset(void) static void torpedo_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); - setup_uma_memory(); } int add_mainboard_resources(struct lb_memory *mem) diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index f0f610a..d8324bc 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -53,8 +53,6 @@ void set_pcie_dereset(void) static void unionstation_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - setup_uma_memory(); } int add_mainboard_resources(struct lb_memory *mem) diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index d3ea27e..7526c6b 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -100,8 +100,6 @@ static void mb_enable(device_t dev) { printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ } diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index d0151be..9a76cce 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -52,7 +52,6 @@ void set_pcie_dereset(void) static void e350m1_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - setup_uma_memory(); } int add_mainboard_resources(struct lb_memory *mem) diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index eea8c0d..738e854 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -122,8 +122,6 @@ static void m4a78em_enable(device_t dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ /* set_thermal_config(); */ diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 45af025..5230f84 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -194,8 +194,6 @@ static void m4a785m_enable(device_t dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ set_thermal_config(); diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 866e8c2..bbb1482 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -79,8 +79,6 @@ static void m5a88pm_v_enable(device_t dev) printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); enable_int_gfx(); } diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 5e50efa..0cc655e 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -78,8 +78,6 @@ static void eax_785e(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - setup_uma_memory(); - set_pcie_dereset(); enable_int_gfx(); } diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 680bb2e..c65fbb6 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -139,8 +139,6 @@ static void ma785gm_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ set_gpio40_gfx(); diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index b7ecf9f..3c26c6a 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -249,8 +249,6 @@ static void ma785gmt_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ set_thermal_config(); diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 6756690..ba9baf4 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -76,8 +76,6 @@ static void ma78gm_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ } diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index e9ef596..44cbfcd 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -58,8 +58,6 @@ static void kino_enable(device_t dev) { printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ } diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index cb37c11..3c4d872 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -105,8 +105,6 @@ static void pa78vm5_enable(device_t dev) { printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); - setup_uma_memory(); - set_pcie_dereset(); /* get_ide_dma66(); */ } diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index dbd4141..4eb638f 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -185,8 +185,6 @@ static void kt690_enable(device_t dev) { printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev); - setup_uma_memory(); - enable_onboard_nic(); get_ide_dma66(); set_thermal_config(); diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 905d23f..e4d88db 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -851,7 +851,6 @@ static void enable_dev(device_t dev) detect_hw_variant(dev); update_subsystemid(dev); - setup_uma_memory(); dev->ops->init = init; // rest of mainboard init later } diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 2975e86..41147cd 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -239,8 +239,6 @@ static void tim5690_enable(device_t dev) vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO; vgabios_init(&vbios_regs); - setup_uma_memory(); - set_thermal_config(); } diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 40ab345..298132b 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -145,8 +145,6 @@ static void tim8690_enable(device_t dev) { printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); - setup_uma_memory(); - enable_onboard_nic(); set_thermal_config(); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 7ac8996..f3f03a4 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -469,7 +469,7 @@ static void set_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - set_resources - End.\n"); } -void setup_uma_memory(void) +static void setup_uma_memory(void) { #if CONFIG_GFXUMA msr_t msr, msr2; @@ -611,6 +611,8 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_uma_memory(); + #if CONFIG_PCI_64BIT_PREF_MEM printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 6cdff27..af6dfcc 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -517,7 +517,7 @@ static void domain_read_resources(device_t dev) #endif } -void setup_uma_memory(void) +static void setup_uma_memory(void) { #if CONFIG_GFXUMA msr_t msr, msr2; @@ -574,6 +574,8 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_uma_memory(); + #if CONFIG_PCI_64BIT_PREF_MEM printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index be86fda..a080293 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -629,7 +629,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) #define ONE_MB 0x100000 -void setup_uma_memory(void) +static void setup_uma_memory(void) { #if CONFIG_GFXUMA msr_t msr, msr2; @@ -686,6 +686,8 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_uma_memory(); + #if CONFIG_PCI_64BIT_PREF_MEM for (link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index b572e24..9a31751 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -638,7 +638,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) #define ONE_MB_SHIFT 20 -void setup_uma_memory(void) +static void setup_uma_memory(void) { #if CONFIG_GFXUMA msr_t msr, msr2; @@ -696,6 +696,8 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_uma_memory(); + #if CONFIG_PCI_64BIT_PREF_MEM for (link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 68e79ad..15b29f6 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -848,7 +848,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) #include #endif -void setup_uma_memory(void) +static void setup_uma_memory(void) { #if CONFIG_GFXUMA msr_t msr, msr2; @@ -903,6 +903,8 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_uma_memory(); + #if CONFIG_PCI_64BIT_PREF_MEM for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 21f2808..bec02f0 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -823,7 +823,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) #include #endif -void setup_uma_memory(void) +static void setup_uma_memory(void) { #if CONFIG_GFXUMA msr_t msr, msr2; @@ -896,6 +896,8 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_uma_memory(); + #if 0 /* Place the IO devices somewhere safe */ io = find_resource(dev, 0); From gerrit at coreboot.org Thu Aug 2 11:18:20 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 11:18:20 +0200 Subject: [coreboot] Patch set updated for coreboot: 31b06e2 RTC: Add a routine to check if the CMOS date is valid References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1389 -gerrit commit 31b06e2259ccfd84e8fe1f5f0bc1b2bcb58c6a28 Author: zbao Date: Thu Aug 2 19:02:26 2012 +0800 RTC: Add a routine to check if the CMOS date is valid If the CMOS is cleared or someone writes some random date/time on purpose, the CMOS date register has a invalid date. This will hurts some OS, like Windows 7, which hangs at MS logo forever. When we detect that, we need to write a reasonable date in CMOS. Alexandru Gagniuc: Hmm, it would be interesting to use the date the coreboot image was built and set that as the default date. At least until time travel is invented. Change-Id: Ic1c7a2d60e711265686441c77bdf7891a7efb42e Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/drivers/pc80/mc146818rtc.c | 43 ++++++++++++++++++++++++++++++++------- src/include/pc80/mc146818rtc.h | 5 ++++ 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 99d670d..cc14a41 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -77,6 +77,20 @@ # define RTC_VRT 0x80 /* valid RAM and time */ /**********************************************************************/ +static void rtc_update_cmos_date(u8 has_century) +{ + /* Now setup a default date of Sat 1 January 2000 */ + /* TODO: Set the time as building time? Is it reasonable? */ + cmos_write(0, RTC_CLK_SECOND); + cmos_write(0, RTC_CLK_MINUTE); + cmos_write(1, RTC_CLK_HOUR); + cmos_write(7, RTC_CLK_DAYOFWEEK); + cmos_write(1, RTC_CLK_DAYOFMONTH); + cmos_write(1, RTC_CLK_MINUTE); + cmos_write(0, RTC_CLK_YEAR); + if (has_century) cmos_write(0x20, RTC_CLK_ALTCENTURY); +} + #if CONFIG_USE_OPTION_TABLE static int rtc_checksum_valid(int range_start, int range_end, int cks_loc) { @@ -147,14 +161,7 @@ void rtc_init(int invalid) } if (cmos_invalid) { - /* Now setup a default date of Sat 1 January 2000 */ - cmos_write(0, 0x00); /* seconds */ - cmos_write(0, 0x02); /* minutes */ - cmos_write(1, 0x04); /* hours */ - cmos_write(7, 0x06); /* day of week */ - cmos_write(1, 0x07); /* day of month */ - cmos_write(1, 0x08); /* month */ - cmos_write(0, 0x09); /* year */ + rtc_update_cmos_date(RTC_HAS_NO_ALTCENTURY); } #endif } @@ -338,3 +345,23 @@ int set_option(const char *name, void *value) return 0; } #endif /* CONFIG_USE_OPTION_TABLE */ + +/* + * If the CMOS is cleared, the rtc_reg has the invalid date. That + * hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need + * to make sure the date is valid. + */ +void rtc_check_update_cmos_date(u8 has_century) +{ + u8 year, century; + + /* Note: We need to check if the hardware supports RTC_CLK_ALTCENTURY. */ + century = has_century ? cmos_read(RTC_CLK_ALTCENTURY) : 0; + year = cmos_read(RTC_CLK_YEAR); + + /* TODO: If century is 0xFF, 100% that the cmos is cleared. + * Other than that, so far rtc_year is the only entry to check if the date is valid. */ + if (century > 0x99 || year > 0x99) { /* Invalid date */ + rtc_update_cmos_date(has_century); + } +} diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 9f18ba4..a916761 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -87,6 +87,10 @@ #define RTC_CLK_DAYOFMONTH 7 #define RTC_CLK_MONTH 8 #define RTC_CLK_YEAR 9 +#define RTC_CLK_ALTCENTURY 0x32 + +#define RTC_HAS_ALTCENTURY 1 +#define RTC_HAS_NO_ALTCENTURY 0 /* On PCs, the checksum is built only over bytes 16..45 */ #define PC_CKS_RANGE_START 16 @@ -136,6 +140,7 @@ static inline void cmos_write32(u8 offset, u32 value) #if !defined(__ROMCC__) void rtc_init(int invalid); +void rtc_check_update_cmos_date(u8 has_century); #if CONFIG_USE_OPTION_TABLE int set_option(const char *name, void *val); int get_option(void *dest, const char *name); From gerrit at coreboot.org Thu Aug 2 11:18:21 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Thu, 2 Aug 2012 11:18:21 +0200 Subject: [coreboot] Patch set updated for coreboot: 13a2dfa AMD hudson: Call the rtc update if needed. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1390 -gerrit commit 13a2dfaa787e56cc159dbbf98c55cafa575177eb Author: zbao Date: Thu Aug 2 19:03:44 2012 +0800 AMD hudson: Call the rtc update if needed. Parmer and thather hang at windows 7 booting process. Setting the valid date in CMOS can fix that. Change-Id: I5e427cfb42430ebebdb4c1e48bd25860c0fec45f Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/southbridge/amd/agesa/hudson/lpc.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 4dd6083..97f27d0 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -67,6 +67,8 @@ static void lpc_init(device_t dev) byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } static void hudson_lpc_read_resources(device_t dev) From gerrit at coreboot.org Thu Aug 2 11:24:36 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 2 Aug 2012 11:24:36 +0200 Subject: [coreboot] New patch to review for coreboot: ccc2f80 Coreboot table cleanup [notformerge] References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1391 -gerrit commit ccc2f808c30389d9f6120c1e5e2a21e58e01307d Author: Ky?sti M?lkki Date: Thu Aug 2 11:52:22 2012 +0300 Coreboot table cleanup [notformerge] Single Jenkins build test to catch flaws and typos. Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Ky?sti M?lkki --- src/Kconfig | 4 ---- src/arch/x86/boot/coreboot_table.c | 9 ++------- src/arch/x86/include/arch/coreboot_tables.h | 7 ------- src/boot/hardwaremain.c | 3 +++ src/include/boot/tables.h | 3 --- src/include/device/device.h | 1 + src/mainboard/advansus/a785e-i/Kconfig | 1 - src/mainboard/advansus/a785e-i/mainboard.c | 6 ------ src/mainboard/amd/bimini_fam10/Kconfig | 1 - src/mainboard/amd/bimini_fam10/mainboard.c | 6 ------ src/mainboard/amd/dbm690t/Kconfig | 1 - src/mainboard/amd/dbm690t/mainboard.c | 6 ------ src/mainboard/amd/dinar/Kconfig | 1 - src/mainboard/amd/dinar/mainboard.c | 5 ----- src/mainboard/amd/inagua/Kconfig | 1 - src/mainboard/amd/inagua/mainboard.c | 5 ----- src/mainboard/amd/mahogany/Kconfig | 1 - src/mainboard/amd/mahogany/mainboard.c | 6 ------ src/mainboard/amd/mahogany_fam10/Kconfig | 1 - src/mainboard/amd/mahogany_fam10/mainboard.c | 6 ------ src/mainboard/amd/parmer/Kconfig | 1 - src/mainboard/amd/parmer/mainboard.c | 5 ----- src/mainboard/amd/persimmon/Kconfig | 1 - src/mainboard/amd/persimmon/mainboard.c | 6 ------ src/mainboard/amd/pistachio/mainboard.c | 6 ------ src/mainboard/amd/south_station/Kconfig | 1 - src/mainboard/amd/south_station/mainboard.c | 5 ----- src/mainboard/amd/tilapia_fam10/Kconfig | 1 - src/mainboard/amd/tilapia_fam10/mainboard.c | 6 ------ src/mainboard/amd/torpedo/Kconfig | 1 - src/mainboard/amd/torpedo/mainboard.c | 5 ----- src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/amd/union_station/mainboard.c | 5 ----- src/mainboard/asrock/939a785gmh/Kconfig | 1 - src/mainboard/asrock/939a785gmh/mainboard.c | 6 ------ src/mainboard/asrock/e350m1/Kconfig | 1 - src/mainboard/asrock/e350m1/mainboard.c | 5 ----- src/mainboard/asus/dsbf/mainboard.c | 2 -- src/mainboard/asus/m2v-mx_se/Kconfig | 1 - src/mainboard/asus/m2v-mx_se/mainboard.c | 6 ------ src/mainboard/asus/m5a88-v/Kconfig | 1 - src/mainboard/asus/m5a88-v/mainboard.c | 6 ------ src/mainboard/asus/mew-am/Kconfig | 1 - src/mainboard/asus/mew-am/mainboard.c | 6 ------ src/mainboard/asus/mew-vm/Kconfig | 1 - src/mainboard/asus/mew-vm/mainboard.c | 6 ------ src/mainboard/avalue/eax-785e/Kconfig | 1 - src/mainboard/avalue/eax-785e/mainboard.c | 6 ------ src/mainboard/ecs/p6iwp-fe/Kconfig | 1 - src/mainboard/ecs/p6iwp-fe/mainboard.c | 6 ------ src/mainboard/getac/p470/mainboard.c | 1 - src/mainboard/gigabyte/ma785gm/Kconfig | 1 - src/mainboard/gigabyte/ma785gm/mainboard.c | 6 ------ src/mainboard/gigabyte/ma785gmt/Kconfig | 1 - src/mainboard/gigabyte/ma785gmt/mainboard.c | 6 ------ src/mainboard/gigabyte/ma78gm/Kconfig | 1 - src/mainboard/gigabyte/ma78gm/mainboard.c | 6 ------ src/mainboard/hp/e_vectra_p2706t/Kconfig | 1 - src/mainboard/hp/e_vectra_p2706t/mainboard.c | 6 ------ src/mainboard/ibase/mb899/mainboard.c | 2 -- src/mainboard/iei/kino-780am2-fam10/Kconfig | 1 - src/mainboard/iei/kino-780am2-fam10/mainboard.c | 6 ------ src/mainboard/intel/d810e2cb/Kconfig | 1 - src/mainboard/intel/d810e2cb/mainboard.c | 6 ------ src/mainboard/intel/d945gclf/mainboard.c | 2 -- src/mainboard/intel/eagleheights/mainboard.c | 7 ------- src/mainboard/intel/emeraldlake2/Kconfig | 1 - src/mainboard/intel/emeraldlake2/chromeos.c | 1 - src/mainboard/intel/emeraldlake2/mainboard.c | 5 ----- src/mainboard/iwave/iWRainbowG6/mainboard.c | 1 - src/mainboard/jetway/pa78vm5/Kconfig | 1 - src/mainboard/jetway/pa78vm5/mainboard.c | 6 ------ src/mainboard/kontron/kt690/Kconfig | 1 - src/mainboard/kontron/kt690/mainboard.c | 6 ------ src/mainboard/lenovo/t60/dock.c | 1 - src/mainboard/lenovo/t60/mainboard.c | 2 -- src/mainboard/lenovo/x60/dock.c | 1 - src/mainboard/lenovo/x60/mainboard.c | 2 -- src/mainboard/mitac/6513wu/Kconfig | 1 - src/mainboard/mitac/6513wu/mainboard.c | 6 ------ src/mainboard/msi/ms6178/Kconfig | 1 - src/mainboard/msi/ms6178/mainboard.c | 6 ------ src/mainboard/nec/powermate2000/Kconfig | 1 - src/mainboard/nec/powermate2000/mainboard.c | 6 ------ src/mainboard/rca/rm4100/Kconfig | 1 - src/mainboard/rca/rm4100/mainboard.c | 7 ------- src/mainboard/roda/rk886ex/mainboard.c | 2 -- src/mainboard/samsung/lumpy/Kconfig | 1 - src/mainboard/samsung/lumpy/chromeos.c | 1 - src/mainboard/samsung/lumpy/mainboard.c | 5 ----- src/mainboard/samsung/stumpy/Kconfig | 1 - src/mainboard/samsung/stumpy/chromeos.c | 1 - src/mainboard/samsung/stumpy/mainboard.c | 5 ----- src/mainboard/siemens/sitemp_g1p1/Kconfig | 1 - src/mainboard/siemens/sitemp_g1p1/mainboard.c | 21 --------------------- src/mainboard/supermicro/h8qgi/mainboard.c | 8 -------- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 8 -------- src/mainboard/supermicro/x7db8/mainboard.c | 2 -- src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim5690/mainboard.c | 4 +--- src/mainboard/technexion/tim8690/mainboard.c | 6 ------ src/mainboard/thomson/ip1000/Kconfig | 1 - src/mainboard/thomson/ip1000/mainboard.c | 7 ------- src/mainboard/via/epia-n/mainboard.c | 19 ------------------- src/northbridge/intel/i5000/northbridge.c | 1 - src/northbridge/intel/i82810/northbridge.c | 1 - src/northbridge/intel/i82830/northbridge.c | 1 - src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/sandybridge/northbridge.c | 1 - src/northbridge/intel/sch/northbridge.c | 1 - src/southbridge/amd/rs690/cmn.c | 1 - src/southbridge/amd/rs690/ht.c | 3 ++- src/southbridge/amd/rs780/cmn.c | 1 - 113 files changed, 9 insertions(+), 382 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 3453614..ccf8665 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -292,10 +292,6 @@ config HIGH_SCRATCH_MEMORY_SIZE hex default 0x0 -config HAVE_MAINBOARD_RESOURCES - bool - default n - config USE_OPTION_TABLE bool default n diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 5b5834a..d056837 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -338,7 +338,7 @@ static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header } #endif -void lb_memory_range(struct lb_memory *mem, +static void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size) { int entries; @@ -503,8 +503,7 @@ static void lb_remove_memory_range(struct lb_memory *mem, } } -/* This function is used in mainboard specific code, too */ -void lb_add_memory_range(struct lb_memory *mem, +static void lb_add_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size) { lb_remove_memory_range(mem, start, size); @@ -667,10 +666,6 @@ unsigned long write_coreboot_table( /* Add reserved regions */ add_lb_reserved(mem); -#if CONFIG_HAVE_MAINBOARD_RESOURCES - add_mainboard_resources(mem); -#endif - lb_dump_memory_ranges(mem); /* Note: diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h index b177949..e9790db 100644 --- a/src/arch/x86/include/arch/coreboot_tables.h +++ b/src/arch/x86/include/arch/coreboot_tables.h @@ -8,18 +8,11 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -void lb_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - /* Routines to extract part so the coreboot table or information * from the coreboot table. */ struct lb_memory *get_lb_mem(void); -/* defined by mainboard.c if the mainboard requires extra resources */ -int add_mainboard_resources(struct lb_memory *mem); -int add_northbridge_resources(struct lb_memory *mem); - void fill_lb_gpios(struct lb_gpios *gpios); #endif /* COREBOOT_TABLE_H */ diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index bb7f264..57a01f0 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -150,6 +150,9 @@ void hardwaremain(int boot_complete) if (! payload) die("Could not find a payload\n"); + if (mainboard_coreboot_completed) + mainboard_coreboot_completed(); + printk(BIOS_DEBUG, "Got a payload\n"); /* Before we go off to run the payload, see if * we stayed within our bounds. diff --git a/src/include/boot/tables.h b/src/include/boot/tables.h index 4b3f70c..869da26 100644 --- a/src/include/boot/tables.h +++ b/src/include/boot/tables.h @@ -4,9 +4,6 @@ #include #include -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - struct lb_memory *write_tables(void); #endif /* BOOT_TABLES_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index eaf84c6..ceae6aa 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -123,6 +123,7 @@ void dev_configure(void); void dev_enable(void); void dev_initialize(void); void dev_optimize(void); +void __attribute__((weak)) mainboard_coreboot_completed(void); /* Generic device helper functions */ int reset_bus(struct bus *bus); diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 7f1d136..327a84c 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 6c190f0..66627dc 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -84,11 +83,6 @@ static void a785e_i_enable(device_t dev) enable_int_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("ADVANSUS A785E-I Mainboard") .enable_dev = a785e_i_enable, diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 06ed977..e38fc50 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select GENERATE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index f587ac1..125d316 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -135,11 +134,6 @@ static void bimini_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD Bimini Mainboard") .enable_dev = bimini_enable, diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index d1bf72f..9f0afa1 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index fbff55b..1f3e3f2 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -192,11 +191,6 @@ static void dbm690t_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD DBM690T Mainboard") .enable_dev = dbm690t_enable, diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index c81ccfa..1c123ec 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -38,7 +38,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select HAVE_ACPI_TABLES #TODO select HAVE_ACPI_RESUME diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 6301b4f..e9d9b93 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -75,10 +74,6 @@ static void dinar_enable(device_t dev) setup_uma_memory(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("AMD DINAR Mainboard") .enable_dev = dinar_enable, diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index a9c2de4..d2c42f4 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index dc83258..41f3533 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -84,10 +83,6 @@ static void inagua_enable(device_t dev) set_pcie_dereset(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = inagua_enable, diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 7c91b7d..20fc190 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG select LIFT_BSP_APIC_ID select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 43ea66f..242b618 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -107,11 +106,6 @@ static void mahogany_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD MAHOGANY Mainboard") .enable_dev = mahogany_enable, diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index 8343fca..eed5ab2 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index b47cdff..d0bf907 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -109,11 +108,6 @@ static void mahogany_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD MAHOGANY Mainboard") .enable_dev = mahogany_enable, diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 3212c44..a5a875f 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 0d73a4c..738ecc0 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -49,10 +48,6 @@ static void parmer_enable(device_t dev) setup_uma_memory(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = parmer_enable, diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index e1f43b1..714d1fa 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index aa3bc1b..2e015da 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -69,11 +68,6 @@ static void persimmon_enable(device_t dev) } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 1355c37..c2db3d7 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -262,11 +261,6 @@ static void pistachio_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD Pistachio Mainboard") .enable_dev = pistachio_enable, diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index c482ab0..19b295b 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 715b40a..2e6ff5a 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -84,10 +83,6 @@ static void southstation_enable(device_t dev) southstation_led_init(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = southstation_enable, diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index 2c29f45..75e22b3 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index cf3e3d3..ea3fe79 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -286,11 +285,6 @@ static void tilapia_enable(device_t dev) set_gpio40_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD TILAPIA Mainboard") .enable_dev = tilapia_enable, diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index bc4030c..9be8df2 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 839ec5c..399c9bc 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -59,10 +58,6 @@ static void torpedo_enable(device_t dev) setup_uma_memory(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = torpedo_enable, diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index e7c2150..73f4839 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index f0f610a..dc3aecc 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -57,10 +56,6 @@ static void unionstation_enable(device_t dev) setup_uma_memory(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = unionstation_enable, diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index 245b845..2c23d45 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_MP_TABLE select HAVE_PIRQ_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select LIFT_BSP_APIC_ID diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index d3ea27e..577677f 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -106,11 +105,6 @@ static void mb_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("Asrock 939A785GMH/128M Mainboard") .enable_dev = mb_enable, diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 6f4ce0f..60de486 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index d0151be..01d1c5e 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -55,10 +54,6 @@ static void e350m1_enable(device_t dev) setup_uma_memory(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = e350m1_enable, diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c index 618eca9..e4057e5 100644 --- a/src/mainboard/asus/dsbf/mainboard.c +++ b/src/mainboard/asus/dsbf/mainboard.c @@ -22,9 +22,7 @@ #include #include #include -#include #include -#include #include #include #include diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 72fa803..de5511e 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select VGA select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select QRANK_DIMM_SUPPORT select SET_FIDVID # TODO test on multicore machines and enable if it works: diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c index 5e3c720..4cb562b 100644 --- a/src/mainboard/asus/m2v-mx_se/mainboard.c +++ b/src/mainboard/asus/m2v-mx_se/mainboard.c @@ -20,14 +20,8 @@ #include #include #include -#include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("ASUS M2V-MX SE Mainboard") }; diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 9cadcde..86fe51a 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 866e8c2..f24f80d 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -85,11 +84,6 @@ static void m5a88pm_v_enable(device_t dev) enable_int_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("ASUS M5A88-V Mainboard") .enable_dev = m5a88pm_v_enable, diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig index 68ac160..fe90d22 100644 --- a/src/mainboard/asus/mew-am/Kconfig +++ b/src/mainboard/asus/mew-am/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/asus/mew-am/mainboard.c b/src/mainboard/asus/mew-am/mainboard.c index 6409dab..09b6533 100644 --- a/src/mainboard/asus/mew-am/mainboard.c +++ b/src/mainboard/asus/mew-am/mainboard.c @@ -19,12 +19,6 @@ */ #include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("ASUS MEW-AM Mainboard") diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig index 4e46192..21b7311 100644 --- a/src/mainboard/asus/mew-vm/Kconfig +++ b/src/mainboard/asus/mew-vm/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/asus/mew-vm/mainboard.c b/src/mainboard/asus/mew-vm/mainboard.c index 2e43be2..6705927 100644 --- a/src/mainboard/asus/mew-vm/mainboard.c +++ b/src/mainboard/asus/mew-vm/mainboard.c @@ -1,10 +1,4 @@ #include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("ASUS MEW-VM Mainboard") diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index aabd724..2b4182b 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 5e50efa..42b3cb4 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -84,11 +83,6 @@ static void eax_785e(device_t dev) enable_int_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = eax_785e, diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index 7d377f4..95bd1c5 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/ecs/p6iwp-fe/mainboard.c b/src/mainboard/ecs/p6iwp-fe/mainboard.c index 667ac5e..c576e47 100644 --- a/src/mainboard/ecs/p6iwp-fe/mainboard.c +++ b/src/mainboard/ecs/p6iwp-fe/mainboard.c @@ -19,12 +19,6 @@ */ #include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("ECS P6IWP-Fe Mainboard") diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 83b4718..1c408db 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include "hda_verb.h" diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index 0e8011b..f4603f8 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 680bb2e..d160c06 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -146,11 +145,6 @@ static void ma785gm_enable(device_t dev) set_gpio40_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE MA785GM-US2H Mainboard") .enable_dev = ma785gm_enable, diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 0605a39..ebe1e57 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index b7ecf9f..cdfa191 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -257,11 +256,6 @@ static void ma785gmt_enable(device_t dev) set_gpio40_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE MA785GMT-UD2H Mainboard") .enable_dev = ma785gmt_enable, diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index 1b6966e..dcba4af 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 6756690..cb706e4 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -82,11 +81,6 @@ static void ma78gm_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE MA78GM-US2H") .enable_dev = ma78gm_enable, diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index 5fab95a..18ff961 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/hp/e_vectra_p2706t/mainboard.c b/src/mainboard/hp/e_vectra_p2706t/mainboard.c index 80e6f61..aa9cc7a 100644 --- a/src/mainboard/hp/e_vectra_p2706t/mainboard.c +++ b/src/mainboard/hp/e_vectra_p2706t/mainboard.c @@ -19,12 +19,6 @@ */ #include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("HP e-Vectra P2706T Mainboard") diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index 4e3d606..086d456 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -20,13 +20,11 @@ #include #include #include -#include #if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include #endif #include #include -#include #if CONFIG_PCI_OPTION_ROM_RUN_YABEL static int int15_handler(void) diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index 01a2429..73279bc 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index e9ef596..5f9eea2 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -64,11 +63,6 @@ static void kino_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("IEI Kino-780AM2 Mainboard") .enable_dev = kino_enable, diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig index 8c6c76b..0725c58 100644 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ b/src/mainboard/intel/d810e2cb/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select USE_WATCHDOG_ON_BOOT select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/intel/d810e2cb/mainboard.c b/src/mainboard/intel/d810e2cb/mainboard.c index 8455377..bf2c902 100644 --- a/src/mainboard/intel/d810e2cb/mainboard.c +++ b/src/mainboard/intel/d810e2cb/mainboard.c @@ -18,12 +18,6 @@ */ #include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("Intel D810E2CB Mainboard") diff --git a/src/mainboard/intel/d945gclf/mainboard.c b/src/mainboard/intel/d945gclf/mainboard.c index ca920bc..2e25fa3 100644 --- a/src/mainboard/intel/d945gclf/mainboard.c +++ b/src/mainboard/intel/d945gclf/mainboard.c @@ -19,8 +19,6 @@ #include #include -#include -#include struct chip_operations mainboard_ops = { CHIP_NAME("Intel D945GCLF Mainboard") diff --git a/src/mainboard/intel/eagleheights/mainboard.c b/src/mainboard/intel/eagleheights/mainboard.c index d6bc10f..dbe76b2 100644 --- a/src/mainboard/intel/eagleheights/mainboard.c +++ b/src/mainboard/intel/eagleheights/mainboard.c @@ -21,13 +21,6 @@ #include -#include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("Intel Eagle Heights Mainboard") diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 873d273..aaca694 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 850af7b..6077ac7 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -29,7 +29,6 @@ #include #ifndef __PRE_RAM__ -#include #include #define GPIO_COUNT 5 diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 796f71e..71832e7 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -42,11 +42,6 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - #if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE static int int15_handler(struct eregs *regs) { diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c index f3fc20f..38847e2 100644 --- a/src/mainboard/iwave/iWRainbowG6/mainboard.c +++ b/src/mainboard/iwave/iWRainbowG6/mainboard.c @@ -20,7 +20,6 @@ #include #include -#include #include "hda_verb.h" static void verb_setup(void) diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index fa39039..08f4355 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index cb37c11..12e68b0 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -111,11 +110,6 @@ static void pa78vm5_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD PA78VM5 Mainboard") .enable_dev = pa78vm5_enable, diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 6a1909f..bac8b60 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select GFXUMA select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index dbd4141..be75ab0 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -192,11 +191,6 @@ static void kt690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("Kontron KT690/mITX Mainboard") .enable_dev = kt690_enable, diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 5cd8997..426286d 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include "dock.h" diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index bd4c4a7..6f00069 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -23,9 +23,7 @@ #include #include #include -#include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index 37d5b76..1b15a6c 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include "dock.h" diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 4ded239..e28fa10 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -23,9 +23,7 @@ #include #include #include -#include #include -#include #include #include #include diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index fac565e..f09f54f 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/mitac/6513wu/mainboard.c b/src/mainboard/mitac/6513wu/mainboard.c index 04af449..e9d80c4 100644 --- a/src/mainboard/mitac/6513wu/mainboard.c +++ b/src/mainboard/mitac/6513wu/mainboard.c @@ -19,12 +19,6 @@ */ #include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("Mitac 6513WU Mainboard") diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig index 1d45464..38ca830 100644 --- a/src/mainboard/msi/ms6178/Kconfig +++ b/src/mainboard/msi/ms6178/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/msi/ms6178/mainboard.c b/src/mainboard/msi/ms6178/mainboard.c index 76c8c04..009c134 100644 --- a/src/mainboard/msi/ms6178/mainboard.c +++ b/src/mainboard/msi/ms6178/mainboard.c @@ -19,12 +19,6 @@ */ #include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS-6178 Mainboard") diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index 55050c0..8c2070a 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/nec/powermate2000/mainboard.c b/src/mainboard/nec/powermate2000/mainboard.c index 3bbaa11..1536b70 100644 --- a/src/mainboard/nec/powermate2000/mainboard.c +++ b/src/mainboard/nec/powermate2000/mainboard.c @@ -19,12 +19,6 @@ */ #include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("NEC PowerMate 2000 Mainboard") diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig index 1e4498a..5247a8c 100644 --- a/src/mainboard/rca/rm4100/Kconfig +++ b/src/mainboard/rca/rm4100/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 - select HAVE_MAINBOARD_RESOURCES select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index ff98977..29885b0 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -19,13 +19,6 @@ */ #include -#include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} static void mainboard_init(device_t dev) { diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 1f4ebc7..e2ca2ef 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -23,12 +23,10 @@ #include #include #include -#include #include #if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include #endif -#include #include #include "m3885.h" diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 0835012..86cb31b 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select HAVE_MAINBOARD_RESOURCES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MMCONF_SUPPORT diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 6d93470..6c86720 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -38,7 +38,6 @@ #define FLAG_DEV_MODE 2 #ifndef __PRE_RAM__ -#include #include #include "ec.h" #include diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index e83516a..b2fcb51 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -49,11 +49,6 @@ void mainboard_suspend_resume(void) send_ec_command(EC_ACPI_ENABLE); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - #if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE static int int15_handler(struct eregs *regs) { diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 18094cf..f16809f 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select HAVE_MAINBOARD_RESOURCES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MMCONF_SUPPORT diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 510d737..61bc18c 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -37,7 +37,6 @@ #define FLAG_DEV_MODE 2 #ifndef __PRE_RAM__ -#include #include #define GPIO_COUNT 5 diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 246b261..2f8f5da 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -42,11 +42,6 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - #if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE static int int15_handler(struct eregs *regs) { diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index b2cae03..dc761cf 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 905d23f..437a48a 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -856,26 +855,6 @@ static void enable_dev(device_t dev) dev->ops->init = init; // rest of mainboard init later } - /** - * @brief - * - * @param - */ - -int add_mainboard_resources(struct lb_memory *mem) -{ - device_t dev; - struct resource *res; - - dev = dev_find_slot(0, PCI_DEVFN(0,0)); - res = probe_resource(dev, 0x1C); - if( res ) { - printk(BIOS_INFO, "mmconf: base=%0llx size=%0llx\n", res->base, res->size); - lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); - } - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_PART_NUMBER) .enable_dev = enable_dev, diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index 1f02c73..e1d3cdb 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -71,13 +70,6 @@ static void h8qgi_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } -#if CONFIG_HAVE_MAINBOARD_RESOURCES -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} -#endif - struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = h8qgi_enable, diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index e5a58fe..3d71996 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -92,13 +91,6 @@ static void h8scm_enable(device_t dev) /* get_ide_dma66(); */ } -#if CONFIG_HAVE_MAINBOARD_RESOURCES -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} -#endif - struct chip_operations mainboard_ops = { CHIP_NAME("AMD H8SCM Mainboard") .enable_dev = h8scm_enable, diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c index 618eca9..e4057e5 100644 --- a/src/mainboard/supermicro/x7db8/mainboard.c +++ b/src/mainboard/supermicro/x7db8/mainboard.c @@ -22,9 +22,7 @@ #include #include #include -#include #include -#include #include #include #include diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 404ddfe..172b478 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA - select HAVE_MAINBOARD_RESOURCES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 2975e86..5209786 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -244,10 +243,9 @@ static void tim5690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) +void mainboard_coreboot_completed(void) { technexion_post_code(LED_MESSAGE_FINISH); - return 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 40ab345..3741405 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -151,11 +150,6 @@ static void tim8690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("TechNexion TIM-8690 Mainboard") .enable_dev = tim8690_enable, diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig index 3bdfb8e..f9bbfa5 100644 --- a/src/mainboard/thomson/ip1000/Kconfig +++ b/src/mainboard/thomson/ip1000/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index ae5872d..b7e3270 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -20,19 +20,12 @@ #include #include -#include #include #if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include #endif -#include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - // setting the bit disables the led. #define PARPORT_GPIO_LED_GREEN (1 << 0) #define PARPORT_GPIO_LED_ORANGE (1 << 1) diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c index 0dfbd3c..528e891 100644 --- a/src/mainboard/via/epia-n/mainboard.c +++ b/src/mainboard/via/epia-n/mainboard.c @@ -20,25 +20,6 @@ */ #include -#include -#include -#include -#include -#include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ -#if CONFIG_IOAPIC - lb_add_memory_range(mem, LB_MEM_RESERVED, - IO_APIC_ADDR, 0x1000); - lb_add_memory_range(mem, LB_MEM_RESERVED, - LOCAL_APIC_ADDR, 0x1000); - lb_add_memory_range(mem, LB_MEM_RESERVED, - 0xFFFF0000ULL, 0x10000); -#endif - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("VIA EPIA-N Mainboard") diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index d3e00c5..ea3665c 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include "chip.h" diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index c738de7..5c51b9a 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -30,7 +30,6 @@ #include #include #include "chip.h" -#include #include "northbridge.h" #include "i82810.h" diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 4951c4f..f3341d4 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -28,7 +28,6 @@ #include #include #include -#include #include "chip.h" #include "i82830.h" diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9d6d0df..41b15cf 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include "chip.h" #include "i945.h" diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b447d52..59a8cf8 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include "chip.h" #include "sandybridge.h" diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 419a82c..48556e2 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include "chip.h" #include "sch.h" diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 68c46e9..0aa4d76 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include "rs690.h" diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index 9eb47bb..e3145f7 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -103,7 +103,8 @@ static void ht_dev_read_resources(device_t dev) res->align = log2(res->size); res->gran = log2(res->size); res->limit = 0xffffffffffffffffULL; /* 64bit */ - res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED; + res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | + IORESOURCE_ASSIGNED | IORESOURCE_RESERVE; compact_resources(dev); #endif diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 5c72a04..d7dca2b 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include "rs780.h" From gerrit at coreboot.org Thu Aug 2 12:36:18 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 12:36:18 +0200 Subject: [coreboot] Patch merged into coreboot/master: ade868c x86emu: Respect the LEA 67h address size prefix References: Message-ID: the following patch was just integrated into master: commit ade868c0ad60486a911b98037e59bc5726bdc0df Author: Stefan Reinauer Date: Thu Jul 26 15:40:06 2012 -0700 x86emu: Respect the LEA 67h address size prefix From http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=f57bc0ede8e018c7e264b917927c42a018cd1d5a Change-Id: Ibdcaa27e936464cec512edb46447aa6284a34975 Signed-off-by: Stefan Reinauer Signed-off-by: Christian Zander Signed-off-by: Aaron Plattner Tested-by: Tiago Vignatti Signed-off-by: Keith Packard Reviewed-By: Patrick Georgi at Thu Aug 2 12:35:42 2012, giving +2 See http://review.coreboot.org/1364 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 12:54:57 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 12:54:57 +0200 Subject: [coreboot] Patch merged into coreboot/master: 3ae2587 AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base References: Message-ID: the following patch was just integrated into master: commit 3ae258787d3392a671a62ca3d94f10dce5eeb4a0 Author: Ky?sti M?lkki Date: Fri Jul 20 08:24:49 2012 +0300 AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base The code in rs690 or rs780 is always used with K8 or AMDFAM10 northbridge. Without GFXUMA, both of these set the same static value indirectly using the variable uma_memory_base. Make the register setting with immediate value, to remove the obscure use of variable uma_memory_base. Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Thu Aug 2 11:34:54 2012, giving +1 Reviewed-By: Anton Kochkov at Thu Aug 2 12:54:55 2012, giving +2 See http://review.coreboot.org/1246 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 12:55:30 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 12:55:30 +0200 Subject: [coreboot] Patch merged into coreboot/master: a54defe AMD Agesa and GFXUMA: drop use of uma_memory_base References: Message-ID: the following patch was just integrated into master: commit a54defe30fa86f01a1b02907594ef4a08217544b Author: Ky?sti M?lkki Date: Fri Jul 20 08:31:37 2012 +0300 AMD Agesa and GFXUMA: drop use of uma_memory_base Without GFXUMA, variables were not referenced anywhere. Fail builds on Family10 if GFXUMA is selected, because the northbridge code does not set UMA base or size. Change-Id: I15b91cf6241e9a890398eed03824b753828a0a51 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Thu Aug 2 11:50:32 2012, giving +1 Reviewed-By: Anton Kochkov at Thu Aug 2 12:55:25 2012, giving +2 See http://review.coreboot.org/1247 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 12:56:10 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 12:56:10 +0200 Subject: [coreboot] Patch merged into coreboot/master: 629ebf4 AMD and GFXUMA: move setup_uma_memory() to northbridge References: Message-ID: the following patch was just integrated into master: commit 629ebf423d20fc56c4e8ae1828192162b3bc9b72 Author: Ky?sti M?lkki Date: Thu Jul 19 19:26:43 2012 +0300 AMD and GFXUMA: move setup_uma_memory() to northbridge UMA region can be determined at any time after the amount of RAM is known and before the uma_resource() call. Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Thu Aug 2 12:07:56 2012, giving +1 Reviewed-By: Anton Kochkov at Thu Aug 2 12:56:09 2012, giving +2 See http://review.coreboot.org/1379 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 13:11:24 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 13:11:24 +0200 Subject: [coreboot] Patch merged into coreboot/master: 3dc036b Remove uma_memory_base from build if no GFXUMA References: Message-ID: the following patch was just integrated into master: commit 3dc036bd59e0534a41d6c1f81d0c2f3a4b0ab6bf Author: Ky?sti M?lkki Date: Wed Aug 1 08:05:22 2012 +0300 Remove uma_memory_base from build if no GFXUMA This patch validates the previous "drop uma_memory_base" patches; there are no more references to uma_memory_base when GFXUMA is not selected. Change-Id: I735b5e765b0c5cb4af1b4a7470cfe1af2bda7d38 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Wed Aug 1 08:51:18 2012, giving +1 Reviewed-By: Anton Kochkov at Thu Aug 2 13:11:23 2012, giving +2 See http://review.coreboot.org/1385 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 14:00:00 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 2 Aug 2012 14:00:00 +0200 Subject: [coreboot] New patch to review for coreboot: ea09f9b VIA Epia-N: drop add_mainboard_resources() References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1392 -gerrit commit ea09f9b62ad0fe5f0a40e1bf6c76fd411c6794fa Author: Ky?sti M?lkki Date: Thu Aug 2 09:43:48 2012 +0300 VIA Epia-N: drop add_mainboard_resources() The board had HAVE_MAINBOARD_RESOURCES=0 so this was never called. Drop unnecessary includes too. Change-Id: Ia7bddf29a16966c052b5cabbb47029299e6dbd12 Signed-off-by: Ky?sti M?lkki --- src/mainboard/via/epia-n/mainboard.c | 19 ------------------- 1 files changed, 0 insertions(+), 19 deletions(-) diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c index 0dfbd3c..528e891 100644 --- a/src/mainboard/via/epia-n/mainboard.c +++ b/src/mainboard/via/epia-n/mainboard.c @@ -20,25 +20,6 @@ */ #include -#include -#include -#include -#include -#include -#include - -int add_mainboard_resources(struct lb_memory *mem) -{ -#if CONFIG_IOAPIC - lb_add_memory_range(mem, LB_MEM_RESERVED, - IO_APIC_ADDR, 0x1000); - lb_add_memory_range(mem, LB_MEM_RESERVED, - LOCAL_APIC_ADDR, 0x1000); - lb_add_memory_range(mem, LB_MEM_RESERVED, - 0xFFFF0000ULL, 0x10000); -#endif - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("VIA EPIA-N Mainboard") From gerrit at coreboot.org Thu Aug 2 14:00:13 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 2 Aug 2012 14:00:13 +0200 Subject: [coreboot] New patch to review for coreboot: 5d8056e AMD RS690: mark MMCONF resource as reserved MEM References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1393 -gerrit commit 5d8056e1359675071eeb5e3c922423c63ead5d17 Author: Ky?sti M?lkki Date: Thu Aug 2 09:46:38 2012 +0300 AMD RS690: mark MMCONF resource as reserved MEM Use IORESOURCE_RESERVE to exclude the region from system RAM table. Change-Id: I61b51022165e1304a41554f67af75b3089d892af Signed-off-by: Ky?sti M?lkki --- src/southbridge/amd/rs690/ht.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index 9eb47bb..e3145f7 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -103,7 +103,8 @@ static void ht_dev_read_resources(device_t dev) res->align = log2(res->size); res->gran = log2(res->size); res->limit = 0xffffffffffffffffULL; /* 64bit */ - res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED; + res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | + IORESOURCE_ASSIGNED | IORESOURCE_RESERVE; compact_resources(dev); #endif From gerrit at coreboot.org Thu Aug 2 14:00:15 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 2 Aug 2012 14:00:15 +0200 Subject: [coreboot] New patch to review for coreboot: 33c63a5 Siemens SiteMP: drop add_mainboard_resources() References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1394 -gerrit commit 33c63a50343c97963cd0111818619b1f00e43298 Author: Ky?sti M?lkki Date: Thu Aug 2 09:44:03 2012 +0300 Siemens SiteMP: drop add_mainboard_resources() Use of lb_add_memory_region() is reduntant with the MMCONF resource being set as reserved. Change-Id: I747ea34823692b6966b2e50d22aea1fb89c73c25 Signed-off-by: Ky?sti M?lkki --- src/mainboard/siemens/sitemp_g1p1/Kconfig | 1 - src/mainboard/siemens/sitemp_g1p1/mainboard.c | 20 -------------------- 2 files changed, 0 insertions(+), 21 deletions(-) diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index b2cae03..dc761cf 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 905d23f..5053efa 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -856,26 +856,6 @@ static void enable_dev(device_t dev) dev->ops->init = init; // rest of mainboard init later } - /** - * @brief - * - * @param - */ - -int add_mainboard_resources(struct lb_memory *mem) -{ - device_t dev; - struct resource *res; - - dev = dev_find_slot(0, PCI_DEVFN(0,0)); - res = probe_resource(dev, 0x1C); - if( res ) { - printk(BIOS_INFO, "mmconf: base=%0llx size=%0llx\n", res->base, res->size); - lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); - } - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_PART_NUMBER) .enable_dev = enable_dev, From gerrit at coreboot.org Thu Aug 2 14:00:19 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 2 Aug 2012 14:00:19 +0200 Subject: [coreboot] New patch to review for coreboot: af46000 Add a notifier just before entering payload References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1395 -gerrit commit af46000277c86642890af68262110a5e153f9be8 Author: Ky?sti M?lkki Date: Thu Aug 2 09:46:54 2012 +0300 Add a notifier just before entering payload Mainboard code may want to update POST display / LEDs / play fanfare once it has succesfully loaded the payload. Change-Id: I6abd3ce883f07d09a0c7ddec745f388e95b8a7e9 Signed-off-by: Ky?sti M?lkki --- src/boot/hardwaremain.c | 3 +++ src/include/device/device.h | 1 + 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index bb7f264..57a01f0 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -150,6 +150,9 @@ void hardwaremain(int boot_complete) if (! payload) die("Could not find a payload\n"); + if (mainboard_coreboot_completed) + mainboard_coreboot_completed(); + printk(BIOS_DEBUG, "Got a payload\n"); /* Before we go off to run the payload, see if * we stayed within our bounds. diff --git a/src/include/device/device.h b/src/include/device/device.h index eaf84c6..ceae6aa 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -123,6 +123,7 @@ void dev_configure(void); void dev_enable(void); void dev_initialize(void); void dev_optimize(void); +void __attribute__((weak)) mainboard_coreboot_completed(void); /* Generic device helper functions */ int reset_bus(struct bus *bus); From gerrit at coreboot.org Thu Aug 2 14:00:20 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 2 Aug 2012 14:00:20 +0200 Subject: [coreboot] New patch to review for coreboot: c7a0c39 Technexion TIM5690: drop add_mainboard_resources() References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1396 -gerrit commit c7a0c3964bbef9eedf6ff9cd3004c2b5ddce437b Author: Ky?sti M?lkki Date: Thu Aug 2 09:44:14 2012 +0300 Technexion TIM5690: drop add_mainboard_resources() Move the POST display to take place just before entering the payload, a bit later than before. Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112 Signed-off-by: Ky?sti M?lkki --- src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim5690/mainboard.c | 3 +-- 2 files changed, 1 insertions(+), 3 deletions(-) diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 404ddfe..172b478 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA - select HAVE_MAINBOARD_RESOURCES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 2975e86..48de84e 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -244,10 +244,9 @@ static void tim5690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) +void mainboard_coreboot_completed(void) { technexion_post_code(LED_MESSAGE_FINISH); - return 0; } struct chip_operations mainboard_ops = { From gerrit at coreboot.org Thu Aug 2 14:42:41 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 14:42:41 +0200 Subject: [coreboot] Patch merged into coreboot/master: 0af8543 x86emu: Fix more mis-decoding of the data prefix References: Message-ID: the following patch was just integrated into master: commit 0af854397bdeb4412803ac46a2edefcfec1e17a5 Author: Stefan Reinauer Date: Thu Jul 26 16:25:53 2012 -0700 x86emu: Fix more mis-decoding of the data prefix cc2c73ddcb4370a7c3ad439cda4da825156c26c9's three-cent titanium tax doesn't go too far enough. Fix the rest of the call and jmp instructions to handle the data prefix correctly. Reference: Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M http://www.intel.com/Assets/PDF/manual/253666.pdf Imported from: http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=bb18f277156c08be028a6e12d8987fb1593e9168 Signed-off-by: Stefan Reinauer Change-Id: I83e6245d9748ee86722cfb7d8ac65258c35c013c Reviewed-by: Julien Cristau Signed-off-by: Adam Jackson Reviewed-By: Patrick Georgi at Thu Aug 2 14:42:40 2012, giving +2 See http://review.coreboot.org/1366 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 14:43:14 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 14:43:14 +0200 Subject: [coreboot] Patch merged into coreboot/master: a408915 x86emu: fix jump_near_IMM to handle DATA: flag correctly References: Message-ID: the following patch was just integrated into master: commit a408915a1c9d323a0735778ab72a0842b82c9df5 Author: Stefan Reinauer Date: Thu Jul 26 15:48:17 2012 -0700 x86emu: fix jump_near_IMM to handle DATA: flag correctly Before (data flag ignored -> broken): 66 DATA: e944f1 JMP 1ff6 After (fixed): 66 DATA: e944f1ffff JMP 00001ff8 This subtle difference in the length of decoded instruction meant that the VBE call jumped to the routine setting AX=0x14F (VBE Failed) instead of the routine that set AX=0x4F (VBE success). The ability to run the same code in vm86 significantly aided the debugging of this issue. Those X.org developers who would like to drop vm86 better take special care towards _all_ vesa bugs, as those will expose further issues. Imported from: http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=cc2c73ddcb4370a7c3ad439cda4da825156c26c9 Signed-off-by: Stefan Reinauer Change-Id: Id08ead9b17468cf19ede45508e5dcc50e45b5acf Signed-off-by: Luc Verhaegen Tested-by: Luc Verhaegen Reviewed-by: Adam Jackson Signed-off-by: Keith Packard Reviewed-By: Patrick Georgi at Thu Aug 2 14:43:12 2012, giving +2 See http://review.coreboot.org/1365 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 17:50:43 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 17:50:43 +0200 Subject: [coreboot] Patch merged into coreboot/master: d102e6b AMD Thatcher Board based on trinity References: Message-ID: the following patch was just integrated into master: commit d102e6b120fb2e4910da565ab293add8d332ab25 Author: zbao Date: Thu Aug 2 18:36:36 2012 +0800 AMD Thatcher Board based on trinity Thatcher features: Family 15 trinity FP2. Hudson. close to Parmer. This board and parmer both need to revert the change http://review.coreboot.org/#/c/1359/, and add thatcher's own chip.h,otherwise the mainboard_enable can not be called. Change-Id: I54e1cfca845fbcea1d3aad5eff08d760d0d215c9 Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Thu Aug 2 11:17:12 2012, giving +1 See http://review.coreboot.org/1382 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 18:03:37 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 18:03:37 +0200 Subject: [coreboot] Patch merged into coreboot/master: 13a2dfa AMD hudson: Call the rtc update if needed. References: Message-ID: the following patch was just integrated into master: commit 13a2dfaa787e56cc159dbbf98c55cafa575177eb Author: zbao Date: Thu Aug 2 19:03:44 2012 +0800 AMD hudson: Call the rtc update if needed. Parmer and thather hang at windows 7 booting process. Setting the valid date in CMOS can fix that. Change-Id: I5e427cfb42430ebebdb4c1e48bd25860c0fec45f Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Thu Aug 2 12:43:38 2012, giving +1 Reviewed-By: Ronald G. Minnich at Thu Aug 2 18:03:35 2012, giving +2 See http://review.coreboot.org/1390 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 18:19:04 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 18:19:04 +0200 Subject: [coreboot] Patch merged into coreboot/master: 6c9e7d7 Limit the device field to 5 bits. References: Message-ID: the following patch was just integrated into master: commit 6c9e7d7c6d8eb28b39c9bef1211031a88fd5773e Author: zbao Date: Mon Jul 23 19:49:40 2012 +0800 Limit the device field to 5 bits. The field device in PCI_ADDRESS only takes 5 bits. So if the device number is more than 32, it will truncated to 5 bits. Before this patch, other pci devices will be incorrectly probed as processor node. Change-Id: I64dcd4f4fda7b7080a9905dce580feb829584b94 Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Tue Jul 31 13:08:25 2012, giving +1 Reviewed-By: Anton Kochkov at Thu Aug 2 13:03:08 2012, giving +1 Reviewed-By: Ronald G. Minnich at Tue Jul 31 17:45:57 2012, giving +2 See http://review.coreboot.org/1264 for details. -gerrit From gerrit at coreboot.org Thu Aug 2 18:39:21 2012 From: gerrit at coreboot.org (Ronald G. Minnich (rminnich@gmail.com)) Date: Thu, 2 Aug 2012 18:39:21 +0200 Subject: [coreboot] New patch to review for coreboot: 8f45a84 Add a capability for mainboard-specific posting. References: Message-ID: Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1397 -gerrit commit 8f45a843b44583fdeade2a78e657efe8424b144b Author: Ronald G. Minnich Date: Thu Aug 2 09:34:05 2012 -0700 Add a capability for mainboard-specific posting. Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case 0xfe: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich --- src/console/post.c | 8 ++++++++ src/include/console/console.h | 2 ++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/console/post.c b/src/console/post.c index 08336a2..0f95427 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,6 +24,13 @@ /* Write POST information */ +/* Some mainboards have very nice features beyond just a simple + * display. They can override this function. + */ +void __attribute__((weak)) mainboard_post(uint8_t value) +{ +} + void post_code(uint8_t value) { #if !CONFIG_NO_POST @@ -33,5 +40,6 @@ void post_code(uint8_t value) print_emerg("\n"); #endif outb(value, CONFIG_POST_PORT); + mainboard_post(value); #endif } diff --git a/src/include/console/console.h b/src/include/console/console.h index 56e202d..00be96f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -69,6 +69,8 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); void post_code(u8 value); +/* this function is weak and can be overridden by a mainboard function. */ +void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); From gerrit at coreboot.org Thu Aug 2 23:17:26 2012 From: gerrit at coreboot.org (Ronald G. Minnich (rminnich@gmail.com)) Date: Thu, 2 Aug 2012 23:17:26 +0200 Subject: [coreboot] Patch set updated for coreboot: 2e42103 Add a capability for mainboard-specific posting. References: Message-ID: Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1397 -gerrit commit 2e4210338aa7a2a8d3725432458e24dae071280d Author: Ronald G. Minnich Date: Thu Aug 2 09:34:05 2012 -0700 Add a capability for mainboard-specific posting. Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case 0xfe: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich --- src/console/post.c | 12 ++++++++++++ src/include/console/console.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/console/post.c b/src/console/post.c index 08336a2..9cdad99 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,6 +24,15 @@ /* Write POST information */ +/* someday romcc will be gone. */ +#ifndef __ROMCC__ +/* Some mainboards have very nice features beyond just a simple + * display. They can override this function. + */ +void __attribute__((weak)) mainboard_post(uint8_t value) +{ +} +#endif void post_code(uint8_t value) { #if !CONFIG_NO_POST @@ -34,4 +43,7 @@ void post_code(uint8_t value) #endif outb(value, CONFIG_POST_PORT); #endif +#ifndef __ROMCC__ + mainboard_post(value); +#endif } diff --git a/src/include/console/console.h b/src/include/console/console.h index 56e202d..00be96f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -69,6 +69,8 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); void post_code(u8 value); +/* this function is weak and can be overridden by a mainboard function. */ +void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); From gerrit at coreboot.org Thu Aug 2 23:40:13 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Aug 2012 23:40:13 +0200 Subject: [coreboot] Patch merged into coreboot/master: 31b06e2 RTC: Add a routine to check if the CMOS date is valid References: Message-ID: the following patch was just integrated into master: commit 31b06e2259ccfd84e8fe1f5f0bc1b2bcb58c6a28 Author: zbao Date: Thu Aug 2 19:02:26 2012 +0800 RTC: Add a routine to check if the CMOS date is valid If the CMOS is cleared or someone writes some random date/time on purpose, the CMOS date register has a invalid date. This will hurts some OS, like Windows 7, which hangs at MS logo forever. When we detect that, we need to write a reasonable date in CMOS. Alexandru Gagniuc: Hmm, it would be interesting to use the date the coreboot image was built and set that as the default date. At least until time travel is invented. Change-Id: Ic1c7a2d60e711265686441c77bdf7891a7efb42e Signed-off-by: Zheng Bao Signed-off-by: zbao Reviewed-By: Patrick Georgi at Thu Aug 2 12:37:23 2012, giving +2 Build-Tested: build bot (Jenkins) at Thu Aug 2 12:27:22 2012, giving +1 See http://review.coreboot.org/1389 for details. -gerrit From gerrit at coreboot.org Fri Aug 3 00:31:43 2012 From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com)) Date: Fri, 3 Aug 2012 00:31:43 +0200 Subject: [coreboot] Patch set updated for coreboot: 090d4d8 Add a capability for mainboard-specific posting. References: Message-ID: Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1397 -gerrit commit 090d4d8421bb113ce98aca598f587fd558b17c80 Author: Ronald G. Minnich Date: Thu Aug 2 09:34:05 2012 -0700 Add a capability for mainboard-specific posting. Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case 0xfe: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich --- src/console/post.c | 12 ++++++++++++ src/include/console/console.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/console/post.c b/src/console/post.c index 08336a2..9cdad99 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,6 +24,15 @@ /* Write POST information */ +/* someday romcc will be gone. */ +#ifndef __ROMCC__ +/* Some mainboards have very nice features beyond just a simple + * display. They can override this function. + */ +void __attribute__((weak)) mainboard_post(uint8_t value) +{ +} +#endif void post_code(uint8_t value) { #if !CONFIG_NO_POST @@ -34,4 +43,7 @@ void post_code(uint8_t value) #endif outb(value, CONFIG_POST_PORT); #endif +#ifndef __ROMCC__ + mainboard_post(value); +#endif } diff --git a/src/include/console/console.h b/src/include/console/console.h index 56e202d..00be96f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -69,6 +69,8 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); void post_code(u8 value); +/* this function is weak and can be overridden by a mainboard function. */ +void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); From gerrit at coreboot.org Fri Aug 3 00:34:50 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 3 Aug 2012 00:34:50 +0200 Subject: [coreboot] Patch merged into coreboot/master: 24a3100 Fix mainboard level enable_dev() References: Message-ID: the following patch was just integrated into master: commit 24a31006d5089550f08076b78e51d92d687ae77a Author: Ky?sti M?lkki Date: Fri Jul 27 19:22:26 2012 +0300 Fix mainboard level enable_dev() Commit 188e3c2ff06a82f61d7d71e610b32b1a250c0a45 dropped mainboard out of the static device tree. This left dev_root->chip_ops unset, and mainboard_ops.enable_dev() was no longer called. Change-Id: I6d447c8049a66041b8bb36ec9aac3e7e0d20a99b Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Fri Jul 27 22:04:59 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Aug 3 00:34:49 2012, giving +2 See http://review.coreboot.org/1374 for details. -gerrit From gerrit at coreboot.org Fri Aug 3 00:57:10 2012 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Fri, 3 Aug 2012 00:57:10 +0200 Subject: [coreboot] New patch to review for coreboot: c8584ce Make the device tree available in the rom stage References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1398 -gerrit commit c8584cefd8799eebab5be4b5564bfc98a2cef468 Author: Stefan Reinauer Date: Tue Jul 31 16:47:25 2012 -0700 Make the device tree available in the rom stage We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich Signed-off-by: Stefan Reinauer --- Makefile.inc | 5 +++ src/cpu/amd/agesa/s3_resume.c | 2 + src/devices/Makefile.inc | 2 + src/devices/device_romstage.c | 80 +++++++++++++++++++++++++++++++++++++++++ src/include/device/device.h | 38 ++++++++++++++------ src/include/device/pci.h | 3 ++ util/sconfig/main.c | 32 ++++++++++------ 7 files changed, 139 insertions(+), 23 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ca1e066..083d423 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -228,6 +228,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devi $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c +romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c $(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" @@ -237,6 +238,10 @@ $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< +$(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $< + ####################################################################### # Clean up rules clean-abuild: diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6bb053d..0348a9f 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -29,7 +29,9 @@ #endif #include #include +#ifndef __PRE_RAM__ #include +#endif #include #include #include diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9ffc0bb..9a2f71e 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -11,6 +11,8 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c +romstage-y+= device_romstage.c + subdirs-y += oprom ifeq ($(CONFIG_PCI_ROM_RUN),y) diff --git a/src/devices/device_romstage.c b/src/devices/device_romstage.c new file mode 100644 index 0000000..475f94a --- /dev/null +++ b/src/devices/device_romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003-2004 Linux Networx + * (Written by Eric Biederman for Linux Networx) + * Copyright (C) 2003 Greg Watson + * Copyright (C) 2004 Li-Ta Lo + * Copyright (C) 2005-2006 Tyan + * (Written by Yinghai Lu for Tyan) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +/** Linked list of ALL devices */ +ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root; + +/** + * Given a PCI bus and a devfn number, find the device structure. + * + * @param bus The bus number. + * @param devfn A device/function number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus, + unsigned int devfn) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_PCI) && + (dev->bus->secondary == bus) && + (dev->path.pci.devfn == devfn)) { + result = dev; + break; + } + } + return result; +} + +/** + * Given an SMBus bus and a device number, find the device structure. + * + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus, + unsigned int addr) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_I2C) && + (dev->bus->secondary == bus) && + (dev->path.i2c.device == addr)) { + result = dev; + break; + } + } + return result; +} + diff --git a/src/include/device/device.h b/src/include/device/device.h index 0b15ac5..88d73c7 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -5,8 +5,14 @@ #include #include +#ifdef __PRE_RAM__ +#define ROMSTAGE_CONST const +#else +#define ROMSTAGE_CONST +#endif struct device; +#ifndef __PRE_RAM__ typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; @@ -42,12 +48,14 @@ struct device_operations { const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations *ops_pci_bus; }; +#endif struct bus { - device_t dev; /* This bridge device */ - device_t children; /* devices behind this bridge */ - struct bus *next; /* The next bridge on this device */ + + ROMSTAGE_CONST struct device * dev; /* This bridge device */ + ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ @@ -70,10 +78,12 @@ struct pci_irq_info { }; struct device { - struct bus * bus; /* bus this device is on, for bridge + ROMSTAGE_CONST struct bus * bus; /* bus this device is on, for bridge * devices, it is the up stream bus */ - device_t sibling; /* next device on this bus */ - device_t next; /* chain of all devices */ + + ROMSTAGE_CONST struct device * sibling; /* next device on this bus */ + + ROMSTAGE_CONST struct device * next; /* chain of all devices */ struct device_path path; unsigned vendor; @@ -89,23 +99,24 @@ struct device { u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ - struct resource *resource_list; + ROMSTAGE_CONST struct resource *resource_list; /* links are (downstream) buses attached to the device, usually a leaf * device with no children has 0 buses attached and a bridge has 1 bus */ - struct bus *link_list; + ROMSTAGE_CONST struct bus *link_list; struct device_operations *ops; const struct chip_operations *chip_ops; - void *chip_info; + ROMSTAGE_CONST void *chip_info; }; /** * This is the root of the device tree. The device tree is defined in the * static.c file and is generated by the config tool at compile time. */ -extern struct device dev_root; +extern ROMSTAGE_CONST struct device dev_root; +#ifndef __PRE_RAM__ extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; @@ -195,5 +206,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); - +#else +ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, + unsigned int devfn); +ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, + unsigned int addr); +#endif #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 51d5283..a215a2a 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -16,9 +16,11 @@ #define PCI_H #include +#include #include #include #include +#ifndef __PRE_RAM__ #include #include @@ -107,4 +109,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) unsigned mainboard_pci_subsystem_vendor_id(struct device *dev); unsigned mainboard_pci_subsystem_device_id(struct device *dev); +#endif #endif /* PCI_H */ diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 824bc6c..82a7491 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -366,13 +366,15 @@ void add_ioapic_info(struct device *dev, int apicid, const char *_srcpin, int ir static void pass0(FILE *fil, struct device *ptr) { if (ptr->type == device && ptr->id == 0) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", ptr->name); + if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) { - fprintf(fil, "static struct device %s;\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST static struct device %s;\n", ptr->name); if (ptr->rescnt > 0) - fprintf(fil, "struct resource %s_res[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[];\n", ptr->name); if (ptr->children || ptr->multidev) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", + ptr->name); } } @@ -382,8 +384,10 @@ static void pass1(FILE *fil, struct device *ptr) if (!ptr->used && (ptr->type == device)) { if (ptr->id != 0) fprintf(fil, "static "); - fprintf(fil, "struct device %s = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct device %s = {\n", ptr->name); + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); @@ -415,7 +419,9 @@ static void pass1(FILE *fil, struct device *ptr) if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); if (ptr->chip->chiph_exists) { + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); } if (ptr->nextdev) @@ -424,7 +430,8 @@ static void pass1(FILE *fil, struct device *ptr) } if (ptr->rescnt > 0) { int i=1; - fprintf(fil, "struct resource %s_res[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[] = {\n", + ptr->name); struct resource *r = ptr->res; while (r) { fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); @@ -441,7 +448,7 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t };\n"); } if (!ptr->used && ptr->type == device && (ptr->children || ptr->multidev)) { - fprintf(fil, "struct bus %s_links[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[] = {\n", ptr->name); if (ptr->multidev) { struct device *d = ptr; while (d) { @@ -473,8 +480,9 @@ static void pass1(FILE *fil, struct device *ptr) } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", - ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = {\n", + ptr->name_underscore, ptr->name_underscore, + ptr->id); struct reg *r = ptr->reg; while (r) { fprintf(fil, "\t.%s = %s,\n", r->key, r->value); @@ -482,7 +490,7 @@ static void pass1(FILE *fil, struct device *ptr) } fprintf(fil, "};\n\n"); } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = { };\n", ptr->name_underscore, ptr->name_underscore, ptr->id); } } @@ -617,9 +625,9 @@ int main(int argc, char** argv) { fprintf(autogen, "\n/* pass 0 */\n"); walk_device_tree(autogen, &root, pass0, NULL); fprintf(autogen, "\n/* pass 1 */\n" - "struct device *last_dev = &%s;\n", lastdev->name); + "ROMSTAGE_CONST struct device * ROMSTAGE_CONST last_dev = &%s;\n", lastdev->name); #ifdef MAINBOARDS_HAVE_CHIP_H - fprintf(autogen, "struct mainboard_config mainboard_info_0;\n"); + fprintf(autogen, "static ROMSTAGE_CONST struct mainboard_config ROMSTAGE_CONST mainboard_info_0;\n"); #endif walk_device_tree(autogen, &root, pass1, NULL); From gerrit at coreboot.org Fri Aug 3 04:09:18 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 04:09:18 +0200 Subject: [coreboot] New patch to review for coreboot: 6c493d7 AMD Parmer: Remove warning. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1399 -gerrit commit 6c493d7bf800fa4e295465f28f8813477121f917 Author: zbao Date: Fri Aug 3 11:47:53 2012 +0800 AMD Parmer: Remove warning. Change-Id: I4ba2d480fa6df5ee741d887d26524b32c1901d73 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/mainboard/amd/parmer/acpi_tables.c | 2 +- src/mainboard/amd/parmer/mptable.c | 6 ------ 2 files changed, 1 insertions(+), 7 deletions(-) diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index c699d5b..0a64535 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -76,7 +76,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* 5 mean: 0101 --> Edige-triggered, Active high */ /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi(current, 0xff, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); /* 1: LINT1 connect to NMI */ return current; diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 143920e..9dcc845 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -75,12 +75,6 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; - int boot_apic_id; - unsigned apic_version; - unsigned cpu_features; - unsigned cpu_feature_flags; - struct cpuid_result result; - unsigned long cpu_flag; u32 dword; u8 byte; From gerrit at coreboot.org Fri Aug 3 06:08:29 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 06:08:29 +0200 Subject: [coreboot] New patch to review for coreboot: 7930ea3 AMD S3: Add a document about S3 on AMD platform References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1400 -gerrit commit 7930ea30fbd307013159deeb1aeee0ca80d05736 Author: zbao Date: Fri Aug 3 13:53:10 2012 +0800 AMD S3: Add a document about S3 on AMD platform See the document. Need review. Everything should be in Authentic English. Change-Id: Idc528b8c6b0d5afe08fc4f4387b7bff30698f677 Signed-off-by: Zheng Bao Signed-off-by: zbao --- documentation/AMD-S3.txt | 95 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 95 insertions(+), 0 deletions(-) diff --git a/documentation/AMD-S3.txt b/documentation/AMD-S3.txt new file mode 100644 index 0000000..58ee0d7 --- /dev/null +++ b/documentation/AMD-S3.txt @@ -0,0 +1,95 @@ + _____ ____ _____ ______ ____ ____ ____ _______ + / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __| + | | | | | | |__) | |__ | |_) | | | | | | | | | + | | | | | | _ /| __| | _ <| | | | | | | | | + | |___| |__| | | \ \| |____| |_) | |__| | |__| | | | + \_____\____/|_| \_\______|____/ \____/ \____/ |_| + + __ __ _____ _____ ____ + /\ | \/ | __ \ / ____| |___ \ + / \ | \ / | | | | | (___ __) | + / /\ \ | |\/| | | | | \___ \ |__ < + / ____ \| | | | |__| | ____) | ___) | + /_/ \_\_| |_|_____/ |_____/ |____/ + + + S3 in Coreboot +---------------------------------------- + Zheng Bao + + + +Introduction +============ +This document is about how the feature S3 is implemented on coreboot, +specificly on AMD platform. This topic deals with ACPI spec, hardware, +BIOS, OS. We try to help coreboot users to realize their own S3. + +S3 in a nutshell +================ +The S3 sleeping state is a low wake latency sleeping state where all +system context is lost except system memory. [1]. S3 is a ACPI +definition. +To enter S3, write 3 in SLP_TYPx and setting the SLP_EN bit. But if +you do that, board can not resume at where it sleeps, because you +don't save the context. More often than not, we make the board go into +S3 by the tools which OSes provide. For windows, click +Start->sleep. For linux, some distribution provide a tools called +pm-suspend, which can make the system goto S3. If pm-suspend is not +available, we can run "echo mem > /sys/power/state", but this way may +not save all the needed context. +In S3 state, the power is off. So when the power button is pressed, +BIOS runs as it does in cold boot. If BIOS didn't detect whether +board boots or resume, it would go the same way as boot. It is not +what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS +are waking up. +BIOS is responsible for restore the machine state as it is before +sleep. It needs restore the memory controller, not overwriting memory +which is marked as reserved. For the peripheral which loses its +registers, BIOS needs to write the original value. +When everything is done, BIOS needs to find out the wakeup vector +provided by OSes and jump there. OSes also have work to do. We can go +to linux kernel or some other open source projects to find out how they +handle S3 resume. + +Memory Layout +============= +Restoring memory is the most important job done by BIOS. When the +power is off, the memory is maintained by standby power. BIOS need to +make sure that when flow goes to OS, everything in memory should be +the same as it was. + +The chip vendor will provide a way, or code, to wake up the memory +from sleeping. In AGESA 2008 arch, it is called AmdInitResume. + +The BIOS itself needs some memory to run. Either, BIOS marks the erea +as reserved in e820, or BIOS saves the content into reserved space. + +Here is the address Map for S3 Resume. Assumingly the total memory is 1GB. +00000000 --- 00100000 BIOS Reserved area. +00100000 --- 00200000 Free +00200000 --- 01000000 Coreboot ramstage area. +01000000 --- 2e160000 Free +2e160000 --- 2e170000 ACPI table +2e170000 --- 2ef70000 OSRAM +2ef70000 --- 2efe0000 Stack in highmem +2efe0000 --- 2f000000 heap in highmem +2f000000 TOM + +AMD requirements in S3 +====================== +Chip vendor like AMD will provide bunch of routines to restore the +board.[2] + * AmdS3Save: It is called in cold boot, save required register into + non-volatile storage. Currently, we use SPI flash to store the data. + * AmdInitResume: Restore the memory controller. + * AmdS3LateRestore: Called after AmdInitResume, restore other + register that memory. + * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore: + Provided by Southbridge vendor code. Early is called before PCI + enumeration, and Late is called after that. + +Reference +========= +[1] ACPI40 +[2] Coreboot Vendorcode From gerrit at coreboot.org Fri Aug 3 07:11:15 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 07:11:15 +0200 Subject: [coreboot] New patch to review for coreboot: f80c3d9 Trivial: Change # to @# in Makefile command References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1401 -gerrit commit f80c3d9eff0d31d02cf8f541a55b3576dc89aedc Author: zbao Date: Fri Aug 3 14:56:49 2012 +0800 Trivial: Change # to @# in Makefile command My editor highlights the # as syntax error. I think it is because every line starting with a is seen as a command. But # is not a makefile accepted command, is it? I found in {top}/Makefile.inc there are some @#. So I think every makefile should sync with that format. Change-Id: Ib86165df4fefff3007693f9b8077a5a0a00bb6d3 Signed-off-by: Zheng Bao Signed-off-by: zbao --- Makefile.inc | 2 +- documentation/Makefile | 2 +- payloads/external/FILO/Makefile.inc | 4 ++-- payloads/external/SeaBIOS/Makefile.inc | 4 ++-- src/southbridge/amd/Makefile.inc | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ca1e066..4259cad 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -95,7 +95,7 @@ $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$(basename $$@)).asl mv $$(basename $$@).hex $$(basename $$@).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$@).c - # keep %.o: %.c rule from catching the temporary .c file after a make clean + @# keep %.o: %.c rule from catching the temporary .c file after a make clean mv $$(basename $$@).c $$(basename $$@).hex endef diff --git a/documentation/Makefile b/documentation/Makefile index 84ac0b5..1a19828 100644 --- a/documentation/Makefile +++ b/documentation/Makefile @@ -32,7 +32,7 @@ else ifneq ($(strip $(CONVERT)),) endif LinuxBIOS-AMD64.toc: $(FIGS) LinuxBIOS-AMD64.tex - # 2 times to make sure we have a current toc. + @# 2 times to make sure we have a current toc. $(PDFLATEX) LinuxBIOS-AMD64.tex $(PDFLATEX) LinuxBIOS-AMD64.tex diff --git a/payloads/external/FILO/Makefile.inc b/payloads/external/FILO/Makefile.inc index 311b3c8..cce075b 100644 --- a/payloads/external/FILO/Makefile.inc +++ b/payloads/external/FILO/Makefile.inc @@ -27,8 +27,8 @@ config: libpayload echo "CONFIG_LZMA=y" >> filo/.config echo "CONFIG_FLASH_FLOPPY=y" >> filo/.config echo "CONFIG_VGAHOOKS=y" >> filo/.config - # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> filo/.config + @# This shows how to force a previously set .config option *off* + @#echo "# CONFIG_SMBIOS is not set" >> filo/.config filo: config echo " MAKE FILO $(NAME-y)" diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index e0f03b1..8e47576 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -29,8 +29,8 @@ config: checkout echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config - # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config + @# This shows how to force a previously set .config option *off* + @#echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config build: config echo " MAKE SeaBIOS $(TAG-y)" diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 9709715..733a9bc 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -21,7 +21,7 @@ ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/s3.rom: echo " S3 NVRAM 0xffff0000 (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) + @ # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ From gerrit at coreboot.org Fri Aug 3 07:23:51 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 07:23:51 +0200 Subject: [coreboot] New patch to review for coreboot: 8452211 SuperIO LPC47N217: Remove warnings References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1402 -gerrit commit 8452211aaea71a5b01b22708fa606e653f336d11 Author: zbao Date: Fri Aug 3 15:09:09 2012 +0800 SuperIO LPC47N217: Remove warnings Change-Id: Id5756f1bb748ae7bec0bcdc21804f5338e850baa Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/superio/smsc/lpc47n217/early_serial.c | 4 ++-- src/superio/smsc/lpc47n217/superio.c | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index ce79db8..d767e05 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) { /* LPC47N217 requires base ports to be a multiple of 4. */ ASSERT(!(iobase & 0x3)); @@ -74,7 +74,7 @@ void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -void lpc47n217_pnp_set_enable(device_t dev, int enable) +static void lpc47n217_pnp_set_enable(device_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 88832e1..01c96b1 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -133,7 +133,8 @@ static void lpc47n217_pnp_enable(device_t dev) */ static void lpc47n217_init(device_t dev) { - struct superio_smsc_lpc47n217_config* conf = dev->chip_info; + /* TODO: Reserved for future. */ + /* struct superio_smsc_lpc47n217_config* conf = dev->chip_info; */ if (!dev->enabled) return; @@ -142,7 +143,7 @@ static void lpc47n217_init(device_t dev) static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02x not allocated\n", + printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", dev_path(dev), resource->index); return; } @@ -160,7 +161,7 @@ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) } else if (resource->flags & IORESOURCE_IRQ) { lpc47n217_pnp_set_irq(dev, resource->base); } else { - printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n", + printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", dev_path(dev), resource->index); return; } From gerrit at coreboot.org Fri Aug 3 07:20:07 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 3 Aug 2012 07:20:07 +0200 Subject: [coreboot] Patch set updated for coreboot: 09c93e1 Technexion TIM5690: drop add_mainboard_resources() References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1396 -gerrit commit 09c93e14176aa5c8a77638ef9102a06924fa5215 Author: Ky?sti M?lkki Date: Thu Aug 2 09:44:14 2012 +0300 Technexion TIM5690: drop add_mainboard_resources() Move the POST display to take place just before jumping the payload, a bit later than before. Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112 Signed-off-by: Ky?sti M?lkki --- src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim5690/mainboard.c | 10 +++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 404ddfe..172b478 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA - select HAVE_MAINBOARD_RESOURCES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 41147cd..c1aa389 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -242,10 +242,14 @@ static void tim5690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) +void mainboard_post(u8 value) { - technexion_post_code(LED_MESSAGE_FINISH); - return 0; + switch (value) { + case POST_ENTER_ELF_BOOT: + technexion_post_code(LED_MESSAGE_FINISH); + break; + default: + } } struct chip_operations mainboard_ops = { From gerrit at coreboot.org Fri Aug 3 08:12:10 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 08:12:10 +0200 Subject: [coreboot] New patch to review for coreboot: 1400723 AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation) References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1404 -gerrit commit 14007235fe60e386584d75148ae9c65cabcae577 Author: zbao Date: Fri Aug 3 15:56:21 2012 +0800 AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation) Apply the change http://review.coreboot.org/1265 to all the AMD northbridge. Change-Id: Idf3994c1e9ec76cd19db9f740d825cf24059884f Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 8d64a30..d7e9521 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -619,7 +619,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } } @@ -779,7 +779,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; sizek = limitk - basek; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7f8650c..c63890d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -628,7 +628,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } } From gerrit at coreboot.org Fri Aug 3 07:59:15 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 07:59:15 +0200 Subject: [coreboot] New patch to review for coreboot: cbe5a5b AMD NB: Limit the device field to 5 bits. (Propagation) References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1403 -gerrit commit cbe5a5b90010158d78913f83817390e332894eae Author: zbao Date: Fri Aug 3 15:44:42 2012 +0800 AMD NB: Limit the device field to 5 bits. (Propagation) Apply the change http://review.coreboot.org/1264 to all the AMD northbridge. Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/northbridge/amd/agesa/family10/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 6 +++++- src/northbridge/amd/agesa/family14/northbridge.c | 6 +++++- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/amdfam10/northbridge.c | 4 ++-- 5 files changed, 16 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 831aec0..8cc9475 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -361,8 +361,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static device_t get_node_pci(u32 nodeid, u32 fn) { -#if NODE_NUMS == 64 - if (nodeid < 32) { +#if NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f3f03a4..af1d4f0 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -50,7 +50,11 @@ static unsigned fx_devs=0; device_t get_node_pci(u32 nodeid, u32 fn) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + if ((CONFIG_CDB + nodeid) < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index af6dfcc..a03939c 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -51,7 +51,11 @@ static unsigned fx_devs = 0; device_t get_node_pci(u32 nodeid, u32 fn) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + if ((CONFIG_CDB + nodeid) < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } } static void get_fx_devs(void) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a080293..8d64a30 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -122,8 +122,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static device_t get_node_pci(u32 nodeid, u32 fn) { -#if MAX_NODE_NUMS == 64 - if (nodeid < 32) { +#if MAX_NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 15b29f6..aa15fdd 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -63,8 +63,8 @@ static unsigned fx_devs=0; device_t get_node_pci(u32 nodeid, u32 fn) { -#if NODE_NUMS == 64 - if(nodeid<32) { +#if NODE_NUMS + CONFIG_CDB >= 32 + if((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); From gerrit at coreboot.org Fri Aug 3 09:13:16 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 09:13:16 +0200 Subject: [coreboot] New patch to review for coreboot: a1b1a4d AMD f15: Change multiply ONE_MB to bit shifting (Propagation) References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1405 -gerrit commit a1b1a4df8b07141ee7e8cfc13095ba36c9f883ed Author: zbao Date: Fri Aug 3 16:06:08 2012 +0800 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) Apply the change http://review.coreboot.org/1263 to family15 northbridge. Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/northbridge/amd/agesa/family15/northbridge.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d7e9521..d9a153b 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -627,7 +627,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB 0x100000 +#define ONE_MB_SHIFT 20 static void setup_uma_memory(void) { @@ -654,13 +654,13 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; + sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { + uma_memory_size = 256 << ONE_MB_SHIFT; } else { - uma_memory_size = 64 * ONE_MB; + uma_memory_size = 64 << ONE_MB_SHIFT; } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ From gerrit at coreboot.org Fri Aug 3 09:13:17 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 09:13:17 +0200 Subject: [coreboot] New patch to review for coreboot: 29ac975 AMD SB: Call the rtc update if needed (Propagation) References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1406 -gerrit commit 29ac9757e06350dbaad8f780b8ce3a51ed419a9a Author: zbao Date: Fri Aug 3 16:58:53 2012 +0800 AMD SB: Call the rtc update if needed (Propagation) Apply the change http://review.coreboot.org/1390 to all the AMD southbridge. Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/southbridge/amd/cimx/sb700/late.c | 12 +++++++++++- src/southbridge/amd/cimx/sb800/late.c | 12 +++++++++++- src/southbridge/amd/cimx/sb900/late.c | 3 +++ src/southbridge/amd/sb600/lpc.c | 1 + src/southbridge/amd/sb700/lpc.c | 2 ++ src/southbridge/amd/sb800/lpc.c | 2 ++ 6 files changed, 30 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 4e51e0a..be2b8cd 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -23,6 +23,7 @@ #include #include #include /* smbus_bus_operations */ +#include #include /* printk */ #include "lpc.h" /* lpc_read_resources */ #include "Platform.h" /* Platfrom Specific Definitions */ @@ -72,11 +73,20 @@ static void lpc_enable_resources(device_t dev) printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__); } +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n"); +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = lpc_enable_resources, - .init = 0, + .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ce82b3..7286a6d 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -23,6 +23,7 @@ #include #include #include /* smbus_bus_operations */ +#include #include /* printk */ #include #include "lpc.h" /* lpc_read_resources */ @@ -120,11 +121,20 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 71c65e3..85485ed 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -22,6 +22,7 @@ #include /* device_operations */ #include #include /* smbus_bus_operations */ +#include #include /* printk */ #include "lpc.h" /* lpc_read_resources */ #include "SbPlatform.h" /* Platfrom Specific Definitions */ @@ -98,6 +99,8 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); /* SB Configure HPET base and enable bit */ //- hpetInit(sb_config, &(sb_config->BuildParameters)); + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); } diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 6f16ea8..22945a7 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -60,6 +60,7 @@ static void lpc_init(device_t dev) byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } static void sb600_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index c968927..be940e3 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -81,6 +81,8 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); } #endif + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } void set_cbmem_toc(struct cbmem_entry *toc) diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 4e2031f..3cb0789 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -67,6 +67,8 @@ static void lpc_init(device_t dev) byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } static void sb800_lpc_read_resources(device_t dev) From gerrit at coreboot.org Fri Aug 3 09:27:12 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 09:27:12 +0200 Subject: [coreboot] New patch to review for coreboot: 7d06a07 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1407 -gerrit commit 7d06a0764ae69af74c46aeb18e582f8799865d20 Author: zbao Date: Fri Aug 3 17:12:45 2012 +0800 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image Apply the change http://review.coreboot.org/1351 to thatcher. Change-Id: I33e7ad0cad2ae06f5934c60939d60a18444aa24e Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/mainboard/amd/thatcher/BiosCallOuts.c | 12 ++++++++++++ src/mainboard/amd/thatcher/BiosCallOuts.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 34936e0..8660e05 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -25,6 +25,7 @@ #include "OptionsIds.h" #include "heapManager.h" #include "FchPlatform.h" +#include "cbfs.h" STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -71,6 +72,9 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, + BiosHookGfxGetVbiosImage + } }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) @@ -735,3 +739,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } + +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) +{ + GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; + pVbiosImageInfo->ImagePtr = cbfs_find_file("pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM); + /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ + return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.h b/src/mainboard/amd/thatcher/BiosCallOuts.h index 1993c64..b7b9eaf 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.h +++ b/src/mainboard/amd/thatcher/BiosCallOuts.h @@ -71,6 +71,8 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* FCH OEM Config*/ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +/* Get Vbios Image */ +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); #define SB_GPIO_REG02 2 #define SB_GPIO_REG09 9 #define SB_GPIO_REG10 10 From gerrit at coreboot.org Fri Aug 3 10:03:11 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 3 Aug 2012 10:03:11 +0200 Subject: [coreboot] Patch set updated for coreboot: b39ea47 Technexion TIM5690: drop add_mainboard_resources() References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1396 -gerrit commit b39ea475fbdeb64bb94f02d83859264fb3ec193e Author: Ky?sti M?lkki Date: Thu Aug 2 09:44:14 2012 +0300 Technexion TIM5690: drop add_mainboard_resources() Move the POST display to take place just before jumping the payload, a bit later than before. Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112 Signed-off-by: Ky?sti M?lkki --- src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim5690/mainboard.c | 9 ++++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 404ddfe..172b478 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA - select HAVE_MAINBOARD_RESOURCES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 41147cd..b87058c 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -242,10 +242,13 @@ static void tim5690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) +void mainboard_post(u8 value) { - technexion_post_code(LED_MESSAGE_FINISH); - return 0; + switch (value) { + case POST_ENTER_ELF_BOOT: + technexion_post_code(LED_MESSAGE_FINISH); + break; + } } struct chip_operations mainboard_ops = { From gerrit at coreboot.org Fri Aug 3 11:40:58 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 3 Aug 2012 11:40:58 +0200 Subject: [coreboot] Patch set updated for coreboot: 67928b4 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1405 -gerrit commit 67928b476da1150db806a63dde367586f89606be Author: zbao Date: Fri Aug 3 16:06:08 2012 +0800 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) Apply the change http://review.coreboot.org/1263 to family15 northbridge. Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7 Signed-off-by: Zheng Bao Signed-off-by: zbao [km: rebased] Signed-off-by: Ky?sti M?lkki --- src/northbridge/amd/agesa/family15/northbridge.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 6ce73cb..11edbf0 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -627,7 +627,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB 0x100000 +#define ONE_MB_SHIFT 20 static void setup_uma_memory(void) { @@ -643,13 +643,13 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = topmem + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((bsp_topmem2()>>32) || (sys_mem >= 2048 * ONE_MB)) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; + sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { + uma_memory_size = 256 << ONE_MB_SHIFT; } else { - uma_memory_size = 64 * ONE_MB; + uma_memory_size = 64 << ONE_MB_SHIFT; } uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ From gerrit at coreboot.org Fri Aug 3 11:40:58 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 3 Aug 2012 11:40:58 +0200 Subject: [coreboot] Patch set updated for coreboot: 5710acf Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1388 -gerrit commit 5710acf9a3d8a8f92ec8e603c6c434ec54049d82 Author: Ky?sti M?lkki Date: Wed Aug 1 14:32:13 2012 +0300 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/mtrr/amd_mtrr.c | 49 ++++++++++++++++++------------------------ 1 files changed, 21 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 9349ad4..bff6702 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -102,20 +102,6 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc } -static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) -{ - struct mem_state *state = gp; - unsigned long topk; - - topk = resk(res->base + res->size); - if (state->tom2k < topk) { - state->tom2k = topk; - } - if ((topk < 4*1024*1024) && (state->tomk < topk)) { - state->tomk = topk; - } -} - /* These will likely move to some device node or cbmem. */ static uint64_t amd_topmem = 0; static uint64_t amd_topmem2 = 0; @@ -154,6 +140,25 @@ void setup_bsp_ramtop(void) amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; } +static void setup_ap_ramtop(void) +{ + msr_t msr; + uint64_t v; + + v = bsp_topmem(); + if (!v) + return; + + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM, msr); + + v = bsp_topmem2(); + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM2, msr); +} + void amd_setup_mtrrs(void) { unsigned long address_bits; @@ -185,9 +190,6 @@ void amd_setup_mtrrs(void) state.tomk = state.tom2k = 0; search_global_resources( - IORESOURCE_MEM | IORESOURCE_UMA_FB, IORESOURCE_MEM | IORESOURCE_UMA_FB, - uma_fb_resource, &state); - search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_fixed_mtrr_resource, &state); @@ -195,20 +197,11 @@ void amd_setup_mtrrs(void) disable_cache(); - /* Round state.tomk up to the next greater size that will fit in TOP_MEM */ - state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tomk >> 22; - msr.lo = state.tomk << 10; - wrmsr(TOP_MEM, msr); + setup_ap_ramtop(); /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if(state.tom2k > (4*1024*1024)) { - /* Round state.tomk up to the next greater size that will fit in TOP_MEM2 */ - state.tom2k = (state.tom2k + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tom2k >> 22; - msr.lo = state.tom2k << 10; - wrmsr(TOP_MEM2, msr); + if (bsp_topmem2() > (uint64_t)1<<32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if(has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB; From gerrit at coreboot.org Fri Aug 3 11:40:59 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 3 Aug 2012 11:40:59 +0200 Subject: [coreboot] Patch set updated for coreboot: bddf83d AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1387 -gerrit commit bddf83d332384ea13884d481c3f2855a4fcee468 Author: Ky?sti M?lkki Date: Tue Jul 31 20:51:48 2012 +0300 AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/mtrr/amd_mtrr.c | 38 ++++++++++++++++++++ src/include/cpu/amd/mtrr.h | 5 +++ src/northbridge/amd/agesa/family10/northbridge.c | 1 + src/northbridge/amd/agesa/family12/northbridge.c | 23 +++--------- src/northbridge/amd/agesa/family14/northbridge.c | 23 +++--------- src/northbridge/amd/agesa/family15/northbridge.c | 22 +++--------- src/northbridge/amd/agesa/family15tn/northbridge.c | 23 +++--------- src/northbridge/amd/amdfam10/northbridge.c | 22 ++--------- src/northbridge/amd/amdk8/northbridge.c | 21 +++-------- 9 files changed, 74 insertions(+), 104 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index f639d59..9349ad4 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -116,6 +116,44 @@ static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) } } +/* These will likely move to some device node or cbmem. */ +static uint64_t amd_topmem = 0; +static uint64_t amd_topmem2 = 0; + +uint64_t bsp_topmem(void) +{ + return amd_topmem; +} + +uint64_t bsp_topmem2(void) +{ + return amd_topmem2; +} + +/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, + * so they can be distributed to AP CPUs. Not strictly MTRRs, + * but this is not that bad a place to have this code. + */ +void setup_bsp_ramtop(void) +{ + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk(BIOS_INFO, + "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk(BIOS_INFO, + "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + amd_topmem = (uint64_t) msr.hi<<32 | msr.lo; + amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; +} + void amd_setup_mtrrs(void) { unsigned long address_bits; diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 3637dd9..aa904e6 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -39,6 +39,11 @@ #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); + +/* To distribute topmem MSRs to APs. */ +void setup_bsp_ramtop(void); +uint64_t bsp_topmem(void); +uint64_t bsp_topmem2(void); #endif #endif /* CPU_AMD_MTRR_H */ diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 831aec0..17bcf03 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -923,6 +923,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); #if CONFIG_GFXUMA #error Northbridge does not set uma_memory_base or uma_memory_size. #endif diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f3f03a4..9f1b712 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -472,21 +472,9 @@ static void set_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family12h BKDG. */ /* Please reference MemNGetUmaSizeLN () */ /* @@ -495,19 +483,17 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ } else if (sys_mem >= 0x40000000) { uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ } else { uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -611,6 +597,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index af6dfcc..a5a6be0 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -520,24 +520,12 @@ static void domain_read_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family14h BKDG. */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ } else { @@ -548,11 +536,9 @@ static void setup_uma_memory(void) } } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -574,6 +560,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a080293..6ce73cb 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -632,20 +632,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -654,20 +643,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { + sys_mem = topmem + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 * ONE_MB)) { uma_memory_size = 512 * ONE_MB; } else if (sys_mem >= 1024 * ONE_MB) { uma_memory_size = 256 * ONE_MB; } else { uma_memory_size = 64 * ONE_MB; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -686,6 +673,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7f8650c..ba2e6c0 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -31,6 +31,7 @@ #include #include +#include #include #include @@ -641,20 +642,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -663,20 +653,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { uma_memory_size = 512 << ONE_MB_SHIFT; } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { uma_memory_size = 256 << ONE_MB_SHIFT; } else { uma_memory_size = 64 << ONE_MB_SHIFT; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -696,6 +684,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 15b29f6..386a369 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -851,22 +851,9 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - + uint32_t topmem = (uint32_t) bsp_topmem(); /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -880,11 +867,9 @@ static void setup_uma_memory(void) break; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -903,6 +888,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index bec02f0..29f4709 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -826,21 +826,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); + uint32_t topmem = (uint32_t) bsp_topmem(); #if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x2000000; /* 32M recommended UMA */ break; @@ -859,7 +849,7 @@ static void setup_uma_memory(void) } #else /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -874,11 +864,9 @@ static void setup_uma_memory(void) } #endif - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -896,6 +884,7 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if 0 From gerrit at coreboot.org Fri Aug 3 11:43:34 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 11:43:34 +0200 Subject: [coreboot] New patch to review for coreboot: bbede2e AMD S3: Remove the hardcoded volatile position References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1408 -gerrit commit bbede2e244e79735525f838ef20ec9b10a760dee Author: zbao Date: Fri Aug 3 19:29:18 2012 +0800 AMD S3: Remove the hardcoded volatile position Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/southbridge/amd/Kconfig | 5 +++++ src/southbridge/amd/Makefile.inc | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..23f6c06 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,8 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +# This can be overriden by mainboard/Kconfig +config S3_VOLATILE_POS + hex + default 0xFFFF0000 diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 733a9bc..449745a 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -20,14 +20,14 @@ ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/s3.rom: - echo " S3 NVRAM 0xffff0000 (S3 storage area)" + echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)" @ # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv s3nv-file := $(obj)/s3.rom -s3nv-position := 0xffff0000 +s3nv-position := $(CONFIG_S3_VOLATILE_POS) s3nv-type := raw endif # CONFIG_CPU_AMD_AGESA == y From gerrit at coreboot.org Fri Aug 3 12:02:03 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 3 Aug 2012 12:02:03 +0200 Subject: [coreboot] Patch set updated for coreboot: ab1ad92 AMD S3: Remove the hardcoded volatile position References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1408 -gerrit commit ab1ad9270161bec43bcee0adcff001fd0f6cd4b8 Author: zbao Date: Fri Aug 3 19:47:27 2012 +0800 AMD S3: Remove the hardcoded volatile position Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/cpu/amd/agesa/s3_resume.h | 6 +++--- src/southbridge/amd/Kconfig | 5 +++++ src/southbridge/amd/Makefile.inc | 4 ++-- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 16ec411..10bc826 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -20,9 +20,9 @@ #ifndef S3_RESUME_H #define S3_RESUME_H -#define S3_DATA_NONVOLATILE_POS 0xFFFF7000 -#define S3_DATA_VOLATILE_POS 0xFFFF0000 -#define S3_DATA_MTRR_POS 0xFFFF6000 +#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_VOLATILE_POS + 0x7000) +#define S3_DATA_VOLATILE_POS CONFIG_S3_VOLATILE_POS +#define S3_DATA_MTRR_POS (CONFIG_S3_VOLATILE_POS + 0x6000) typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..23f6c06 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,8 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +# This can be overriden by mainboard/Kconfig +config S3_VOLATILE_POS + hex + default 0xFFFF0000 diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 733a9bc..449745a 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -20,14 +20,14 @@ ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/s3.rom: - echo " S3 NVRAM 0xffff0000 (S3 storage area)" + echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)" @ # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv s3nv-file := $(obj)/s3.rom -s3nv-position := 0xffff0000 +s3nv-position := $(CONFIG_S3_VOLATILE_POS) s3nv-type := raw endif # CONFIG_CPU_AMD_AGESA == y From gerrit at coreboot.org Fri Aug 3 12:19:33 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 3 Aug 2012 12:19:33 +0200 Subject: [coreboot] Patch merged into coreboot/master: 850fd7a Intel CPUs: Fix counting of CPU cores References: Message-ID: the following patch was just integrated into master: commit 850fd7a8379c49ec961dda12c8119f405c0d3cec Author: Ky?sti M?lkki Date: Wed Jul 4 12:02:58 2012 +0300 Intel CPUs: Fix counting of CPU cores Detection for a hyper-threading CPU was not compatible with multicore CPUs. When using CPUID eax==4, also need to set ecx=0. CAR init tested on real hardware with hyper-threading model_f25 and under qemu 0.15.1 with multicore CPU. Change-Id: I28ac8790f94652e4ba8ff88fe7812c812f967608 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Tue Jul 31 22:27:13 2012, giving +1 Reviewed-By: Anton Kochkov at Fri Aug 3 12:19:31 2012, giving +2 See http://review.coreboot.org/1172 for details. -gerrit From gerrit at coreboot.org Fri Aug 3 12:25:52 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 3 Aug 2012 12:25:52 +0200 Subject: [coreboot] Patch merged into coreboot/master: ea09f9b VIA Epia-N: drop add_mainboard_resources() References: Message-ID: the following patch was just integrated into master: commit ea09f9b62ad0fe5f0a40e1bf6c76fd411c6794fa Author: Ky?sti M?lkki Date: Thu Aug 2 09:43:48 2012 +0300 VIA Epia-N: drop add_mainboard_resources() The board had HAVE_MAINBOARD_RESOURCES=0 so this was never called. Drop unnecessary includes too. Change-Id: Ia7bddf29a16966c052b5cabbb47029299e6dbd12 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Thu Aug 2 14:23:42 2012, giving +1 Reviewed-By: Anton Kochkov at Fri Aug 3 12:25:51 2012, giving +2 See http://review.coreboot.org/1392 for details. -gerrit From gerrit at coreboot.org Fri Aug 3 20:21:58 2012 From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com)) Date: Fri, 3 Aug 2012 20:21:58 +0200 Subject: [coreboot] Patch set updated for coreboot: dd9e9f1 Add a capability for mainboard-specific posting. References: Message-ID: Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1397 -gerrit commit dd9e9f1786dbdb314ce0c4244dee85357e2ae58a Author: Alexandru Gagniuc Date: Fri Aug 3 13:20:57 2012 -0500 Add a capability for mainboard-specific posting. Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case POST_TIME_TO_PARTY: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich Signed-off-by: Alexandru Gagniuc --- src/console/post.c | 15 +++++++++++++++ src/include/console/console.h | 2 ++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/src/console/post.c b/src/console/post.c index 08336a2..be2d0e9 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,6 +24,20 @@ /* Write POST information */ +/* someday romcc will be gone. */ +#ifndef __ROMCC__ +/* Some mainboards have very nice features beyond just a simple display. + * They can override this function. + */ +void __attribute__((weak)) mainboard_post(uint8_t value) +{ +} + +#else +/* This just keeps the number of #ifs to a minimum */ +#define mainboard_post(x) +#endif + void post_code(uint8_t value) { #if !CONFIG_NO_POST @@ -34,4 +48,5 @@ void post_code(uint8_t value) #endif outb(value, CONFIG_POST_PORT); #endif + mainboard_post(value); } diff --git a/src/include/console/console.h b/src/include/console/console.h index 56e202d..00be96f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -69,6 +69,8 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); void post_code(u8 value); +/* this function is weak and can be overridden by a mainboard function. */ +void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); From gerrit at coreboot.org Fri Aug 3 23:09:08 2012 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Fri, 3 Aug 2012 23:09:08 +0200 Subject: [coreboot] Patch set updated for coreboot: 866b519 Make the device tree available in the rom stage References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1398 -gerrit commit 866b519aa88a4177508d182b4c18a61b919d94c5 Author: Stefan Reinauer Date: Tue Jul 31 16:47:25 2012 -0700 Make the device tree available in the rom stage We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich Signed-off-by: Stefan Reinauer --- Makefile.inc | 5 ++ src/arch/x86/include/stddef.h | 6 ++ src/cpu/amd/agesa/s3_resume.c | 2 + src/devices/Makefile.inc | 2 + src/devices/device_romstage.c | 80 ++++++++++++++++++++++++++ src/include/device/device.h | 35 +++++++---- src/include/device/pci.h | 3 + src/include/device/resource.h | 3 +- util/lint/lint-stable-002-build-dir-handling | 17 ++++-- util/sconfig/main.c | 32 +++++++---- 10 files changed, 154 insertions(+), 31 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ca1e066..083d423 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -228,6 +228,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devi $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c +romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c $(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" @@ -237,6 +238,10 @@ $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< +$(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $< + ####################################################################### # Clean up rules clean-abuild: diff --git a/src/arch/x86/include/stddef.h b/src/arch/x86/include/stddef.h index a6c3fc6..fc89de5 100644 --- a/src/arch/x86/include/stddef.h +++ b/src/arch/x86/include/stddef.h @@ -15,4 +15,10 @@ typedef unsigned int wint_t; #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#ifdef __PRE_RAM__ +#define ROMSTAGE_CONST const +#else +#define ROMSTAGE_CONST +#endif + #endif /* I386_STDDEF_H */ diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6bb053d..0348a9f 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -29,7 +29,9 @@ #endif #include #include +#ifndef __PRE_RAM__ #include +#endif #include #include #include diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9ffc0bb..9a2f71e 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -11,6 +11,8 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c +romstage-y+= device_romstage.c + subdirs-y += oprom ifeq ($(CONFIG_PCI_ROM_RUN),y) diff --git a/src/devices/device_romstage.c b/src/devices/device_romstage.c new file mode 100644 index 0000000..475f94a --- /dev/null +++ b/src/devices/device_romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003-2004 Linux Networx + * (Written by Eric Biederman for Linux Networx) + * Copyright (C) 2003 Greg Watson + * Copyright (C) 2004 Li-Ta Lo + * Copyright (C) 2005-2006 Tyan + * (Written by Yinghai Lu for Tyan) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +/** Linked list of ALL devices */ +ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root; + +/** + * Given a PCI bus and a devfn number, find the device structure. + * + * @param bus The bus number. + * @param devfn A device/function number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus, + unsigned int devfn) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_PCI) && + (dev->bus->secondary == bus) && + (dev->path.pci.devfn == devfn)) { + result = dev; + break; + } + } + return result; +} + +/** + * Given an SMBus bus and a device number, find the device structure. + * + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus, + unsigned int addr) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_I2C) && + (dev->bus->secondary == bus) && + (dev->path.i2c.device == addr)) { + result = dev; + break; + } + } + return result; +} + diff --git a/src/include/device/device.h b/src/include/device/device.h index 0b15ac5..b44a551 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -2,11 +2,12 @@ #define DEVICE_H #include +#include #include #include - struct device; +#ifndef __PRE_RAM__ typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; @@ -42,12 +43,14 @@ struct device_operations { const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations *ops_pci_bus; }; +#endif struct bus { - device_t dev; /* This bridge device */ - device_t children; /* devices behind this bridge */ - struct bus *next; /* The next bridge on this device */ + + ROMSTAGE_CONST struct device * dev; /* This bridge device */ + ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ @@ -70,10 +73,12 @@ struct pci_irq_info { }; struct device { - struct bus * bus; /* bus this device is on, for bridge + ROMSTAGE_CONST struct bus * bus; /* bus this device is on, for bridge * devices, it is the up stream bus */ - device_t sibling; /* next device on this bus */ - device_t next; /* chain of all devices */ + + ROMSTAGE_CONST struct device * sibling; /* next device on this bus */ + + ROMSTAGE_CONST struct device * next; /* chain of all devices */ struct device_path path; unsigned vendor; @@ -89,23 +94,24 @@ struct device { u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ - struct resource *resource_list; + ROMSTAGE_CONST struct resource *resource_list; /* links are (downstream) buses attached to the device, usually a leaf * device with no children has 0 buses attached and a bridge has 1 bus */ - struct bus *link_list; + ROMSTAGE_CONST struct bus *link_list; struct device_operations *ops; const struct chip_operations *chip_ops; - void *chip_info; + ROMSTAGE_CONST void *chip_info; }; /** * This is the root of the device tree. The device tree is defined in the * static.c file and is generated by the config tool at compile time. */ -extern struct device dev_root; +extern ROMSTAGE_CONST struct device dev_root; +#ifndef __PRE_RAM__ extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; @@ -195,5 +201,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); - +#else +ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, + unsigned int devfn); +ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, + unsigned int addr); +#endif #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 51d5283..a215a2a 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -16,9 +16,11 @@ #define PCI_H #include +#include #include #include #include +#ifndef __PRE_RAM__ #include #include @@ -107,4 +109,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) unsigned mainboard_pci_subsystem_vendor_id(struct device *dev); unsigned mainboard_pci_subsystem_device_id(struct device *dev); +#endif #endif /* PCI_H */ diff --git a/src/include/device/resource.h b/src/include/device/resource.h index c28ada5..ddedc2f 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -2,6 +2,7 @@ #define DEVICE_RESOURCE_H #include +#include #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ @@ -72,7 +73,7 @@ struct resource { resource_t base; /* Base address of the resource */ resource_t size; /* Size of the resource */ resource_t limit; /* Largest valid value base + size -1 */ - struct resource* next; /* Next resource in the list */ + ROMSTAGE_CONST struct resource* next; /* Next resource in the list */ unsigned long flags; /* Descriptions of the kind of resource */ unsigned long index; /* Bus specific per device resource id */ unsigned char align; /* Required alignment (log 2) of the resource */ diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling index c4247b5..d5295d2 100755 --- a/util/lint/lint-stable-002-build-dir-handling +++ b/util/lint/lint-stable-002-build-dir-handling @@ -20,7 +20,7 @@ # $1: command to test for GNU make search_make() { -if [ -n "`$1 --version 2>&1 |grep GNU`" ]; then MAKE=$1; fi +if [ -n "`$1 --version 2>&1 | grep GNU`" ]; then MAKE=$1; fi } # if $1 and $2 differ, exit with failure @@ -33,7 +33,12 @@ fi # $1: object directory run_printall() { -$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |tr " " "\n"|grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," +$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 \ + DOTCONFIG=$TMPCONFIG obj=$1 printall | \ + sed -e "s,^ *,," -e "s,^r.mstage-objs:=,," \ + -e "s,mainboard/[^/]*/[^/]*/,.../,g" | \ + tr " " "\n" | grep "/static.*\.[co]" | sort | \ + tr '\012\015' ' ' | sed -e "s, *, ,g" -e "s, *$,," } # find GNU make @@ -54,10 +59,10 @@ $MAKE DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null # look up parent directory PARENTDIR=`dirname $PWD` -compare_output "`run_printall build`" "build/.../static.c build/.../static.ramstage.o" -compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o" -compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" -compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" +compare_output "`run_printall build`" "build/.../static.c build/.../static.c build/.../static.ramstage.o build/.../static.romstage.o" +compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o $PARENTDIR/obj/.../static.romstage.o" +compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" +compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" rm -f $TMPCONFIG diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 824bc6c..82a7491 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -366,13 +366,15 @@ void add_ioapic_info(struct device *dev, int apicid, const char *_srcpin, int ir static void pass0(FILE *fil, struct device *ptr) { if (ptr->type == device && ptr->id == 0) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", ptr->name); + if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) { - fprintf(fil, "static struct device %s;\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST static struct device %s;\n", ptr->name); if (ptr->rescnt > 0) - fprintf(fil, "struct resource %s_res[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[];\n", ptr->name); if (ptr->children || ptr->multidev) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", + ptr->name); } } @@ -382,8 +384,10 @@ static void pass1(FILE *fil, struct device *ptr) if (!ptr->used && (ptr->type == device)) { if (ptr->id != 0) fprintf(fil, "static "); - fprintf(fil, "struct device %s = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct device %s = {\n", ptr->name); + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); @@ -415,7 +419,9 @@ static void pass1(FILE *fil, struct device *ptr) if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); if (ptr->chip->chiph_exists) { + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); } if (ptr->nextdev) @@ -424,7 +430,8 @@ static void pass1(FILE *fil, struct device *ptr) } if (ptr->rescnt > 0) { int i=1; - fprintf(fil, "struct resource %s_res[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[] = {\n", + ptr->name); struct resource *r = ptr->res; while (r) { fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); @@ -441,7 +448,7 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t };\n"); } if (!ptr->used && ptr->type == device && (ptr->children || ptr->multidev)) { - fprintf(fil, "struct bus %s_links[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[] = {\n", ptr->name); if (ptr->multidev) { struct device *d = ptr; while (d) { @@ -473,8 +480,9 @@ static void pass1(FILE *fil, struct device *ptr) } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", - ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = {\n", + ptr->name_underscore, ptr->name_underscore, + ptr->id); struct reg *r = ptr->reg; while (r) { fprintf(fil, "\t.%s = %s,\n", r->key, r->value); @@ -482,7 +490,7 @@ static void pass1(FILE *fil, struct device *ptr) } fprintf(fil, "};\n\n"); } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = { };\n", ptr->name_underscore, ptr->name_underscore, ptr->id); } } @@ -617,9 +625,9 @@ int main(int argc, char** argv) { fprintf(autogen, "\n/* pass 0 */\n"); walk_device_tree(autogen, &root, pass0, NULL); fprintf(autogen, "\n/* pass 1 */\n" - "struct device *last_dev = &%s;\n", lastdev->name); + "ROMSTAGE_CONST struct device * ROMSTAGE_CONST last_dev = &%s;\n", lastdev->name); #ifdef MAINBOARDS_HAVE_CHIP_H - fprintf(autogen, "struct mainboard_config mainboard_info_0;\n"); + fprintf(autogen, "static ROMSTAGE_CONST struct mainboard_config ROMSTAGE_CONST mainboard_info_0;\n"); #endif walk_device_tree(autogen, &root, pass1, NULL); From gerrit at coreboot.org Fri Aug 3 23:48:12 2012 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Fri, 3 Aug 2012 23:48:12 +0200 Subject: [coreboot] Patch set updated for coreboot: 3bf9ed1 Make the device tree available in the rom stage References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1398 -gerrit commit 3bf9ed165efd91cb8d51e42e71528c140b4caf15 Author: Stefan Reinauer Date: Tue Jul 31 16:47:25 2012 -0700 Make the device tree available in the rom stage We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich Signed-off-by: Stefan Reinauer --- Makefile.inc | 5 ++ src/arch/x86/include/stddef.h | 6 ++ src/cpu/amd/agesa/s3_resume.c | 2 + src/devices/Makefile.inc | 2 + src/devices/device_romstage.c | 80 ++++++++++++++++++++++++++ src/ec/lenovo/pmh7/pmh7.c | 4 + src/include/device/device.h | 35 +++++++---- src/include/device/pci.h | 3 + src/include/device/resource.h | 3 +- util/lint/lint-stable-002-build-dir-handling | 17 ++++-- util/sconfig/main.c | 32 +++++++---- 11 files changed, 158 insertions(+), 31 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ca1e066..083d423 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -228,6 +228,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devi $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c +romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c $(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" @@ -237,6 +238,10 @@ $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< +$(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $< + ####################################################################### # Clean up rules clean-abuild: diff --git a/src/arch/x86/include/stddef.h b/src/arch/x86/include/stddef.h index a6c3fc6..fc89de5 100644 --- a/src/arch/x86/include/stddef.h +++ b/src/arch/x86/include/stddef.h @@ -15,4 +15,10 @@ typedef unsigned int wint_t; #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#ifdef __PRE_RAM__ +#define ROMSTAGE_CONST const +#else +#define ROMSTAGE_CONST +#endif + #endif /* I386_STDDEF_H */ diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6bb053d..0348a9f 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -29,7 +29,9 @@ #endif #include #include +#ifndef __PRE_RAM__ #include +#endif #include #include #include diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9ffc0bb..9a2f71e 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -11,6 +11,8 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c +romstage-y+= device_romstage.c + subdirs-y += oprom ifeq ($(CONFIG_PCI_ROM_RUN),y) diff --git a/src/devices/device_romstage.c b/src/devices/device_romstage.c new file mode 100644 index 0000000..475f94a --- /dev/null +++ b/src/devices/device_romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003-2004 Linux Networx + * (Written by Eric Biederman for Linux Networx) + * Copyright (C) 2003 Greg Watson + * Copyright (C) 2004 Li-Ta Lo + * Copyright (C) 2005-2006 Tyan + * (Written by Yinghai Lu for Tyan) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +/** Linked list of ALL devices */ +ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root; + +/** + * Given a PCI bus and a devfn number, find the device structure. + * + * @param bus The bus number. + * @param devfn A device/function number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus, + unsigned int devfn) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_PCI) && + (dev->bus->secondary == bus) && + (dev->path.pci.devfn == devfn)) { + result = dev; + break; + } + } + return result; +} + +/** + * Given an SMBus bus and a device number, find the device structure. + * + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus, + unsigned int addr) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_I2C) && + (dev->bus->secondary == bus) && + (dev->path.i2c.device == addr)) { + result = dev; + break; + } + } + return result; +} + diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 844e233..28f3814 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -19,8 +19,12 @@ #include #include +#ifndef __PRE_RAM__ +#ifndef __SMM__ #include #include +#endif +#endif #include #include "pmh7.h" #include "chip.h" diff --git a/src/include/device/device.h b/src/include/device/device.h index 0b15ac5..b44a551 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -2,11 +2,12 @@ #define DEVICE_H #include +#include #include #include - struct device; +#ifndef __PRE_RAM__ typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; @@ -42,12 +43,14 @@ struct device_operations { const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations *ops_pci_bus; }; +#endif struct bus { - device_t dev; /* This bridge device */ - device_t children; /* devices behind this bridge */ - struct bus *next; /* The next bridge on this device */ + + ROMSTAGE_CONST struct device * dev; /* This bridge device */ + ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ @@ -70,10 +73,12 @@ struct pci_irq_info { }; struct device { - struct bus * bus; /* bus this device is on, for bridge + ROMSTAGE_CONST struct bus * bus; /* bus this device is on, for bridge * devices, it is the up stream bus */ - device_t sibling; /* next device on this bus */ - device_t next; /* chain of all devices */ + + ROMSTAGE_CONST struct device * sibling; /* next device on this bus */ + + ROMSTAGE_CONST struct device * next; /* chain of all devices */ struct device_path path; unsigned vendor; @@ -89,23 +94,24 @@ struct device { u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ - struct resource *resource_list; + ROMSTAGE_CONST struct resource *resource_list; /* links are (downstream) buses attached to the device, usually a leaf * device with no children has 0 buses attached and a bridge has 1 bus */ - struct bus *link_list; + ROMSTAGE_CONST struct bus *link_list; struct device_operations *ops; const struct chip_operations *chip_ops; - void *chip_info; + ROMSTAGE_CONST void *chip_info; }; /** * This is the root of the device tree. The device tree is defined in the * static.c file and is generated by the config tool at compile time. */ -extern struct device dev_root; +extern ROMSTAGE_CONST struct device dev_root; +#ifndef __PRE_RAM__ extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; @@ -195,5 +201,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); - +#else +ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, + unsigned int devfn); +ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, + unsigned int addr); +#endif #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 51d5283..a215a2a 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -16,9 +16,11 @@ #define PCI_H #include +#include #include #include #include +#ifndef __PRE_RAM__ #include #include @@ -107,4 +109,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) unsigned mainboard_pci_subsystem_vendor_id(struct device *dev); unsigned mainboard_pci_subsystem_device_id(struct device *dev); +#endif #endif /* PCI_H */ diff --git a/src/include/device/resource.h b/src/include/device/resource.h index c28ada5..ddedc2f 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -2,6 +2,7 @@ #define DEVICE_RESOURCE_H #include +#include #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ @@ -72,7 +73,7 @@ struct resource { resource_t base; /* Base address of the resource */ resource_t size; /* Size of the resource */ resource_t limit; /* Largest valid value base + size -1 */ - struct resource* next; /* Next resource in the list */ + ROMSTAGE_CONST struct resource* next; /* Next resource in the list */ unsigned long flags; /* Descriptions of the kind of resource */ unsigned long index; /* Bus specific per device resource id */ unsigned char align; /* Required alignment (log 2) of the resource */ diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling index c4247b5..d5295d2 100755 --- a/util/lint/lint-stable-002-build-dir-handling +++ b/util/lint/lint-stable-002-build-dir-handling @@ -20,7 +20,7 @@ # $1: command to test for GNU make search_make() { -if [ -n "`$1 --version 2>&1 |grep GNU`" ]; then MAKE=$1; fi +if [ -n "`$1 --version 2>&1 | grep GNU`" ]; then MAKE=$1; fi } # if $1 and $2 differ, exit with failure @@ -33,7 +33,12 @@ fi # $1: object directory run_printall() { -$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |tr " " "\n"|grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," +$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 \ + DOTCONFIG=$TMPCONFIG obj=$1 printall | \ + sed -e "s,^ *,," -e "s,^r.mstage-objs:=,," \ + -e "s,mainboard/[^/]*/[^/]*/,.../,g" | \ + tr " " "\n" | grep "/static.*\.[co]" | sort | \ + tr '\012\015' ' ' | sed -e "s, *, ,g" -e "s, *$,," } # find GNU make @@ -54,10 +59,10 @@ $MAKE DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null # look up parent directory PARENTDIR=`dirname $PWD` -compare_output "`run_printall build`" "build/.../static.c build/.../static.ramstage.o" -compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o" -compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" -compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" +compare_output "`run_printall build`" "build/.../static.c build/.../static.c build/.../static.ramstage.o build/.../static.romstage.o" +compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o $PARENTDIR/obj/.../static.romstage.o" +compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" +compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" rm -f $TMPCONFIG diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 824bc6c..82a7491 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -366,13 +366,15 @@ void add_ioapic_info(struct device *dev, int apicid, const char *_srcpin, int ir static void pass0(FILE *fil, struct device *ptr) { if (ptr->type == device && ptr->id == 0) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", ptr->name); + if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) { - fprintf(fil, "static struct device %s;\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST static struct device %s;\n", ptr->name); if (ptr->rescnt > 0) - fprintf(fil, "struct resource %s_res[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[];\n", ptr->name); if (ptr->children || ptr->multidev) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", + ptr->name); } } @@ -382,8 +384,10 @@ static void pass1(FILE *fil, struct device *ptr) if (!ptr->used && (ptr->type == device)) { if (ptr->id != 0) fprintf(fil, "static "); - fprintf(fil, "struct device %s = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct device %s = {\n", ptr->name); + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); @@ -415,7 +419,9 @@ static void pass1(FILE *fil, struct device *ptr) if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); if (ptr->chip->chiph_exists) { + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); } if (ptr->nextdev) @@ -424,7 +430,8 @@ static void pass1(FILE *fil, struct device *ptr) } if (ptr->rescnt > 0) { int i=1; - fprintf(fil, "struct resource %s_res[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[] = {\n", + ptr->name); struct resource *r = ptr->res; while (r) { fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); @@ -441,7 +448,7 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t };\n"); } if (!ptr->used && ptr->type == device && (ptr->children || ptr->multidev)) { - fprintf(fil, "struct bus %s_links[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[] = {\n", ptr->name); if (ptr->multidev) { struct device *d = ptr; while (d) { @@ -473,8 +480,9 @@ static void pass1(FILE *fil, struct device *ptr) } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", - ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = {\n", + ptr->name_underscore, ptr->name_underscore, + ptr->id); struct reg *r = ptr->reg; while (r) { fprintf(fil, "\t.%s = %s,\n", r->key, r->value); @@ -482,7 +490,7 @@ static void pass1(FILE *fil, struct device *ptr) } fprintf(fil, "};\n\n"); } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = { };\n", ptr->name_underscore, ptr->name_underscore, ptr->id); } } @@ -617,9 +625,9 @@ int main(int argc, char** argv) { fprintf(autogen, "\n/* pass 0 */\n"); walk_device_tree(autogen, &root, pass0, NULL); fprintf(autogen, "\n/* pass 1 */\n" - "struct device *last_dev = &%s;\n", lastdev->name); + "ROMSTAGE_CONST struct device * ROMSTAGE_CONST last_dev = &%s;\n", lastdev->name); #ifdef MAINBOARDS_HAVE_CHIP_H - fprintf(autogen, "struct mainboard_config mainboard_info_0;\n"); + fprintf(autogen, "static ROMSTAGE_CONST struct mainboard_config ROMSTAGE_CONST mainboard_info_0;\n"); #endif walk_device_tree(autogen, &root, pass1, NULL); From gerrit at coreboot.org Sat Aug 4 01:13:30 2012 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Sat, 4 Aug 2012 01:13:30 +0200 Subject: [coreboot] New patch to review for coreboot: 4974878 bd82x6x: Add beep commands References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1410 -gerrit commit 4974878d81fa32f95dfdc5f62308a8f66926c4b1 Author: Dylan Reid Date: Fri Apr 27 11:37:33 2012 -0700 bd82x6x: Add beep commands Move beep commands to board-specific area as they need to be different for different codecs. Change-Id: I2a1ac938c49827cc816a95df10793a7e234942bf Signed-off-by: Dylan Reid --- src/mainboard/samsung/lumpy/hda_verb.h | 10 ++++++++++ src/mainboard/samsung/lumpy/mainboard.c | 4 ++++ src/mainboard/samsung/stumpy/hda_verb.h | 9 +++++++++ src/mainboard/samsung/stumpy/mainboard.c | 4 ++++ src/southbridge/intel/bd82x6x/azalia.c | 12 ++++++++++++ 5 files changed, 39 insertions(+), 0 deletions(-) diff --git a/src/mainboard/samsung/lumpy/hda_verb.h b/src/mainboard/samsung/lumpy/hda_verb.h index 732f0aa..3871aa1 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.h +++ b/src/mainboard/samsung/lumpy/hda_verb.h @@ -69,3 +69,13 @@ static const u32 mainboard_cim_verb_data[] = { 0x00a71e45, 0x00a71f43 }; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x00170500, /* power up codec */ + 0x00270500, /* power up DAC */ + 0x00670500, /* power up speaker */ + 0x00670740, /* enable speaker output */ + 0x0023B04B, /* set DAC gain */ +}; +static const u32 mainboard_pc_beep_verbs_size = + sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index e83516a..62d87b6 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -253,11 +253,15 @@ static void int15_install(void) extern const u32 * cim_verb_data; extern u32 cim_verb_data_size; +extern const u32 * pc_beep_verbs; +extern u32 pc_beep_verbs_size; static void verb_setup(void) { cim_verb_data = mainboard_cim_verb_data; cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; } static void mainboard_init(device_t dev) diff --git a/src/mainboard/samsung/stumpy/hda_verb.h b/src/mainboard/samsung/stumpy/hda_verb.h index 9a4a740..c9a49c5 100644 --- a/src/mainboard/samsung/stumpy/hda_verb.h +++ b/src/mainboard/samsung/stumpy/hda_verb.h @@ -97,3 +97,12 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771f18 }; +static const u32 mainboard_pc_beep_verbs[] = { + 0x00170500, /* power up codec */ + 0x00270500, /* power up DAC */ + 0x00670500, /* power up speaker */ + 0x00670740, /* enable speaker output */ + 0x0023B04B, /* set DAC gain */ +}; +static const u32 mainboard_pc_beep_verbs_size = + sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 246b261..c70673b 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -223,11 +223,15 @@ static void int15_install(void) extern const u32 * cim_verb_data; extern u32 cim_verb_data_size; +extern const u32 * pc_beep_verbs; +extern u32 pc_beep_verbs_size; static void verb_setup(void) { cim_verb_data = mainboard_cim_verb_data; cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; } // mainboard_enable is executed as first thing after diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index e40bbe3..a257daf 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -92,6 +92,8 @@ no_codec: const u32 * cim_verb_data = NULL; u32 cim_verb_data_size = 0; +const u32 * pc_beep_verbs = NULL; +u32 pc_beep_verbs_size = 0; static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) { @@ -218,6 +220,16 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) if (codec_mask & (1 << i)) codec_init(dev, base, i); } + + for (i = 0; i < pc_beep_verbs_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, pc_beep_verbs[i]); + + if (wait_for_valid(base) == -1) + return; + } } static void azalia_init(struct device *dev) From gerrit at coreboot.org Sat Aug 4 01:16:18 2012 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Sat, 4 Aug 2012 01:16:18 +0200 Subject: [coreboot] New patch to review for coreboot: 5c663a9 Perform additional programming requirements for SATA References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1411 -gerrit commit 5c663a9caa0c310687919dbaa6299d150ef89742 Author: Stefan Reinauer Date: Tue Jul 17 16:42:51 2012 -0700 Perform additional programming requirements for SATA In accordance to PCH EDS 14.1.35.1 Change-Id: I2e6cec6d4f49f404e33a171a8fbd6e4880327896 Signed-off-by: Stefan Reinauer --- src/southbridge/intel/bd82x6x/pch.h | 2 + src/southbridge/intel/bd82x6x/sata.c | 49 ++++++++++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index beed63a..7e67e3b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -196,6 +196,8 @@ int smbus_read_byte(unsigned device, unsigned address); #define PCB1 (1 << 1) #define PCB0 (1 << 0) +#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ +#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ /* SATA IOBP Registers */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 2e41158..fb29d73 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -27,6 +27,18 @@ typedef struct southbridge_intel_bd82x6x_config config_t; +static inline u32 sir_read(struct device *dev, int idx) +{ + pci_write_config32(dev, SATA_SIRI, idx); + return pci_read_config32(dev, SATA_SIRD); +} + +static inline void sir_write(struct device *dev, int idx, u32 value) +{ + pci_write_config32(dev, SATA_SIRI, idx); + pci_write_config32(dev, SATA_SIRD, value); +} + static void sata_init(struct device *dev) { u32 reg32; @@ -34,10 +46,10 @@ static void sata_init(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - printk(BIOS_DEBUG, "pch_sata: initializing...\n"); + printk(BIOS_DEBUG, "SATA: Initializing...\n"); if (config == NULL) { - printk(BIOS_ERR, "pch_sata: error: device not in devicetree.cb!\n"); + printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); return; } @@ -47,7 +59,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x0007); if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); + printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -85,7 +97,7 @@ static void sata_init(struct device *dev) } else if(config->sata_ahci) { u32 abar; - printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); + printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ @@ -137,7 +149,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { - printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); + printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -191,6 +203,33 @@ static void sata_init(struct device *dev) if (config->sata_port1_gen3_tx) pch_iobp_update(SATA_IOBP_SP1G3IR, 0, config->sata_port1_gen3_tx); + + /* Additional Programming Requirements */ + sir_write(dev, 0x04, 0x00001600); + sir_write(dev, 0x28, 0xa0000033); + reg32 = sir_read(dev, 0x54); + reg32 &= 0xff000000; + reg32 |= 0x5555aa; + sir_write(dev, 0x54, reg32); + sir_write(dev, 0x64, 0xcccc8484); + reg32 = sir_read(dev, 0x68); + reg32 &= 0xffff0000; + reg32 |= 0xcccc; + sir_write(dev, 0x68, reg32); + reg32 = sir_read(dev, 0x78); + reg32 &= 0x0000ffff; + reg32 |= 0x88880000; + sir_write(dev, 0x78, reg32); + sir_write(dev, 0x84, 0x001c7000); + sir_write(dev, 0x88, 0x88338822); + sir_write(dev, 0xa0, 0x001c7000); + // a4 + sir_write(dev, 0xc4, 0x0c0c0c0c); + sir_write(dev, 0xc8, 0x0c0c0c0c); + sir_write(dev, 0xd4, 0x10000000); + + pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); + pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } static void sata_enable(device_t dev) From gerrit at coreboot.org Sat Aug 4 01:28:22 2012 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Sat, 4 Aug 2012 01:28:22 +0200 Subject: [coreboot] New patch to review for coreboot: 26538f0 Sandy/Ivy Bridge and Cougar/Panther Point: Fix names References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1413 -gerrit commit 26538f0559a2ab70b085029441fc421ea3aec607 Author: Stefan Reinauer Date: Wed Jul 25 16:10:36 2012 -0700 Sandy/Ivy Bridge and Cougar/Panther Point: Fix names The names were set at various times during development, but the way the code works, you might end up with the wrong name being displayed in the logs. Instead of doing magic, just display both names for each component Change-Id: I1f8ce44d156442f5f7d717e1a2b47ed1218d4527 Signed-off-by: Stefan Reinauer --- src/northbridge/intel/sandybridge/northbridge.c | 2 +- src/southbridge/intel/bd82x6x/Kconfig | 12 ------------ src/southbridge/intel/bd82x6x/pch.c | 2 +- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b447d52..fb0b4cb 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -511,6 +511,6 @@ static void enable_dev(device_t dev) } struct chip_operations northbridge_intel_sandybridge_ops = { - CHIP_NAME("Intel i7 (Sandybridge) integrated Northbridge") + CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge") .enable_dev = enable_dev, }; diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 33dfe9d..a7d41dc 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -56,15 +56,3 @@ config SERIRQ_CONTINUOUS_MODE operated in continuous mode. endif - -if SOUTHBRIDGE_INTEL_BD82X6X -config PCH_CHIP_NAME - string - default "Cougar Point" -endif - -if SOUTHBRIDGE_INTEL_C216 -config PCH_CHIP_NAME - string - default "Panther Point" -endif diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 3c448de..d8a919d 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -405,6 +405,6 @@ void pch_enable(device_t dev) } struct chip_operations southbridge_intel_bd82x6x_ops = { - CHIP_NAME("Intel Series 6/7 (" CONFIG_PCH_CHIP_NAME ") Southbridge") + CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") .enable_dev = pch_enable, }; From gerrit at coreboot.org Sat Aug 4 01:17:14 2012 From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org)) Date: Sat, 4 Aug 2012 01:17:14 +0200 Subject: [coreboot] New patch to review for coreboot: 1829cdf Sandybridge: Fix integer overrun in romstage udelay() References: Message-ID: Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1412 -gerrit commit 1829cdfcb84662a78320b1979cb6e3b3ec2f28f6 Author: Stefan Reinauer Date: Wed Jul 25 16:15:25 2012 -0700 Sandybridge: Fix integer overrun in romstage udelay() This was broken, fixing according to related patch for i945 Change-Id: I925cd205ee5beb918181740a7b981a4209688ac6 Signed-off-by: Stefan Reinauer --- src/northbridge/intel/sandybridge/udelay.c | 20 ++++++++++++++------ 1 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 3d8ba96..2e795c7 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -23,9 +23,20 @@ #include /** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz */ +/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ +static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) +{ + tsc->lo = (a & 0xffff) * (b & 0xffff); + tsc->hi = ((tsc->lo >> 16) + + ((a & 0xffff) * (b >> 16)) + + ((b & 0xffff) * (a >> 16))); + tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); + tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); +} + void udelay(u32 us) { u32 dword; @@ -33,15 +44,12 @@ void udelay(u32 us) msr_t msr; u32 fsb = 100, divisor; u32 d; /* ticks per us */ - u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ msr = rdmsr(0xce); divisor = (msr.lo >> 8) & 0xff; - d = fsb * divisor; - - tscd.hi = us / dn; - tscd.lo = (us - tscd.hi * dn) * d; + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + multiply_to_tsc(&tscd, us, d); tsc1 = rdtsc(); dword = tsc1.lo + tscd.lo; From gerrit at coreboot.org Sat Aug 4 05:38:41 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 4 Aug 2012 05:38:41 +0200 Subject: [coreboot] Patch merged into coreboot/master: 6c493d7 AMD Parmer: Remove warning. References: Message-ID: the following patch was just integrated into master: commit 6c493d7bf800fa4e295465f28f8813477121f917 Author: zbao Date: Fri Aug 3 11:47:53 2012 +0800 AMD Parmer: Remove warning. Change-Id: I4ba2d480fa6df5ee741d887d26524b32c1901d73 Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Fri Aug 3 04:28:05 2012, giving +1 See http://review.coreboot.org/1399 for details. -gerrit From gerrit at coreboot.org Sat Aug 4 05:40:13 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 4 Aug 2012 05:40:13 +0200 Subject: [coreboot] Patch merged into coreboot/master: 8452211 SuperIO LPC47N217: Remove warnings References: Message-ID: the following patch was just integrated into master: commit 8452211aaea71a5b01b22708fa606e653f336d11 Author: zbao Date: Fri Aug 3 15:09:09 2012 +0800 SuperIO LPC47N217: Remove warnings Change-Id: Id5756f1bb748ae7bec0bcdc21804f5338e850baa Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Fri Aug 3 08:12:07 2012, giving +1 See http://review.coreboot.org/1402 for details. -gerrit From gerrit at coreboot.org Sat Aug 4 05:41:28 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 4 Aug 2012 05:41:28 +0200 Subject: [coreboot] Patch merged into coreboot/master: cbe5a5b AMD NB: Limit the device field to 5 bits. (Propagation) References: Message-ID: the following patch was just integrated into master: commit cbe5a5b90010158d78913f83817390e332894eae Author: zbao Date: Fri Aug 3 15:44:42 2012 +0800 AMD NB: Limit the device field to 5 bits. (Propagation) Apply the change http://review.coreboot.org/1264 to all the AMD northbridge. Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574 Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Fri Aug 3 08:28:06 2012, giving +1 See http://review.coreboot.org/1403 for details. -gerrit From gerrit at coreboot.org Sat Aug 4 05:42:04 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 4 Aug 2012 05:42:04 +0200 Subject: [coreboot] Patch merged into coreboot/master: 1400723 AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation) References: Message-ID: the following patch was just integrated into master: commit 14007235fe60e386584d75148ae9c65cabcae577 Author: zbao Date: Fri Aug 3 15:56:21 2012 +0800 AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation) Apply the change http://review.coreboot.org/1265 to all the AMD northbridge. Change-Id: Idf3994c1e9ec76cd19db9f740d825cf24059884f Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Fri Aug 3 08:44:28 2012, giving +1 See http://review.coreboot.org/1404 for details. -gerrit From gerrit at coreboot.org Sat Aug 4 18:05:40 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 4 Aug 2012 18:05:40 +0200 Subject: [coreboot] Patch merged into coreboot/master: 3bf9ed1 Make the device tree available in the rom stage References: Message-ID: the following patch was just integrated into master: commit 3bf9ed165efd91cb8d51e42e71528c140b4caf15 Author: Stefan Reinauer Date: Tue Jul 31 16:47:25 2012 -0700 Make the device tree available in the rom stage We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich Signed-off-by: Stefan Reinauer Build-Tested: build bot (Jenkins) at Sat Aug 4 00:06:15 2012, giving +1 Reviewed-By: Ronald G. Minnich at Sat Aug 4 18:05:34 2012, giving +2 See http://review.coreboot.org/1398 for details. -gerrit From gerrit at coreboot.org Sat Aug 4 18:06:38 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 4 Aug 2012 18:06:38 +0200 Subject: [coreboot] Patch merged into coreboot/master: 5c663a9 Perform additional programming requirements for SATA References: Message-ID: the following patch was just integrated into master: commit 5c663a9caa0c310687919dbaa6299d150ef89742 Author: Stefan Reinauer Date: Tue Jul 17 16:42:51 2012 -0700 Perform additional programming requirements for SATA In accordance to PCH EDS 14.1.35.1 Change-Id: I2e6cec6d4f49f404e33a171a8fbd6e4880327896 Signed-off-by: Stefan Reinauer Build-Tested: build bot (Jenkins) at Sat Aug 4 01:50:26 2012, giving +1 Reviewed-By: Ronald G. Minnich at Sat Aug 4 18:06:37 2012, giving +2 See http://review.coreboot.org/1411 for details. -gerrit From gerrit at coreboot.org Sat Aug 4 18:10:36 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Sat, 4 Aug 2012 18:10:36 +0200 Subject: [coreboot] Patch set updated for coreboot: 1cd3013 AMD SB: Call the rtc update if needed (Propagation) References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1406 -gerrit commit 1cd30138b5c836448b7c2b63549b0e919655904a Author: zbao Date: Fri Aug 3 16:58:53 2012 +0800 AMD SB: Call the rtc update if needed (Propagation) Apply the change http://review.coreboot.org/1390 to all the AMD southbridge. Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/southbridge/amd/cimx/sb700/late.c | 12 +++++++++++- src/southbridge/amd/cimx/sb800/late.c | 12 +++++++++++- src/southbridge/amd/cimx/sb900/late.c | 3 +++ src/southbridge/amd/sb600/lpc.c | 1 + src/southbridge/amd/sb700/lpc.c | 2 ++ src/southbridge/amd/sb800/lpc.c | 2 ++ 6 files changed, 30 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 4e51e0a..be2b8cd 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -23,6 +23,7 @@ #include #include #include /* smbus_bus_operations */ +#include #include /* printk */ #include "lpc.h" /* lpc_read_resources */ #include "Platform.h" /* Platfrom Specific Definitions */ @@ -72,11 +73,20 @@ static void lpc_enable_resources(device_t dev) printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__); } +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n"); +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = lpc_enable_resources, - .init = 0, + .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ce82b3..7286a6d 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -23,6 +23,7 @@ #include #include #include /* smbus_bus_operations */ +#include #include /* printk */ #include #include "lpc.h" /* lpc_read_resources */ @@ -120,11 +121,20 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 71c65e3..85485ed 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -22,6 +22,7 @@ #include /* device_operations */ #include #include /* smbus_bus_operations */ +#include #include /* printk */ #include "lpc.h" /* lpc_read_resources */ #include "SbPlatform.h" /* Platfrom Specific Definitions */ @@ -98,6 +99,8 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); /* SB Configure HPET base and enable bit */ //- hpetInit(sb_config, &(sb_config->BuildParameters)); + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); } diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 6f16ea8..22945a7 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -60,6 +60,7 @@ static void lpc_init(device_t dev) byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } static void sb600_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index c968927..be940e3 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -81,6 +81,8 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); } #endif + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } void set_cbmem_toc(struct cbmem_entry *toc) diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 4e2031f..3cb0789 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -67,6 +67,8 @@ static void lpc_init(device_t dev) byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } static void sb800_lpc_read_resources(device_t dev) From gerrit at coreboot.org Sat Aug 4 18:26:17 2012 From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com)) Date: Sat, 4 Aug 2012 18:26:17 +0200 Subject: [coreboot] Patch set updated for coreboot: f4d450c buildsystem: Make CPU microcode updating more configurable References: Message-ID: Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit f4d450cf2259b260d3393c6d2459a3c1747955c0 Author: Alexandru Gagniuc Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem: Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. Choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is needed by intel microcode updating. Once all intel cpus are converted to cbfs updating, this variable can go away. These files are then compiled and assembled into a binary CBFS file. The advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) Gives user more control over if and how to include microcode blobs 3) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 28 ++++----- src/cpu/Kconfig | 88 ++++++++++++++++++++++++++- src/cpu/Makefile.inc | 37 ++++++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++----- src/cpu/intel/microcode/microcode.c | 8 +- src/cpu/intel/microcode/microcode_blob.c | 22 ------- src/cpu/intel/model_206ax/Kconfig | 5 +- src/cpu/intel/model_206ax/Makefile.inc | 2 + src/cpu/intel/model_206ax/microcode_blob.c | 22 +++++++ src/include/cpu/intel/microcode.h | 2 +- 11 files changed, 169 insertions(+), 67 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 176ff67..4122bc4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm +classes-y := ramstage romstage driver smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..3b27fe3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,8 @@ +################################################################################ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich ## @@ -17,8 +19,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin -microcode_blob.bin-type = 0x53 -endif - -####################################################################### +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -123,7 +119,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -135,7 +131,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -150,7 +146,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -174,7 +170,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -185,7 +181,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -264,7 +260,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -274,7 +270,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -331,7 +327,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..1ed721f 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,90 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS - bool "Look for microcode in CBFS" +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS + bool default n + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS + default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" help - Load microcode updates from CBFS instead of compiling them in. + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage. -endif # ARCH_X86 + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select this option. + +config CPU_MICROCODE_CBFS_EXTERNAL + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. There is a push to move all microcode to CBFS, but this + change is not implemented for all CPUs. + + This option currently applies to: + - Intel SandyBridge/IvyBridge + - VIA Nano + + Microcode may be added to the ROM image at a later time with cbfstool, + if desired. + + If unsure, select "Generate from tree" + + The GOOD: + Microcode updates intend to solve issues that have been discovered + after CPU production. The expected effect is that systems work as + intended with the updated microcode, but we have also seen cases where + issues were solved by not applying microcode updates. + + The BAD: + Note that some operating system include these same microcode patches, + so you may need to also disable microcode updates in your operating + system for this option to have an effect. + + The UGLY: + A word of CAUTION: some CPUs depend on microcode updates to function + correctly. Not updating the microcode may leave the CPU operating at + less than optimal performance, or may cause outright hangups. + There are CPUs where coreboot cannot properly initialize the CPU + without microcode updates + For example, if running with the factory microcode, some Intel + SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs + will hang when changing the frequency. + + Make sure you have a way of flashing the ROM externally before + selecting this option. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..0f32ad4 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,40 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) + +cbfs-files-y += cpu_microcode_blob.bin + +cpu_microcode_blob.bin-type = 0x53 + +# External microcode file, or are we generating one ? +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) + cpu_microcode_blob.bin-file = $(CONFIG_CPU_MICROCODE_FILE) +else + cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +endif + +# In case we have more than one "source" (cough) files containing microcodem, we +# Link them together in one large blob, so that we get all the microcode updates +# in one file. This makes it easier for objcopy in the final step. +# The --entry=0 is just here to suppress the LD warning. It does not affect the +# final microcode file. +$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) + @printf " LD $(subst $(obj)/,,$(@))\n" + $(LD) -static --entry=0 $< -o $@ + +# We have a lot of useless data in the large blob, and we are only interested in +# the data section, so we only copy that part to the final microcode file +$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -j .data -O binary $< $@ + +endif diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include #include -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c deleted file mode 100644 index 69238a9..0000000 --- a/src/cpu/intel/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -unsigned microcode[] = { -#include -}; diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..1b4351e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string @@ -22,9 +22,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config MICROCODE_INCLUDE_PATH - string - default "src/cpu/intel/model_206ax" endif if CPU_INTEL_MODEL_206AX diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e9b8e6d..6ab4840 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c + cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c new file mode 100644 index 0000000..c2538e8 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include "microcode_blob.h" +}; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates); From gerrit at coreboot.org Sat Aug 4 18:15:05 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Sat, 4 Aug 2012 18:15:05 +0200 Subject: [coreboot] Patch set updated for coreboot: 403f4d6 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1407 -gerrit commit 403f4d69942e9d14e381439a8a9a5ad2471568d4 Author: zbao Date: Fri Aug 3 17:12:45 2012 +0800 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image Apply the change http://review.coreboot.org/1351 to thatcher. Change-Id: I33e7ad0cad2ae06f5934c60939d60a18444aa24e Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/mainboard/amd/thatcher/BiosCallOuts.c | 12 ++++++++++++ src/mainboard/amd/thatcher/BiosCallOuts.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 34936e0..8660e05 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -25,6 +25,7 @@ #include "OptionsIds.h" #include "heapManager.h" #include "FchPlatform.h" +#include "cbfs.h" STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -71,6 +72,9 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, + BiosHookGfxGetVbiosImage + } }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) @@ -735,3 +739,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } + +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) +{ + GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; + pVbiosImageInfo->ImagePtr = cbfs_find_file("pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM); + /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ + return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.h b/src/mainboard/amd/thatcher/BiosCallOuts.h index 1993c64..b7b9eaf 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.h +++ b/src/mainboard/amd/thatcher/BiosCallOuts.h @@ -71,6 +71,8 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* FCH OEM Config*/ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +/* Get Vbios Image */ +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); #define SB_GPIO_REG02 2 #define SB_GPIO_REG09 9 #define SB_GPIO_REG10 10 From gerrit at coreboot.org Sat Aug 4 19:34:47 2012 From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com)) Date: Sat, 4 Aug 2012 19:34:47 +0200 Subject: [coreboot] Patch set updated for coreboot: 8c292de Technexion TIM5690: drop add_mainboard_resources() References: Message-ID: Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1396 -gerrit commit 8c292de76fbe2e6495b526627cd1ce7bdf962baf Author: Ky?sti M?lkki Date: Thu Aug 2 09:44:14 2012 +0300 Technexion TIM5690: drop add_mainboard_resources() Move the POST display to take place just before jumping the payload, a bit later than before. Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112 Signed-off-by: Ky?sti M?lkki --- src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim5690/mainboard.c | 9 ++++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 404ddfe..172b478 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA - select HAVE_MAINBOARD_RESOURCES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 41147cd..b87058c 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -242,10 +242,13 @@ static void tim5690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) +void mainboard_post(u8 value) { - technexion_post_code(LED_MESSAGE_FINISH); - return 0; + switch (value) { + case POST_ENTER_ELF_BOOT: + technexion_post_code(LED_MESSAGE_FINISH); + break; + } } struct chip_operations mainboard_ops = { From gerrit at coreboot.org Sat Aug 4 19:31:22 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 4 Aug 2012 19:31:22 +0200 Subject: [coreboot] Patch merged into coreboot/master: dd9e9f1 Add a capability for mainboard-specific posting. References: Message-ID: the following patch was just integrated into master: commit dd9e9f1786dbdb314ce0c4244dee85357e2ae58a Author: Alexandru Gagniuc Date: Fri Aug 3 13:20:57 2012 -0500 Add a capability for mainboard-specific posting. Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case POST_TIME_TO_PARTY: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich Signed-off-by: Alexandru Gagniuc Build-Tested: build bot (Jenkins) at Fri Aug 3 20:56:15 2012, giving +1 Reviewed-By: Alexandru Gagniuc at Sat Aug 4 19:31:19 2012, giving +2 See http://review.coreboot.org/1397 for details. -gerrit From gerrit at coreboot.org Sat Aug 4 19:54:05 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 4 Aug 2012 19:54:05 +0200 Subject: [coreboot] Patch merged into coreboot/master: 403f4d6 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image References: Message-ID: the following patch was just integrated into master: commit 403f4d69942e9d14e381439a8a9a5ad2471568d4 Author: zbao Date: Fri Aug 3 17:12:45 2012 +0800 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image Apply the change http://review.coreboot.org/1351 to thatcher. Change-Id: I33e7ad0cad2ae06f5934c60939d60a18444aa24e Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Sat Aug 4 19:24:10 2012, giving +1 Reviewed-By: Ronald G. Minnich at Sat Aug 4 19:54:03 2012, giving +2 See http://review.coreboot.org/1407 for details. -gerrit From gerrit at coreboot.org Sat Aug 4 20:55:47 2012 From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com)) Date: Sat, 4 Aug 2012 20:55:47 +0200 Subject: [coreboot] Patch set updated for coreboot: 01d99d2 buildsystem: Make CPU microcode updating more configurable References: Message-ID: Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit 01d99d2354d17b168b1ff49939d0bc1d53570ca0 Author: Alexandru Gagniuc Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem: Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. Choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is needed by intel microcode updating. Once all intel cpus are converted to cbfs updating, this variable can go away. These files are then compiled and assembled into a binary CBFS file. The advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) Gives user more control over if and how to include microcode blobs 3) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 28 ++++----- src/cpu/Kconfig | 88 ++++++++++++++++++++++++++- src/cpu/Makefile.inc | 37 ++++++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++----- src/cpu/intel/microcode/microcode.c | 8 +- src/cpu/intel/microcode/microcode_blob.c | 22 ------- src/cpu/intel/model_206ax/Kconfig | 3 +- src/cpu/intel/model_206ax/Makefile.inc | 2 + src/cpu/intel/model_206ax/microcode_blob.c | 22 +++++++ src/include/cpu/intel/microcode.h | 2 +- 11 files changed, 169 insertions(+), 65 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 083d423..d06a24d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm +classes-y := ramstage romstage driver smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..3b27fe3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,8 @@ +################################################################################ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich ## @@ -17,8 +19,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin -microcode_blob.bin-type = 0x53 -endif - -####################################################################### +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -123,7 +119,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -135,7 +131,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -150,7 +146,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -174,7 +170,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -185,7 +181,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -264,7 +260,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -274,7 +270,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -331,7 +327,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..1ed721f 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,90 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS - bool "Look for microcode in CBFS" +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS + bool default n + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS + default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" help - Load microcode updates from CBFS instead of compiling them in. + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage. -endif # ARCH_X86 + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select this option. + +config CPU_MICROCODE_CBFS_EXTERNAL + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. There is a push to move all microcode to CBFS, but this + change is not implemented for all CPUs. + + This option currently applies to: + - Intel SandyBridge/IvyBridge + - VIA Nano + + Microcode may be added to the ROM image at a later time with cbfstool, + if desired. + + If unsure, select "Generate from tree" + + The GOOD: + Microcode updates intend to solve issues that have been discovered + after CPU production. The expected effect is that systems work as + intended with the updated microcode, but we have also seen cases where + issues were solved by not applying microcode updates. + + The BAD: + Note that some operating system include these same microcode patches, + so you may need to also disable microcode updates in your operating + system for this option to have an effect. + + The UGLY: + A word of CAUTION: some CPUs depend on microcode updates to function + correctly. Not updating the microcode may leave the CPU operating at + less than optimal performance, or may cause outright hangups. + There are CPUs where coreboot cannot properly initialize the CPU + without microcode updates + For example, if running with the factory microcode, some Intel + SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs + will hang when changing the frequency. + + Make sure you have a way of flashing the ROM externally before + selecting this option. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..0f32ad4 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,40 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) + +cbfs-files-y += cpu_microcode_blob.bin + +cpu_microcode_blob.bin-type = 0x53 + +# External microcode file, or are we generating one ? +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) + cpu_microcode_blob.bin-file = $(CONFIG_CPU_MICROCODE_FILE) +else + cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +endif + +# In case we have more than one "source" (cough) files containing microcodem, we +# Link them together in one large blob, so that we get all the microcode updates +# in one file. This makes it easier for objcopy in the final step. +# The --entry=0 is just here to suppress the LD warning. It does not affect the +# final microcode file. +$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) + @printf " LD $(subst $(obj)/,,$(@))\n" + $(LD) -static --entry=0 $< -o $@ + +# We have a lot of useless data in the large blob, and we are only interested in +# the data section, so we only copy that part to the final microcode file +$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -j .data -O binary $< $@ + +endif diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include #include -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c deleted file mode 100644 index 69238a9..0000000 --- a/src/cpu/intel/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -unsigned microcode[] = { -#include -}; diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 9cc6edd..15cbd17 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,8 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS - #select AP_IN_SIPI_WAIT + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e9b8e6d..6ab4840 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c + cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c new file mode 100644 index 0000000..c2538e8 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include "microcode_blob.h" +}; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates); From gerrit at coreboot.org Sat Aug 4 21:11:01 2012 From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com)) Date: Sat, 4 Aug 2012 21:11:01 +0200 Subject: [coreboot] Patch set updated for coreboot: b86360e Enable ROM cache for payload decompression on all boards References: Message-ID: Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1147 -gerrit commit b86360e30ae29c2caba6035f5cce3642970a8e17 Author: Ky?sti M?lkki Date: Sat Jun 30 11:42:08 2012 +0300 Enable ROM cache for payload decompression on all boards The static size of 8 MB ChromeOS defines for SPI flash would extend over write-protection control MMIO of older LPC/FWH flash, so use a configurable region size instead. Change-Id: Ife6d11a29794bdbf0463911e589e86102e9b897d Signed-off-by: Ky?sti M?lkki --- src/cpu/x86/Kconfig | 4 ---- src/cpu/x86/mtrr/mtrr.c | 8 ++++---- src/mainboard/samsung/lumpy/Kconfig | 4 ++++ src/mainboard/samsung/stumpy/Kconfig | 4 ++++ src/vendorcode/google/chromeos/Kconfig | 1 - 5 files changed, 12 insertions(+), 9 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 0eaee2e..9ac7365 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -40,10 +40,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool - default n - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a061b54..252ee30 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include @@ -484,12 +483,13 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } -#if CONFIG_CACHE_ROM +#if CONFIG_CACHE_ROM_SIZE /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ - if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(total_mtrrs - 1, (4096 - 8)*1024, 8 * 1024, + if (acpi_slp_type != 3) { + set_var_mtrr(total_mtrrs - 1, (unsigned) CACHE_ROM_BASE>>10, + CONFIG_CACHE_ROM_SIZE>>10, MTRR_TYPE_WRPROT, address_bits); } #endif diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 0835012..dd1e8d3 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -40,6 +40,10 @@ config MAX_CPUS int default 8 +config CACHE_ROM_SIZE + hex + default 0x800000 + config VGA_BIOS_FILE string default "pci8086,0106.rom" diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 18094cf..ff7aaa2 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -39,6 +39,10 @@ config MAX_CPUS int default 8 +config CACHE_ROM_SIZE + hex + default 0x800000 + config VGA_BIOS_FILE string default "pci8086,0106.rom" diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 179bbb1..f098912 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -20,7 +20,6 @@ config CHROMEOS bool default n select TPM - select CACHE_ROM help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported From gerrit at coreboot.org Sun Aug 5 05:46:39 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Sun, 5 Aug 2012 05:46:39 +0200 Subject: [coreboot] Patch set updated for coreboot: cb4673e AMD S3: Remove the hardcoded volatile position References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1408 -gerrit commit cb4673e961ca3e35564053cfc3896b476b9b8271 Author: zbao Date: Sun Aug 5 11:46:23 2012 +0800 AMD S3: Remove the hardcoded volatile position Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/cpu/amd/agesa/s3_resume.h | 6 +++--- src/southbridge/amd/Kconfig | 5 +++++ src/southbridge/amd/Makefile.inc | 4 ++-- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 16ec411..10bc826 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -20,9 +20,9 @@ #ifndef S3_RESUME_H #define S3_RESUME_H -#define S3_DATA_NONVOLATILE_POS 0xFFFF7000 -#define S3_DATA_VOLATILE_POS 0xFFFF0000 -#define S3_DATA_MTRR_POS 0xFFFF6000 +#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_VOLATILE_POS + 0x7000) +#define S3_DATA_VOLATILE_POS CONFIG_S3_VOLATILE_POS +#define S3_DATA_MTRR_POS (CONFIG_S3_VOLATILE_POS + 0x6000) typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..23f6c06 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,8 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +# This can be overriden by mainboard/Kconfig +config S3_VOLATILE_POS + hex + default 0xFFFF0000 diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 9709715..d2b9b65 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -20,14 +20,14 @@ ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/s3.rom: - echo " S3 NVRAM 0xffff0000 (S3 storage area)" + echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)" # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv s3nv-file := $(obj)/s3.rom -s3nv-position := 0xffff0000 +s3nv-position := $(CONFIG_S3_VOLATILE_POS) s3nv-type := raw endif # CONFIG_CPU_AMD_AGESA == y From gerrit at coreboot.org Sun Aug 5 05:58:57 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sun, 5 Aug 2012 05:58:57 +0200 Subject: [coreboot] Patch set updated for coreboot: 634d4a4 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1405 -gerrit commit 634d4a43cc36a51904d1b681064a8ea3d1de1252 Author: zbao Date: Fri Aug 3 16:06:08 2012 +0800 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) Apply the change http://review.coreboot.org/1263 to family15 northbridge. Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7 Signed-off-by: Zheng Bao Signed-off-by: zbao [km: rebased] Signed-off-by: Ky?sti M?lkki --- src/northbridge/amd/agesa/family15/northbridge.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d7e9521..d9a153b 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -627,7 +627,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB 0x100000 +#define ONE_MB_SHIFT 20 static void setup_uma_memory(void) { @@ -654,13 +654,13 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; + sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { + uma_memory_size = 256 << ONE_MB_SHIFT; } else { - uma_memory_size = 64 * ONE_MB; + uma_memory_size = 64 << ONE_MB_SHIFT; } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ From gerrit at coreboot.org Sun Aug 5 06:13:18 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Sun, 5 Aug 2012 06:13:18 +0200 Subject: [coreboot] Patch set updated for coreboot: eea8da7 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1405 -gerrit commit eea8da7be97e90b03adecba4b5a371eebc87a60d Author: zbao Date: Fri Aug 3 16:06:08 2012 +0800 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) Apply the change http://review.coreboot.org/1263 to family15 northbridge. Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7 Signed-off-by: Zheng Bao Signed-off-by: zbao [km: rebased] Signed-off-by: Ky?sti M?lkki --- src/northbridge/amd/agesa/family15/northbridge.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d7e9521..d9a153b 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -627,7 +627,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB 0x100000 +#define ONE_MB_SHIFT 20 static void setup_uma_memory(void) { @@ -654,13 +654,13 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; + sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { + uma_memory_size = 256 << ONE_MB_SHIFT; } else { - uma_memory_size = 64 * ONE_MB; + uma_memory_size = 64 << ONE_MB_SHIFT; } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ From gerrit at coreboot.org Sun Aug 5 06:34:19 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 5 Aug 2012 06:34:19 +0200 Subject: [coreboot] Patch merged into coreboot/master: cb4673e AMD S3: Remove the hardcoded volatile position References: Message-ID: the following patch was just integrated into master: commit cb4673e961ca3e35564053cfc3896b476b9b8271 Author: zbao Date: Sun Aug 5 11:46:23 2012 +0800 AMD S3: Remove the hardcoded volatile position Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Sun Aug 5 06:24:42 2012, giving +1 Reviewed-By: Alexandru Gagniuc at Sun Aug 5 06:34:14 2012, giving +2 See http://review.coreboot.org/1408 for details. -gerrit From gerrit at coreboot.org Sun Aug 5 06:38:33 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 5 Aug 2012 06:38:33 +0200 Subject: [coreboot] Patch merged into coreboot/master: 8c292de Technexion TIM5690: drop add_mainboard_resources() References: Message-ID: the following patch was just integrated into master: commit 8c292de76fbe2e6495b526627cd1ce7bdf962baf Author: Ky?sti M?lkki Date: Thu Aug 2 09:44:14 2012 +0300 Technexion TIM5690: drop add_mainboard_resources() Move the POST display to take place just before jumping the payload, a bit later than before. Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Sat Aug 4 21:08:22 2012, giving +1 Reviewed-By: Alexandru Gagniuc at Sat Aug 4 21:08:34 2012, giving +2 See http://review.coreboot.org/1396 for details. -gerrit From gerrit at coreboot.org Sun Aug 5 07:01:27 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 5 Aug 2012 07:01:27 +0200 Subject: [coreboot] Patch merged into coreboot/master: 1cd3013 AMD SB: Call the rtc update if needed (Propagation) References: Message-ID: the following patch was just integrated into master: commit 1cd30138b5c836448b7c2b63549b0e919655904a Author: zbao Date: Fri Aug 3 16:58:53 2012 +0800 AMD SB: Call the rtc update if needed (Propagation) Apply the change http://review.coreboot.org/1390 to all the AMD southbridge. Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f Signed-off-by: Zheng Bao Signed-off-by: zbao Build-Tested: build bot (Jenkins) at Sat Aug 4 19:04:32 2012, giving +1 Reviewed-By: Alexandru Gagniuc at Sun Aug 5 07:01:26 2012, giving +2 See http://review.coreboot.org/1406 for details. -gerrit From gerrit at coreboot.org Sun Aug 5 12:40:25 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sun, 5 Aug 2012 12:40:25 +0200 Subject: [coreboot] Patch set updated for coreboot: 4843b1f Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1388 -gerrit commit 4843b1fc22216a3c5128aca20070044b555950c3 Author: Ky?sti M?lkki Date: Sun Aug 5 12:12:05 2012 +0300 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/mtrr/amd_mtrr.c | 49 ++++++++++++++++++------------------------ 1 files changed, 21 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 9349ad4..bff6702 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -102,20 +102,6 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc } -static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) -{ - struct mem_state *state = gp; - unsigned long topk; - - topk = resk(res->base + res->size); - if (state->tom2k < topk) { - state->tom2k = topk; - } - if ((topk < 4*1024*1024) && (state->tomk < topk)) { - state->tomk = topk; - } -} - /* These will likely move to some device node or cbmem. */ static uint64_t amd_topmem = 0; static uint64_t amd_topmem2 = 0; @@ -154,6 +140,25 @@ void setup_bsp_ramtop(void) amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; } +static void setup_ap_ramtop(void) +{ + msr_t msr; + uint64_t v; + + v = bsp_topmem(); + if (!v) + return; + + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM, msr); + + v = bsp_topmem2(); + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM2, msr); +} + void amd_setup_mtrrs(void) { unsigned long address_bits; @@ -185,9 +190,6 @@ void amd_setup_mtrrs(void) state.tomk = state.tom2k = 0; search_global_resources( - IORESOURCE_MEM | IORESOURCE_UMA_FB, IORESOURCE_MEM | IORESOURCE_UMA_FB, - uma_fb_resource, &state); - search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_fixed_mtrr_resource, &state); @@ -195,20 +197,11 @@ void amd_setup_mtrrs(void) disable_cache(); - /* Round state.tomk up to the next greater size that will fit in TOP_MEM */ - state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tomk >> 22; - msr.lo = state.tomk << 10; - wrmsr(TOP_MEM, msr); + setup_ap_ramtop(); /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if(state.tom2k > (4*1024*1024)) { - /* Round state.tomk up to the next greater size that will fit in TOP_MEM2 */ - state.tom2k = (state.tom2k + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tom2k >> 22; - msr.lo = state.tom2k << 10; - wrmsr(TOP_MEM2, msr); + if (bsp_topmem2() > (uint64_t)1<<32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if(has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB; From gerrit at coreboot.org Sun Aug 5 12:40:26 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sun, 5 Aug 2012 12:40:26 +0200 Subject: [coreboot] Patch set updated for coreboot: 4d5ba2c AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1387 -gerrit commit 4d5ba2cf1ae8384b2c504b80093286843312d899 Author: Ky?sti M?lkki Date: Sun Aug 5 12:11:40 2012 +0300 AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/mtrr/amd_mtrr.c | 38 ++++++++++++++++++++ src/include/cpu/amd/mtrr.h | 5 +++ src/northbridge/amd/agesa/family10/northbridge.c | 1 + src/northbridge/amd/agesa/family12/northbridge.c | 23 +++--------- src/northbridge/amd/agesa/family14/northbridge.c | 23 +++--------- src/northbridge/amd/agesa/family15/northbridge.c | 22 +++--------- src/northbridge/amd/agesa/family15tn/northbridge.c | 23 +++--------- src/northbridge/amd/amdfam10/northbridge.c | 22 ++--------- src/northbridge/amd/amdk8/northbridge.c | 21 +++-------- 9 files changed, 74 insertions(+), 104 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index f639d59..9349ad4 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -116,6 +116,44 @@ static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) } } +/* These will likely move to some device node or cbmem. */ +static uint64_t amd_topmem = 0; +static uint64_t amd_topmem2 = 0; + +uint64_t bsp_topmem(void) +{ + return amd_topmem; +} + +uint64_t bsp_topmem2(void) +{ + return amd_topmem2; +} + +/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, + * so they can be distributed to AP CPUs. Not strictly MTRRs, + * but this is not that bad a place to have this code. + */ +void setup_bsp_ramtop(void) +{ + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk(BIOS_INFO, + "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk(BIOS_INFO, + "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + amd_topmem = (uint64_t) msr.hi<<32 | msr.lo; + amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; +} + void amd_setup_mtrrs(void) { unsigned long address_bits; diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 3637dd9..aa904e6 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -39,6 +39,11 @@ #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); + +/* To distribute topmem MSRs to APs. */ +void setup_bsp_ramtop(void); +uint64_t bsp_topmem(void); +uint64_t bsp_topmem2(void); #endif #endif /* CPU_AMD_MTRR_H */ diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 8cc9475..4b3859b 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -923,6 +923,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); #if CONFIG_GFXUMA #error Northbridge does not set uma_memory_base or uma_memory_size. #endif diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index af1d4f0..6689e71 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -476,21 +476,9 @@ static void set_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family12h BKDG. */ /* Please reference MemNGetUmaSizeLN () */ /* @@ -499,19 +487,17 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ } else if (sys_mem >= 0x40000000) { uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ } else { uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -615,6 +601,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index a03939c..875dbbb 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -524,24 +524,12 @@ static void domain_read_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family14h BKDG. */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ } else { @@ -552,11 +540,9 @@ static void setup_uma_memory(void) } } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -578,6 +564,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d9a153b..96cfca2 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -632,20 +632,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -654,20 +643,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { uma_memory_size = 512 << ONE_MB_SHIFT; } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { uma_memory_size = 256 << ONE_MB_SHIFT; } else { uma_memory_size = 64 << ONE_MB_SHIFT; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -686,6 +673,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c63890d..fb30277 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -31,6 +31,7 @@ #include #include +#include #include #include @@ -641,20 +642,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -663,20 +653,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { uma_memory_size = 512 << ONE_MB_SHIFT; } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { uma_memory_size = 256 << ONE_MB_SHIFT; } else { uma_memory_size = 64 << ONE_MB_SHIFT; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -696,6 +684,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index aa15fdd..865a3bc 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -851,22 +851,9 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - + uint32_t topmem = (uint32_t) bsp_topmem(); /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -880,11 +867,9 @@ static void setup_uma_memory(void) break; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -903,6 +888,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index bec02f0..29f4709 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -826,21 +826,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); + uint32_t topmem = (uint32_t) bsp_topmem(); #if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x2000000; /* 32M recommended UMA */ break; @@ -859,7 +849,7 @@ static void setup_uma_memory(void) } #else /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -874,11 +864,9 @@ static void setup_uma_memory(void) } #endif - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -896,6 +884,7 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if 0 From gerrit at coreboot.org Sun Aug 5 16:18:48 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 5 Aug 2012 16:18:48 +0200 Subject: [coreboot] Patch merged into coreboot/master: eea8da7 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) References: Message-ID: the following patch was just integrated into master: commit eea8da7be97e90b03adecba4b5a371eebc87a60d Author: zbao Date: Fri Aug 3 16:06:08 2012 +0800 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) Apply the change http://review.coreboot.org/1263 to family15 northbridge. Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7 Signed-off-by: Zheng Bao Signed-off-by: zbao [km: rebased] Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Sun Aug 5 07:54:56 2012, giving +1 Reviewed-By: Alexandru Gagniuc at Sun Aug 5 07:05:18 2012, giving +2 See http://review.coreboot.org/1405 for details. -gerrit From gerrit at coreboot.org Mon Aug 6 00:23:26 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 6 Aug 2012 00:23:26 +0200 Subject: [coreboot] Patch set updated for coreboot: 1873e5b AMD northbridges: replace alloc_dev() with alloc_find_dev() References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1186 -gerrit commit 1873e5b7103dbd639cce3f709d0f0d434eed5125 Author: Ky?sti M?lkki Date: Fri Jul 6 19:02:56 2012 +0300 AMD northbridges: replace alloc_dev() with alloc_find_dev() Use of alloc_find_dev() prevents creation of a device duplicates for device_path and is SMP safe. Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0 Signed-off-by: Ky?sti M?lkki --- src/northbridge/amd/agesa/family10/northbridge.c | 21 ++++++------------- src/northbridge/amd/agesa/family15/northbridge.c | 19 ++++++----------- src/northbridge/amd/agesa/family15tn/northbridge.c | 19 ++++++----------- src/northbridge/amd/amdfam10/northbridge.c | 21 ++++++------------- src/northbridge/amd/amdk8/northbridge.c | 21 ++++++------------- 5 files changed, 35 insertions(+), 66 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 8cc9475..330c545 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1393,21 +1393,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - - /* Enable the cpu if I have the processor */ if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d9a153b..a690e9c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1092,19 +1092,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, cpu_path.apic.apic_id); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - /* Enable the cpu if I have the processor */ if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; } /* Report what I have done */ diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c63890d..44d2f05 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1099,19 +1099,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, cpu_path.apic.apic_id); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - /* Enable the cpu if I have the processor */ if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; } /* Report what I have done */ diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index aa15fdd..febaa37 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1425,21 +1425,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - - /* Enable the cpu if I have the processor */ if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index bec02f0..3c69042 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1327,21 +1327,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - - /* Enable the cpu if I have the processor */ if (cpu_dev && cpu_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cpu_dev || !cpu_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; } From gerrit at coreboot.org Mon Aug 6 06:42:53 2012 From: gerrit at coreboot.org (Ricardo Martins (rasmartins@gmail.com)) Date: Mon, 6 Aug 2012 06:42:53 +0200 Subject: [coreboot] Patch set updated for coreboot: 91b69c6 IEI PM-LX2-800-R10: Added preliminary mainboard support References: Message-ID: Ricardo Martins (rasmartins at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1152 -gerrit commit 91b69c6ccd6d56368a7f6212a8c40a13662058ed Author: Ricardo Martins Date: Mon Aug 6 05:40:07 2012 +0100 IEI PM-LX2-800-R10: Added preliminary mainboard support Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050662496936266123&id=09034367569861123956 Support for the IT8888 PCI to ISA bridge will be added in a later patch. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins --- src/mainboard/iei/Kconfig | 3 + src/mainboard/iei/pm-lx2-800-r10/Kconfig | 54 ++++++++++ src/mainboard/iei/pm-lx2-800-r10/devicetree.cb | 87 +++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/irq_tables.c | 134 ++++++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/mainboard.c | 52 +++++++++ src/mainboard/iei/pm-lx2-800-r10/romstage.c | 90 ++++++++++++++++ 6 files changed, 420 insertions(+), 0 deletions(-) diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig index ea26922..0fbb617 100644 --- a/src/mainboard/iei/Kconfig +++ b/src/mainboard/iei/Kconfig @@ -31,6 +31,8 @@ config BOARD_IEI_PCISA_LX_800_R10 bool "PCISA LX-800-R10" config BOARD_IEI_PM_LX_800_R11 bool "PM LX-800-R11" +config BOARD_IEI_PM_LX2_800_R10 + bool "PM LX2-800-R10" endchoice @@ -39,6 +41,7 @@ source "src/mainboard/iei/kino-780am2-fam10/Kconfig" source "src/mainboard/iei/nova4899r/Kconfig" source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig" source "src/mainboard/iei/pm-lx-800-r11/Kconfig" +source "src/mainboard/iei/pm-lx2-800-r10/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/iei/pm-lx2-800-r10/Kconfig b/src/mainboard/iei/pm-lx2-800-r10/Kconfig new file mode 100644 index 0000000..1485c94 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/Kconfig @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +if BOARD_IEI_PM_LX2_800_R10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 + +config MAINBOARD_DIR + string + default iei/pm-lx2-800-r10 + +config MAINBOARD_PART_NUMBER + string + default "PM-LX2-800-R10" + +config IRQ_SLOT_COUNT + int + default 3 + +config PLLMSRlo + hex + default 0x07de0000 + +endif # BOARD_IEI_PM_LX2_800_R10 diff --git a/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb new file mode 100644 index 0000000..ff60894 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Video Adapter + device pci 1.2 on end # AES Security Block + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_polarity" = "0x0000ef25" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0d0c0700" + register "enable_ide_nand_flash" = "0" + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" + register "com1_enable" = "0" + register "com2_enable" = "0" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 11.0 on end # IT8888 + device pci e.0 on end # RTL8100C + device pci f.0 on # ISA Bridge + chip superio/smsc/smscsuperio # SMSC SCH3114 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + + device pnp 2e.a on # Runtime Register + io 0x60 = 0x400 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c new file mode 100644 index 0000000..2bbf218 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 11 + +/* Links */ +#define L_PIRQN 0 +#define L_PIRQA 1 +#define L_PIRQB 2 +#define L_PIRQC 3 +#define L_PIRQD 4 + +/* Bitmaps */ +#define B_LINKN (0) +#define B_LINK0 (1 << PIRQA) +#define B_LINK1 (1 << PIRQB) +#define B_LINK2 (1 << PIRQC) +#define B_LINK3 (1 << PIRQD) + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + (B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_AMD, /* Vendor */ + PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */ + 0, /* Miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0x27, /* Checksum */ + { + [0] = { /* Host bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x01 << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + }, + + [1] = { /* ISA bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0f << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [2] = { /* Ethernet */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0e << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + } + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/pm-lx2-800-r10/mainboard.c b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c new file mode 100644 index 0000000..9ba687f --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +/* SCH3114 runtime register (RTR) address. */ +#define SCH3114_RTR_ADDR (0x400) +/* H/W Monitoring register block index. */ +#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70) +/* H/W Monitoring register block data. */ +#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71) +/* H/W Monitoring Ready/Lock/Start register. */ +#define SCH3114_HWM_RLS_REG (0x40) + +static void init(struct device *dev) +{ + /* SCH3114: enable hardware monitor. */ + printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n"); + outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX); + outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("IEI PM-LX2-800-R10 Mainboard") + .enable_dev = enable_dev, +}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c new file mode 100644 index 0000000..c6b485f --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Ricardo Martins + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + /* Only DIMM0 is available. */ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#include +#include +#include +#include +#include +#include +#include + +void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Enable COM3. */ + device_t dev = PNP_DEV(0x2e, 0x0b); + u16 port = dev >> 8; + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + outb(0xaa, port); + + report_bist_failure(bist); + + pll_reset(); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); +} From gerrit at coreboot.org Mon Aug 6 07:09:56 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 6 Aug 2012 07:09:56 +0200 Subject: [coreboot] Patch set updated for coreboot: 07f63f5 AMD northbridges: rewrite CPU allocation References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1186 -gerrit commit 07f63f5bc09b65f36e5b720f2a1b829ec4f6bf00 Author: Ky?sti M?lkki Date: Fri Jul 6 19:02:56 2012 +0300 AMD northbridges: rewrite CPU allocation Use of alloc_find_dev() prevents creation of a device duplicates for device_path and is SMP safe. Reduce scope of variables to make the code more readable and in preparation for refactoring the allocation out of northbridge.c. Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0 Signed-off-by: Ky?sti M?lkki --- src/northbridge/amd/agesa/family10/northbridge.c | 46 ++++++--------- src/northbridge/amd/agesa/family14/northbridge.c | 19 +++--- src/northbridge/amd/agesa/family15/northbridge.c | 41 ++++++-------- src/northbridge/amd/agesa/family15tn/northbridge.c | 41 ++++++-------- src/northbridge/amd/amdfam10/northbridge.c | 60 ++++++++------------ src/northbridge/amd/amdk8/northbridge.c | 53 +++++++----------- 6 files changed, 104 insertions(+), 156 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 8cc9475..55be491 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1310,8 +1310,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < nodes; i++) { - device_t cdb_dev, cpu; - struct device_path cpu_path; + device_t cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1354,7 +1353,8 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cores_found = 0; // one core cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); - if (cdb_dev && cdb_dev->enabled) { + int enable_node = cdb_dev && cdb_dev->enabled; + if (enable_node) { j = pci_read_config32(cdb_dev, 0xe8); cores_found = (j >> 12) & 3; // dev is func 3 if (siblings > 3) @@ -1373,6 +1373,8 @@ static u32 cpu_bus_scan(device_t dev, u32 max) extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; + struct device_path cpu_path; + device_t cpu; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -1393,31 +1395,19 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - - /* Enable the cpu if I have the processor */ - if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { - cpu->enabled = 0; - } - - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } + /* Update CPU in devicetree. */ + if (enable_node) + cpu = alloc_find_dev(cpu_bus, &cpu_path); + else + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; + + cpu->enabled = enable_node; + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } //j } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index a03939c..1d9ef64 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -845,7 +845,6 @@ static void cpu_bus_set_resources(device_t dev) { static u32 cpu_bus_scan(device_t dev, u32 max) { device_t cpu; - struct device_path cpu_path; int apic_id, cores_found; /* There is only one node for fam14, but there may be multiple cores. */ @@ -858,18 +857,18 @@ static u32 cpu_bus_scan(device_t dev, u32 max) for (apic_id = 0; apic_id <= cores_found; apic_id++) { + struct device_path cpu_path; + cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = apic_id; cpu = alloc_find_dev(dev->link_list, &cpu_path); - if (cpu) { - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } else { - cpu->enabled = 0; - } + if (!cpu) + continue; + cpu->enabled = 1; + cpu->path.apic.node_id = 0; + cpu->path.apic.core_id = apic_id; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } return max; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d9a153b..3092735 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1000,8 +1000,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev, cpu; - struct device_path cpu_path; + device_t cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1057,6 +1056,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } else { siblings = 0; //default one core } + int enable_node = cdb_dev && cdb_dev->enabled; printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); @@ -1064,6 +1064,8 @@ static u32 cpu_bus_scan(device_t dev, u32 max) extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; + struct device_path cpu_path; + device_t cpu; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -1092,28 +1094,19 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, cpu_path.apic.apic_id); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - /* Enable the cpu if I have the processor */ - if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { - cpu->enabled = 0; - } - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } + /* Update CPU in devicetree. */ + if (enable_node) + cpu = alloc_find_dev(cpu_bus, &cpu_path); + else + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; + + cpu->enabled = enable_node; + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } //j } return max; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c63890d..36ded65 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1007,8 +1007,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev, cpu; - struct device_path cpu_path; + device_t cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1064,6 +1063,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } else { siblings = 0; //default one core } + int enable_node = cdb_dev && cdb_dev->enabled; printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); @@ -1071,6 +1071,8 @@ static u32 cpu_bus_scan(device_t dev, u32 max) extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; + struct device_path cpu_path; + device_t cpu; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -1099,28 +1101,19 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, cpu_path.apic.apic_id); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - /* Enable the cpu if I have the processor */ - if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { - cpu->enabled = 0; - } - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } + /* Update CPU in devicetree. */ + if (enable_node) + cpu = alloc_find_dev(cpu_bus, &cpu_path); + else + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; + + cpu->enabled = enable_node; + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } //j } return max; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index aa15fdd..b061acf 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1359,8 +1359,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for(i = 0; i < nodes; i++) { - device_t cdb_dev, cpu; - struct device_path cpu_path; + device_t cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1403,7 +1402,8 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cores_found = 0; // one core cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); - if (cdb_dev && cdb_dev->enabled) { + int enable_node = cdb_dev && cdb_dev->enabled; + if (enable_node) { j = pci_read_config32(cdb_dev, 0xe8); cores_found = (j >> 12) & 3; // dev is func 3 if (siblings > 3) @@ -1420,47 +1420,33 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } for (j = 0; j <=jj; j++ ) { + struct device_path cpu_path; + device_t cpu; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - - /* Enable the cpu if I have the processor */ - if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { - cpu->enabled = 0; - } - - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - #if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0) - if(sysconf.enabled_apic_ext_id) { - if(sysconf.lift_bsp_apicid) { - cpu->path.apic.apic_id += sysconf.apicid_offset; - } else - { - if (cpu->path.apic.apic_id != 0) - cpu->path.apic.apic_id += sysconf.apicid_offset; - } + /* Update CPU in devicetree. */ + if (enable_node) + cpu = alloc_find_dev(cpu_bus, &cpu_path); + else + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; + +#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0) + if(sysconf.enabled_apic_ext_id) { + if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) { + cpu->path.apic.apic_id += sysconf.apicid_offset; } - #endif - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); } +#endif + cpu->enabled = enable_node; + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } //j } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index bec02f0..a7538a6 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1250,8 +1250,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for(i = 0; i < sysconf.nodes; i++) { - device_t cpu_dev, cpu; - struct device_path cpu_path; + device_t cpu_dev; /* Find the cpu's pci device */ cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); @@ -1275,7 +1274,8 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } e0_later_single_core = 0; - if (cpu_dev && cpu_dev->enabled) { + int enable_node = cpu_dev && cpu_dev->enabled; + if (enable_node) { j = pci_read_config32(cpu_dev, 0xe8); j = (j >> 12) & 3; // dev is func 3 printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cpu_dev), j); @@ -1322,45 +1322,32 @@ static u32 cpu_bus_scan(device_t dev, u32 max) #endif for (j = 0; j <=jj; j++ ) { + struct device_path cpu_path; + device_t cpu; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); + /* Update CPU in devicetree. */ + if (enable_node) + cpu = alloc_find_dev(cpu_bus, &cpu_path); + else + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; - /* Enable the cpu if I have the processor */ - if (cpu_dev && cpu_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; + if(sysconf.enabled_apic_ext_id) { + if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) { + cpu->path.apic.apic_id += sysconf.apicid_offset; } } - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cpu_dev || !cpu_dev->enabled)) { - cpu->enabled = 0; - } - - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - if(sysconf.enabled_apic_ext_id) { - if(sysconf.lift_bsp_apicid) { - cpu->path.apic.apic_id += sysconf.apicid_offset; - } else - { - if (cpu->path.apic.apic_id != 0) - cpu->path.apic.apic_id += sysconf.apicid_offset; - } - } - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } + cpu->enabled = enable_node; + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } //j } From gerrit at coreboot.org Tue Aug 7 00:31:05 2012 From: gerrit at coreboot.org (Alexandru Gagniuc (mr.nuke.me@gmail.com)) Date: Tue, 7 Aug 2012 00:31:05 +0200 Subject: [coreboot] Patch set updated for coreboot: 4f0de5b buildsystem: Make CPU microcode updating more configurable References: Message-ID: Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit 4f0de5b92239e0c08c056413e8210b6daa241515 Author: Alexandru Gagniuc Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem: Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. Choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is needed by intel microcode updating. Once all intel cpus are converted to cbfs updating, this variable can go away. These files are then compiled and assembled into a binary CBFS file. The advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) Gives user more control over if and how to include microcode blobs 3) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 28 ++++----- src/cpu/Kconfig | 88 ++++++++++++++++++++++++++- src/cpu/Makefile.inc | 37 ++++++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++----- src/cpu/intel/microcode/microcode.c | 8 +- src/cpu/intel/microcode/microcode_blob.c | 22 ------- src/cpu/intel/model_206ax/Kconfig | 3 +- src/cpu/intel/model_206ax/Makefile.inc | 2 + src/cpu/intel/model_206ax/microcode_blob.c | 22 +++++++ src/include/cpu/intel/microcode.h | 2 +- 11 files changed, 169 insertions(+), 65 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 083d423..d06a24d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm +classes-y := ramstage romstage driver smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..3b27fe3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,8 @@ +################################################################################ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich ## @@ -17,8 +19,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin -microcode_blob.bin-type = 0x53 -endif - -####################################################################### +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -123,7 +119,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -135,7 +131,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -150,7 +146,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -174,7 +170,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -185,7 +181,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -264,7 +260,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -274,7 +270,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -331,7 +327,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..1ed721f 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,90 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS - bool "Look for microcode in CBFS" +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS + bool default n + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS + default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" help - Load microcode updates from CBFS instead of compiling them in. + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage. -endif # ARCH_X86 + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select this option. + +config CPU_MICROCODE_CBFS_EXTERNAL + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. There is a push to move all microcode to CBFS, but this + change is not implemented for all CPUs. + + This option currently applies to: + - Intel SandyBridge/IvyBridge + - VIA Nano + + Microcode may be added to the ROM image at a later time with cbfstool, + if desired. + + If unsure, select "Generate from tree" + + The GOOD: + Microcode updates intend to solve issues that have been discovered + after CPU production. The expected effect is that systems work as + intended with the updated microcode, but we have also seen cases where + issues were solved by not applying microcode updates. + + The BAD: + Note that some operating system include these same microcode patches, + so you may need to also disable microcode updates in your operating + system for this option to have an effect. + + The UGLY: + A word of CAUTION: some CPUs depend on microcode updates to function + correctly. Not updating the microcode may leave the CPU operating at + less than optimal performance, or may cause outright hangups. + There are CPUs where coreboot cannot properly initialize the CPU + without microcode updates + For example, if running with the factory microcode, some Intel + SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs + will hang when changing the frequency. + + Make sure you have a way of flashing the ROM externally before + selecting this option. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..938a8df 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,40 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) + +cbfs-files-y += cpu_microcode_blob.bin + +cpu_microcode_blob.bin-type = 0x53 + +# External microcode file, or are we generating one ? +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) +cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +else +cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +endif + +# In case we have more than one "source" (cough) files containing microcode, we +# Link them together in one large blob, so that we get all the microcode updates +# in one file. This makes it easier for objcopy in the final step. +# The --entry=0 is just here to suppress the LD warning. It does not affect the +# final microcode file. +$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) + @printf " LD $(subst $(obj)/,,$(@))\n" + $(LD) -static --entry=0 $< -o $@ + +# We have a lot of useless data in the large blob, and we are only interested in +# the data section, so we only copy that part to the final microcode file +$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -j .data -O binary $< $@ + +endif diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include #include -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c deleted file mode 100644 index 69238a9..0000000 --- a/src/cpu/intel/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -unsigned microcode[] = { -#include -}; diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 9cc6edd..15cbd17 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,8 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS - #select AP_IN_SIPI_WAIT + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e9b8e6d..6ab4840 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c + cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c new file mode 100644 index 0000000..c2538e8 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include "microcode_blob.h" +}; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates); From sambesselink at planet.nl Sun Aug 5 20:46:43 2012 From: sambesselink at planet.nl (sambesselink at planet.nl) Date: Sun, 5 Aug 2012 20:46:43 +0200 Subject: [coreboot] Support for laptop Samsung X360 Message-ID: <0D6BC2513C59184C80EF4675EDDB7FEB02F5E002@CPEXBE-EML16.kpnsp.local> Hi all, I got interested in coreboot and started reading coreboot.org. I gathered some information and am wondering what you guys think of the chances of getting to run coreboot on my laptop. Brand: Samsung Type: NP-X360-AA03NL CPU: Intel Core2 Duo SU9300 Northbridge: Intel GS45ME Southbridge: Intel ICH9M-E SuperIO: SMSC FDC37N972 EC: unknown (how do I find this?) Flash chip: MX25L1605 Flash size, type: 2048kB, SPI Running flashrom allowed me to find the flash info. It didn't throw any problems (besides moaning that it's a laptop). I can also provide the dmidecode.log, ectool.log etc and the rom.bin I read out if you would like me to. Thanks in advance for your help. Sam -------------- next part -------------- An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Tue Aug 7 01:03:42 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Aug 2012 01:03:42 +0200 Subject: [coreboot] Patch merged into coreboot/master: 5d8056e AMD RS690: mark MMCONF resource as reserved MEM References: Message-ID: the following patch was just integrated into master: commit 5d8056e1359675071eeb5e3c922423c63ead5d17 Author: Ky?sti M?lkki Date: Thu Aug 2 09:46:38 2012 +0300 AMD RS690: mark MMCONF resource as reserved MEM Use IORESOURCE_RESERVE to exclude the region from system RAM table. Change-Id: I61b51022165e1304a41554f67af75b3089d892af Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Thu Aug 2 14:40:23 2012, giving +1 Reviewed-By: Anton Kochkov at Mon Aug 6 17:01:42 2012, giving +2 See http://review.coreboot.org/1393 for details. -gerrit From gerrit at coreboot.org Tue Aug 7 01:03:44 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Aug 2012 01:03:44 +0200 Subject: [coreboot] Patch merged into coreboot/master: 4974878 bd82x6x: Add beep commands References: Message-ID: the following patch was just integrated into master: commit 4974878d81fa32f95dfdc5f62308a8f66926c4b1 Author: Dylan Reid Date: Fri Apr 27 11:37:33 2012 -0700 bd82x6x: Add beep commands Move beep commands to board-specific area as they need to be different for different codecs. Change-Id: I2a1ac938c49827cc816a95df10793a7e234942bf Signed-off-by: Dylan Reid Build-Tested: build bot (Jenkins) at Sat Aug 4 01:34:50 2012, giving +1 See http://review.coreboot.org/1410 for details. -gerrit From gerrit at coreboot.org Tue Aug 7 01:05:48 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Aug 2012 01:05:48 +0200 Subject: [coreboot] Patch merged into coreboot/master: 26538f0 Sandy/Ivy Bridge and Cougar/Panther Point: Fix names References: Message-ID: the following patch was just integrated into master: commit 26538f0559a2ab70b085029441fc421ea3aec607 Author: Stefan Reinauer Date: Wed Jul 25 16:10:36 2012 -0700 Sandy/Ivy Bridge and Cougar/Panther Point: Fix names The names were set at various times during development, but the way the code works, you might end up with the wrong name being displayed in the logs. Instead of doing magic, just display both names for each component Change-Id: I1f8ce44d156442f5f7d717e1a2b47ed1218d4527 Signed-off-by: Stefan Reinauer Build-Tested: build bot (Jenkins) at Sat Aug 4 02:23:23 2012, giving +1 See http://review.coreboot.org/1413 for details. -gerrit From gerrit at coreboot.org Tue Aug 7 06:01:24 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 7 Aug 2012 06:01:24 +0200 Subject: [coreboot] Patch set updated for coreboot: a031b9d Move cpus_ready_for_init() to AMD K8 References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1184 -gerrit commit a031b9dd760b439d681133cfe50c0e4b2ed9520b Author: Ky?sti M?lkki Date: Sat Jul 7 13:42:03 2012 +0300 Move cpus_ready_for_init() to AMD K8 The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Ky?sti M?lkki --- src/cpu/x86/Kconfig | 4 ---- src/cpu/x86/lapic/lapic_cpu_init.c | 2 -- src/include/cpu/cpu.h | 6 ------ src/mainboard/amd/pistachio/Kconfig | 1 - src/mainboard/ibm/e325/Kconfig | 1 - src/mainboard/ibm/e326/Kconfig | 1 - src/mainboard/iwill/dk8_htx/Kconfig | 1 - src/mainboard/iwill/dk8s2/Kconfig | 1 - src/mainboard/iwill/dk8x/Kconfig | 1 - src/mainboard/msi/ms9652_fam10/Kconfig | 4 ---- src/mainboard/technexion/tim8690/Kconfig | 1 - src/northbridge/amd/amdk8/Kconfig | 4 ++++ src/northbridge/amd/amdk8/amdk8.h | 2 ++ src/northbridge/amd/amdk8/northbridge.c | 3 +++ 14 files changed, 9 insertions(+), 23 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 0eaee2e..07e9d9e 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -2,10 +2,6 @@ config SERIAL_CPU_INIT bool default y -config WAIT_BEFORE_CPUS_INIT - bool - default n - config UDELAY_IO bool default y if !UDELAY_LAPIC && !UDELAY_TSC diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index d61547d..fc5a786 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -502,8 +502,6 @@ void initialize_cpus(struct bus *cpu_bus) smm_init(); #endif - cpus_ready_for_init(); - #if CONFIG_SMP #if !CONFIG_SERIAL_CPU_INIT /* start all aps at first, so we can init ECC all together */ diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index c2113c1..34ba61e 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -9,12 +9,6 @@ struct bus; void initialize_cpus(struct bus *cpu_bus); void secondary_cpu_init(void); -#if !CONFIG_WAIT_BEFORE_CPUS_INIT - #define cpus_ready_for_init() do {} while(0) -#else - void cpus_ready_for_init(void); -#endif - #if CONFIG_HAVE_SMI_HANDLER void smm_init(void); void smm_lock(void); diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index d140878..a83fbcf 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 48b93d1..2bb9db4 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 81c10ba..e93cb7e 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index 3785b11..9380ea5 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select LIFT_BSP_APIC_ID select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index 1c35cb2..6476d50 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index 9216078..e09a27b 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 7439646..886bfe1 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -161,10 +161,6 @@ config MEM_TRAIN_SEQ int default 2 -config WAIT_BEFORE_CPUS_INIT - bool - default n - config AMD_UCODE_PATCH_FILE string default "mc_patch_01000096.h" diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 293590c..6bfa814 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 70e75e9..9ea5404 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -33,6 +33,10 @@ config K8_HT_FREQ_1G_SUPPORT bool default n +config WAIT_BEFORE_CPUS_INIT + bool + default n + config MEM_TRAIN_SEQ int default 0 diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 5aa3b31..e001706 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -14,4 +14,6 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); #endif +void cpus_ready_for_init(void); + #endif /* AMDK8_H */ diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index bec02f0..b6e1a7d 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1369,6 +1369,9 @@ static u32 cpu_bus_scan(device_t dev, u32 max) static void cpu_bus_init(device_t dev) { +#if CONFIG_WAIT_BEFORE_CPUS_INIT + cpus_ready_for_init(); +#endif initialize_cpus(dev->link_list); } From gerrit at coreboot.org Tue Aug 7 06:40:42 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Aug 2012 06:40:42 +0200 Subject: [coreboot] Patch merged into coreboot/master: a031b9d Move cpus_ready_for_init() to AMD K8 References: Message-ID: the following patch was just integrated into master: commit a031b9dd760b439d681133cfe50c0e4b2ed9520b Author: Ky?sti M?lkki Date: Sat Jul 7 13:42:03 2012 +0300 Move cpus_ready_for_init() to AMD K8 The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Tue Aug 7 06:26:21 2012, giving +1 Reviewed-By: Alexandru Gagniuc at Tue Aug 7 06:40:41 2012, giving +2 See http://review.coreboot.org/1184 for details. -gerrit From gerrit at coreboot.org Tue Aug 7 06:41:16 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Aug 2012 06:41:16 +0200 Subject: [coreboot] Patch merged into coreboot/master: 33c63a5 Siemens SiteMP: drop add_mainboard_resources() References: Message-ID: the following patch was just integrated into master: commit 33c63a50343c97963cd0111818619b1f00e43298 Author: Ky?sti M?lkki Date: Thu Aug 2 09:44:03 2012 +0300 Siemens SiteMP: drop add_mainboard_resources() Use of lb_add_memory_region() is reduntant with the MMCONF resource being set as reserved. Change-Id: I747ea34823692b6966b2e50d22aea1fb89c73c25 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Thu Aug 2 14:58:12 2012, giving +1 Reviewed-By: Alexandru Gagniuc at Sat Aug 4 21:08:00 2012, giving +2 See http://review.coreboot.org/1394 for details. -gerrit From gerrit at coreboot.org Tue Aug 7 06:48:12 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 7 Aug 2012 06:48:12 +0200 Subject: [coreboot] New patch to review for coreboot: 46d9b54 Drop HAVE_MAINBOARD_RESOURCES References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1414 -gerrit commit 46d9b54674c65d28d8b0c55828d580d823f76c64 Author: Ky?sti M?lkki Date: Thu Aug 2 09:48:38 2012 +0300 Drop HAVE_MAINBOARD_RESOURCES These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Ky?sti M?lkki --- src/Kconfig | 4 ---- src/arch/x86/boot/coreboot_table.c | 4 ---- src/arch/x86/include/arch/coreboot_tables.h | 4 ---- src/mainboard/advansus/a785e-i/Kconfig | 1 - src/mainboard/advansus/a785e-i/mainboard.c | 5 ----- src/mainboard/amd/bimini_fam10/Kconfig | 1 - src/mainboard/amd/bimini_fam10/mainboard.c | 5 ----- src/mainboard/amd/dbm690t/Kconfig | 1 - src/mainboard/amd/dbm690t/mainboard.c | 5 ----- src/mainboard/amd/dinar/Kconfig | 1 - src/mainboard/amd/dinar/mainboard.c | 4 ---- src/mainboard/amd/inagua/Kconfig | 1 - src/mainboard/amd/inagua/mainboard.c | 4 ---- src/mainboard/amd/mahogany/Kconfig | 1 - src/mainboard/amd/mahogany/mainboard.c | 5 ----- src/mainboard/amd/mahogany_fam10/Kconfig | 1 - src/mainboard/amd/mahogany_fam10/mainboard.c | 5 ----- src/mainboard/amd/parmer/Kconfig | 1 - src/mainboard/amd/parmer/mainboard.c | 4 ---- src/mainboard/amd/persimmon/Kconfig | 1 - src/mainboard/amd/persimmon/mainboard.c | 5 ----- src/mainboard/amd/pistachio/mainboard.c | 5 ----- src/mainboard/amd/south_station/Kconfig | 1 - src/mainboard/amd/south_station/mainboard.c | 4 ---- src/mainboard/amd/thatcher/Kconfig | 1 - src/mainboard/amd/thatcher/mainboard.c | 4 ---- src/mainboard/amd/tilapia_fam10/Kconfig | 1 - src/mainboard/amd/tilapia_fam10/mainboard.c | 5 ----- src/mainboard/amd/torpedo/Kconfig | 1 - src/mainboard/amd/torpedo/mainboard.c | 4 ---- src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/amd/union_station/mainboard.c | 4 ---- src/mainboard/asrock/939a785gmh/Kconfig | 1 - src/mainboard/asrock/939a785gmh/mainboard.c | 5 ----- src/mainboard/asrock/e350m1/Kconfig | 1 - src/mainboard/asrock/e350m1/mainboard.c | 4 ---- src/mainboard/asus/m2v-mx_se/Kconfig | 1 - src/mainboard/asus/m2v-mx_se/mainboard.c | 5 ----- src/mainboard/asus/m5a88-v/Kconfig | 1 - src/mainboard/asus/m5a88-v/mainboard.c | 5 ----- src/mainboard/asus/mew-am/Kconfig | 1 - src/mainboard/asus/mew-am/mainboard.c | 5 ----- src/mainboard/asus/mew-vm/Kconfig | 1 - src/mainboard/asus/mew-vm/mainboard.c | 5 ----- src/mainboard/avalue/eax-785e/Kconfig | 1 - src/mainboard/avalue/eax-785e/mainboard.c | 5 ----- src/mainboard/ecs/p6iwp-fe/Kconfig | 1 - src/mainboard/ecs/p6iwp-fe/mainboard.c | 5 ----- src/mainboard/gigabyte/ma785gm/Kconfig | 1 - src/mainboard/gigabyte/ma785gm/mainboard.c | 5 ----- src/mainboard/gigabyte/ma785gmt/Kconfig | 1 - src/mainboard/gigabyte/ma785gmt/mainboard.c | 5 ----- src/mainboard/gigabyte/ma78gm/Kconfig | 1 - src/mainboard/gigabyte/ma78gm/mainboard.c | 5 ----- src/mainboard/hp/e_vectra_p2706t/Kconfig | 1 - src/mainboard/hp/e_vectra_p2706t/mainboard.c | 5 ----- src/mainboard/iei/kino-780am2-fam10/Kconfig | 1 - src/mainboard/iei/kino-780am2-fam10/mainboard.c | 5 ----- src/mainboard/intel/d810e2cb/Kconfig | 1 - src/mainboard/intel/d810e2cb/mainboard.c | 5 ----- src/mainboard/intel/eagleheights/mainboard.c | 5 ----- src/mainboard/intel/emeraldlake2/Kconfig | 1 - src/mainboard/intel/emeraldlake2/mainboard.c | 5 ----- src/mainboard/jetway/pa78vm5/Kconfig | 1 - src/mainboard/jetway/pa78vm5/mainboard.c | 5 ----- src/mainboard/kontron/kt690/Kconfig | 1 - src/mainboard/kontron/kt690/mainboard.c | 5 ----- src/mainboard/mitac/6513wu/Kconfig | 1 - src/mainboard/mitac/6513wu/mainboard.c | 5 ----- src/mainboard/msi/ms6178/Kconfig | 1 - src/mainboard/msi/ms6178/mainboard.c | 5 ----- src/mainboard/nec/powermate2000/Kconfig | 1 - src/mainboard/nec/powermate2000/mainboard.c | 5 ----- src/mainboard/rca/rm4100/Kconfig | 1 - src/mainboard/rca/rm4100/mainboard.c | 5 ----- src/mainboard/samsung/lumpy/Kconfig | 1 - src/mainboard/samsung/lumpy/mainboard.c | 5 ----- src/mainboard/samsung/stumpy/Kconfig | 1 - src/mainboard/samsung/stumpy/mainboard.c | 5 ----- src/mainboard/supermicro/h8qgi/mainboard.c | 7 ------- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 7 ------- src/mainboard/technexion/tim8690/mainboard.c | 5 ----- src/mainboard/thomson/ip1000/Kconfig | 1 - src/mainboard/thomson/ip1000/mainboard.c | 5 ----- 84 files changed, 0 insertions(+), 261 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 3453614..ccf8665 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -292,10 +292,6 @@ config HIGH_SCRATCH_MEMORY_SIZE hex default 0x0 -config HAVE_MAINBOARD_RESOURCES - bool - default n - config USE_OPTION_TABLE bool default n diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 5b5834a..9050836 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -667,10 +667,6 @@ unsigned long write_coreboot_table( /* Add reserved regions */ add_lb_reserved(mem); -#if CONFIG_HAVE_MAINBOARD_RESOURCES - add_mainboard_resources(mem); -#endif - lb_dump_memory_ranges(mem); /* Note: diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h index b177949..8fc648b 100644 --- a/src/arch/x86/include/arch/coreboot_tables.h +++ b/src/arch/x86/include/arch/coreboot_tables.h @@ -16,10 +16,6 @@ void lb_memory_range(struct lb_memory *mem, */ struct lb_memory *get_lb_mem(void); -/* defined by mainboard.c if the mainboard requires extra resources */ -int add_mainboard_resources(struct lb_memory *mem); -int add_northbridge_resources(struct lb_memory *mem); - void fill_lb_gpios(struct lb_gpios *gpios); #endif /* COREBOOT_TABLE_H */ diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 7f1d136..327a84c 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 356ea1c..27bdbd7 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -82,11 +82,6 @@ static void a785e_i_enable(device_t dev) enable_int_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("ADVANSUS A785E-I Mainboard") .enable_dev = a785e_i_enable, diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 06ed977..e38fc50 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select GENERATE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index aecb036..19cb2ba 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -133,11 +133,6 @@ static void bimini_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD Bimini Mainboard") .enable_dev = bimini_enable, diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index d1bf72f..9f0afa1 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 0121879..8511eaa 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -190,11 +190,6 @@ static void dbm690t_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD DBM690T Mainboard") .enable_dev = dbm690t_enable, diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index c81ccfa..1c123ec 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -38,7 +38,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select HAVE_ACPI_TABLES #TODO select HAVE_ACPI_RESUME diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index af70ddc..5e9e9d7 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -74,10 +74,6 @@ static void dinar_enable(device_t dev) printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME("AMD DINAR Mainboard") .enable_dev = dinar_enable, diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index a9c2de4..d2c42f4 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 9099a4d..c18e728 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -82,10 +82,6 @@ static void inagua_enable(device_t dev) set_pcie_dereset(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = inagua_enable, diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 7c91b7d..20fc190 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG select LIFT_BSP_APIC_ID select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 66d0d28..d9a1643 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -106,11 +106,6 @@ static void mahogany_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD MAHOGANY Mainboard") .enable_dev = mahogany_enable, diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index 8343fca..eed5ab2 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index d1701fd..c17ff6a 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -107,11 +107,6 @@ static void mahogany_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD MAHOGANY Mainboard") .enable_dev = mahogany_enable, diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 3212c44..a5a875f 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 095f02f..0a67726 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -47,10 +47,6 @@ static void parmer_enable(device_t dev) #endif } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = parmer_enable, diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index e1f43b1..714d1fa 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 3bf05db..079ffef 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -66,11 +66,6 @@ static void persimmon_enable(device_t dev) #endif } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 32912f4..558bbe5 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -259,11 +259,6 @@ static void pistachio_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD Pistachio Mainboard") .enable_dev = pistachio_enable, diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index c482ab0..19b295b 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index dbfce2b..efd56ae 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -82,10 +82,6 @@ static void southstation_enable(device_t dev) southstation_led_init(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = southstation_enable, diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 82a154b..c7e7e82 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index b2a01d4..b52fe30 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -64,10 +64,6 @@ static void thatcher_enable(device_t dev) #endif } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = thatcher_enable, diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index 2c29f45..75e22b3 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index f655513..b11f10b 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -284,11 +284,6 @@ static void tilapia_enable(device_t dev) set_gpio40_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD TILAPIA Mainboard") .enable_dev = tilapia_enable, diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index bc4030c..9be8df2 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 91e3ead..407077e 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -58,10 +58,6 @@ static void torpedo_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = torpedo_enable, diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index e7c2150..73f4839 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index d8324bc..5965e41 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -55,10 +55,6 @@ static void unionstation_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = unionstation_enable, diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index 245b845..2c23d45 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_MP_TABLE select HAVE_PIRQ_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select LIFT_BSP_APIC_ID diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 7526c6b..952b735 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -104,11 +104,6 @@ static void mb_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("Asrock 939A785GMH/128M Mainboard") .enable_dev = mb_enable, diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 6f4ce0f..60de486 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 9a76cce..33f7d60 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -54,10 +54,6 @@ static void e350m1_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = e350m1_enable, diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 72fa803..de5511e 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select VGA select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select QRANK_DIMM_SUPPORT select SET_FIDVID # TODO test on multicore machines and enable if it works: diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c index 5e3c720..774a0d3 100644 --- a/src/mainboard/asus/m2v-mx_se/mainboard.c +++ b/src/mainboard/asus/m2v-mx_se/mainboard.c @@ -23,11 +23,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("ASUS M2V-MX SE Mainboard") }; diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 9cadcde..86fe51a 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index bbb1482..2c27fa7 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -83,11 +83,6 @@ static void m5a88pm_v_enable(device_t dev) enable_int_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("ASUS M5A88-V Mainboard") .enable_dev = m5a88pm_v_enable, diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig index 68ac160..fe90d22 100644 --- a/src/mainboard/asus/mew-am/Kconfig +++ b/src/mainboard/asus/mew-am/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/asus/mew-am/mainboard.c b/src/mainboard/asus/mew-am/mainboard.c index 6409dab..4346b5a 100644 --- a/src/mainboard/asus/mew-am/mainboard.c +++ b/src/mainboard/asus/mew-am/mainboard.c @@ -21,11 +21,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("ASUS MEW-AM Mainboard") }; diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig index 4e46192..21b7311 100644 --- a/src/mainboard/asus/mew-vm/Kconfig +++ b/src/mainboard/asus/mew-vm/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/asus/mew-vm/mainboard.c b/src/mainboard/asus/mew-vm/mainboard.c index 2e43be2..6fd8d3e 100644 --- a/src/mainboard/asus/mew-vm/mainboard.c +++ b/src/mainboard/asus/mew-vm/mainboard.c @@ -1,11 +1,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("ASUS MEW-VM Mainboard") }; diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index aabd724..2b4182b 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 0cc655e..6c14a71 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -82,11 +82,6 @@ static void eax_785e(device_t dev) enable_int_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = eax_785e, diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index 7d377f4..95bd1c5 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/ecs/p6iwp-fe/mainboard.c b/src/mainboard/ecs/p6iwp-fe/mainboard.c index 667ac5e..d45c8ec 100644 --- a/src/mainboard/ecs/p6iwp-fe/mainboard.c +++ b/src/mainboard/ecs/p6iwp-fe/mainboard.c @@ -21,11 +21,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("ECS P6IWP-Fe Mainboard") }; diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index 0e8011b..f4603f8 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index c65fbb6..fef1903 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -144,11 +144,6 @@ static void ma785gm_enable(device_t dev) set_gpio40_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE MA785GM-US2H Mainboard") .enable_dev = ma785gm_enable, diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 0605a39..ebe1e57 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 3c26c6a..89e75e7 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -255,11 +255,6 @@ static void ma785gmt_enable(device_t dev) set_gpio40_gfx(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE MA785GMT-UD2H Mainboard") .enable_dev = ma785gmt_enable, diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index 1b6966e..dcba4af 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index ba9baf4..402e586 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -80,11 +80,6 @@ static void ma78gm_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE MA78GM-US2H") .enable_dev = ma78gm_enable, diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index 5fab95a..18ff961 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/hp/e_vectra_p2706t/mainboard.c b/src/mainboard/hp/e_vectra_p2706t/mainboard.c index 80e6f61..4d2e0ab 100644 --- a/src/mainboard/hp/e_vectra_p2706t/mainboard.c +++ b/src/mainboard/hp/e_vectra_p2706t/mainboard.c @@ -21,11 +21,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("HP e-Vectra P2706T Mainboard") }; diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index 01a2429..73279bc 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index 44cbfcd..75ca17b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -62,11 +62,6 @@ static void kino_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("IEI Kino-780AM2 Mainboard") .enable_dev = kino_enable, diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig index 8c6c76b..0725c58 100644 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ b/src/mainboard/intel/d810e2cb/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select USE_WATCHDOG_ON_BOOT select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/intel/d810e2cb/mainboard.c b/src/mainboard/intel/d810e2cb/mainboard.c index 8455377..9db723b 100644 --- a/src/mainboard/intel/d810e2cb/mainboard.c +++ b/src/mainboard/intel/d810e2cb/mainboard.c @@ -20,11 +20,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("Intel D810E2CB Mainboard") }; diff --git a/src/mainboard/intel/eagleheights/mainboard.c b/src/mainboard/intel/eagleheights/mainboard.c index d6bc10f..7b27358 100644 --- a/src/mainboard/intel/eagleheights/mainboard.c +++ b/src/mainboard/intel/eagleheights/mainboard.c @@ -24,11 +24,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("Intel Eagle Heights Mainboard") }; diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 873d273..aaca694 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 796f71e..71832e7 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -42,11 +42,6 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - #if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE static int int15_handler(struct eregs *regs) { diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index fa39039..08f4355 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 3c4d872..5b09596 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -109,11 +109,6 @@ static void pa78vm5_enable(device_t dev) /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("AMD PA78VM5 Mainboard") .enable_dev = pa78vm5_enable, diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 6a1909f..bac8b60 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES select GFXUMA select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index 4eb638f..ebbf45a 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -190,11 +190,6 @@ static void kt690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("Kontron KT690/mITX Mainboard") .enable_dev = kt690_enable, diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index fac565e..f09f54f 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/mitac/6513wu/mainboard.c b/src/mainboard/mitac/6513wu/mainboard.c index 04af449..3322ef3 100644 --- a/src/mainboard/mitac/6513wu/mainboard.c +++ b/src/mainboard/mitac/6513wu/mainboard.c @@ -21,11 +21,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("Mitac 6513WU Mainboard") }; diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig index 1d45464..38ca830 100644 --- a/src/mainboard/msi/ms6178/Kconfig +++ b/src/mainboard/msi/ms6178/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/msi/ms6178/mainboard.c b/src/mainboard/msi/ms6178/mainboard.c index 76c8c04..795d2d3 100644 --- a/src/mainboard/msi/ms6178/mainboard.c +++ b/src/mainboard/msi/ms6178/mainboard.c @@ -21,11 +21,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS-6178 Mainboard") }; diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index 55050c0..8c2070a 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select GFXUMA config MAINBOARD_DIR diff --git a/src/mainboard/nec/powermate2000/mainboard.c b/src/mainboard/nec/powermate2000/mainboard.c index 3bbaa11..40390af 100644 --- a/src/mainboard/nec/powermate2000/mainboard.c +++ b/src/mainboard/nec/powermate2000/mainboard.c @@ -21,11 +21,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("NEC PowerMate 2000 Mainboard") }; diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig index 1e4498a..5247a8c 100644 --- a/src/mainboard/rca/rm4100/Kconfig +++ b/src/mainboard/rca/rm4100/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 - select HAVE_MAINBOARD_RESOURCES select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index ff98977..663e82b 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -22,11 +22,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - static void mainboard_init(device_t dev) { // TODO Switch parport LEDs again diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 0835012..86cb31b 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select HAVE_MAINBOARD_RESOURCES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MMCONF_SUPPORT diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 62d87b6..e54b861 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -49,11 +49,6 @@ void mainboard_suspend_resume(void) send_ec_command(EC_ACPI_ENABLE); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - #if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE static int int15_handler(struct eregs *regs) { diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 18094cf..f16809f 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select HAVE_MAINBOARD_RESOURCES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MMCONF_SUPPORT diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index c70673b..7922fcd 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -42,11 +42,6 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - #if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE static int int15_handler(struct eregs *regs) { diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index 1f02c73..c4c9180 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -71,13 +71,6 @@ static void h8qgi_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } -#if CONFIG_HAVE_MAINBOARD_RESOURCES -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} -#endif - struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = h8qgi_enable, diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index e5a58fe..e957c96 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -92,13 +92,6 @@ static void h8scm_enable(device_t dev) /* get_ide_dma66(); */ } -#if CONFIG_HAVE_MAINBOARD_RESOURCES -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} -#endif - struct chip_operations mainboard_ops = { CHIP_NAME("AMD H8SCM Mainboard") .enable_dev = h8scm_enable, diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 298132b..87f6147 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -149,11 +149,6 @@ static void tim8690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - struct chip_operations mainboard_ops = { CHIP_NAME("TechNexion TIM-8690 Mainboard") .enable_dev = tim8690_enable, diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig index 3bdfb8e..f9bbfa5 100644 --- a/src/mainboard/thomson/ip1000/Kconfig +++ b/src/mainboard/thomson/ip1000/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_MAINBOARD_RESOURCES select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index ae5872d..ac06b25 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -28,11 +28,6 @@ #include #include -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} - // setting the bit disables the led. #define PARPORT_GPIO_LED_GREEN (1 << 0) #define PARPORT_GPIO_LED_ORANGE (1 << 1) From gerrit at coreboot.org Tue Aug 7 06:50:01 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 7 Aug 2012 06:50:01 +0200 Subject: [coreboot] New patch to review for coreboot: 273e929 Do not allow modifying memory table directly References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1415 -gerrit commit 273e92999ff827454d12bc121bc2cf7e8e0db9f5 Author: Ky?sti M?lkki Date: Thu Aug 2 09:49:11 2012 +0300 Do not allow modifying memory table directly Adding ranges directly into coreboot memory table raised issues as those methods bypassed the MTRR setup. Such regions are now added as resources, so declare the functions again as static. Change-Id: If78613da40eabc5c99c49dbe2d6047cb22a71b69 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/boot/coreboot_table.c | 5 ++--- src/arch/x86/include/arch/coreboot_tables.h | 3 --- src/include/boot/tables.h | 3 --- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 9050836..d056837 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -338,7 +338,7 @@ static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header } #endif -void lb_memory_range(struct lb_memory *mem, +static void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size) { int entries; @@ -503,8 +503,7 @@ static void lb_remove_memory_range(struct lb_memory *mem, } } -/* This function is used in mainboard specific code, too */ -void lb_add_memory_range(struct lb_memory *mem, +static void lb_add_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size) { lb_remove_memory_range(mem, start, size); diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h index 8fc648b..e9790db 100644 --- a/src/arch/x86/include/arch/coreboot_tables.h +++ b/src/arch/x86/include/arch/coreboot_tables.h @@ -8,9 +8,6 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -void lb_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - /* Routines to extract part so the coreboot table or information * from the coreboot table. */ diff --git a/src/include/boot/tables.h b/src/include/boot/tables.h index 4b3f70c..869da26 100644 --- a/src/include/boot/tables.h +++ b/src/include/boot/tables.h @@ -4,9 +4,6 @@ #include #include -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - struct lb_memory *write_tables(void); #endif /* BOOT_TABLES_H */ From gerrit at coreboot.org Tue Aug 7 06:57:39 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 7 Aug 2012 06:57:39 +0200 Subject: [coreboot] Patch set updated for coreboot: b3a77bf Cleanup coreboot memory table includes References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1391 -gerrit commit b3a77bf36a1d3ccf0bf0f11d6a003519f0b9e303 Author: Ky?sti M?lkki Date: Thu Aug 2 11:52:22 2012 +0300 Cleanup coreboot memory table includes The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Ky?sti M?lkki --- src/mainboard/advansus/a785e-i/mainboard.c | 1 - src/mainboard/amd/bimini_fam10/mainboard.c | 1 - src/mainboard/amd/dbm690t/mainboard.c | 1 - src/mainboard/amd/dinar/mainboard.c | 1 - src/mainboard/amd/inagua/mainboard.c | 1 - src/mainboard/amd/mahogany/mainboard.c | 1 - src/mainboard/amd/mahogany_fam10/mainboard.c | 1 - src/mainboard/amd/parmer/mainboard.c | 1 - src/mainboard/amd/persimmon/mainboard.c | 1 - src/mainboard/amd/pistachio/mainboard.c | 1 - src/mainboard/amd/south_station/mainboard.c | 1 - src/mainboard/amd/thatcher/mainboard.c | 1 - src/mainboard/amd/tilapia_fam10/mainboard.c | 1 - src/mainboard/amd/torpedo/mainboard.c | 1 - src/mainboard/amd/union_station/mainboard.c | 1 - src/mainboard/asrock/939a785gmh/mainboard.c | 1 - src/mainboard/asrock/e350m1/mainboard.c | 1 - src/mainboard/asus/dsbf/mainboard.c | 2 -- src/mainboard/asus/m2v-mx_se/mainboard.c | 1 - src/mainboard/asus/m5a88-v/mainboard.c | 1 - src/mainboard/asus/mew-am/mainboard.c | 1 - src/mainboard/asus/mew-vm/mainboard.c | 1 - src/mainboard/avalue/eax-785e/mainboard.c | 1 - src/mainboard/ecs/p6iwp-fe/mainboard.c | 1 - src/mainboard/getac/p470/mainboard.c | 1 - src/mainboard/gigabyte/ma785gm/mainboard.c | 1 - src/mainboard/gigabyte/ma785gmt/mainboard.c | 1 - src/mainboard/gigabyte/ma78gm/mainboard.c | 1 - src/mainboard/hp/e_vectra_p2706t/mainboard.c | 1 - src/mainboard/ibase/mb899/mainboard.c | 2 -- src/mainboard/iei/kino-780am2-fam10/mainboard.c | 1 - src/mainboard/intel/d810e2cb/mainboard.c | 1 - src/mainboard/intel/d945gclf/mainboard.c | 2 -- src/mainboard/intel/eagleheights/mainboard.c | 2 -- src/mainboard/intel/emeraldlake2/chromeos.c | 1 - src/mainboard/iwave/iWRainbowG6/mainboard.c | 1 - src/mainboard/jetway/pa78vm5/mainboard.c | 1 - src/mainboard/kontron/kt690/mainboard.c | 1 - src/mainboard/lenovo/t60/dock.c | 1 - src/mainboard/lenovo/t60/mainboard.c | 2 -- src/mainboard/lenovo/x60/dock.c | 1 - src/mainboard/lenovo/x60/mainboard.c | 2 -- src/mainboard/mitac/6513wu/mainboard.c | 1 - src/mainboard/msi/ms6178/mainboard.c | 1 - src/mainboard/nec/powermate2000/mainboard.c | 1 - src/mainboard/rca/rm4100/mainboard.c | 2 -- src/mainboard/roda/rk886ex/mainboard.c | 2 -- src/mainboard/samsung/lumpy/chromeos.c | 1 - src/mainboard/samsung/stumpy/chromeos.c | 1 - src/mainboard/siemens/sitemp_g1p1/mainboard.c | 1 - src/mainboard/supermicro/h8qgi/mainboard.c | 1 - src/mainboard/supermicro/h8scm_fam10/mainboard.c | 1 - src/mainboard/supermicro/x7db8/mainboard.c | 2 -- src/mainboard/technexion/tim5690/mainboard.c | 1 - src/mainboard/technexion/tim8690/mainboard.c | 1 - src/mainboard/thomson/ip1000/mainboard.c | 2 -- src/northbridge/intel/i5000/northbridge.c | 1 - src/northbridge/intel/i82810/northbridge.c | 1 - src/northbridge/intel/i82830/northbridge.c | 1 - src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/sandybridge/northbridge.c | 1 - src/northbridge/intel/sch/northbridge.c | 1 - src/southbridge/amd/rs690/cmn.c | 1 - src/southbridge/amd/rs780/cmn.c | 1 - 64 files changed, 0 insertions(+), 74 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 27bdbd7..44def89 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 19cb2ba..d18a24e 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 8511eaa..fe441e9 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 5e9e9d7..ea196ed 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index c18e728..e71e5b6 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index d9a1643..b292d33 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index c17ff6a..c0e7c34 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.