From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.0.1355070886.16123.coreboot@coreboot.org>

this point LLNL and linuxnetworx are building a 1000+ node linux cluster
using linuxbios machines.

> >   - What are the main benefits in using LinuxBIOS?

maintainable clusters
maintainable systems
fast boot (matters to some people)
better control of the system
LinuxBIOS in many cases does a better job of chipset config


>     Not as flexible as a normal BIOS.

well, not really true in all cases. Check out the cwlinux offering, where
flash boots into busybox linux. NO BIOS is that flexible!

>     Requires hardware and chipset documentation, it's hard to keep up
>     with the hardware development..

true for now, although at least two motherboard vendors are plannning to
support linuxbios.

>     Hard to handle PCI cards with expansion ROMs on them that expect a
>     standard PC BIOS.

partially true, but getting better.

> >   - What chipsets are supported by LinuxBIOS today?
> Is there a list of supported chipsets?
ls src/*bridge*/*/*

ron



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1.1355070887.16123.coreboot@coreboot.org>

what you are talking about so you should do fine.  Good Luck.

Eric


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2.1355070888.16123.coreboot@coreboot.org>


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.3.1355070888.16123.coreboot@coreboot.org>

Does this look like a problem with BIOS or could this chipset be one that 
linux doesn't fully support yet?  The customer bought it and had it sent to 
the server farm that will be hosting it so its not available to either of us. 
 Yes, I know, why aren't we using scsi for a server.  I would if I could.

GO

<Jerle> [root at taenaria root]# hdparm -d1 /dev/hda
<Jerle> /dev/hda:
<Jerle>  setting using_dma to 1 (on)
<Jerle>  HDIO_SET_DMA failed: Operation not permitted
<Jerle>  using_dma    =  0 (off)
<Jerle> [root at taenaria root]#
<[GNU]Order> type lspci
<Jerle> [root at taenaria root]# lspci
<Jerle> 00:00.0 Host bridge: Intel Corp. e7500 DRAM Controller (rev 02)
<Jerle> 00:02.0 PCI bridge: Intel Corp. e7500 HI_B Virtual PCI-to-PCI Bridge 
(F0) (rev 02)
<Jerle> 00:1d.0 USB Controller: Intel Corp. 82801CA/CAM USB (Hub  (rev 02)
<Jerle> 00:1e.0 PCI bridge: Intel Corp. 82801BA/CA PCI Bridge (rev 42)
<Jerle> 00:1f.0 ISA bridge: Intel Corp. 82801CA ISA Bridge (LPC) (rev 02)
<Jerle> 00:1f.1 IDE interface: Intel Corp. 82801CA IDE U100 (rev 02)
<Jerle> 00:1f.3 SMBus: Intel Corp. 82801CA/CAM SMBus (rev 02)
<Jerle> 01:02.0 VGA compatible controller: ATI Technologies Inc Rage XL (rev 
27)
<Jerle> 01:03.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] 
(rev 0c)
<Jerle> 02:1c.0 PIC: Intel Corp. 82870P2 P64H2 I/OxAPIC (rev 03)
<Jerle> 02:1d.0 PCI bridge: Intel Corp. 82870P2 P64H2 Hub PCI Bridge (rev 03)
<Jerle> 02:1e.0 PIC: Intel Corp. 82870P2 P64H2 I/OxAPIC (rev 03)
<Jerle> 02:1f.0 PCI bridge: Intel Corp. 82870P2 P64H2 Hub PCI Bridge (rev 03)
<Jerle> 04:01.0 Ethernet controller: Intel Corp. 82544EI Gigabit Ethernet 
Controller (rev 02)
<Jerle> PCI: Device 00:1f.1 not available because of resource collisions
<Jerle> ICH3: (ide_setup_pci_device:) Could not enable device.
<[GNU]Order> with lspci you got that last error?
<Jerle> no, that was out of the dmesg
<[GNU]Order> oh
<Jerle> Just reprinting for reference.
<[GNU]Order> the resource collisions one too?
<Jerle> yes


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.4.1355070894.16123.coreboot@coreboot.org>

On Thu, Nov 14, 2002 at 09:29:27AM -0500, McCarty, Paul wrote:
> Why can't we just tweak the linux kernel a little to do more aggressive
> disk caching? Or make use of RAM disks to keep things off the disk until
> we want to save things? for wearable applications compact disk space is
> more expensive then RAM:
<rest deleted>




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.5.1355070895.16123.coreboot@coreboot.org>

that it is declared valid.  If I examine code at 0x400000 it seems to be 
correct, meaning that it did copy the code over there.

The processor never gets up there though.  From tracing through the image it 
seems that the adjustment for Linuxbios' image in high memory is all messed 
up.

After editing loglevel.h to allow "spew" level printks, the following is 
visible (I could see it throught the bochs debugger, but this just verifies 
that I'm not totally crazy.  :-)

Loaded segments
verified segments
closed down stream
Jumping to boot code at 0x400000
entry    = 0x00400000
lb_start = 0x00004000
lb_size  = 0x0004e2d0
adjust   = 0x3fbadd30
buffer   = 0x3fb63a60
     elf_boot_notes = 0x0000bc40
adjusted_boot_notes = 0x3fbb9970

now adjust and buffer are both waaaaaaaaaaaaaay beyond normal memory space...  
Is this normal or did I just fail to initialize something correctly?

the objdump output for the natsemi.elf is also attached.  From what I can tell 
it's nothing unusual.

Regards,
Andrew
--Boundary-00=_TbT49FrWBdLVpdd
Content-Type: text/plain;
  charset="us-ascii";
  name="linuxbios.dump"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment; filename="linuxbios.dump"

LinuxBIOS-1.0.0 Sun Nov 24 14:12:38 EST 2002 starting...
Ram1
OOps, can't write to PAM registers properly
After 0x0000000 nop...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x54...
After 0x00...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x4000000 nop...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x0000000 nop...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x54...
After 0x00...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x4000000 nop...
First DRAM setup done
Ram2
Ram3
Ram Enable 1
Ram Enable 2
Ram Enable 3
Ram Enable 4
Ram Enable 5
Ram4
Ram5
Ram6
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
LinuxBIOS-1.0.0 Sun Nov 24 14:12:38 EST 2002 booting...
Finding PCI configuration type.
Scanning PCI bus...PCI: pci_scan_bus for bus 0
PCI: pci_scan_bus returning with max=00
done
Allocating PCI resources...
ASSIGN RESOURCES, bus 0
ASSIGNED RESOURCES, bus 0
done.
Enabling PCI resourcess...done.
Initializing PCI devices...
PCI devices initialized
totalram: 1020M
Initializing CPU #0
Enabling cache...done.

Max cpuid index    : 1
Vendor ID          : GenuineIntel
Processor Type     : 0x00
Processor Family   : 0x05
Processor Model    : 0x01
Processor Mask     : 0x00
Processor Stepping : 0x03
Feature flags      : 0x00800111

done.
CPU #0 Initialized
intel_mainboard_fixup()
Testing SMI
SMI disabled
Enabling extended BIOS access...done.
Checking IRQ routing tables.../home/andrew/linuxbios/freebios/src/arch/i386/lib/pirq_routing.c:    24:check_pirq_routing_table() - irq_routing_table located at: 0x00009720
/home/andrew/linuxbios/freebios/src/arch/i386/lib/pirq_routing.c:    31:check_pirq_routing_table() - checksum is: 0x63 but should be: 0xa6
/home/andrew/linuxbios/freebios/src/arch/i386/lib/pirq_routing.c:    49:check_pirq_routing_table() - checksum error in irq routing table
done.
Copying IRQ routing tables to 0xf0000...done.
Wrote linuxbios table at: 00000500 - 00000644  checksum f2ff

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2

    37:init_bytes() - zkernel_start:0x000c0000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x400000 size 0xb560 offset 0x60 filesize 0x7209
(cleaned up) New segment addr 0x400000 size 0xb560 offset 0x60 filesize 0x7209
Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000b560 filesz: 0x0000000000007209
Clearing Segment: addr: 0x0000000000407209 memsz: 0x0000000000004357
Jumping to boot code at 0x400000



registers just before 'cld' instruction:
eax            0x3fbb9970       1069259120
ecx            0x80             128
edx            0x4d650          317008
ebx            0x3fb65360       1068913504
esp            0x115a4          0x115a4
ebp            0x115ac          0x115ac
esi            0x400000         4194304
edi            0x115d8          71128
eip            0x8748           0x8748
eflags         0x7              7
cs             0x10             16
ss             0x18             24
ds             0x18             24
es             0x18             24
fs             0x18             24
gs             0x18             24

registers just before 'rep movsl'
eax            0x3fbae9b0       1069214128
ecx            0x13594          79252
edx            0x4d650          317008
ebx            0x3fb65360       1068913504
esp            0x11580          0x11580
ebp            0x115ac          0x115ac
esi            0x4000           16384
edi            0x3fbb29b0       1069230512
eip            0x877c           0x877c
eflags         0x2              2
cs             0x10             16
ss             0x18             24
ds             0x18             24
es             0x18             24
fs             0x18             24
gs             0x18             24

registers after 'rep movsl'
eax            0x3fbae9b0       1069214128
ecx            0x0              0
edx            0x4d650          317008
ebx            0x3fb65360       1068913504
esp            0x11580          0x11580
ebp            0x115ac          0x115ac
esi            0x51650          333392
edi            0x3fc00000       1069547520
eip            0x877e           0x877e
eflags         0x2              2
cs             0x10             16
ss             0x18             24
ds             0x18             24
es             0x18             24
fs             0x18             24
gs             0x18             24



--Boundary-00=_TbT49FrWBdLVpdd
Content-Type: text/plain;
  charset="us-ascii";
  name="natsemi.objdump"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment; filename="natsemi.objdump"


../natsemi.elf:     file format elf32-i386
../natsemi.elf
architecture: i386, flags 0x00000002:
EXEC_P
start address 0x00400000

Program Header:
    LOAD off    0x00000060 vaddr 0x00400000 paddr 0x00400000 align 2**5
         filesz 0x00007209 memsz 0x0000b560 flags rwx

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         00006109  00400000  00400000  00000060  2**2
                  CONTENTS, ALLOC, LOAD, CODE
  1 .rodata       00000fbe  00406120  00406120  00006180  2**5
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  2 .data         00000129  004070e0  004070e0  00007140  2**5
                  CONTENTS, ALLOC, LOAD, DATA
  3 .bss          00004340  00407220  00407220  00007280  2**5
                  ALLOC
  4 .comment      000000d0  00000000  00000000  00007280  2**0
                  CONTENTS, READONLY

--Boundary-00=_TbT49FrWBdLVpdd
Content-Type: text/plain;
  charset="us-ascii";
  name="config"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment; filename="config"

target orasis-v1 
mainboard dauphin/orasis-v1

option HAVE_PIRQ_TABLE=1
option SERIAL_CONSOLE=1

option INBUF_COPY=1
option DEFAULT_CONSOLE_LOGLEVEL=15
#option SERIAL_POST=1
option DEBUG=1
option USE_GENERIC_ROM=1
option ROM_SIZE=262144

option NO_KEYBOARD=0 
keyboard pc80

option USE_ELF_BOOT=1
#option BOOT_IDE=1
#option BOOT_FLOPPY=1
#option BOOT_TFTP=1
option BOOT_ROM=1
#option IDE_OFFSET=0x7e00
option IDE_OFFSET=0x0
option IDE_DELAY=1
dir src/pc80/ide

# Path to your kernel (vmlinux) 
linux /home/andrew/linuxbios/linux

# Kernel command line parameters
commandline root=/dev/hda2 console=ttyS0,9600 single 

option RAMTEST=0
payload ../natsemi.elf
option PAYLOAD_SIZE=196608


--Boundary-00=_TbT49FrWBdLVpdd--



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.6.1355070897.16123.coreboot@coreboot.org>

of folks unfamilar with the BIOS projects, an and this FAQ hopes to clear
up the confusion.

	http://www.eax.com/ADLO-FAQ.html

Big Pilot, if I may call you that, does this FAQ answers tose questions?
The way I see, the part below is answered by Q5. Since I assume you are
asking about LinuxBIOS. If you are really asking about linux kernel, then
it is definitely wrong mailing list.

> > if Linux fails, how is one supposed to repair it? Or is the only
> > option booting Linux off a floppy and repairing using that?


> > I'm wondering whether it is still possible to boot DOS (or a free
> > equivalent) from a floppy if LinuxBIOS is installed on the mobo.

As for above. We had limited success with Win98 which is DOS based (we can
get as far as desktop screen, but there are issues), but as the Q6 says it
is still long way to go.

As for the particular susbsystem -- floppy, it has not been tested at all,
and is presumed not working at the moment.

-- 
Adam Sulmicki
http://www.eax.com 	The Supreme Headquarters of the 32 bit registers




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.7.1355070898.16123.coreboot@coreboot.org>

--------------------
I have the code to set the legacy registers to start VGA for a vga console,
integrated into linuxbios, working on two different integrated chips, the
stpc cpu/chipset, and the sis 630 chipset.  It sets the registers for
640x400 std text vga, and also 640x480x4 graphics.  I was working on the
display of a .pcx graphics file when I had to get onto something else, but
it was all working the last time I tried it.

The only reason this hasn't been integrated into linuxbios codebase at this
point is partly lack of interest (I think) in this group, since most use the
serial console, and partly that I have been off on other things lately.

Until this gets into the linuxbios base, anyone that wants the code just
send me an email.
-----------------------

I guess as interest picks up, we need to integrate it into linuxbios.  File
list is below.

-Steve

#added files

#vga generic
src/include/pc80/vga.h
src/pc80/beep.c
src/pc80/font_8x16.c
src/pc80/vga_load_pcx.c
src/pc80/vga_load_regs.c
src/pc80/vga_set_mode.c

#this is a replacement
src/lib/video_subr.c

#pcchips 787 specific
util/config/pcchips787.config
src/mainboard/pcchips/m787cl+/irq_tables.c
src/mainboard/pcchips/m787cl+/Config
src/mainboard/pcchips/m787cl+/dll.inc
src/mainboard/pcchips/m787cl+/mainboard.c

#sis-vga specific
src/northsouthbridge/sis/630/chipinit.h
src/northsouthbridge/sis/630/chipinit.inc
src/northsouthbridge/sis/630/sis630_vga.c


#stpc specific
util/config/stpc.config
src/include/cpu/stpc/consumer2/stpc.h
src/include/cpu/stpc/consumer2/vga_stpc.h
src/cpu/stpc/consumer2/stpc_ram_init.inc
src/cpu/stpc/consumer2/stpc_shadow_rom.inc
src/cpu/stpc/consumer2/stpc_chip.inc
src/cpu/stpc/consumer2/stpc_ioinit.inc
src/cpu/stpc/consumer2/stpc_memsize.inc
src/cpu/stpc/consumer2/stpc_cache.inc
src/cpu/stpc/consumer2/stpc_idt.inc
src/cpu/stpc/consumer2/stpc_framebuffer.inc
src/cpu/stpc/consumer2/stpc_vga.c
src/cpu/stpc/consumer2/Config
src/cpu/stpc/consumer2/stpc_conf.c
src/superio/SMC/fdc37b78x
src/superio/SMC/fdc37b78x/setup_serial.inc
src/superio/SMC/fdc37b78x/superio.c
src/superio/SMC/fdc37b78x/superio.o
src/mainboard/stpc/consumer2/Config
src/mainboard/stpc/consumer2/mainboard.c
src/mainboard/stpc/consumer2/irq_tables.c
src/northsouthbridge/stpc/consumer2/Config
src/northsouthbridge/stpc/consumer2/nsbridge.c



#changed (diff) files

src/include/pc80/ide.h
src/pc80/Config
src/pc80/ide/ide.c
src/lib/linuxbiosmain.c
src/arch/i386/lib/hardwaremain.c
src/arch/i386/lib/params.c
src/arch/i386/include/arch/pirq_routing.h
src/rom/ide_fill_inbuf.c
src/rom/floppy_fill_inbuf.c
src/cpu/p5/Config
src/cpu/p5/delay_tsc.c
src/northsouthbridge/sis/630/Config
src/northsouthbridge/sis/630/raminit.inc
src/northsouthbridge/sis/630/southbridge.c



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.8.1355070901.16123.coreboot@coreboot.org>

...
Copying IRQ routing tables to 0xf0000...done.
Verifing priq routing tables copy at 0xf0000...failed
Wrote linuxbios table at: 00000500 - 0000063c  checksum f4eb
...



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.9.1355070901.16123.coreboot@coreboot.org>

...
Probing...[SIS900]Found SIS 900 ROM address 0x0000
The PCI BIOS has not enabled this device!
Updating PCI command 0003->0007. pci_bus 00 pci_device_fn 09
...

Linux startup messages:
...
sis900.c: v1.08.04 4/25/2002
PCI: No IRQ known for interrupt pin C of device 00:01.1. Please try using 
pci=b.
eth0: SiS 900 Internal MII PHY transceiver found at address 1.
eth0: Using transceiver found at address 1 as default
eth0: SiS 900 PCI Fast Ethernet at 0x2000, IRQ 0, 00:d0:09:a2:0b:f0.
...





From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.10.1355070904.16123.coreboot@coreboot.org>

However, due to full support of VGA is necessary, I'm trying to figure out
ADLO to run binary only 
VGABIOS rom image. 
Can I acomplish this with ADLO?. If yes, how much extra work will be needed
you think? 

Thanks, 

-
HeeChul Yun,          
Embedded S/W Team at ETRI
phone: +82-42-860-1673


------_=_NextPart_001_01C2E6A3.9894EDF0
Content-Type: text/html;
	charset="iso-2022-kr"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-2022-kr">
<META NAME="Generator" CONTENT="MS Exchange Server version 5.5.2653.12">
<TITLE>ADLO for EPIA </TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=2>Hello, </FONT>
</P>

<P><FONT SIZE=2>I'm trying to bring up VGA on EPIA board. </FONT>
<BR><FONT SIZE=2>From the list, EPIA board is supported and I've tested with Angrew's image. </FONT>
<BR><FONT SIZE=2>However, due to full support of VGA is necessary, I'm trying to figure out ADLO to run binary only </FONT>
<BR><FONT SIZE=2>VGABIOS rom image. </FONT>
<BR><FONT SIZE=2>Can I acomplish this with ADLO?. If yes, how much extra work will be needed you think? </FONT>
</P>

<P><FONT SIZE=2>Thanks, </FONT>
</P>

<P><FONT SIZE=2>-</FONT>
<BR><FONT SIZE=2>HeeChul Yun,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </FONT>
<BR><FONT SIZE=2>Embedded S/W Team at ETRI</FONT>
<BR><FONT SIZE=2>phone: +82-42-860-1673</FONT>
</P>

</BODY>

------_=_NextPart_001_01C2E6A3.9894EDF0--


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.11.1355070907.16123.coreboot@coreboot.org>

for the fallback image to be appended. It didn't work because you didn't
have a fallback image at the top of the flash (the end of the image file).

G'day,
sjames




On Thu, 10 Apr 2003, Atherton, Stephen wrote:

> 
> I'm trying to get etherboot and linuxbios running on a supermicro p4dpe.
> 
> The config file I'm using is below.  It builds okay, and I get a
> romimage of around 460k (not sure why it isn't 524288), but when I burn
> it (using flash_and_burn), it doesn't seem to work.  I get no output on
> the serial port.  Note that I have BOOT_IDE set to 1 because at this
> point I would be happy just to see it boot anything, and I have linux on
> the ide hard disk.  Does BOOT_IDE do what I think it does, or is that
> for something else?  Is there something wrong with my config file, or
> should I use some other flash program for this board?  I tried the one
> from supermicro, and doesn't seem to like my romimage file, it exits
> with "cannot close filehandle".
> 
> Also, a few other questions...
> 
> Does linuxbios cause a beep or do anything so that when the machine is
> powered on I would have some clue that it is working?
> 
> Since I'm using the etherboot elf image as a payload, the linux and
> commandline directives in the config file do nothing, right?
> 
> What does USE_FALLBACK_IMAGE do exactly?
> 
> 
> LinuxBios Config file:
> 
> target supermicro
> mainboard supermicro/p4dpe
> option USE_FALLBACK_IMAGE=0
> option ROM_SIZE=524288
> option ROM_IMAGE_SIZE=49152
> option SERIAL_CONSOLE=1
> option TTYS0_BAUD=9600
> option TTYS0_BASE=0x3f8
> option TTYS0_LCS=0x3
> option DEFAULT_CONSOLE_LOGLEVEL=9
> option MAXIMUM_CONSOLE_LOGLEVEL=8
> option USE_ELF_BOOT=1
> option BOOT_IDE=1
> payload ../eepro100.elf
> option CPU_CLOCK_MULTIPLIER=XEON_X17
> option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON
> linux /usr/src/linux-2.4.18-14
> commandline root=/dev/hda2 console=ttyS0,9600 single
> 
> 

-- 
-------------------------steven james, director of research, linux labs
... ........ ..... ....                    230 peachtree st nw ste 2701
the original linux labs                             atlanta.ga.us 30303
      -since 1995                              http://www.linuxlabs.com
                                   office 404.577.7747 fax 404.577.7743
-----------------------------------------------------------------------




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.12.1355070907.16123.coreboot@coreboot.org>

G'day,
sjames





On Fri, 11 Apr 2003, ron minnich wrote:

> On Fri, 11 Apr 2003, steven james wrote:
> 
> > intel/Clearwater533 will be quite similar. Note that the e7501 code has
> > reported problems with 533MHz CPUs. It looks like there are just a few
> > registers in the northbridge that will need to be tweaked. I need to get a
> > pair of CPUs to fix that unless someone beats me to it (patches greatfully
> > accepted :-)
> 
> I called Intel yesterday about this 533 Mhz. issue and the lack of 
> accurate docs. The person I talked to said he will try to help.
> 
> ron
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 

-- 
-------------------------steven james, director of research, linux labs
... ........ ..... ....                    230 peachtree st nw ste 2701
the original linux labs                             atlanta.ga.us 30303
      -since 1995                              http://www.linuxlabs.com
                                   office 404.577.7747 fax 404.577.7743
-----------------------------------------------------------------------




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.13.1355070908.16123.coreboot@coreboot.org>

for the fallback image to be appended. It didn't work because you didn't
have a fallback image at the top of the flash (the end of the image file).

Ron Minnich expanded on fallback vs. primary:

You need to build TWO linuxbioses, a fallback and a primary. The fallback 
is 64k. The primary is (romsize-64k). 

To build a romimage, you build the fallback, build the primary, then:

cat primary/romimage fallback/romimage > final_romimage

flash_rom final_romimage

Steve Gehlbach wrote about using BOOT_IDE:
See pcchips787.config in util/config for complete configuration.

option BOOT_IDE=1
This enables booting from IDE, the file to use is linux.bin.gz:

option IDE_BOOT_DRIVE=2
If you do not use drive 0  (default), then you can set which drive to 
boot; (0,1,2,3) are the four standard PC drives:

option ONE_TRACK=32
The linux.bin.gz file is put in raw form at partition 1, ie, the first 
partition on the disk.  This is located just past the partition table. 
The partition table size varies, it is "one track" from the beginning of 
the disk.  "one track" in c/h/s notation is "s" or the number of sectors 
per track.  ONE_TRACK is in sectors, the software multiplies by 512. 
Most disks are 63 sectors per track (the default), but my CF is 32 
sectors per track.  eg, the partion table is 63x512 or 32x512 bytes.

You can partition your disk as you want, but Linux goes raw in partition 
1; just make sure partition 1 is big enough, not a problem on today's 
disks.  You could put the Linux root file system on partition 2, for 
example.  In pcchips787.config, I put the Linux root file system on IDE 
0, partition 2 (I was experimenting with Linux in partition 1), but I 
eventually put Linux on drive 2 using CF.  You are right, copying of 
linux.bin.gz raw to the partition is dangerous, and something like "cat 
linux.bin.gz > /dev/hda1" will definitely screw the disk if you put the 
wrong disk or partition.  I recommend a shell script, fingers cannot be 
trusted.  You can also use "dd" but "cat" works.

Greg Watsons had some good comments on on the boot process and file layout:
There seem to be two main parts to linuxbios. The first is 
arch/{arch}/config/ctr0.base which does the very low level 
initialization, like turning on memory, etc. The second is 
arch/{arch}/lib/c_start.S which does whatever else is necessary to 
call the C function hardwaremain(). hardwaremain() then does whatever 
else is necessary to load Linux.

c_start.S is linked with linuxbios.a, a library containing generic 
support routines (those found in the lib directory) and anything 
specified using the 'object'  directive in a Config file (and other 
stuff). The resultant 'executable' is called linuxbios_c. The loader 
script used to link linuxbios_c is config/linuxbios_c.ld, and is 
configured to be loaded relative to _RAMBASE.

crt0.base is not linked against anything. Any additional assembly 
routines you need must be specified using the 'mainboardinit' 
directive in a Config file. This causes the specified assembly file 
to be added to "crt0_includes.h" which is in turn included at the 
start of crt0.base (or at the end in the case of the ppc version). 
The loader script used to link crt0.base is in 
arch/{arch}/config/ldscript.base. The resultant 'executable' is 
called linuxbios and will be loaded at _ROMBASE. The tricky thing is 
that this loader script will also load the linuxbios_c 'executable' 
at a location called _payload in this file. The main task of 
crt0.base is then to initialize enough hardware so that this payload 
can be copied from ROM into ram (which may also involve uncompressing 
code). Then control is transferred to _start, which is the first 
location in linuxbios_c.

To get an idea of how crt0.base works, look at the following files. 
This is the order of execution specified by the configuration file 
for sis735.

cpu/i386/entry16.inc
cpu/i386/entry32.inc
superio/sis/950/setup_serial.inc
pc80/serial.inc
arch/i386/lib/console.inc
cpu/k7/earlymtrr.inc
northsouthbridge/sis/735/raminit.inc
arch/i386/config/crt0.base

Next look at c_start.S which will show you what happens once control 
is transferred to _start. Finally, look at 
arch/{arch}/lib/hardwaremain.c to see what other stuff is done to get 
Linux loaded.

Most other files are specific to particular hardware, so it can be 
pretty confusing to just browse the tree.

Hope this helps,

Greg



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.14.1355070921.16123.coreboot@coreboot.org>

cat image > /dev/mtd0

So it seems there is something 'sticky' in these parts when new, cured by
programming individual blocks. Flash is very odd ...

ron



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.15.1355070922.16123.coreboot@coreboot.org>

_________________________________________________________________
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http://www.msn.co.kr/money/interlotto/  



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.16.1355070922.16123.coreboot@coreboot.org>

_________________________________________________________________
MSN Messenger?? ???? ?????????? ???? ?????? ?????? ????????.   
http://messenger.msn.co.kr  



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.17.1355070932.16123.coreboot@coreboot.org>

> LinuxBIOS-1.1.5.0Normal Sat Oct 11 00:21:05 MDT 2003 booting...
> Finding PCI configuration type.
> PCI: Using configuration type 1
> Enumerating: AMD K8 Northbridge
> Enumerating: AMD K8 Northbridge
> Enumerating: AMD K8
> Enumerating: AMD K8
> Enumerating: AMD 8111
> Enumerating: NSC 87360
> Enumerating buses...PCI: pci_scan_bus for bus 0
> PCI: 00:18.0 [1022/1100] enabled
> PCI: 00:18.1 [1022/1101] enabled
> PCI: 00:18.2 [1022/1102] enabled
> PCI: 00:18.3 [1022/1103] ops
> PCI: 00:18.3 [1022/1103] enabled
> PCI: 00:19.0 [1022/1100] enabled
> PCI: 00:19.1 [1022/1101] enabled
> PCI: 00:19.2 [1022/1102] enabled
> PCI: 00:19.3 [1022/1103] ops
> PCI: 00:19.3 [1022/1103] enabled
> amdk8_scan_chains max: 0 starting...
> Hyper transport scan link: 0 max: 1
> PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003
> PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007
> HyperT reset not needed
> PCI: pci_scan_bus for bus 1
> PCI: 01:01.0 [1022/7450] bus ops
> PCI: 01:01.0 [1022/7450] enabled
> PCI: 01:01.1 [1022/7451] ops
> PCI: 01:01.1 [1022/7451] enabled
> PCI: 01:02.0 [1022/7450] bus ops
> PCI: 01:02.0 [1022/7450] enabled
> PCI: 01:02.1 [1022/7451] ops
> PCI: 01:02.1 [1022/7451] enabled
> PCI: 01:03.0 [1022/7460] enabled
> PCI: 01:04.0 [1022/7468] bus ops
> PCI: 01:04.0 [1022/7468] enabled
> PCI: 01:04.1 [1022/7469] ops
> PCI: 01:04.1 [1022/7469] enabled
> PCI: 01:04.2 [1022/746a] enabled
> PCI: 01:04.3 [1022/746b] ops
> PCI: 01:04.3 [1022/746b] enabled
> amd8111_enable dev: PCI: 01:04.5 lpc_dev: PCI: 01:04.0 index: 5 reg: ffff -> ffdf done
> PCI: 01:04.5 [ffff/ffff] disabled
> amd8111_enable dev: PCI: 01:04.6 lpc_dev: PCI: 01:04.0 index: 6 reg: ffdf -> ff9f done
> PCI: 01:04.6 [ffff/ffff] disabled
> PCI: pci_scan_bus for bus 2
> PCI: 02:03.0 [14e4/16a6] enabled
> PCI: 02:04.0 [14e4/16a6] enabled
> PCI: pci_scan_bus returning with max=02
> PCI: pci_scan_bus for bus 3
> PCI: pci_scan_bus returning with max=03
> PCI: pci_scan_bus for bus 4
> PCI: 04:00.0 [1022/7464] ops
> PCI: 04:00.0 [1022/7464] enabled
> PCI: 04:00.1 [1022/7464] ops
> PCI: 04:00.1 [1022/7464] enabled
> PCI: 04:00.2 [1022/7463] ops
> PCI: 04:00.2 [1022/7463] enabled
> amd8111_enable dev: PCI: 04:01.0 lpc_dev: PCI: 01:04.0 index: 9 reg: ff9f -> fd9f done
> PCI: 04:01.0 [ffff/ffff] disabled
> PCI: 04:06.0 [1002/4752] enabled
> PCI: pci_scan_bus returning with max=04
> PNP: 002e.0 enabled
> PNP: 002e.1 enabled
> PNP: 002e.2 enabled
> PNP: 002e.3 enabled
> PNP: 002e.4 enabled
> PNP: 002e.5 enabled
> PNP: 002e.6 enabled
> PNP: 002e.7 enabled
> PNP: 002e.8 enabled
> PNP: 002e.9 enabled
> PNP: 002e.a enabled
> PCI: pci_scan_bus returning with max=04
> Hyper transport scan link: 0 new max: 4
> Hypertransport scan link done
> amdk8_scan_chains max: 4 done
> amdk8_scan_chains max: 4 starting...
> amdk8_scan_chains max: 4 done
> PCI: pci_scan_bus returning with max=04
> done
> Allocating resources...
> PCI: 04:01.0 missing read_resources
> PCI: 04:01.0 missing read_resources
> PCI: 04:01.0 missing read_resources
> PCI: 01:04.5 missing read_resources
> PCI: 01:04.6 missing read_resources
> PCI: 01:04.5 missing read_resources
> PCI: 01:04.6 missing read_resources
> ASSIGN RESOURCES, bus 0
> PCI: 01:04.5 missing read_resources
> PCI: 01:04.6 missing read_resources
> PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 0 io
> PCI: 01:04.5 missing read_resources
> PCI: 01:04.6 missing read_resources
> PCI: 00:18.0 b8 <- [0xfd000000 - 0xfe2fffff] node 0 link 0 mem
> ASSIGN RESOURCES, bus 1
> PCI: 01:01.0 1c <- [0x00002000 - 0x00001fff] bus 2 io
> PCI: 01:01.0 24 <- [0xfe200000 - 0xfe1fffff] bus 2 prefmem
> PCI: 01:01.0 20 <- [0xfe100000 - 0xfe1fffff] bus 2 mem
> ASSIGN RESOURCES, bus 2
> PCI: 02:03.0 10 <- [0xfe100000 - 0xfe10ffff] mem
> PCI: 02:04.0 10 <- [0xfe110000 - 0xfe11ffff] mem
> ASSIGNED RESOURCES, bus 2
> PCI: 01:01.1 10 <- [0xfe200000 - 0xfe200fff] mem
> PCI: 01:02.0 1c <- [0x00002000 - 0x00001fff] bus 3 io
> PCI: 01:02.0 24 <- [0xfe200000 - 0xfe1fffff] bus 3 prefmem
> PCI: 01:02.0 20 <- [0xfe200000 - 0xfe1fffff] bus 3 mem
> PCI: 01:02.1 10 <- [0xfe201000 - 0xfe201fff] mem
> PCI: 04:01.0 missing read_resources
> PCI: 01:03.0 1c <- [0x00001000 - 0x00001fff] bus 4 io
> PCI: 04:01.0 missing read_resources
> PCI: 01:03.0 24 <- [0xfe200000 - 0xfe1fffff] bus 4 prefmem
> PCI: 04:01.0 missing read_resources
> PCI: 01:03.0 20 <- [0xfd000000 - 0xfeffffff] bus 4 mem
> ASSIGN RESOURCES, bus 4
> PCI: 04:00.0 10 <- [0xfe000000 - 0xfe000fff] mem
> PCI: 04:00.1 10 <- [0xfe001000 - 0xfe001fff] mem
> PCI: 04:00.2 10 <- [0xfe003000 - 0xfe0030ff] mem
> PCI: 04:00.2 14 <- [0xfe004000 - 0xfe00401f] mem
> PCI: 04:01.0 missing set_resources
> PCI: 04:06.0 10 <- [0xfd000000 - 0xfdffffff] mem
> PCI: 04:06.0 14 <- [0x00001000 - 0x000010ff] io
> PCI: 04:06.0 18 <- [0xfe002000 - 0xfe002fff] mem
> ASSIGNED RESOURCES, bus 4
> PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] io
> PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] mem
> ASSIGN RESOURCES, bus 0
> PNP: 002e.0 60 <- [0x00002480 - 0x00002485 io
> ERROR: PNP: 002e.0 70 not allocated
> ERROR: PNP: 002e.0 74 not allocated
> PNP: 002e.1 60 <- [0x00002000 - 0x00002307 io
> ERROR: PNP: 002e.1 70 not allocated
> ERROR: PNP: 002e.1 74 not allocated
> PNP: 002e.2 60 <- [0x00002440 - 0x00002447 io
> ERROR: PNP: 002e.2 70 not allocated
> ERROR: PNP: 002e.2 74 not allocated
> ERROR: PNP: 002e.2 75 not allocated
> PNP: 002e.3 60 <- [0x000003f8 - 0x000003f7 io
> PNP: 002e.3 70 <- [0x00000004 - 0x00000003 irq
> PNP: 002e.4 60 <- [0x00002420 - 0x0000242f io
> ERROR: PNP: 002e.4 70 not allocated
> ERROR: PNP: 002e.5 70 not allocated
> PNP: 002e.6 60 <- [0x00000060 - 0x0000005f io
> PNP: 002e.6 62 <- [0x00000064 - 0x00000063 io
> PNP: 002e.7 60 <- [0x00002450 - 0x00002457 io
> ERROR: PNP: 002e.7 70 not allocated
> PNP: 002e.8 60 <- [0x00002460 - 0x00002467 io
> ERROR: PNP: 002e.8 70 not allocated
> PNP: 002e.9 60 <- [0x00002470 - 0x00002477 io
> ERROR: PNP: 002e.9 70 not allocated
> PNP: 002e.a 60 <- [0x00002490 - 0x00002493 io
> ERROR: PNP: 002e.a 70 not allocated
> ASSIGNED RESOURCES, bus 0
> PCI: 01:04.1 20 <- [0x00002430 - 0x0000243f] io
> PCI: 01:04.2 10 <- [0x00002400 - 0x0000241f] io
> PCI: 01:04.5 missing set_resources
> PCI: 01:04.6 missing set_resources
> ASSIGNED RESOURCES, bus 1
> ASSIGNED RESOURCES, bus 0
> Allocating VGA resource
> done.
> Enabling resourcess...
> PCI: 00:18.0 cmd <- 00
> PCI: 01:01.0 bridge ctrl <- 0000
> PCI: 01:01.0 cmd <- 07
> PCI: 02:03.0 cmd <- 02
> PCI: 02:04.0 cmd <- 02
> PCI: 01:01.1 cmd <- 02
> PCI: 01:02.0 bridge ctrl <- 0000
> PCI: 01:02.0 cmd <- 07
> PCI: 01:02.1 cmd <- 02
> PCI: 01:03.0 bridge ctrl <- 003e
> PCI: 01:03.0 cmd <- 07
> PCI: 04:00.0 cmd <- 02
> PCI: 04:00.1 cmd <- 02
> PCI: 04:00.2 cmd <- 02
> PCI: 04:01.0 missing enable_resources
> PCI: 04:06.0 cmd <- 83
> PCI: 01:04.0 cmd <- 0f
> PCI: 01:04.1 cmd <- 01
> PCI: 01:04.2 cmd <- 01
> PCI: 01:04.3 cmd <- 00
> PCI: 01:04.5 missing enable_resources
> PCI: 01:04.6 missing enable_resources
> PCI: 00:18.1 cmd <- 00
> PCI: 00:18.2 cmd <- 00
> PCI: 00:18.3 cmd <- 00
> PCI: 00:19.0 cmd <- 00
> PCI: 00:19.1 cmd <- 00
> PCI: 00:19.2 cmd <- 00
> PCI: 00:19.3 cmd <- 00
> done.
> Initializing devices...
> PCI: 00:18.3 init
> NB: Function 3 Misc Control.. done.
> PCI: 00:19.3 init
> NB: Function 3 Misc Control.. done.
> PCI: 01:01.0 init
> PCI: 01:02.0 init
> PCI: 01:04.0 init
> lpc_init
> PCI: 01:04.1 init
> ide_init
> IDE1 IDE0 PCI: 01:04.3 init
> set power on after power fail
> PCI: 04:00.0 init
> USB: Setting up controller.. done.
> PCI: 04:00.1 init
> USB: Setting up controller.. done.
> PCI: 04:00.2 init
> USB: Setting up controller.. done.
> Devices initialized
> mmio_base: 3932160KB
> totalram: 2048M
> Initializing CPU #0
> Enabling cache...
> Setting fixed MTRRs(0-88) type: UC
> Setting fixed MTRRs(0-88) type: WB
> DONE fixed MTRRs
> Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
> DONE variable MTRRs
> Clear out the extra MTRR's
> call intel_enable_fixed_mtrr()
> call intel_enable_var_mtrr()
> Leave setup_mtrrs
> done.
> 
> Max cpuid index    : 1
> Vendor ID          : AuthenticAMD
> Processor Type     : 0x00
> Processor Family   : 0x0f
> Processor Model    : 0x05
> Processor Mask     : 0x00
> Processor Stepping : 0x01
> Feature flags      : 0x078bfbff
> 
> 
> MTRR check
> Fixed MTRRs   : Enabled
> Variable MTRRs: Enabled
> 
> Setting up local apic... apic_id: 0 done.
> CPU #0 Initialized
> secondary_cpu_init
> Waiting for 2 CPUS to stop
> mmio_base: 3932160KB
> Initializing CPU #1
> Enabling cache...
> Setting fixed MTRRs(0-88) type: UC
> Setting fixed MTRRs(0-88) type: WB
> DONE fixed MTRRs
> Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
> DONE variable MTRRs
> Clear out the extra MTRR's
> call intel_enable_fixed_mtrr()
> call intel_enable_var_mtrr()
> Leave setup_mtrrs
> done.
> 
> Max cpuid index    : 1
> Vendor ID          : AuthenticAMD
> Processor Type     : 0x00
> Processor Family   : 0x0f
> Processor Model    : 0x05
> Processor Mask     : 0x00
> Processor Stepping : 0x01
> Feature flags      : 0x078bfbff
> 
> 
> MTRR check
> Fixed MTRRs   : Enabled
> Variable MTRRs: Enabled
> 
> Setting up local apic... apic_id: 16777216 done.
> CPU #1 Initialized
> secondary_cpu_init  1/1
> All AP CPUs stopped
> Checking IRQ routing tables...
> Inconsistent IRQ routing table size
> /home/eric/projects/linuxbios/checkin/hdama/foo/freebios2/src/arch/i386/boot/pirq_routing.c:    29:check_pirq_routing_table() - irq_routing_table located at: 0x0000f1c0
> done.
> Copying IRQ routing tables to 0xf0000...done.
> Verifing priq routing tables copy at 0xf0000...succeed
> Wrote the mp table end at: 00000020 - 0000021c
> Wrote linuxbios table at: 00000500 - 00000b00  checksum 4399
> 
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.3
> 
> Found ELF candiate at offset 0
> Loading Etherboot version: 5.2.1eb1
> Dropping non PT_LOAD segment
> New segment addr 0x20000 size 0x3936f offset 0xc0 filesize 0x70d8
> (cleaned up) New segment addr 0x20000 size 0x3936f offset 0xc0 filesize 0x70d8
> Loading Segment: addr: 0x0000000000020000 memsz: 0x000000000003936f filesz: 0x00000000000070d8
> Clearing Segment: addr: 0x00000000000270d8 memsz: 0x0000000000032297
> Jumping to boot code at 0x20000
> ROM segment 0x0000 length 0x0000 reloc 0x00020000
> CPU 1457 Mhz
> Etherboot 5.2.1eb1 (GPL) http://etherboot.org ELF64 ELF for [TG3][IDE]


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.18.1355070938.16123.coreboot@coreboot.org>

range of helpful holiday info here.  
http://special.msn.com/network/happyholidays.armx



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.19.1355070939.16123.coreboot@coreboot.org>

more robust than your armboot, so I'd like to merge your stuff into
mine if possible.  Now that 2.6.0 is out I can start sending patches
again.

- I avoid deliberately avoid vmalloc, the vmalloc area is a limited
  resource, and I support loading large kernel ramdisk combinations.
- I avoid greater than page size memory allocations because random 
  memory fragmentation can make that fail.
- I don't leak memory.
- I have an implementation that works on SMP machines.  

The worst part is getting all of the drivers to shut themselves down
properly.  But I have the appropriate hooks and it doesn't take an
extension of the kernel api just lots of driver bug fixes.

If even the arm guys are up to using a kernel it should be easier
to make progress in this array.  On several projects the people
I have talked to are two size constrained to even try using a kernel.

Eric


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.20.1355070939.16123.coreboot@coreboot.org>

The Core Logic module positively decodes memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
8- or 16-bit wide ROM is supported. BOOT16 strap determines
the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block allows program control of the width.
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#,WR# and ROMCS#
asserted.

The Boot Flash supported by the SC1200/SC1201 can be
up to 16 MB. It is supported with the ROMCS# signal.

        As the corelogic module positively decodes the memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset, I can have my Flash memory mapped to 
the lower address. Is it?


>From: ron minnich <rminnich at lanl.gov>
>To: Devi Priya <ijpriya at hotmail.com>
>CC: linuxbios at clustermatic.org
>Subject: Re: Flash mapped to lower address?
>Date: Wed, 24 Dec 2003 18:39:20 -0700 (MST)
>
>On Tue, 23 Dec 2003, Devi Priya wrote:
>
> > If i have my Flash memory mapped to the lower address (0x0000-0x3FFFFF),
> > then what modification should be made to linux bios?
>
>why on earth would you map flash to this address? it makes no sense to me.
>
>ron
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios at clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios

_________________________________________________________________
NRI?s, Free Money transfer to India. 
http://server1.msn.co.in/msnleads/citibankrca/citibankrca2.asp?type=hottag 
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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.21.1355070939.16123.coreboot@coreboot.org>

it appears to be the equal of bk etc.  I think I see some
was to make it simpler and more powerful but that is not needed to
make a good revision control system.

I need to do a little more testing to see what arch is actually like
to use.  Before I seriously start advocating anything but I'm not
expecting any weird issues to crop up.  Except possibly for some
issues running under cygwin, for the platform challenged.

Once my evaluation is finished I plan on pushing the projects I work
on in that direction.  So this is something to think about.

Eric


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.22.1355070942.16123.coreboot@coreboot.org>

extra eeprom actually connected, so there is no real alternative other
than downloading the controller firmware

> Actually the FW download and controller starting can be done by Linux kernel
> driver.

Aha! This sounds really interesting. Looking into the code, there is
/dev/mptctl. This can be used for firmware upload/download (ioctl
interface) - Is there a utility to do this, yet?

  Stefan

-- 
     Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.23.1355070942.16123.coreboot@coreboot.org>

buried within them. For example, ATi and their OEMs release a series of 
cards called "All-In-Wonder" with each new chip. These AIW cards have a 
ton of extras on them like TV-tuners, hardware media decoders, the works. 
So for people looking to by a single card to perform multiple tasks 
rather than buying a Radeon, DXR3, tv tuner, etc, this is a good 
deal. However, those extras such the TV tuner and media decoder chips 
aren't necessarily ATi's own design. And for some reason, ATi can't 
release specs on everything *but* the proprietary chips (And some  
industry "analysts" call the GPL viral!). 

But then again, I have no way of verifying this, and it's a discussion 
for another BBS :)

On Mon, 9 Feb 2004, Terry Blunt wrote:

> "Hendricks David W." <dwh at lanl.gov> wrote:
> 
> > We don't need to with nVidia, we can run their VGA BIOS using testbios.
> > 
> > Though in the perfect world, they'd be more forthcoming with specs so that
> > someone can make an LB port for their nForce boards.
> > 
> > On Mon, 9 Feb 2004, Carlos Silva wrote:
> > 
> > > Really nice news... i'll keep dreaming that nvidia will do the same.
> 
> Maybe I'm missing something, but I can never understand hardware
> manufacturers being cagey about their specs. I would have thought it would
> save them a lot of hassle if they *didn't* have to write drivers themselves.
> If they made the information available with suggestions and worked examples,
> the software industry would do it all for them.
> 
> To forestall one argument, I really don't see anyone being able to reverse
> engineer the *hardware* from the overall specs.
> 
> 



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.24.1355070943.16123.coreboot@coreboot.org>

cards depend on, or can depend on at that stage so we should be in
reasonably good shape long term.  At least until x86 BIOS
compatibility is given up.

An important thing to verify here is that the standard cpu
identification steps will show the emulated cpu to be a 386 or whatever
minimal processor we support.  And we should tightly restrict the
emulated codes access to memory, presenting it with a virtual not a
real view of what is going on.  Keeping the code chained as much as
possible.


Beyond that...

If we want the video card to provide int 0x10 services to a pcbios
compatibility layer we need to rerun the video card initialization
in the bochs bios.

I think the simplest path to a flexible LinuxBIOS solution is to have
a native LinuxBIOS loader like etherboot, the Linux kernel or possibly
something much simpler act as a switch between the different
personalities we can wear, PCBIOS openfirmware, efi, arc, etc.   And
we will boot with whichever one the user selects.

Using a bootloader as a switch to select among the others is the only
easy way I can see to have my cake and it too with supporting multiple
personalities.  You get only one at a time but I think that is easier
to verify.

Eric


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.25.1355070944.16123.coreboot@coreboot.org>

Some efforts are on their way, but still in development...
( VIA does not want to give all the information we need so far )

-----Original Message-----
Subject: Epia-M IDE HowTo

> 
> Hi,
> I have a EPIA-M (ME6000) and I want to use Linuxbios for my HTPC.
> 
> So I want to boot from hd.
> Is there anywhere a good HowTo for this.
> 
> The HowTo in the cvs for talks only about etherboot.
> 
> greetz
> 



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.26.1355070946.16123.coreboot@coreboot.org>

Strange enough, since the Maxtor harddrive was installed using 
LinuxBIOS and Filo a while ago..

  Stefan

-- 
  Stefan Reinauer, SUSE LINUX AG
Head of Architecture Development


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.27.1355070949.16123.coreboot@coreboot.org>

Travel Guide! http://special.msn.com/local/springtravel.armx



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.28.1355070949.16123.coreboot@coreboot.org>

Travel Guide! http://special.msn.com/local/springtravel.armx



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.29.1355070953.16123.coreboot@coreboot.org>

> 
> I don't really think it is BIOS issue.
> 
> OS can do it just fine on its own. I don't see why BIOS should be
> invovled
> here.
> 
> > Has any work been done toward the goal of "Hibernation"?  I'm writing
> of
> > the type that would use a separate partition equal to ram + swap space
> > to store the current memory state.  If no one has done any work to
> this
> > effect, how difficult would it be?  I may be willing to help the
> effort.
> > I've never programmed for a BIOS, but I've done mmap() stuff before.
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.30.1355070953.16123.coreboot@coreboot.org>

> 
> well I guess it depends on philosophy. if the idea is to have
> minimalistic
> bios then ability to suspend doesn't belong there.
> 
> on the other hand some configurations of "bios" (where "bios" would be
> the
> thing in the thing in FLASH), often include linux kernel and that alone
> could be re-used to enable suspend. Although the proper way to do this
> is
> probably to use "management mode" of the recent CPUs.
> 
> On Fri, 14 May 2004 lbios_kk at redfenix.com wrote:
> 
> > If the hibernation restore occurred from the BIOS, then one wouldn't
> need to boot from disk, right?  Also, if you don't need to boot from
> disk, the BIOS could restore the entire memory state and then
> re-initialize any peripherals that need it (PCI, PCMCIA, CF, VGA, etc.) 
> Should be quicker, elegant, and more effective, right?  (and OS
> independent if done right.)
> >
> > Question is, how much memory does LinuxBIOS use for itself?  We'd have
> to make sure that it doesn't "step on its own feet" trying to get the
> memory state loaded.
> >
> > --Kevin
> >
> > >From Adam Sulmicki <adam at cfar.umd.edu> on 14 May 2004:
> >
> > >
> > > I don't really think it is BIOS issue.
> > >
> > > OS can do it just fine on its own. I don't see why BIOS should be
> > > invovled
> > > here.
> > >
> > > > Has any work been done toward the goal of "Hibernation"?  I'm
> writing
> > > of
> > > > the type that would use a separate partition equal to ram + swap
> space
> > > > to store the current memory state.  If no one has done any work to
> > > this
> > > > effect, how difficult would it be?  I may be willing to help the
> > > effort.
> > > > I've never programmed for a BIOS, but I've done mmap() stuff
> before.
> > >
> > > _______________________________________________
> > > Linuxbios mailing list
> > > Linuxbios at clustermatic.org
> > > http://www.clustermatic.org/mailman/listinfo/linuxbios
> > >
> >
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.31.1355070953.16123.coreboot@coreboot.org>

> On Friday 14 May 2004 4:36 pm, lbios_kk at redfenix.com wrote:
> 
> > I'm not necessarily talking about handling a suspend or low-power
> mode. 
> > I'm talking about copying the memory to disk, then powering off. 
> Then,
> > upon power-on next time, reload the memory state, re-init peripherals
> and
> > go!
> 
> I can't help feeling that it's a bit simplistic to just say "re-init 
> peripherals" like that.   Some peripherals can have quite a complex
> state 
> associated with them, and just re-initialising them as though you were 
> starting from power-up may not make the O/S happy when it finds itself
> back 
> in control after the hibernation is over?
> 
> There has to be some O/S involvement in going into, and returning from, 
> hibernation mode - the question for LinuxBIOS is "how much of a task is
> left 
> over once you take out what the Linux kernel can already do for itself?"
> 
> Regards,
> 
> Antony.
> 
> -- 
> Microsoft may sell more software than any other company, but McDonald's
> sell 
> more burgers than any other company, and I think the other similarities
> are 
> obvious...
> 
>                                                      Please reply to the
> list;
>                                                            please don't
> CC me.
> 
> _______________________________________________
> Linuxbios mailing list
> Linuxbios at clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
> 


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.32.1355070956.16123.coreboot@coreboot.org>

CPU feature.  From what I have seen, embedded platforms seem to be a 
bit more developer friendly then normal x86 hardware.

With just a small stack you can probably create much denser
code at boot time. Especially since you don't have to inline
everything.  On the flip side cpu developers especially on the bleeding
edge seem to be inovating with caches a lot so it is an easy way to
run into cpu bugs.

Eric


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.33.1355070956.16123.coreboot@coreboot.org>

wanting to implement some form of code reuse.  And to reuse code
things must share and cooperate.

I will argue that if want code reuse someone should be a library of
the functions that will be reused.  Then we don't need multiple
PAYLOADs and all of the associated nastiness.  Plus the act of
putting the code in a library and cleaning it up so it can live
in one is what is needed to actually make the code reusable.

The current architecture of LinuxBIOS (not counting the weird FILO thing)
works and does not leave us implementing an OS.  As we approach being
feature complete and quite general we accumulate a lot of code.  But
largely it is conditional upon what hardware actually exists on a
motherboard.

Another issue on this topic is what interface do we provide to the
outside world to people who want to customize LinuxBIOS.  The reason I
am largely in favor of testbios, openbios, ADLO and the Linux kernel
is those are interfaces that already exist.  Commodity interfaces you
might call them.  We don't have to convince hardware manufacturers or
software developers to support something new.  That makes the option
rom problem easier.

For embedded developers the question is what will work best for their
hardware and use the least amount of resources (to keep the price
down) while doing so.   So far LinuxBIOS has kept itself inside of 64K
for x86 which is doing pretty good on general purpose server boards.

As best I can tell there are two primary target configurations for
LinuxBIOS.  General purpose firmware that can do a lot of things.
Embedded systems where things are well enough understood you can
directly load your final image from flash.

Except for a few issues like romcc being a code size pig I think
we are ok on the minimal configurations.  For the general purpose
default configuration/configurations we still have a long ways
to go.  Etherboot when I proposed it was a stop gap that worked.
And we could use it immediately because of it's size.

Etherboot does not currently do everything we need.  It works but is
lousy at booting off of disks, for example.  There are a lot of
ways forward including enhancing etherboot, enhancing filo, or finally
getting the Linux kernel small enough we can use it.

So far I have been buried alive under the task of catching with the
latest and greatest chipsets and doing all of the required ports.  
I have not had much time to work on the bootloader problem recently.
I want people to understand the reason I have not followed through on
my ideas have been scheduling conflicts and not because of any
intrinsic problems with the ideas.  Except possibly the romcc size
optimizations :)

Eric


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.34.1355070967.16123.coreboot@coreboot.org>

Or if the CF FS crashed, how do you roll it back?

Regards

Yinghai Lu

-----Original Message-----
From: Li-Ta Lo [mailto:ollie at lanl.gov] 
Sent: Monday, November 01, 2004 12:05 PM
To: YhLu
Cc: Ronald G. Minnich; LinuxBIOS
Subject: RE: FILO fixups

On Mon, 2004-11-01 at 12:00, YhLu wrote:
> The reason for put filo in etherboot.
> 1. It can let boot from HD or net according to CMOS setting.
> 2. Etherboot can produce zelf. We may got more space to put other stuff
such
> as USB support...
> 3. Etherboot structure and support...
> 
> I may check if filo.zlef only include FILO ..., even it is not, we still
can
> make it clean.
> 

You have the same blind spot as Eric. For many people, boot over net is
irrelevant. Why do they need to live with the overhead of network 
protocol stack and driver if all they want to to boot form some
mass storage device ?

Ollie



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.35.1355070973.16123.coreboot@coreboot.org>

asm(	"movl $1f, %esp\n\t"
        "jmp low_level_shell\n\t"
        "1:\n\t"
);

Of course you won't come back unless you have your serial console working...


Eric


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.36.1355070974.16123.coreboot@coreboot.org>

only. The broadband provider bundles in a 15" CRT from
LG-India bringing the price up to USD$250 or so.

Also, from what I've read, the simputer is more like a
enhanced-PDA, ie: handheld device, rather than like a
computer. From their FAQ;

# Q: Is the Simputer like a PC?
A: No. The Simputer is *NOT* a personal computer. It
could however be a pocket computer.
# Q: Is the Simputer like a Palm?
A: Again no! The Simputer is much more powerful than a
Palm. For example, in terms of screen size (320x240),
memory capabilities (32MB RAM) and the OS (GNU/Linux).

Ramesh



		
__________________________________ 
Do you Yahoo!? 
Take Yahoo! Mail with you! Get it on your mobile phone. 
http://mobile.yahoo.com/maildemo 


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.37.1355070978.16123.coreboot@coreboot.org>

and most if not all flashchips that /dev/bios supports, plus it is less
intrusive, being a userspace program. I should probably drop /dev/bios
completely.

Stefan


 


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.38.1355070978.16123.coreboot@coreboot.org>

ROM-o-matic for the davicom card.  Although one poster said he had to
make mods to the etherboot loader since there is no INT19 support in
the BIOS of the device and the NOINT19 stuff in etherboot didn't work.
 Perhaps thats all fixed now.

Geting it to dhcp a linux kernel and then dumping the northbridge and
sourthbridge settings is probably your only chance unless of course
you can find a datasheet for OPTi somewhere.   You should be able to
get the SMC superIO to work pretty easily.

All in all I would say the ROI on that is very low.  Probably not
worth the effort.

-- 
Richard A. Smith


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.39.1355070979.16123.coreboot@coreboot.org>

LinuxBIOS but rather chose the same name. But then again, changing a
couple of strings is nothing too hard.

The way to go is rather to convince them to go with the real
LinuxBIOS[tm] in future.

Stefan


 


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.40.1355070980.16123.coreboot@coreboot.org>

That could be part of the problem. 

ron


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.43.1355071000.16123.coreboot@coreboot.org>

Small Linux' (DSL). With the latter I had to download the full X server =
package to get the Via driver, and change configuration slightly to make =
sure that this driver was the one that ran rather than the default Vesa =
driver. Both of these setups use 2.4.x kernels, and I have no experience =
with 2.6.x.

To make Linuxbios VESA compatible would thus require Linuxbios to create =
a persistent int 21 handler in 16 bit code. It could be made persistent =
by creating it somewhere in the 0xf000 segment along with the various =
tables which it creates.

The int 21 handler itself is fairly trivial - it just seems to return =
certain values describing the environment in which it is running:
- The type and speed of main memory - which in turn is used to limit the =
max resolution and refresh rate of the display so as not to hog main =
memory bandwidth on slower memory
- The type of display chosen and saved in CMOS - CRT, TV, Flat Panel
- The size of a flat panel etc.

The current int 21 handler simply returns hard coded values for these =
i.e. 266Mhz DDR ram, and CRT display only.
 =20
Unless anyone feels that they would like to add such a handler, I would =
thus recommend that folk stick with the native chipset drivers, and make =
sure that they are configured to not use Bios calls for setting the =
graphics mode.

Other mailings have suggested that the Via 1.1.16 vga bios does not =
work, whereas the 1.1.13 bios does. I suspect that Via have extended or =
changed their definition of the int 21 call between these two versions - =
Joy.

Nick Barker




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.44.1355071002.16123.coreboot@coreboot.org>

embedded systems, but I wonder if my board may work ? The website is a
little vague on supported boards (out of date ?) so I have answered
the questions from one of the FAQ entries below.

Thanks for any pointers, Simon

  ============

If the above sources don't help, please send the following to the
Mailinglist:

    * Step 1: A very brief description of your system: CPU and mainboard
and optionally other important details.

Gigabyte GA-8I848P-G / ATX / Pentium 4 / Socket 478

    * Step 2: Linux lspci output for your system, generated by booting
Linux via the original BIOS and runnning lspci.

00:00.0 Host bridge: Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface (rev 02)
00:01.0 PCI bridge: Intel Corporation 82865G/PE/P PCI to AGP Controller (rev 02)
00:1d.0 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 (rev 02)
00:1d.1 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 (rev 02)
00:1d.2 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 (rev 02)
00:1d.3 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 (rev 02)
00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02)
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev c2)
00:1f.0 ISA bridge: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge (rev 02)
00:1f.1 IDE interface: Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller (rev 02)
00:1f.2 IDE interface: Intel Corporation 82801EB (ICH5) SATA Controller (rev 02)
00:1f.3 SMBus: Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller (rev 02)
00:1f.5 Multimedia audio controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller (rev 02)
01:00.0 VGA compatible controller: nVidia Corporation NV18 [GeForce4 MX 4000 AGP 8x] (rev c1)
02:02.0 Network controller: AVM Audiovisuelles MKTG & Computer System GmbH Fritz!Card DSL SL (rev 01)

    * Step 3: SuperIO chip on the mainboard (report the model numbers on
the actual chip - doesn't appear in the lspci output)

ITE 8712F

    * Step 4: Type of BIOS device (See the question "How do I identify
the BIOS chip on my mainboard?" below.)

    * Step 5: URL to the mainboard specifications page (optional)

http://www.giga-byte.com/Motherboard/Products/Products_GA-8I848P-G.htm

    * Step 6: Any other relevant information you can provide 

-- 
Simon Kellett,        |   Gentoo Linux, Fvwm, Firefox 
Darmstadt, Germany    |              Xemacs, Vm, Gnus




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.51.1355071003.16123.coreboot@coreboot.org>

How would such an option in the chip struct look like? Should we have
the revision and vendor of the SuperIO chip stored in the device tree's
superio entry and enable the workaround if we find an adequate device in
the tree?

Yinghai, can we switch this on unconditionally or might that hurt some
motherboards? 

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.52.1355071003.16123.coreboot@coreboot.org>

know if anyone has tried to get it yet.

> Has anyone ever been able to work the Insyde/AMD VSA binaries into
> LinuxBIOS?
>

I have pretty much idea about how the VSA is working. Once I got the most
basic chipset init done. I will try to integrate VSA into LinuxBIOS.

One advantage we just got is AMD has committed to provide support for
the One Laptop per Poor Child project. Probably we will get something
not normally avaliable to the public.

BTW, I really need help from the LB community. I simply can't do all
the hacking and coding by myself and meet OLPC/Quanta's tight schedule.

Ollie




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.53.1355071004.16123.coreboot@coreboot.org>

but does not talk.

What format is the kernel image? (bzimage?)


> [e1000-82541gi]Ethernet addr: 00:D0:68:09:EC:FE
> Searching for server (DHCP)...
> ...Me: xxx.xxx.xxx.xxx, Server: 134.155.45.16, Gateway xxx.xxx.xxx.xxx
> Loading xxx.xxx.xxx.xxx:/htxlinux.0 ...
> (ELF)... .............................................................................................................
> ...........................................................................................................................................................
> ...........................................................................................................................................................
> ...........................................................................................................................................................
> ...........................................................................................................................................................
> ...................................................................done
> Firmware type: LinuxBIOS
 






From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.54.1355071005.16123.coreboot@coreboot.org>

with all bits set, while the vendor-supplied image contains
meaningful data there.

From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.55.1355071005.16123.coreboot@coreboot.org>

it seems that one is only meaningful for the extracted image.

My first thought was to just exclude 0x006e000-0x006e8c0
from flashing, but the fact that flash_rom read only 0xff
from 0x0040000-0x005fff0 made me worried.

Do you have any suggestions how to find out whether the
results above are expected?

switch:/storage/LinuxBIOSv2-2251/util/flashrom # ./flashrom
Calibrating delay loop... ok
No LinuxBIOS table found.
Enabling flash write on NVIDIA CK804...OK
SST49LF004A/B found at physical address: 0xfff80000
Flash part is SST49LF004A/B
OK, only ENABLING flash write, but NOT FLASHING.

Thanks,
Carl-Daniel
-- 
http://www.hailfinger.org/



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.56.1355071011.16123.coreboot@coreboot.org>

gather that these boards have the problem:

VIA EPIA-MS10000E
EPIA-M mainboards
EPIA-MII mainboards
EPIA-TC mainboard
EPIA-PD mainboard
VIA EPIA M mainboard
VIA EPIA MII mainboard
VIA EPIA SP mainboard
VIA EPIA CL mainboard

Note that the "fix" is a new BIOS, which is useless to potential LB 
users.  Also, the ML (my board) is not on there, but it has the EXACT 
same symptoms.

>
>> (mini-itx, preferrably), that has all the usual goodies
>> (IDE,USB,VGA,serial, etc) that is known to work well with LinuxBios?
>> Naturally, one without a VIA chipset?
>
>
> Working well with LB is the kicker.  You could join us on the GX1
> quest.  There are several GX1 boards out there.  If you get one like
> Chris's with an external VGA chip then you won't have to mess with the
> VSA stuff.  I think the GX1 is close to working good but it just need
> a few tweaks to get there. 

I'll look into them ...




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.57.1355071016.16123.coreboot@coreboot.org>

answered them:
1. Can I fit LinuxBios with Etherboot to boot from SATA in 128KiB, it does
not matter how much i chunk out as long as the machine boots!
2. If this is true, can someone PLEASE tell me how to build Etherboot under
x86_64?
Thanks,

-- 
------------------------
Arturo Mann, arturo.mann at gmail.com

------=_Part_17672_5643318.1151020394068
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 7bit
Content-Disposition: inline

Hello there,<br>As i stated previously, i got my hands on a Tyan S2892, and it's included SST 49LF 8Mbit chip was botched,<br>after a flashing, it went completely dead, I actually tried to prom it with a big-time universal 8-gang flash PLCC prommer today.
<br>Currently, there are no SST49LF 8Mbit replacements available in mexico (or any equivalents, actually), so, I got my hands<br>on the best i could get on the spot, a 128KiB (Kilobyte) AMD chip which <span style="font-style: italic;">
is</span> supported by uniFlash.<br>From this, I got two questions, and I would be very grateful if you lot answered them:<br>1. Can I fit LinuxBios with Etherboot to boot from SATA in 128KiB, it does not matter how much i chunk out as long as the machine boots!
<br>2. If this is true, can someone PLEASE tell me how to build Etherboot under x86_64?<br>Thanks,<br clear="all"><br>-- <br>------------------------<br>Arturo Mann, <a href="mailto:arturo.mann at gmail.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">

arturo.mann at gmail.com</a><br><br>


------=_Part_17672_5643318.1151020394068--



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.58.1355071017.16123.coreboot@coreboot.org>

Ive just tried LB on a VIA-EPAI-PD10000 board using the EPAI-M LB config (i dont have a serial cable connected at present, going to grab one tomorow!)
using my post card i get the following sequance displayed : 10/80/05 (all hex)
can anyone poinbt me in the write direction ether for a list of the bios codes or if thats not available, then what the above codes indicate.
I get no video output when trying to boot to the LB.
It has been compiled from latest svn, with filo.
If there is any other info that might help, please let me know, im hoping the post codes may point to something stupid i did in configuring/installing LB.

Thanks

Matt
P.S. The EIPA-PD apears to use the saem chipsets as the EPIA-M, so im asuming the LB should work (at least to some extent)

--bound1151714580--




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.59.1355071023.16123.coreboot@coreboot.org>

them, 1000 boards probably is.

Maybe this is an area where the FSF could help to gain momentum?
I got some pretty good contacts to some of the companies meanwhile, but
most of our customers think 1000 boards is a whole lot.

Stefan

-- 
coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ??? Fax: +49 761 7664613
Email: info at coresystems.de  ??? http://www.coresystems.de/



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.60.1355071024.16123.coreboot@coreboot.org>

We have been trying to solve the via EPIA vt8601 problem but its
complicated by the fact that most of the older revs won't build
anymore.  Compiling romcc pukes on a lot of them.  Upgrading romcc and
then trying and older rev gets ugly quick.

What toolchain were you on when you did most of your work on romcc?

-- 
Richard A. Smith



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.61.1355071026.16123.coreboot@coreboot.org>

into an existing ELF file.

Cheers,
Adam.



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.62.1355071028.16123.coreboot@coreboot.org>

The board is industrial grade, and it can be found here:
http://www.icpamerica.com/products/single_board_computers/5_25_NOVA/NOVA-4899.html

The version I have has the realtek ethernet chips.

Now, for my questions:

1) if I don't specify a device in config.lb, Linux will still be able
to recognize it
2) about IRQ sharing, what is the best solution
3) is it possible to enable ACPI without having the tables from the factory bios

Below you'll find an 'lspci -vvv' that I managed to produce

Thanks for all the input you may provide.

Luis Correia


lspci -vvv output

00:00.0 Host bridge: Cyrix Corporation PCI Master
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 0

00:0a.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ (rev 10)
	Subsystem: Realtek Semiconductor Co., Ltd. RT8139
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 9
	Region 0: I/O ports at e000 [size=256]
	Region 1: Memory at d0000000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0b.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ (rev 10)
	Subsystem: Realtek Semiconductor Co., Ltd. RT8139
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 12
	Region 0: I/O ports at e400 [size=256]
	Region 1: Memory at d0001000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0c.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ (rev 10)
	Subsystem: Realtek Semiconductor Co., Ltd. RT8139
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 10
	Region 0: I/O ports at e800 [size=256]
	Region 1: Memory at d0002000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:12.0 ISA bridge: Cyrix Corporation 5530 Legacy [Kahlua] (rev 30)
	Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV+ VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 64, Cache Line Size 04

00:12.1 Bridge: Cyrix Corporation 5530 SMI [Kahlua]
	Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Region 0: Memory at 40012000 (32-bit, non-prefetchable) [size=256]

00:12.2 IDE interface: Cyrix Corporation 5530 IDE [Kahlua] (prog-if 80 [Master])
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Region 4: I/O ports at f000 [size=16]

00:12.3 Multimedia audio controller: Cyrix Corporation 5530 Audio [Kahlua]
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Region 0: Memory at 40011000 (32-bit, non-prefetchable) [size=128]

00:12.4 VGA compatible controller: Cyrix Corporation 5530 Video
[Kahlua] (prog-if 00 [VGA])
	Subsystem: Cyrix Corporation: Unknown device 0001
	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Region 0: Memory at 40800000 (32-bit, non-prefetchable) [size=8M]

00:13.0 USB Controller: Compaq Computer Corporation ZFMicro Chipset
USB (rev 06) (prog-if 10 [OHCI])
	Subsystem: Compaq Computer Corporation ZFMicro Chipset USB
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (20000ns max), Cache Line Size 08
	Interrupt: pin A routed to IRQ 11
	Region 0: Memory at d0006000 (32-bit, non-prefetchable) [size=4K]



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.73.1355071035.16123.coreboot@coreboot.org>

problems tracking down just where it hangs.

At first sight it appears to happen inside the SMBus read function, but
that is a guess from the debug output.
The problem I get is if I try and add any debug output inside SMBus read
it gets worse and locks more frequently.

If I have the memory test enabled it can also lock up when doing the verify.

So I guess I can think of 3 reason for it to lock.

    1. Some enabled, but not handled interrupt is happening.  (I would
assume that all interrupts are disabled at powerup but hardware so this
is probably not it)

    2. Southbridge is not configured properly.    (would be very bad
chip design if the SMBus part of the southbridge interferred with the
rest of the functionality)

    3. It is actually running, but serial output has stopped. ( don't
think this is the case as it never boots up)


I guess I need to look for loops that can become locked, probably
withing the serial output code.

Can anyone think of some other reason for it to lock up ?






From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.93.1355071039.16123.coreboot@coreboot.org>

off list into the issue tracker. When a new patch occurs for the same
issue, it should be attached to an existing ticket.

Also, Acked-By: and Signed-off-by: messages should be added to the
tracker instead of using emails now (emails will be sent to the list
when you do this, anyways), so we have a logically structured overview 
on changes that happen to LinuxBIOS.

Have fun using the tool!

Questions, ideas and flames are welcome, as always.


Best regards,
Stefan


-- 
coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ??? Fax: +49 761 7664613
Email: info at coresystems.de  ??? http://www.coresystems.de/



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.110.1355071044.16123.coreboot@coreboot.org>

The PROMJet has a clever function where a sequence of reads from ROM
are interpreted as a debug write, and sent to the host.

Could be a killer feature if we can't use any kind of serial.
(I know that the PROMJet is expensive, but the feature is simple.)

Will at least some part of the ROM always be readable after reset?
Is that defined by the CPU?

Does/will it happen that something between CPU and flash actually
pre-loads the ROM so that there's no direct communication path?


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.121.1355071045.16123.coreboot@coreboot.org>

living with 15-second BIOS times?

If so, pointers on how to get started would be appreciated.

Thanks

George


#lspci -vvv
00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express
Processor to DRAM Controller (rev 04)
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
        Latency: 0
        Capabilities: [e0] Vendor Specific Information

00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML
Express Graphics Controller (rev 04) (prog-if 00 [VGA])
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin A routed to IRQ 193
        Region 0: Memory at d0180000 (32-bit, non-prefetchable) [size=512K]
        Region 1: I/O ports at ea00 [size=8]
        Region 2: Memory at c0000000 (32-bit, prefetchable) [size=256M]
        Region 3: Memory at d0200000 (32-bit, non-prefetchable) [size=256K]
        Capabilities: [d0] Power Management version 2
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML
Express Graphics Controller (rev 04)
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Region 0: Memory at d0100000 (32-bit, non-prefetchable) [size=512K]
        Capabilities: [d0] Power Management version 2
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB UHCI #1 (rev 04) (prog-if 00 [UHCI])
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin A routed to IRQ 177
        Region 4: I/O ports at eb00 [size=32]

00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB UHCI #2 (rev 04) (prog-if 00 [UHCI])
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin B routed to IRQ 185
        Region 4: I/O ports at ed00 [size=32]

00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB UHCI #3 (rev 04) (prog-if 00 [UHCI])
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin C routed to IRQ 169
        Region 4: I/O ports at e800 [size=32]

00:1d.3 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB UHCI #4 (rev 04) (prog-if 00 [UHCI])
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin D routed to IRQ 193
        Region 4: I/O ports at e900 [size=32]

00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB2 EHCI Controller (rev 04) (prog-if 20 [EHCI])
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin A routed to IRQ 177
        Region 0: Memory at d0240000 (32-bit, non-prefetchable) [size=1K]
        Capabilities: [50] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d4)
(prog-if 01 [Subtractive decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=32
        I/O behind bridge: 0000d000-0000dfff
        Memory behind bridge: d0000000-d00fffff
        Prefetchable memory behind bridge: 0000000010000000-0000000010000000
        Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ <SERR- <PERR-
        BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
        Capabilities: [50] #0d [0000]

00:1e.2 Multimedia audio controller: Intel Corporation 82801FB/FBM/FR/FW/FRW
(ICH6 Family) AC'97 Audio Controller (rev 04)
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin A routed to IRQ 201
        Region 0: I/O ports at e000 [size=256]
        Region 1: I/O ports at ec00 [size=64]
        Region 2: Memory at d0241000 (32-bit, non-prefetchable) [size=512]
        Region 3: Memory at d0242000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [50] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:1f.0 ISA bridge: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge
(rev 04)
        Subsystem: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0

00:1f.1 IDE interface: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family)
IDE Controller (rev 04) (prog-if 8a [Master SecP PriP])
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin A routed to IRQ 169
        Region 0: I/O ports at <unassigned>
        Region 1: I/O ports at <unassigned>
        Region 2: I/O ports at <unassigned>
        Region 3: I/O ports at <unassigned>
        Region 4: I/O ports at f000 [size=16]

00:1f.3 SMBus: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus
Controller (rev 04)
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Interrupt: pin B routed to IRQ 185
        Region 4: I/O ports at 5000 [size=32]

01:03.0 FireWire (IEEE 1394): Agere Systems FW323 (rev 61) (prog-if 10
[OHCI])
        Subsystem: AOPEN Inc. Unknown device 030a
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32 (3000ns min, 6000ns max), Cache Line Size: 32 bytes
        Interrupt: pin A routed to IRQ 185
        Region 0: Memory at d0021000 (32-bit, non-prefetchable) [size=4K]
        Capabilities: [44] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME+

01:06.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8169
Gigabit Ethernet (rev 10)
        Subsystem: AOPEN Inc. Unknown device 0589
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32 (8000ns min, 16000ns max), Cache Line Size: 32 bytes
        Interrupt: pin A routed to IRQ 169
        Region 0: I/O ports at d000 [size=256]
        Region 1: Memory at d0020000 (32-bit, non-prefetchable) [size=256]
        [virtual] Expansion ROM at 10000000 [disabled] [size=128K]
        Capabilities: [dc] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
PME(D0-,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

------=_Part_186_33092904.1164678298128
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<div>I'd like to get LinuxBIOS running on an AOpen Mini PC.</div>
<div>&nbsp;</div>
<div>From the output below, do you think this is doable?&nbsp; Or am I doomed to living with 15-second BIOS times?</div>
<div>&nbsp;</div>
<div>If so, pointers on how to get started would be appreciated.</div>
<div>&nbsp;</div>
<div>Thanks</div>
<div>&nbsp;</div>
<div>George</div>
<div>&nbsp;</div>
<div>&nbsp;</div>
<div>#lspci -vvv<br>00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 04)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast &gt;TAbort- &lt;TAbort- &lt;MAbort+ &gt;SERR- &lt;PERR-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Capabilities: [e0] Vendor Specific Information<br><br>00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04) (prog-if 00 [VGA]) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin A routed to IRQ 193<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 0: Memory at d0180000 (32-bit, non-prefetchable) [size=512K]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 1: I/O ports at ea00 [size=8]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 2: Memory at c0000000 (32-bit, prefetchable) [size=256M] 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 3: Memory at d0200000 (32-bit, non-prefetchable) [size=256K]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Capabilities: [d0] Power Management version 2<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: D0 PME-Enable- DSel=0 DScale=0 PME-<br><br>00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 0: Memory at d0100000 (32-bit, non-prefetchable) [size=512K]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Capabilities: [d0] Power Management version 2<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: D0 PME-Enable- DSel=0 DScale=0 PME-<br><br>00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 (rev 04) (prog-if 00 [UHCI])<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin A routed to IRQ 177<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 4: I/O ports at eb00 [size=32]<br><br>00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 (rev 04) (prog-if 00 [UHCI]) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin B routed to IRQ 185<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 4: I/O ports at ed00 [size=32]<br><br>00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 (rev 04) (prog-if 00 [UHCI]) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin C routed to IRQ 169<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 4: I/O ports at e800 [size=32]<br><br>00:1d.3 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 (rev 04) (prog-if 00 [UHCI]) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin D routed to IRQ 193<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 4: I/O ports at e900 [size=32]<br><br>00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 04) (prog-if 20 [EHCI]) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin A routed to IRQ 177<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 0: Memory at d0240000 (32-bit, non-prefetchable) [size=1K]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Capabilities: [50] Power Management version 2<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: D0 PME-Enable- DSel=0 DScale=0 PME-<br><br>00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d4) (prog-if 01 [Subtractive decode])<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Bus: primary=00, secondary=01, subordinate=01, sec-latency=32<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O behind bridge: 0000d000-0000dfff 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Memory behind bridge: d0000000-d00fffff<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Prefetchable memory behind bridge: 0000000010000000-0000000010000000<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort+ &lt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- &gt;Reset- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Capabilities: [50] #0d [0000]<br><br>00:1e.2 Multimedia audio controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller (rev 04) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin A routed to IRQ 201<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 0: I/O ports at e000 [size=256]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 1: I/O ports at ec00 [size=64]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 2: Memory at d0241000 (32-bit, non-prefetchable) [size=512] 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 3: Memory at d0242000 (32-bit, non-prefetchable) [size=256]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Capabilities: [50] Power Management version 2<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: D0 PME-Enable- DSel=0 DScale=0 PME-<br><br>00:1f.0 ISA bridge: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge (rev 04)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br><br>00:1f.1 IDE interface: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller (rev 04) (prog-if 8a [Master SecP PriP])<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 0<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin A routed to IRQ 169<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 0: I/O ports at &lt;unassigned&gt; 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 1: I/O ports at &lt;unassigned&gt;<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 2: I/O ports at &lt;unassigned&gt;<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 3: I/O ports at &lt;unassigned&gt;<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 4: I/O ports at f000 [size=16]<br><br>00:1f.3
 SMBus: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller (rev 04)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin B routed to IRQ 185<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 4: I/O ports at 5000 [size=32]<br>
<br>01:03.0 FireWire (IEEE 1394): Agere Systems FW323 (rev 61) (prog-if 10 [OHCI])<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 030a<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 32 (3000ns min, 6000ns max), Cache Line Size: 32 bytes<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin A routed to IRQ 185 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 0: Memory at d0021000 (32-bit, non-prefetchable) [size=4K]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Capabilities: [44] Power Management version 2<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: D0 PME-Enable- DSel=0 DScale=0 PME+<br><br>01:06.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8169 Gigabit Ethernet (rev 10)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subsystem: AOPEN Inc. Unknown device 0589<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Latency: 32 (8000ns min, 16000ns max), Cache Line Size: 32 bytes<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Interrupt: pin A routed to IRQ 169<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 0: I/O ports at d000 [size=256]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Region 1: Memory at d0020000 (32-bit, non-prefetchable) [size=256] 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; [virtual] Expansion ROM at 10000000 [disabled] [size=128K]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Capabilities: [dc] Power Management version 2<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) 
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Status: D0 PME-Enable- DSel=0 DScale=0 PME-<br><br>&nbsp;</div>

------=_Part_186_33092904.1164678298128--



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.122.1355071047.16123.coreboot@coreboot.org>

---->	nForce 550/570/570/590 SLI (C51+MCP55) driver package 9.16 WHQL
consists of the following components:

	. Ethernet Driver MCP55 (v60.15) "WHQL"
	. Network Management Tools MCP55 (v55.23)
	. SMBus Driver (v4.52) "WHQL"
	. Installer (v5.05)
	. WinXP IDE SataRAID Driver (v6.66) "WHQL"
	. WinXP IDE SataIDE Driver (v6.66) "WHQL"
	. WinXP RAIDTOOL Application (v6.63)

	This WinXP 64-bit nForce (MCP55) 9.16 driver package consists of the
following components:

	. Ethernet Driver MCP55 (v60.15) "WHQL"
	. Network Management Tools MCP55 (v55.23)
	. SMBus Driver (v4.52) "WHQL"
	. Installer (v5.05)
	. WinXP IDE SataRAID Driver (v6.66) "WHQL"
	. WinXP IDE SataIDE Driver (v6.66) "WHQL"
	. WinXP RAIDTOOL Application (v6.63)

So I think it's C51+MCP55, but maybe a true "hardware" guy could confirm ;)

Simon Labrecque

-----Original Message-----
From: Lu, Yinghai [mailto:yinghai.lu at amd.com] 
Sent: Thursday, November 30, 2006 1:52 PM
To: Carl-Daniel Hailfinger; Simon Labrecque
Cc: ron minnich; linuxbios at linuxbios.org
Subject: RE: [LinuxBIOS] Support for recent chipset and powerful desktop CPU

-----Original Message-----
From: linuxbios-bounces+yinghai.lu=amd.com at linuxbios.org
[mailto:linuxbios-

>Both of them would be good targets. Both have onboard serial ports and
both
>are passively cooled.
>
>Differences between the two boards:
>K9N Platinum
>* nForce 570
>* 6 internal USB ports
>* 6 SATA ports
>* 2x Gbit LAN
>* Firewire <------ good for Media Center

What is NForce 570? 

Is it C51+MCP55?

YH





From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.124.1355071047.16123.coreboot@coreboot.org>

some lines in buffer.

YH






From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.131.1355071048.16123.coreboot@coreboot.org>

0. Now if the base address is set wrongly that would explain why the ide
enable is coming back with what appears to be invalid register values.

Anyone have any thoughts ?

many thanks
Ben



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.134.1355071049.16123.coreboot@coreboot.org>

I have the 4M version - it's my main computer.

What else would you like to know?

   Russ





From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.135.1355071050.16123.coreboot@coreboot.org>

00:11.1 IDE interface: VIA Technologies, Inc.
VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06)
(prog-if 8a [Master SecP PriP])
    Subsystem: VIA Technologies, Inc. Unknown device 6010
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
    Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
    Latency: 32
    Region 4: I/O ports at d000 [size=16]
    Capabilities: [c0] Power Management version 2
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
        Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 d0 00 00 00 00 00 00 00 00 00 00 06 11 10 60


10h - 1Ch above are all 0, so I assume that there are no BASE ADDRESS
registers allocated here. One thing I am curious about is that according
to the PCI spec (I only have version 2.1) the base address registers
start at 10h, so why, in the above , does the IDE controller, and in
fact most of the devices on the board use the higher base address
registers ?

Another question I have is the fact that 20h contians d001h. The PCI
spec does mention that a device  may have don't care bits in the base
address. So can I assume that, that is the case here ?

Or is there some strange bit shifting going on ?

What confuses me is that on an earlier version (head version 2401) this
worked. Comparing the two versions I can see there have been changes to
the PCI parts of the code, but nothing to dramatic, and as I have said
no one else seems to be having problems.

The EPIA code is more or less the same, just a few text changes in the
debug so was it just working by luck before ?

Does anyone have any thoughts on why the enumeration is wrong ?

I guess I am looking at a wrongly configured southbridge chip or
northbridge chip.


Ben.



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.149.1355071052.16123.coreboot@coreboot.org>

but the SMM registers on the AMD K8 platform are locked using the SMMLOCK
bit. How does the platform then handle SMI when using LinuxBIOS? I would
be grateful for any advice or gotchas for my implementation.

Thanks,
Arvind







From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.151.1355071054.16123.coreboot@coreboot.org>

"The new Technologic Systems Bootloader is totally Linux-based,
enabling much more control over the system through all the standard
Linux utility commands from inside the bootloader itself. Meanwhile,
it delivers fast bootup time, as short as 1.1 seconds, and small
footprint, not only meeting the requirements of the real-world
embedded systems, but delivering additional flexibility and power
instead. After all, it is Linux booting Linux.

The "bootload" facility may be useful for kernel developers, since
they now have a faster way to test their new kernels without rebooting
the whole system. In case a fast bootup solution is not being used,
developers benefit from the use of the "bootload" program given that
the time spent with firmware loading will be saved.

Also, the new Bootloader solution allows the use of standard shell
scripts for the programmatic selection of appropriate kernels, Linux
initrd's, and kernel command line arguments for maximum flexibility.
Click on the link below and find out how the TS-7400 takes advantage
of these features in order to provide multiple booting options via
Linux shell scripts:"
ron

---------- Forwarded message ----------

Date: Jan 10, 2007 9:21 AM
Subject: 1.1 sec from power on to Linux shell (busybox) prompt
To: ron minnich <rminnich at gmail.com>


I know these guys provided the lunchbox boards you described in your Linux
Journal article.  I like how they accelerated flash boot by implementing HW
ECC in the CPLD.  Nice work.  This would have been nice in OLPC.

  http://www.embeddedarm.com/linux/linuxbootloader.htm



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.167.1355071057.16123.coreboot@coreboot.org>

segment is reserved, and a part is available as memory. Does the linux
code require that a 64k segment be all one or the other? What are the
rules here?

thanks

ron
===
Hello,

I have this situation:

Linuxbios boots an Opteron motherboard with 1GB memory.

Linuxbios directly loads a recent linux kernel.
The memory layout is like this:

BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
 BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
 BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
 BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved)
 BIOS-e820: 00000000000f0400 - 0000000040000000 (usable)

The f0000-f0400 region contains IRQ and ACPI tables.

At some point the kernel builds a resource table containing
all physical address ranges and type of hardware the addresses
are mapped to. The table is accessible via /proc/iomem:

# cat /proc/iomem
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
e0000000-efffffff : PCI Bus #03
  e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
  f4000000-f4ffffff : 0000:03:00.0
  f5000000-f5ffffff : 0000:03:00.0
  f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
  f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
  f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
  f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

As you can see, the 00000000000f0400-0000000040000000
region is not listed.

It is not listed because the kernel unconditionally adds
"000f0000-000fffff : System ROM" first (look for
"request_resource(&iomem_resource, &system_rom_resource)"),
and then the attempt to add f0400-40000000 range fails
because of overlapping.

The kernel does not care that the range is not listed there.
Kexec does. It uses the /proc/iomem file to instruct the
kexec system call how to place the segments of a new kernel
in the physical memory. Kexec fails to start a new kernel
because it cannot locate enough physical memory.

This must be fixed either in linux or linuxbios.

Assuming that linuxbios is to be fixed, I cooked a patch
which provides this memory layout:

BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
 BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
 BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
 BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
 BIOS-e820: 0000000000100000 - 0000000040000000 (usable)

The /proc/iomem contains:

# cat /proc/iomem
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
00100000-3fffffff : System RAM
  00100000-00203c61 : Kernel code
  00203c62-00248c3f : Kernel data
e0000000-efffffff : PCI Bus #03
  e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
  f4000000-f4ffffff : 0000:03:00.0
  f5000000-f5ffffff : 0000:03:00.0
  f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
  f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
  f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
  f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

Kexec is happier with the patch.



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.168.1355071058.16123.coreboot@coreboot.org>

ROM signature.  Regardless with my patch that switches the order the
current error handling challenged code will simply drop those regions.

Eric






From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.182.1355071061.16123.coreboot@coreboot.org>

after 0xC0000 segment, but it is pointing to wrong place (segment
0x32).

I don't know why it is occuring with LinuxBIOS. All appear go fine,
but just the Interrupt Pointer is wrong.

There is someone running X Server (with Driver "vesa" on X config)?
I verified this error occur with default X Server as with Xvesa.

Cheers,

Alan

P.S.: I am sending the serial console log attached, maybe it give some help.






LinuxBIOS-2.0.0_s2850_Fallback Sun Feb 25 16:10:36 BRT 2007 starting...
SBLink=00
NC node|link=00
Ram1.00
Ram2.00
Ram3
Initializing memory:  done
Ram4
v_esp=000cffe4
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Copying LinuxBIOS to RAM.
src=fffe0000
dst=00004000
linxbios_ram.nrv2b length = 0000d7d7
linxbios_ram.bin   length = 00023150
Jumping to LinuxBIOS.
LinuxBIOS-2.0.0_s2850_Fallback Sun Feb 25 18:34:50 BRT 2007 booting...
Enumerating buses...
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
  PCI: 00:18.3 siblings=0
CPU: APIC: 00 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] enabled
PCI: 01:00.0 [1022/7460] enabled
PCI: 01:01.0 [1022/7460] enabled next_unitid: 0005
PCI: pci_scan_bus for bus 01
PCI: 01:01.0 [1022/7460] enabled
PCI: 01:02.0 [1022/7468] enabled
PCI: 01:02.1 [1022/7469] enabled
PCI: 01:02.2 [1022/746a] enabled
PCI: 01:02.3 [1022/746b] enabled
PCI: 01:02.5 [1022/746d] enabled
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [1022/7464] enabled
PCI: 02:00.1 [1022/7464] enabled
PCI: 02:0b.0 [1002/4752] enabled
PCI: 02:0d.0 [14e4/1653] enabled
PCI: 02:0e.0 [14e4/1653] enabled
PCI: pci_scan_bus returning with max=002
PNP: 002e.0 enabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 disabled
PNP: 002e.5 enabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
PNP: 002e.b enabled
smbus: PCI: 01:02.3[0]->I2C: 01:50 enabled
smbus: PCI: 01:02.3[0]->I2C: 01:51 enabled
smbus: PCI: 01:02.3[0]->I2C: 01:52 enabled
smbus: PCI: 01:02.3[0]->I2C: 01:53 enabled
PCI: pci_scan_bus returning with max=002
PCI: pci_scan_bus returning with max=002
done
Allocating resources...
Reading resources...
PCI: 01:01.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 02 prefmem
Done reading resources.
Allocating VGA resource PCI: 02:0b.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 01:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Setting resources...
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 1b8 <- [0x00fd100000 - 0x00fd0fffff] prefmem <node 0 link 0>
PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] io <node 0 link 0>
PCI: 00:18.0 1b0 <- [0x00fc000000 - 0x00fd0fffff] mem <node 0 link 0>
PCI: 01:01.0 1c <- [0x0000001000 - 0x0000001fff] bus 02 io
PCI: 01:01.0 20 <- [0x00fc000000 - 0x00fd0fffff] bus 02 mem
PCI: 02:00.0 10 <- [0x00fd040000 - 0x00fd040fff] mem
PCI: 02:00.1 10 <- [0x00fd041000 - 0x00fd041fff] mem
PCI: 02:0b.0 10 <- [0x00fc000000 - 0x00fcffffff] mem
PCI: 02:0b.0 14 <- [0x0000001000 - 0x00000010ff] io
PCI: 02:0b.0 18 <- [0x00fd042000 - 0x00fd042fff] mem
PCI: 02:0b.0 30 <- [0x00ffe00000 - 0x00ffe1ffff] romem
PCI: 02:0d.0 10 <- [0x00fd000000 - 0x00fd00ffff] mem64
PCI: 02:0d.0 30 <- [0x00fd010000 - 0x00fd01ffff] romem
PCI: 02:0e.0 10 <- [0x00fd020000 - 0x00fd02ffff] mem64
PCI: 02:0e.0 30 <- [0x00fd030000 - 0x00fd03ffff] romem
PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] io
PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] irq
PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] io
PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] irq
PCI: 01:02.1 20 <- [0x0000002860 - 0x000000286f] io
PCI: 01:02.2 10 <- [0x0000002840 - 0x000000285f] io
PCI: 01:02.3 58 <- [0x0000002000 - 0x00000020ff] io
PCI: 01:02.5 10 <- [0x0000002400 - 0x00000024ff] io
PCI: 01:02.5 14 <- [0x0000002800 - 0x000000283f] io
PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] mem <gart>
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 140
PCI: 01:01.0 bridge ctrl <- 000b
PCI: 01:01.0 cmd <- 147
PCI: 02:00.0 subsystem <- 10f1/2850
PCI: 02:00.0 cmd <- 142
PCI: 02:00.1 subsystem <- 10f1/2850
PCI: 02:00.1 cmd <- 142
PCI: 02:0b.0 subsystem <- 10f1/2850
PCI: 02:0b.0 cmd <- 1c3
PCI: 02:0d.0 cmd <- 142
PCI: 02:0e.0 cmd <- 142
PCI: 01:02.0 subsystem <- 10f1/2850
PCI: 01:02.0 cmd <- 14f
w83627hf hwm smbus enabled
PCI: 01:02.1 subsystem <- 10f1/2850
PCI: 01:02.1 cmd <- 141
PCI: 01:02.2 subsystem <- 10f1/2850
PCI: 01:02.2 cmd <- 141
PCI: 01:02.3 subsystem <- 10f1/2850
PCI: 01:02.3 cmd <- 141
PCI: 01:02.5 subsystem <- 10f1/2850
PCI: 01:02.5 cmd <- 141
PCI: 00:18.1 subsystem <- 10f1/2850
PCI: 00:18.1 cmd <- 140
PCI: 00:18.2 subsystem <- 10f1/2850
PCI: 00:18.2 cmd <- 140
PCI: 00:18.3 cmd <- 140
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor AMD device f5a
CPU: family 0f, model 05, stepping 0a
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

microcode: equivalent processor rev id  = 0x004a, patch id = 0x00000000
microcode: patch id that want to apply= 0x00000047
microcode: updated to patch id = 0x00000047  success
CPU model AMD Athlon(tm) 64 FX-53 Processor
Setting up local apic... apic_id: 0x00 done.
Clearing memory 2048K - 524288K: ------- done
CPU #0 Initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 01:01.0 init
PCI: 02:0b.0 init
rom address for PCI: 02:0b.0 = ffe00000
copying VGA ROM Image from 0xffe00000 to 0xc0000, 0x9000 bytes
entering emulator
halt_sys: file /home/alan/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c,
line 47PCI: 01:02.0 init
amd8111: ioapic bsp_apicid = 00
RTC Init
Invalid CMOS LB checksum
enabling HPET @0xfed00000
PNP: 002e.0 init
PNP: 002e.2 init
PNP: 002e.5 init
PNP: 002e.b init
PCI: 01:02.1 init
IDE1 IDE0 PCI: 01:02.3 init
set power on after power fail
PCI: 00:18.1 init
PCI: 00:18.2 init
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 02:0d.0 init
rom address for PCI: 02:0d.0 = fd000000
Incorrect Expansion ROM Header Signature 14e4
PCI: 02:0e.0 init
rom address for PCI: 02:0e.0 = fd020000
Incorrect Expansion ROM Header Signature 14e4
Devices initialized
Copying IRQ routing tables to 0xf0000...done.
Verifing copy of IRQ routing tables at 0xf0000...done
Checking IRQ routing table consistency...
check_pirq_routing_table() - irq_routing_table located at: 0x000f0000
/home/alan/LinuxBIOSv2/src/arch/i386/boot/pirq_routing.c:
36:check_pirq_routddone.
Wrote the mp table end at: 00000020 - 000001e8
Moving GDT to 0x500...ok
Wrote linuxbios table at: 00000530 - 00000db8  checksum 2104

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3

rom_stream: 0xffe09000 - 0xfffdffff
Found ELF candidate at offset 0
Dropping non PT_LOAD segment
New segment addr 0x10000 size 0x1ab24 offset 0x134 filesize 0x561c
(cleaned up) New segment addr 0x10000 size 0x1ab24 offset 0x134 filesize 0x561c
New segment addr 0x91000 size 0x70 offset 0x5750 filesize 0x0
(cleaned up) New segment addr 0x91000 size 0x70 offset 0x5750 filesize 0x0
New segment addr 0x100000 size 0x700000 offset 0x5750 filesize 0x1bb5f9
(cleaned up) New segment addr 0x100000 size 0x700000 offset 0x5750
filesize 0x19Loading Segment: addr: 0x000000001ffb0000 memsz:
0x000000000001ab24 filesz: 0x0cClearing Segment: addr:
0x000000001ffb561c memsz: 0x0000000000015508
Loading Segment: addr: 0x0000000000091000 memsz: 0x0000000000000070
filesz: 0x00Clearing Segment: addr: 0x0000000000091000 memsz:
0x0000000000000070
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000700000
filesz: 0x09Clearing Segment: addr: 0x00000000002bb5f9 memsz:
0x0000000000544a07
Jumping to boot code at 0x10000
Firmware type: LinuxBIOS



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.193.1355071065.16123.coreboot@coreboot.org>

> How do the bytes change every time in 5 boots? Are
> bytes just increasing?
> 
> > So.... are flashrom and Q-flash doing the right thing (disabling shadowing),
> > and if so, what's causing those 3 bytes to be different each time?
> 
> Yes, shadow handling seems to work fine. The BIOS has _some_ reason to
> change it's config (which is far bigger than the 256 bytes of nvram
> nowadays, --> ESCD/DMI)
> 
> Have you changed the configuration of the machine? (Enable/Disable
> Floppy, ...?)

I have not changed anything after enabling the floppy - and 3 bytes change
every boot, indeed.

> Can you please observe the changes over several consequtive reboots (5
> or so)

I will do that Monday or Tuesday, and report back.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.194.1355071065.16123.coreboot@coreboot.org>

plain IDE device will in fact work, but I did not want to do that
because the card could be unplugged after boot and Linux would
surely not like that. (At the very least, the slot would stop
working until reboot, not good enough.)

Linux pcmcia did not start the CF slot until after udevstart was
run, so initramfs/initrd was required for root on CF.

I discussed this on linux-pcmcia and it seems that in the 2.6.18rc7
kernel I was using the CF card just wasn't added to the kernel
drivers, but it has been added since.

I'd like to try this with a recent kernel, it may just work now.


> As for my current issue, I just read something that leads me to
> believe that I need to disable PCI support in filo, but I won't be
> able to try until later tonight.

Yes, that is correct. From my FILO Config:

IDE_DISK=1
PCMCIA_CF=1
#SUPPORT_PCI=1


Re long cycles, I suggest using an Etherboot payload. You can even
send FILO as a boot image to Etherboot, and experimenting with kernel
parameters becomes simple.

dhcpd.conf:
subnet 192.168.3.0 netmask 255.255.255.0 {
  range dynamic-bootp 192.168.3.25 192.168.3.99;
  option routers 192.168.3.1;
  option domain-name-servers 192.168.3.1;
  if substring (option vendor-class-identifier, 0, 9) = "PXEClient" {
    filename "/eb-5.4.1-via-rhine.zpxe";
  } else if substring (option vendor-class-identifier, 0, 9) = "Etherboot" {
    filename "/boot.elf";
    option vendor-encapsulated-options 3c:09:45:74:68:65:72:62:6f:6f:74:ff;
  }
}

Starting tftpd from the shell: (make sure to use hpa-tftp)
in.tftpd -l -s -p -u root /root/epia


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.196.1355071069.16123.coreboot@coreboot.org>

> Google Summer of Code(tm) is a program that offers student developers
> stipends to write code for various open source projects. Google will
> be working with a several open source, free software and
> technology-related groups to identify and fund several projects over a
> three month period.  Historically, the program has brought together
> over 1,000 students with over 100 open source projects, to create
> hundreds of thousands of lines of code.

Find more information at

        http://code.google.com/soc/

We also started setting up a list of ideas for student projects.

        http://linuxbios.org/GSoC

If you wish to participate, and take one of the projects, or have
another idea for a project, please contact me via email or apply via the
Google GSoC page.

Have fun!

Best regards,

   Stefan Reinauer

-- 
coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ??? Fax: +49 761 7664613
Email: info at coresystems.de  ??? http://www.coresystems.de/



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.200.1355071072.16123.coreboot@coreboot.org>

Is this still the vt8601 northbridge board?
what southbridge? In one of your previous mails you wrote 82C686, 
in another one VT8231?

You don't post any code that would allow people to help you debug the
problem.

The memory test in auto.c is not qualifying. If that jmp does not work,
your memory does not work. It really is that simple. This can be
frustrating, don't despair. 

Have you compared northbridge register dumps between linuxbios and the
legacy bios?


-- 
coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ??? Fax: +49 761 7664613
Email: info at coresystems.de  ??? http://www.coresystems.de/



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.201.1355071072.16123.coreboot@coreboot.org>

Is this still the vt8601 northbridge board?
what southbridge? In one of your previous mails you wrote 82C686, 
in another one VT8231?

You don't post any code that would allow people to help you debug the
problem.

The memory test in auto.c is not qualifying. If that jmp does not work,
your memory does not work. It really is that simple. This can be
frustrating, don't despair. 

Have you compared northbridge register dumps between linuxbios and the
legacy bios?


-- 
coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 ??? Fax: +49 761 7664613
Email: info at coresystems.de ??? http://www.coresystems.de/

-- 
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linuxbios at linuxbios.org
http://www.linuxbios.org/mailman/listinfo/linuxbios

 
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<div>Hi Stepen,</div>  <div>&nbsp;</div>  <div>I would like to thank you for the movitation you given to me. </div>  <div>&nbsp;</div>  <div>A. For the conveniance of clarity, i am again recapitulate the facts/figures about my board.</div>  <div>1. Northbridge: VT8605&nbsp; almost similar to VT8601 or VT8603</div>  <div>2.Southbridge: VT 82C686 which has integrated super I/O controller</div>  <div>3. CPU: 300Mhz Celeron Processor</div>  <div>4. Memory: 512 MB SDRAM</div>  <div>---------------------------------------------------------</div>  <div>if any other info, pls let me know</div>  <div>&nbsp;</div>  <div>B. </div>  <div>--------</div>  <div>&nbsp;&nbsp;&nbsp; 1. In this mail, i am sending you data as much as possible for you </div>  <div>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; comments/suggestion&nbsp;&nbsp; for improvment the porting process.</div>  <div>&nbsp;&nbsp;&nbsp; 2. Now i would like to ask couple of question. Since raminit does not complain any
 failure and ramcheck also passes ramtest.Next, code in crt0.S is able to copy the code from ROM to RAM. I am also able to read the code and print them in the serial output.So my question is, if i am able to read/write correct data to/from RAM, why is there doubt on incorrect DRAM initialisation?</div>  <div>If i am not able to jump to a designated place (0x4000) in RAM simply due incorrect DRAM initialisation, then what are those things which i am not taking care of during DRAM initialization? Can u pls hightlight those area in RAMINIT so that i can re-walk those area.</div>  <div>&nbsp;3. if really, the DRAM initialization is correct, then what are the factors that may stop/misdirect the control to jump to a correct location in RAM.</div>  <div>I tried to print the contents from the RAM which is copied from the ROM to RAM in the start of crt0.S, they are byte by byte same as is for c_start.o</div>  <div>&nbsp;</div>  <div>4. Are there any role of the register like AX,BX,
 CX and DX &amp; other index register while control is try to jump at ram location. For reference, i am also printed the contents of the register before jumping i.e jmp *%edi</div>  <div>5. In my config, i have set DCAHE_RAM =0</div>  <div>&nbsp;</div>  <div>6. i have&nbsp;compared the register dump for linuxbios and legacy bios.They are not exactly same. Should i try to cpmpare the entire dump&nbsp;or the register dump of device 00.0 only?&nbsp;</div>  <div>&nbsp;</div>  <div>&nbsp;</div>  <div>&nbsp;</div>  <div>B. I would also like to give you the register dump( for the Device&nbsp;00.0)&nbsp;of legacy BIOS</div>  <div>&nbsp;&nbsp;&nbsp;&nbsp; The ouput given below has been taken by lspci</div>  <div>&nbsp;&nbsp;&nbsp;&nbsp; --------------------------------------------------------------------</div>  <div>00: 06 11 05 06 06 00 10 22 00 00 00 06 00 00 00 00</div>  <div>10: 08 00 00 ec 00 00 00 00 00 00 00 00 00 00 00 00</div>  <div>20: 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00</div>  <div>30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00</div>  <div>40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</div>  <div>50: fd db c8 fe 02 00 20 20 e0 00 10 20 20 20 20 20</div>  <div>60: 3f 2a 00 a0 e6 00 00 00 41 7c 43 0f 08 21 00 00</div>  <div>70: c4 80 cc 0c 0e a1 d2 00 01 b4 09 00 00 00 00 00</div>  <div>80: 0f 40 00 00 c0 00 00 00 02 00 00 00 00 00 00 00</div>  <div>90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</div>  <div>a0: 02 c0 20 00 01 02 00 1f 00 00 00 00 27 12 00 00</div>  <div>b0: c0 ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00</div>  <div>c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00</div>  <div>d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</div>  <div>e0: 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</div>  <div>f0: 00 00 00 00 00 00 04 00 32 42 00 b0 00 00 00 00</div>  <div>&nbsp;</div>  <div>&nbsp;</div>  <div>&nbsp;</div>  <div>C. linuxbios log</div> 
 <div>------------------------------------------------------------------------</div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">LinuxBIOS-2.0.0.fallback Fri Mar 23 18:50:48 IST 2007 starting...<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">01 is the comm register<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">SMBus controller enabled<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">vt8605<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>init starting<o:p></o:p></FONT></SPAN></div>  <div
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00000000 is the north 1106 0605<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">0120NOP<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">PRECHARGE<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DUMMY READS<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">CBR<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier
 New">MRS<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">NORMAL<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">set ref. rate<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">enable multi-page open<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Register Dump (from LinuxBIOS) for Device 00.0<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">--------------------------------------------------<o:p></o:p></FONT></SPAN></div>  <div
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00:06 11 05 06 06 00 10 22 00 00 00 06 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">40:00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">50:ac 08 80 03 00 00 20 20 e0 00 20 20 20 20 20 20 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">60:3f 00 00 30 e6 00 00 00 41 7c 43 01 08 21 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">70:00 00 00 00 00 00 00 00 01 f0 00 02 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">80:00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">a0:02 c0 20 00 01 02 00 1f 00 00 00 00 00 02 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">b0:80 63 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">f0:00 00 00 00 00 00 04 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">&nbsp;<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">---Register Dump End here--------------------------<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">---RAM CHECKING (from
 0-640K &amp; 1M-16M)-------------<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Testing DRAM : 00000000-000a0000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM fill: 00000000-000a0000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00000000 00010000 00020000 00030000<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>00040000 00050000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00060000 00070000 00080000 00090000<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>000a0000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText
 style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM filled<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM verify: 00000000-000a0000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00000000 00010000 00020000 00030000<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>00040000 00050000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00060000 00070000 00080000 00090000<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>000a0000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM range
 verified.<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Done.<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">&nbsp;<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Testing DRAM : 00100000-01000000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM fill: 00100000-01000000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00100000 00110000 00120000 00130000 00140000 00150000 00160000 00170000
 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00180000 00190000 001a0000 001b0000 001c0000 001d0000 001e0000 001f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00200000 00210000 00220000 00230000 00240000 00250000 00260000 00270000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00280000 00290000 002a0000 002b0000 002c0000 002d0000 002e0000 002f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00300000 00310000 00320000 00330000 00340000 00350000 00360000 00370000 <o:p></o:p></FONT></SPAN></div>  <div
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00380000 00390000 003a0000 003b0000 003c0000 003d0000 003e0000 003f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00400000 00410000 00420000 00430000 00440000 00450000 00460000 00470000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00480000 00490000 004a0000 004b0000 004c0000 004d0000 004e0000 004f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00500000 00510000 00520000 00530000 00540000 00550000 00560000 00570000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00580000 00590000 005a0000 005b0000 005c0000 005d0000 005e0000 005f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00600000 00610000 00620000 00630000 00640000 00650000 00660000 00670000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00680000 00690000 006a0000 006b0000 006c0000 006d0000 006e0000 006f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00700000 00710000 00720000 00730000 00740000 00750000 00760000 00770000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT
 face="Courier New">00780000 00790000 007a0000 007b0000 007c0000 007d0000 007e0000 007f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00800000 00810000 00820000 00830000 00840000 00850000 00860000 00870000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00880000 00890000 008a0000 008b0000 008c0000 008d0000 008e0000 008f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00900000 00910000 00920000 00930000 00940000 00950000 00960000 00970000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00980000 00990000 009a0000 009b0000
 009c0000 009d0000 009e0000 009f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00a00000 00a10000 00a20000 00a30000 00a40000 00a50000 00a60000 00a70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00a80000 00a90000 00aa0000 00ab0000 00ac0000 00ad0000 00ae0000 00af0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00b00000 00b10000 00b20000 00b30000 00b40000 00b50000 00b60000 00b70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00b80000 00b90000 00ba0000 00bb0000 00bc0000 00bd0000 00be0000 00bf0000
 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00c00000 00c10000 00c20000 00c30000 00c40000 00c50000 00c60000 00c70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00c80000 00c90000 00ca0000 00cb0000 00cc0000 00cd0000 00ce0000 00cf0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00d00000 00d10000 00d20000 00d30000 00d40000 00d50000 00d60000 00d70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00d80000 00d90000 00da0000 00db0000 00dc0000 00dd0000 00de0000 00df0000 <o:p></o:p></FONT></SPAN></div>  <div
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00e00000 00e10000 00e20000 00e30000 00e40000 00e50000 00e60000 00e70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00e80000 00e90000 00ea0000 00eb0000 00ec0000 00ed0000 00ee0000 00ef0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00f00000 00f10000 00f20000 00f30000 00f40000 00f50000 00f60000 00f70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00f80000 00f90000 00fa0000 00fb0000 00fc0000 00fd0000 00fe0000 00ff0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">01000000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM filled<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM verify: 00100000-01000000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00100000 00110000 00120000 00130000 00140000 00150000 00160000 00170000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00180000 00190000 001a0000 001b0000 001c0000 001d0000 001e0000 001f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in
 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00200000 00210000 00220000 00230000 00240000 00250000 00260000 00270000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00280000 00290000 002a0000 002b0000 002c0000 002d0000 002e0000 002f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00300000 00310000 00320000 00330000 00340000 00350000 00360000 00370000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00380000 00390000 003a0000 003b0000 003c0000 003d0000 003e0000 003f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS
 Mincho'"><FONT face="Courier New">00400000 00410000 00420000 00430000 00440000 00450000 00460000 00470000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00480000 00490000 004a0000 004b0000 004c0000 004d0000 004e0000 004f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00500000 00510000 00520000 00530000 00540000 00550000 00560000 00570000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00580000 00590000 005a0000 005b0000 005c0000 005d0000 005e0000 005f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00600000 00610000
 00620000 00630000 00640000 00650000 00660000 00670000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00680000 00690000 006a0000 006b0000 006c0000 006d0000 006e0000 006f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00700000 00710000 00720000 00730000 00740000 00750000 00760000 00770000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00780000 00790000 007a0000 007b0000 007c0000 007d0000 007e0000 007f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00800000 00810000 00820000 00830000 00840000 00850000 00860000 00870000
 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00880000 00890000 008a0000 008b0000 008c0000 008d0000 008e0000 008f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00900000 00910000 00920000 00930000 00940000 00950000 00960000 00970000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00980000 00990000 009a0000 009b0000 009c0000 009d0000 009e0000 009f0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00a00000 00a10000 00a20000 00a30000 00a40000 00a50000 00a60000 00a70000 <o:p></o:p></FONT></SPAN></div>  <div
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00a80000 00a90000 00aa0000 00ab0000 00ac0000 00ad0000 00ae0000 00af0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00b00000 00b10000 00b20000 00b30000 00b40000 00b50000 00b60000 00b70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00b80000 00b90000 00ba0000 00bb0000 00bc0000 00bd0000 00be0000 00bf0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00c00000 00c10000 00c20000 00c30000 00c40000 00c50000 00c60000 00c70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00c80000 00c90000 00ca0000 00cb0000 00cc0000 00cd0000 00ce0000 00cf0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00d00000 00d10000 00d20000 00d30000 00d40000 00d50000 00d60000 00d70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00d80000 00d90000 00da0000 00db0000 00dc0000 00dd0000 00de0000 00df0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00e00000 00e10000 00e20000 00e30000 00e40000 00e50000 00e60000 00e70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT
 face="Courier New">00e80000 00e90000 00ea0000 00eb0000 00ec0000 00ed0000 00ee0000 00ef0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00f00000 00f10000 00f20000 00f30000 00f40000 00f50000 00f60000 00f70000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00f80000 00f90000 00fa0000 00fb0000 00fc0000 00fd0000 00fe0000 00ff0000 <o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">01000000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM range verified.<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in
 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Done.<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">-------------END OF AUTO.C----------------------------------<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">&nbsp;<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">&nbsp;<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">vt8605 done<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier
 New">&nbsp;<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">-----WE are in crt0.S-------<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Copying LinuxBIOS to RAM.<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">--regsister dump when copying is done-----<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing eax=00003333<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing ebx=ffffd14a<SPAN style="mso-tab-count:
 1">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </SPAN><o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing ecx=00000000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing edx=ffff03f8<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing esi=ffff7094<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing edi=00004000<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing cs=00000008<o:p></o:p></FONT></SPAN></div>  <div
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing ds=00000010<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">End of Register dump</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New"><o:p></o:p></FONT></SPAN>&nbsp;</div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Memory dump (from RAM 0x4000 upto 7094byte)</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New"><o:p>[I have intentionaly put some ee at the start of c_start.s for conveniance of identification. I have also deleted some of the last byte for saving
 space]</o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">-------------------------------------------<o:p></o:p></FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">ee2e0f011538410000ea104000001000b8180000008ed88ec08ed08ee08ee8b013</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">e680fc8d3d00600100b90080010029f9c1e90231c0f3ab8d3d2c340100b9e85401</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">0029f97407c1e90231c0f3abbc008001006a006a005589e58d3d10dc00008d1da1</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS
 Mincho'"><FONT face="Courier New">400000b8000010006689d889da66ba008e89470089570483c30683c70881ffb0dc</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">000075e30f011d08dc0000b0fee68089ece8a21e0000b0eee680f4ebf96a006a00</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">eb726a006a01eb6c6a006a02eb666a006a03eb606a006a04eb5a6a006a05eb546a</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">006a06eb4e6a006a07eb486a08eb4490906a006a09eb3c6a0aeb3890906a0beb32</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">90906a0ceb2c90906a0deb2690906a0eeb2090906a006a0feb186a006a10eb126a</FONT></SPAN></div> 
 <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">11eb0e90906a006a12eb066a006a13eb005756558d6c2420555352515054e8b51e</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00005858595a5b5d5d5e5f83c408cf2700e0db000090905589e56a036a0668f803</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">0000e8bf33000083c40cc9c35589e50fb645085068f8030000e838340000585ac9</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">c35589e568f8030000e8643400000fb6c0c9c35589e568f8030000e840340000c9</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier
 New">c39090905589e556538b750868d4c000006a07e8bc0700006a6c56e8b305000083</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">c8800fb6c0506a6c56e8330600006a7f6a4156e82906000083c4286a4056e88f05</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00000fb6c0506a4056e8120600006a4256e87b05000083c8f00fb6c0506a4256e8</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">fb05000083c4286a4a56e86105000083c8080fb6c0506a4a56e8e10500006a4f56</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">e84a05000083c8080fb6c0506a4f56e8ca05000083c4286a036a5856e8bd050000</FONT></SPAN></div>  <div class=MsoPlainText
 style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">83c40c85f6741a6a5156e81f05000083c8180fb6c0506a5156e89f05000083c414</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">6a5056e80505000088c30fb6c05068e4c000006a07e8f406000081e3f700000053</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">6803c100006a07e8e106000083c420536a5056e8630500006a4c56e8cc04000088</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">c389d883e00f50681cc100006a07e8b906000081e3f000000083cb0483c42053683</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier
 New">6c100006a07e8a0060000536a4c56e8250500006a046a4656e81b05000083c4246a</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">036a4756e80e05000068980000006a6e56e8010500006a546a4056e8f704000083c</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">4246a00e8c24d00005668ecdc0000684fc100006a06e84d06000083c41485f6742a</FONT></SPAN></div>  <div class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Jumping to LinuxBIOS.<o:p></o:p></FONT></SPAN></div>  <div>  <div><FONT color=#ff007f size=4>[After that, it simply hangs]<BR></FONT>---------------------------------------------------------------------------</div>  <div>if any other info is required to get out this problem, pls let me know.</div>  <div>&nbsp;</div> 
 <div>&nbsp;</div>  <div>Regards,</div>  <div>Sanjay<BR><B><I>Stefan Reinauer &lt;stepan at coresystems.de&gt;</I></B> wrote:</div></div>  <BLOCKQUOTE class=replbq style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #1010ff 2px solid">* sanjay tiwary <STIWARY20 at YAHOO.COM>[070323 14:20]:<BR>&gt; Hi<BR>&gt; <BR>&gt; I am not able to go beyound "Jumping to LinuxBIOS".Initially i thought<BR>&gt; it is a DRAM problem. But ram test passes. I am also able to<BR>&gt; read/write from/to RAM.So i guess my jump is not working. But i am not<BR>&gt; able to find out.<BR>&gt; So, Can anybody see the register dump which is taken before the jmp<BR>&gt; *%edi.<BR>&gt; <BR>&gt; LinuxBIOS-"2.0.0"".fallback" "Fri Mar 23 18:28:27 IST 2007" starting...<BR>&gt; Copying LinuxBIOS to RAM.<BR>&gt; Printing eax=00003333<BR>&gt; Printing ebx=ffffd14a<BR>&gt; Printing ecx=00000000<BR>&gt; Printing edx=ffff03f8<BR>&gt; Printing esi=ffff7092<BR>&gt; Printing edi=00004000<BR>&gt; Printing
 cs=00000008<BR>&gt; Printing ds=00000010<BR>&gt; End of Register dump<BR>&gt; --------------------------------------------<BR><BR>Sorry, this log contains no information useful for debugging the<BR>problem. <BR><BR>From the log it seems no memory init is done at all? <BR><BR>Is this still the vt8601 northbridge board?<BR>what southbridge? In one of your previous mails you wrote 82C686, <BR>in another one VT8231?<BR><BR>You don't post any code that would allow people to help you debug the<BR>problem.<BR><BR>The memory test in auto.c is not qualifying. If that jmp does not work,<BR>your memory does not work. It really is that simple. This can be<BR>frustrating, don't despair. <BR><BR>Have you compared northbridge register dumps between linuxbios and the<BR>legacy bios?<BR><BR><BR>-- <BR>coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.<BR>Tel.: +49 761 7668825 ??? Fax: +49 761 7664613<BR>Email: info at coresystems.de ??? http://www.coresystems.de/<BR><BR>--
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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.202.1355071072.16123.coreboot@coreboot.org>

be used to lock the chip write or chip select line.

Stefan

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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.203.1355071072.16123.coreboot@coreboot.org>

Is this still the vt8601 northbridge board?
what southbridge? In one of your previous mails you wrote 82C686, 
in another one VT8231?

You don't post any code that would allow people to help you debug the
problem.

The memory test in auto.c is not qualifying. If that jmp does not work,
your memory does not work. It really is that simple. This can be
frustrating, don't despair. 

Have you compared northbridge register dumps between linuxbios and the
legacy bios?


-- 
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Tel.: +49 761 7668825 ??? Fax: +49 761 7664613
Email: info at coresystems.de ??? http://www.coresystems.de/

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<div>Hi Stepen ,</div>  <div>Thanks !!!</div>  <div>&nbsp;</div>  <div>I tried to use the same sequence of RAM initialisation as is in northbridge/via/vt8601/raminit.c but i have use the legacy bios value whenever i am try to program the register you pointed out.</div>  <div>I have also programmed Reg 50-55 for CPU setup with the proper value from the legacy BIOS.Did proper setting for 0xf8 and 0xf9 at the end of DRAM initialisation.</div>  <div>&nbsp;</div>  <div>Still it is not jumping. I guess i am missing somewhere in the sequence of initialisation .</div>  <div>If u have any pointer , pls let me know.</div>  <div>Some of the more facts , i would like to tell you</div>  <div>1.I am enabling Shadow ram before starting the ram initialization. I dont know what impact it will make. Shadow ram register are 0x61, 0x62 and 0x63.</div>  <div>2. After SDRAM normal operation setiing to the 0x6c register, i am setting 0x5A-0x5F and 0x56,0x57 , 0x58 with the correct value as per
 the legacy BIOS. (Will this impact??).</div>  <div>3. I have also include the dump of northbridge device, pls have a look.</div>  <div>&nbsp;</div>  <div>----------------------</div>  <div>You were talking of Crystall Ball, can u tell me in details or any url to get this??</div>  <div>-----------------------</div>  <div>&nbsp;</div>  <div>This is the new log after setting the required register.</div>  <div>-----------------------------------------------------------------------------------------------</div><FONT size=2>  <div>Enabling vt82c686a_serial ...Enabling UART...Initializing Console ...</div>  <div>LinuxBIOS-2.0.0.SANJAY Mon Mar 26 03:18:17 IST 2007 starting...</div>  <div>Enabling Mainboard Devices ...Enabling smbus ...01 is the comm register</div>  <div>SMBus controller enabled</div>  <div>Enabling shadow ram...</div>  <div>Setting SDRAM Registervt8605 init starting</div>  <div>00000000 is the north</div>  <div>1106 0605</div>  <div>01d4 is the computed
 timing</div>  <div>Enabling SDRAMNOP</div>  <div>PRECHARGE</div>  <div>DUMMY READS</div>  <div>CBR</div>  <div>MRS</div>  <div>NORMAL</div>  <div>set ref. rate</div>  <div>enable multi-page open</div>  <div>Slot 00 is SDRAM 08000000 bytes x2</div>  <div>0100 is the chip size</div>  <div>000e is the MA type</div>  <div>vt8605 done</div>  <div>Testing DRAM : 00000000-000a0000</div>  <div>DRAM fill: 00000000-000a0000</div>  <div>00000000 00010000 00020000 00030000 00040000 00050000 00060000 </div>  <div>00070000 00080000 00090000 000a0000</div>  <div>DRAM filled</div>  <div>DRAM verify: 00000000-000a0000</div>  <div>00000000 00010000 00020000 00030000 00040000 00050000 00060000 </div>  <div>00070000 00080000 00090000 000a0000</div>  <div>DRAM range verified.</div>  <div>Done.</div>  <div>Testing DRAM : 00100000-01000000</div>  <div>DRAM fill: 00100000-01000000</div>  <div>00100000 00110000 00120000 00130000 00140000 00150000 00160000 </div>  <div>00170000 00180000 00190000
 001a0000 001b0000 001c0000 001d0000 </div>  <div>001e0000 001f0000 00200000 00210000 00220000 00230000 00240000 </div>  <div>00250000 00260000 00270000 00280000 00290000 002a0000 002b0000 </div>  <div>002c0000 002d0000 002e0000 002f0000 00300000 00310000 00320000 </div>  <div>00330000 00340000 00350000 00360000 00370000 00380000 00390000 </div>  <div>003a0000 003b0000 003c0000 003d0000 003e0000 003f0000 00400000 </div>  <div>00410000 00420000 00430000 00440000 00450000 00460000 00470000 </div>  <div>00480000 00490000 004a0000 004b0000 004c0000 004d0000 004e0000 </div>  <div>004f0000 00500000 00510000 00520000 00530000 00540000 00550000 </div>  <div>00560000 00570000 00580000 00590000 005a0000 005b0000 005c0000 </div>  <div>005d0000 005e0000 005f0000 00600000 00610000 00620000 00630000 </div>  <div>00640000 00650000 00660000 00670000 00680000 00690000 006a0000 </div>  <div>006b0000 006c0000 006d0000 006e0000 006f0000 00700000 00710000 </div>  <div>00720000 00730000 00740000
 00750000 00760000 00770000 00780000 </div>  <div>00790000 007a0000 007b0000 007c0000 007d0000 007e0000 007f0000 </div>  <div>00800000 00810000 00820000 00830000 00840000 00850000 00860000 </div>  <div>00870000 00880000 00890000 008a0000 008b0000 008c0000 008d0000 </div>  <div>008e0000 008f0000 00900000 00910000 00920000 00930000 00940000 </div>  <div>00950000 00960000 00970000 00980000 00990000 009a0000 009b0000 </div>  <div>009c0000 009d0000 009e0000 009f0000 00a00000 00a10000 00a20000 </div>  <div>00a30000 00a40000 00a50000 00a60000 00a70000 00a80000 00a90000 </div>  <div>00aa0000 00ab0000 00ac0000 00ad0000 00ae0000 00af0000 00b00000 </div>  <div>00b10000 00b20000 00b30000 00b40000 00b50000 00b60000 00b70000 </div>  <div>00b80000 00b90000 00ba0000 00bb0000 00bc0000 00bd0000 00be0000 </div>  <div>00bf0000 00c00000 00c10000 00c20000 00c30000 00c40000 00c50000 </div>  <div>00c60000 00c70000 00c80000 00c90000 00ca0000 00cb0000 00cc0000 </div>  <div>00cd0000 00ce0000 00cf0000
 00d00000 00d10000 00d20000 00d30000 </div>  <div>00d40000 00d50000 00d60000 00d70000 00d80000 00d90000 00da0000 </div>  <div>00db0000 00dc0000 00dd0000 00de0000 00df0000 00e00000 00e10000 </div>  <div>00e20000 00e30000 00e40000 00e50000 00e60000 00e70000 00e80000 </div>  <div>00e90000 00ea0000 00eb0000 00ec0000 00ed0000 00ee0000 00ef0000 </div>  <div>00f00000 00f10000 00f20000 00f30000 00f40000 00f50000 00f60000 </div>  <div>00f70000 00f80000 00f90000 00fa0000 00fb0000 00fc0000 00fd0000 </div>  <div>00fe0000 00ff0000 01000000</div>  <div>DRAM filled</div>  <div>DRAM verify: 00100000-01000000</div>  <div>00100000 00110000 00120000 00130000 00140000 00150000 00160000 </div>  <div>00170000 00180000 00190000 001a0000 001b0000 001c0000 001d0000 </div>  <div>001e0000 001f0000 00200000 00210000 00220000 00230000 00240000 </div>  <div>00250000 00260000 00270000 00280000 00290000 002a0000 002b0000 </div>  <div>002c0000 002d0000 002e0000 002f0000 00300000 00310000 00320000 </div> 
 <div>00330000 00340000 00350000 00360000 00370000 00380000 00390000 </div>  <div>003a0000 003b0000 003c0000 003d0000 003e0000 003f0000 00400000 </div>  <div>00410000 00420000 00430000 00440000 00450000 00460000 00470000 </div>  <div>00480000 00490000 004a0000 004b0000 004c0000 004d0000 004e0000 </div>  <div>004f0000 00500000 00510000 00520000 00530000 00540000 00550000 </div>  <div>00560000 00570000 00580000 00590000 005a0000 005b0000 005c0000 </div>  <div>005d0000 005e0000 005f0000 00600000 00610000 00620000 00630000 </div>  <div>00640000 00650000 00660000 00670000 00680000 00690000 006a0000 </div>  <div>006b0000 006c0000 006d0000 006e0000 006f0000 00700000 00710000 </div>  <div>00720000 00730000 00740000 00750000 00760000 00770000 00780000 </div>  <div>00790000 007a0000 007b0000 007c0000 007d0000 007e0000 007f0000 </div>  <div>00800000 00810000 00820000 00830000 00840000 00850000 00860000 </div>  <div>00870000 00880000 00890000 008a0000 008b0000 008c0000 008d0000 </div> 
 <div>008e0000 008f0000 00900000 00910000 00920000 00930000 00940000 </div>  <div>00950000 00960000 00970000 00980000 00990000 009a0000 009b0000 </div>  <div>009c0000 009d0000 009e0000 009f0000 00a00000 00a10000 00a20000 </div>  <div>00a30000 00a40000 00a50000 00a60000 00a70000 00a80000 00a90000 </div>  <div>00aa0000 00ab0000 00ac0000 00ad0000 00ae0000 00af0000 00b00000 </div>  <div>00b10000 00b20000 00b30000 00b40000 00b50000 00b60000 00b70000 </div>  <div>00b80000 00b90000 00ba0000 00bb0000 00bc0000 00bd0000 00be0000 </div>  <div>00bf0000 00c00000 00c10000 00c20000 00c30000 00c40000 00c50000 </div>  <div>00c60000 00c70000 00c80000 00c90000 00ca0000 00cb0000 00cc0000 </div>  <div>00cd0000 00ce0000 00cf0000 00d00000 00d10000 00d20000 00d30000 </div>  <div>00d40000 00d50000 00d60000 00d70000 00d80000 00d90000 00da0000 </div>  <div>00db0000 00dc0000 00dd0000 00de0000 00df0000 00e00000 00e10000 </div>  <div>00e20000 00e30000 00e40000 00e50000 00e60000 00e70000 00e80000 </div> 
 <div>00e90000 00ea0000 00eb0000 00ec0000 00ed0000 00ee0000 00ef0000 </div>  <div>00f00000 00f10000 00f20000 00f30000 00f40000 00f50000 00f60000 </div>  <div>00f70000 00f80000 00f90000 00fa0000 00fb0000 00fc0000 00fd0000 </div>  <div>00fe0000 00ff0000 01000000</div>  <div>DRAM range verified.</div>  <div>Done.</div>  <div>DUMP NORTH</div>  <div>00:06 11 05 06 06 00 10 22 00 00 00 06 00 00 00 00 </div>  <div>10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </div>  <div>20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </div>  <div>30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 </div>  <div>40:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </div>  <div>50:fd db c8 fe 02 00 20 20 e0 00 10 20 20 20 20 20 </div>  <div>60:3f 2a 00 30 e6 00 00 00 41 7c 43 0f 08 21 00 00 </div>  <div>70:00 00 00 00 00 00 00 00 01 f0 00 02 00 00 00 00 </div>  <div>80:00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </div>  <div>90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </div> 
 <div>a0:02 c0 20 00 01 02 00 1f 00 00 00 00 00 02 00 00 </div>  <div>b0:80 63 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </div>  <div>c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 </div>  <div>d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </div>  <div>e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </div>  <div>f0:00 00 00 00 00 00 04 00 32 42 00 00 00 00 00 00 </div>  <div>*************End of AUTO.C************</div>  <div>Copying LinuxBIOS to RAM.</div>  <div>Jumping to LinuxBIOS.</div>  <div>&nbsp;</div>  <div>&nbsp;</div>  <div>&nbsp;</div>  <div>&nbsp;</div>  <div></FONT><B><I>sanjay tiwary &lt;stiwary20 at yahoo.com&gt;</I></B> wrote:</div>  <BLOCKQUOTE class=replbq style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #1010ff 2px solid">  <DIV>Hi Stepen,</DIV>  <DIV>&nbsp;</DIV>  <DIV>I would like to thank you for the movitation you given to me. </DIV>  <DIV>&nbsp;</DIV>  <DIV>A. For the conveniance of clarity, i am again recapitulate the facts/figures
 about my board.</DIV>  <DIV>1. Northbridge: VT8605&nbsp; almost similar to VT8601 or VT8603</DIV>  <DIV>2.Southbridge: VT 82C686 which has integrated super I/O controller</DIV>  <DIV>3. CPU: 300Mhz Celeron Processor</DIV>  <DIV>4. Memory: 512 MB SDRAM</DIV>  <DIV>---------------------------------------------------------</DIV>  <DIV>if any other info, pls let me know</DIV>  <DIV>&nbsp;</DIV>  <DIV>B. </DIV>  <DIV>--------</DIV>  <DIV>&nbsp;&nbsp;&nbsp; 1. In this mail, i am sending you data as much as possible for you </DIV>  <DIV>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; comments/suggestion&nbsp;&nbsp; for improvment the porting process.</DIV>  <DIV>&nbsp;&nbsp;&nbsp; 2. Now i would like to ask couple of question. Since raminit does not complain any failure and ramcheck also passes ramtest.Next, code in crt0.S is able to copy the code from ROM to RAM. I am also able to read the code and print them in the serial output.So my question is, if i am able to read/write
 correct data to/from RAM, why is there doubt on incorrect DRAM initialisation?</DIV>  <DIV>If i am not able to jump to a designated place (0x4000) in RAM simply due incorrect DRAM initialisation, then what are those things which i am not taking care of during DRAM initialization? Can u pls hightlight those area in RAMINIT so that i can re-walk those area.</DIV>  <DIV>&nbsp;3. if really, the DRAM initialization is correct, then what are the factors that may stop/misdirect the control to jump to a correct location in RAM.</DIV>  <DIV>I tried to print the contents from the RAM which is copied from the ROM to RAM in the start of crt0.S, they are byte by byte same as is for c_start.o</DIV>  <DIV>&nbsp;</DIV>  <DIV>4. Are there any role of the register like AX,BX, CX and DX &amp; other index register while control is try to jump at ram location. For reference, i am also printed the contents of the register before jumping i.e jmp *%edi</DIV>  <DIV>5. In my config, i have set
 DCAHE_RAM =0</DIV>  <DIV>&nbsp;</DIV>  <DIV>6. i have&nbsp;compared the register dump for linuxbios and legacy bios.They are not exactly same. Should i try to cpmpare the entire dump&nbsp;or the register dump of device 00.0 only?&nbsp;</DIV>  <DIV>&nbsp;</DIV>  <DIV>&nbsp;</DIV>  <DIV>&nbsp;</DIV>  <DIV>B. I would also like to give you the register dump( for the Device&nbsp;00.0)&nbsp;of legacy BIOS</DIV>  <DIV>&nbsp;&nbsp;&nbsp;&nbsp; The ouput given below has been taken by lspci</DIV>  <DIV>&nbsp;&nbsp;&nbsp;&nbsp; --------------------------------------------------------------------</DIV>  <DIV>00: 06 11 05 06 06 00 10 22 00 00 00 06 00 00 00 00</DIV>  <DIV>10: 08 00 00 ec 00 00 00 00 00 00 00 00 00 00 00 00</DIV>  <DIV>20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</DIV>  <DIV>30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00</DIV>  <DIV>40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</DIV>  <DIV>50: fd db c8 fe 02 00 20 20 e0 00 10 20 20 20 20 20</DIV> 
 <DIV>60: 3f 2a 00 a0 e6 00 00 00 41 7c 43 0f 08 21 00 00</DIV>  <DIV>70: c4 80 cc 0c 0e a1 d2 00 01 b4 09 00 00 00 00 00</DIV>  <DIV>80: 0f 40 00 00 c0 00 00 00 02 00 00 00 00 00 00 00</DIV>  <DIV>90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</DIV>  <DIV>a0: 02 c0 20 00 01 02 00 1f 00 00 00 00 27 12 00 00</DIV>  <DIV>b0: c0 ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00</DIV>  <DIV>c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00</DIV>  <DIV>d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</DIV>  <DIV>e0: 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</DIV>  <DIV>f0: 00 00 00 00 00 00 04 00 32 42 00 b0 00 00 00 00</DIV>  <DIV>&nbsp;</DIV>  <DIV>&nbsp;</DIV>  <DIV>&nbsp;</DIV>  <DIV>C. linuxbios log</DIV>  <DIV>------------------------------------------------------------------------</DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">LinuxBIOS-2.0.0.fallback Fri Mar 23 18:50:48 IST
 2007 starting...<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">01 is the comm register<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">SMBus controller enabled<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">vt8605<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>init starting<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00000000 is the north 1106 0605<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">0120NOP<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">PRECHARGE<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DUMMY READS<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">CBR<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier&#13;&#10; New">MRS<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">NORMAL<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText
 style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">set ref. rate<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">enable multi-page open<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Register Dump (from LinuxBIOS) for Device 00.0<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">--------------------------------------------------<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00:06 11 05 06 06 00 10 22 00 00 00 06 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText
 style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">40:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">50:ac 08 80 03 00 00 20 20 e0 00 20
 20 20 20 20 20 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">60:3f 00 00 30 e6 00 00 00 41 7c 43 01 08 21 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">70:00 00 00 00 00 00 00 00 01 f0 00 02 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">80:00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family:
 'MS Mincho'"><FONT face="Courier New">a0:02 c0 20 00 01 02 00 1f 00 00 00 00 00 02 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">b0:80 63 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">f0:00 00 00 00 00 00 04 00 00 00 00 00 00 00 00 00 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">&nbsp;<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">---Register Dump End here--------------------------<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">---RAM CHECKING (from 0-640K &amp; 1M-16M)-------------<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Testing DRAM :
 00000000-000a0000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM fill: 00000000-000a0000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00000000 00010000 00020000 00030000<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>00040000 00050000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00060000 00070000 00080000 00090000<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>000a0000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM filled<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM verify: 00000000-000a0000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00000000 00010000 00020000 00030000<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>00040000 00050000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00060000 00070000 00080000 00090000<SPAN style="mso-spacerun: yes">&nbsp; </SPAN>000a0000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM range verified.<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier
 New">Done.<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">&nbsp;<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Testing DRAM : 00100000-01000000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM fill: 00100000-01000000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00100000 00110000 00120000 00130000 00140000 00150000 00160000 00170000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00180000 00190000 001a0000
 001b0000 001c0000 001d0000 001e0000 001f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00200000 00210000 00220000 00230000 00240000 00250000 00260000 00270000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00280000 00290000 002a0000 002b0000 002c0000 002d0000 002e0000 002f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00300000 00310000 00320000 00330000 00340000 00350000 00360000 00370000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00380000 00390000 003a0000 003b0000 003c0000 003d0000 003e0000 003f0000
 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00400000 00410000 00420000 00430000 00440000 00450000 00460000 00470000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00480000 00490000 004a0000 004b0000 004c0000 004d0000 004e0000 004f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00500000 00510000 00520000 00530000 00540000 00550000 00560000 00570000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00580000 00590000 005a0000 005b0000 005c0000 005d0000 005e0000 005f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00600000 00610000 00620000 00630000 00640000 00650000 00660000 00670000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00680000 00690000 006a0000 006b0000 006c0000 006d0000 006e0000 006f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00700000 00710000 00720000 00730000 00740000 00750000 00760000 00770000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00780000 00790000 007a0000 007b0000 007c0000 007d0000 007e0000 007f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00800000 00810000 00820000 00830000 00840000 00850000 00860000 00870000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00880000 00890000 008a0000 008b0000 008c0000 008d0000 008e0000 008f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00900000 00910000 00920000 00930000 00940000 00950000 00960000 00970000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00980000 00990000 009a0000 009b0000 009c0000 009d0000 009e0000 009f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT
 face="Courier New">00a00000 00a10000 00a20000 00a30000 00a40000 00a50000 00a60000 00a70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00a80000 00a90000 00aa0000 00ab0000 00ac0000 00ad0000 00ae0000 00af0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00b00000 00b10000 00b20000 00b30000 00b40000 00b50000 00b60000 00b70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00b80000 00b90000 00ba0000 00bb0000 00bc0000 00bd0000 00be0000 00bf0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00c00000 00c10000 00c20000 00c30000
 00c40000 00c50000 00c60000 00c70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00c80000 00c90000 00ca0000 00cb0000 00cc0000 00cd0000 00ce0000 00cf0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00d00000 00d10000 00d20000 00d30000 00d40000 00d50000 00d60000 00d70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00d80000 00d90000 00da0000 00db0000 00dc0000 00dd0000 00de0000 00df0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00e00000 00e10000 00e20000 00e30000 00e40000 00e50000 00e60000 00e70000
 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00e80000 00e90000 00ea0000 00eb0000 00ec0000 00ed0000 00ee0000 00ef0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00f00000 00f10000 00f20000 00f30000 00f40000 00f50000 00f60000 00f70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00f80000 00f90000 00fa0000 00fb0000 00fc0000 00fd0000 00fe0000 00ff0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">01000000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM filled<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM verify: 00100000-01000000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00100000 00110000 00120000 00130000 00140000 00150000 00160000 00170000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00180000 00190000 001a0000 001b0000 001c0000 001d0000 001e0000 001f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00200000 00210000 00220000 00230000 00240000 00250000 00260000 00270000
 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00280000 00290000 002a0000 002b0000 002c0000 002d0000 002e0000 002f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00300000 00310000 00320000 00330000 00340000 00350000 00360000 00370000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00380000 00390000 003a0000 003b0000 003c0000 003d0000 003e0000 003f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS   Mincho'"><FONT face="Courier New">00400000 00410000 00420000 00430000 00440000 00450000 00460000 00470000 <o:p></o:p></FONT></SPAN></DIV>  <DIV
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00480000 00490000 004a0000 004b0000 004c0000 004d0000 004e0000 004f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00500000 00510000 00520000 00530000 00540000 00550000 00560000 00570000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00580000 00590000 005a0000 005b0000 005c0000 005d0000 005e0000 005f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00600000 00610000 00620000 00630000 00640000 00650000 00660000 00670000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00680000 00690000 006a0000 006b0000 006c0000 006d0000 006e0000 006f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00700000 00710000 00720000 00730000 00740000 00750000 00760000 00770000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00780000 00790000 007a0000 007b0000 007c0000 007d0000 007e0000 007f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00800000 00810000 00820000 00830000 00840000 00850000 00860000 00870000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT
 face="Courier New">00880000 00890000 008a0000 008b0000 008c0000 008d0000 008e0000 008f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00900000 00910000 00920000 00930000 00940000 00950000 00960000 00970000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00980000 00990000 009a0000 009b0000 009c0000 009d0000 009e0000 009f0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00a00000 00a10000 00a20000 00a30000 00a40000 00a50000 00a60000 00a70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00a80000 00a90000 00aa0000 00ab0000
 00ac0000 00ad0000 00ae0000 00af0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00b00000 00b10000 00b20000 00b30000 00b40000 00b50000 00b60000 00b70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00b80000 00b90000 00ba0000 00bb0000 00bc0000 00bd0000 00be0000 00bf0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00c00000 00c10000 00c20000 00c30000 00c40000 00c50000 00c60000 00c70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00c80000 00c90000 00ca0000 00cb0000 00cc0000 00cd0000 00ce0000 00cf0000
 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00d00000 00d10000 00d20000 00d30000 00d40000 00d50000 00d60000 00d70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00d80000 00d90000 00da0000 00db0000 00dc0000 00dd0000 00de0000 00df0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00e00000 00e10000 00e20000 00e30000 00e40000 00e50000 00e60000 00e70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00e80000 00e90000 00ea0000 00eb0000 00ec0000 00ed0000 00ee0000 00ef0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00f00000 00f10000 00f20000 00f30000 00f40000 00f50000 00f60000 00f70000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00f80000 00f90000 00fa0000 00fb0000 00fc0000 00fd0000 00fe0000 00ff0000 <o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">01000000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">DRAM range verified.<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Done.<o:p></o:p></FONT></SPAN></DIV>  <DIV
 class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">-------------END OF AUTO.C----------------------------------<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">&nbsp;<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">&nbsp;<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">vt8605 done<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier&#13;&#10; New">&nbsp;<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN
 style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">-----WE are in crt0.S-------<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Copying LinuxBIOS to RAM.<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">--regsister dump when copying is done-----<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing eax=00003333<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing ebx=ffffd14a<SPAN style="mso-tab-count: 1">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </SPAN><o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText
 style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing ecx=00000000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing edx=ffff03f8<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing esi=ffff7094<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing edi=00004000<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Printing cs=00000008<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS
 Mincho'"><FONT face="Courier New">Printing ds=00000010<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">End of Register dump</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New"><o:p></o:p></FONT></SPAN>&nbsp;</DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Memory dump (from RAM 0x4000 upto 7094byte)</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New"><o:p>[I have intentionaly put some ee at the start of c_start.s for conveniance of identification. I have also deleted some of the last byte for saving space]</o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in
 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">-------------------------------------------<o:p></o:p></FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">ee2e0f011538410000ea104000001000b8180000008ed88ec08ed08ee08ee8b013</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">e680fc8d3d00600100b90080010029f9c1e90231c0f3ab8d3d2c340100b9e85401</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">0029f97407c1e90231c0f3abbc008001006a006a005589e58d3d10dc00008d1da1</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS   Mincho'"><FONT face="Courier
 New">400000b8000010006689d889da66ba008e89470089570483c30683c70881ffb0dc</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">000075e30f011d08dc0000b0fee68089ece8a21e0000b0eee680f4ebf96a006a00</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">eb726a006a01eb6c6a006a02eb666a006a03eb606a006a04eb5a6a006a05eb546a</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">006a06eb4e6a006a07eb486a08eb4490906a006a09eb3c6a0aeb3890906a0beb32</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">90906a0ceb2c90906a0deb2690906a0eeb2090906a006a0feb186a006a10eb126a</FONT></SPAN></DIV>  <DIV class=MsoPlainText
 style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">11eb0e90906a006a12eb066a006a13eb005756558d6c2420555352515054e8b51e</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00005858595a5b5d5d5e5f83c408cf2700e0db000090905589e56a036a0668f803</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">0000e8bf33000083c40cc9c35589e50fb645085068f8030000e838340000585ac9</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">c35589e568f8030000e8643400000fb6c0c9c35589e568f8030000e840340000c9</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier&#13;&#10;
 New">c39090905589e556538b750868d4c000006a07e8bc0700006a6c56e8b305000083</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">c8800fb6c0506a6c56e8330600006a7f6a4156e82906000083c4286a4056e88f05</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">00000fb6c0506a4056e8120600006a4256e87b05000083c8f00fb6c0506a4256e8</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">fb05000083c4286a4a56e86105000083c8080fb6c0506a4a56e8e10500006a4f56</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">e84a05000083c8080fb6c0506a4f56e8ca05000083c4286a036a5856e8bd050000</FONT></SPAN></DIV>  <DIV class=MsoPlainText
 style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">83c40c85f6741a6a5156e81f05000083c8180fb6c0506a5156e89f05000083c414</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">6a5056e80505000088c30fb6c05068e4c000006a07e8f406000081e3f700000053</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">6803c100006a07e8e106000083c420536a5056e8630500006a4c56e8cc04000088</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">c389d883e00f50681cc100006a07e8b906000081e3f000000083cb0483c42053683</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier&#13;&#10;
 New">6c100006a07e8a0060000536a4c56e8250500006a046a4656e81b05000083c4246a</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">036a4756e80e05000068980000006a6e56e8010500006a546a4056e8f704000083c</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">4246a00e8c24d00005668ecdc0000684fc100006a06e84d06000083c41485f6742a</FONT></SPAN></DIV>  <DIV class=MsoPlainText style="MARGIN: 0in 0in 0pt"><SPAN style="mso-fareast-font-family: 'MS Mincho'"><FONT face="Courier New">Jumping to LinuxBIOS.<o:p></o:p></FONT></SPAN></DIV>  <DIV>  <DIV><FONT color=#ff007f size=4>[After that, it simply hangs]<BR></FONT>---------------------------------------------------------------------------</DIV>  <DIV>if any other info is required to get out this problem, pls let me know.</DIV>  <DIV>&nbsp;</DIV> 
 <DIV>&nbsp;</DIV>  <DIV>Regards,</DIV>  <DIV>Sanjay<BR><B><I>Stefan Reinauer &lt;stepan at coresystems.de&gt;</I></B> wrote:</DIV></DIV>  <BLOCKQUOTE class=replbq style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #1010ff 2px solid">* sanjay tiwary <STIWARY20 at YAHOO.COM>[070323 14:20]:<BR>&gt; Hi<BR>&gt; <BR>&gt; I am not able to go beyound "Jumping to LinuxBIOS".Initially i thought<BR>&gt; it is a DRAM problem. But ram test passes. I am also able to<BR>&gt; read/write from/to RAM.So i guess my jump is not working. But i am not<BR>&gt; able to find out.<BR>&gt; So, Can anybody see the register dump which is taken before the jmp<BR>&gt; *%edi.<BR>&gt; <BR>&gt; LinuxBIOS-"2.0.0"".fallback" "Fri Mar 23 18:28:27 IST 2007" starting...<BR>&gt; Copying LinuxBIOS to RAM.<BR>&gt; Printing eax=00003333<BR>&gt; Printing ebx=ffffd14a<BR>&gt; Printing ecx=00000000<BR>&gt; Printing edx=ffff03f8<BR>&gt; Printing esi=ffff7092<BR>&gt; Printing edi=00004000<BR>&gt; Printing
 cs=00000008<BR>&gt; Printing ds=00000010<BR>&gt; End of Register dump<BR>&gt; --------------------------------------------<BR><BR>Sorry, this log contains no information useful for debugging the<BR>problem. <BR><BR>From the log it seems no memory init is done at all? <BR><BR>Is this still the vt8601 northbridge board?<BR>what southbridge? In one of your previous mails you wrote 82C686, <BR>in another one VT8231?<BR><BR>You don't post any code that would allow people to help you debug the<BR>problem.<BR><BR>The memory test in auto.c is not qualifying. If that jmp does not work,<BR>your memory does not work. It really is that simple. This can be<BR>frustrating, don't despair. <BR><BR>Have you compared northbridge register dumps between linuxbios and the<BR>legacy bios?<BR><BR><BR>-- <BR>coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.<BR>Tel.: +49 761 7668825 ??? Fax: +49 761 7664613<BR>Email: info at coresystems.de ??? http://www.coresystems.de/<BR><BR>--
 <BR>linuxbios mailing list<BR>linuxbios at linuxbios.org<BR>http://www.linuxbios.org/mailman/listinfo/linuxbios</BLOCKQUOTE><BR>  <div>  <HR SIZE=1>  It's here! Your new message!<BR>Get <A href="http://us.rd.yahoo.com/evt=49938/*http://tools.search.yahoo.com/toolbar/features/mail/">new email alerts</A> with the free <A href="http://us.rd.yahoo.com/evt=49938/*http://tools.search.yahoo.com/toolbar/features/mail/">Yahoo! Toolbar.</A>-- <BR>linuxbios mailing list<BR>linuxbios at linuxbios.org<BR>http://www.linuxbios.org/mailman/listinfo/linuxbios</BLOCKQUOTE><BR><p>&#32;

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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.204.1355071074.16123.coreboot@coreboot.org>

The Via VT8235 in linuxbios has code to set up serial output. But the
VT8235M datasheet, which is the part I have, doesn't mention anything
about super io functions. And there's definately no other super io chip.
I'm so lost right now...

I've tried setting up the ite super io at 0x4e, and still no dice.
Tomorrow I'm going to play with VGA roms, I think.

Thanks,
Corey



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.241.1355071080.16123.coreboot@coreboot.org>

nVIDIA MCP55 southbridge. However, the Super I/O chip on the S2927 is a
SMSC SCH5017 and not the Winbond W83627HF found on the S2912. The S2915
uses the nVIDIA NFP3600 + NPF3050 as the southbridge and the SMSC 5307
Super I/O controller.

Would Yinghai's patch support either of these two boards?

Thanks,
Arvind






From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.244.1355071083.16123.coreboot@coreboot.org>

Have you done any other config changes?

Is it possible for you to send me (gzipped?) the version of videobios
you used (I suspect, I missed something). 

BTW, do you have any card in the HTX slot installed?

Alexei I. Adamovich



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.258.1355071091.16123.coreboot@coreboot.org>

motherboard.
Does it mean that every hope is lost, or would it be possible to use an
external BIOS to do the development, or another simila solution ?

Thanks,
S=E9bastien.



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.260.1355071091.16123.coreboot@coreboot.org>

Reworking TSOP chips without the right tools is no fun, but it can be
done even with just a very warm soldering iron, and if the chip
doesn't have to be re-used it's even easier. (Just cut off all the
pins and then use any soldering iron and a soldering wick to clean up
all the pins and the solder that held them to the mainboard.)

There are TSOP sockets that could be installed where the chip used to
be, but I haven't found them available in smaller quantities than
what would cost a few $100. (Maybe segor.de have some though.)


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.302.1355071099.16123.coreboot@coreboot.org>

h
the RD1-PL is the version of the bios saviour that I need for this
particular motherboard, however I am having a hard time find a place to
buy this specific model.  I was wondering if anyone knows where I can
purchase this model or if there is another model that will work equally a=
s
well.  Also, if anyone can recommend a place to buy PLCC chips or any
other solutions I would greatly appreciate it.

William




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.344.1355071111.16123.coreboot@coreboot.org>

0        -- Resource Indicator -- RO. tied to 1 to indicate I/O space

Should it be
pmbase_value = pci_read_long(LPCBridge, 0x40) & 0xff80;
?

Is shifting necessary, too (see attached file)?

On my machine, output from my variant:
Extracted address from PMBASE: 0x00000800
Offset to SMI_EN  (PMBASE + 0x30): 0x00000830
Offset to SMI_STS (PMBASE + 0x34): 0x00000834
Value in SMI_EN:  0xffffffff
Value in SMI_STS: 0xffffffff

Output from Stefans variant:
the same as from above

Output from my variant with shift:
Extracted address from PMBASE: 0x00000010
Offset to SMI_EN  (PMBASE + 0x30): 0x00000040
Offset to SMI_STS (PMBASE + 0x34): 0x00000044
Value in SMI_EN:  0x00000801
Value in SMI_STS: 0x00000010

Output from Stefans variant with shift:
 the same as from above
 
Which of these four variants is correct?

Regards

Andon


       
---------------------------------
Building a website is a piece of cake. 
Yahoo! Small Business gives you all the tools to get online.
--0-465367909-1179837539=:83441
Content-Type: text/html; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

<br>&gt;&gt; Hello,<br>&gt;&gt;     pmbase_value = pci_read_long(LPCBridge, 0x40);<br>&gt;<br>&gt;This neads to read <br>&gt;<br>      &gt;pmbase_value = pci_read_long(LPCBridge, 0x40) &amp; 0xfffffffe ;<br>&gt;<br>&gt;I have not checked the data sheets but I would bet the lowest bit is<br>&gt;enable.<br><br>From datasheet ICH3M, according to PMBASE:<br>31:16 --&nbsp; reserved<br>15:7&nbsp;&nbsp; --&nbsp; Base address <br>6:1&nbsp;&nbsp;&nbsp;&nbsp; -- reserved<br>0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -- Resource Indicator -- RO. tied to 1 to indicate I/O space<br><br>Should it be<br>pmbase_value = pci_read_long(LPCBridge, 0x40) &amp; 0xff80;<br>?<br><br>Is shifting necessary, too (see attached file)?<br><br>On my machine, output from my variant:<br>Extracted address from PMBASE: 0x00000800<br>Offset to SMI_EN&nbsp; (PMBASE + 0x30): 0x00000830<br>Offset to SMI_STS (PMBASE + 0x34): 0x00000834<br>Value in SMI_EN:&nbsp; 0xffffffff<br>Value in SMI_STS:
 0xffffffff<br><br>Output from Stefans variant:<br>the same as from above<br><br>Output from my variant with shift:<br>Extracted address from PMBASE: 0x00000010<br>Offset to SMI_EN&nbsp; (PMBASE + 0x30): 0x00000040<br>Offset to SMI_STS (PMBASE + 0x34): 0x00000044<br>Value in SMI_EN:&nbsp; 0x00000801<br>Value in SMI_STS: 0x00000010<br><br>Output from Stefans variant with shift:<br> the same as from above<br> <br>Which of these four variants is correct?<br><br>Regards<br><br>Andon<br><br><p>&#32;
      <hr size=1>Building a website is a piece of cake. <br>Yahoo! Small Business gives you <a href="http://us.rd.yahoo.com/evt=48251/*http://smallbusiness.yahoo.com/webhosting/?p=PASSPORTPLUS">all the tools to get online.</a>
--0-465367909-1179837539=:83441--
--0-628321999-1179837539=:83441
Content-Type: text/x-csrc; name="get_content_of_pmbase_libpci.c"
Content-Description: 2332724126-get_content_of_pmbase_libpci.c
Content-Disposition: inline; filename="get_content_of_pmbase_libpci.c"

#include <stdio.h>
#include <pci/pci.h>  

int main(void) {

	struct pci_access *pacc;
	struct pci_dev *LPCBridge;
	u32 pmbase_value, smi_en_offset, smi_sts_offset, smi_en_value, smi_sts_value;

	pacc = pci_alloc();
	pci_init(pacc);
	
	LPCBridge = pci_get_dev(pacc, 0, 0, 0x1f, 0);
	
	//pmbase_value = pci_read_long(LPCBridge, 0x40) & 0xff80; /* my variant */
	//pmbase_value = pci_read_long(LPCBridge, 0x40) & 0xfffffffe; /* Stefans variant */
	//pmbase_value = (pci_read_long(LPCBridge, 0x40) & 0xff80) >> 7; /* my variant with shift */
        pmbase_value = (pci_read_long(LPCBridge, 0x40) & 0xfffffffe) >> 7; /* Stefans variant with shift */
	printf("Extracted address from PMBASE: 0x%08x\n", pmbase_value);
	
	smi_en_offset  = pmbase_value + 0x30;
	smi_sts_offset = pmbase_value + 0x34;
	printf("Offset to SMI_EN  (PMBASE + 0x30): 0x%08x\n", smi_en_offset);
	printf("Offset to SMI_STS (PMBASE + 0x34): 0x%08x\n", smi_sts_offset);

	smi_en_value =   pci_read_long(LPCBridge, smi_en_offset);
	smi_sts_value =  pci_read_long(LPCBridge, smi_sts_offset);
	printf("Value in SMI_EN:  0x%08x\n", smi_en_value);
	printf("Value in SMI_STS: 0x%08x\n", smi_sts_value);
	

	return 0;
}







--0-628321999-1179837539=:83441--



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.391.1355071120.16123.coreboot@coreboot.org>

will always be 24 bytes, and the LinuxBIOS Table header will never be
extended in the future (or is this just a bug that makes "lbtdump"
unable to handle forward/backward compatability)?

The file "src/include/boot/linuxbios_tables.h" defines 3 types of memory ranges:

#define LB_MEM_RAM       1	/* Memory anyone can use */
#define LB_MEM_RESERVED  2	/* Don't use this memory region */
#define LB_MEM_TABLE     16	/* Ram configuration tables are kept in */

The file "util/lbtdump/lbtdump.c" doesn't agree:

		switch(rec->map[i].type) {
		case 1: mem_type = "ram"; break;
		case 3: mem_type = "acpi"; break;
		case 4: mem_type = "nvs"; break;
		default:
		case 2: mem_type = "reserved"; break;
		}

Can I assume that the defines in "linuxbios_tables.h" are out-of-date,
and that the memory type field is the same as specified by version 2
of the ACPI specification (but perhaps not version 3, as that defines
a new "5 = faulty RAM" type)? If "linuxbios_tables.h" is out-of-date,
is "16 = RAM configuration tables are stored in" still possible on
older versions of LinuxBIOS (and how would I detect which version of
LinuxBIOS is present, considering there's no version number in the
LinuxBIOS Table header)?

What is the LB_TAG_HWRPB structure. Is it something to do with a
"Hardware Restart Parameter Block", and what does it contain? For e.g.
would a value of zero indicate that the computer was shutdown
correctly before boot, and a non-zero value indicate that the computer
crashed or had hardware problems?

Would I also be correct to assume that a payload doesn't need to care
about any of the "cmos_entries" and "cmos_enums", unless a BIOS
setup/configuration utility is being built into the payload?
Alternatively, could/would a payload search for strings to find CMOS
values (e.g. search for the cmos_entry with the name string
"power_on_after_fail" to see if additional hardware testing can be
skipped, search for "baud_rate" to determine the serial port
configuration, etc)?

> It is of course not unique. It is the index of the vendor name within
> the strings array of struct lb_mainboard. Since we're not trying to
> close things down, we don't have to work with magic numbers. So nothing
> needs to stay unique.

Of course - it's similar to the way SMI/DMI does strings, yet are the
strings themselves guaranteed to be unique, or is it possible for one
manufacturer to use an identifying string in the future that another
(possibly out of business) manufacturer had used in the past?

Motherboard manufacturer identification is one of the things that
(IMHO) should be unique. The motherboard part number string should
also be unique for that manufacturer ID. Otherwise it'd be difficult
for payloads/utilities/OSs to use these IDs to avoid any hardware
problems in specific motherboards.

> > > > I assume there may also be ACPI, MP specification, PIRQ routing and/or
> > > > (possibly) SMI/DMI tables, and I'm guessing that (if present) these
> > > > tables can be searched for using the same methods as described in
> > > > their corresponding specifications.
> > >
> > > They're not used by payloads (except the Linux kernel)
> >
> >  Surely LinuxBIOS isn't intended as a "Linux only" BIOS though....
>
> Of course not. ACPI is not really useful for payloads though, unless the
> payload wants to carry a full blown ACPI interpreter. Which rules out
> basically anything but an OS.

I can think of a variety of uses, ranging from utilities that do
nothing more than display hardware information, to diagnostics, to
benchmarking, to hyper-visors, to full OSs...

> > > > - are AP CPUs started (or waiting for a SIPI sequence)?
> > >
> > > yes, hardware is completely up when linuxbios is done.
> >
> >  I tried it on a dual CPU Bochs emulation (second CPU was left in "wait
> >  for SIPI" state) - I'm guessing I need to enable multi-CPU support
> >  via. some compile time option for the "emulation/qemu-i386" target?
>
> Yes, the emulation/qemu-i386 is per default not supporting SMP.

I'm becoming skeptical here. I can't find anything in LinuxBIOS source
code that starts AP CPUs, but in "src/arch/i386/smp/mpspec.c" I did
find:

/* If we assume a symmetric processor configuration we can
 * get all of the information we need to write the processor
 * entry from the bootstrap processor.
 * Plus I don't think linux really even cares.
 * Having the proper apicid's in the table so the non-bootstrap
 *  processors can be woken up should be enough.
 */

It might be possible that no AP CPUs are ever started, and are instead
left in a "wait for SIPI" default state, assumed to be identical to
the BSP, and even assumed to be working (no BIST checks).

AFAIK the normal approach is to send a broadcast INIT-SIPI sequence
and wait to see which AP CPUs start (if any), and then either record
details somewhere or have each AP CPU add itself to the MP
specification and ACPI tables, then setup their MTTRs, thermal
monitoring, HT links, SMBASE, etc before sending the APs back to the
"wait for SIPI" state - i.e. in theory it should be mostly
"configuration-less".

In any case, I'm guessing I need to get LinuxBIOS to generate MP
specification and ACPI tables to suit the number of CPUs being
emulated by Bochs/Qemu. Is this as simple as adding something like
"option CPUs = ?" to the "targets/emulation/qemu-i386/Config.lb" file?
I'm guessing it's more involved than this, as I couldn't find an
example in the "Config.lb" of other targets.

> >  Either:
> >  a) PCI buses and bridges aren't guaranteed to be enumerated, or
> >  b) PCI buses and bridges are guaranteed to be enumerated but PCI
> >  devices aren't guaranteed to be assigned resources, or
> >  c) PCI buses and bridges are guaranteed to be enumerated and PCI
> >  devices are guaranteed to have resources assigned (including ROMs)
> >  d) PCI buses and bridges are guaranteed to be enumerated and PCI
> >  devices are guaranteed to have resources assigned (except ROMs)
>
> >  "They have their resources." would mean either c) or d), where each
> >  device may or may not be in a power saving state (if supported by the
> >  device), and may or may not be still configured to use MSI (if
> >  supported by the device)....
>
> yes, either c or d. You choose.

You mean all LinuxBIOS developers are willing to make sure all PCI
device ROMs either have physical addresses assigned or don't have
physical addresses assigned based on my advice? Perhaps I've
misunderstood... :-)

> > > Not at the moment. But in General this is easy. If no VGA class PCI
> > > device is there, the machine is 99.99% headless.
> >
> >  And if a VGA class PCI device is present, you've got no idea if no
> >  monitor is attached...
>
> Obviously not. and if the device does not do EDD you have no reliable
> way of finding out either.

There's a simple and easy way to find out if a monitor is attached or
not, and it doesn't involve messing about with EDD - simply give the
end-user the option of setting (or not setting) a value in the CMOS.

My (limited) reverse engineering has already shown that there's CMOS
entries for a serial port (possibly intended for setting up a serial
cable to communicate with a terminal emulator?).

> > > > - can anything be assumed about AGP and the first video card (if the
> > > > computer isn't headless)?
> > >
> > > What would you like to assume?
> >
> >  Video card set to default "80 * 25" text mode accessible at 0xB8000;
> >  or some video mode set with display memory directly accessible at some
> >  physical address (where video mode details and physical address
> >  included in LinuxBIOS Table); or AGP aperture configured, AGP transfer
> >  speed set, MTRRs set to "write combining" and some video mode set with
> >  display memory directly accessible at some physical address; or
> >  anything else, as long as a payload writer knows how much or how
> >  little they can assume about it (and hopefully doesn't need to
> >  implement a wide range of video drivers just to do a "Hello World"
> >  that works on all video cards)... ;)
>
> Ok, the video hardware is in the state that the VGA Option ROM sets it
> to. Since that is closed source, we can not guarantee anything,
> obviously. A rule of thumb tells you that 80x25 at B8000 is a reasonable
> assumption. The AGP setup is chipset specific, so it might vary from
> chipset to chipset.

Cool :-)

Next question would be how to get that to work under Qemu and/or
Bochs. I realise this may not be easy (I've had problems with Bochs
before, as the VGA ROM seems to behave like an ISA card ROM and
doesn't behave like a PCI card ROM - i.e. the ROM ignores settings in
PCI configuration space)...


Thanks,

Brendan



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.402.1355071122.16123.coreboot@coreboot.org>

used. For e.g. if my code knows it can't drop back to real mode and
use legacy BIOS interrupts, then it can skip it or use an alternative
(in this specific case, I only used legacy BIOS interrupts to allow
the user to select and change the video mode).

> > Consider the multi-boot specification. OS developers can write code
> > that complies with the multi-boot specification without regard to any
> > bootloader, and bootloader writers can write code with that complies
> > with the multi-boot specification without caring about any OS. Despite
> > this, all OSs and all boot loaders that comply with the multi-boot
> > specification will work together without problems. The same applies to
> > EFI and OpenFirmware.
>
> I think some of this is actually more in the domain of EFI and Open
> Firmware than in LinuxBIOS, which is more a low level firmware. So we
> should work on getting EFI / OFW easily usable as an interface for everyone
> instead of defining a third interface. to the OS and user. Our interface
> is to OFW / EFI though (plus other options of course)

Put more generally, all interfaces between components developed by
different parties should be adequately documented. This includes the
interface between hardware and LinuxBIOS, the interface between
LinuxBIOS and it's payloads, the interface/s between payloads and
anything that use the payload/s, the interface between boot loaders
and OSs, the interface between an OS and software designed for that
OS, etc.

BTW I'm more interested in "boot from ROM" systems, where the "OS" is
stored in ROM, and doesn't require or rely on disk drives or
networking (but may use disk drives and/or networking if present,
after the system is running). GRUB, Openfirmware and EFI payloads
would consume too much of the limited space in ROM.


Cheers,

Brendan



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.536.1355071137.16123.coreboot@coreboot.org>

we even have the serial console.

Stefan

-- 
coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ??? Fax: +49 761 7664613
Email: info at coresystems.de  ??? http://www.coresystems.de/



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.542.1355071141.16123.coreboot@coreboot.org>

to work. More below. USB and PS/2 are quite different code paths in
the kernel, until one of them is working there is surely some generic
problem, quite possibly in LB.


> I changed some code, it still doesn't work. Maybe I miss something.
> In Linux, kudzu can do some hardware detect, but don't work in this
> case.

Can you get more details from kudzu about why it fails? Perhaps by
running it manually after the system has booted? Perhaps by looking
in the syslog files? I don't know much about RedHat so I can't give
much advice on kudzu. (On the other hand, kudzu itself is not very
important, having the hardware work is important, and then kudzu will
be happy too.)


> The attached is a log, maybe you can help me find some clue. Thank
> you.

Great - see some comments below.


> We just want to gain some BIOS experience, so the LinuxBIOS
> version is very old.

This can be both good and bad. If you started from a known working LB
version then there's no big problem, but if a lot of changes and
bugfixes have gone into LB since the version you are using, it could
be worthwhile to try also a new version.


Comments on the log:

> PCI: pci_scan_bus for bus 00
> PCI: 00:01.0 [1166/0036] enabled

HT1000 PCI/PCI-X bridge


> PCI: 00:02.0 [1166/0205] enabled

HT1000 Legacy South Bridge


> PCI: 00:02.1 [1166/0214] enabled

HT1000 Legacy IDE controller


> PCI: 00:02.2 [1166/0234] enabled

HT1000 LPC Bridge


> PCI: 00:02.3 [1166/0238] enabled
> PCI: 00:02.4 [1166/0235] enabled
> PCI: 00:02.5 [1166/0235] enabled
> PCI: 00:02.6 [1166/0235] enabled

Not in my pci.ids.


> PCI: 00:03.0 [1166/0223] enabled
> PCI: 00:03.1 [1166/0223] enabled
> PCI: 00:03.2 [1166/0223] enabled

3x HT1000 USB Controller


> PCI: 00:04.0 [8086/1229] enabled

82557/8/9 [Ethernet Pro 100]


[..]


> Reading resources...
[..]

> PCI: 00:01.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 01 prefmem

[..]

> PCI: 00:00.0 missing read_resources
> PCI: 00:01.0 missing read_resources
> PCI: 00:02.0 missing read_resources
> PCI: 00:03.0 missing read_resources
> PCI: 00:04.0 missing read_resources
> PCI: 00:05.0 missing read_resources
> PCI: 00:00.0 missing read_resources
> PCI: 00:01.0 missing read_resources
> PCI: 00:01.1 missing read_resources
> PCI: 00:01.2 missing read_resources
> PCI: 00:01.3 missing read_resources
> PCI: 00:01.4 missing read_resources
> PCI: 00:01.5 missing read_resources
> PCI: 00:01.6 missing read_resources
> PCI: 00:02.0 missing read_resources
> PCI: 00:02.1 missing read_resources
> PCI: 00:02.2 missing read_resources
> PCI: 00:03.0 missing read_resources
> PCI: 00:00.0 missing read_resources
> PCI: 00:01.0 missing read_resources
> PCI: 00:02.0 missing read_resources
> PCI: 00:03.0 missing read_resources
> PCI: 00:04.0 missing read_resources
> PCI: 00:05.0 missing read_resources
> PCI: 00:00.0 missing read_resources
> PCI: 00:01.0 missing read_resources
> PCI: 00:01.1 missing read_resources
> PCI: 00:01.2 missing read_resources
> PCI: 00:01.3 missing read_resources
> PCI: 00:01.4 missing read_resources
> PCI: 00:01.5 missing read_resources
> PCI: 00:01.6 missing read_resources
> PCI: 00:02.0 missing read_resources
> PCI: 00:02.1 missing read_resources
> PCI: 00:02.2 missing read_resources
> PCI: 00:03.0 missing read_resources
> PCI: 00:00.0 missing read_resources
> PCI: 00:01.0 missing read_resources
> PCI: 00:02.0 missing read_resources
> PCI: 00:03.0 missing read_resources
> PCI: 00:04.0 missing read_resources
> PCI: 00:05.0 missing read_resources
> PCI: 00:00.0 missing read_resources
> PCI: 00:01.0 missing read_resources
> PCI: 00:01.1 missing read_resources
> PCI: 00:01.2 missing read_resources
> PCI: 00:01.3 missing read_resources
> PCI: 00:01.4 missing read_resources
> PCI: 00:01.5 missing read_resources
> PCI: 00:01.6 missing read_resources
> PCI: 00:02.0 missing read_resources
> PCI: 00:02.1 missing read_resources
> PCI: 00:02.2 missing read_resources
> PCI: 00:03.0 missing read_resources
> Done reading resources.

[..]

> Setting resources...

[..]

> PCI: 00:00.0 missing read_resources
> PCI: 00:01.0 missing read_resources
> PCI: 00:02.0 missing read_resources
> PCI: 00:03.0 missing read_resources
> PCI: 00:04.0 missing read_resources
> PCI: 00:05.0 missing read_resources
[..]

Does this matter, anyone? If there's no read_resources() op (or even
no dev->ops) there's no fallback to generic routines in the code -
are the devices likely to work anyway?


[..]

> PCI: 00:02.0 90 <- [0x0000003040 - 0x000000304f] io
> PCI: 00:02.1 10 <- [0x0000003060 - 0x0000003067] io
> PCI: 00:02.1 14 <- [0x0000003080 - 0x0000003083] io
> PCI: 00:02.1 18 <- [0x0000003070 - 0x0000003077] io
> PCI: 00:02.1 1c <- [0x0000003090 - 0x0000003093] io
> PCI: 00:02.1 20 <- [0x0000003050 - 0x000000305f] io
> PCI: 00:02.1 64 <- [0x00000030a0 - 0x00000030a3] io
> PCI: 00:02.3 10 <- [0x00fc250000 - 0x00fc250fff] mem
> PCI: 00:02.4 10 <- [0x00fc251000 - 0x00fc251fff] mem
> PCI: 00:02.5 10 <- [0x00fc252000 - 0x00fc252fff] mem
> PCI: 00:02.6 10 <- [0x00fc253000 - 0x00fc253fff] mem

Some resources are being assigned either way..

[..]

> Done setting resources.
> Done allocating resources.
> Enabling resources...

[..]

> PCI: 00:01.0 bridge ctrl <- 0003
> PCI: 00:01.0 cmd <- 147

[..]

> PCI: 00:02.0 cmd <- 147
> PCI: 00:02.1 cmd <- 141
> PCI: 00:02.2 cmd <- 144
> PCI: 00:02.3 cmd <- 146
> PCI: 00:02.4 cmd <- 146
> PCI: 00:02.5 cmd <- 146
> PCI: 00:02.6 cmd <- 146
> PCI: 00:03.0 cmd <- 143
> PCI: 00:03.1 cmd <- 143
> PCI: 00:03.2 cmd <- 143
> PCI: 00:04.0 cmd <- 143
[..]

And some command seems to be sent, but..


> PCI: 00:00.0 missing enable_resources
> PCI: 00:01.0 missing enable_resources
> PCI: 00:02.0 missing enable_resources
> PCI: 00:03.0 missing enable_resources
> PCI: 00:04.0 missing enable_resources
> PCI: 00:05.0 missing enable_resources
> PCI: 00:00.0 missing enable_resources
> PCI: 00:01.0 missing enable_resources
> PCI: 00:01.1 missing enable_resources
> PCI: 00:01.2 missing enable_resources
> PCI: 00:01.3 missing enable_resources
> PCI: 00:01.4 missing enable_resources
> PCI: 00:01.5 missing enable_resources
> PCI: 00:01.6 missing enable_resources
> PCI: 00:02.0 missing enable_resources
> PCI: 00:02.1 missing enable_resources
> PCI: 00:02.2 missing enable_resources
> PCI: 00:03.0 missing enable_resources

Here we go again about missing *_resources op or even dev->ops.

Is it just that none is needed for HT1000 or can this be the cause of
the problems?


> NB: Function 3 Misc Control.. done.
> PCI: 00:02.0 init
> PCI: 00:02.1 init
> PCI: 00:02.2 init
> RTC Init
> Invalid CMOS LB checksum
> PCI: 00:02.3 init
> PCI: 00:02.4 init
> PCI: 00:02.5 init
> PCI: 00:02.6 init
> PCI: 00:03.0 init
> PCI: 00:03.1 init
> PCI: 00:03.2 init
> PCI: 00:04.0 init

[..]

> Devices initialized


So most of the devices are initialized, but that may not mean much.



> FILO version 0.5 (fengl at localhost.localdomain) Sat Jul  7 02:41:14 CST 2007
> menu: hda1:/grub/grub.conf

What about FILO - have you tried using a PS/2 keyboard there?
(Compile FILO with a timeout for the boot prompt.) Until that works,
there is not much reason to boot Linux. (Quicker cycles)

[..]


> Linux version 2.6.9-22.ELsmp (bhcompile at crowe.devel.redhat.com)
> (gcc version 3.4.4 20050721 (Red Hat 3.4.4-2)) #1 SMP Mon Sep 19
> 18:00:54 EDT 2005

This kernel is almost two years old, you are ignoring the last 1/5
part of the lifetime of the Linux project.

I would strongly suggest building a recent kernel.org version of
Linux (2.6.21.6 or 2.6.22.1) without modules and making sure it is
configured according to the hardware you're working with. If you want
the list to review your configuration, please feel free to send the
.config created by make menuconfig. (or make xconfig or make qconfig)


[..]

> usbcore: registered new driver hiddev
> usbcore: registered new driver usbhid
> drivers/usb/input/hid-core.c: v2.0:USB HID core driver
> mice: PS/2 mouse device common for all mice

No USB host controllers are found by Linux so it is impossible for a
USB keyboard to work. The HID driver is loaded but it only depends on
the USB core. Maybe the host controller drivers aren't enabled in
this kernel, maybe the PCI devices don't respond properly (LB's
fault) or maybe there are bugs in the HCI drivers. Too many unknowns.


There are at least two interesting things you could try:

1. Investigate the {read,enable}_resources messages from LB for
HT1000 and fix the problem if there is in fact a problem. Best case
this makes everything work. A good first test is if a PS/2 keyboard
works in FILO.

2. Upgrade to the latest kernel, correctly configured for the system,
and see what works/does not work. Perhaps that can give clues about
what is wrong in LB. (if there is something more than 1)

(Could be useful to try 2 before 1 as well.)


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.547.1355071143.16123.coreboot@coreboot.org>

a driver would not have to do very much once in the stack. Is it
really not feasible? It would definately be the cleanest way.


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.560.1355071145.16123.coreboot@coreboot.org>

on which mainboard (and other hardware stats) Linux  was installed.

http://smolt.fedoraproject.org/stats

-- 
With best regards!



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.581.1355071153.16123.coreboot@coreboot.org>

contacts seem easier to solder, but I like the idea of having one
factory bios stuffed away in a safe place, away from the mobo and that
seems easier to achieve with a socket. :)

/Rasmus



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.634.1355071160.16123.coreboot@coreboot.org>

Right now, you would probably get a MB with an SPI BIOS if you buy one,
and those boards seem to be a bit of work in progress. You may want to
try any of the boards listed on <http://www.linuxbios.org/Desktops> if
you feel adventurous.

/Rasmus



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.685.1355071169.16123.coreboot@coreboot.org>

(publicly-available) laptop hardware.  To quote Uwe Hermann:

http://article.gmane.org/gmane.linux.bios/26520
"Correct. No laptop whatsoever (except for the OLPC) is supported by
LinuxBIOS at the moment. We definately like to change that, but at the
moment there's no support at all."

Now before you consider purchasing an OLPC, please note that Uwe is
referring to alpha/beta OLPC hardware; the final mass-produced model
does not use LinuxBIOS, and the hardware has changed significantly
enough that it would take quite a bit of effort to get it to support
LinuxBIOS.

Don't give up hope:  a significant number of people (myself included)
would very much like to have a laptop that supports LinuxBIOS.  If
you're interested in making this happen, you might consider staying on
the mailing list and seeing what you can do to help LinuxBIOS in
general.


Cheers,
-- R



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.719.1355071176.16123.coreboot@coreboot.org>

PlayStation 3. It's based on the existing kboot project, plus the twin
windowing system for the GUI."

Maybe this is something we can list in the wiki as possible payload.

Carl-Daniel



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.733.1355071180.16123.coreboot@coreboot.org>

>> +
>> +
>> +	// enable the internal I/O decode
>> +	enables = pci_read_config8(dev, 0x6C);
>> +	enables |= 0x80;
>> +	pci_write_config8(dev, 0x6C, enables);
>> +
>> +	//FIXME Map 4MB of FLASH into the address space
>> +	pci_write_config8(dev, 0x41, 0x0);
>>     
>
> Should be the maximum possible, does that make sense? Or it could be
> a config option.
>   

I'll test this soon. Do as you wish with it, I can patch it up later if
needed.

>> +
>> +	// Set bit 6 of 0x40, because Award does it (IO recovery time)
>> +	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI 
>> +	// interrupts can be properly marked as level triggered.
>> +	enables = pci_read_config8(dev, 0x40);
>> +	enables |= 0x44;
>> +	pci_write_config8(dev, 0x40, enables);
>> +
>> +	// Set 0x42 to 0xf8 to match Award bios
>>     
>
> Nah, please don't try to blindly match what other BIOSes do, only if
> there's a good reason (functionality or performance). We want to
> know exactly _why_ this is done (or not).
>   

It's interrupt options, explaning would be a pain without just copy and
pasting the datasheet. Perhaps a "refer to the datasheet" would be best.

>> +	enables = pci_read_config8(dev, 0x42);
>> +	enables |= 0xf8;
>> +	pci_write_config8(dev, 0x42, enables);
>> +
>> +
>> +	/* Delay Transaction Control */
>> +	pci_write_config8(dev, 0x43, 0xb);
>> +
>> +	/* IO Recovery time */
>> +	pci_write_config8(dev, 0x4c, 0x44);
>> +
>> +	/* ROM Memory Cycles Go To LPC */
>> +	pci_write_config8(dev, 0x59, 0x80);
>> +
>> +	/* bypass Bypass APIC De-Assert Message,  INTE#, INTF#, INTG#, INTH# as PCI  */
>> +	pci_write_config8(dev, 0x5B, 0xb);
>> +
>> +	/* set  Read Pass Write Control  Enable (force A2 from APIC FSB to low) */
>> +	pci_write_config8(dev, 0x48, 0x8c);
>> +
>> +	/* Set 0x58 to 0x43 APIC and RTC */
>> +	pci_write_config8(dev, 0x58, 0x43);
>> +
>> +	/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
>> +	enables = pci_read_config8(dev, 0x4f);
>> +	enables |= 0x08;
>> +	pci_write_config8(dev, 0x4f, enables);
>> +
>> +	/* enable serial irq */
>> +	pci_write_config8(dev, 0x52, 0x9);
>> +
>> +
>> +
>> +	/* dma */
>> +	//pci_write_config8(dev, 0x53, 0x00);
>> +
>> +	//enable HPET, ACPI has define to fixed addr
>> +#define HPET_ADDR  0xfed00000ULL
>>     
>
> Put this at the top of the file or in the *.h file. Does it make sense
> to make a config option out of it?
>   

No config option, it's a fixed address. I'm writing this from the bottom
up, so the lower posts explain a bit more. Should be at the top of the
file though, or else hardcoded (or perhaps even defined in acpi files,
since these seem to be generic values). It might already be defined in
some acpi file.

>> +void vt8237r_read_resources(device_t dev)
>> +{
>> +	struct resource *res;
>> +
>> +	pci_dev_read_resources(dev);
>> +
>> +	/* fixed APIC resource */
>> +	res = new_resource(dev, 0x44);
>> +	res->base = 0xfec00000;
>>     
>
> Is this different from HPET_ADDR? Should it?
>   

Yes, this is ioapic not hpet.

>> +	vt8237r_init(dev);
>> +	pci_routing_fixup(dev);
>> +	setup_ioapic(0xfec00000);
>>     
>
> Why hardcode this number here again?
>   

This is a non-configurable address, messing around with it will bork
things up.

>> +	if (resource) {
>> +		report_resource_stored(dev, resource, "<mmconfig>");
>> +
>> +		/* Remember this resource has been stored */
>> +		resource->flags |= IORESOURCE_STORED;
>> +		pci_write_config8(dev, 0x61, (resource->base >> 28));
>> +		reg = pci_read_config8(dev, 0x60);
>> +		reg |= 0x3;
>> +		/* enable MMCONFIG decoding */
>> +		pci_write_config8(dev, 0x60, reg);
>> +	}
>> +
>> +	pci_dev_set_resources(dev);
>> +}
>> +
>> +
>> +
>> +static void apic_mmconfig_read_resources(device_t dev)
>> +{
>> +	struct resource *res;
>> +	pci_dev_read_resources(dev);
>> +
>> +	res = new_resource(dev, 0x40);
>> +	/* NB APIC fixed to this addr */
>> +	res->base = 0xfecc0000;
>>     
>
> Hardcoded again. I think this should be a #define in *.h or even a
> config option, rather than hardcoding it in all places.
>   

Another fixed address, I think this one is LAPIC. Config options are not
an option, these aren't configurable.

>> +
>> +##
>> +## Build code to export an x86 MP table
>> +## Useful for specifying IRQ routing values
>> +##
>> +default HAVE_MP_TABLE=1
>> +
>> +##
>> +## Build code to export a CMOS option table
>> +##
>> +##default HAVE_OPTION_TABLE=1
>>     
>
> Either enable it, or drop cmos.layout below.
>   

Huh? afaik it is enabled (with default USE_OPTION_TABLE !=
USE_FALLBACK_IMAGE below).

>> Index: src/mainboard/asus/a8v/acpi_tables.c
>> ===================================================================
>> --- src/mainboard/asus/a8v/acpi_tables.c	(revision 0)
>> +++ src/mainboard/asus/a8v/acpi_tables.c	(revision 0)
>> @@ -0,0 +1,155 @@
>> +/*
>> + * LinuxBIOS ACPI Table support
>> + * written by Stefan Reinauer <stepan at openbios.org>
>> + * ACPI FADT, FACS, and DSDT table support added by 
>> + * Nick Barker <nick.barker9 at btinternet.com>, and those portions
>> + * (C) Copyright 2004 Nick Barker
>> + * (C) Copyright 2005 Stefan Reinauer
>> + */
>>     
>
> Missing license. Please check back with Stefan/Nick, but I guess it's
> GPL (v2? v2-or-later?).
>
> How similar is this file to the original one? Does it make sense to
> drop this file and make the original one a generic version which can be
> used by multiple chipsets?
>   

Nope, different boards have different tables. A uniprocessor board has
fewer tables than a multiprocessor board, and different archs also have
different/other tables. I think acpi is as generic as it's going to get.

>> Index: src/mainboard/asus/a8v/fadt.c
>> ===================================================================
>> --- src/mainboard/asus/a8v/fadt.c	(revision 0)
>> +++ src/mainboard/asus/a8v/fadt.c	(revision 0)
>> @@ -0,0 +1,157 @@
>> +/*
>> + * ACPI - create the Fixed ACPI Description Tables (FADT)
>> + * (C) Copyright 2004 Nick Barker <nick.barker9 at btinternet.com>
>> + *
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>> + */
>> +
>> +
>> +#include <string.h>
>> +#include <arch/acpi.h>
>> +
>> +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
>> +{
>>     
>
> Did you modify this file? How? Should probably be a common global file,
> not copied in each target?

The FADT is/should be mainboard-specific. So please don't try to
generic-ize it. My fadt is somewhat different, FWIW.

-Corey



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.830.1355071196.16123.coreboot@coreboot.org>

similar. Could you write a few lines about it? Like a changelog
message.. "fix" is not very informative. :\ (Yes, I could try to
understand the code.)


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.843.1355071197.16123.coreboot@coreboot.org>

Does anybody have an idea what's missing/changed?

Thanks,

	Andi 



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.942.1355071212.16123.coreboot@coreboot.org>

easy.  Very small changes frequently require you to run make oldconfig so
that you can handle all of the options that were not set, but now need to be
set because you changed an option.

Maybe there is a good way to do hierarchical make menuconfig, but then you
get the problem that the sources haven't been downloaded yet when you are
configuring buildrom.

That said, I haven't used v3 yet.

It seems like in the current state, the addition of new options (a new form
of compression, for instance) in v3's config files might require patching
all of the .config files in buildrom.  That doesn't seem nice.

I'm just hoping that when v3 supports the platforms I'm interested in it
will be easy for buildrom to select which images to include and do some
rudimentary calculations to see if they'll fit in the ROM.

Thanks,

Myles
PS If I'm overlooking the obvious, easy ways to do things I'm all ears.
It's easy to end up doing things the hard way if you don't know what the
easy way is.





From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.963.1355071217.16123.coreboot@coreboot.org>

contains
hardware other then just normal things found on the average desktop. =
There
are controllers in use that are normally not documented for special =
features
for example.

Take a look for example at the Linux kernel features for enabling the =
GPIO
found on the VAIO from Sony, since the firm probably was reluctant to
release information on it, it was sorted out by reverse engineering.

That's just one example. I would imagine that the others can bring up =
more
items to this discussion.
--
Gregg C Levine hansolofalcon at worldnet.att.net
"The Force will be with you always." Obi-Wan Kenobi
=A0=20


> -----Original Message-----
> From: linuxbios-bounces+hansolofalcon=3Dworldnet.att.net at linuxbios.org
[mailto:linuxbios-
> bounces+hansolofalcon=3Dworldnet.att.net at linuxbios.org] On Behalf Of =
Jun Koi
> Sent: Tuesday, December 11, 2007 7:41 PM
> To: Uwe Hermann
> Cc: linuxbios at linuxbios.org
> Subject: Re: [LinuxBIOS] Will linuxBIOS Work on My Machine?
>=20
> On 12/10/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> > On Wed, Dec 05, 2007 at 12:31:54PM -0800, Wakefield, John  wrote:
> > > I have an Acer 5102WLMi Notebook with Dual Core AMD TL50s, which =
are
64
> >
> > I'm afraid LinuxBIOS doesn't yet work on laptops, those are much =
harder
> > to support than "normal" PCs for various reasons. It's on our TODO =
list
to
> > support laptops too sooner or later, but it's not a trivial task.
> >
>=20
> Uwe, could you elaborate a bit here? Why supporting laptops is
> technically much harder than desktop??
>=20
> Many thanks,
> Jun
>=20
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.991.1355071224.16123.coreboot@coreboot.org>

that caused this problem. I saw you allocated 32MB for agp
aperture memory in agp.c, so reserving 32MB works for you, and I
changed this to 128MB for agp aperture memory so 128MB works for me.
The problem is why this agp aperture memory is at physical memory range
(tolm - agp_aperture_size to tolm) while we have set this agp
aperture memory
base at some very large address(e.g 0xe0000000). should this memory range
be assigned a mtrr?

The changes I made to your code are :
1) some registers in host bus, as their values are different from the
factory BIOS ones;
2) dram size releated registers
3) dram timing is ok. and I found couldn't change dram operating frequency
;-(

------=_Part_255_23671061.1198250742389
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Content-Disposition: inline

On Dec 21, 2007 1:40 PM, Corey Osgood &lt;<a href="mailto:corey.osgood at gmail.com" target="_blank">corey.osgood at gmail.com</a>&gt; wrote:<br>
<div class="gmail_quote">
<blockquote class="gmail_quote" style="PADDING-LEFT: 1ex; MARGIN: 0pt 0pt 0pt 0.8ex; BORDER-LEFT: rgb(204,204,204) 1px solid">
<div>
<div></div>
<div>aaron lwe wrote:<br>&gt; Dear All,<br>&gt;<br>&gt; I&#39;m terribly sorry that I just found I&#39;ve mistakenly configured the<br>&gt; dram MA Map Type, and now memtest<br>&gt; showed no errors. But I still have to reduce the mem size when 
<br>&gt; reporting to system through ram_resource<br>&gt; or filo couldn&#39;t be started. &nbsp;I have disabled the integrated graphics<br>&gt; card and the agp, so I don&#39;t think the top<br>&gt; memory should be reserved for frame buffer. 
<br><br></div></div>And now you&#39;re where I am. For some reason there&#39;s a reserved memory<br>range _somewhere_ at the tolm, of some unknown size. I&#39;ve found that<br>reserving an extra 1MB doesn&#39;t work, but 32MB does. I&#39;ve found nothing 
<br>in the documentation I have to explain this. BTW, have you had to make<br>any code changes other than the MA Map, and board-specific fixes? I&#39;m<br>wondering how generic that code really is.<br><font color="#888888">
<br>-Corey<br></font></blockquote></div>
<div><br><br>From what you have said, I guess it might&nbsp;be&nbsp;AGP aperture memory</div>
<div>that caused this problem. I saw you allocated 32MB for agp</div>
<div>aperture memory in agp.c, so reserving 32MB works for you, and I </div>
<div>changed this to&nbsp;128MB for agp aperture memory&nbsp;so&nbsp;128MB&nbsp;works for me.</div>
<div>The problem is why this agp aperture memory is at physical memory range</div>
<div>(tolm - agp_aperture_size to tolm) while&nbsp;we have set&nbsp;this agp aperture&nbsp;memory</div>
<div>base at some very large address(e.g 0xe0000000). should this memory range </div>
<div>be assigned a mtrr?</div>
<div>&nbsp;</div>
<div>The changes I made to your code&nbsp;are :</div>
<div>1) some registers in host bus, as their values&nbsp;are different&nbsp;from the factory BIOS ones;</div>
<div>2) dram size releated registers</div>
<div>3) dram timing is ok. and I found couldn&#39;t change dram operating frequency ;-(</div>
<div>&nbsp;</div>

------=_Part_255_23671061.1198250742389--



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.992.1355071224.16123.coreboot@coreboot.org>

that caused this problem. I saw you allocated 32MB for agp
aperture memory in agp.c, so reserving 32MB works for you, and I
changed this to 128MB for agp aperture memory so 128MB works for me.
The problem is why this agp aperture memory is at physical memory range
(tolm - agp_aperture_size to tolm) while we have set this agp
aperture memory
base at some very large address(e.g 0xe0000000). should this memory range
be assigned a mtrr?

The changes I made to your code are :
1) some registers in host bus, as their values are different from the
factory BIOS ones;
2) dram size releated registers
3) dram timing is ok. and I found couldn't change dram operating frequency
;-(

------=_Part_279_2122024.1198252516299
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Content-Disposition: inline

<div class="gmail_quote">
<div>
<div class="Wj3C7c">On Dec 21, 2007 1:40 PM, Corey Osgood &lt;<a href="mailto:corey.osgood at gmail.com" target="_blank">corey.osgood at gmail.com</a>&gt; wrote:<br>
<div class="gmail_quote">
<blockquote class="gmail_quote" style="PADDING-LEFT: 1ex; MARGIN: 0pt 0pt 0pt 0.8ex; BORDER-LEFT: rgb(204,204,204) 1px solid">
<div>
<div></div>
<div>aaron lwe wrote:<br>&gt; Dear All,<br>&gt;<br>&gt; I&#39;m terribly sorry that I just found I&#39;ve mistakenly configured the<br>&gt; dram MA Map Type, and now memtest<br>&gt; showed no errors. But I still have to reduce the mem size when 
<br>&gt; reporting to system through ram_resource<br>&gt; or filo couldn&#39;t be started. &nbsp;I have disabled the integrated graphics<br>&gt; card and the agp, so I don&#39;t think the top<br>&gt; memory should be reserved for frame buffer. 
<br><br></div></div>And now you&#39;re where I am. For some reason there&#39;s a reserved memory<br>range _somewhere_ at the tolm, of some unknown size. I&#39;ve found that<br>reserving an extra 1MB doesn&#39;t work, but 32MB does. I&#39;ve found nothing 
<br>in the documentation I have to explain this. BTW, have you had to make<br>any code changes other than the MA Map, and board-specific fixes? I&#39;m<br>wondering how generic that code really is.<br><font color="#888888">
<br>-Corey<br></font></blockquote></div></div></div>
<div><br>&nbsp;</div>
<div>It seems that the last message I sent is wrong...</div>
<div><br>From what you have said, I guess it might&nbsp;be&nbsp;AGP aperture memory</div>
<div>that caused this problem. I saw you allocated 32MB for agp</div>
<div>aperture memory in agp.c, so reserving 32MB works for you, and I </div>
<div>changed this to&nbsp;128MB for agp aperture memory&nbsp;so&nbsp;128MB&nbsp;works for me.</div>
<div>The problem is why this agp aperture memory is at physical memory range</div>
<div>(tolm - agp_aperture_size to tolm) while&nbsp;we have set&nbsp;this agp aperture&nbsp;memory</div>
<div>base at some very large address(e.g 0xe0000000). should this memory range </div>
<div>be assigned a mtrr?</div>
<div>&nbsp;</div>
<div>The changes I made to your code&nbsp;are :</div>
<div>1) some registers in host bus, as their values&nbsp;are different&nbsp;from the factory BIOS ones;</div>
<div>2) dram size releated registers</div>
<div>3) dram timing is ok. and I found couldn&#39;t change dram operating frequency ;-(</div></div>

------=_Part_279_2122024.1198252516299--



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1001.1355071226.16123.coreboot@coreboot.org>

around 7 seconds.  I've got access to device programmers and 2m repair
stuff, so flashing isn't a huge issue.

Would this be a good board for a proof of concept, or should I look at
something else.

The board is a Kino LX800, AMD GEODE 500mhz, sata/pata, onboard amd
video, onboard realtek 8139 ethernet.

I'd like to to LB and kernel in flash, but if the hardware won't suppor
a 16mbit flash, then I'll do lb/filo and boot from CF over the standard
ide channel.  The board currently has a 49fl004 socketed flash.  Plan on
using a stripped down debian install, since that's the only one I can
reliably shrink.

Thanks,
Mark



Here's all the specs:

http://tinyurl.com/3ajv9l

Here's the output of lspci.

00:01.0 Host bridge: Advanced Micro Devices [AMD] Unknown device 2080
(rev 31)
00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX
Video
00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD]
Geode LX AES Security Block
00:0e.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ (rev 10)
00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode
companion] ISA (rev 03)
00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode
companion] IDE (rev 01)
00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536
[Geode companion] Audio (rev 01)
00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode
companion] OHC (rev 02)
00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode
companion] EHC (rev 02)
00:10.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ (rev 10)
00:11.0 Mass storage controller: ALi Corporation ALi M5281 Serial ATA /
RAID Host Controller (rev a4)
00:11.1 Mass storage controller: ALi Corporation M5228 ALi ATA/RAID
Controller (rev c6)
00:12.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ (rev 10)


Here's the more verbose lspci output recommend by the guys on irc.


00:01.0 0600: 1022:2080 (rev 31)
        Subsystem: 1022:2080
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 248, Cache Line Size: 32 bytes
        Region 0: I/O ports at ac1c [size=4]
        Region 1: I/O ports at 9e00 [size=8]
00: 22 10 80 20 05 00 20 02 31 00 00 06 08 f8 80 00
10: 1d ac 00 00 01 9e 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 80 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:01.1 0300: 1022:2081
        Subsystem: 1022:2081
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0, Cache Line Size: 32 bytes
        Interrupt: pin A routed to IRQ 11
        Region 0: Memory at ee000000 (32-bit, non-prefetchable) [size=16M]
        Region 1: Memory at efff4000 (32-bit, non-prefetchable) [size=16K]
        Region 2: Memory at efff0000 (32-bit, non-prefetchable) [size=16K]
        Region 3: Memory at effec000 (32-bit, non-prefetchable) [size=16K]
        Region 4: Memory at effe8000 (32-bit, non-prefetchable) [size=16K]
00: 22 10 81 20 07 00 20 02 00 00 00 03 08 00 00 00
10: 00 00 00 ee 00 40 ff ef 00 00 ff ef 00 c0 fe ef
20: 00 80 fe ef 00 00 00 00 00 00 00 00 22 10 81 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00

00:01.2 1010: 1022:2082
        Subsystem: 1022:2082
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0, Cache Line Size: 32 bytes
        Interrupt: pin A routed to IRQ 11
        Region 0: Memory at effe4000 (32-bit, non-prefetchable) [size=16K]
00: 22 10 82 20 06 00 a0 02 00 00 10 10 08 00 00 00
10: 00 40 fe ef 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 82 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00

00:0e.0 0200: 10ec:8139 (rev 10)
        Subsystem: 10ec:8139
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR+
        Latency: 32 (8000ns min, 16000ns max)
        Interrupt: pin A routed to IRQ 11
        Region 0: I/O ports at f200 [size=256]
        Region 1: Memory at effff000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [50] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
PME(D0-,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: ec 10 39 81 07 00 90 82 10 00 00 02 00 20 00 00
10: 01 f2 00 00 00 f0 ff ef 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40

00:0f.0 0601: 1022:2090 (rev 03)
        Subsystem: 1022:2090
        Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Region 0: I/O ports at 6000 [size=8]
        Region 1: I/O ports at 6100 [size=256]
        Region 2: I/O ports at 6200 [size=64]
        Region 3: I/O ports at 1000 [size=32]
        Region 4: I/O ports at 9d00 [size=128]
        Region 5: I/O ports at 9c00 [size=64]
00: 22 10 90 20 09 00 a0 02 03 00 01 06 08 40 80 00
10: 01 60 00 00 01 61 00 00 01 62 00 00 01 10 00 00
20: 01 9d 00 00 01 9c 00 00 00 00 00 00 22 10 90 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:0f.2 0101: 1022:209a (rev 01) (prog-if 80)
        Subsystem: 1022:209a
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 248, Cache Line Size: 32 bytes
        Region 0: [virtual] Memory at 000001f0 (32-bit,
non-prefetchable) [disabled] [size=8]
        Region 1: [virtual] Memory at 000003f0 (type 3,
non-prefetchable) [disabled] [size=1]
        Region 2: [virtual] Memory at 00000170 (32-bit,
non-prefetchable) [disabled] [size=8]
        Region 3: [virtual] Memory at 00000370 (type 3,
non-prefetchable) [disabled] [size=1]
        Region 4: I/O ports at ff00 [size=16]
00: 22 10 9a 20 05 00 a0 02 01 80 01 01 08 f8 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 ff 00 00 00 00 00 00 00 00 00 00 22 10 9a 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:0f.3 0401: 1022:2093 (rev 01)
        Subsystem: 1022:2093
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0, Cache Line Size: 32 bytes
        Interrupt: pin B routed to IRQ 11
        Region 0: I/O ports at fe00 [size=128]
00: 22 10 93 20 05 00 a0 02 01 00 01 04 08 00 00 00
10: 01 fe 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 93 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 02 00 00

00:0f.4 0c03: 1022:2094 (rev 02) (prog-if 10)
        Subsystem: 1022:2094
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0, Cache Line Size: 32 bytes
        Interrupt: pin D routed to IRQ 11
        Region 0: Memory at efffe000 (32-bit, non-prefetchable) [size=4K]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 22 10 94 20 06 00 30 02 02 10 03 0c 08 00 00 00
10: 00 e0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 94 20
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 00 00

00:0f.5 0c03: 1022:2095 (rev 02) (prog-if 20)
        Subsystem: 1022:2095
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0, Cache Line Size: 32 bytes
        Interrupt: pin D routed to IRQ 11
        Region 0: Memory at efffd000 (32-bit, non-prefetchable) [size=4K]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 22 10 95 20 06 00 30 02 02 20 03 0c 08 00 00 00
10: 00 d0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 95 20
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 00 00

00:10.0 0200: 10ec:8139 (rev 10)
        Subsystem: 10ec:8139
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32 (8000ns min, 16000ns max)
        Interrupt: pin A routed to IRQ 11
        Region 0: I/O ports at f000 [size=256]
        Region 1: Memory at efffc000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [50] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
PME(D0-,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 f0 00 00 00 c0 ff ef 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40

00:11.0 0180: 10b9:5281 (rev a4) (prog-if 85)
        Subsystem: 10b9:5281
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 128, Cache Line Size: 512 bytes
        Interrupt: pin A routed to IRQ 11
        Region 0: I/O ports at fd00 [size=8]
        Region 1: I/O ports at fc00 [size=4]
        Region 2: I/O ports at fb00 [size=8]
        Region 3: I/O ports at fa00 [size=4]
        Region 4: I/O ports at f900 [size=16]
        [virtual] Expansion ROM at 20000000 [disabled] [size=64K]
00: b9 10 81 52 05 00 a0 02 a4 85 80 01 80 80 80 00
10: 01 fd 00 00 01 fc 00 00 01 fb 00 00 01 fa 00 00
20: 01 f9 00 00 00 00 00 00 00 00 00 00 b9 10 81 52
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00

00:11.1 0180: 10b9:5228 (rev c6) (prog-if 85)
        Subsystem: 10b9:5281
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 128
        Interrupt: pin A routed to IRQ 11
        Region 0: I/O ports at f800 [size=8]
        Region 1: I/O ports at f700 [size=4]
        Region 2: I/O ports at f600 [size=8]
        Region 3: I/O ports at f500 [size=4]
        Region 4: I/O ports at f400 [size=16]
00: b9 10 28 52 05 00 a0 02 c6 85 80 01 00 80 80 00
10: 01 f8 00 00 01 f7 00 00 01 f6 00 00 01 f5 00 00
20: 01 f4 00 00 00 00 00 00 a0 00 00 00 b9 10 81 52
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00

00:12.0 0200: 10ec:8139 (rev 10)
        Subsystem: 10ec:8139
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32 (8000ns min, 16000ns max)
        Interrupt: pin A routed to IRQ 11
        Region 0: I/O ports at ee00 [size=256]
        Region 1: Memory at efffb000 (32-bit, non-prefetchable) [size=256]
        [virtual] Expansion ROM at 20010000 [disabled] [size=64K]
        Capabilities: [50] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0-,D1+,D2+,D3hot+,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 ee 00 00 00 b0 ff ef 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1101.1355071246.16123.coreboot@coreboot.org>

biosint: INT# 0x18
biosint: eax 0x84e53 ebx 0x38 ecx 0xff0 edx 0x87ed8
biosint: ebp 0x60000000 esp 0x87f60 edi 0x15 esi 0x0
biosint:  ip 0x28   cs 0x1000  flags 0x26

That's just bogus as far as I can tell. Note that edi is 15, kind of looks like
the interrupt. ebp is 60000000, kind of looks like cs and something else.

And so on. It's like we got someone else's stack frame.

ron



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1116.1355071249.16123.coreboot@coreboot.org>

"In the LAN controller the D0 state is partitioned into two substates, D0
Uninitialized (D0u) and D0 Active (D0a). [...] Initialization of the CSR,
Memory, or I/O Base Registers in the PCI Configuration space switches the
LAN controller D0u state to the D0a state."

and

"The integrated LAN controller will be disabled if no Platform LAN Connect
component is detected (See Section 5.2.1.3)."


Any help?

-Corey

On Feb 5, 2008 11:44 AM, Peter Stuge <peter at stuge.se> wrote:

> On Tue, Feb 05, 2008 at 10:51:39AM -0500, joe at smittys.pointclark.netwrote:
> > So I found this in the ICH4 datasheet:
> >
> > The LAN controller enters Wake on LAN mode after reset if the Wake
> > on LAN bit in the EEPROM is set *(which it is)*.
>
> You could try changing this bit in the EEPROM before running
> coreboot and see if you get different results from the PCI scan.
>
>
> > When the LAN controller is in Wake on LAN mode:
> > ? The LAN controller scans incoming packets for a Magic Packet and
> > asserts the PME# signal for 52 ms when a one is detected in Wake on
> > LAN mode.
>
> ..
> > ? The PCI Configuration registers are accessible to the host *(this
> > is what I'm looking for!!)*.
>
> Right, and this says that they are accessible even when the NIC is in
> WoL mode.
>
>
> > So, if this is correct I think I was right in saying the nic seemed
> > like it was powered off?? At this point I need to figure out how to
> > assert a PME# signal to wake up the nic. Maybe from the Power
> > Managment Control register??
>
> Note that PME# is asserted by the NIC. Ie. PME# is considered an
> output from the NIC. Remember that Wake on LAN means that the NIC
> wakes up the computer if a special packet is received.
>
> I'm afraid I don't think this is causing the problem you're seeing.
> :\
>
>
> //Peter
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

------=_Part_742_15635457.1202240992449
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Content-Disposition: inline


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1117.1355071249.16123.coreboot@coreboot.org>

<br>and<br><br>&quot;The integrated LAN controller will be disabled if no Platform LAN Connect component is detected (See Section <a href="http://5.2.1.3">5.2.1.3</a>).&quot;<br><br><br>Any help?<br><br>-Corey<br><br><div class="gmail_quote">
On Feb 5, 2008 11:44 AM, Peter Stuge &lt;<a href="mailto:peter at stuge.se">peter at stuge.se</a>&gt; wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div class="Ih2E3d">On Tue, Feb 05, 2008 at 10:51:39AM -0500, <a href="mailto:joe at smittys.pointclark.net">joe at smittys.pointclark.net</a> wrote:<br>&gt; So I found this in the ICH4 datasheet:<br>&gt;<br>&gt; The LAN controller enters Wake on LAN mode after reset if the Wake<br>
&gt; on LAN bit in the EEPROM is set *(which it is)*.<br><br></div>You could try changing this bit in the EEPROM before running<br>coreboot and see if you get different results from the PCI scan.<br><div class="Ih2E3d"><br>
<br>&gt; When the LAN controller is in Wake on LAN mode:<br>&gt; ? The LAN controller scans incoming packets for a Magic Packet and<br>&gt; asserts the PME# signal for 52 ms when a one is detected in Wake on<br>&gt; LAN mode.<br>
<br>..<br></div><div class="Ih2E3d">&gt; ? The PCI Configuration registers are accessible to the host *(this<br>&gt; is what I&#39;m looking for!!)*.<br><br></div>Right, and this says that they are accessible even when the NIC is in<br>
WoL mode.<br><div class="Ih2E3d"><br><br>&gt; So, if this is correct I think I was right in saying the nic seemed<br>&gt; like it was powered off?? At this point I need to figure out how to<br>&gt; assert a PME# signal to wake up the nic. Maybe from the Power<br>
&gt; Managment Control register??<br><br></div>Note that PME# is asserted by the NIC. Ie. PME# is considered an<br>output from the NIC. Remember that Wake on LAN means that the NIC<br>wakes up the computer if a special packet is received.<br>
<br>I&#39;m afraid I don&#39;t think this is causing the problem you&#39;re seeing.<br>:\<br><font color="#888888"><br><br>//Peter<br></font><div><div></div><div class="Wj3C7c"><br>--<br>coreboot mailing list<br><a href="mailto:coreboot at coreboot.org">coreboot at coreboot.org</a><br>
<a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br></div></div></blockquote></div><br>

------=_Part_742_15635457.1202240992449--



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1253.1355071275.16123.coreboot@coreboot.org>

want to read some partition information from, I would guess, the MBR -- and there is no MBR from the process we used to generate the
disk image file. I think that is the problem. I don't know much about qemu-img options that may get around this or if some FILO
options do this. I would guess that that would be where to try and find a way out of this.

I'm told, near the beginning, one can run fdisk on the image file, to create an MBR, but then adding the OS files becomes a problem
because you must copy them to some offset in the disk image file.

IS the problem that an MBR is needed and that it should have been created or is there something else to do, to make it boot without
an MBR?



> -----Original Message-----
> From: ron minnich [mailto:rminnich at gmail.com]
> Sent: Thursday, March 06, 2008 4:01 PM
> To: David Edrich
> Cc: Myles Watson; Coreboot
> Subject: Re: [coreboot] qemu error message: "Unrecognized partitioning scheme"
> 
> david, can you just send me your disk image file?
> 
> ron





From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1335.1355071289.16123.coreboot@coreboot.org>

S-records which contain both address and data. Because x86 always
starts at top of 4GB there is no need for address information.

The flash chip must always be at the top of 4GB. The binary flash
file is always written to the top of the flash.


> (or) how can I locate the code inside the coreboot.rom,if it is
> there inside the rom file.

The dd and objdump trick I show above will work but is very clumsy
and does not scale well.

I recommend the DOS utility HIEW (Hackers View) if you're going to be
taking apart binary files. It has some useful disassembly options.

The thing with dd and objdump is that because there are bytes in the
coreboot.rom stream that are not instructions but instead data, it is
not neccessarily possible to disassemble the entire coreboot.rom file
in one go and then take it apart. When data at one byte position is
parsed as an instruction it may parse the following byte as part of
the same instruction which causes an error in alignment in the
disassembler because the data byte in the first position was actually
the last data byte and the following byte was the first byte of an
instruction. This is why you usually have to explicitly chop up the
binary file at whatever boundary you are interested in.


But why are you doing this anyway? Wouldn't it be easier to just look
at the source code?


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1383.1355071298.16123.coreboot@coreboot.org>

$ telnet smittys.pointclark.net 25
Trying 65.175.181.44...
Connected to smittys.pointclark.net.
Escape character is '^]'.
220 smittys.pointclark.net ESMTP Postfix
quit
221 Bye
Connection closed by foreign host.

Traceroute looks normal:

khepri:/var/log/exim $ traceroute smittys.pointclark.net
traceroute to smittys.pointclark.net (65.175.181.44), 30 hops max, 40 byte
packets
 1  gw.rtr1.colo1.NBG1.ip-exchange.de (212.123.124.185)  0.317 ms   0.490 ms
0.501 ms
 2  ge3-5.cr2.NBG1.content-core.net (212.123.127.65)  0.224 ms   0.227 ms
0.217 ms
 3  Tenge2-4-57.cr3.FRA3.content-core.net (212.123.123.203)  3.525 ms   3.471
ms   3.484 ms
 4  4G-p2.cr1.FRA3.content-core.net (212.123.123.42)  3.503 ms   3.458 ms
3.402 ms
 5  193.159.224.21 (193.159.224.21)  3.707 ms   3.700 ms   3.509 ms
 6  f-ea5.F.DE.net.DTAG.DE (62.154.16.161)  3.741 ms   3.753 ms   3.759 ms
 7  te-4-4.car2.Frankfurt1.Level3.net (4.68.110.253)  4.089 ms   4.119 ms
4.101 ms
 8  ae-32-54.ebr2.Frankfurt1.Level3.net (4.68.118.126)  6.728 ms   16.346 ms
13.799 ms
 9  ae-1-100.ebr1.Frankfurt1.Level3.net (4.69.132.125)  13.597 ms   6.701 ms
6.489 ms
10  ae-2.ebr2.Paris1.Level3.net (4.69.132.141)  13.381 ms   26.367 ms
25.514 ms
11  ae-44.ebr2.Washington1.Level3.net (4.69.137.62)  100.867 ms
ae-41.ebr2.Washington1.Level3.net (4.69.137.50)  97.342 ms
ae-42.ebr2.Washington1.Level3.net (4.69.137.54)  97.593 ms
12  ae-82-82.csw3.Washington1.Level3.net (4.69.134.154)  107.265 ms
ae-92-92.csw4.Washington1.Level3.net (4.69.134.158)  97.440 ms
ae-62-62.csw1.Washington1.Level3.net (4.69.134.146)  101.640 ms
13  ae-71-71.ebr1.Washington1.Level3.net (4.69.134.133)  97.547 ms
ae-81-81.ebr1.Washington1.Level3.net (4.69.134.137)  103.698 ms *
14  ae-4-4.car1.Cleveland1.Level3.net (4.69.132.193)  101.302 ms   102.199 ms
102.147 ms
15  ae-11-11.car2.Cleveland1.Level3.net (4.69.132.198)  102.603 ms   101.464
ms   101.079 ms
16  ROADRUNNER.car2.Cleveland1.Level3.net (4.78.59.46)  122.099 ms   122.230
ms   121.963 ms
17  gig15-0-0.ptldmeptl-rtr02.nyroc.rr.com (24.24.7.150)  134.609 ms
135.359 ms   134.807 ms
18  rrcs-24-39-3-2.nys.biz.rr.com (24.39.3.2)  134.779 ms   136.254 ms
135.865 ms
19  * * *
...

And from here in Boston:

$ traceroute smittys.pointclark.net
traceroute to smittys.pointclark.net (65.175.181.44), 30 hops max, 40 byte
packets
 ...
 3  vl200.aggr1.sbo.ma.rcn.net (209.6.160.100)  16.420 ms  16.833 ms  17.103
ms
 4  ge3-4.border1.sbo.ma.rcn.net (207.172.19.85)  46.691 ms  47.108 ms
47.312 ms
 5  gigabitethernet6-24.car2.bos1.Level3.net (63.211.176.17)  17.384 ms
20.025 ms  20.415 ms
 6  ae-5-5.ebr1.NewYork1.Level3.net (4.69.132.250)  28.679 ms  27.749 ms
25.022 ms
 7  ae-81-81.csw3.NewYork1.Level3.net (4.69.134.74)  28.837 ms
ae-91-91.csw4.NewYork1.Level3.net (4.69.134.78)  31.413 ms
ae-61-61.csw1.NewYork1.Level3.net (4.69.134.66)  22.518 ms
 8  ae-74-74.ebr4.NewYork1.Level3.net (4.69.134.117)  25.795 ms
ae-83-83.ebr3.NewYork1.Level3.net (4.69.134.105)  21.125 ms
ae-93-93.ebr3.NewYork1.Level3.net (4.69.134.109)  19.931 ms
 9  ae-3.ebr3.Washington1.Level3.net (4.69.132.89)  26.395 ms
ae-3.ebr4.Washington1.Level3.net (4.69.132.93)  26.157 ms
ae-3.ebr3.Washington1.Level3.net (4.69.132.89)  27.952 ms
10  ae-74-74.csw2.Washington1.Level3.net (4.69.134.182)  27.395 ms
ae-83-83.csw3.Washington1.Level3.net (4.69.134.170)  35.010 ms
ae-94-94.csw4.Washington1.Level3.net (4.69.134.190)  33.347 ms
11  ae-61-61.ebr1.Washington1.Level3.net (4.69.134.129)  26.157 ms
ae-71-71.ebr1.Washington1.Level3.net (4.69.134.133)  26.932 ms
ae-81-81.ebr1.Washington1.Level3.net (4.69.134.137)  26.572 ms
12  ae-4-4.car1.Cleveland1.Level3.net (4.69.132.193)  32.026 ms  32.630 ms
32.396 ms
13  ae-11-11.car2.Cleveland1.Level3.net (4.69.132.198)  32.929 ms  33.136 ms
35.418 ms
14  ROADRUNNER.car2.Cleveland1.Level3.net (4.78.59.46)  34.417 ms  34.816 ms
35.012 ms
15  gig15-0-0.ptldmeptl-rtr02.nyroc.rr.com (24.24.7.150)  42.779 ms  42.381
ms  46.577 ms
16  rrcs-24-39-3-2.nys.biz.rr.com (24.39.3.2)  49.243 ms  48.864 ms  48.490
ms
17  rrcs-24-39-50-36.nys.biz.rr.com (24.39.50.36)  51.890 ms  48.315 ms
51.254 ms
18  * * *
19  * * *
20  * * *
21  * * *
...

So, "the internet is broken". Routing problem somewhere between Germany and
the US?

Or... you're not doing fancy antispam based on RBLs or something are you,
that would just drop incoming tcp connections from 'suspicious' IPs?

If you hop on IRC, we can discuss further there.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1423.1355071304.16123.coreboot@coreboot.org>

"The OS driver initiates an ownership request by setting the OS Owned
semaphore to a one. The OS waits for the BIOS Owned bit to go to a zero
before attempting to use the EHCI controller. The time that OS must wait
for BIOS to respond to the request for ownership is beyond the scope of
this specification."

"If the BIOS has set SMI on OS Ownership Change in the USBLEGCTLSTS
register to a one, it receives an SMI when the OS Driver sets the OS
Owned semaphore to a one. BIOS observes that OS has changed the value of
the OS Owned bit..."

What happens if the BIOS doesn't relinquish control of the EHCI?  Does
hardware somehow prevent the OS from accessing the USB controller?  What
happens if the OS tries to use the USB controller without using these
semaphores at all? It seems to me that the OS can at least cause a
Denial-of-Service by sending commands to the USB controller, but I
suspect it can also eavesdrop on keyboard events.  Can anybody confirm
or deny this attack?

If this is outside the scope of coreboot, I'm sorry for bothering the list.

Thank you for your time,
-Jon




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1427.1355071304.16123.coreboot@coreboot.org>

I can confirm that PS/2 still does not work. Unfortunately I do not have a USB keyboard anymore; once I tested it did not work, too.

Is this a A8N-E topic only? All other mainboards with that superio are without such a problem?

The A8N-E boots with coreboot-v2 and I could reach a console over the serial port from a second computer.

Is anyone investigating this behaviour?

Unfortunately I do not have C programming skills yet. I promise to learn, but I assume to do research-programming a mainboard is just a much higher level.

So thanks for all the good work until now and any answers to my topic!
-- 
Psssst! Schon vom neuen GMX MultiMessenger geh?rt?
Der kann`s mit allen: http://www.gmx.net/de/go/multimessenger



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1436.1355071305.16123.coreboot@coreboot.org>

 tyan s2892
 tyan s2895
 sun ultra40
 
Since you've already tested an s2892, I'd be happy to supply a patch and you
can ack it? Same for s2895 - you have that hardware right?

Anyone got a sun ultra40 with sata problems to test this patch on?

Myles - have you ever run bonnie++ on your s2892 or s2895? Or noticed poor
sata performance? I'd really like to solve that multi-mode problem...

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1542.1355071318.16123.coreboot@coreboot.org>

your ethernet is using only one. For the USB to work, you probably
need all three of INTA, INTB, and INTC working. properly. For
ethernet, you only need the one hooked to the ethernet's INTA to work.



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1592.1355071325.16123.coreboot@coreboot.org>

likely more flexible.

-Kevin



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1695.1355071342.16123.coreboot@coreboot.org>

Space that gets eaten
 0___________________20___________________40____________________________________80
enter handle_17: a=00000178 b=00000008 c=00000040 d=000a0000
si=00005017 di=00000000
  ds=00001a49 es=00000040 ip=00003dd6 cs=00001000 f=00000206 r=00000c48
enter handle_17: a=00000200 b=00000008 c=00000040 d=000a0000
si=00005017 di=00000000
  ds=00001a49 es=00000040 ip=0000a2fc cs=00001000 f=00000206 r=00000c3e
enter handle_11: a=00000000 b=00000007 c=00000040 d=000a0000
si=00001338 di=00000000
  ds=00001a49 es=00005030 ip=0000412e cs=00001000 f=00000202 r=00000d06
KBD: int09h_handler(): unknown scancode read: 0x00000061!
DSsDSsDSsDSsfail_with_code floppy_13XX: a=00001505 b=00000001
c=0000000d d=000a5000 si=00005017 di=00000000
  ds=00001a49 es=00005040 ip=000055be cs=00001000 f=00000212 r=00000c02
Returning 00000001

Space that gets eaten
 0___________________20___________________40____________________________________80


From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1696.1355071342.16123.coreboot@coreboot.org>

Space that gets eaten
 0___________________20___________________40_________enter handle_11:
a=00000000 b=0000000c c=00000040 d=00040000 si=00001338 di=00000000
  ds=00001a49 es=00000040 ip=0000412e cs=00001000 f=00000246 r=00000d06
sendmouse: keyboard input buffer full

Thanks,
Myles



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1708.1355071345.16123.coreboot@coreboot.org>

general, debugging OS boot of a full installation is usually much
easier than trying to debug the installation process of an OS. There
are less obstacles to booting an already-installed image, and there
are much more tools available for debugging the aleady-installed OS.
Once you get that working, you can go back to debugging the CD.

It would be interesting to see if your platform has the same sort of
success that Kevin got on the epia. Maybe your different graphics
controller will work even better.



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1722.1355071346.16123.coreboot@coreboot.org>

it has limited size) in the boot block. That avoids any and all
requirements to keep code in RAM, thereby taking away the problem of
code relocation.

> In the case of the SMM handler, this would also confine us, because the
> actual SMI# handling code (written in C) would not be shared between
> CPUs but has to be duplicated for every CPU core. However, my current
> approach only keeps a very small amount of code per CPU, that is just
> enough to enter gcc compiled functions and return from them, cleanly.
>   

AFAIK factory BIOS SMM handlers have the ability to lock down the memory
segment they are using, protecting them from accidental or deliberate
tampering by the OS (which could lead to interesting security issues).
Can we do that even if the handler is "somewhere" in RAM?

> One of the questions in my mind is: where should we put the coreboot
> image, if we want to keep it around?
>
> A little excerpt from coreboot v2:
>
> I know the problem of where to put coreboot has been thought about
> before, elfboot() relocates coreboot to another place when loading an
> ELF binary that demands the space where coreboot lives:
>  * coreboot tries to load a segment and finds out, that it is in the way.
>  * coreboot copies itself to a new position
>  * coreboot jumps into the assembler handler in jmp_to_elf_entry at the
> new position
>  * coreboot tries to start the ELF binary.
>  * If it fails, it overwrites the loaded ELF binary by copying itself
> back and jumping to the original position.
>
> This is quite an interesting concept, but it also makes clear that the
> ram portion of coreboot itself ("stage2") can not be relocated freely in
> memory. Yet.
>   

Please see my other mail in this thread about possible problems with a
relocatable stage2. Besides that, we'd need a way in v3 to tag a LAR
member as PIC (sort of done for the special case of XIP in initram) and
new code to figure out a good load address during run time.

> Since we know how big our RAM is when we copy coreboot to RAM, I suggest
> that we copy coreboot to the end of memory and run it from there. It is
> a pretty good assumption that no payload will require that space. During
> memory map creation, we just reserve 256k at the upper end, and we're good.
>   

Hm... I assume end of memory is "end of memory below 4G". If we want to
avoid conflicts with mapped memory areas of extension cards, stage2 code
has to be loaded twice: Once before setting up extension cards (load
stage2 to above 1M or other failsafe location) and after setting up
extension cards (load stage2 to end of memory below 4G and below
extension card space). That's not exactly the nicest code flow I can
think of.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1810.1355071354.16123.coreboot@coreboot.org>

> +		if (memcmp(cmos_entry->name, name, len))
..

> +#define CB_TAG_OPTION         0x00c9
> +#define CMOS_MAX_NAME_LENGTH    32
> +struct cb_cmos_entries {
> +	u32 tag;
> +	u32 size;
> +	u32 bit;
> +	u32 length;
> +	u32 config;
> +	u32 config_id;
> +	u8 name[CMOS_MAX_NAME_LENGTH];
> +};

memcmp() expects char *

What should change? I'm thinking memcmp() and friends.


Later revisions breaks more stuff. :\


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.1922.1355071363.16123.coreboot@coreboot.org>

CPU core glued to an Intel 3100 northbridge/southbridge/SuperIO, with
a slightly fancier DDR2 memory controller. Thus my patches augment the
existing Intel 3100 code in coreboot.

The code was written using information in the datasheet available on
the Intel web site, and has been tested on an EP80579 Development
Board (codename "Truxton"), booting a Linux 2.6.25.1 kernel payload.

--Ed



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2041.1355071378.16123.coreboot@coreboot.org>

Use dev_path() to have nice debug output
patch is run-time tested

Trivial, thus:
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/devices/pci_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_device.c	2008-09-10 20:40:46 UTC (rev 3571)
+++ trunk/coreboot-v2/src/devices/pci_device.c	2008-09-11 06:52:22 UTC (rev 3572)
@@ -923,7 +923,7 @@
 		if (	(id == 0xffffffff) || (id == 0x00000000) ||
 			(id == 0x0000ffff) || (id == 0xffff0000))
 		{
-			printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
+			printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
 			return NULL;
 		}
 		dev = alloc_dev(bus, &dummy.path);




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2042.1355071378.16123.coreboot@coreboot.org>

Use dev_path() to have nice debug output
patch is run-time tested

Trivial, thus:
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3572&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3572&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2138.1355071388.16123.coreboot@coreboot.org>

SIO and the HW monitoring chip. I'll doublecheck for other devices (and 
serial config ROMs) in the evening, but I don't have much hope.

>> Excerpt from lspci -vvnnxx I've got lying around:
>
> Would be nice to see the full output.

Here you go. Note that the VGA and ethernet are PCI cards, not onboard.

Kind regards,
 	Tim.


00:00.0 Host bridge [0600]: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge [8086:7190] (rev 03)
 	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
 	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
 	Latency: 64
 	Region 0: Memory at e0000000 (32-bit, prefetchable) [size=64M]
 	Capabilities: [a0] AGP version 1.0
 		Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2
 		Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none>
 	Kernel driver in use: agpgart-intel
 	Kernel modules: intel-agp
00: 86 80 90 71 06 00 10 22 03 00 00 06 00 40 00 00
10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 0c aa 00 ff 00 00 00 09 03 10 11 01 00 00 00 00
60: 00 08 10 18 28 28 28 28 00 2f 00 f0 03 ca 00 00
70: 20 1f 0a 78 54 02 03 01 27 ff 10 38 00 00 00 00
80: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 98 88 00 00 04 61 00 00 00 05 00 00 00 00 00 00
a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00
b0: 80 20 00 00 30 00 00 00 00 00 4d 13 20 10 00 00
c0: 00 00 00 00 00 00 00 00 18 0c 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00
e0: 4c ad ff bb 8a 3e 00 80 2c d3 f7 cf 9d 3e 00 00
f0: 40 01 00 00 00 f8 00 60 20 0f 00 00 00 00 00 00

00:01.0 PCI bridge [0604]: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge [8086:7191] (rev 03)
 	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
 	Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
 	Latency: 64
 	Bus: primary=00, secondary=01, subordinate=01, sec-latency=64
 	I/O behind bridge: 0000d000-0000dfff
 	Memory behind bridge: e4000000-e5ffffff
 	Prefetchable memory behind bridge: e6000000-e7ffffff
 	Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
 	BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B+
 		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
 	Kernel modules: shpchp
00: 86 80 91 71 07 01 20 02 03 00 04 06 00 40 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 40 d0 d0 a0 22
20: 00 e4 f0 e5 00 e6 f0 e7 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:07.0 ISA bridge [0601]: Intel Corporation 82371AB/EB/MB PIIX4 ISA [8086:7110] (rev 02)
 	Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
 	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
 	Latency: 0
00: 86 80 10 71 0f 00 80 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 4d 00 20 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 8b 80 80 0a d0 00 00 00 00 f2 80 00 00 00 00 00
70: 00 00 00 00 00 00 0c 0c 00 00 00 00 00 00 00 00
80: 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 05 01 01 e0 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 21 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00

00:07.1 IDE interface [0101]: Intel Corporation 82371AB/EB/MB PIIX4 IDE [8086:7111] (rev 01) (prog-if 80 [Master])
 	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
 	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
 	Latency: 64
 	Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8]
 	Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1]
 	Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8]
 	Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1]
 	Region 4: I/O ports at f000 [size=16]
 	Kernel driver in use: PIIX_IDE
 	Kernel modules: piix
00: 86 80 11 71 05 00 80 02 01 80 01 01 00 40 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 07 a3 00 80 00 00 00 00 01 00 02 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00

00:07.2 USB Controller [0c03]: Intel Corporation 82371AB/EB/MB PIIX4 USB [8086:7112] (rev 01)
 	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
 	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
 	Latency: 64
 	Interrupt: pin D routed to IRQ 10
 	Region 4: I/O ports at e000 [size=32]
 	Kernel driver in use: uhci_hcd
 	Kernel modules: uhci-hcd
00: 86 80 12 71 05 00 80 02 01 00 03 0c 00 40 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 04 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00

00:07.3 Bridge [0680]: Intel Corporation 82371AB/EB/MB PIIX4 ACPI [8086:7113] (rev 02)
 	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
 	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
 	Interrupt: pin ? routed to IRQ 9
 	Kernel driver in use: piix4_smbus
 	Kernel modules: i2c-piix4
00: 86 80 13 71 03 00 80 02 02 00 80 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 58 1f 00 00 00 00 00 07 00 00 02 00 00 00 00
60: 94 02 83 00 00 00 00 10 00 00 00 00 00 00 00 00
70: 04 40 11 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 01 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 09 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00

00:11.0 Ethernet controller [0200]: National Semiconductor Corporation DP83815 (MacPhyter) Ethernet Controller [100b:0020]
 	Subsystem: National Semiconductor Corporation DP83815 (MacPhyter) Ethernet Controller [100b:0020]
 	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
 	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
 	Latency: 64 (2750ns min, 13000ns max)
 	Interrupt: pin A routed to IRQ 10
 	Region 0: I/O ports at e400 [size=256]
 	Region 1: Memory at e9000000 (32-bit, non-prefetchable) [size=4K]
 	Expansion ROM at e8000000 [disabled] [size=64K]
 	Capabilities: [40] Power Management version 2
 		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=320mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
 		Status: D0 PME-Enable- DSel=0 DScale=0 PME+
 	Kernel driver in use: natsemi
 	Kernel modules: natsemi
00: 0b 10 20 00 07 00 90 02 00 00 00 02 00 40 00 00
10: 01 e4 00 00 00 00 00 e9 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 0b 10 20 00
30: 00 00 00 e8 40 00 00 00 00 00 00 00 0a 01 0b 34
40: 01 00 82 ff 00 80 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01:00.0 VGA compatible controller [0300]: nVidia Corporation NV5 [RIVA TNT2/TNT2 Pro] [10de:0028] (rev 15)
 	Subsystem: ASUSTeK Computer Inc. Device [1043:4000]
 	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
 	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
 	Latency: 64 (1250ns min, 250ns max)
 	Interrupt: pin A routed to IRQ 11
 	Region 0: Memory at e4000000 (32-bit, non-prefetchable) [size=16M]
 	Region 1: Memory at e6000000 (32-bit, prefetchable) [size=32M]
 	Expansion ROM at e5000000 [disabled] [size=64K]
 	Capabilities: [60] Power Management version 1
 		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
 		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
 	Capabilities: [44] AGP version 2.0
 		Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA- ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
 		Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none>
 	Kernel modules: nvidiafb
00: de 10 28 00 07 00 b0 02 15 00 00 03 00 40 00 00
10: 00 00 00 e4 08 00 00 e6 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 00 40
30: 00 00 00 e5 60 00 00 00 00 00 00 00 0b 01 05 01
40: 43 10 00 40 02 00 20 00 07 00 00 1f 00 00 00 00
50: 01 00 00 00 01 00 00 00 ce d6 23 00 0f 00 00 00
60: 01 44 01 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2212.1355071397.16123.coreboot@coreboot.org>

onto LPC in steps of 64k, meaning that you will be able to use as
large a flash chip as you can find.

I suggest trying to find one of two SST flash chips;

SST49LF016C-33-4C-NHE
or
SST49LF160C-33-4C-NHE

(66 instead of 33 is fine, but N in NHE means PLCC so is important)

If I remember correctly, one is LPC only and the other is combined
FWH/LPC, but I would like someone else to confirm this.

The data sheets on these two parts are unfortunately not at all
helpful.

These parts are both 16Mbit = 2Mbyte so you'll have some room for
using a Linux kernel as payload.


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2249.1355071403.16123.coreboot@coreboot.org>

the v3 printk at the moment because I've not reviewed r921 yet.

Oh, and please be aware that any multicore/multiprocessor machine in v3
is completely BROKEN right now and has been that way for months. (Yes, I
have a fix in the queue. Remind me in a few days.)

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2272.1355071407.16123.coreboot@coreboot.org>

<uwe___> we'll need 'superiotool -dV' output, 'getpir' output (a file called
irq_table.c), 'mptable' output, maybe others

Done!

See attachments.

2008/10/12 razor1394 <razor1394 at gmail.com>

> Hello
>
> I'm really interested in putting Coreboot on my firmware chip but I'm not
> entirely sure it will work. My motherboard is on the desktop candidates list
> which is good news I presume.
>
> I've attached output of some hardware info commands. Super I/O is ITE
> IT8712F. The bios chip is removable and I have 5 spare. It says:
>
> SST
> 49LF004B
> 0446053-C
>
> Some questions...
>
> Can you have bluetooth compiled inside the kernel of Coreboot? I was
> thinking of using bluetooth keyboards to access firmware settings. This is
> something that BIOS does not let me. Only thing that works on my computer is
> PS/2 and USB.
>
> Thanks.
>
>
> --
> RaZoR1394
>



-- 
RaZoR1394

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Some more info.<br><br>From irc:<br><br><div style="margin-left: 40px;">&lt;uwe___&gt; we&#39;ll need &#39;superiotool -dV&#39; output, &#39;getpir&#39; output (a file called irq_table.c), &#39;mptable&#39; output, maybe others<br>
<br></div>Done!<br><br>See attachments.<br><br><div class="gmail_quote">2008/10/12 razor1394 <span dir="ltr">&lt;<a href="mailto:razor1394 at gmail.com">razor1394 at gmail.com</a>&gt;</span><br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div dir="ltr">Hello<br><br>I&#39;m really interested in putting Coreboot on my firmware chip but I&#39;m not entirely sure it will work. My motherboard is on the desktop candidates list which is good news I presume.<br><br>

I&#39;ve attached output of some hardware info commands. Super I/O is ITE
 IT8712F. The bios chip is removable and I have 5 spare. It says:<br><br>SST<br clear="all">49LF004B<br>0446053-C<br><br>Some questions...<br><br>Can you have bluetooth compiled inside the kernel of Coreboot? I was thinking of using bluetooth keyboards to access firmware settings. This is something that BIOS does not let me. Only thing that works on my computer is PS/2 and USB.<br>

<br>Thanks.<br><br><br>-- <br>RaZoR1394<br>
</div>
</blockquote></div><br><br clear="all"><br>-- <br>RaZoR1394<br>

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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2312.1355071411.16123.coreboot@coreboot.org>

   memset(dev, 0, sizeof(*dev));
    dev->path = *path;
    dev->id = *devid;

    /* Initialize the back pointers in the link fields. */
    for (link = 0; link < MAX_LINKS; link++) {
        dev->link[link].dev = dev;
        dev->link[link].link = link;
    }

    /* By default devices are enabled. */
    dev->enabled = 1;

    /* Add the new device to the list of children of the bus. */
    dev->bus = parent;
    if (child) {
        child->sibling = dev;
    } else {
        parent->children = dev;
    }

    /* Append a new device to the global device list.
     * The list is used to find devices once everything is set up.
     */
    *last_dev_p = dev;
    last_dev_p = &dev->next;

    /* Give the device a name. */
    sprintf(dev->dtsname, "dynamic %s", dev_path(dev));

    /* Run the device specific constructor as last part of the chain
     * so it gets the chance to overwrite the "inherited" values above
     */

    constructor(dev);

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<div dir="ltr">Why do we call the constructor function of a new device?&nbsp;&nbsp; I can&#39;t see where we ever set it.<br>Thanks,<br>Myles <br><br>From device/device.c:<br><br>&nbsp;&nbsp; memset(dev, 0, sizeof(*dev));<br>&nbsp;&nbsp;&nbsp; dev-&gt;path = *path;<br>
&nbsp;&nbsp;&nbsp; dev-&gt;id = *devid;<br><br>&nbsp;&nbsp;&nbsp; /* Initialize the back pointers in the link fields. */<br>&nbsp;&nbsp;&nbsp; for (link = 0; link &lt; MAX_LINKS; link++) {<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; dev-&gt;link[link].dev = dev;<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; dev-&gt;link[link].link = link;<br>
&nbsp;&nbsp;&nbsp; }<br><br>&nbsp;&nbsp;&nbsp; /* By default devices are enabled. */<br>&nbsp;&nbsp;&nbsp; dev-&gt;enabled = 1;<br><br>&nbsp;&nbsp;&nbsp; /* Add the new device to the list of children of the bus. */<br>&nbsp;&nbsp;&nbsp; dev-&gt;bus = parent;<br>&nbsp;&nbsp;&nbsp; if (child) {<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; child-&gt;sibling = dev;<br>
&nbsp;&nbsp;&nbsp; } else {<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; parent-&gt;children = dev;<br>&nbsp;&nbsp;&nbsp; }<br><br>&nbsp;&nbsp;&nbsp; /* Append a new device to the global device list.<br>&nbsp;&nbsp;&nbsp; &nbsp;* The list is used to find devices once everything is set up.<br>&nbsp;&nbsp;&nbsp; &nbsp;*/<br>&nbsp;&nbsp;&nbsp; *last_dev_p = dev;<br>
&nbsp;&nbsp;&nbsp; last_dev_p = &amp;dev-&gt;next;<br><br>&nbsp;&nbsp;&nbsp; /* Give the device a name. */<br>&nbsp;&nbsp;&nbsp; sprintf(dev-&gt;dtsname, &quot;dynamic %s&quot;, dev_path(dev));<br><br>&nbsp;&nbsp;&nbsp; /* Run the device specific constructor as last part of the chain<br>
&nbsp;&nbsp;&nbsp; &nbsp;* so it gets the chance to overwrite the &quot;inherited&quot; values above<br>&nbsp;&nbsp;&nbsp; &nbsp;*/<br><br>&nbsp;&nbsp;&nbsp; constructor(dev);<br></div>

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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2314.1355071411.16123.coreboot@coreboot.org>

19.[0123] and other processor devices all live on PCI bus 0? Is that bus
somewhat related to the buses attached via ncHT? IIRC I once saw a
machine where 18.[0123] was alone on bus 0 and all other PCI devices
were on separate buses.

Taking the "everything is PCI" model, how would I specify the virtual
PCI buses attached via ncHT? Are they children (secondary buses) of 18.0
which would act like a PCI-to-PCI bridge?


> The dts should be easy for people to fill in to make a platform work.

Agreed.


> They don't know (or need to know) what ht links are connecting the cpu
> and what ones go to pci bus.

They need a way to specify settings for any given PCI device. Since most
modern machines have multiple PCI devices with the same vendor/device
ID, we have to be able to identify devices based on their logical path.
For that, we have to model the logical PCI bus/device/tree reasonably
well. I'm trying to do that, but no model seems to fit.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2320.1355071413.16123.coreboot@coreboot.org>

right. I may be wrong but I am not sure all those issues are being
taken into consideration.

A writeup of all this by a person who'd never looked at it before
would be really useful. Why? because they won't take things for
granted -- they'll look at it with a fresh perspective.

Stefan and I are going to walk this stuff as well.

ron



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2321.1355071413.16123.coreboot@coreboot.org>

congruent with the logical PCI tree, but they differ significantly in a
few places. It is desirable to have both trees available: One for
resource allocation, one for device discovery. Killing either is calling
for problems down the road. Besides that, in reality we're neither
dealing with a real tree nor a completely acyclic graph.
There are easy ways out which either make the dts completely unreadable
or beget some unholy device tree code. Neither is acceptable if we
consider maintainability to be important.

The good thing is that my diploma thesis provides solutions for exactly
that class of problems. It's not about coreboot, but the problems we
face right now are so strikingly similar that I regret not writing the
whole thing in English. Anyway, I'll try to create a short writeup which
captures the essential results, and how to apply them without losing
mental sanity (or maintainability, for that matter).

The trick is to declare a preferred and readable form for storing device
relations (the existing dts structure works quite well in that regard)
and to handle different requirements for that representation like
database views. With a nice set of node properties and the right amount
of abstraction, we can keep both the code and the dts human readable and
have them provide easily understood views of their respective purposes
(resource allocation vs. device discovery). If we do it right, even such
horrors as wandering PATA/SATA PCI devices (after disabling PATA, SATA
will change its PCI devfn) are easily expressed and handled.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2362.1355071420.16123.coreboot@coreboot.org>

memory smaller than a page, and failing.  It would be helpful if you posted
your command line and the complete output.  Probably the output of
./flashrom -V too.

 

Thanks,

Myles

 

  _____  

From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
On Behalf Of Collin Gregory
Sent: Friday, October 31, 2008 2:17 PM
To: coreboot at coreboot.org
Subject: [coreboot] Flashrom problem

 

Hello everyone,

I'm a newbies in coreboot installation but not in linux, hopefully :)
When i'm launching flashrom, i get this error message :

Can't mmap memory using /dev/mem : Invalid ARgument ...

Does anyone knows what does it means ?

My motherboard is the D945gclf with these technical informations :

- Soldered-down IntelR AtomR processor 230 with a 533 MHz system bus
- IntelR 945GC Chipset, consisting of:

. IntelR 82945GC Graphics Memory Controller Hub (GMCH)

. IntelR 82801GB I/O Controller Hub (ICH7)

- Realtek* ALC662 for the sound chipset
- IntelR GMA950 onboard graphics subsystem Video
- SMSC LPC47M997 based Legacy I/O controller for hardware management,
serial, parallel, and PS/2* ports
- Realtek RTL8102EL LAN adapter device

Thanks for your help !!!!

Greg


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<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'>From the comment in flashrom.c, it =
looks
like flashrom is trying to allocate memory smaller than a page, and =
failing.&nbsp;
It would be helpful if you posted your command line and the complete =
output.&nbsp;
Probably the output of ./flashrom &#8211;V =
too.<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'><o:p>&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'>Thanks,<o:p></o:p></span></font></p>=


<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'>Myles<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'><o:p>&nbsp;</o:p></span></font></p>

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<p class=3DMsoNormal><b><font size=3D2 face=3DTahoma><span =
style=3D'font-size:10.0pt;
font-family:Tahoma;font-weight:bold'>From:</span></font></b><font =
size=3D2
face=3DTahoma><span style=3D'font-size:10.0pt;font-family:Tahoma'>
coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] =
<b><span
style=3D'font-weight:bold'>On Behalf Of </span></b>Collin Gregory<br>
<b><span style=3D'font-weight:bold'>Sent:</span></b> Friday, October 31, =
2008
2:17 PM<br>
<b><span style=3D'font-weight:bold'>To:</span></b> =
coreboot at coreboot.org<br>
<b><span style=3D'font-weight:bold'>Subject:</span></b> [coreboot] =
Flashrom
problem</span></font><o:p></o:p></p>

</div>

<p class=3DMsoNormal><font size=3D3 face=3D"Times New Roman"><span =
style=3D'font-size:
12.0pt'><o:p>&nbsp;</o:p></span></font></p>

<p class=3DMsoNormal><font size=3D3 face=3D"Times New Roman"><span =
style=3D'font-size:
12.0pt'>Hello everyone,<br>
<br>
I'm a newbies in coreboot installation but not in linux, hopefully =
:)<br>
When i'm launching flashrom, i get this error message :<br>
<br>
Can't mmap memory using /dev/mem : Invalid ARgument ...<br>
<br>
Does anyone knows what does it means ?<br>
<br>
My motherboard is the D945gclf with these technical informations :<br>
<br>
- Soldered-down Intel&reg; Atom&reg; processor 230 with a 533 MHz system =
bus<br>
- Intel&reg; 945GC Chipset, consisting of:<o:p></o:p></span></font></p>

<div style=3D'margin-left:30.0pt'>

<p class=3DMsoNormal><font size=3D3 face=3D"Times New Roman"><span =
style=3D'font-size:
12.0pt'>&#8226; Intel&reg; 82945GC Graphics Memory Controller Hub =
(GMCH)<o:p></o:p></span></font></p>

</div>

<div style=3D'margin-left:30.0pt'>

<p class=3DMsoNormal><font size=3D3 face=3D"Times New Roman"><span =
style=3D'font-size:
12.0pt'>&#8226; Intel&reg; 82801GB I/O Controller Hub =
(ICH7)<o:p></o:p></span></font></p>

</div>

<p class=3DMsoNormal><font size=3D3 face=3D"Times New Roman"><span =
style=3D'font-size:
12.0pt'>- Realtek* ALC662 for the sound chipset<br>
- Intel&reg; GMA950 onboard graphics subsystem Video<br>
- SMSC LPC47M997 based Legacy I/O controller for hardware management, =
serial,
parallel, and PS/2* ports<br>
- Realtek RTL8102EL LAN adapter device<br>
<br>
Thanks for your help !!!!<br>
<br>
Greg<o:p></o:p></span></font></p>

</div>

</div>

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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2377.1355071423.16123.coreboot@coreboot.org>

3.1 Configuration Space Accesses
The AMD Athlon=99 64 and AMD Opteron=99 Processors implement configuration =
space
as defined in
the PCI Local Bus Specification, Rev. 2.2, and the HyperTransport=99 I/O Li=
nk
Specification, Rev.
1.03.

I read that to mean that even though the processor reports Rev 1.02, it's
1.03.

Thanks,
Myles

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<br><br><div class=3D"gmail_quote">On Fri, Oct 24, 2008 at 9:21 AM, Carl-Da=
niel Hailfinger <span dir=3D"ltr">&lt;<a href=3D"mailto:c-d.hailfinger.deve=
l.2006 at gmx.net">c-d.hailfinger.devel.2006 at gmx.net</a>&gt;</span> wrote:<br>=
<blockquote class=3D"gmail_quote" style=3D"border-left: 1px solid rgb(204, =
204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div class=3D"Ih2E3d">On 24.10.2008 17:13, Carl-Daniel Hailfinger wrote:<br=
>
&gt; Hi,<br>
&gt;<br>
&gt; I&#39;m getting the following message from lspci on my K8 machine:<br>
&gt;<br>
&gt; 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8<br>
&gt; [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100]=
<br>
&gt; &nbsp; &nbsp; &nbsp; &nbsp; Control: I/O- Mem- BusMaster- SpecCycle- M=
emWINV- VGASnoop-<br>
&gt; ParErr- Stepping- SERR- FastB2B- DisINTx-<br>
&gt; &nbsp; &nbsp; &nbsp; &nbsp; Status: Cap+ 66MHz- UDF- FastB2B- ParErr- =
DEVSEL=3Dfast &gt;TAbort-<br>
&gt; &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- INTx-<br>
&gt; &nbsp; &nbsp; &nbsp; &nbsp; Capabilities: [80] HyperTransport: Host or=
 Secondary Interface<br>
&gt; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; !!! Possibly i=
ncomplete decoding for revision 1.02<br>
&gt; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; Command: WarmR=
st+ DblEnd-<br>
&gt; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; Link Control: =
CFlE- CST- CFE- &lt;LkFail- Init+ EOC- TXO-<br>
&gt; &lt;CRCErr=3D0<br>
&gt; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; Link Config: M=
LWI=3D16bit MLWO=3D16bit LWI=3D16bit LWO=3D16bit<br>
&gt; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; Revision ID: 1=
.02<br>
&gt; &nbsp; &nbsp; &nbsp; &nbsp; Kernel modules: ipmi_si<br>
&gt;<br>
</div><div class=3D"Ih2E3d">&gt; Note the warning about &quot;Possibly inco=
mplete decoding&quot; which stems from<br>
&gt; the fact that the processor mentions HT revision 1.02 which is the las=
t<br>
&gt; non-public revision. Every revision from 1.03 and beyond seems to be<b=
r>
&gt; publically available. Now the big question is: Can we decode HT 1.02<b=
r>
&gt; like HT 1.03 or have there been fundamental changes in between? I&#39;=
d like<br>
&gt; to create a patch for PCIutils (lspci) so we can have full info withou=
t<br>
&gt; a warning message.<br></div></blockquote><div><br>From the BKDG:<br>3.=
1 Configuration Space Accesses<br>The AMD Athlon=99 64 and AMD Opteron=99 P=
rocessors implement configuration space as defined in<br>the PCI Local Bus =
Specification, Rev. 2.2, and the HyperTransport=99 I/O Link Specification, =
Rev.<br>
1.03.<br><br>I read that to mean that even though the processor reports Rev=
 1.02, it&#39;s 1.03.<br><br>Thanks,<br>Myles <br></div></div><br>

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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2386.1355071425.16123.coreboot@coreboot.org>

const struct pci_bus_operations *pci_check_direct(void)
{
    unsigned int tmp;

    /*
     * Check if configuration type 1 works.
     */
    {
        outb(0x01, 0xCFB);
        tmp = inl(0xCF8);
        outl(0x80000000, 0xCF8);
        if ((inl(0xCF8) == 0x80000000) &&
            pci_sanity_check(&pci_cf8_conf1))
        {
            outl(tmp, 0xCF8);
            printk(BIOS_DEBUG, "PCI: Using configuration type 1\n");
            return &pci_cf8_conf1;
        }
        outl(tmp, 0xCF8);
    }

    die("pci_check_direct failed\n");
    return NULL;
}

/** Set the method to be used for PCI, type I or type II
 */
void pci_set_method(struct device * dev)
{
    printk(BIOS_INFO, "Finding PCI configuration type.\n");
    dev->ops->ops_pci_bus = pci_check_direct();
    post_code(POST_STAGE2_PHASE2_PCI_SET_METHOD);
}

Here are the interesting things:
1. pci_check_direct either returns pci_cfg8_conf1 or dies
2. This code is only used by geodelx

I think the const struct is the right way to do this.  Can we change these
functions?

Two solutions:
1. Set the entire ops
2. Initialize it correctly and die if the check fails

Comments?

Thanks,
Myles

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<br><br><div class="gmail_quote">On Wed, Nov 5, 2008 at 1:24 PM, Myles Watson <span dir="ltr">&lt;<a href="mailto:mylesgw at gmail.com">mylesgw at gmail.com</a>&gt;</span> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div class="Ih2E3d">&gt; Are you testing these on qemu I assume?<br>
<br>
</div>I can. &nbsp;I don&#39;t think I&#39;ve made any functional changes, but it&#39;s probably<br>
good to check.<br>
<br>
Most of this patch isn&#39;t exercised by qemu, though. &nbsp;There are no bridges<br>
which are not in the dts.<font color="#888888"><br>
</font></blockquote></div><br>It turns out that I forgot the importance of make clean for build testing.&nbsp; I wish I knew better how to fix the dependencies.<br><br>This breaks the build now that I made the change for the pci_ops structs to be const.<br>
<br>From pci_ops_auto.c:<br>const struct pci_bus_operations *pci_check_direct(void)<br>{<br>&nbsp;&nbsp;&nbsp; unsigned int tmp;<br><br>&nbsp;&nbsp;&nbsp; /*<br>&nbsp;&nbsp;&nbsp; &nbsp;* Check if configuration type 1 works.<br>&nbsp;&nbsp;&nbsp; &nbsp;*/<br>&nbsp;&nbsp;&nbsp; {<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; outb(0x01, 0xCFB);<br>
&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; tmp = inl(0xCF8);<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; outl(0x80000000, 0xCF8);<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; if ((inl(0xCF8) == 0x80000000) &amp;&amp; <br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; pci_sanity_check(&amp;pci_cf8_conf1)) <br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; {<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; outl(tmp, 0xCF8);<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; printk(BIOS_DEBUG, &quot;PCI: Using configuration type 1\n&quot;);<br>
&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; return &amp;pci_cf8_conf1;<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; }<br>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; outl(tmp, 0xCF8);<br>&nbsp;&nbsp;&nbsp; }<br><br>&nbsp;&nbsp;&nbsp; die(&quot;pci_check_direct failed\n&quot;);<br>&nbsp;&nbsp;&nbsp; return NULL;<br>}<br><br>/** Set the method to be used for PCI, type I or type II<br>
&nbsp;*/<br>void pci_set_method(struct device * dev)<br>{<br>&nbsp;&nbsp;&nbsp; printk(BIOS_INFO, &quot;Finding PCI configuration type.\n&quot;);<br>&nbsp;&nbsp;&nbsp; dev-&gt;ops-&gt;ops_pci_bus = pci_check_direct();<br>&nbsp;&nbsp;&nbsp; post_code(POST_STAGE2_PHASE2_PCI_SET_METHOD);<br>
}<br><br>Here are the interesting things:<br>1. pci_check_direct either returns pci_cfg8_conf1 or dies<br>2. This code is only used by geodelx<br><br>I think the const struct is the right way to do this.&nbsp; Can we change these functions?<br>
<br>Two solutions:<br>1. Set the entire ops<br>2. Initialize it correctly and die if the check fails<br><br>Comments?<br><br>Thanks,<br>Myles<br>

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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2410.1355071430.16123.coreboot@coreboot.org>

v2 auto.c did this. Things were set up just enough that the basic
legacy devices worked. Note that config space doesn't change later --
just some basic routing. So if the subtractive path doesn't get messed
up, and no other resource positively decodes this, we're ok.

Let's not  bring the IOINDEX_SUBTRACTIVE resources into this
discussion -- I did that already and it got me into trouble. The
SUBTRACTIVE name in the resource code is misleading IMHO.

ron



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2525.1355071445.16123.coreboot@coreboot.org>

size are serial flash chips, and the ones with non-uniform size are
parallel flash chips. I propose a new design the 'flashchip'
structure. In this new design, serial and parallel flash chip
information is stored in 'serial_flashchip' and 'parallel_flashchip'
seperately, with a common 'flashchip_common' internal struct as their
first field.


serial_flashchip
+------------------+------------------------------+
| flashchip_common | sector_size, block_size, ... |
+------------------+------------------------------+

parallel_flashchip
+------------------+------------------------------+
| flashchip_common | erase_block	       	  |
+------------------+------------------------------+

'flashchip_common' contains names, id's and common operation functions.

The design above looks clearer. And There is another advantage.

I guess(confirm and disproof welcome) one chipset only provides one of
the two flash interface. When a chipset is detected, we can probe only
one kind of them, (hopefully) faster and safer. It is ok if we want to
probe the other kind.


> Index: flashrom-eraseblocks/flashrom.c
> ===================================================================
> --- flashrom-eraseblocks/flashrom.c     (Revision 3776)
> +++ flashrom-eraseblocks/flashrom.c     (Arbeitskopie)
> @@ -534,11 +534,33 @@
>
>        if (erase_it) {
>                printf("Erasing flash chip.\n");
> -               if (!flash->erase) {
> -                       fprintf(stderr, "Error: flashrom has no erase function for this flash chip.\n");
> +               if (!flash->block_erase && flash->eraseblocks[0].count) {
> +                       fprintf(stderr, "Hint: flashrom knows the eraseblock "
> +                               "layout, but there is no blockwise erase "
> +                               "function for this flash chip. "
> +                               "Using whole-chip erase.\n");
> +               }
> +               if (flash->block_erase && !flash->eraseblocks[0].count) {
> +                       fprintf(stderr, "Hint: flashrom has a blockwise erase "
> +                               "function for this flash chip, but the "
> +                               "eraseblock layout is unknown. "
> +                               "Using whole-chip erase.\n");
> +               }
> +               if (flash->block_erase && flash->eraseblocks[0].count) {
> +                       unsigned long done = 0;
> +                       int i, j;
> +                       for (i = 0; done < flash->total_size * 1024; i++) {
> +                               for (j = 0; j < flash->eraseblocks[i].count; j++) {
> +                                       flash->block_erase(flash, done + flash->eraseblocks[i].size * j);
> +                               }
> +                               done += flash->eraseblocks[i].count * flash->eraseblocks[i].size;
> +                       }
> +               } else if (flash->erase) {
> +                       flash->erase(flash);
> +               } else {
> +                       fprintf(stderr, "Error: flashrom has no chip erase function for this flash chip.\n");
>                        return 1;
>                }
> -               flash->erase(flash);
>                exit(0);
>        } else if (read_it) {
>                if ((image = fopen(filename, "w")) == NULL) {

No comment to the logic. But the new code has a different degree of
detail compared to other 'if (do_it)' blocks(i.e., the for loop).

yu ning



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2541.1355071447.16123.coreboot@coreboot.org>

<quote>
LV2 ??? Level 2 Register
I/O Address: PMBASE + 14h
...
Reads to this register return all 0s, writes to this register have no
effect. Reads to this
register generate a ???enter a level 2 power state??? (C2) to the clock
control logic. This will
cause the STPCLK# signal to go active, and stay active until a break
event occurs.
Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.
...
NOTE: This register should not be used by IA-64 processors or systems
with more than 1 logical
      processor, unless appropriate semaphoring software has been put in
place to ensure that
      all threads/processors are ready for the C2 state when the read to
this register occurs.
</quote>

The subsequent byte registers are LV3, LV4, LV5 and for mobile version
LV6 intended for entering C3, C4, C5 and C6 states.

-- 
Andriy Gapon



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2554.1355071449.16123.coreboot@coreboot.org>

the parallel port. 

One way is to use /dev/parportX. The /dev/parportX method is a higher level
driver. I'm still looking into this to see if it will be better. I think
Stefan was referring to the parport_find_base() function which wouldn't
work for me. For that you input a base address and it returns the
corresponding parallel port.

The other method is directly controlling the I/O. It is a lower level
driver directly accessing the hardware. It is supposed to be faster, which
will be good for flashing. It is also very simple, using outb and inb. This
is the method I prefer. But it seems in all the examples I have looked at
the the base address is statically defined. That is what I am trying to do
is automate that.


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2555.1355071449.16123.coreboot@coreboot.org>

the parallel port.

One way is to use /dev/parportX. The /dev/parportX method is a higher level
driver. I'm still looking into this to see if it will be better. I think
Stefan was referring to the parport_find_base() function which wouldn't
work for me. For that you input a base address and it returns the
corresponding parallel port.

The other method is directly controlling the I/O. It is a lower level
driver directly accessing the hardware. It is supposed to be faster, which
will be good for flashing. It is also very simple, using outb and inb. This
is the method I prefer. But it seems in all the examples I have looked at
the the base address is statically defined. That is what I am trying to do
is automate that.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2570.1355071453.16123.coreboot@coreboot.org>

Celeron M (4xx) Processor
FSB 667MHz
Socket M

It is just in a different package, It supports the Socket (M) uFCBGA
PBGA479 (mobile) processor. Not the LGA775.

Should that matter???

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2584.1355071458.16123.coreboot@coreboot.org>

L1 Cache:  128K   3265 MB/s
Memory  :  480M    240 MB/s

That's right, faster then v2 :) I've managed to coerce the northbridge into
running the memory at 200MHz (DDR400) without locking up the system like it
does in v2, and also to use 1GB of ram, which the fuctory BIOS only sees as
512MB, and v2 for some reason trips over. However, it's a mixed blessing,
even though memtest86 now runs at an acceptable speed, coreboot is still
running fairly slowly. I'm attaching a patch that brings over mtrr.c from v2
and hacks it to work with v3, but no sign-off because IMO it's not ready to
be committed. I'll try booting a FILO payload and a kernel tomorrow, but
right now it's time for some sleep.

-Corey

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On Wed, Dec 17, 2008 at 11:04 PM, Corey Osgood <span dir="ltr">&lt;<a href="mailto:corey.osgood at gmail.com">corey.osgood at gmail.com</a>&gt;</span> wrote:<br><div class="gmail_quote"><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div class="Ih2E3d">On Wed, Dec 17, 2008 at 8:55 PM, Peter Stuge <span dir="ltr">&lt;<a href="mailto:peter at stuge.se" target="_blank">peter at stuge.se</a>&gt;</span> wrote:<br></div><div class="gmail_quote"><div class="Ih2E3d">
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div>Corey Osgood wrote:<br>
&gt; would there be any problem with calling functions to enable mtrrs<br>
&gt; and the cache (if it&#39;s not already) from the end of disable_car()?<br>
<br>
</div>None whatsoever. Commit at will.<font color="#888888"></font></blockquote></div><div><br>It didn&#39;t help, disable_car() already does essentially the same thing; disable cache, enable mtrrs, re-enable cache. I&#39;m comparing memtest between the stock bios and coreboot right now, the throughput for the stock bios is 6122MB/s for L1 cache and 574MB/s for memory. With v2, it&#39;s 3265 and 191, respectively (using ROMCC), with v3 it&#39;s 15 and 18. So something&#39;s not right somewhere. The other thing is that in v2 and v3, the CPU is only running at 800MHz in memtest, but with the stock BIOS it runs at 1.5GHz, that&#39;s probably the reason for the differing cache throughputs. Anyways, I&#39;m diving into both v2 and v3 and trying to track down why this is running so slowly.</div>
</div></blockquote><div><br>&lt;insert happy dance here&gt;<br><br>From the currently-running memtest86 on coreboot-v3:<br></div></div>L1 Cache:&nbsp; 128K&nbsp;&nbsp; 3265 MB/s<br>Memory&nbsp; :&nbsp; 480M&nbsp;&nbsp;&nbsp; 240 MB/s<br><br>That&#39;s right, faster then v2 :) I&#39;ve managed to coerce the northbridge into running the memory at 200MHz (DDR400) without locking up the system like it does in v2, and also to use 1GB of ram, which the fuctory BIOS only sees as 512MB, and v2 for some reason trips over. However, it&#39;s a mixed blessing, even though memtest86 now runs at an acceptable speed, coreboot is still running fairly slowly. I&#39;m attaching a patch that brings over mtrr.c from v2 and hacks it to work with v3, but no sign-off because IMO it&#39;s not ready to be committed. I&#39;ll try booting a FILO payload and a kernel tomorrow, but right now it&#39;s time for some sleep.<br>
<br>-Corey<br>

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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2712.1355071475.16123.coreboot@coreboot.org>

or some such.

This might even be caused by my high tables patch from recently, but it
looks like a bug to me.

>>> However, a subtractive setup is not always more efficient. 
>>>     
>>>       
>> Is it not? It sounds like at least if we have 2^x bytes of memory and
>> subtract a small chunk or two, we would be quite well off with it.
>>   
>>     
>
> Assuming you don't have anything you want to cache near 4 GB (like flash):
> Both strategies are equally efficient if the contiguous cacheable area
> has a size of 2^n+2^(n-1).
> The additive strategy is more efficient if the size is 2^n+2^(n-k) and k>1.
> The subtractive strategy is more efficient if the size is 2^n-2^(n-k)
> and k>1.
>
> I hope that you accept this without a detailed mathematical proof. ;-)
>   

So in a setup with 2 equally sized DIMMs or only one DIMM, and possibly
UMA the subtractive method will always be the way to go.


>   
>>> That means we
>>> have to select the best setup type. I devised a slightly tricky
>>> algorithm to do that:
>>> 1. Check if there are multiple disjoint cached areas in a given
>>> power-of-two sized area.
>>> 1a. If no, go to step 2
>>> 1b. If yes, stop here. Need advanced setup not described here.
>>>   
>>>     
>>>       
>> please describe ;)
>>   
>>     
>
> 1b. Take the largest contiguous power-of-2 sized natually aligned chunk.
> Use additive setup for that chunk. Look at the remaining area. Does it
> still contain two disjoint chunks? If yes, go to 1b. If no, go to 2.
>
>
>   
>>> 2. additive_count=bitcount(top_cached_addr+1)
>>> 3.
>>> subtractive_count=bitcount(rounduptonextpowerof2(top_cached_addr)-(top_cached_addr+1))
>>> 4. if (additive_count>subtractive_count) go to subtractive_method else
>>> go to additive_method
>>>   
>>>     
>>>       
>> Yes, sounds good.
>>   
>>     
>
> Glad to hear that. I hope the rest of the algorithm is OK for you as well.
>   

Thinking about it again I'm not sure we're ever going to see multiple
disjoint cached areas in a given 2^x sized area. That would be... UMA in
the middle of the memory or something? Uh.. or more than 4G of memory?


-- 
coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ??? Fax: +49 761 7664613
Email: info at coresystems.de  ??? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ??? HRB 7656
Gesch??ftsf??hrer: Stefan Reinauer ??? Ust-IdNr.: DE245674866




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2733.1355071476.16123.coreboot@coreboot.org>

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/util/flashrom/flash.h
===================================================================
--- trunk/util/flashrom/flash.h	2009-01-26 03:23:50 UTC (rev 3912)
+++ trunk/util/flashrom/flash.h	2009-01-26 03:37:40 UTC (rev 3913)
@@ -523,6 +523,7 @@
 int spi_disable_blockprotect(void);
 void spi_byte_program(int address, uint8_t byte);
 int spi_nbyte_read(int address, uint8_t *bytes, int len);
+int spi_aai_write(struct flashchip *flash, uint8_t *buf);
 
 /* 82802ab.c */
 int probe_82802ab(struct flashchip *flash);

Modified: trunk/util/flashrom/flashchips.c
===================================================================
--- trunk/util/flashrom/flashchips.c	2009-01-26 03:23:50 UTC (rev 3912)
+++ trunk/util/flashrom/flashchips.c	2009-01-26 03:37:40 UTC (rev 3913)
@@ -1128,6 +1128,20 @@
 
 	{
 		.vendor		= "SST",
+		.name		= "SST25VF040B.REMS",
+		.manufacture_id	= 0xbf,
+		.model_id	= 0x8d,
+		.total_size	= 512,
+		.page_size	= 64*1024,
+		.tested		= TEST_OK_PR,
+		.probe		= probe_spi_rems,
+		.erase		= spi_chip_erase_c7,
+		.write		= spi_chip_aai_write,
+		.read		= spi_chip_read,
+	},
+
+	{
+		.vendor		= "SST",
 		.name		= "SST25VF080B",
 		.manufacture_id	= SST_ID,
 		.model_id	= SST_25VF080B,

Modified: trunk/util/flashrom/spi.c
===================================================================
--- trunk/util/flashrom/spi.c	2009-01-26 03:23:50 UTC (rev 3912)
+++ trunk/util/flashrom/spi.c	2009-01-26 03:37:40 UTC (rev 3913)
@@ -615,3 +615,29 @@
 
 	return 1;
 }
+
+int spi_aai_write(struct flashchip *flash, uint8_t *buf) {
+	uint32_t pos = 2, size = flash->total_size * 1024;
+	unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
+	switch (flashbus) {
+		case BUS_TYPE_WBSIO_SPI:
+			fprintf(stderr, "%s: impossible with Winbond SPI masters, degrading to byte program\n", __func__);
+			return spi_chip_write(flash, buf);
+		default:
+			break;
+	}
+	flash->erase(flash);
+	spi_write_enable();
+	spi_command(6, 0, w, NULL);
+	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+		myusec_delay(5); /* SST25VF040B Tbp is max 10us */
+	while (pos < size) {
+		w[1] = buf[pos++];
+		w[2] = buf[pos++];
+		spi_command(3, 0, w, NULL);
+		while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+			myusec_delay(5); /* SST25VF040B Tbp is max 10us */
+	}
+	spi_write_disable();
+	return 0;
+}




From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2748.1355071478.16123.coreboot@coreboot.org>

etherboot folks. They had coreboot support in etherboot, but it has not
(yet?) been implemented in gPXE.

With libpayload, this might actually be a lot easier now that it would have
been.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2792.1355071486.16123.coreboot@coreboot.org>

struct lb_memory_range {
        struct lb_uint64 start;
        struct lb_uint64 size;
        uint32_t type;
#define LB_MEM_RAM       1      /* Memory anyone can use */
#define LB_MEM_RESERVED  2      /* Don't use this memory region */
#define LB_MEM_TABLE     16     /* Ram configuration tables are kept in */
};


And the e820 looks like:

#define E820_RAM          1
#define E820_RESERVED     2
#define E820_ACPI         3
#define E820_NVS          4
#define E820_UNUSABLE     5

struct e820entry {
    u64 start;
    u64 size;
    u32 type;
};


So, SeaBIOS just copies the info over (with special handling for
LB_MEM_TABLE).

-Kevin



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2817.1355071489.16123.coreboot@coreboot.org>

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-unneeded_volatile/sst28sf040.c
===================================================================
--- flashrom-unneeded_volatile/sst28sf040.c	(Revision 3971)
+++ flashrom-unneeded_volatile/sst28sf040.c	(Arbeitskopie)
@@ -32,8 +32,7 @@
 
 static __inline__ void protect_28sf040(volatile uint8_t *bios)
 {
-	/* ask compiler not to optimize this */
-	volatile uint8_t tmp;
+	uint8_t tmp;
 
 	tmp = readb(bios + 0x1823);
 	tmp = readb(bios + 0x1820);
@@ -46,8 +45,7 @@
 
 static __inline__ void unprotect_28sf040(volatile uint8_t *bios)
 {
-	/* ask compiler not to optimize this */
-	volatile uint8_t tmp;
+	uint8_t tmp;
 
 	tmp = readb(bios + 0x1823);
 	tmp = readb(bios + 0x1820);


-- 
http://www.hailfinger.org/


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From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2819.1355071489.16123.coreboot@coreboot.org>

snapshot version=20
http://tracker.coreboot.org/trac/coreboot/changeset/latest/trunk/coreboo
t-v2?old_path=3D%2F&format=3Dzip (text: ... You can also download the =
most
current snapshot directly.)  does not contain the complete source thus
is causing 'buildingtarget' to fail. I just did a file diff, it is
missing 91 files from the util directory.

=20

Meanwhile, If I get it from http://qa.coreboot.org/ ->=20
http://qa.coreboot.org/snapshots/coreboot-v2-3973.tar.bz2
<http://qa.coreboot.org/snapshots/coreboot-v2-3972.tar.bz2> , I am was
able to do 'buildtarget' and 'gmake' for example, on
serengeti_cheetah_fam10 fine.

=20

Is there a reason to keep both mechanism ? It seems like=20
http://qa.coreboot.org/ is a better way to go, since it also doing
regression build on every svn checkin.

=20

=20

Best Regards,

=20

Vincent Lim
SimNow Team

Performance CoE
Central Engineering
T 512.602.1618
F 512.602.7745
=20

=20


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<p class=3DMsoNormal>Hi All:<o:p></o:p></p>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

<p class=3DMsoNormal>From http://www.coreboot.org/Download_coreboot =
page, I
discovered that snapshot version <a
href=3D"http://tracker.coreboot.org/trac/coreboot/changeset/latest/trunk/=
coreboot-v2?old_path=3D%2F&amp;format=3Dzip">http://tracker.coreboot.org/=
trac/coreboot/changeset/latest/trunk/coreboot-v2?old_path=3D%2F&amp;forma=
t=3Dzip</a>
(text: ... You can also download the most current snapshot directly.) =
&nbsp;does
not contain the complete source thus is causing 'buildingtarget' to =
fail. I
just did a file diff, it is missing 91 files from the util =
directory.<o:p></o:p></p>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

<p class=3DMsoNormal>Meanwhile, If I get it from <a =
href=3D"http://qa.coreboot.org/">http://qa.coreboot.org/</a>
-&gt; <a =
href=3D"http://qa.coreboot.org/snapshots/coreboot-v2-3972.tar.bz2">http:/=
/qa.coreboot.org/snapshots/coreboot-v2-3973.tar.bz2</a>,
I am was able to do 'buildtarget' and 'gmake' for example, on =
serengeti_cheetah_fam10
fine.<o:p></o:p></p>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

<p class=3DMsoNormal>Is there a reason to keep both mechanism ? It seems =
like <a
href=3D"http://qa.coreboot.org/">http://qa.coreboot.org/</a> is a better =
way to
go, since it also doing regression build on every svn =
checkin.<o:p></o:p></p>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

<p class=3DMsoNormal><b><span =
style=3D'font-size:7.5pt;font-family:"Verdana","sans-serif";
color:black'>Best Regards,<o:p></o:p></span></b></p>

<p class=3DMsoNormal><b><span =
style=3D'font-size:7.5pt;font-family:"Verdana","sans-serif";
color:black'><o:p>&nbsp;</o:p></span></b></p>

<p class=3DMsoNormal><b><span =
style=3D'font-size:7.5pt;font-family:"Verdana","sans-serif";
color:black'>Vincent Lim</span></b><b><span =
style=3D'font-size:7.5pt;font-family:
"Verdana","sans-serif";color:black'><br>
</span></b><span =
style=3D'font-size:7.5pt;font-family:"Verdana","sans-serif";
color:black'>SimNow Team</span><o:p></o:p></p>

<p class=3DMsoNormal><span =
style=3D'font-size:7.5pt;font-family:"Verdana","sans-serif";
color:black'>Performance CoE<b><br>
</b>Central Engineering<b><br>
</b>T 512.602.1618<br>
F 512.602.7745</span><span =
style=3D'font-size:7.5pt;font-family:"Verdana","sans-serif";
color:#404040'><br>
</span><span style=3D'color:black'><img border=3D0 width=3D288 =
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alt=3D"fusion_sig_file"></span><span style=3D'font-family:"Courier =
New"'><o:p></o:p></span></p>

<p class=3DMsoNormal><o:p>&nbsp;</o:p></p>

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------_=_NextPart_001_01C99E7E.C33FC9BB--



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2832.1355071491.16123.coreboot@coreboot.org>

from the normal XP build. XP Embedded is basically a totally
modularizable Windows XP distribution, but the lowest layer is never
changed. So because SeaBIOS starts normal XP, it will also start XP
Embedded. Freeldr was not familiar to anyone in the MS booth, but they
did like the prospect of booting kernel really quickly from reset - as
always! :)


I have never been so convinced that coreboot is potent and worthwhile
as I am today.


//Peter



From bogus@does.not.exist.com  Sun Dec  9 17:34:17 2012
From: bogus@does.not.exist.com ()
Date: Sun, 09 Dec 2012 16:34:17 -0000
Subject: No subject
Message-ID: <mailman.2870.1355071495.16123.coreboot@coreboot.org>

error.
OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus
consumes 1MB */
        Field(PCFG, ByteAcc, NoLock, Preserve) {
        /* Byte offsets are computed using the following technique:
           * ((bus number + 1) * ((device number * 8) * 4096)) +
register offset
           * The 8 comes from 8 functions per device, and 4096 bytes per
function config space
        */
        Offset(0x00090024),     /* Byte offset to SATA register 24h -
Bus 0, Device 18, Function 0 */
        STB5, 32,               /* Address of SATA_BAR5 */
...
}

OperationRegion(SB5, SystemMemory, STB5, 0x1000) /* SATA_BAR5 (ABAR) */
        Field(SB5, AnyAcc, NoLock, Preserve)
        {
...
        Offset(0x128),          /* Port 0 Serial ATA status */
        P0DD, 4,                /* Port 0 Device Detection (DET) */
        , 4,
        P0IS, 4,                /* Port 0 Interface Power Management
(IPM) */
        Offset(0x12C),          /* Port 0 Serial ATA control */
        P0DI, 4,
        Offset(0x130),          /* Port 0 Serial ATA error */
        , 16,
        P0PR, 1,


The only explanation I can come up with is:
P0IS lives at addrof(SB5)+0x129
P0PR lives at addrof(SB5)+0x132
Field SB5 has address STB5.
Therefore:
P0IS lives at STB5+0x129
P0PR lives at STB5+0x132
The accesses to P0IS happen at 0x100000128.
The accesses to P0PR happen at 0x100000131.
Subtraction yields:
STB5=0xffffffff.
That's certainly NOT a valid address of a BAR.

The coreboot log says:
sata_bar5=fc409000

/proc/iomem says:
fc409000-fc4093ff : 0000:00:12.0
  fc409000-fc4093ff : ahci

lspci says:
00:12.0 SATA controller [0106]: ATI Technologies Inc SB600 Non-Raid-5
SATA [1002:4380] (prog-if 01 [AHCI 1.0])
        Subsystem: ATI Technologies Inc SB600 Non-Raid-5 SATA [1002:4380]
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR+ FastB2B- DisINTx-
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 64, Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 22
        Region 0: I/O ports at 4020 [size=8]
        Region 1: I/O ports at 4060 [size=4]
        Region 2: I/O ports at 4030 [size=8]
        Region 3: I/O ports at 4070 [size=4]
        Region 4: I/O ports at 4000 [size=16]
        Region 5: Memory at fc409000 (32-bit, non-prefetchable) [size=1K]
        Capabilities: [60] Power Management version 2
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
        Kernel driver in use: ahci
        Kernel modules: ahci
00: 02 10 80 43 07 01 30 02 00 01 06 01 10 40 00 00
10: 21 40 00 00 61 40 00 00 31 40 00 00 71 40 00 00
20: 01 40 00 00 00 90 40 fc 00 00 00 00 02 10 80 43
30: 00 00 00 00 60 00 00 00 00 00 00 00 00 01 00 00
40: 14 00 80 02 01 00 10 00 01 00 00 00 00 00 00 00
50: 05 00 84 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 01 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 12 00 10 00 0f 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 06 00 00 2c d6 01 b4 00 d6 01 b4 00
90: d6 01 b4 00 d6 01 b4 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 b8 00 00 00 00 00 00 00 b8 00 00
b0: 00 00 00 00 00 b8 00 00 00 00 00 00 00 b8 00 00
c0: 00 20 00 00 80 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Tell me what additional info you need and I'll send it.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/


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