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Sun Dec 9 17:34:17 CET 2012

it has limited size) in the boot block. That avoids any and all
requirements to keep code in RAM, thereby taking away the problem of
code relocation.

> In the case of the SMM handler, this would also confine us, because the
> actual SMI# handling code (written in C) would not be shared between
> CPUs but has to be duplicated for every CPU core. However, my current
> approach only keeps a very small amount of code per CPU, that is just
> enough to enter gcc compiled functions and return from them, cleanly.

AFAIK factory BIOS SMM handlers have the ability to lock down the memory
segment they are using, protecting them from accidental or deliberate
tampering by the OS (which could lead to interesting security issues).
Can we do that even if the handler is "somewhere" in RAM?

> One of the questions in my mind is: where should we put the coreboot
> image, if we want to keep it around?
> A little excerpt from coreboot v2:
> I know the problem of where to put coreboot has been thought about
> before, elfboot() relocates coreboot to another place when loading an
> ELF binary that demands the space where coreboot lives:
>  * coreboot tries to load a segment and finds out, that it is in the way.
>  * coreboot copies itself to a new position
>  * coreboot jumps into the assembler handler in jmp_to_elf_entry at the
> new position
>  * coreboot tries to start the ELF binary.
>  * If it fails, it overwrites the loaded ELF binary by copying itself
> back and jumping to the original position.
> This is quite an interesting concept, but it also makes clear that the
> ram portion of coreboot itself ("stage2") can not be relocated freely in
> memory. Yet.

Please see my other mail in this thread about possible problems with a
relocatable stage2. Besides that, we'd need a way in v3 to tag a LAR
member as PIC (sort of done for the special case of XIP in initram) and
new code to figure out a good load address during run time.

> Since we know how big our RAM is when we copy coreboot to RAM, I suggest
> that we copy coreboot to the end of memory and run it from there. It is
> a pretty good assumption that no payload will require that space. During
> memory map creation, we just reserve 256k at the upper end, and we're good.

Hm... I assume end of memory is "end of memory below 4G". If we want to
avoid conflicts with mapped memory areas of extension cards, stage2 code
has to be loaded twice: Once before setting up extension cards (load
stage2 to above 1M or other failsafe location) and after setting up
extension cards (load stage2 to end of memory below 4G and below
extension card space). That's not exactly the nicest code flow I can
think of.



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