No subject

Sun Dec 9 17:34:17 CET 2012

CPU core glued to an Intel 3100 northbridge/southbridge/SuperIO, with
a slightly fancier DDR2 memory controller. Thus my patches augment the
existing Intel 3100 code in coreboot.

The code was written using information in the datasheet available on
the Intel web site, and has been tested on an EP80579 Development
Board (codename "Truxton"), booting a Linux kernel payload.


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