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3.1 Configuration Space Accesses
The AMD Athlon=99 64 and AMD Opteron=99 Processors implement configuration =
space
as defined in
the PCI Local Bus Specification, Rev. 2.2, and the HyperTransport=99 I/O Li=
nk
Specification, Rev.
1.03.

I read that to mean that even though the processor reports Rev 1.02, it's
1.03.

Thanks,
Myles

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<br><br><div class=3D"gmail_quote">On Fri, Oct 24, 2008 at 9:21 AM, Carl-Da=
niel Hailfinger <span dir=3D"ltr"><<a href=3D"mailto:c-d.hailfinger.deve=
l.2006 at gmx.net">c-d.hailfinger.devel.2006 at gmx.net</a>></span> wrote:<br>=
<blockquote class=3D"gmail_quote" style=3D"border-left: 1px solid rgb(204, =
204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div class=3D"Ih2E3d">On 24.10.2008 17:13, Carl-Daniel Hailfinger wrote:<br=
>
> Hi,<br>
><br>
> I'm getting the following message from lspci on my K8 machine:<br>
><br>
> 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8<br>
> [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100]=
<br>
>         Control: I/O- Mem- BusMaster- SpecCycle- M=
emWINV- VGASnoop-<br>
> ParErr- Stepping- SERR- FastB2B- DisINTx-<br>
>         Status: Cap+ 66MHz- UDF- FastB2B- ParErr- =
DEVSEL=3Dfast >TAbort-<br>
> <TAbort- <MAbort- >SERR- <PERR- INTx-<br>
>         Capabilities: [80] HyperTransport: Host or=
 Secondary Interface<br>
>                 !!! Possibly i=
ncomplete decoding for revision 1.02<br>
>                 Command: WarmR=
st+ DblEnd-<br>
>                 Link Control: =
CFlE- CST- CFE- <LkFail- Init+ EOC- TXO-<br>
> <CRCErr=3D0<br>
>                 Link Config: M=
LWI=3D16bit MLWO=3D16bit LWI=3D16bit LWO=3D16bit<br>
>                 Revision ID: 1=
.02<br>
>         Kernel modules: ipmi_si<br>
><br>
</div><div class=3D"Ih2E3d">> Note the warning about "Possibly inco=
mplete decoding" which stems from<br>
> the fact that the processor mentions HT revision 1.02 which is the las=
t<br>
> non-public revision. Every revision from 1.03 and beyond seems to be<b=
r>
> publically available. Now the big question is: Can we decode HT 1.02<b=
r>
> like HT 1.03 or have there been fundamental changes in between? I'=
d like<br>
> to create a patch for PCIutils (lspci) so we can have full info withou=
t<br>
> a warning message.<br></div></blockquote><div><br>From the BKDG:<br>3.=
1 Configuration Space Accesses<br>The AMD Athlon=99 64 and AMD Opteron=99 P=
rocessors implement configuration space as defined in<br>the PCI Local Bus =
Specification, Rev. 2.2, and the HyperTransport=99 I/O Link Specification, =
Rev.<br>
1.03.<br><br>I read that to mean that even though the processor reports Rev=
 1.02, it's 1.03.<br><br>Thanks,<br>Myles <br></div></div><br>

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