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<quote>
LV2 — Level 2 Register
I/O Address: PMBASE + 14h
...
Reads to this register return all 0s, writes to this register have no
effect. Reads to this
register generate a “enter a level 2 power state” (C2) to the clock
control logic. This will
cause the STPCLK# signal to go active, and stay active until a break
event occurs.
Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.
...
NOTE: This register should not be used by IA-64 processors or systems
with more than 1 logical
      processor, unless appropriate semaphoring software has been put in
place to ensure that
      all threads/processors are ready for the C2 state when the read to
this register occurs.
</quote>

The subsequent byte registers are LV3, LV4, LV5 and for mobile version
LV6 intended for entering C3, C4, C5 and C6 states.

-- 
Andriy Gapon