[coreboot] Patch set updated for coreboot: 5d4b0b8 Add minimal mainboard support for snow
Ronald G. Minnich (rminnich@gmail.com)
gerrit at coreboot.org
Tue Dec 11 02:31:09 CET 2012
Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2018
-gerrit
commit 5d4b0b84066ccdbe3eee4527acb37932fa557f78
Author: Ronald G. Minnich <rminnich at gmail.com>
Date: Mon Dec 10 16:13:43 2012 -0800
Add minimal mainboard support for snow
This is the minimal set of sources that allow the board to build.
These need to be filled in with actual code. But if we get these in upstream
we can stop working against a WIP patch.
Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
src/mainboard/google/snow/Kconfig | 161 +++++++++++++++++++++++++++++++
src/mainboard/google/snow/Makefile.inc | 36 +++++++
src/mainboard/google/snow/board.h | 33 +++++++
src/mainboard/google/snow/devicetree.cb | 7 ++
src/mainboard/google/snow/mainboard.c | 37 +++++++
src/mainboard/google/snow/romstage.c | 33 +++++++
src/mainboard/google/snow/smdk5250_spl.c | 81 ++++++++++++++++
7 files changed, 388 insertions(+)
diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig
new file mode 100644
index 0000000..98ffa0e
--- /dev/null
+++ b/src/mainboard/google/snow/Kconfig
@@ -0,0 +1,161 @@
+if BOARD_GOOGLE_SNOW
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_ARMV7
+ select CPU_SAMSUNG_EXYNOS5
+ select HAVE_UART_MEMORY_MAPPED
+ select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging
+# select EC_GOOGLE_CHROMEEC
+ select BOARD_ROMSIZE_KB_4096
+ select DRIVER_MAXIM_77686
+# select HAVE_ACPI_TABLES
+# select MMCONF_SUPPORT
+# select CHROMEOS
+
+config MAINBOARD_DIR
+ string
+ default google/snow
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "SNOW"
+
+#config MMCONF_BASE_ADDRESS
+# hex
+# default 0xf0000000
+
+#config IRQ_SLOT_COUNT
+# int
+# default 18
+
+config MAX_CPUS
+ int
+ default 2
+
+config MAINBOARD_VENDOR
+ string
+ default "Samsung"
+
+# SPL (second-phase loader) stuff
+config SPL_TEXT_BASE
+ hex "SPL executable base"
+ default 0x02023400
+ help
+ Location of SPL. Default location is within iRAM region.
+
+#FIXME: increased "SPL" size to get around build issues
+#config SPL_MAX_SIZE
+# hex "SPL executable max size"
+# default 0x3800
+# help
+# Max size of SPL. Default is 14KB
+config SPL_MAX_SIZE
+ hex "SPL executable max size"
+ default 0x8000
+ help
+ Max size of SPL. Let's say 32KB for now...
+
+config DRAM_SIZE_MB
+ int "DRAM size (MB)"
+ default 2048
+
+config NR_DRAM_BANKS
+ int "Number of DRAM banks"
+ default 1
+
+choice
+ prompt "Serial Console UART"
+ default CONSOLE_SERIAL_UART3
+ depends on CONSOLE_SERIAL_NONSTANDARD_MEM
+
+config CONSOLE_SERIAL_UART0
+ bool "UART0"
+ help
+ Serial console on UART0
+
+config CONSOLE_SERIAL_UART1
+ bool "UART1"
+ help
+ Serial console on UART1
+
+config CONSOLE_SERIAL_UART2
+ bool "UART2"
+ help
+ Serial console on UART2
+
+config CONSOLE_SERIAL_UART3
+ bool "UART3"
+ help
+ Serial console on UART3
+
+endchoice
+
+config CONSOLE_SERIAL_UART_ADDRESS
+ hex
+ depends on CONSOLE_SERIAL_NONSTANDARD_MEM
+ default 0x12c00000 if CONSOLE_SERIAL_UART0
+ default 0x12c10000 if CONSOLE_SERIAL_UART1
+ default 0x12c20000 if CONSOLE_SERIAL_UART2
+ default 0x12c30000 if CONSOLE_SERIAL_UART3
+ help
+ Map the UART names to the respective MMIO address.
+
+#################################################################
+# stuff from smdk5250.h #
+# FIXME: can we move some of these to exynos5250's Kconfig? #
+#################################################################
+config SYS_I2C_SPEED
+ int
+ default 100000
+
+config SYS_I2C_SLAVE
+ hex
+ default 0x0
+
+config I2C_MULTI_BUS
+ bool
+ default y
+
+#config HARD_I2C
+# bool
+# default y
+#CMD_I2C
+#I2C_EDID
+#DRIVER_S3C24X0_I2C
+
+config VDD_ARM_MV
+ int
+ default 1300 #1.3V
+
+config VDD_INT_UV
+ int
+ default 1012500 # 1.0125v
+
+config VDD_MIF_MV
+ int
+ default 1000 # 1.0v
+
+config VDD_G3D_MV
+ int
+ default 1200 # 1.2v
+
+config VDD_LDO2_MV
+ int
+ default 1500 # 1.5v
+
+config VDD_LDO3_MV
+ int
+ default 1800 # 1.8v
+
+config VDD_LDO5_MV
+ int
+ default 1800 # 1.8v
+
+config VDD_LDO10_MV
+ int
+ default 1800 # 1.8v
+
+######### smdk5250.h ########
+
+endif # BOARD_GOOGLE_SNOW
diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc
new file mode 100644
index 0000000..01488d0
--- /dev/null
+++ b/src/mainboard/google/snow/Makefile.inc
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#romstage-y += romstage.c
+
+# ramstage-y += ec.c
+
+# FIXME: smdk5250_spl and mainboard.c are a mess. In the long
+# run we'll want to replace low-level code that calls mainboard code
+# with mainboard code that calls low-level code with appropriate
+# parameters. Grep around for spl_get_machine_params for examples.
+romstage-y += smdk5250_spl.c
+ramstage-y += smdk5250_spl.c
+#ramstage-y += mainboard.c
+
+# romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+# FIXME: we should do something similar to x86 platforms for Snow SPDs
+
+SRC_ROOT = $(src)/mainboard/google/snow
diff --git a/src/mainboard/google/snow/board.h b/src/mainboard/google/snow/board.h
new file mode 100644
index 0000000..bedd740
--- /dev/null
+++ b/src/mainboard/google/snow/board.h
@@ -0,0 +1,33 @@
+/*
+ * Board header file for Exynos boards
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SAMSUNG_BOARD_H
+#define __SAMSUNG_BOARD_H
+
+/* Init the SPI driver */
+void spi_init(void);
+
+/* Init the I2C driver */
+void board_i2c_init(const void *blob);
+
+#endif
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
new file mode 100644
index 0000000..1d9d553
--- /dev/null
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -0,0 +1,7 @@
+# FIXME: this is just a stub for now
+chip cpu/samsung/exynos5250
+ chip drivers/generic/generic # I2C0 controller
+ device i2c 6 on end # ?
+ device i2c 9 on end # ?
+ end
+end
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
new file mode 100644
index 0000000..8e51b73
--- /dev/null
+++ b/src/mainboard/google/snow/mainboard.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2012 The ChromeOS Authors
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <device/device.h>
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ //dev->ops->init = mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = "Samsung/Google ARM ChromeBook",
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
new file mode 100644
index 0000000..a059f2b
--- /dev/null
+++ b/src/mainboard/google/snow/romstage.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <system.h>
+#include <cache.h>
+
+static void mmu_setup(void)
+{
+ dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
+}
+
+void main(unsigned long bist)
+{
+ mmu_setup();
+}
diff --git a/src/mainboard/google/snow/smdk5250_spl.c b/src/mainboard/google/snow/smdk5250_spl.c
new file mode 100644
index 0000000..f3a88f3
--- /dev/null
+++ b/src/mainboard/google/snow/smdk5250_spl.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <arch/gpio.h>
+#include <cpu/samsung/exynos5-common/spl.h>
+#include <cpu/samsung/exynos5250/gpio.h>
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version = 1,
+ .params = "vmubfasirMw",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size = 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+ * Set uboot_size to 0x100000 bytes.
+ *
+ * This is an overly conservative value chosen to accommodate all
+ * possible U-Boot image. You are advised to set this value to a
+ * smaller realistic size via scripts that modifies the .machine_param
+ * section of output U-Boot image.
+ */
+ .uboot_size = 0x100000,
+
+ .boot_source = BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1700,
+ .serial_base = 0x12c30000,
+ .i2c_base = 0x12c60000,
+ .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16),
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+ .bad_wake_gpio = GPIO_Y10,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* TODO: Call panic() here */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
+
+int board_wakeup_permitted(void)
+{
+ struct spl_machine_param *param = spl_get_machine_params();
+ const int gpio = param->bad_wake_gpio;
+ int is_bad_wake;
+
+ /* We're a bad wakeup if the gpio was defined and was high */
+ is_bad_wake = ((gpio != -1) && gpio_get_value(gpio));
+
+ return !is_bad_wake;
+}
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