[coreboot] Patch merged into coreboot/master: 3aef7b4 Fix SPI BAR special case in lpc_set_resources

gerrit at coreboot.org gerrit at coreboot.org
Wed Dec 12 22:34:33 CET 2012

the following patch was just integrated into master:
commit 3aef7b4f63b3870e3699d5408d0fb8917c5eb135
Author: Martin Roth <martin at se-eng.com>
Date:   Wed Dec 5 15:50:32 2012 -0700

    Fix SPI BAR special case in lpc_set_resources
    There was already a special case for the SPI base address in
    lpc_set_resources for southbridge/amd/cimx/sb800 and
    southbridge/amd/agesa/hudson, but it needed to be modified
    to keep from killing the IMC rom during initialization.  As
    soon as the BAR is disabled by setting the new base address,
    the IMC dies.  The fix is to make sure it's still enabled
    when setting the new base address instead of setting the new
    address then re-enabling it.
    to more accurately describe what we're using.
    Change-Id: I216d75b722c4332c239d487111a9880eabf59e91
    Signed-off-by: Martin Roth <martin at se-eng.com>
    Reviewed-on: http://review.coreboot.org/1975
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Fri Dec  7 00:55:20 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Dec  7 00:30:25 2012, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Wed Dec 12 17:42:07 2012, giving +2
See http://review.coreboot.org/1975 for details.


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