[coreboot] New patch to review for coreboot: ab4e5aa Rename mainboard_smi.c to smihandler.c
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Wed Dec 19 18:07:12 CET 2012
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2058
-gerrit
commit ab4e5aa6637f34a6e902387e5e9b50efbd1385db
Author: Patrick Georgi <patrick at georgi-clan.de>
Date: Wed Dec 19 16:32:47 2012 +0100
Rename mainboard_smi.c to smihandler.c
This mirrors the naming convention of handlers in
northbridge and southbridge.
Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
src/arch/x86/Makefile.inc | 4 +-
src/mainboard/getac/p470/acpi/ec.asl | 4 +-
src/mainboard/getac/p470/mainboard_smi.c | 203 ---------------------
src/mainboard/getac/p470/smihandler.c | 203 +++++++++++++++++++++
src/mainboard/google/parrot/Makefile.inc | 2 -
src/mainboard/google/parrot/mainboard_smi.c | 217 -----------------------
src/mainboard/google/parrot/smihandler.c | 217 +++++++++++++++++++++++
src/mainboard/ibase/mb899/mainboard_smi.c | 52 ------
src/mainboard/ibase/mb899/smihandler.c | 52 ++++++
src/mainboard/intel/d945gclf/mainboard_smi.c | 52 ------
src/mainboard/intel/d945gclf/smihandler.c | 52 ++++++
src/mainboard/intel/emeraldlake2/mainboard_smi.c | 97 ----------
src/mainboard/intel/emeraldlake2/smihandler.c | 97 ++++++++++
src/mainboard/iwave/iWRainbowG6/mainboard_smi.c | 52 ------
src/mainboard/iwave/iWRainbowG6/smihandler.c | 52 ++++++
src/mainboard/kontron/986lcd-m/mainboard_smi.c | 52 ------
src/mainboard/kontron/986lcd-m/smihandler.c | 52 ++++++
src/mainboard/lenovo/t60/mainboard_smi.c | 199 ---------------------
src/mainboard/lenovo/t60/smihandler.c | 199 +++++++++++++++++++++
src/mainboard/lenovo/x60/mainboard_smi.c | 208 ----------------------
src/mainboard/lenovo/x60/smihandler.c | 208 ++++++++++++++++++++++
src/mainboard/rca/rm4100/mainboard_smi.c | 31 ----
src/mainboard/rca/rm4100/smihandler.c | 31 ++++
src/mainboard/roda/rk886ex/mainboard_smi.c | 53 ------
src/mainboard/roda/rk886ex/smihandler.c | 53 ++++++
src/mainboard/roda/rk9/Makefile.inc | 1 -
src/mainboard/roda/rk9/mainboard_smi.c | 76 --------
src/mainboard/roda/rk9/smihandler.c | 76 ++++++++
src/mainboard/samsung/lumpy/mainboard_smi.c | 123 -------------
src/mainboard/samsung/lumpy/smihandler.c | 123 +++++++++++++
src/mainboard/samsung/stumpy/mainboard_smi.c | 113 ------------
src/mainboard/samsung/stumpy/smihandler.c | 113 ++++++++++++
src/mainboard/thomson/ip1000/mainboard_smi.c | 31 ----
src/mainboard/thomson/ip1000/smihandler.c | 31 ++++
34 files changed, 1563 insertions(+), 1566 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index b8ad37e..e84700e 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -260,8 +260,8 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c
endif
endif
ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
-ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard_smi.c),)
-smm-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard_smi.c
+ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),)
+smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c
endif
endif
ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c),)
diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl
index 70faab2..b8e2954 100644
--- a/src/mainboard/getac/p470/acpi/ec.asl
+++ b/src/mainboard/getac/p470/acpi/ec.asl
@@ -425,14 +425,14 @@ Scope(\_SB)
Method(SBLL, 1, Serialized)
{
Store (Arg0, BRTL)
- TRAP(0xd5) // See mainboard_smi.c
+ TRAP(0xd5) // See mainboard's smihandler.c
Return (0)
}
/* Get Brightness Level */
Method(GBLL, 0, Serialized)
{
- TRAP(0xd6) // See mainboard_smi.c
+ TRAP(0xd6) // See mainboard's smihandler.c
Return (BRTL)
}
diff --git a/src/mainboard/getac/p470/mainboard_smi.c b/src/mainboard/getac/p470/mainboard_smi.c
deleted file mode 100644
index 4a5a3ff..0000000
--- a/src/mainboard/getac/p470/mainboard_smi.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx.h"
-#include "southbridge/intel/i82801gx/nvs.h"
-#include <ec/acpi/ec.h>
-#include "ec_oem.c"
-
-#define MAX_LCD_BRIGHTNESS 0xd8
-
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern global_nvs_t *gnvs;
-
-int mainboard_io_trap_handler(int smif)
-{
- u8 reg8;
- u32 reg32;
-
- switch (smif) {
- case 0x2b:
- printk(BIOS_DEBUG, "CPU power state switch\n");
- // TODO, move to CPU handler?
- break;
- case 0x3d:
- printk(BIOS_DEBUG, "Enable C-State SMM coordination\n");
- // TODO, move to CPU handler?
- break;
- case 0x46:
- printk(BIOS_DEBUG, "S3 DTS SMI (completely re-enable DTS)\n");
- // TODO, move to CPU handler?
- break;
- case 0x47:
- printk(BIOS_DEBUG, "S4 DTS SMI (Update NVS DTS temperature)\n");
- // TODO, move to CPU handler?
- break;
- case 0xc0:
- printk(BIOS_DEBUG, "Disable RF\n");
- // TODO
- break;
- case 0xd0:
- printk(BIOS_DEBUG, "ACBS LAN Power on\n");
- // TODO
- break;
- case 0xd1:
- printk(BIOS_DEBUG, "ACBS LAN Power off\n");
- // TODO
- break;
- case 0xd2:
- printk(BIOS_DEBUG, "Check AC status\n");
- // TODO
- break;
- case 0xd3:
- printk(BIOS_DEBUG, "Enable Bluetooth\n");
- // TODO
- break;
- case 0xd4:
- printk(BIOS_DEBUG, "Disable Bluetooth\n");
- // TODO
- break;
- case 0xd5:
- printk(BIOS_DEBUG, "Set Brightness\n");
- reg8 = gnvs->brtl;
- printk(BIOS_DEBUG, "brtl: %x\n", reg8);
- ec_write(0x17, reg8);
- break;
- case 0xd6:
- printk(BIOS_DEBUG, "Get Brightness\n");
- reg8 = ec_read(0x17);
- printk(BIOS_DEBUG, "brtl: %x\n", reg8);
- gnvs->brtl = reg8;
- break;
- case 0xd7:
- printk(BIOS_DEBUG, "Get ECO mode status\n");
- // TODO
- break;
- case 0xd8:
- printk(BIOS_DEBUG, "Get sunlight readable status\n");
- // TODO
- break;
- case 0xd9:
- printk(BIOS_DEBUG, "Get docking connection\n");
- // TODO
- break;
- case 0xda:
- printk(BIOS_DEBUG, "Power off docking\n");
- // TODO
- break;
- case 0xdc:
- printk(BIOS_DEBUG, "EC: Turn on LED on ECO enable\n");
- // TODO
- break;
- case 0xdd:
- printk(BIOS_DEBUG, "EC: Turn off LED on ECO disable\n");
- // TODO
- break;
- case 0xde:
- printk(BIOS_DEBUG, "LAN power off\n");
- reg32 = inl(DEFAULT_GPIOBASE + GP_LVL);
- reg32 |= (1 << 24); // Disable LAN Power
- outl(reg32, DEFAULT_GPIOBASE + GP_LVL);
- break;
- case 0xdf:
- printk(BIOS_DEBUG, "RF enable\n");
- // TODO
- break;
- case 0xe0:
- printk(BIOS_DEBUG, "Get RTC wake flag\n");
- // TODO
- break;
- case 0xe1:
- printk(BIOS_DEBUG, "Hotkey function\n");
- // TODO
- break;
- case 0xe3:
- printk(BIOS_DEBUG, "ECO disable\n");
- // TODO
- break;
- default:
- return 0;
- }
-
- /* gnvs->smif:
- * On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- */
- gnvs->smif = 0;
- return 1;
-}
-
-static void mainboard_smi_hotkey(u8 hotkey)
-{
- u8 reg8;
-
- switch (hotkey) {
- case 0x3b: break; // Fn+F1
- case 0x3c: break; // Fn+F2
- case 0x3d: break; // Fn+F3
- case 0x3e: break; // Fn+F4
- case 0x3f: break; // Fn+F5
- case 0x40: // Fn+F6 (Decrease Display Brightness)
- reg8 = ec_read(0x17);
- reg8 = (reg8 > 8) ? (reg8 - 8) : 0;
- ec_write(0x17, reg8);
- return;
- case 0x41: // Fn+F7 (Increase Display Brightness)
- reg8 = ec_read(0x17);
- reg8 += 8;
- reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8;
- ec_write(0x17, reg8);
- return;
- case 0x42: break; // Fn+F8
- case 0x43: break; // Fn+F9
- case 0x44: break; // Fn+F10
- case 0x57: break; // Fn+F11
- case 0x58: break; // Fn+F12
- }
- printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey);
-}
-
-void mainboard_smi_gpi(u16 gpi_sts)
-{
- u8 source, hotkey;
- send_ec_oem_command(0x5c);
- source = recv_ec_oem_data();
-
- switch (source) {
- case 0:
- // Some kind of ACK?
- break;
- case 1:
- send_ec_oem_command(0x59);
- hotkey = recv_ec_oem_data();
- mainboard_smi_hotkey(hotkey);
- break;
- default:
- printk(BIOS_DEBUG, "EC SMI source: %02x\n", source);
- }
-}
-
diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c
new file mode 100644
index 0000000..4a5a3ff
--- /dev/null
+++ b/src/mainboard/getac/p470/smihandler.c
@@ -0,0 +1,203 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/i82801gx.h"
+#include "southbridge/intel/i82801gx/nvs.h"
+#include <ec/acpi/ec.h>
+#include "ec_oem.c"
+
+#define MAX_LCD_BRIGHTNESS 0xd8
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ u8 reg8;
+ u32 reg32;
+
+ switch (smif) {
+ case 0x2b:
+ printk(BIOS_DEBUG, "CPU power state switch\n");
+ // TODO, move to CPU handler?
+ break;
+ case 0x3d:
+ printk(BIOS_DEBUG, "Enable C-State SMM coordination\n");
+ // TODO, move to CPU handler?
+ break;
+ case 0x46:
+ printk(BIOS_DEBUG, "S3 DTS SMI (completely re-enable DTS)\n");
+ // TODO, move to CPU handler?
+ break;
+ case 0x47:
+ printk(BIOS_DEBUG, "S4 DTS SMI (Update NVS DTS temperature)\n");
+ // TODO, move to CPU handler?
+ break;
+ case 0xc0:
+ printk(BIOS_DEBUG, "Disable RF\n");
+ // TODO
+ break;
+ case 0xd0:
+ printk(BIOS_DEBUG, "ACBS LAN Power on\n");
+ // TODO
+ break;
+ case 0xd1:
+ printk(BIOS_DEBUG, "ACBS LAN Power off\n");
+ // TODO
+ break;
+ case 0xd2:
+ printk(BIOS_DEBUG, "Check AC status\n");
+ // TODO
+ break;
+ case 0xd3:
+ printk(BIOS_DEBUG, "Enable Bluetooth\n");
+ // TODO
+ break;
+ case 0xd4:
+ printk(BIOS_DEBUG, "Disable Bluetooth\n");
+ // TODO
+ break;
+ case 0xd5:
+ printk(BIOS_DEBUG, "Set Brightness\n");
+ reg8 = gnvs->brtl;
+ printk(BIOS_DEBUG, "brtl: %x\n", reg8);
+ ec_write(0x17, reg8);
+ break;
+ case 0xd6:
+ printk(BIOS_DEBUG, "Get Brightness\n");
+ reg8 = ec_read(0x17);
+ printk(BIOS_DEBUG, "brtl: %x\n", reg8);
+ gnvs->brtl = reg8;
+ break;
+ case 0xd7:
+ printk(BIOS_DEBUG, "Get ECO mode status\n");
+ // TODO
+ break;
+ case 0xd8:
+ printk(BIOS_DEBUG, "Get sunlight readable status\n");
+ // TODO
+ break;
+ case 0xd9:
+ printk(BIOS_DEBUG, "Get docking connection\n");
+ // TODO
+ break;
+ case 0xda:
+ printk(BIOS_DEBUG, "Power off docking\n");
+ // TODO
+ break;
+ case 0xdc:
+ printk(BIOS_DEBUG, "EC: Turn on LED on ECO enable\n");
+ // TODO
+ break;
+ case 0xdd:
+ printk(BIOS_DEBUG, "EC: Turn off LED on ECO disable\n");
+ // TODO
+ break;
+ case 0xde:
+ printk(BIOS_DEBUG, "LAN power off\n");
+ reg32 = inl(DEFAULT_GPIOBASE + GP_LVL);
+ reg32 |= (1 << 24); // Disable LAN Power
+ outl(reg32, DEFAULT_GPIOBASE + GP_LVL);
+ break;
+ case 0xdf:
+ printk(BIOS_DEBUG, "RF enable\n");
+ // TODO
+ break;
+ case 0xe0:
+ printk(BIOS_DEBUG, "Get RTC wake flag\n");
+ // TODO
+ break;
+ case 0xe1:
+ printk(BIOS_DEBUG, "Hotkey function\n");
+ // TODO
+ break;
+ case 0xe3:
+ printk(BIOS_DEBUG, "ECO disable\n");
+ // TODO
+ break;
+ default:
+ return 0;
+ }
+
+ /* gnvs->smif:
+ * On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ */
+ gnvs->smif = 0;
+ return 1;
+}
+
+static void mainboard_smi_hotkey(u8 hotkey)
+{
+ u8 reg8;
+
+ switch (hotkey) {
+ case 0x3b: break; // Fn+F1
+ case 0x3c: break; // Fn+F2
+ case 0x3d: break; // Fn+F3
+ case 0x3e: break; // Fn+F4
+ case 0x3f: break; // Fn+F5
+ case 0x40: // Fn+F6 (Decrease Display Brightness)
+ reg8 = ec_read(0x17);
+ reg8 = (reg8 > 8) ? (reg8 - 8) : 0;
+ ec_write(0x17, reg8);
+ return;
+ case 0x41: // Fn+F7 (Increase Display Brightness)
+ reg8 = ec_read(0x17);
+ reg8 += 8;
+ reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8;
+ ec_write(0x17, reg8);
+ return;
+ case 0x42: break; // Fn+F8
+ case 0x43: break; // Fn+F9
+ case 0x44: break; // Fn+F10
+ case 0x57: break; // Fn+F11
+ case 0x58: break; // Fn+F12
+ }
+ printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey);
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+ u8 source, hotkey;
+ send_ec_oem_command(0x5c);
+ source = recv_ec_oem_data();
+
+ switch (source) {
+ case 0:
+ // Some kind of ACK?
+ break;
+ case 1:
+ send_ec_oem_command(0x59);
+ hotkey = recv_ec_oem_data();
+ mainboard_smi_hotkey(hotkey);
+ break;
+ default:
+ printk(BIOS_DEBUG, "EC SMI source: %02x\n", source);
+ }
+}
+
diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc
index c4fb74d..f2de43e 100644
--- a/src/mainboard/google/parrot/Makefile.inc
+++ b/src/mainboard/google/parrot/Makefile.inc
@@ -22,6 +22,4 @@ ramstage-y += ec.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
-
SRC_ROOT = $(src)/mainboard/google/parrot
diff --git a/src/mainboard/google/parrot/mainboard_smi.c b/src/mainboard/google/parrot/mainboard_smi.c
deleted file mode 100644
index 6f83fd8..0000000
--- a/src/mainboard/google/parrot/mainboard_smi.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/bd82x6x/nvs.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/me.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <cpu/intel/model_206ax/model_206ax.h>
-#include <elog.h>
-#include <ec/compal/ene932/ec.h>
-#include "ec.h"
-
-/* Power Management PCI Configuration Registers
- * Bus 0, Device 31, Function 0, Offset 0xB8
- * 00 = No Effect
- * 01 = SMI#
- * 10 = SCI
- * 11 = NMI
- */
-#define GPI_ROUT 0x8000F8B8
-#define GPI_IS_SMI 0x01
-#define GPI_IS_SCI 0x02
-
-static void set_lid_gpi_mode(u32 mode)
-{
- u32 reg32 = 0;
- u16 reg16 = 0;
-
- /* read the GPI register, clear the lid GPI's mode, write the new mode
- * and write out the register.
- */
- outl(GPI_ROUT, 0xcf8);
- reg32 = inl(0xcfc);
- reg32 &= ~(0x03 << (EC_LID_GPI * 2));
- reg32 |= (mode << (EC_LID_GPI * 2));
- outl(GPI_ROUT, 0xcf8);
- outl(reg32, 0xcfc);
-
- /* Set or Disable Lid GPE as SMI source in the ALT_GPI_SMI_EN register. */
- reg16 = inw(smm_get_pmbase() + ALT_GP_SMI_EN);
- if (mode == GPI_IS_SCI) {
- reg16 &= ~(1 << EC_LID_GPI);
- } else {
- reg16 |= (1 << EC_LID_GPI);
- }
- outw(reg16, smm_get_pmbase() + ALT_GP_SMI_EN);
-
- return;
-}
-
-int mainboard_io_trap_handler(int smif)
-{
- printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif);
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- smm_get_gnvs()->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1;
-}
-
-
-static u8 mainboard_smi_ec(void)
-{
- u8 src;
- u32 pm1_cnt;
- static int battery_critical_logged;
-
- ec_kbc_write_cmd(0x56);
- src = ec_kbc_read_ob();
- printk(BIOS_DEBUG, "mainboard_smi_ec src: %x\n", src);
-
- switch (src) {
- case EC_BATTERY_CRITICAL:
-#if CONFIG_ELOG_GSMI
- if (!battery_critical_logged)
- elog_add_event_byte(ELOG_TYPE_EC_EVENT,
- EC_EVENT_BATTERY_CRITICAL);
-#endif
- battery_critical_logged = 1;
- break;
- case EC_LID_CLOSE:
- printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-
-#if CONFIG_ELOG_GSMI
- elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
-#endif
- /* Go to S5 */
- pm1_cnt = inl(smm_get_pmbase() + PM1_CNT);
- pm1_cnt |= (0xf << 10);
- outl(pm1_cnt, smm_get_pmbase() + PM1_CNT);
- break;
- }
-
- return src;
-}
-
-void mainboard_smi_gpi(u16 gpi_sts)
-{
- u32 pm1_cnt;
-
- printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts);
- if (gpi_sts & (1 << EC_SMI_GPI)) {
- /* Process all pending events from EC */
- while (mainboard_smi_ec() != EC_NO_EVENT);
- }
- else if (gpi_sts & (1 << EC_LID_GPI)) {
- printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-
-#if CONFIG_ELOG_GSMI
- elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
-#endif
- /* Go to S5 */
- pm1_cnt = inl(smm_get_pmbase() + PM1_CNT);
- pm1_cnt |= (0xf << 10);
- outl(pm1_cnt, smm_get_pmbase() + PM1_CNT);
- }
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
- printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ);
- /* Disable SCI and SMI events */
-
-
- /* Clear pending events that may trigger immediate wake */
-
-
- /* Enable wake events */
-
-
- /* Tell the EC to Disable USB power */
- if (smm_get_gnvs()->s3u0 == 0 && smm_get_gnvs()->s3u1 == 0) {
- ec_kbc_write_cmd(0x45);
- ec_kbc_write_ib(0xF2);
- }
-}
-
-#define APMC_FINALIZE 0xcb
-#define APMC_ACPI_EN 0xe1
-#define APMC_ACPI_DIS 0x1e
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
- printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc);
- switch (apmc) {
- case APMC_FINALIZE:
- printk(BIOS_DEBUG, "APMC: FINALIZE\n");
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "APMC#: Already finalized\n");
- return 0;
- }
-
- intel_me_finalize_smm();
- intel_pch_finalize_smm();
- intel_sandybridge_finalize_smm();
- intel_model_206ax_finalize_smm();
-
- mainboard_finalized = 1;
- break;
- case APMC_ACPI_EN:
- printk(BIOS_DEBUG, "APMC: ACPI_EN\n");
- /* Clear all pending events */
- /* EC cmd:59 data:E8 */
- ec_kbc_write_cmd(0x59);
- ec_kbc_write_ib(0xE8);
-
- /* Set LID GPI to generate SCIs */
- set_lid_gpi_mode(GPI_IS_SCI);
-
- break;
- case APMC_ACPI_DIS:
- printk(BIOS_DEBUG, "APMC: ACPI_DIS\n");
- /* Clear all pending events */
- /* EC cmd:59 data:e9 */
- ec_kbc_write_cmd(0x59);
- ec_kbc_write_ib(0xE9);
-
- /* Set LID GPI to generate SMIs */
- set_lid_gpi_mode(GPI_IS_SMI);
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c
new file mode 100644
index 0000000..6f83fd8
--- /dev/null
+++ b/src/mainboard/google/parrot/smihandler.c
@@ -0,0 +1,217 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <elog.h>
+#include <ec/compal/ene932/ec.h>
+#include "ec.h"
+
+/* Power Management PCI Configuration Registers
+ * Bus 0, Device 31, Function 0, Offset 0xB8
+ * 00 = No Effect
+ * 01 = SMI#
+ * 10 = SCI
+ * 11 = NMI
+ */
+#define GPI_ROUT 0x8000F8B8
+#define GPI_IS_SMI 0x01
+#define GPI_IS_SCI 0x02
+
+static void set_lid_gpi_mode(u32 mode)
+{
+ u32 reg32 = 0;
+ u16 reg16 = 0;
+
+ /* read the GPI register, clear the lid GPI's mode, write the new mode
+ * and write out the register.
+ */
+ outl(GPI_ROUT, 0xcf8);
+ reg32 = inl(0xcfc);
+ reg32 &= ~(0x03 << (EC_LID_GPI * 2));
+ reg32 |= (mode << (EC_LID_GPI * 2));
+ outl(GPI_ROUT, 0xcf8);
+ outl(reg32, 0xcfc);
+
+ /* Set or Disable Lid GPE as SMI source in the ALT_GPI_SMI_EN register. */
+ reg16 = inw(smm_get_pmbase() + ALT_GP_SMI_EN);
+ if (mode == GPI_IS_SCI) {
+ reg16 &= ~(1 << EC_LID_GPI);
+ } else {
+ reg16 |= (1 << EC_LID_GPI);
+ }
+ outw(reg16, smm_get_pmbase() + ALT_GP_SMI_EN);
+
+ return;
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif);
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ smm_get_gnvs()->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+
+static u8 mainboard_smi_ec(void)
+{
+ u8 src;
+ u32 pm1_cnt;
+ static int battery_critical_logged;
+
+ ec_kbc_write_cmd(0x56);
+ src = ec_kbc_read_ob();
+ printk(BIOS_DEBUG, "mainboard_smi_ec src: %x\n", src);
+
+ switch (src) {
+ case EC_BATTERY_CRITICAL:
+#if CONFIG_ELOG_GSMI
+ if (!battery_critical_logged)
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT,
+ EC_EVENT_BATTERY_CRITICAL);
+#endif
+ battery_critical_logged = 1;
+ break;
+ case EC_LID_CLOSE:
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+#if CONFIG_ELOG_GSMI
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
+#endif
+ /* Go to S5 */
+ pm1_cnt = inl(smm_get_pmbase() + PM1_CNT);
+ pm1_cnt |= (0xf << 10);
+ outl(pm1_cnt, smm_get_pmbase() + PM1_CNT);
+ break;
+ }
+
+ return src;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+ u32 pm1_cnt;
+
+ printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts);
+ if (gpi_sts & (1 << EC_SMI_GPI)) {
+ /* Process all pending events from EC */
+ while (mainboard_smi_ec() != EC_NO_EVENT);
+ }
+ else if (gpi_sts & (1 << EC_LID_GPI)) {
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+#if CONFIG_ELOG_GSMI
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
+#endif
+ /* Go to S5 */
+ pm1_cnt = inl(smm_get_pmbase() + PM1_CNT);
+ pm1_cnt |= (0xf << 10);
+ outl(pm1_cnt, smm_get_pmbase() + PM1_CNT);
+ }
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ);
+ /* Disable SCI and SMI events */
+
+
+ /* Clear pending events that may trigger immediate wake */
+
+
+ /* Enable wake events */
+
+
+ /* Tell the EC to Disable USB power */
+ if (smm_get_gnvs()->s3u0 == 0 && smm_get_gnvs()->s3u1 == 0) {
+ ec_kbc_write_cmd(0x45);
+ ec_kbc_write_ib(0xF2);
+ }
+}
+
+#define APMC_FINALIZE 0xcb
+#define APMC_ACPI_EN 0xe1
+#define APMC_ACPI_DIS 0x1e
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc);
+ switch (apmc) {
+ case APMC_FINALIZE:
+ printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+ case APMC_ACPI_EN:
+ printk(BIOS_DEBUG, "APMC: ACPI_EN\n");
+ /* Clear all pending events */
+ /* EC cmd:59 data:E8 */
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE8);
+
+ /* Set LID GPI to generate SCIs */
+ set_lid_gpi_mode(GPI_IS_SCI);
+
+ break;
+ case APMC_ACPI_DIS:
+ printk(BIOS_DEBUG, "APMC: ACPI_DIS\n");
+ /* Clear all pending events */
+ /* EC cmd:59 data:e9 */
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE9);
+
+ /* Set LID GPI to generate SMIs */
+ set_lid_gpi_mode(GPI_IS_SMI);
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/ibase/mb899/mainboard_smi.c b/src/mainboard/ibase/mb899/mainboard_smi.c
deleted file mode 100644
index 3e3bee7..0000000
--- a/src/mainboard/ibase/mb899/mainboard_smi.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/nvs.h"
-
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern global_nvs_t *gnvs;
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- gnvs->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1;
-}
-
-
diff --git a/src/mainboard/ibase/mb899/smihandler.c b/src/mainboard/ibase/mb899/smihandler.c
new file mode 100644
index 0000000..3e3bee7
--- /dev/null
+++ b/src/mainboard/ibase/mb899/smihandler.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+
diff --git a/src/mainboard/intel/d945gclf/mainboard_smi.c b/src/mainboard/intel/d945gclf/mainboard_smi.c
deleted file mode 100644
index dbd1a81..0000000
--- a/src/mainboard/intel/d945gclf/mainboard_smi.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/nvs.h"
-
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern global_nvs_t *gnvs;
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- gnvs->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1;
-}
-
-
diff --git a/src/mainboard/intel/d945gclf/smihandler.c b/src/mainboard/intel/d945gclf/smihandler.c
new file mode 100644
index 0000000..dbd1a81
--- /dev/null
+++ b/src/mainboard/intel/d945gclf/smihandler.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+
diff --git a/src/mainboard/intel/emeraldlake2/mainboard_smi.c b/src/mainboard/intel/emeraldlake2/mainboard_smi.c
deleted file mode 100644
index 03c505b..0000000
--- a/src/mainboard/intel/emeraldlake2/mainboard_smi.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/bd82x6x/nvs.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/me.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <cpu/intel/model_206ax/model_206ax.h>
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- smm_get_gnvs()->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1;
-}
-
-/*
- * Change LED_POWER# (SIO GPIO 45) state based on sleep type.
- * The IO address is hardcoded as we don't have device path in SMM.
- */
-#define SIO_GPIO_BASE_SET4 (0x730 + 3)
-#define SIO_GPIO_BLINK_GPIO45 0x25
-void mainboard_smi_sleep(u8 slp_typ)
-{
- u8 reg8;
-
- switch (slp_typ) {
- case SLP_TYP_S3:
- case SLP_TYP_S4:
- break;
-
- case SLP_TYP_S5:
- /* Turn off LED */
- reg8 = inb(SIO_GPIO_BASE_SET4);
- reg8 |= (1 << 5);
- outb(reg8, SIO_GPIO_BASE_SET4);
- break;
- }
-}
-
-#define APMC_FINALIZE 0xcb
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
- switch (apmc) {
- case APMC_FINALIZE:
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "SMI#: Already finalized\n");
- return 0;
- }
-
- intel_me_finalize_smm();
- intel_pch_finalize_smm();
- intel_sandybridge_finalize_smm();
- intel_model_206ax_finalize_smm();
-
- mainboard_finalized = 1;
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c
new file mode 100644
index 0000000..03c505b
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/smihandler.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ smm_get_gnvs()->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+/*
+ * Change LED_POWER# (SIO GPIO 45) state based on sleep type.
+ * The IO address is hardcoded as we don't have device path in SMM.
+ */
+#define SIO_GPIO_BASE_SET4 (0x730 + 3)
+#define SIO_GPIO_BLINK_GPIO45 0x25
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ u8 reg8;
+
+ switch (slp_typ) {
+ case SLP_TYP_S3:
+ case SLP_TYP_S4:
+ break;
+
+ case SLP_TYP_S5:
+ /* Turn off LED */
+ reg8 = inb(SIO_GPIO_BASE_SET4);
+ reg8 |= (1 << 5);
+ outb(reg8, SIO_GPIO_BASE_SET4);
+ break;
+ }
+}
+
+#define APMC_FINALIZE 0xcb
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ switch (apmc) {
+ case APMC_FINALIZE:
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard_smi.c b/src/mainboard/iwave/iWRainbowG6/mainboard_smi.c
deleted file mode 100644
index fc4defb..0000000
--- a/src/mainboard/iwave/iWRainbowG6/mainboard_smi.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/nvs.h" // FIXME: this should point to its own copy of nvs
-
-/*
- * The southbridge SMI handler checks whether gnvs has a valid pointer before
- * calling the trap handler.
- */
-// extern global_nvs_t *gnvs;
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- // gnvs->smif = 0;
- break;
- default:
- return 0;
- }
-
- /*
- * On success, the IO Trap Handler returns 0.
- * On failure, the IO Trap Handler returns a value != 0.
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- // gnvs->smif = 0;
- return 1;
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/smihandler.c b/src/mainboard/iwave/iWRainbowG6/smihandler.c
new file mode 100644
index 0000000..fc4defb
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/smihandler.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h" // FIXME: this should point to its own copy of nvs
+
+/*
+ * The southbridge SMI handler checks whether gnvs has a valid pointer before
+ * calling the trap handler.
+ */
+// extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ // gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /*
+ * On success, the IO Trap Handler returns 0.
+ * On failure, the IO Trap Handler returns a value != 0.
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ // gnvs->smif = 0;
+ return 1;
+}
diff --git a/src/mainboard/kontron/986lcd-m/mainboard_smi.c b/src/mainboard/kontron/986lcd-m/mainboard_smi.c
deleted file mode 100644
index 3e3bee7..0000000
--- a/src/mainboard/kontron/986lcd-m/mainboard_smi.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/nvs.h"
-
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern global_nvs_t *gnvs;
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- gnvs->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1;
-}
-
-
diff --git a/src/mainboard/kontron/986lcd-m/smihandler.c b/src/mainboard/kontron/986lcd-m/smihandler.c
new file mode 100644
index 0000000..3e3bee7
--- /dev/null
+++ b/src/mainboard/kontron/986lcd-m/smihandler.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+
diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c b/src/mainboard/lenovo/t60/mainboard_smi.c
deleted file mode 100644
index 6ea5037..0000000
--- a/src/mainboard/lenovo/t60/mainboard_smi.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/nvs.h"
-#include "southbridge/intel/i82801gx/i82801gx.h"
-#include <ec/acpi/ec.h>
-#include "dock.h"
-#include "smi.h"
-
-#define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern global_nvs_t *gnvs;
-
-static void mainboard_smm_init(void)
-{
- printk(BIOS_DEBUG, "initializing SMI\n");
- /* Enable 0x1600/0x1600 register pair */
- ec_set_bit(0x00, 0x05);
-}
-
-static void mainboard_smi_brightness_down(void)
-{
- u8 *bar;
- if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
- printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
- *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0;
- if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10)
- *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10;
- }
-}
-
-static void mainboard_smi_brightness_up(void)
-{
- u8 *bar;
- if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
- printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL));
- *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;
- if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)
- *(bar+LVTMA_BL_MOD_LEVEL) += 0x10;
- }
-}
-
-int mainboard_io_trap_handler(int smif)
-{
- static int smm_initialized;
-
- if (!smm_initialized) {
- mainboard_smm_init();
- smm_initialized = 1;
- }
-
- switch (smif) {
- case SMI_DOCK_CONNECT:
- /* If there's an legacy I/O module present, we're not
- * allowed to connect the Docking LPC Bus, as both Super I/O
- * chips are using 0x2e as base address.
- */
- if (legacy_io_present())
- break;
-
- if (!dock_connect()) {
- /* set dock LED to indicate status */
- ec_write(0x0c, 0x08);
- ec_write(0x0c, 0x89);
- } else {
- /* blink dock LED to indicate failure */
- ec_write(0x0c, 0xc8);
- ec_write(0x0c, 0x09);
- }
- break;
-
- case SMI_DOCK_DISCONNECT:
- dock_disconnect();
- ec_write(0x0c, 0x09);
- ec_write(0x0c, 0x08);
- break;
-
- case SMI_BRIGHTNESS_UP:
- mainboard_smi_brightness_up();
- break;
-
- case SMI_BRIGHTNESS_DOWN:
- mainboard_smi_brightness_down();
- break;
-
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 1
- * On failure, the IO Trap Handler returns a value != 1 */
- return 1;
-}
-
-static void mainboard_smi_handle_ec_sci(void)
-{
- u8 status = inb(EC_SC);
- u8 event;
-
- if (!(status & EC_SCI_EVT))
- return;
-
- event = ec_query();
- printk(BIOS_DEBUG, "EC event %02x\n", event);
-
- switch(event) {
- /* brightness up */
- case 0x14:
- mainboard_smi_brightness_up();
- break;
- /* brightness down */
- case 0x15:
- mainboard_smi_brightness_down();
- break;
- /* Fn-F9 Key */
- case 0x18:
- /* power loss */
- case 0x27:
- /* undock event */
- case 0x50:
- mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
- break;
- /* dock event */
- case 0x37:
- mainboard_io_trap_handler(SMI_DOCK_CONNECT);
- break;
- default:
- break;
- }
-}
-
-void mainboard_smi_gpi(u16 gpi)
-{
- if (gpi & (1 << 12))
- mainboard_smi_handle_ec_sci();
-}
-
-int mainboard_smi_apmc(u8 data)
-{
- u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
- u8 tmp;
-
- printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
-
- if (!pmbase)
- return 0;
-
- switch(data) {
- case APM_CNT_ACPI_ENABLE:
- /* use 0x1600/0x1604 to prevent races with userspace */
- ec_set_ports(0x1604, 0x1600);
- /* route H8SCI to SCI */
- outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x02;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
- break;
- case APM_CNT_ACPI_DISABLE:
- /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
- provide a EC query function */
- ec_set_ports(0x66, 0x62);
- /* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
- break;
- default:
- break;
- }
- return 0;
-}
-
diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c
new file mode 100644
index 0000000..6ea5037
--- /dev/null
+++ b/src/mainboard/lenovo/t60/smihandler.c
@@ -0,0 +1,199 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <ec/acpi/ec.h>
+#include "dock.h"
+#include "smi.h"
+
+#define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 *bar;
+ if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
+ printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
+ *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0;
+ if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10)
+ *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10;
+ }
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 *bar;
+ if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
+ printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL));
+ *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;
+ if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)
+ *(bar+LVTMA_BL_MOD_LEVEL) += 0x10;
+ }
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ case SMI_DOCK_CONNECT:
+ /* If there's an legacy I/O module present, we're not
+ * allowed to connect the Docking LPC Bus, as both Super I/O
+ * chips are using 0x2e as base address.
+ */
+ if (legacy_io_present())
+ break;
+
+ if (!dock_connect()) {
+ /* set dock LED to indicate status */
+ ec_write(0x0c, 0x08);
+ ec_write(0x0c, 0x89);
+ } else {
+ /* blink dock LED to indicate failure */
+ ec_write(0x0c, 0xc8);
+ ec_write(0x0c, 0x09);
+ }
+ break;
+
+ case SMI_DOCK_DISCONNECT:
+ dock_disconnect();
+ ec_write(0x0c, 0x09);
+ ec_write(0x0c, 0x08);
+ break;
+
+ case SMI_BRIGHTNESS_UP:
+ mainboard_smi_brightness_up();
+ break;
+
+ case SMI_BRIGHTNESS_DOWN:
+ mainboard_smi_brightness_down();
+ break;
+
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch(event) {
+ /* brightness up */
+ case 0x14:
+ mainboard_smi_brightness_up();
+ break;
+ /* brightness down */
+ case 0x15:
+ mainboard_smi_brightness_down();
+ break;
+ /* Fn-F9 Key */
+ case 0x18:
+ /* power loss */
+ case 0x27:
+ /* undock event */
+ case 0x50:
+ mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
+ break;
+ /* dock event */
+ case 0x37:
+ mainboard_io_trap_handler(SMI_DOCK_CONNECT);
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u16 gpi)
+{
+ if (gpi & (1 << 12))
+ mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
+
+ if (!pmbase)
+ return 0;
+
+ switch(data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route H8SCI to SCI */
+ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route H8SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
diff --git a/src/mainboard/lenovo/x60/mainboard_smi.c b/src/mainboard/lenovo/x60/mainboard_smi.c
deleted file mode 100644
index c0d8440..0000000
--- a/src/mainboard/lenovo/x60/mainboard_smi.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/nvs.h"
-#include "southbridge/intel/i82801gx/i82801gx.h"
-#include <ec/acpi/ec.h>
-#include <pc80/mc146818rtc.h>
-#include <ec/lenovo/h8/h8.h>
-#include <delay.h>
-#include "dock.h"
-#include "smi.h"
-
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern global_nvs_t *gnvs;
-
-static void mainboard_smm_init(void)
-{
- printk(BIOS_DEBUG, "initializing SMI\n");
- /* Enable 0x1600/0x1600 register pair */
- ec_set_bit(0x00, 0x05);
-}
-
-static void mainboard_smi_save_cmos(void)
-{
- u8 val;
- u8 tmp70, tmp72;
-
- tmp70 = inb(0x70);
- tmp72 = inb(0x72);
-
- val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);
- set_option("tft_brightness", &val);
- val = ec_read(H8_VOLUME_CONTROL);
- set_option("volume", &val);
-
- outb(tmp70, 0x70);
- outb(tmp72, 0x72);
-}
-
-int mainboard_io_trap_handler(int smif)
-{
- static int smm_initialized;
-
- if (!smm_initialized) {
- mainboard_smm_init();
- smm_initialized = 1;
- }
-
- switch (smif) {
- case SMI_DOCK_CONNECT:
- ec_clr_bit(0x03, 2);
- udelay(250000);
- if (!dock_connect()) {
- ec_set_bit(0x03, 2);
- /* set dock LED to indicate status */
- ec_write(0x0c, 0x09);
- ec_write(0x0c, 0x88);
- } else {
- /* blink dock LED to indicate failure */
- ec_write(0x0c, 0x08);
- ec_write(0x0c, 0xc9);
- }
- break;
-
- case SMI_DOCK_DISCONNECT:
- ec_clr_bit(0x03, 2);
- dock_disconnect();
- break;
-
- case SMI_SAVE_CMOS:
- mainboard_smi_save_cmos();
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 1
- * On failure, the IO Trap Handler returns a value != 1 */
- return 1;
-}
-
-static void mainboard_smi_brightness_up(void)
-{
- u8 value;
-
- if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
- pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
-}
-
-static void mainboard_smi_brightness_down(void)
-{
- u8 value;
-
- if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
- pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value - 0x10) & 0xf0);
-}
-
-static void mainboard_smi_handle_ec_sci(void)
-{
- u8 status = inb(EC_SC);
- u8 event;
-
- if (!(status & EC_SCI_EVT))
- return;
-
- event = ec_query();
- printk(BIOS_DEBUG, "EC event %02x\n", event);
-
- switch(event) {
- /* brightness up */
- case 0x14:
- mainboard_smi_brightness_up();
- mainboard_smi_save_cmos();
- break;
- /* brightness down */
- case 0x15:
- mainboard_smi_brightness_down();
- mainboard_smi_save_cmos();
- break;
- /* Fn-F9 key */
- case 0x18:
- /* Power loss */
- case 0x27:
- /* Undock Key */
- case 0x50:
- mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
- break;
- /* Dock Event */
- case 0x37:
- case 0x58:
- mainboard_io_trap_handler(SMI_DOCK_CONNECT);
- break;
- default:
- break;
- }
-}
-
-void mainboard_smi_gpi(u16 gpi)
-{
- if (gpi & (1 << 12))
- mainboard_smi_handle_ec_sci();
-}
-
-int mainboard_smi_apmc(u8 data)
-{
- u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
- u8 tmp;
-
- printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
-
- if (!pmbase)
- return 0;
-
- switch(data) {
- case APM_CNT_ACPI_ENABLE:
- /* use 0x1600/0x1604 to prevent races with userspace */
- ec_set_ports(0x1604, 0x1600);
- /* route H8SCI to SCI */
- outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x02;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
- /* discard all events, and enable attention */
- ec_write(0x80, 0x01);
- break;
- case APM_CNT_ACPI_DISABLE:
- /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
- provide a EC query function */
- ec_set_ports(0x66, 0x62);
- /* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
- /* discard all events, and enable attention */
- ec_write(0x80, 0x01);
- break;
- default:
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c
new file mode 100644
index 0000000..c0d8440
--- /dev/null
+++ b/src/mainboard/lenovo/x60/smihandler.c
@@ -0,0 +1,208 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include "dock.h"
+#include "smi.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+static void mainboard_smi_save_cmos(void)
+{
+ u8 val;
+ u8 tmp70, tmp72;
+
+ tmp70 = inb(0x70);
+ tmp72 = inb(0x72);
+
+ val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);
+ set_option("tft_brightness", &val);
+ val = ec_read(H8_VOLUME_CONTROL);
+ set_option("volume", &val);
+
+ outb(tmp70, 0x70);
+ outb(tmp72, 0x72);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ case SMI_DOCK_CONNECT:
+ ec_clr_bit(0x03, 2);
+ udelay(250000);
+ if (!dock_connect()) {
+ ec_set_bit(0x03, 2);
+ /* set dock LED to indicate status */
+ ec_write(0x0c, 0x09);
+ ec_write(0x0c, 0x88);
+ } else {
+ /* blink dock LED to indicate failure */
+ ec_write(0x0c, 0x08);
+ ec_write(0x0c, 0xc9);
+ }
+ break;
+
+ case SMI_DOCK_DISCONNECT:
+ ec_clr_bit(0x03, 2);
+ dock_disconnect();
+ break;
+
+ case SMI_SAVE_CMOS:
+ mainboard_smi_save_cmos();
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch(event) {
+ /* brightness up */
+ case 0x14:
+ mainboard_smi_brightness_up();
+ mainboard_smi_save_cmos();
+ break;
+ /* brightness down */
+ case 0x15:
+ mainboard_smi_brightness_down();
+ mainboard_smi_save_cmos();
+ break;
+ /* Fn-F9 key */
+ case 0x18:
+ /* Power loss */
+ case 0x27:
+ /* Undock Key */
+ case 0x50:
+ mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
+ break;
+ /* Dock Event */
+ case 0x37:
+ case 0x58:
+ mainboard_io_trap_handler(SMI_DOCK_CONNECT);
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u16 gpi)
+{
+ if (gpi & (1 << 12))
+ mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
+
+ if (!pmbase)
+ return 0;
+
+ switch(data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route H8SCI to SCI */
+ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route H8SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/rca/rm4100/mainboard_smi.c b/src/mainboard/rca/rm4100/mainboard_smi.c
deleted file mode 100644
index 8cfefae..0000000
--- a/src/mainboard/rca/rm4100/mainboard_smi.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-
-int mainboard_io_trap_handler(int smif)
-{
- printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
- return 1;
-}
diff --git a/src/mainboard/rca/rm4100/smihandler.c b/src/mainboard/rca/rm4100/smihandler.c
new file mode 100644
index 0000000..8cfefae
--- /dev/null
+++ b/src/mainboard/rca/rm4100/smihandler.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+
+int mainboard_io_trap_handler(int smif)
+{
+ printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
+ return 1;
+}
diff --git a/src/mainboard/roda/rk886ex/mainboard_smi.c b/src/mainboard/roda/rk886ex/mainboard_smi.c
deleted file mode 100644
index 6736ace..0000000
--- a/src/mainboard/roda/rk886ex/mainboard_smi.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/nvs.h"
-
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern global_nvs_t *gnvs;
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- //gnvs->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1;
-}
-
diff --git a/src/mainboard/roda/rk886ex/smihandler.c b/src/mainboard/roda/rk886ex/smihandler.c
new file mode 100644
index 0000000..6736ace
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/smihandler.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ //gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc
index 9a2f0b1..1a6cb02 100644
--- a/src/mainboard/roda/rk9/Makefile.inc
+++ b/src/mainboard/roda/rk9/Makefile.inc
@@ -18,4 +18,3 @@
##
ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/roda/rk9/mainboard_smi.c b/src/mainboard/roda/rk9/mainboard_smi.c
deleted file mode 100644
index 8a87cd9..0000000
--- a/src/mainboard/roda/rk9/mainboard_smi.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/i82801ix/nvs.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
-#include <ec/acpi/ec.h>
-
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern global_nvs_t *gnvs;
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- gnvs->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1;
-}
-
-void mainboard_smi_gpi(u16 gpi_sts)
-{
- if (gpi_sts & (1 << 1)) {
- printk(BIOS_DEBUG, "EC/SMI\n");
- /* TODO */
- }
-}
-
-int mainboard_smi_apmc(u8 apmc)
-{
- switch (apmc) {
- case APM_CNT_ACPI_ENABLE:
- send_ec_command(0x05); /* Set_SMI_Disable */
- send_ec_command(0xaa); /* Set_ACPI_Enable */
- break;
-
- case APM_CNT_ACPI_DISABLE:
- send_ec_command(0x04); /* Set_SMI_Enable */
- send_ec_command(0xab); /* Set_ACPI_Disable */
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/roda/rk9/smihandler.c b/src/mainboard/roda/rk9/smihandler.c
new file mode 100644
index 0000000..8a87cd9
--- /dev/null
+++ b/src/mainboard/roda/rk9/smihandler.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/i82801ix/nvs.h>
+#include <southbridge/intel/i82801ix/i82801ix.h>
+#include <ec/acpi/ec.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+ if (gpi_sts & (1 << 1)) {
+ printk(BIOS_DEBUG, "EC/SMI\n");
+ /* TODO */
+ }
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ switch (apmc) {
+ case APM_CNT_ACPI_ENABLE:
+ send_ec_command(0x05); /* Set_SMI_Disable */
+ send_ec_command(0xaa); /* Set_ACPI_Enable */
+ break;
+
+ case APM_CNT_ACPI_DISABLE:
+ send_ec_command(0x04); /* Set_SMI_Enable */
+ send_ec_command(0xab); /* Set_ACPI_Disable */
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/samsung/lumpy/mainboard_smi.c b/src/mainboard/samsung/lumpy/mainboard_smi.c
deleted file mode 100644
index 4e73a57..0000000
--- a/src/mainboard/samsung/lumpy/mainboard_smi.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/bd82x6x/nvs.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/me.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <cpu/intel/model_206ax/model_206ax.h>
-#include <ec/smsc/mec1308/ec.h>
-#include "ec.h"
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- smm_get_gnvs()->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1;
-}
-
-static u8 mainboard_smi_ec(void)
-{
- u8 cmd;
- u32 pm1_cnt;
-
- cmd = read_ec_command_byte(EC_GET_SMI_CAUSE);
-
- switch (cmd) {
- case EC_LID_CLOSE:
- printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-
- /* Go to S5 */
- pm1_cnt = inl(smm_get_pmbase() + PM1_CNT);
- pm1_cnt |= (0xf << 10);
- outl(pm1_cnt, smm_get_pmbase() + PM1_CNT);
- break;
- }
-
- return cmd;
-}
-
-void mainboard_smi_gpi(u16 gpi_sts)
-{
- if (gpi_sts & (1 << EC_SMI_GPI)) {
- /* Process all pending EC requests */
- ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1);
- while (mainboard_smi_ec() != 0xff);
-
- /* The EC may keep asserting SMI# for some
- * period unless we kick it here.
- */
- send_ec_command(EC_SMI_DISABLE);
- send_ec_command(EC_SMI_ENABLE);
- }
-}
-
-#define APMC_FINALIZE 0xcb
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
- ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1);
-
- switch (apmc) {
- case 0xe1: /* ACPI ENABLE */
- send_ec_command(EC_SMI_DISABLE);
- send_ec_command(EC_ACPI_ENABLE);
- break;
-
- case 0x1e: /* ACPI DISABLE */
- send_ec_command(EC_SMI_ENABLE);
- send_ec_command(EC_ACPI_DISABLE);
- break;
-
- case APMC_FINALIZE:
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "SMI#: Already finalized\n");
- return 0;
- }
-
- intel_me_finalize_smm();
- intel_pch_finalize_smm();
- intel_sandybridge_finalize_smm();
- intel_model_206ax_finalize_smm();
-
- mainboard_finalized = 1;
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c
new file mode 100644
index 0000000..4e73a57
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/smihandler.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <ec/smsc/mec1308/ec.h>
+#include "ec.h"
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ smm_get_gnvs()->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+static u8 mainboard_smi_ec(void)
+{
+ u8 cmd;
+ u32 pm1_cnt;
+
+ cmd = read_ec_command_byte(EC_GET_SMI_CAUSE);
+
+ switch (cmd) {
+ case EC_LID_CLOSE:
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+ /* Go to S5 */
+ pm1_cnt = inl(smm_get_pmbase() + PM1_CNT);
+ pm1_cnt |= (0xf << 10);
+ outl(pm1_cnt, smm_get_pmbase() + PM1_CNT);
+ break;
+ }
+
+ return cmd;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+ if (gpi_sts & (1 << EC_SMI_GPI)) {
+ /* Process all pending EC requests */
+ ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1);
+ while (mainboard_smi_ec() != 0xff);
+
+ /* The EC may keep asserting SMI# for some
+ * period unless we kick it here.
+ */
+ send_ec_command(EC_SMI_DISABLE);
+ send_ec_command(EC_SMI_ENABLE);
+ }
+}
+
+#define APMC_FINALIZE 0xcb
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1);
+
+ switch (apmc) {
+ case 0xe1: /* ACPI ENABLE */
+ send_ec_command(EC_SMI_DISABLE);
+ send_ec_command(EC_ACPI_ENABLE);
+ break;
+
+ case 0x1e: /* ACPI DISABLE */
+ send_ec_command(EC_SMI_ENABLE);
+ send_ec_command(EC_ACPI_DISABLE);
+ break;
+
+ case APMC_FINALIZE:
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/samsung/stumpy/mainboard_smi.c b/src/mainboard/samsung/stumpy/mainboard_smi.c
deleted file mode 100644
index 660bb31..0000000
--- a/src/mainboard/samsung/stumpy/mainboard_smi.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/bd82x6x/nvs.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/me.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <cpu/intel/model_206ax/model_206ax.h>
-
-/* Include romstage serial for SIO helper functions */
-#include <superio/ite/it8772f/early_serial.c>
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- smm_get_gnvs()->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1;
-}
-
-/*
- * Change LED_POWER# (SIO GPIO 45) state based on sleep type.
- * The IO address is hardcoded as we don't have device path in SMM.
- */
-#define SIO_GPIO_BASE_SET4 (0x730 + 3)
-#define SIO_GPIO_BLINK_GPIO45 0x25
-void mainboard_smi_sleep(u8 slp_typ)
-{
- u8 reg8;
-
- switch (slp_typ) {
- case SLP_TYP_S3:
- case SLP_TYP_S4:
- /* Blink LED */
- it8772f_enter_conf();
- it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
- /* Enable blink pin map */
- it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_PINMAP,
- SIO_GPIO_BLINK_GPIO45);
- /* Enable 4HZ blink */
- it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02);
- /* Set GPIO to alternate function */
- reg8 = it8772f_sio_read(GPIO_REG_ENABLE(3));
- reg8 &= ~(1 << 5);
- it8772f_sio_write(GPIO_REG_ENABLE(3), reg8);
- it8772f_exit_conf();
- break;
-
- case SLP_TYP_S5:
- /* Turn off LED */
- reg8 = inb(SIO_GPIO_BASE_SET4);
- reg8 |= (1 << 5);
- outb(reg8, SIO_GPIO_BASE_SET4);
- break;
- }
-}
-
-#define APMC_FINALIZE 0xcb
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
- switch (apmc) {
- case APMC_FINALIZE:
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "SMI#: Already finalized\n");
- return 0;
- }
-
- intel_me_finalize_smm();
- intel_pch_finalize_smm();
- intel_sandybridge_finalize_smm();
- intel_model_206ax_finalize_smm();
-
- mainboard_finalized = 1;
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c
new file mode 100644
index 0000000..660bb31
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/smihandler.c
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* Include romstage serial for SIO helper functions */
+#include <superio/ite/it8772f/early_serial.c>
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ smm_get_gnvs()->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+/*
+ * Change LED_POWER# (SIO GPIO 45) state based on sleep type.
+ * The IO address is hardcoded as we don't have device path in SMM.
+ */
+#define SIO_GPIO_BASE_SET4 (0x730 + 3)
+#define SIO_GPIO_BLINK_GPIO45 0x25
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ u8 reg8;
+
+ switch (slp_typ) {
+ case SLP_TYP_S3:
+ case SLP_TYP_S4:
+ /* Blink LED */
+ it8772f_enter_conf();
+ it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+ /* Enable blink pin map */
+ it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_PINMAP,
+ SIO_GPIO_BLINK_GPIO45);
+ /* Enable 4HZ blink */
+ it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02);
+ /* Set GPIO to alternate function */
+ reg8 = it8772f_sio_read(GPIO_REG_ENABLE(3));
+ reg8 &= ~(1 << 5);
+ it8772f_sio_write(GPIO_REG_ENABLE(3), reg8);
+ it8772f_exit_conf();
+ break;
+
+ case SLP_TYP_S5:
+ /* Turn off LED */
+ reg8 = inb(SIO_GPIO_BASE_SET4);
+ reg8 |= (1 << 5);
+ outb(reg8, SIO_GPIO_BASE_SET4);
+ break;
+ }
+}
+
+#define APMC_FINALIZE 0xcb
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ switch (apmc) {
+ case APMC_FINALIZE:
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/thomson/ip1000/mainboard_smi.c b/src/mainboard/thomson/ip1000/mainboard_smi.c
deleted file mode 100644
index 8cfefae..0000000
--- a/src/mainboard/thomson/ip1000/mainboard_smi.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-
-int mainboard_io_trap_handler(int smif)
-{
- printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
- return 1;
-}
diff --git a/src/mainboard/thomson/ip1000/smihandler.c b/src/mainboard/thomson/ip1000/smihandler.c
new file mode 100644
index 0000000..8cfefae
--- /dev/null
+++ b/src/mainboard/thomson/ip1000/smihandler.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+
+int mainboard_io_trap_handler(int smif)
+{
+ printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
+ return 1;
+}
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